Module Definition
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Module : edn
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.94 95.94

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_edn1 93.38 93.38
tb.dut.top_earlgrey.u_edn0 95.85 95.85


Module Instance : tb.dut.top_earlgrey.u_edn1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.38 93.38


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.38 93.38


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.77 90.32 90.98 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_edn0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.85 95.85


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.85 95.85


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.77 90.32 90.98 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : edn
TotalCoveredPercent
Totals 78 63 80.77
Total Bits 1206 1157 95.94
Total Bits 0->1 603 580 96.19
Total Bits 1->0 603 577 95.69

Ports 78 63 80.77
Port Bits 1206 1157 95.94
Port Bits 0->1 603 580 96.19
Port Bits 1->0 603 577 95.69

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T30,T4 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T82,T116,T123 Yes T82,T116,T123 INPUT
tl_i.a_user.cmd_intg[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[1] No No No INPUT
tl_i.a_user.cmd_intg[6:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T82,T116,T123 Yes T82,T116,T123 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[6:2] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[1:0] Yes Yes *T65,*T66,*T1 Yes T65,T66,T1 INPUT
tl_i.a_source[5:2] No No No INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[0] No No No INPUT
tl_i.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[1:0] No No No INPUT
tl_i.a_opcode[2] Yes Yes T82,T116,T123 Yes T82,T116,T123 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T82,T116,T123 Yes T82,T116,T123 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T2,T30,T4 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes *T2,*T30,*T4 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T2,T30,T4 Yes T1,T2,T3 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[1:0] Yes Yes *T65,*T66,*T2 Yes T65,T66,T1 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T2,T30,T4 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T82,*T116,*T123 Yes T82,T116,T123 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_i[0].edn_req Yes Yes T43,T116,T117 Yes T43,T116,T117 INPUT
edn_i[1].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[2].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[3].edn_req Yes Yes T116,T130,T323 Yes T116,T130,T323 INPUT
edn_i[4].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[5].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[6].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[7].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T43,T116,T117 Yes T43,T116,T117 OUTPUT
edn_o[0].edn_fips Yes Yes T123,T125,T219 Yes T116,T123,T124 OUTPUT
edn_o[0].edn_ack Yes Yes T43,T116,T117 Yes T43,T116,T117 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[1].edn_fips No No Yes T129,T191,T192 OUTPUT
edn_o[1].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T2,T3,T80 Yes T2,T3,T80 OUTPUT
edn_o[2].edn_fips Yes Yes T126,T127,T128 Yes T116,T129,T130 OUTPUT
edn_o[2].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T116,T323,T410 Yes T116,T130,T323 OUTPUT
edn_o[3].edn_fips No No Yes T116,T130,T323 OUTPUT
edn_o[3].edn_ack Yes Yes T116,T130,T323 Yes T116,T130,T323 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T2,T30,T81 Yes T1,T2,T30 OUTPUT
edn_o[4].edn_fips No No Yes T129,T411,T412 OUTPUT
edn_o[4].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[5].edn_fips Yes Yes T125,T413,T414 Yes T116,T125,T130 OUTPUT
edn_o[5].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[6].edn_fips Yes Yes T123,T125,T219 Yes T116,T123,T124 OUTPUT
edn_o[6].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[7].edn_bus[31:0] Yes Yes T2,T39,T40 Yes T2,T3,T80 OUTPUT
edn_o[7].edn_fips Yes Yes T123,T125,T219 Yes T116,T123,T125 OUTPUT
edn_o[7].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T2,T30,T4 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.genbits_fips Yes Yes T219,T220,T126 Yes T116,T123,T124 INPUT
csrng_cmd_i.genbits_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_rsp_sts No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T123,T125,T415 Yes T123,T125,T415 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T62,T63,T64 Yes T62,T63,T64 INPUT
alert_rx_i[0].ping_n Yes Yes T62,T63,T64 Yes T62,T63,T64 INPUT
alert_rx_i[0].ping_p Yes Yes T62,T63,T64 Yes T62,T63,T64 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T62,T63,T369 Yes T62,T63,T369 INPUT
alert_rx_i[1].ping_n Yes Yes T62,T63,T64 Yes T62,T63,T64 INPUT
alert_rx_i[1].ping_p Yes Yes T62,T63,T64 Yes T62,T63,T64 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T62,T63,T64 Yes T62,T63,T64 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T62,T63,T369 Yes T62,T63,T369 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T124,T216,T353 Yes T124,T216,T353 OUTPUT
intr_edn_fatal_err_o Yes Yes T216,T217,T218 Yes T216,T217,T218 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn1
TotalCoveredPercent
Totals 50 37 74.00
Total Bits 710 663 93.38
Total Bits 0->1 355 332 93.52
Total Bits 1->0 355 331 93.24

Ports 50 37 74.00
Port Bits 710 663 93.38
Port Bits 0->1 355 332 93.52
Port Bits 1->0 355 331 93.24

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T30,T4 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T2,T30,T4 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T82,T116,T123 Yes T82,T116,T123 INPUT
tl_i.a_user.cmd_intg[0] Yes Yes *T82,*T116,*T123 Yes T82,T116,T123 INPUT
tl_i.a_user.cmd_intg[1] No No No INPUT
tl_i.a_user.cmd_intg[6:2] Yes Yes T82,T116,T123 Yes T82,T116,T123 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T82,*T116,*T123 Yes T82,T116,T123 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T82,T116,T123 Yes T82,T116,T123 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T82,T116,T123 Yes T82,T116,T123 INPUT
tl_i.a_mask[3:0] Yes Yes T82,T116,T123 Yes T82,T116,T123 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[6:2] Yes Yes *T82,*T116,*T123 Yes T82,T116,T123 INPUT
tl_i.a_address[18:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:19] Yes Yes T82,T116,T123 Yes T82,T116,T123 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T82,*T116,*T123 Yes T82,T116,T123 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T82,*T116,*T123 Yes T82,T116,T123 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[1:0] Yes Yes *T65,*T66,*T82 Yes T65,T66,T82 INPUT
tl_i.a_source[5:2] No No No INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[0] No No No INPUT
tl_i.a_size[1] Yes Yes T82,T116,T123 Yes T82,T116,T123 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[1:0] No No No INPUT
tl_i.a_opcode[2] Yes Yes T82,T116,T123 Yes T82,T116,T123 INPUT
tl_i.a_valid Yes Yes T82,T116,T123 Yes T82,T116,T123 INPUT
tl_o.a_ready Yes Yes T82,T116,T123 Yes T82,T116,T123 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T82,T116,T123 Yes T82,T116,T123 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T116,T123,T124 Yes T82,T116,T123 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes *T126,*T65,*T176 Yes T82,T116,T123 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T116,T123,T124 Yes T82,T116,T123 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[1:0] Yes Yes *T65,*T66,*T82 Yes T65,T66,T82 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T126,T65,T176 Yes T82,T116,T123 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T82,*T116,*T123 Yes T82,T116,T123 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T82,T116,T123 Yes T82,T116,T123 OUTPUT
edn_i[0].edn_req Yes Yes T116,T123,T124 Yes T116,T123,T124 INPUT
edn_i[1].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[2].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[3].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[4].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[5].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[6].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[7].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_o[0].edn_bus[31:0] Yes Yes T116,T123,T124 Yes T116,T123,T124 OUTPUT
edn_o[0].edn_fips Yes Yes T123,T125,T219 Yes T116,T123,T124 OUTPUT
edn_o[0].edn_ack Yes Yes T116,T123,T124 Yes T116,T123,T124 OUTPUT
edn_o[1].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
csrng_cmd_o.genbits_ready Yes Yes T116,T123,T124 Yes T116,T123,T124 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T116,T123,T124 Yes T116,T123,T124 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T116,T123,T124 Yes T116,T123,T124 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T116,T123,T124 Yes T116,T123,T124 INPUT
csrng_cmd_i.genbits_fips No No Yes T219,T220,T416 INPUT
csrng_cmd_i.genbits_valid Yes Yes T116,T123,T124 Yes T116,T123,T124 INPUT
csrng_cmd_i.csrng_rsp_sts No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T116,T123,T124 Yes T116,T123,T124 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T123,T125,T127 Yes T123,T125,T127 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T62,T63,T64 Yes T62,T63,T64 INPUT
alert_rx_i[0].ping_n Yes Yes T62,T63,T64 Yes T62,T63,T64 INPUT
alert_rx_i[0].ping_p Yes Yes T62,T63,T64 Yes T62,T63,T64 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T62,T63,T369 Yes T62,T63,T369 INPUT
alert_rx_i[1].ping_n Yes Yes T62,T63,T64 Yes T62,T63,T64 INPUT
alert_rx_i[1].ping_p Yes Yes T62,T63,T64 Yes T62,T63,T64 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T62,T63,T64 Yes T62,T63,T64 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T62,T63,T369 Yes T62,T63,T369 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T124,T216,T353 Yes T124,T216,T353 OUTPUT
intr_edn_fatal_err_o Yes Yes T216,T217,T218 Yes T216,T217,T218 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn0
TotalCoveredPercent
Totals 78 62 79.49
Total Bits 1204 1154 95.85
Total Bits 0->1 602 579 96.18
Total Bits 1->0 602 575 95.51

Ports 78 62 79.49
Port Bits 1204 1154 95.85
Port Bits 0->1 602 579 96.18
Port Bits 1->0 602 575 95.51

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T30,T4 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T82,T116,T123 Yes T82,T116,T123 INPUT
tl_i.a_user.cmd_intg[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[1] No No No INPUT
tl_i.a_user.cmd_intg[6:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T82,T116,T123 Yes T82,T116,T123 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[6:2] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18:16] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[1:0] Yes Yes *T65,*T66,*T1 Yes T65,T66,T1 INPUT
tl_i.a_source[5:2] No No No INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[0] No No No INPUT
tl_i.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[1:0] No No No INPUT
tl_i.a_opcode[2] Yes Yes T82,T116,T123 Yes T82,T116,T123 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T82,T116,T123 Yes T82,T116,T123 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T2,T30,T4 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes *T2,*T30,*T4 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T2,T30,T4 Yes T1,T2,T3 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[1:0] Yes Yes *T65,*T66,*T2 Yes T65,T66,T1 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T2,T30,T4 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T82,*T116,*T123 Yes T82,T116,T123 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_i[0].edn_req Yes Yes T43,T116,T117 Yes T43,T116,T117 INPUT
edn_i[1].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[2].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[3].edn_req Yes Yes T116,T130,T323 Yes T116,T130,T323 INPUT
edn_i[4].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[5].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[6].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[7].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T43,T116,T117 Yes T43,T116,T117 OUTPUT
edn_o[0].edn_fips No No Yes T116,T130,T323 OUTPUT
edn_o[0].edn_ack Yes Yes T43,T116,T117 Yes T43,T116,T117 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[1].edn_fips No No Yes T129,T191,T192 OUTPUT
edn_o[1].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T2,T3,T80 Yes T2,T3,T80 OUTPUT
edn_o[2].edn_fips Yes Yes T126,T127,T128 Yes T116,T129,T130 OUTPUT
edn_o[2].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T116,T323,T410 Yes T116,T130,T323 OUTPUT
edn_o[3].edn_fips No No Yes T116,T130,T323 OUTPUT
edn_o[3].edn_ack Yes Yes T116,T130,T323 Yes T116,T130,T323 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T2,T30,T81 Yes T1,T2,T30 OUTPUT
edn_o[4].edn_fips No No Yes T129,T411,T412 OUTPUT
edn_o[4].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[5].edn_fips Yes Yes T125,T413,T414 Yes T116,T125,T130 OUTPUT
edn_o[5].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[6].edn_fips Yes Yes T123,T125,T219 Yes T116,T123,T124 OUTPUT
edn_o[6].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[7].edn_bus[31:0] Yes Yes T2,T39,T40 Yes T2,T3,T80 OUTPUT
edn_o[7].edn_fips Yes Yes T123,T125,T219 Yes T116,T123,T125 OUTPUT
edn_o[7].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T2,T30,T4 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.genbits_fips Yes Yes T219,T220,T126 Yes T116,T123,T124 INPUT
csrng_cmd_i.genbits_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_rsp_sts No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T123,T125,T415 Yes T123,T125,T415 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T62,T63,T64 Yes T62,T63,T64 INPUT
alert_rx_i[0].ping_n Yes Yes T62,T63,T64 Yes T62,T63,T64 INPUT
alert_rx_i[0].ping_p Yes Yes T62,T63,T64 Yes T62,T63,T64 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T62,T63,T64 Yes T62,T63,T64 INPUT
alert_rx_i[1].ping_n Yes Yes T62,T63,T64 Yes T62,T63,T64 INPUT
alert_rx_i[1].ping_p Yes Yes T62,T63,T64 Yes T62,T63,T64 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T62,T63,T64 Yes T62,T63,T64 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T62,T63,T64 Yes T62,T63,T64 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T124,T216,T353 Yes T124,T216,T353 OUTPUT
intr_edn_fatal_err_o Yes Yes T216,T217,T218 Yes T216,T217,T218 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%