CHIP Simulation Results

Thursday April 18 2024 19:02:27 UTC

GitHub Revision: `d3942ca074`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 25859338206198790995583629940734127463564215244480240139741775999763579929205

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	4.380m	3.212ms	3	3	100.00
		chip_sw_example_rom	2.252m	2.750ms	3	3	100.00
		chip_sw_example_manufacturer	3.193m	2.063ms	3	3	100.00
		chip_sw_example_concurrency	5.843m	3.374ms	3	3	100.00
		chip_sw_uart_smoketest_signed			0	3	0.00
V1	csr_hw_reset	chip_csr_hw_reset	6.620m	7.407ms	5	5	100.00
V1	csr_rw	chip_csr_rw	12.024m	6.131ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	1.640h	45.727ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	2.489h	50.858ms	4	5	80.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	1.936m	2.449ms	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	2.489h	50.858ms	4	5	80.00
		chip_csr_rw	12.024m	6.131ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	11.080s	252.259us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	8.666m	3.784ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	8.666m	3.784ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	8.666m	3.784ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	14.483m	4.403ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	14.483m	4.403ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	11.284m	4.264ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	11.447m	4.126ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	13.519m	4.381ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	47.892m	12.537ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	32.847m	8.947ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	40.305m	13.435ms	5	5	100.00
V1		TOTAL			199	223	89.24
V2	chip_pin_mux	chip_padctrl_attributes	6.491m	5.556ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	6.491m	5.556ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	5.620m	3.271ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	7.895m	5.196ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	7.362m	3.961ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	24.558m	14.841ms	5	5	100.00
		chip_tap_straps_testunlock0	12.085m	7.112ms	5	5	100.00
		chip_tap_straps_rma	16.820m	8.926ms	5	5	100.00
		chip_tap_straps_prod	3.026m	2.856ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	5.193m	3.490ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	24.937m	8.744ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	14.734m	4.781ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	14.734m	4.781ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	19.055m	6.974ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	36.617m	17.680ms	2	3	66.67
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	11.765m	4.519ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	23.388m	6.343ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.061h	19.292ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.479m	2.658ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	18.167m	5.382ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	6.019m	2.885ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	10.701m	4.650ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.698m	3.127ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.948m	4.778ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.420m	3.592ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	6.868m	3.181ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	18.784m	8.052ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	10.621m	5.689ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	6.098m	2.935ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	10.621m	5.689ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	4.552m	2.743ms	3	3	100.00
		chip_sw_aes_smoketest	5.694m	3.228ms	3	3	100.00
		chip_sw_aon_timer_smoketest	5.330m	2.784ms	3	3	100.00
		chip_sw_clkmgr_smoketest	3.797m	3.284ms	3	3	100.00
		chip_sw_csrng_smoketest	3.144m	2.536ms	3	3	100.00
		chip_sw_entropy_src_smoketest	8.014m	3.428ms	3	3	100.00
		chip_sw_gpio_smoketest	4.762m	2.396ms	3	3	100.00
		chip_sw_hmac_smoketest	6.975m	3.029ms	3	3	100.00
		chip_sw_kmac_smoketest	6.148m	3.192ms	3	3	100.00
		chip_sw_otbn_smoketest	30.909m	9.959ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	4.935m	2.851ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	9.498m	5.200ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	8.196m	6.240ms	3	3	100.00
		chip_sw_rv_plic_smoketest	5.136m	2.574ms	3	3	100.00
		chip_sw_rv_timer_smoketest	6.489m	3.418ms	3	3	100.00
		chip_sw_rstmgr_smoketest	3.732m	3.013ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	3.790m	2.551ms	3	3	100.00
		chip_sw_uart_smoketest	5.393m	2.770ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	11.270m	3.910ms	3	3	100.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed			0	3	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.579h	76.911ms	1	3	33.33
V2	chip_sw_secure_boot	rom_e2e_smoke			0	3	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	5.159h	204.823ms	0	3	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	11.927m	4.463ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	10.445m	10.728ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	3.118h	58.969ms	3	3	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.337h	64.021ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	7.000m	4.145ms	30	30	100.00
V2	tl_d_illegal_access	chip_tl_errors	7.000m	4.145ms	30	30	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	2.489h	50.858ms	4	5	80.00
		chip_same_csr_outstanding	1.379h	32.281ms	19	20	95.00
		chip_csr_hw_reset	6.620m	7.407ms	5	5	100.00
		chip_csr_rw	12.024m	6.131ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	2.489h	50.858ms	4	5	80.00
		chip_same_csr_outstanding	1.379h	32.281ms	19	20	95.00
		chip_csr_hw_reset	6.620m	7.407ms	5	5	100.00
		chip_csr_rw	12.024m	6.131ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.735m	2.623ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.830s	58.281us	100	100	100.00
		xbar_smoke_large_delays	2.093m	11.096ms	100	100	100.00
		xbar_smoke_slow_rsp	1.940m	6.576ms	100	100	100.00
		xbar_random_zero_delays	1.020m	604.385us	100	100	100.00
		xbar_random_large_delays	22.442m	110.658ms	100	100	100.00
		xbar_random_slow_rsp	21.396m	67.596ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.017m	1.417ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.050m	1.495ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.635m	2.454ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.050m	1.495ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	3.021m	3.828ms	100	100	100.00
		xbar_access_same_device_slow_rsp	48.449m	161.879ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.404m	2.762ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	11.411m	15.209ms	100	100	100.00
		xbar_stress_all_with_error	13.965m	21.795ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	16.992m	19.995ms	100	100	100.00
		xbar_stress_all_with_reset_error	16.569m	23.810ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke			0	3	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output			0	3	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	53.801m	15.252ms	3	3	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	41.349m	8.968ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	53.625m	12.420ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	43.562m	12.140ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	47.121m	11.914ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	51.539m	12.318ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	38.626m	9.204ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	55.608m	12.639ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	43.495m	12.328ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	48.681m	12.109ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	48.504m	12.029ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	58.026m	14.034ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	1.123h	18.154ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	1.499h	19.229ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	1.236h	19.249ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	1.211h	18.313ms	1	1	100.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	59.139m	13.176ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	1.349h	17.744ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	1.032h	18.026ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	1.212h	18.162ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	1.350h	17.679ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	39.190m	10.630ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	54.064m	14.042ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	1.262h	14.621ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	52.636m	14.573ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	51.877m	14.513ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	34.745m	9.836ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	45.519m	14.554ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	58.205m	14.856ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	1.021h	15.146ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	58.066m	14.390ms	1	1	100.00
V2	rom_e2e_sigverify_mod_exp	rom_e2e_sigverify_mod_exp_test_unlocked0_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_sw			0	3	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	39.416m	10.539ms	3	3	100.00
		rom_e2e_asm_init_dev	1.008h	15.239ms	3	3	100.00
		rom_e2e_asm_init_prod	1.007h	15.208ms	3	3	100.00
		rom_e2e_asm_init_prod_end	1.225h	15.472ms	3	3	100.00
		rom_e2e_asm_init_rma	1.172h	14.683ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas			0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	1.110h	20.016ms	0	3	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.933m	2.831ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.479m	2.658ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.764m	3.094ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.813m	2.647ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	10.890m	5.109ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	9.144m	17.477ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	9.144m	17.477ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	8.645m	4.334ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	9.498m	5.200ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	8.645m	4.334ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	16.186m	7.183ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	16.186m	7.183ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	9.976m	7.087ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	13.129m	5.972ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	17.760m	5.894ms	3	3	100.00
		chip_sw_aes_idle	4.813m	2.647ms	3	3	100.00
		chip_sw_hmac_enc_idle	5.612m	3.056ms	3	3	100.00
		chip_sw_kmac_idle	5.571m	3.172ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	8.630m	5.917ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	9.398m	5.673ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	11.454m	5.986ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	8.423m	4.555ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	20.659m	11.936ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	10.432m	3.602ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.283m	5.477ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	9.817m	4.139ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.206m	4.586ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.577m	4.714ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.237m	4.258ms	3	3	100.00
		chip_sw_ast_clk_outputs	19.055m	6.974ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	15.049m	12.407ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	9.817m	4.139ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.206m	4.586ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	11.765m	4.519ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	23.388m	6.343ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.061h	19.292ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.479m	2.658ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	18.167m	5.382ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	6.019m	2.885ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	10.701m	4.650ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.698m	3.127ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.948m	4.778ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.420m	3.592ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.844m	2.650ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	11.565m	4.413ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	20.179m	7.292ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.088h	24.506ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	5.763m	3.369ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	4.508m	2.827ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	10.240m	4.555ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	6.687m	3.538ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	12.217m	4.779ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	39.088m	26.164ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	1.031h	19.248ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	19.055m	6.974ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.887m	4.594ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	6.885m	3.362ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	14.652m	4.924ms	100	100	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	30.317m	7.654ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	27.273m	7.760ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	7.716m	4.912ms	3	3	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	12.784m	7.230ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	5.024m	2.860ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	24.595m	7.960ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	32.958m	22.336ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	5.454m	2.859ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	40.760s	10.240us	0	3	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	13.257m	4.815ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	32.958m	22.336ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	32.958m	22.336ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	56.738m	21.088ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	56.738m	21.088ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	11.832m	5.084ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	9.144m	17.477ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.598h	23.717ms	3	3	100.00
		chip_sw_entropy_src_ast_rng_req	3.797m	2.348ms	3	3	100.00
		chip_sw_edn_entropy_reqs	20.440m	6.172ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	3.797m	2.348ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	27.273m	7.760ms	3	3	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	4.861m	2.086ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	51.060m	18.876ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	17.942m	5.772ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	23.388m	6.343ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	12.868m	4.255ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	11.765m	4.519ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.396h	44.612ms	3	3	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	51.060m	18.876ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	6.622m	3.511ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	10.095m	4.392ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	11.492m	4.618ms	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.396h	44.612ms	3	3	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	11.492m	4.618ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	11.492m	4.618ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	11.492m	4.618ms	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	11.492m	4.618ms	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	14.652m	4.924ms	100	100	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	5.769m	10.911ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	19.004m	6.031ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	9.164m	4.154ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	9.164m	4.154ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	5.210m	2.615ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	6.019m	2.885ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.612m	3.056ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	16.182m	6.028ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	13.347m	4.856ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	19.501m	5.887ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	9.820m	3.692ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	10.095m	4.392ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	10.701m	4.650ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	11.941m	4.972ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	10.890m	5.109ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	54.274m	14.554ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.534m	2.691ms	3	3	100.00
		chip_sw_kmac_mode_kmac	6.480m	3.375ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.698m	3.127ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	10.095m	4.392ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	19.329m	13.260ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	4.252m	3.345ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.208m	2.880ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	5.571m	3.172ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	12.938m	6.336ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	24.558m	14.841ms	5	5	100.00
		chip_tap_straps_rma	16.820m	8.926ms	5	5	100.00
		chip_tap_straps_prod	3.026m	2.856ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	6.415m	3.375ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	19.329m	13.260ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	19.329m	13.260ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	19.329m	13.260ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	10.410m	5.134ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	11.492m	4.618ms	3	3	100.00
		chip_sw_flash_rma_unlocked	1.396h	44.612ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.135m	4.888ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	24.155m	8.655ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	25.553m	8.176ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	24.067m	7.329ms	3	3	100.00
		chip_sw_lc_ctrl_transition	19.329m	13.260ms	15	15	100.00
		chip_sw_keymgr_key_derivation	10.095m	4.392ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	10.419m	9.741ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	16.169m	8.869ms	3	3	100.00
		chip_prim_tl_access	5.769m	10.911ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	15.049m	12.407ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	10.432m	3.602ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.283m	5.477ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	9.817m	4.139ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.206m	4.586ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.577m	4.714ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.237m	4.258ms	3	3	100.00
		chip_tap_straps_dev	24.558m	14.841ms	5	5	100.00
		chip_tap_straps_rma	16.820m	8.926ms	5	5	100.00
		chip_tap_straps_prod	3.026m	2.856ms	5	5	100.00
		chip_rv_dm_lc_disabled	7.362m	17.298ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.726m	3.743ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.382m	2.833ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.430m	3.156ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.845m	3.087ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	48.050m	34.308ms	3	3	100.00
		chip_rv_dm_lc_disabled	7.362m	17.298ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.530h	49.450ms	3	3	100.00
		chip_sw_lc_walkthrough_prod	1.562h	50.137ms	3	3	100.00
		chip_sw_lc_walkthrough_prodend	21.668m	11.055ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	1.501h	49.159ms	3	3	100.00
		chip_sw_lc_walkthrough_testunlocks	48.050m	34.308ms	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	2.042m	2.579ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	2.204m	2.876ms	3	3	100.00
		rom_volatile_raw_unlock	2.123m	2.389ms	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	19.329m	13.260ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	51.060m	18.876ms	3	3	100.00
		chip_sw_otbn_mem_scramble	9.867m	3.508ms	3	3	100.00
		chip_sw_keymgr_key_derivation	10.095m	4.392ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	12.898m	3.766ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.074m	2.667ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	51.060m	18.876ms	3	3	100.00
		chip_sw_otbn_mem_scramble	9.867m	3.508ms	3	3	100.00
		chip_sw_keymgr_key_derivation	10.095m	4.392ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	12.898m	3.766ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.074m	2.667ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	19.329m	13.260ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	19.664m	14.227ms	0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	6.415m	3.375ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.135m	4.888ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	24.155m	8.655ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	25.553m	8.176ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	24.067m	7.329ms	3	3	100.00
		chip_sw_lc_ctrl_transition	19.329m	13.260ms	15	15	100.00
		chip_prim_tl_access	5.769m	10.911ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	5.769m	10.911ms	3	3	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	10.130m	8.968ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	28.418m	19.797ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	7.456m	7.187ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	13.426m	7.296ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	15.136m	7.921ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	26.078m	23.680ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	28.817m	13.963ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	16.186m	7.183ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	28.485m	11.278ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	10.427m	3.928ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	10.130m	8.968ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	7.789m	4.758ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	54.885m	34.285ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	9.603m	6.222ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	7.957m	6.649ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	37.671m	21.779ms	2	3	66.67
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	24.595m	7.960ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	26.864m	12.219ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	47.106m	20.844ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	5.655m	2.665ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	14.652m	4.924ms	100	100	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	10.419m	9.741ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	10.419m	9.741ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	26.864m	12.219ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	37.671m	21.779ms	2	3	66.67
		chip_sw_pwrmgr_wdog_reset	10.427m	3.928ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	9.498m	5.200ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	6.154m	3.270ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	15.731m	6.048ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	9.610m	5.209ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	36.140m	10.721ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.632m	2.725ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	14.652m	4.924ms	100	100	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	32.647m	9.397ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	20.650m	5.601ms	3	3	100.00
		chip_plic_all_irqs_10	10.820m	4.093ms	3	3	100.00
		chip_plic_all_irqs_20	14.383m	4.928ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.740m	2.645ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	4.644m	3.060ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke			0	3	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	12.686m	6.555ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	9.594m	4.304ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	5.989m	3.796ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	6.449m	2.431ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	12.898m	3.766ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.948m	4.778ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	16.075m	6.623ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	11.642m	8.792ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	16.169m	8.869ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	14.652m	4.924ms	100	100	100.00
		chip_sw_data_integrity_escalation	14.734m	4.781ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	3.891m	2.686ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	3.904m	2.940ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	8.140m	3.007ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	10.043m	3.911ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	31.607m	8.035ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.933h	31.406ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	50.929m	12.186ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	7.652m	3.351ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	12.938m	6.336ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	14.652m	4.924ms	100	100	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	7.264m	3.385ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	36.140m	10.721ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	9.902m	5.589ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	11.037m	3.392ms	89	90	98.89
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	27.537m	12.217ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	30.317m	7.654ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	32.647m	9.397ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.774h	255.763ms	3	3	100.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	46.662m	19.707ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	28.386m	13.535ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	6.154m	3.270ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	10.697m	4.403ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	10.330m	3.796ms	0	3	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	16.820m	8.926ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	7.362m	17.298ms	3	3	100.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			2591	2657	97.52
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.042m	3.149ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark	2.843h	50.969ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	16.937m	5.780ms	0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	1.849m	1.896ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.590m	1.755ms	0	1	0.00
		rom_e2e_jtag_debug_rma	2.598m	2.349ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	1.133h	50.665ms	0	1	0.00
		rom_e2e_jtag_inject_dev	1.046h	50.891ms	0	1	0.00
		rom_e2e_jtag_inject_rma	1.090h	48.220ms	0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash			0	0	--
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	7.635m	4.027ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	10.064m	2.978ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	20.661m	5.240ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	35.745m	7.663ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	12.646m	3.498ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	23.497m	5.287ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	chip_sw_i2c_override			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	4.367m	2.472ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	10.918m	6.297ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	8.760m	23.370ms	0	3	0.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	10.492m	4.917ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	26.864m	12.219ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	14.652m	4.924ms	100	100	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	chip_sw_spi_device_pass_through_flash_model			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	chip_sw_spi_host_pass_through			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	14.483m	4.403ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.185h	18.701ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	1.849m	1.896ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.590m	1.755ms	0	1	0.00
		rom_e2e_jtag_debug_rma	2.598m	2.349ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.986m	5.211ms	3	3	100.00
V3		TOTAL			30	45	66.67
	Unmapped tests	chip_sival_flash_info_access	5.308m	3.264ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	11.421m	5.434ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	1.330h	16.927ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	19.728m	5.563ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	16.965m	4.739ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	9.425m	6.487ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	4.675m	2.812ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	5.054m	2.546ms	3	3	100.00
		chip_sw_flash_ctrl_write_clear			0	3	0.00
		TOTAL			2847	2955	96.35

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	9	9	8	88.89
V1	19	19	16	84.21
V2	290	276	251	86.55
V2S	1	1	1	100.00
V3	91	21	12	13.19

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.94	95.29	93.57	95.62	--	94.21	97.38	99.55

Failure Buckets

Exit reason: Error: User command failed Job returned non-zero exit code has 45 failures:

Test chip_sw_flash_ctrl_write_clear has 3 failures.

0.chip_sw_flash_ctrl_write_clear.96506800209050817751724549250694883876271914475451920813694307739759970061528
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_write_clear/latest/run.log

  (16:12:43) Loading:
  (16:12:43) Loading:
  (16:12:43) Loading: 4 packages loaded
  (16:12:44) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (16:12:44) WARNING: Target pattern parsing failed.
  (16:12:44) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (16:12:44) INFO: Elapsed time: 62.722s
  (16:12:44) INFO: 0 processes.
  (16:12:44) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_flash_ctrl_write_clear.24652028632949830997914799167811817951955437841134031059630627763691398303146
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_write_clear/latest/run.log

  (16:23:35) Loading:
  (16:23:36) Loading:
  (16:23:36) Loading: 4 packages loaded
  (16:23:36) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (16:23:36) WARNING: Target pattern parsing failed.
  (16:23:36) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (16:23:36) INFO: Elapsed time: 17.726s
  (16:23:36) INFO: 0 processes.
  (16:23:36) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_meas.5239461334957945240275228591456800078022683074395970009663524064700065865609
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

  (16:14:27) Loading:
  (16:14:28) Loading:
  (16:14:28) Loading: 4 packages loaded
  (16:14:28) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:14:28) WARNING: Target pattern parsing failed.
  (16:14:28) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:14:28) INFO: Elapsed time: 63.617s
  (16:14:28) INFO: 0 processes.
  (16:14:28) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_meas.55303526389915862972405336216698592996469472648237742302100454206213148487405
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

  (16:25:09) Loading:
  (16:25:10) Loading:
  (16:25:10) Loading: 4 packages loaded
  (16:25:10) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:25:10) WARNING: Target pattern parsing failed.
  (16:25:10) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:25:10) INFO: Elapsed time: 20.958s
  (16:25:10) INFO: 0 processes.
  (16:25:10) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_no_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_no_meas.30313998896121393246539378971117371769332188237143874173057494198597276600785
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

  (16:15:57) Loading:
  (16:15:58) Loading:
  (16:15:58) Loading: 4 packages loaded
  (16:15:58) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:15:58) WARNING: Target pattern parsing failed.
  (16:15:58) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:15:58) INFO: Elapsed time: 84.248s
  (16:15:58) INFO: 0 processes.
  (16:15:58) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_no_meas.53300150417382036782897197131458986780412634976741221207190114555303264972130
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

  (16:25:08) Loading:
  (16:25:09) Loading:
  (16:25:09) Loading: 4 packages loaded
  (16:25:09) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:25:09) WARNING: Target pattern parsing failed.
  (16:25:09) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:25:09) INFO: Elapsed time: 26.894s
  (16:25:09) INFO: 0 processes.
  (16:25:09) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_invalid_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_invalid_meas.24114859400588363407690279930037439858243661257993833336325740151652525666637
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

  (16:13:38) Loading:
  (16:13:38) Loading:
  (16:13:38) Loading: 4 packages loaded
  (16:13:38) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:13:38) WARNING: Target pattern parsing failed.
  (16:13:38) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:13:38) INFO: Elapsed time: 19.046s
  (16:13:38) INFO: 0 processes.
  (16:13:38) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_invalid_meas.31156206154273306196877806548880488498713526204592821652592803718940514071447
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

  (16:25:08) Loading:
  (16:25:09) Loading:
  (16:25:09) Loading: 4 packages loaded
  (16:25:09) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:25:09) WARNING: Target pattern parsing failed.
  (16:25:09) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:25:09) INFO: Elapsed time: 25.712s
  (16:25:09) INFO: 0 processes.
  (16:25:09) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_sigverify_mod_exp_test_unlocked0_otbn has 3 failures.

0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.88660156155345744001678609790388536020632627254446684358475710917922744770548
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

  (16:15:33) Loading:
  (16:15:34) Loading:
  (16:15:34) Loading: 4 packages loaded
  (16:15:34) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (16:15:34) WARNING: Target pattern parsing failed.
  (16:15:34) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (16:15:34) INFO: Elapsed time: 72.606s
  (16:15:34) INFO: 0 processes.
  (16:15:34) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.29193615236360233069294368089090537594876724112655772275882908310829711416749
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

  (16:25:07) Loading:
  (16:25:07) Loading:
  (16:25:07) Loading: 4 packages loaded
  (16:25:07) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (16:25:07) WARNING: Target pattern parsing failed.
  (16:25:07) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (16:25:08) INFO: Elapsed time: 18.989s
  (16:25:08) INFO: 0 processes.
  (16:25:08) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

... and 10 more tests.

UVM_ERROR @ * us: (cip_base_vseq.sv:829) [chip_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test chip_csr_mem_rw_with_rand_reset has 20 failures.
  - 0.chip_csr_mem_rw_with_rand_reset.67969597653799179919467424681426691035375552952187219662812788897924329704530
    Line 360, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2864.561663 us: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2864.561663 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_csr_mem_rw_with_rand_reset.4746978901035424439566675839703141019248906665951466604264839294237217793095
    Line 368, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2648.588726 us: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2648.588726 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 14 failures:
- Test chip_sw_rv_timer_systick_test has 3 failures.
  - 0.chip_sw_rv_timer_systick_test.17612607581738513298628657374130370990586412937674328067033773748072575083386
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:3123257b-6697-4e81-b656-83987e9d935f
```
  - 1.chip_sw_rv_timer_systick_test.65849454719679906344723788904896501498072204302001251849768146188241017154195
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:7f4f81fe-5f58-4553-ba81-918cd19561ff
```
  - ... and 1 more failures.
- Test rom_e2e_smoke has 3 failures.
  - 0.rom_e2e_smoke.106323713013972225763450163641245367833182093531981241008452333834562942359399
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_smoke/latest/run.log
```
  Job ID: smart:9377ceae-f23c-4f70-a131-0d1d88be125a
```
  - 1.rom_e2e_smoke.25574366021417404141099450905423177969029093431910246648799820876072740376542
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_smoke/latest/run.log
```
  Job ID: smart:8e298be7-0e74-4cb6-a6f4-805acab7c3ee
```
  - ... and 1 more failures.
- Test rom_e2e_shutdown_output has 3 failures.
  - 0.rom_e2e_shutdown_output.57478284163792483243238669834998360518957946384426763146085151944786348239704
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log
```
  Job ID: smart:c01605e1-cd1d-4944-a3cb-6db34cb123a0
```
  - 1.rom_e2e_shutdown_output.36886191429004145261601134100841196516761589139570845246054847213901928408878
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_output/latest/run.log
```
  Job ID: smart:b449ab26-6ad9-40ec-a788-cc9e4f2589c2
```
  - ... and 1 more failures.
- Test chip_sw_uart_tx_rx_bootstrap has 2 failures.
  - 1.chip_sw_uart_tx_rx_bootstrap.114981470325863344014225560798147955257125429567495973860530775976176133223363
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_bootstrap/latest/run.log
```
  Job ID: smart:59934099-16ff-460f-aa1d-238071cc4495
```
  - 2.chip_sw_uart_tx_rx_bootstrap.6197886402292321855226329091877821173185304496492966132552295247858030244527
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_bootstrap/latest/run.log
```
  Job ID: smart:c00a31e6-65ac-4f94-95e1-98063dee8d8f
```
- Test chip_sw_power_virus has 2 failures.
  - 1.chip_sw_power_virus.93611986093979052612795268975489411213674538447148509697278177656913733310213
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:e5c6a4b3-6e16-4342-9d48-b21debdc9a99
```
  - 2.chip_sw_power_virus.89436298716250732794170857663114800555435876330868897698547562536117356688466
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:698f29d6-e8fc-4d5e-98cb-96fda08c1fd3
```
- ... and 1 more tests.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat" has 3 failures:
- Test chip_sw_sysrst_ctrl_outputs has 3 failures.
  - 0.chip_sw_sysrst_ctrl_outputs.39551495194272367222455035472185605617454506414214551379736090181064841530449
    Line 770, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_sysrst_ctrl_outputs.65941109267175911097217263963401630074783328738709929109174144881715819854548
    Line 762, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:
- Test chip_sw_lc_ctrl_program_error has 3 failures.
  - 0.chip_sw_lc_ctrl_program_error.85882747458573279243493790813506156786172301685866640627659874625447856348981
    Line 920, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 14227.428936 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 14227.428936 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.chip_sw_lc_ctrl_program_error.104048742081129936635993924138647949999242645989865792035362172710169764982196
    Line 782, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 15483.022276 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 15483.022276 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_if.sv:717) [chip_if] wait timeout occurred! has 3 failures:
- Test chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up has 3 failures.
  - 0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.45260111644953466646733031925091044480301553858832596136367422067656503514709
    Line 804, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log
```
  UVM_FATAL @ 23927.675834 us: (chip_if.sv:717) [chip_if] wait timeout occurred!
  UVM_INFO @ 23927.675834 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.111998221751580717990756338915938732920071683162787833216207151198340593345358
    Line 767, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log
```
  UVM_FATAL @ 23370.125448 us: (chip_if.sv:717) [chip_if] wait timeout occurred!
  UVM_INFO @ 23370.125448 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep. has 3 failures:
- Test chip_sw_rv_dm_access_after_wakeup has 3 failures.
  - 0.chip_sw_rv_dm_access_after_wakeup.37845843727832175180646631783778363454513638162418177242168644516560298303376
    Line 920, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3795.520938 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3795.520938 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_rv_dm_access_after_wakeup.106694774234699036015352065855932948790426442696468288085956210805297405650733
    Line 739, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3887.377216 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3887.377216 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.22282677527315879723204775634922814634451020407155573407460959669892186082829
    Line 762, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 1895.831000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 1895.831000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.105116041325644562843689996680609789119861916594272427002588480455140289892190
    Line 750, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 1755.458500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 1755.458500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.43290597952810223360767992951135238005711060832526266464411076972126724504390
    Line 770, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 2348.791000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2348.791000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 3 failures:
- Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_inject_test_unlocked0.51381768990458446643182995377292502911939871851879154239892256487533942698877
    Line 777, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 50665.216906 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 50665.216906 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_dev has 1 failures.
  - 0.rom_e2e_jtag_inject_dev.57620699252582205842781802028631217918658778885507573008090329612385882172512
    Line 795, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log
```
  UVM_FATAL @ 50891.474760 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 50891.474760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_rma has 1 failures.
  - 0.rom_e2e_jtag_inject_rma.80897027751525637545250936857249415655900819897079554506658745929379892038568
    Line 793, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log
```
  UVM_FATAL @ 48219.791480 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 48219.791480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 3 failures:

Test rom_raw_unlock has 3 failures.

0.rom_raw_unlock.102812062479324664586468036583835733466733727577458400819890656496808595404867
Line 761, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest/run.log

  UVM_ERROR @ 205874.085450 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns
  
  UVM_INFO @ 205874.085450 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.rom_raw_unlock.108230211740559066972659800844059160942837201860613168130558773961690992252694
Line 776, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_raw_unlock/latest/run.log

  UVM_ERROR @ 204823.355183 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns
  
  UVM_INFO @ 204823.355183 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 2 failures:

Test rom_e2e_static_critical has 2 failures.

0.rom_e2e_static_critical.72848940977048322041809340862521812561732669616258012899780854378360899269980
Line 1010, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_static_critical/latest/run.log

  UVM_ERROR @ 20015.190407 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 20000000 ns
  
  UVM_INFO @ 20015.190407 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.rom_e2e_static_critical.11091337017790518841539289348479404570586370331945761181209630709957370198225
Line 969, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_static_critical/latest/run.log

  UVM_ERROR @ 20016.412356 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 20000000 ns
  
  UVM_INFO @ 20016.412356 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.107647556343029755316694839541461556137109501204731843175875702697030797308305
    Line 817, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3391.613784 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003718 MTVAL=40600800
  UVM_INFO @ 3391.613784 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:166) [chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != *'b* (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.53263912760145233710611093566157734201580795324040319101033560941445167526773
    Line 968, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 5779.550519 us: (chip_sw_power_virus_vseq.sv:166) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != 4'b0000 (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 5779.550519 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job chip_earlgrey_asic-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test chip_csr_aliasing has 1 failures.
  - 1.chip_csr_aliasing.52819003595020316992789516527853624059226284873605802980964939742124798115177
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_aliasing/latest/run.log
```
  Job ID: smart:dea553a5-1d06-4f32-8726-c615210364e0
```
Offending '(pend_req[h2d.a_source].pend == *)' has 1 failures:
- Test chip_sw_pwrmgr_random_sleep_all_reset_reqs has 1 failures.
  - 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.11235058359317888222077353107444742198544621940866305723513281761944981372734
    Line 930, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log
```
      Offending '(pend_req[h2d.a_source].pend == 0)'
  UVM_ERROR @ 17848.899492 us: (tlul_assert.sv:268) [ASSERT FAILED] pendingReqPerSrc_M
  UVM_INFO @ 17848.899492 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 1 failures:
- Test rom_e2e_static_critical has 1 failures.
  - 2.rom_e2e_static_critical.87225764025694206581113815508210644669955698700867963175700624504161048165435
    Line 968, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.rom_e2e_static_critical/latest/run.log
```
  UVM_ERROR @ 20019.878830 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 20000000 ns
  
  UVM_INFO @ 20019.878830 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:250) [chip_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_same_csr_outstanding has 1 failures.
  - 13.chip_same_csr_outstanding.22758182550385448248689377796510314915949310915157135912442387889349901060752
    Line 2998, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/13.chip_same_csr_outstanding/latest/run.log
```
  UVM_ERROR @ 16707.290288 us: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed masked_data == exp_data (1342177281 [0x50000001] vs 1342177280 [0x50000000]) addr 0x403200a8 read out mismatch
  UVM_INFO @ 16707.290288 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```