CHIP Simulation Results

Sunday April 21 2024 19:02:51 UTC

GitHub Revision: 4fd94db59a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 89274329416853274976097168471417145417282051311181377329444669936981619711436

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	4.123m	3.069ms	3	3	100.00
		chip_sw_example_rom	2.318m	2.493ms	3	3	100.00
		chip_sw_example_manufacturer	4.860m	2.917ms	3	3	100.00
		chip_sw_example_concurrency	5.092m	3.348ms	3	3	100.00
		chip_sw_uart_smoketest_signed			0	3	0.00
V1	csr_hw_reset	chip_csr_hw_reset			0	5	0.00
V1	csr_rw	chip_csr_rw			0	20	0.00
V1	csr_bit_bash	chip_csr_bit_bash			0	5	0.00
V1	csr_aliasing	chip_csr_aliasing			0	5	0.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset			0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing			0	5	0.00
		chip_csr_rw			0	20	0.00
V1	xbar_smoke	xbar_smoke			0	100	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	8.773m	4.532ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	8.773m	4.532ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	8.773m	4.532ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	12.353m	4.481ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	12.353m	4.481ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	13.431m	4.049ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	10.938m	3.708ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	13.802m	3.635ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	57.526m	13.096ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	53.979m	12.834ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	33.744m	13.800ms	5	5	100.00
V1		TOTAL			65	223	29.15
V2	chip_pin_mux	chip_padctrl_attributes	5.009m	5.819ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	5.009m	5.819ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	6.087m	3.863ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	8.039m	5.531ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	5.942m	3.625ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	29.180m	13.693ms	5	5	100.00
		chip_tap_straps_testunlock0	11.288m	6.414ms	5	5	100.00
		chip_tap_straps_rma	13.209m	6.303ms	5	5	100.00
		chip_tap_straps_prod	30.315m	15.059ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	4.541m	2.500ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	24.715m	7.703ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	13.260m	5.548ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	13.260m	5.548ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	18.229m	6.426ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs			0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	13.929m	4.333ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	21.259m	6.520ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.286h	18.983ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.096m	2.603ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	19.832m	5.802ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.462m	3.286ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	8.190m	3.785ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.668m	2.868ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	9.245m	3.756ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.144m	2.980ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	5.192m	2.599ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	16.559m	7.685ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	8.173m	5.524ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	4.659m	3.347ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	8.173m	5.524ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	4.631m	3.005ms	3	3	100.00
		chip_sw_aes_smoketest	5.089m	2.824ms	3	3	100.00
		chip_sw_aon_timer_smoketest	6.429m	2.885ms	3	3	100.00
		chip_sw_clkmgr_smoketest	5.513m	3.167ms	3	3	100.00
		chip_sw_csrng_smoketest	4.466m	2.744ms	3	3	100.00
		chip_sw_entropy_src_smoketest	9.627m	3.319ms	3	3	100.00
		chip_sw_gpio_smoketest	5.312m	2.819ms	3	3	100.00
		chip_sw_hmac_smoketest	6.103m	3.859ms	3	3	100.00
		chip_sw_kmac_smoketest	6.336m	3.588ms	3	3	100.00
		chip_sw_otbn_smoketest	43.867m	9.965ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	4.343m	3.325ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	10.767m	5.927ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	6.713m	5.610ms	3	3	100.00
		chip_sw_rv_plic_smoketest	4.552m	2.448ms	3	3	100.00
		chip_sw_rv_timer_smoketest	6.123m	3.314ms	3	3	100.00
		chip_sw_rstmgr_smoketest	4.772m	2.375ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	5.535m	3.415ms	3	3	100.00
		chip_sw_uart_smoketest	4.554m	2.788ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	8.647m	3.934ms	3	3	100.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed			0	3	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap			0	3	0.00
V2	chip_sw_secure_boot	rom_e2e_smoke			0	3	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	5.521h	204.325ms	0	3	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	13.934m	4.270ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	11.845m	10.501ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	3.316h	57.691ms	2	3	66.67
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.695h	64.644ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors			0	30	0.00
V2	tl_d_illegal_access	chip_tl_errors			0	30	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing			0	5	0.00
		chip_same_csr_outstanding			0	20	0.00
		chip_csr_hw_reset			0	5	0.00
		chip_csr_rw			0	20	0.00
V2	tl_d_partial_access	chip_csr_aliasing			0	5	0.00
		chip_same_csr_outstanding			0	20	0.00
		chip_csr_hw_reset			0	5	0.00
		chip_csr_rw			0	20	0.00
V2	xbar_base_random_sequence	xbar_random			0	100	0.00
V2	xbar_random_delay	xbar_smoke_zero_delays			0	100	0.00
		xbar_smoke_large_delays			0	100	0.00
		xbar_smoke_slow_rsp			0	100	0.00
		xbar_random_zero_delays			0	100	0.00
		xbar_random_large_delays			0	100	0.00
		xbar_random_slow_rsp			0	100	0.00
V2	xbar_unmapped_address	xbar_unmapped_addr			0	100	0.00
		xbar_error_and_unmapped_addr			0	100	0.00
V2	xbar_error_cases	xbar_error_random			0	100	0.00
		xbar_error_and_unmapped_addr			0	100	0.00
V2	xbar_all_access_same_device	xbar_access_same_device			0	100	0.00
		xbar_access_same_device_slow_rsp			0	100	0.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source			0	100	0.00
V2	xbar_stress_all	xbar_stress_all			0	100	0.00
		xbar_stress_all_with_error			0	100	0.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset			0	100	0.00
		xbar_stress_all_with_reset_error			0	100	0.00
V2	rom_e2e_smoke	rom_e2e_smoke			0	3	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output			0	3	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c			0	3	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	4.245h	77.364ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	5.012h	77.522ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma			0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	8.940h	153.117ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	4.950h	79.376ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma			0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	4.952h	79.578ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev			0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod			0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end			0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma			0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	5.197h	79.958ms	3	3	100.00
		rom_e2e_asm_init_dev			0	3	0.00
		rom_e2e_asm_init_prod			0	3	0.00
		rom_e2e_asm_init_prod_end			0	3	0.00
		rom_e2e_asm_init_rma			0	3	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas			0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	1.473h	20.018ms	0	3	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	5.960m	2.947ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.096m	2.603ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.780m	3.731ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.395m	2.592ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	6.847m	3.447ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	12.691m	19.332ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	12.691m	19.332ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	7.531m	3.967ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	10.767m	5.927ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	7.531m	3.967ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	20.466m	9.656ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	20.466m	9.656ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	9.825m	7.773ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	11.073m	5.241ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	17.114m	5.809ms	3	3	100.00
		chip_sw_aes_idle	4.395m	2.592ms	3	3	100.00
		chip_sw_hmac_enc_idle	5.162m	2.925ms	3	3	100.00
		chip_sw_kmac_idle	4.785m	2.765ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	9.646m	5.625ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	9.607m	4.115ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	8.995m	5.678ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	9.173m	5.502ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	28.271m	11.345ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.680m	4.449ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.383m	5.271ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.587m	3.963ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.730m	4.963ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.066m	4.344ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.421m	4.552ms	3	3	100.00
		chip_sw_ast_clk_outputs	18.229m	6.426ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	14.487m	10.281ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.587m	3.963ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.730m	4.963ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	13.929m	4.333ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	21.259m	6.520ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.286h	18.983ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.096m	2.603ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	19.832m	5.802ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.462m	3.286ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	8.190m	3.785ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.668m	2.868ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	9.245m	3.756ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.144m	2.980ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.984m	2.250ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	12.444m	4.688ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	20.786m	7.462ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.214h	25.317ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	4.784m	3.066ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	5.345m	3.315ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	8.694m	4.449ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	5.548m	3.440ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	12.338m	5.161ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	38.578m	21.949ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	1.254h	18.451ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	18.229m	6.426ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.741m	4.463ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	8.787m	3.441ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	16.537m	5.297ms	96	100	96.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	28.867m	8.152ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	34.793m	8.546ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	9.919m	4.781ms	3	3	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	10.268m	6.618ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.471m	3.328ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	19.553m	6.865ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	36.205m	23.569ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	7.019m	2.856ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	42.180s	10.340us	0	3	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	14.313m	4.709ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	36.205m	23.569ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	36.205m	23.569ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	1.122h	20.543ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	1.122h	20.543ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	7.869m	4.811ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	12.691m	19.332ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.936h	23.774ms	3	3	100.00
		chip_sw_entropy_src_ast_rng_req	4.034m	2.836ms	3	3	100.00
		chip_sw_edn_entropy_reqs	18.255m	5.857ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	4.034m	2.836ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	34.793m	8.546ms	3	3	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	4.537m	2.573ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	40.161m	22.739ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	18.980m	5.723ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	21.259m	6.520ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	12.207m	4.307ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	13.929m	4.333ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.763h	44.789ms	3	3	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	40.161m	22.739ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	7.812m	3.770ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	8.964m	4.262ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	10.418m	5.178ms	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.763h	44.789ms	3	3	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	10.418m	5.178ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	10.418m	5.178ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	10.418m	5.178ms	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	10.418m	5.178ms	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	16.537m	5.297ms	96	100	96.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access			0	3	0.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	16.841m	5.313ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	15.660m	6.085ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	15.660m	6.085ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	5.344m	3.413ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.462m	3.286ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.162m	2.925ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	19.501m	6.078ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	18.792m	6.134ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	12.117m	5.277ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	7.949m	3.575ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	8.964m	4.262ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	8.190m	3.785ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	8.842m	5.263ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	6.847m	3.447ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.630h	19.842ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	5.720m	3.483ms	3	3	100.00
		chip_sw_kmac_mode_kmac	6.372m	2.934ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.668m	2.868ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	8.964m	4.262ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	22.040m	10.107ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	4.566m	3.092ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.530m	3.249ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.785m	2.765ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	8.690m	5.082ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	29.180m	13.693ms	5	5	100.00
		chip_tap_straps_rma	13.209m	6.303ms	5	5	100.00
		chip_tap_straps_prod	30.315m	15.059ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.325m	2.982ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	22.040m	10.107ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	22.040m	10.107ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	22.040m	10.107ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	10.589m	4.102ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	10.418m	5.178ms	3	3	100.00
		chip_sw_flash_rma_unlocked	1.763h	44.789ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.301m	4.567ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	24.746m	8.384ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	25.047m	7.979ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	24.122m	8.363ms	3	3	100.00
		chip_sw_lc_ctrl_transition	22.040m	10.107ms	15	15	100.00
		chip_sw_keymgr_key_derivation	8.964m	4.262ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	10.148m	8.494ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	14.395m	8.413ms	3	3	100.00
		chip_prim_tl_access			0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_lc	14.487m	10.281ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.680m	4.449ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.383m	5.271ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.587m	3.963ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.730m	4.963ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.066m	4.344ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.421m	4.552ms	3	3	100.00
		chip_tap_straps_dev	29.180m	13.693ms	5	5	100.00
		chip_tap_straps_rma	13.209m	6.303ms	5	5	100.00
		chip_tap_straps_prod	30.315m	15.059ms	5	5	100.00
		chip_rv_dm_lc_disabled			0	3	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.709m	3.278ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.174m	3.414ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.962m	3.348ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.488m	3.115ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	45.260m	24.166ms	3	3	100.00
		chip_rv_dm_lc_disabled			0	3	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	2.153h	47.594ms	3	3	100.00
		chip_sw_lc_walkthrough_prod	1.889h	48.710ms	3	3	100.00
		chip_sw_lc_walkthrough_prodend	14.963m	8.973ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	1.872h	49.433ms	3	3	100.00
		chip_sw_lc_walkthrough_testunlocks	45.260m	24.166ms	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.876m	2.688ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.809m	2.548ms	3	3	100.00
		rom_volatile_raw_unlock	1.960m	2.554ms	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	22.040m	10.107ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	40.161m	22.739ms	3	3	100.00
		chip_sw_otbn_mem_scramble	7.913m	4.330ms	3	3	100.00
		chip_sw_keymgr_key_derivation	8.964m	4.262ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	13.553m	5.281ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.179m	2.717ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	40.161m	22.739ms	3	3	100.00
		chip_sw_otbn_mem_scramble	7.913m	4.330ms	3	3	100.00
		chip_sw_keymgr_key_derivation	8.964m	4.262ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	13.553m	5.281ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.179m	2.717ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	22.040m	10.107ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	19.822m	14.140ms	0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.325m	2.982ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.301m	4.567ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	24.746m	8.384ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	25.047m	7.979ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	24.122m	8.363ms	3	3	100.00
		chip_sw_lc_ctrl_transition	22.040m	10.107ms	15	15	100.00
		chip_prim_tl_access			0	3	0.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access			0	3	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	9.407m	7.349ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	26.350m	16.734ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	8.390m	8.182ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	10.218m	8.901ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	15.005m	6.703ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	33.790m	23.760ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	32.357m	17.058ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	20.466m	9.656ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	30.927m	11.478ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	11.373m	5.556ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	9.407m	7.349ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	9.510m	4.686ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	1.078h	32.627ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	7.450m	6.368ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	10.250m	5.750ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	48.931m	24.820ms	2	3	66.67
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	19.553m	6.865ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	36.640m	13.388ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	54.299m	25.013ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	4.536m	3.213ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	16.537m	5.297ms	96	100	96.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	10.148m	8.494ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	10.148m	8.494ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	36.640m	13.388ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	48.931m	24.820ms	2	3	66.67
		chip_sw_pwrmgr_wdog_reset	11.373m	5.556ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	10.767m	5.927ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	7.645m	4.069ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	11.511m	5.384ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	7.384m	4.269ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	34.284m	11.496ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.654m	2.702ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	16.537m	5.297ms	96	100	96.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	32.233m	8.930ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	19.595m	5.918ms	3	3	100.00
		chip_plic_all_irqs_10	12.043m	3.752ms	3	3	100.00
		chip_plic_all_irqs_20	13.542m	4.329ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.294m	3.090ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.150m	3.447ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke			0	3	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	13.667m	6.060ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	42.300m	12.987ms	2	3	66.67
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	8.037m	3.559ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	4.525m	3.104ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	13.553m	5.281ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	9.245m	3.756ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	11.901m	7.518ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	14.006m	6.575ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	14.395m	8.413ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	16.537m	5.297ms	96	100	96.00
		chip_sw_data_integrity_escalation	13.260m	5.548ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	3.556m	3.286ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	4.717m	3.053ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	7.049m	3.849ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	8.338m	4.166ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	39.372m	8.684ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	2.467h	31.307ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	58.033m	11.714ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	6.073m	2.843ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	8.690m	5.082ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	16.537m	5.297ms	96	100	96.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	4.992m	2.833ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	34.284m	11.496ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	8.178m	4.710ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	9.527m	4.080ms	88	90	97.78
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	26.870m	12.148ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	28.867m	8.152ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	32.233m	8.930ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.594h	256.045ms	2	3	66.67
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	40.957m	18.813ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	24.828m	13.836ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	7.645m	4.069ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	10.238m	4.414ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	9.443m	3.971ms	0	3	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	13.209m	6.303ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled			0	3	0.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			785	2627	29.88
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.294m	2.922ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark			0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	11.669m	4.055ms	0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	1.507m	2.180ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.759m	2.099ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.707m	2.048ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	1.290h	51.122ms	0	1	0.00
		rom_e2e_jtag_inject_dev	1.602h	45.824ms	0	1	0.00
		rom_e2e_jtag_inject_rma	1.326h	60.000ms	0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash			0	0	--
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	7.840m	3.777ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	10.061m	3.041ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	25.639m	5.783ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	40.240m	11.063ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	13.214m	2.984ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	24.064m	5.873ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	chip_sw_i2c_override			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	2.008m	2.553ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	11.533m	5.455ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	8.447m	23.316ms	0	3	0.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	8.423m	4.723ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	36.640m	13.388ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	16.537m	5.297ms	96	100	96.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	chip_sw_spi_device_pass_through_flash_model			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	chip_sw_spi_host_pass_through			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	12.353m	4.481ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.482h	18.562ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	1.507m	2.180ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.759m	2.099ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.707m	2.048ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	11.160m	6.131ms	3	3	100.00
V3		TOTAL			29	45	64.44
	Unmapped tests	chip_sival_flash_info_access	5.413m	2.601ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	10.083m	4.761ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	1.252h	17.421ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	16.008m	6.235ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	15.213m	4.251ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	10.108m	6.554ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	4.194m	2.967ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	4.335m	2.647ms	2	3	66.67
		chip_sw_flash_ctrl_write_clear			0	3	0.00
		TOTAL			905	2925	30.94

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	9	9	7	77.78
V1	19	19	12	63.16
V2	280	266	197	70.36
V2S	1	1	1	100.00
V3	91	21	11	12.09

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.47	93.52	83.37	90.65	--	94.80	97.38	83.11

Failure Buckets

• launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = The service is currently unavailable. has 956 failures:

  • Test chip_csr_bit_bash has 3 failures.

    • 0.chip_csr_bit_bash.35375986005243173314961050547789962178496249758735438226278877017559544291702
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log

    • 2.chip_csr_bit_bash.73116082363300700072493520250407481401794400621563132554705942539511715794111
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_csr_bit_bash/latest/run.log

    • ... and 1 more failures.

  • Test chip_same_csr_outstanding has 3 failures.

    • 0.chip_same_csr_outstanding.2740176066794439090507732305816576666526776419625501790268635646349358154318
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log

    • 2.chip_same_csr_outstanding.92898900666772460375666332570845009826873498228342028205980900449588233778376
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_same_csr_outstanding/latest/run.log

    • ... and 1 more failures.

  • Test chip_prim_tl_access has 2 failures.

    • 0.chip_prim_tl_access.65084335358508415675572959701072636573399632316352397182519282688266872585913
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_prim_tl_access/latest/run.log

    • 2.chip_prim_tl_access.109348114807797439116697378562125762749389350305804788603366810308874299859553
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_prim_tl_access/latest/run.log

  • Test xbar_smoke has 8 failures.

    • 0.xbar_smoke.60551586608754549305968958833648780173306283205101355406503725070597023806124
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke/latest/run.log

    • 2.xbar_smoke.4308828895047471101201163631095508005117038025429326411300418678261038063642
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke/latest/run.log

    • ... and 6 more failures.

  • Test xbar_smoke_large_delays has 8 failures.

    • 0.xbar_smoke_large_delays.38977701851154507311014851337542652897069314943199928766648045335217690803989
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_large_delays/latest/run.log

    • 2.xbar_smoke_large_delays.21135447166836096165547224574856787315115075790534591670968602816991593153812
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_large_delays/latest/run.log

    • ... and 6 more failures.

  • ... and 22 more tests.

• Job killed most likely because its dependent job failed. has 955 failures:

  • Test chip_csr_aliasing has 3 failures.

    • 0.chip_csr_aliasing.113243048392030764496076226014039626986170653316979735043508676161211933686507
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log

    • 2.chip_csr_aliasing.6224466517231028400065653535911202355439574907127824983200423174684008753662
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_csr_aliasing/latest/run.log

    • ... and 1 more failures.

  • Test chip_tl_errors has 8 failures.

    • 0.chip_tl_errors.28175170458043127834413601882070006692005815396012119238262647881544130055749
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

    • 2.chip_tl_errors.46265881641087467461415012121231249180630770963332110436961081812701882375419
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_tl_errors/latest/run.log

    • ... and 6 more failures.

  • Test chip_rv_dm_lc_disabled has 2 failures.

    • 0.chip_rv_dm_lc_disabled.15241674932558369723242449814438869194510840171780660827974049576083581272938
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log

    • 2.chip_rv_dm_lc_disabled.10374162221966380149014726479468293773578059654370470712581236659353516785708
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_rv_dm_lc_disabled/latest/run.log

  • Test xbar_smoke_zero_delays has 8 failures.

    • 0.xbar_smoke_zero_delays.9256960530565484732334878555100586474305727353461134067119580174787647969976
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_zero_delays/latest/run.log

    • 2.xbar_smoke_zero_delays.56961173209882674511060143432258341826660786785092082868753407276103489417966
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_zero_delays/latest/run.log

    • ... and 6 more failures.

  • Test xbar_smoke_slow_rsp has 8 failures.

    • 0.xbar_smoke_slow_rsp.23185860690805045977425998755216523325840742980197173111173765258022249399974
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_slow_rsp/latest/run.log

    • 2.xbar_smoke_slow_rsp.65842085323235399845843964998622517577517480954562716958177878967912943814644
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_slow_rsp/latest/run.log

    • ... and 6 more failures.

  • ... and 22 more tests.

• Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 60 failures:

  • Test chip_sw_uart_tx_rx_bootstrap has 3 failures.

    • 0.chip_sw_uart_tx_rx_bootstrap.110527788351913444867403442046998522885861704939221825450182925817048905521887
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_bootstrap/latest/run.log

        Job ID: smart:fd589355-9532-4181-8820-84f748f5e668
      

    • 1.chip_sw_uart_tx_rx_bootstrap.36076032241555399912672945974469394273437912520280412457817062597744194245446
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_bootstrap/latest/run.log

        Job ID: smart:362cc480-9e49-4173-814e-4e302c655f10
      

    • ... and 1 more failures.

  • Test chip_sw_rv_timer_systick_test has 3 failures.

    • 0.chip_sw_rv_timer_systick_test.92351484503693984054531683515104948378549298617184349703625130766120943086252
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log

        Job ID: smart:4a5c22ca-93ee-4b5e-9358-a10393974493
      

    • 1.chip_sw_rv_timer_systick_test.111705980997285158273237231082860911817678635921404884802235633017392560803990
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log

        Job ID: smart:74494d3b-1183-4f5a-9a51-52499cdfa4dd
      

    • ... and 1 more failures.

  • Test chip_sw_coremark has 1 failures.

    • 0.chip_sw_coremark.40989904644017032460508192756902799891882322079881721530199597556560515424179
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log

        Job ID: smart:e98d4391-6a9c-4f15-bf27-d3cb9afba6c8
      

  • Test chip_sw_ast_clk_rst_inputs has 3 failures.

    • 0.chip_sw_ast_clk_rst_inputs.5643326487428872199582180256192290230217455924510825835243454435427110297069
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log

        Job ID: smart:becb09cc-41fb-435f-91e0-56cea314ae17
      

    • 1.chip_sw_ast_clk_rst_inputs.83634232057252167024287131441433009970724400433297593181874685293954180027565
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log

        Job ID: smart:11419f10-956c-4569-8995-cd912ce3aed6
      

    • ... and 1 more failures.

  • Test chip_sw_power_virus has 2 failures.

    • 0.chip_sw_power_virus.64363831994551929608979085636685118256025978919952998161909454872941094516071
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log

        Job ID: smart:07ea6f77-c10a-464d-86b2-0b61cc34df7d
      

    • 2.chip_sw_power_virus.101658560198152061310004676132687278179530051573374469983707459002966871273375
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_virus/latest/run.log

        Job ID: smart:45c37174-4849-4eb5-9be5-e6943fa28f3e
      

  • ... and 34 more tests.

• Exit reason: Error: User command failed Job returned non-zero exit code has 15 failures:

  • Test chip_sw_flash_ctrl_write_clear has 3 failures.

    • 0.chip_sw_flash_ctrl_write_clear.60603403968503145224186363145564292877422637088135366418072851890028248469663
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_write_clear/latest/run.log

        (14:54:49) Loading:
        (14:54:50) Loading:
        (14:54:50) Loading: 4 packages loaded
        (14:54:50) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
        (14:54:50) WARNING: Target pattern parsing failed.
        (14:54:50) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
        (14:54:50) INFO: Elapsed time: 20.357s
        (14:54:50) INFO: 0 processes.
        (14:54:50) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.chip_sw_flash_ctrl_write_clear.8775955022905724106891703677917329786397754727192986821934523469639115404368
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_write_clear/latest/run.log

        (15:08:45) Loading:
        (15:08:46) Loading:
        (15:08:46) Loading: 4 packages loaded
        (15:08:46) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
        (15:08:46) WARNING: Target pattern parsing failed.
        (15:08:46) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
        (15:08:46) INFO: Elapsed time: 20.040s
        (15:08:46) INFO: 0 processes.
        (15:08:46) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • Test rom_e2e_keymgr_init_rom_ext_meas has 3 failures.

    • 0.rom_e2e_keymgr_init_rom_ext_meas.110203183545438699062037899870782211618642552950160627446516998705420774912350
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

        (14:58:12) Loading:
        (14:58:13) Loading:
        (14:58:13) Loading: 4 packages loaded
        (14:58:13) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (14:58:13) WARNING: Target pattern parsing failed.
        (14:58:13) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (14:58:13) INFO: Elapsed time: 36.452s
        (14:58:13) INFO: 0 processes.
        (14:58:13) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.rom_e2e_keymgr_init_rom_ext_meas.2303746437678081948874601159824620001033122917121563747408469162108790732781
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

        (15:10:11) Loading:
        (15:10:12) Loading:
        (15:10:12) Loading: 4 packages loaded
        (15:10:12) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:10:12) WARNING: Target pattern parsing failed.
        (15:10:12) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:10:12) INFO: Elapsed time: 20.096s
        (15:10:12) INFO: 0 processes.
        (15:10:12) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • Test rom_e2e_keymgr_init_rom_ext_no_meas has 3 failures.

    • 0.rom_e2e_keymgr_init_rom_ext_no_meas.29806335931256978324540955921393152070246711345133958614149652172314968902276
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

        (14:58:01) Loading:
        (14:58:02) Loading:
        (14:58:02) Loading: 4 packages loaded
        (14:58:02) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (14:58:02) WARNING: Target pattern parsing failed.
        (14:58:02) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (14:58:02) INFO: Elapsed time: 19.747s
        (14:58:02) INFO: 0 processes.
        (14:58:02) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.rom_e2e_keymgr_init_rom_ext_no_meas.93036551219728837432434891007261014625097668032592873978872528316189866176061
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

        (15:10:07) Loading:
        (15:10:08) Loading:
        (15:10:08) Loading: 4 packages loaded
        (15:10:08) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:10:08) WARNING: Target pattern parsing failed.
        (15:10:08) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:10:08) INFO: Elapsed time: 18.728s
        (15:10:08) INFO: 0 processes.
        (15:10:08) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • Test rom_e2e_keymgr_init_rom_ext_invalid_meas has 3 failures.

    • 0.rom_e2e_keymgr_init_rom_ext_invalid_meas.37670207659250756321861019071569272225612642216160176661328785498349035098921
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

        (14:58:21) Loading:
        (14:58:22) Loading:
        (14:58:22) Loading: 4 packages loaded
        (14:58:22) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (14:58:22) WARNING: Target pattern parsing failed.
        (14:58:22) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (14:58:22) INFO: Elapsed time: 23.380s
        (14:58:22) INFO: 0 processes.
        (14:58:22) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.rom_e2e_keymgr_init_rom_ext_invalid_meas.61941608308875296115600791006428697841553875224442364244589121424883121756915
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

        (15:10:22) Loading:
        (15:10:23) Loading:
        (15:10:23) Loading: 4 packages loaded
        (15:10:23) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:10:23) WARNING: Target pattern parsing failed.
        (15:10:23) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:10:23) INFO: Elapsed time: 27.374s
        (15:10:23) INFO: 0 processes.
        (15:10:23) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • Test chip_sw_uart_smoketest_signed has 3 failures.

    • 0.chip_sw_uart_smoketest_signed.62638649533932508020158394604230709999643968883332903047786533233414789123309
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_smoketest_signed/latest/run.log

        (14:58:31) Loading:
        (14:58:32) Loading:
        (14:58:32) Loading: 4 packages loaded
        (14:58:32) ERROR: Skipping '//sw/device/tests:uart_smoketest_signed_sim_dv': no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /workspace/mnt/repo_top/sw/device/tests/BUILD (Tip: use `query "//sw/device/tests:*"` to see all the targets in that package)
        (14:58:32) WARNING: Target pattern parsing failed.
        (14:58:32) ERROR: no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /workspace/mnt/repo_top/sw/device/tests/BUILD (Tip: use `query "//sw/device/tests:*"` to see all the targets in that package)
        (14:58:33) INFO: Elapsed time: 19.740s
        (14:58:33) INFO: 0 processes.
        (14:58:33) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.chip_sw_uart_smoketest_signed.91931420550298513522232340346826831068088478463898324428772394900881809648605
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_smoketest_signed/latest/run.log

        (15:10:20) Loading:
        (15:10:21) Loading:
        (15:10:21) Loading: 4 packages loaded
        (15:10:21) ERROR: Skipping '//sw/device/tests:uart_smoketest_signed_sim_dv': no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /workspace/mnt/repo_top/sw/device/tests/BUILD (Tip: use `query "//sw/device/tests:*"` to see all the targets in that package)
        (15:10:21) WARNING: Target pattern parsing failed.
        (15:10:21) ERROR: no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /workspace/mnt/repo_top/sw/device/tests/BUILD (Tip: use `query "//sw/device/tests:*"` to see all the targets in that package)
        (15:10:21) INFO: Elapsed time: 19.722s
        (15:10:21) INFO: 0 processes.
        (15:10:21) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 4 failures:

  • Test chip_sw_all_escalation_resets has 4 failures.

    • 2.chip_sw_all_escalation_resets.112596024777114364844686418238079286507942162468762233588695627581953189046388
      Line 806, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_all_escalation_resets/latest/run.log

        UVM_ERROR @ 3260.026168 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
        UVM_INFO @ 3260.026168 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 14.chip_sw_all_escalation_resets.29488353502385271563773504992329572931396602788528040311663643140501804395258
      Line 757, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/14.chip_sw_all_escalation_resets/latest/run.log

        UVM_ERROR @ 2580.336792 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
        UVM_INFO @ 2580.336792 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat" has 3 failures:

  • Test chip_sw_sysrst_ctrl_outputs has 3 failures.

    • 0.chip_sw_sysrst_ctrl_outputs.73466747094807947324118610250179242528312105445083865686994196496094207733299
      Line 774, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest/run.log

        UVM_FATAL @  10.380001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
        UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_sysrst_ctrl_outputs.105777723709076692676786174524791057565055739024630226360841408709666847935884
      Line 769, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest/run.log

        UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
        UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:

  • Test chip_sw_lc_ctrl_program_error has 3 failures.

    • 0.chip_sw_lc_ctrl_program_error.30035098249060225231488433837027332448367040133288485071525352291529617579956
      Line 765, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log

        UVM_ERROR @ 14211.026360 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
        
        UVM_INFO @ 14211.026360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 1.chip_sw_lc_ctrl_program_error.47549280326439504447757737551078520200077557567977228861643823417948168888259
      Line 778, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log

        UVM_ERROR @ 14140.297832 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
        
        UVM_INFO @ 14140.297832 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (chip_if.sv:717) [chip_if] wait timeout occurred! has 3 failures:

  • Test chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up has 3 failures.

    • 0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.107245443663186819552648259783008179616019893074942070891620746908770690284167
      Line 759, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log

        UVM_FATAL @ 23315.976232 us: (chip_if.sv:717) [chip_if] wait timeout occurred!
        UVM_INFO @ 23315.976232 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.40739102921556154111862591536848079144860864549679397977566022923807342375730
      Line 787, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log

        UVM_FATAL @ 22275.152020 us: (chip_if.sv:717) [chip_if] wait timeout occurred!
        UVM_INFO @ 22275.152020 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep. has 3 failures:

  • Test chip_sw_rv_dm_access_after_wakeup has 3 failures.

    • 0.chip_sw_rv_dm_access_after_wakeup.93961780414358311858480215474003689670725942554123127432287810109169407329071
      Line 769, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log

        UVM_FATAL @ 3665.935766 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
        UVM_INFO @ 3665.935766 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_rv_dm_access_after_wakeup.28646227871367878973757428535388018944348389763051696948057804511789161124165
      Line 769, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log

        UVM_FATAL @ 3971.410895 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
        UVM_INFO @ 3971.410895 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:

  • Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.

    • 0.rom_e2e_jtag_debug_test_unlocked0.79486242251956659510083810817580684204553858726397503157467936358980204301078
      Line 775, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log

        UVM_FATAL @ 2180.265000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
        UVM_INFO @ 2180.265000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_jtag_debug_dev has 1 failures.

    • 0.rom_e2e_jtag_debug_dev.84821272023535155651728023965358278270797009734039090678964942276534193644726
      Line 726, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log

        UVM_FATAL @ 2098.878000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
        UVM_INFO @ 2098.878000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_jtag_debug_rma has 1 failures.

    • 0.rom_e2e_jtag_debug_rma.22787217098532798725840751893327784604290749066580325946315836240402709115515
      Line 727, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log

        UVM_FATAL @ 2047.759500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
        UVM_INFO @ 2047.759500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 2 failures:

  • Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.

    • 0.rom_e2e_jtag_inject_test_unlocked0.74776075181270205308586900885970299459025910344728991725676064074201601950084
      Line 750, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log

        UVM_FATAL @ 51121.772224 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
        UVM_INFO @ 51121.772224 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_jtag_inject_dev has 1 failures.

    • 0.rom_e2e_jtag_inject_dev.81956107423078818691686327036658439447245065955335163134606228806599825148684
      Line 735, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log

        UVM_FATAL @ 45824.250008 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
        UVM_INFO @ 45824.250008 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 2 failures:

  • Test rom_e2e_static_critical has 2 failures.

    • 0.rom_e2e_static_critical.56157757696421811643020244458244306441352987345985140975288358799819168600150
      Line 991, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_static_critical/latest/run.log

        UVM_ERROR @ 20018.115690 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 20000000 ns
        
        UVM_INFO @ 20018.115690 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 2.rom_e2e_static_critical.7425014213728429405563418175496242609968066883569705438990761269093996096210
      Line 985, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.rom_e2e_static_critical/latest/run.log

        UVM_ERROR @ 20016.606623 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 20000000 ns
        
        UVM_INFO @ 20016.606623 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 2 failures:

  • Test rom_raw_unlock has 2 failures.

    • 0.rom_raw_unlock.2646333714546845342196733908479511658642601663228025821305961664691371016783
      Line 762, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest/run.log

        UVM_ERROR @ 204325.092023 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 200000000 ns
        
        UVM_INFO @ 204325.092023 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 1.rom_raw_unlock.69855997054203071256388355302057516588198018644156554295811289430082239025779
      Line 784, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_raw_unlock/latest/run.log

        UVM_ERROR @ 205976.473614 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 200000000 ns
        
        UVM_INFO @ 205976.473614 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 2 failures:

  • Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 2 failures.

    • 16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1546201768703993107515457189323326376547051242586494882537591744803918108509
      Line 771, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log

        UVM_ERROR @ 3665.702896 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003718 MTVAL=40600800
        UVM_INFO @ 3665.702896 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 48.chip_sw_alert_handler_lpg_sleep_mode_alerts.54255219460201522446145080549491874525058692562678184203677033030954854634129
      Line 786, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log

        UVM_ERROR @ 3260.861896 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003718 MTVAL=40600800
        UVM_INFO @ 3260.861896 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (chip_sw_base_vseq.sv:457) [chip_sw_spi_passthrough_collision_vseq] timeout occurred! has 1 failures:

  • Test chip_sw_spi_device_pass_through_collision has 1 failures.

    • 0.chip_sw_spi_device_pass_through_collision.75466667814975116505882866757377163566404497342026598304851083175422927972450
      Line 744, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log

        UVM_FATAL @ 12986.552422 us: (chip_sw_base_vseq.sv:457) [uvm_test_top.env.virtual_sequencer.chip_sw_spi_passthrough_collision_vseq] timeout occurred!
        UVM_INFO @ 12986.552422 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_opcode === ((pend_req[d2h.d_source].opcode == Get) ? AccessAckData : AccessAck))' has 1 failures:

  • Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.

    • 0.chip_sw_rv_core_ibex_lockstep_glitch.67815085953951491321756871088796420206524631258624933942405568744189784932439
      Line 785, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log

            Offending '(d2h.d_opcode === ((pend_req[d2h.d_source].opcode == Get) ? AccessAckData : AccessAck))'
        UVM_ERROR @ 3053.637184 us: (tlul_assert.sv:258) [ASSERT FAILED] respOpcode_M
        UVM_INFO @ 3053.637184 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * us hit, indicating a probable testbench issue has 1 failures:

  • Test rom_e2e_jtag_inject_rma has 1 failures.

    • 0.rom_e2e_jtag_inject_rma.53110352028314635634562257253575860318312777329882361252938455018380679401575
      Line 768, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log

        UVM_FATAL @ 60000.000000 us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 60000.000000 us hit, indicating a probable testbench issue
        UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(pend_req[h2d.a_source].pend == *)' has 1 failures:

  • Test chip_sw_pwrmgr_random_sleep_all_reset_reqs has 1 failures.

    • 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.90962106781101786629498603935210835342346689815860115205231115676954689784786
      Line 909, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log

            Offending '(pend_req[h2d.a_source].pend == 0)'
        UVM_ERROR @ 17322.312024 us: (tlul_assert.sv:268) [ASSERT FAILED] pendingReqPerSrc_M
        UVM_INFO @ 17322.312024 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:166) [chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != *'b* (* [*] vs * [*]) has 1 failures:

  • Test chip_sw_power_virus has 1 failures.

    • 1.chip_sw_power_virus.46994625390578900910331200292693077568715624311658478942867277097237462696106
      Line 961, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log

        UVM_ERROR @ 4055.340789 us: (chip_sw_power_virus_vseq.sv:166) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != 4'b0000 (0 [0x0] vs 0 [0x0])
        UVM_INFO @ 4055.340789 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 1 failures:

  • Test rom_e2e_static_critical has 1 failures.

    • 1.rom_e2e_static_critical.34790352353574918390539686440864581069090497428720489334947320263057081511120
      Line 960, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_static_critical/latest/run.log

        UVM_ERROR @ 20018.674798 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 20000000 ns
        
        UVM_INFO @ 20018.674798 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 1 failures:

  • Test rom_raw_unlock has 1 failures.

    • 2.rom_raw_unlock.8807441578416738480211787573352879304233955562920495535034313185038488379853
      Line 787, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.rom_raw_unlock/latest/run.log

        UVM_ERROR @ 205440.549493 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns
        
        UVM_INFO @ 205440.549493 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• summary
• lint
• 2024.04.19_05.40.36
• 2024.04.17_05.47.39
• 2024.04.16_04.44.49
• 2024.04.05_04.55.17
• 2024.04.03_04.14.35