CHIP Simulation Results

Tuesday April 23 2024 19:02:21 UTC

GitHub Revision: `41bc3e0c7f`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 60193594966460162319774997373112005644450303415496697929754976735654535188776

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	5.544m	2.997ms	3	3	100.00
		chip_sw_example_rom	1.961m	2.273ms	3	3	100.00
		chip_sw_example_manufacturer	3.559m	2.328ms	3	3	100.00
		chip_sw_example_concurrency	5.395m	2.758ms	3	3	100.00
		chip_sw_uart_smoketest_signed	45.819m	10.010ms	0	3	0.00
V1	csr_hw_reset	chip_csr_hw_reset	6.781m	6.310ms	5	5	100.00
V1	csr_rw	chip_csr_rw	11.518m	5.939ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	1.168h	44.671ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	2.367h	63.337ms	4	5	80.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	2.121m	3.018ms	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	2.367h	63.337ms	4	5	80.00
		chip_csr_rw	11.518m	5.939ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	11.850s	269.696us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	8.869m	3.654ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	8.869m	3.654ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	8.869m	3.654ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	10.052m	3.981ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	10.052m	3.981ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	11.392m	3.758ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	11.926m	4.256ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	12.473m	3.724ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	45.402m	13.031ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	50.434m	13.268ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	23.721m	8.410ms	5	5	100.00
V1		TOTAL			199	223	89.24
V2	chip_pin_mux	chip_padctrl_attributes	6.086m	4.449ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	6.086m	4.449ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	4.861m	2.806ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	4.811m	4.492ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	4.778m	3.963ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	22.070m	11.578ms	5	5	100.00
		chip_tap_straps_testunlock0	13.469m	8.940ms	5	5	100.00
		chip_tap_straps_rma	8.563m	6.812ms	5	5	100.00
		chip_tap_straps_prod	16.792m	11.672ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	3.891m	2.588ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	26.143m	9.245ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	12.312m	5.973ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	12.312m	5.973ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	15.199m	7.364ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	45.048m	19.584ms	1	3	33.33
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	9.602m	3.558ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	17.973m	6.617ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.098h	18.298ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.087m	2.685ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	19.458m	5.518ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.042m	2.585ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	6.380m	4.099ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	4.606m	3.171ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	9.388m	4.776ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.835m	2.788ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	4.070m	3.037ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	19.398m	7.871ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	10.538m	5.694ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	4.321m	2.827ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	10.538m	5.694ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	4.528m	2.553ms	3	3	100.00
		chip_sw_aes_smoketest	5.678m	2.689ms	3	3	100.00
		chip_sw_aon_timer_smoketest	4.371m	2.674ms	3	3	100.00
		chip_sw_clkmgr_smoketest	3.236m	2.582ms	3	3	100.00
		chip_sw_csrng_smoketest	4.094m	2.753ms	3	3	100.00
		chip_sw_entropy_src_smoketest	8.410m	3.213ms	3	3	100.00
		chip_sw_gpio_smoketest	5.524m	3.274ms	3	3	100.00
		chip_sw_hmac_smoketest	5.605m	3.712ms	3	3	100.00
		chip_sw_kmac_smoketest	5.535m	2.881ms	3	3	100.00
		chip_sw_otbn_smoketest	43.014m	10.793ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	4.048m	2.919ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	8.543m	5.436ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	6.816m	5.896ms	3	3	100.00
		chip_sw_rv_plic_smoketest	4.187m	2.367ms	3	3	100.00
		chip_sw_rv_timer_smoketest	3.748m	2.672ms	3	3	100.00
		chip_sw_rstmgr_smoketest	4.097m	2.311ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	5.258m	3.510ms	3	3	100.00
		chip_sw_uart_smoketest	3.758m	2.840ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	9.925m	5.343ms	3	3	100.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	45.819m	10.010ms	0	3	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.772h	77.837ms	1	3	33.33
V2	chip_sw_secure_boot	rom_e2e_smoke			0	3	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	3.998h	205.573ms	0	3	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	12.831m	3.874ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	8.722m	10.774ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	3.203h	59.854ms	2	3	66.67
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.568h	64.488ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	9.038m	4.559ms	30	30	100.00
V2	tl_d_illegal_access	chip_tl_errors	9.038m	4.559ms	30	30	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	2.367h	63.337ms	4	5	80.00
		chip_same_csr_outstanding	1.249h	34.076ms	20	20	100.00
		chip_csr_hw_reset	6.781m	6.310ms	5	5	100.00
		chip_csr_rw	11.518m	5.939ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	2.367h	63.337ms	4	5	80.00
		chip_same_csr_outstanding	1.249h	34.076ms	20	20	100.00
		chip_csr_hw_reset	6.781m	6.310ms	5	5	100.00
		chip_csr_rw	11.518m	5.939ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.856m	2.103ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.870s	57.040us	100	100	100.00
		xbar_smoke_large_delays	1.972m	10.026ms	100	100	100.00
		xbar_smoke_slow_rsp	2.118m	6.755ms	100	100	100.00
		xbar_random_zero_delays	59.660s	554.236us	100	100	100.00
		xbar_random_large_delays	21.892m	108.784ms	100	100	100.00
		xbar_random_slow_rsp	22.475m	72.878ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.075m	1.387ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.014m	1.447ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.737m	2.470ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.014m	1.447ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.562m	3.043ms	100	100	100.00
		xbar_access_same_device_slow_rsp	45.587m	156.189ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.438m	2.478ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	16.250m	24.015ms	100	100	100.00
		xbar_stress_all_with_error	10.974m	20.387ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	17.802m	25.782ms	100	100	100.00
		xbar_stress_all_with_reset_error	18.053m	20.332ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke			0	3	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output			0	3	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c			0	3	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	4.476h	77.863ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	2.672h	50.020ms	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	5.220h	77.563ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	2.738h	50.026ms	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma			0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	8.488h	152.752ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	4.434h	80.236ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma			0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	4.443h	80.202ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev			0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod			0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end			0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma			0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	5.027h	79.246ms	3	3	100.00
		rom_e2e_asm_init_dev			0	3	0.00
		rom_e2e_asm_init_prod			0	3	0.00
		rom_e2e_asm_init_prod_end			0	3	0.00
		rom_e2e_asm_init_rma			0	3	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas			0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	1.390h	20.018ms	0	3	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	5.351m	2.626ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.087m	2.685ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.320m	3.167ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.127m	2.521ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	7.478m	4.281ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	9.556m	18.619ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	9.556m	18.619ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	8.529m	3.789ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	8.543m	5.436ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	8.529m	3.789ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	19.772m	10.070ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	19.772m	10.070ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	8.117m	6.369ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	9.974m	5.675ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	19.599m	6.041ms	3	3	100.00
		chip_sw_aes_idle	4.127m	2.521ms	3	3	100.00
		chip_sw_hmac_enc_idle	6.001m	2.948ms	3	3	100.00
		chip_sw_kmac_idle	5.328m	2.625ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	9.138m	4.507ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	9.260m	4.631ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	7.479m	5.296ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	7.438m	4.697ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	26.670m	11.565ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.537m	4.285ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.292m	4.918ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.846m	4.204ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.400m	5.144ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.737m	4.212ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.164m	5.127ms	3	3	100.00
		chip_sw_ast_clk_outputs	15.199m	7.364ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	7.512m	5.376ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.846m	4.204ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.400m	5.144ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	9.602m	3.558ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	17.973m	6.617ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.098h	18.298ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.087m	2.685ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	19.458m	5.518ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.042m	2.585ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	6.380m	4.099ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	4.606m	3.171ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	9.388m	4.776ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.835m	2.788ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.029m	2.233ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	11.285m	4.444ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	17.473m	7.141ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.061h	24.625ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	4.072m	2.969ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	4.605m	3.058ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	8.568m	4.741ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	5.289m	3.589ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	10.837m	5.007ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	35.505m	25.772ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	1.043h	21.462ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	15.199m	7.364ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	13.568m	4.568ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	7.333m	3.890ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	13.309m	4.465ms	99	100	99.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	27.753m	8.673ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	26.712m	7.450ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	12.774m	5.577ms	3	3	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	11.165m	5.869ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.796m	3.116ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	20.547m	7.715ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	31.537m	21.731ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	6.011m	3.233ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	38.430s	10.300us	0	3	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	11.384m	4.996ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	31.537m	21.731ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	31.537m	21.731ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	58.097m	20.535ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	58.097m	20.535ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	8.239m	5.505ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	9.556m	18.619ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	59.676m	13.435ms	3	3	100.00
		chip_sw_entropy_src_ast_rng_req	3.491m	3.081ms	3	3	100.00
		chip_sw_edn_entropy_reqs	20.579m	5.936ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	3.491m	3.081ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	26.712m	7.450ms	3	3	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	4.030m	2.463ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	38.518m	25.383ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	18.896m	6.047ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	17.973m	6.617ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	9.256m	4.587ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	9.602m	3.558ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.480h	44.132ms	3	3	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	38.518m	25.383ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	6.374m	3.214ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	7.788m	5.612ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	6.468m	3.898ms	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.480h	44.132ms	3	3	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	6.468m	3.898ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	6.468m	3.898ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	6.468m	3.898ms	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	6.468m	3.898ms	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	13.309m	4.465ms	99	100	99.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	4.856m	6.962ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	19.385m	4.796ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	10.575m	5.116ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	10.575m	5.116ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.511m	2.796ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.042m	2.585ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	6.001m	2.948ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	17.064m	5.548ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	13.719m	4.969ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	14.219m	5.695ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	9.312m	3.815ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	7.788m	5.612ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	6.380m	4.099ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	9.859m	4.936ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	7.478m	4.281ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.211h	17.793ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.965m	2.247ms	3	3	100.00
		chip_sw_kmac_mode_kmac	5.366m	2.990ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	4.606m	3.171ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	7.788m	5.612ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	16.564m	10.964ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	4.559m	3.297ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	4.273m	2.659ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	5.328m	2.625ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	9.708m	5.613ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	22.070m	11.578ms	5	5	100.00
		chip_tap_straps_rma	8.563m	6.812ms	5	5	100.00
		chip_tap_straps_prod	16.792m	11.672ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.046m	3.367ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	16.564m	10.964ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	16.564m	10.964ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	16.564m	10.964ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	8.594m	4.468ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	6.468m	3.898ms	3	3	100.00
		chip_sw_flash_rma_unlocked	1.480h	44.132ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.292m	5.094ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	24.620m	8.446ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	23.594m	9.638ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	21.876m	6.908ms	3	3	100.00
		chip_sw_lc_ctrl_transition	16.564m	10.964ms	15	15	100.00
		chip_sw_keymgr_key_derivation	7.788m	5.612ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	9.050m	8.844ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	18.229m	9.816ms	3	3	100.00
		chip_prim_tl_access	4.856m	6.962ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	7.512m	5.376ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.537m	4.285ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.292m	4.918ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.846m	4.204ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.400m	5.144ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.737m	4.212ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.164m	5.127ms	3	3	100.00
		chip_tap_straps_dev	22.070m	11.578ms	5	5	100.00
		chip_tap_straps_rma	8.563m	6.812ms	5	5	100.00
		chip_tap_straps_prod	16.792m	11.672ms	5	5	100.00
		chip_rv_dm_lc_disabled	9.325m	15.205ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.672m	2.987ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.180m	2.380ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.880m	3.455ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.220m	2.714ms	2	3	66.67
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	41.954m	28.419ms	3	3	100.00
		chip_rv_dm_lc_disabled	9.325m	15.205ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.817h	47.788ms	3	3	100.00
		chip_sw_lc_walkthrough_prod	1.551h	48.372ms	3	3	100.00
		chip_sw_lc_walkthrough_prodend	14.652m	9.913ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	1.618h	45.631ms	3	3	100.00
		chip_sw_lc_walkthrough_testunlocks	41.954m	28.419ms	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.753m	2.314ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.976m	2.716ms	3	3	100.00
		rom_volatile_raw_unlock	1.746m	2.130ms	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	16.564m	10.964ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	38.518m	25.383ms	3	3	100.00
		chip_sw_otbn_mem_scramble	8.302m	3.550ms	3	3	100.00
		chip_sw_keymgr_key_derivation	7.788m	5.612ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	8.577m	4.003ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.552m	3.082ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	38.518m	25.383ms	3	3	100.00
		chip_sw_otbn_mem_scramble	8.302m	3.550ms	3	3	100.00
		chip_sw_keymgr_key_derivation	7.788m	5.612ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	8.577m	4.003ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.552m	3.082ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	16.564m	10.964ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	17.020m	14.467ms	0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.046m	3.367ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.292m	5.094ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	24.620m	8.446ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	23.594m	9.638ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	21.876m	6.908ms	3	3	100.00
		chip_sw_lc_ctrl_transition	16.564m	10.964ms	15	15	100.00
		chip_prim_tl_access	4.856m	6.962ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	4.856m	6.962ms	3	3	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	8.376m	9.374ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	26.428m	20.234ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	6.418m	6.098ms	1	3	33.33
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	12.326m	7.037ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	11.849m	6.341ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	24.752m	19.489ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	26.649m	17.396ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	19.772m	10.070ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	28.190m	12.094ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	9.013m	5.595ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	8.376m	9.374ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	6.975m	4.611ms	2	3	66.67
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	1.030h	36.512ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	8.445m	6.359ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	8.071m	5.309ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	36.674m	17.874ms	2	3	66.67
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	20.547m	7.715ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	28.558m	13.627ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	38.982m	28.416ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	4.948m	2.811ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	13.309m	4.465ms	99	100	99.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	9.050m	8.844ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	9.050m	8.844ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	28.558m	13.627ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	36.674m	17.874ms	2	3	66.67
		chip_sw_pwrmgr_wdog_reset	9.013m	5.595ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	8.543m	5.436ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	6.924m	4.814ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	16.179m	7.207ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	7.677m	4.622ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	31.501m	13.465ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.308m	2.354ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	13.309m	4.465ms	99	100	99.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	26.794m	8.752ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	22.083m	6.699ms	3	3	100.00
		chip_plic_all_irqs_10	9.977m	4.198ms	3	3	100.00
		chip_plic_all_irqs_20	12.722m	4.657ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.199m	2.394ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.654m	3.093ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke			0	3	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	12.702m	7.739ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	7.951m	4.931ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	5.489m	3.426ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	4.734m	3.266ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	8.577m	4.003ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	9.388m	4.776ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	11.208m	6.658ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	10.550m	7.075ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	18.229m	9.816ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	13.309m	4.465ms	99	100	99.00
		chip_sw_data_integrity_escalation	12.312m	5.973ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	3.992m	2.858ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	3.870m	2.309ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	7.634m	3.407ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	7.631m	3.223ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	26.820m	7.301ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.945h	31.427ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	50.435m	12.649ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	6.001m	2.916ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	9.708m	5.613ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	13.309m	4.465ms	99	100	99.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	5.101m	2.933ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	31.501m	13.465ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	9.017m	5.913ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	9.628m	3.171ms	88	90	97.78
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	22.230m	10.182ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	27.753m	8.673ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	26.794m	8.752ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.860h	255.838ms	3	3	100.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	32.248m	16.839ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	24.846m	13.555ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	6.924m	4.814ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	9.821m	5.172ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	9.120m	3.931ms	0	3	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	8.563m	6.812ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	9.325m	15.205ms	3	3	100.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			2544	2627	96.84
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.805m	2.612ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark	2.819h	50.513ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	19.219m	5.285ms	0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	1.922m	1.881ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.614m	2.098ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.770m	2.130ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	1.216h	60.000ms	0	1	0.00
		rom_e2e_jtag_inject_dev	1.043h	60.000ms	0	1	0.00
		rom_e2e_jtag_inject_rma	1.142h	60.000ms	0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash			0	0	--
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.424m	3.339ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	8.990m	3.071ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	16.719m	4.788ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	44.715m	10.961ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	10.277m	3.165ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	16.957m	6.029ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	//sw/device/tests:i2c_host_override_test			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	4.875m	3.564ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	13.707m	5.357ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	5.822m	23.058ms	0	3	0.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	9.213m	5.165ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	28.558m	13.627ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	13.309m	4.465ms	99	100	99.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	chip_sw_spi_device_pass_through_flash_model			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	chip_sw_spi_host_pass_through			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	10.052m	3.981ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.336h	19.674ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	1.922m	1.881ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.614m	2.098ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.770m	2.130ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.987m	6.031ms	3	3	100.00
V3		TOTAL			30	45	66.67
	Unmapped tests	chip_sival_flash_info_access	4.183m	3.137ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	11.311m	5.758ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	1.115h	17.256ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	15.978m	5.063ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	15.057m	4.962ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	7.688m	4.392ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	4.777m	2.196ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	2.575m	2.506ms	3	3	100.00
		chip_sw_flash_ctrl_write_clear			0	3	0.00
		TOTAL			2800	2925	95.73

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	9	9	8	88.89
V1	19	19	16	84.21
V2	280	266	217	77.50
V2S	1	1	1	100.00
V3	91	21	12	13.19

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.00	95.29	93.69	95.62	--	94.41	97.38	99.59

Failure Buckets

Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 53 failures:
- Test chip_sw_uart_tx_rx_bootstrap has 2 failures.
  - 0.chip_sw_uart_tx_rx_bootstrap.58090763013028188775634685451345267038768398765050600831038542126807530252532
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_bootstrap/latest/run.log
```
  Job ID: smart:7a2dd18e-73b9-4e27-93f1-b263378ae600
```
  - 2.chip_sw_uart_tx_rx_bootstrap.66220457001819798395610084419236227076275653424918249979771629411492162547865
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_bootstrap/latest/run.log
```
  Job ID: smart:11363392-8fb7-40c4-bcea-9c351f620874
```
- Test chip_sw_exit_test_unlocked_bootstrap has 1 failures.
  - 0.chip_sw_exit_test_unlocked_bootstrap.47341114872011942485612172267600345802933397037174002036228267366300912197239
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_exit_test_unlocked_bootstrap/latest/run.log
```
  Job ID: smart:be1f553f-90f9-4079-b205-28ec0abd97b1
```
- Test chip_sw_rv_timer_systick_test has 3 failures.
  - 0.chip_sw_rv_timer_systick_test.86910903318121211155190008738501169384138745876811455785556278568043491309305
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:c7dd9203-185a-4fd0-812d-bda88af016ba
```
  - 1.chip_sw_rv_timer_systick_test.111250902627376398023270529317115506301794482064986913598140043248055886500377
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:464a81a7-811a-4330-9596-c223604dda2e
```
  - ... and 1 more failures.
- Test chip_sw_ast_clk_rst_inputs has 2 failures.
  - 0.chip_sw_ast_clk_rst_inputs.74009390627823535145908972065330929744187405268016139162402611621865728688829
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:e225bfd8-6bbd-4a3f-8131-952cd9b4822f
```
  - 1.chip_sw_ast_clk_rst_inputs.41381435195184051469300384227542916844421800243020243821475669573918791721753
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:f8b7f8c4-1dc0-4cfd-b7ad-87619d521b9f
```
- Test rom_e2e_smoke has 3 failures.
  - 0.rom_e2e_smoke.70363130528914324836224427451132475504186251423921987944338678365913836430574
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_smoke/latest/run.log
```
  Job ID: smart:02497678-ea39-496d-9801-7b68c5b29cf2
```
  - 1.rom_e2e_smoke.17842163927957260771738875715619665501956562123289181392875583444100457721091
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_smoke/latest/run.log
```
  Job ID: smart:f69b7c7d-1ad2-4e36-b6ec-bea48c776cab
```
  - ... and 1 more failures.
- ... and 30 more tests.
UVM_ERROR @ * us: (cip_base_vseq.sv:829) [chip_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test chip_csr_mem_rw_with_rand_reset has 20 failures.
  - 0.chip_csr_mem_rw_with_rand_reset.42356858346088544049797652647266312234242229854286710838252918402149637403369
    Line 371, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2576.434753 us: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2576.434753 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_csr_mem_rw_with_rand_reset.74351147613798222787182495484103771860782314755126808983707050709613666680151
    Line 373, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2599.962659 us: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2599.962659 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 12 failures:

Test chip_sw_flash_ctrl_write_clear has 3 failures.

0.chip_sw_flash_ctrl_write_clear.7181650482235911838066958224815095066598438705372943276138131807559416560205
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_write_clear/latest/run.log

  (15:47:41) Loading:
  (15:47:42) Loading:
  (15:47:42) Loading: 4 packages loaded
  (15:47:42) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:47:42) WARNING: Target pattern parsing failed.
  (15:47:42) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:47:42) INFO: Elapsed time: 29.458s
  (15:47:42) INFO: 0 processes.
  (15:47:42) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_flash_ctrl_write_clear.110906464686794461279786807633198694180606534297737936353503261895209272820298
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_write_clear/latest/run.log

  (16:05:25) Loading:
  (16:05:26) Loading:
  (16:05:26) Loading: 4 packages loaded
  (16:05:26) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (16:05:26) WARNING: Target pattern parsing failed.
  (16:05:26) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (16:05:26) INFO: Elapsed time: 37.562s
  (16:05:26) INFO: 0 processes.
  (16:05:26) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_meas.72262485521417594287813252267369928399219381334623307136952972487367791675276
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

  (15:54:20) Loading:
  (15:54:21) Loading:
  (15:54:21) Loading: 4 packages loaded
  (15:54:21) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:54:21) WARNING: Target pattern parsing failed.
  (15:54:21) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:54:21) INFO: Elapsed time: 18.914s
  (15:54:21) INFO: 0 processes.
  (15:54:21) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_meas.77145741773394807497542682856423551564631291408663729720284068074739844418107
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

  (16:06:14) Loading:
  (16:06:14) Loading:
  (16:06:14) Loading: 4 packages loaded
  (16:06:14) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:06:14) WARNING: Target pattern parsing failed.
  (16:06:14) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:06:15) INFO: Elapsed time: 20.269s
  (16:06:15) INFO: 0 processes.
  (16:06:15) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_no_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_no_meas.103319953244622497017158595570407567511370973596593610297868941845025201258946
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

  (15:54:20) Loading:
  (15:54:21) Loading:
  (15:54:21) Loading: 4 packages loaded
  (15:54:21) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:54:21) WARNING: Target pattern parsing failed.
  (15:54:21) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:54:21) INFO: Elapsed time: 16.930s
  (15:54:21) INFO: 0 processes.
  (15:54:21) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_no_meas.40419514492798020511412224815241325075419910289061191484175594661222064059787
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

  (16:06:29) Loading:
  (16:06:29) Loading:
  (16:06:29) Loading: 4 packages loaded
  (16:06:30) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:06:30) WARNING: Target pattern parsing failed.
  (16:06:30) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:06:30) INFO: Elapsed time: 20.516s
  (16:06:30) INFO: 0 processes.
  (16:06:30) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_invalid_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_invalid_meas.56011356274435293337375298619795236404484241427895156254532750270953153774046
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

  (15:54:23) Loading:
  (15:54:24) Loading:
  (15:54:24) Loading: 4 packages loaded
  (15:54:24) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:54:24) WARNING: Target pattern parsing failed.
  (15:54:24) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:54:24) INFO: Elapsed time: 16.868s
  (15:54:24) INFO: 0 processes.
  (15:54:24) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_invalid_meas.58484698997249911829357986018207459127395103055345431984259230981686214588908
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

  (16:06:20) Loading:
  (16:06:21) Loading:
  (16:06:21) Loading: 4 packages loaded
  (16:06:21) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:06:21) WARNING: Target pattern parsing failed.
  (16:06:21) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:06:21) INFO: Elapsed time: 18.180s
  (16:06:21) INFO: 0 processes.
  (16:06:21) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.60459194975839016851069652025161172300486418672136145102579305621451359024069
    Line 991, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest/run.log
```
  UVM_ERROR @ 50020.341559 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 50000000 ns
  
  UVM_INFO @ 50020.341559 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.96458108148288687508452069959387866808910014496253957297953988279063949654795
    Line 971, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_ERROR @ 50025.929209 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 50000000 ns
  
  UVM_INFO @ 50025.929209 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_static_critical has 3 failures.
  - 0.rom_e2e_static_critical.63218995521623129020801396584081661004446569815963508776612901008323167376030
    Line 925, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_static_critical/latest/run.log
```
  UVM_ERROR @ 20021.768481 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 20000000 ns
  
  UVM_INFO @ 20021.768481 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.rom_e2e_static_critical.8534949709146110871040697474396692007747028086019939029473187649684650504715
    Line 1124, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_static_critical/latest/run.log
```
  UVM_ERROR @ 20016.195573 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 20000000 ns
  
  UVM_INFO @ 20016.195573 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat" has 3 failures:
- Test chip_sw_sysrst_ctrl_outputs has 3 failures.
  - 0.chip_sw_sysrst_ctrl_outputs.23688827123405253787624189671103909635798629537626326339920621413808270961498
    Line 777, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.300001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_sysrst_ctrl_outputs.61756843129720986735994439747294643648996473657122033526335168866231817576879
    Line 744, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:
- Test chip_sw_lc_ctrl_program_error has 3 failures.
  - 0.chip_sw_lc_ctrl_program_error.67517974634813304303773373912945309381733113275590554453758546265340949976272
    Line 778, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 14736.541752 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 14736.541752 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.chip_sw_lc_ctrl_program_error.87972335667166681966804137987524242928238476324270595980477764419849814625104
    Line 773, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 15128.995000 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 15128.995000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_if.sv:717) [chip_if] wait timeout occurred! has 3 failures:
- Test chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up has 3 failures.
  - 0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.35229433592494172127780930666017454090903936095683415494864181954905706870056
    Line 883, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log
```
  UVM_FATAL @ 23402.583544 us: (chip_if.sv:717) [chip_if] wait timeout occurred!
  UVM_INFO @ 23402.583544 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.93277150886304993226282966383153871638619737074916597096548280526291509493206
    Line 796, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log
```
  UVM_FATAL @ 23057.771450 us: (chip_if.sv:717) [chip_if] wait timeout occurred!
  UVM_INFO @ 23057.771450 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep. has 3 failures:
- Test chip_sw_rv_dm_access_after_wakeup has 3 failures.
  - 0.chip_sw_rv_dm_access_after_wakeup.76233501268905385147369008540509993401305326622371004912705897374156452146537
    Line 802, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3931.288904 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3931.288904 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_rv_dm_access_after_wakeup.8845046650736807410967486229527463195363733111033761450494188327868879540597
    Line 733, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3612.054772 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3612.054772 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.83495101716292291793156385220163159634114421318555391305652142041989301872276
    Line 727, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 1880.552000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 1880.552000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.71265783759746964050609656585332522742072210002178638721051082918748830662358
    Line 712, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 2097.950000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2097.950000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.90263487964534839123992837448781179620353577869428714490318978905172942548873
    Line 715, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 2129.729000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2129.729000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * us hit, indicating a probable testbench issue has 3 failures:
- Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_inject_test_unlocked0.48944927910913810788003113368732438868505117769500342724405269116379821245155
    Line 748, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 60000.000000 us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 60000.000000 us hit, indicating a probable testbench issue
  UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_dev has 1 failures.
  - 0.rom_e2e_jtag_inject_dev.114694591604890448145930440100718220587320227477550088507865055632775497948522
    Line 735, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log
```
  UVM_FATAL @ 60000.000000 us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 60000.000000 us hit, indicating a probable testbench issue
  UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_rma has 1 failures.
  - 0.rom_e2e_jtag_inject_rma.90072594166248220259023289384112754784333913970521093866214887480194598830799
    Line 745, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log
```
  UVM_FATAL @ 60000.000000 us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 60000.000000 us hit, indicating a probable testbench issue
  UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_uart_smoke_vseq.sv:24) [chip_sw_uart_smoke_vseq] wait timeout occurred! has 3 failures:
- Test chip_sw_uart_smoketest_signed has 3 failures.
  - 0.chip_sw_uart_smoketest_signed.2910630305322550404265939249394086456704288511190492659161499184475528669513
    Line 934, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_smoketest_signed/latest/run.log
```
  UVM_FATAL @ 10010.280001 us: (chip_sw_uart_smoke_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.chip_sw_uart_smoke_vseq] wait timeout occurred!
  UVM_INFO @ 10010.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_uart_smoketest_signed.91392368844003427819143854534813250562344951321824724389297867241067131894571
    Line 918, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_smoketest_signed/latest/run.log
```
  UVM_FATAL @ 10010.360001 us: (chip_sw_uart_smoke_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.chip_sw_uart_smoke_vseq] wait timeout occurred!
  UVM_INFO @ 10010.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits * and * set in filter status, got status * has 2 failures:
- Test chip_sw_pwrmgr_normal_sleep_all_wake_ups has 2 failures.
  - 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.22409237064479843303038121137598269267463869048962271635987403326385538769790
    Line 759, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log
```
  UVM_ERROR @ 6323.618792 us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits 5 and 8 set in filter status, got status 0x100
  UVM_INFO @ 6323.618792 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.40812911644542842826828255894107098247355696668686779408515249340750671642152
    Line 813, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log
```
  UVM_ERROR @ 6098.146616 us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits 5 and 8 set in filter status, got status 0x100
  UVM_INFO @ 6098.146616 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:178) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 2 failures:
- Test chip_sw_power_virus has 2 failures.
  - 0.chip_sw_power_virus.36616702808846777004976226689375558166403250863522021850124785681301719319613
    Line 992, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 5852.139817 us: (chip_sw_power_virus_vseq.sv:178) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 5852.139817 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_power_virus.102436526499372823961284194849881675894270199589380868502440324449835259518479
    Line 1034, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 5284.702376 us: (chip_sw_power_virus_vseq.sv:178) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 5284.702376 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 2 failures:

Test rom_raw_unlock has 2 failures.

0.rom_raw_unlock.115434793127041116741649737954200617764122369651144253440052214812251203781901
Line 750, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest/run.log

  UVM_ERROR @ 205452.578780 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns
  
  UVM_INFO @ 205452.578780 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.rom_raw_unlock.78416241490573383662889876202783304590708567343155534845563174063644215655241
Line 791, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.rom_raw_unlock/latest/run.log

  UVM_ERROR @ 205905.893280 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns
  
  UVM_INFO @ 205905.893280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 2 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 2 failures.
  - 7.chip_sw_alert_handler_lpg_sleep_mode_alerts.30957625231099744009531200486364500124666223100461874842160313381765156129031
    Line 811, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 4205.623016 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003718 MTVAL=40600800
  UVM_INFO @ 4205.623016 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 65.chip_sw_alert_handler_lpg_sleep_mode_alerts.77725628780364097861761636679096342204028274174357119638215109108306355046176
    Line 952, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 4160.010736 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003718 MTVAL=40600800
  UVM_INFO @ 4160.010736 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(rst_sys_req[*] || rst_sys_src_n[*])' has 1 failures:
- Test chip_sw_pwrmgr_main_power_glitch_reset has 1 failures.
  - 0.chip_sw_pwrmgr_main_power_glitch_reset.47944133516972694826593979685479955513109180593876982631013392020724200318099
    Line 847, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_main_power_glitch_reset/latest/run.log
```
      Offending '(rst_sys_req[1] || rst_sys_src_n[1])'
  UVM_ERROR @ 2408.791744 us: (pwrmgr_rstmgr_sva_if.sv:44) [ASSERT FAILED] SysHandshakeOff_A
  UVM_INFO @ 2408.791744 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 1 failures:
- Test rom_raw_unlock has 1 failures.
  - 1.rom_raw_unlock.13389741184499025269165645237180493950222256451128508179594969508762381470540
    Line 745, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_raw_unlock/latest/run.log
```
  UVM_ERROR @ 205572.544347 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 200000000 ns
  
  UVM_INFO @ 205572.544347 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job chip_earlgrey_asic-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test chip_csr_aliasing has 1 failures.
  - 2.chip_csr_aliasing.79439925591113985773374231605411392659299764006716406361461149619190506026304
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_csr_aliasing/latest/run.log
```
  Job ID: smart:5973c86c-ed36-40f4-ab09-aa04e742e24e
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:770) [chip_sw_lc_ctrl_scrap_vseq] Check failed (status_val) >> dummy.num() == * (* [*] vs * [*]) Unexpected status error b37c* has 1 failures:
- Test chip_sw_lc_ctrl_rand_to_scrap has 1 failures.
  - 2.chip_sw_lc_ctrl_rand_to_scrap.96544019929050351620551105538803383579697781106412772125544720722752507385078
    Line 749, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_ctrl_rand_to_scrap/latest/run.log
```
  UVM_ERROR @ 2923.567685 us: (chip_sw_base_vseq.sv:770) [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] Check failed (status_val) >> dummy.num() == 0 (45948 [0xb37c] vs 0 [0x0]) Unexpected status error b37c000
  UVM_INFO @ 2923.567685 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(pend_req[h2d.a_source].pend == *)' has 1 failures:
- Test chip_sw_pwrmgr_random_sleep_all_reset_reqs has 1 failures.
  - 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.38067615263660934783280121887076933112611517072753108393735013376038072618973
    Line 807, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log
```
      Offending '(pend_req[h2d.a_source].pend == 0)'
  UVM_ERROR @ 15327.345848 us: (tlul_assert.sv:268) [ASSERT FAILED] pendingReqPerSrc_M
  UVM_INFO @ 15327.345848 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 1 failures:
- Test chip_sw_all_escalation_resets has 1 failures.
  - 55.chip_sw_all_escalation_resets.24814448329473597373607207310892986903578954322568902238938897527805406220149
    Line 795, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/55.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2975.287008 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 2975.287008 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```