CHIP Simulation Results

Sunday May 26 2024 19:04:10 UTC

GitHub Revision: `2cf28c40e5`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 76231542290686940289653487239061276463019235878731279188279352215076078972419

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	4.593m	2.121ms	3	3	100.00
		chip_sw_example_rom	2.435m	3.077ms	3	3	100.00
		chip_sw_example_manufacturer	3.619m	2.321ms	3	3	100.00
		chip_sw_example_concurrency	4.608m	2.778ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset	6.508m	5.497ms	5	5	100.00
V1	csr_rw	chip_csr_rw	11.642m	5.959ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	1.463h	44.368ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	2.899h	73.423ms	4	5	80.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	2.009m	2.614ms	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	2.899h	73.423ms	4	5	80.00
		chip_csr_rw	11.642m	5.959ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	11.020s	259.502us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	9.249m	4.465ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	9.249m	4.465ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	9.249m	4.465ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	12.486m	4.665ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	12.486m	4.665ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	13.332m	4.269ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	12.746m	3.765ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	11.434m	4.536ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	47.078m	12.502ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	33.469m	8.877ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	21.226m	9.083ms	5	5	100.00
V1		TOTAL			199	220	90.45
V2	chip_pin_mux	chip_padctrl_attributes	6.461m	5.452ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	6.461m	5.452ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	4.897m	3.464ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	5.416m	3.391ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	6.558m	4.219ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	37.406m	18.571ms	5	5	100.00
		chip_tap_straps_testunlock0	12.431m	8.273ms	5	5	100.00
		chip_tap_straps_rma	13.425m	8.211ms	5	5	100.00
		chip_tap_straps_prod	14.360m	7.452ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	4.286m	2.353ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	24.030m	7.724ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	14.649m	5.758ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	14.649m	5.758ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	19.054m	6.522ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	40.211m	17.626ms	2	3	66.67
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	11.790m	3.775ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	21.095m	5.803ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.206h	18.345ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	3.851m	3.303ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	18.852m	6.635ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.058m	3.014ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	40.931m	13.542ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.415m	3.188ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.972m	4.368ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.898m	3.086ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	4.515m	3.633ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	15.294m	7.379ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	9.064m	5.028ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	4.952m	2.738ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	9.064m	5.028ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	6.047m	2.392ms	3	3	100.00
		chip_sw_aes_smoketest	6.277m	2.800ms	3	3	100.00
		chip_sw_aon_timer_smoketest	6.532m	3.053ms	3	3	100.00
		chip_sw_clkmgr_smoketest	5.619m	3.494ms	3	3	100.00
		chip_sw_csrng_smoketest	4.675m	2.888ms	3	3	100.00
		chip_sw_entropy_src_smoketest	10.368m	4.108ms	3	3	100.00
		chip_sw_gpio_smoketest	5.004m	2.874ms	3	3	100.00
		chip_sw_hmac_smoketest	7.053m	3.175ms	3	3	100.00
		chip_sw_kmac_smoketest	4.058m	2.743ms	3	3	100.00
		chip_sw_otbn_smoketest	42.752m	10.454ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	5.355m	3.052ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	6.407m	5.404ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	8.181m	5.820ms	3	3	100.00
		chip_sw_rv_plic_smoketest	5.006m	3.212ms	3	3	100.00
		chip_sw_rv_timer_smoketest	4.322m	2.649ms	3	3	100.00
		chip_sw_rstmgr_smoketest	4.082m	2.435ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	4.748m	3.502ms	3	3	100.00
		chip_sw_uart_smoketest	5.150m	3.258ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	9.954m	5.784ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.703h	77.683ms	2	3	66.67
V2	chip_sw_secure_boot	rom_e2e_smoke	1.164h	14.522ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	3.331m	4.540ms	0	3	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	10.875m	4.084ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	11.948m	9.314ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	5.218m	3.838ms	0	3	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.149h	64.197ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	8.008m	5.220ms	30	30	100.00
V2	tl_d_illegal_access	chip_tl_errors	8.008m	5.220ms	30	30	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	2.899h	73.423ms	4	5	80.00
		chip_same_csr_outstanding	1.360h	28.365ms	20	20	100.00
		chip_csr_hw_reset	6.508m	5.497ms	5	5	100.00
		chip_csr_rw	11.642m	5.959ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	2.899h	73.423ms	4	5	80.00
		chip_same_csr_outstanding	1.360h	28.365ms	20	20	100.00
		chip_csr_hw_reset	6.508m	5.497ms	5	5	100.00
		chip_csr_rw	11.642m	5.959ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.676m	2.585ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.460s	56.528us	100	100	100.00
		xbar_smoke_large_delays	2.017m	11.265ms	100	100	100.00
		xbar_smoke_slow_rsp	1.963m	6.518ms	100	100	100.00
		xbar_random_zero_delays	1.019m	643.876us	100	100	100.00
		xbar_random_large_delays	24.166m	120.045ms	100	100	100.00
		xbar_random_slow_rsp	22.618m	68.785ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.118m	1.534ms	100	100	100.00
		xbar_error_and_unmapped_addr	55.670s	1.238ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.518m	2.112ms	100	100	100.00
		xbar_error_and_unmapped_addr	55.670s	1.238ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.625m	4.008ms	100	100	100.00
		xbar_access_same_device_slow_rsp	53.700m	162.702ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.409m	2.637ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	17.144m	25.447ms	100	100	100.00
		xbar_stress_all_with_error	14.113m	19.094ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	22.309m	29.300ms	100	100	100.00
		xbar_stress_all_with_reset_error	16.465m	21.900ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	1.164h	14.522ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	59.283m	22.083ms	3	3	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	1.045h	14.243ms	3	3	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	55.979m	10.705ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	1.076h	13.703ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	55.828m	14.634ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	1.016h	13.960ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	1.212h	14.436ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	56.512m	10.399ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	58.396m	14.119ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	1.128h	14.486ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	55.971m	14.602ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	56.540m	14.422ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	1.414h	17.842ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	1.581h	22.378ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	1.860h	22.795ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	1.468h	23.140ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	1.695h	21.964ms	1	1	100.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	1.512h	17.238ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	1.613h	21.641ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	1.931h	21.158ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	1.496h	21.548ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	1.273h	22.516ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	54.812m	10.497ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	59.564m	13.404ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	53.707m	13.917ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	1.104h	13.489ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	1.041h	13.425ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	50.640m	10.026ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	1.251h	13.910ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	53.924m	13.384ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	52.628m	12.913ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	48.196m	13.557ms	1	1	100.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	46.434m	11.213ms	3	3	100.00
		rom_e2e_asm_init_dev	1.101h	14.451ms	3	3	100.00
		rom_e2e_asm_init_prod	1.171h	14.097ms	3	3	100.00
		rom_e2e_asm_init_prod_end	54.625m	14.719ms	3	3	100.00
		rom_e2e_asm_init_rma	1.332h	14.176ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	1.024h	15.073ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	1.226h	14.293ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	1.218h	14.273ms	3	3	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	1.092h	20.018ms	0	3	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	7.007m	3.732ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	3.851m	3.303ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.695m	3.158ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.880m	2.907ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	38.120m	10.608ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.906m	18.387ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.906m	18.387ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	7.625m	3.886ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	6.407m	5.404ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	7.625m	3.886ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	16.275m	7.371ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	16.275m	7.371ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	10.028m	7.525ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	13.792m	5.548ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	17.279m	5.499ms	3	3	100.00
		chip_sw_aes_idle	4.880m	2.907ms	3	3	100.00
		chip_sw_hmac_enc_idle	5.746m	2.933ms	3	3	100.00
		chip_sw_kmac_idle	5.109m	2.720ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	9.549m	4.686ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	8.116m	5.609ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	10.876m	4.449ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	9.399m	4.812ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	29.245m	10.155ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.853m	3.914ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.315m	4.878ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.961m	4.235ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.173m	4.677ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.856m	4.192ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	14.088m	4.857ms	3	3	100.00
		chip_sw_ast_clk_outputs	19.054m	6.522ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	3.610m	3.875ms	0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.961m	4.235ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.173m	4.677ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	11.790m	3.775ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	21.095m	5.803ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.206h	18.345ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	3.851m	3.303ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	18.852m	6.635ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.058m	3.014ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	40.931m	13.542ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.415m	3.188ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.972m	4.368ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.898m	3.086ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.699m	2.570ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	13.038m	5.489ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	21.026m	7.431ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.161h	24.890ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	5.330m	3.192ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	4.649m	3.209ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	36.531m	12.431ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	5.868m	3.411ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	11.554m	5.656ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	42.471m	25.292ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	1.166h	28.941ms	1	3	33.33
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	19.054m	6.522ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	11.257m	4.358ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	8.468m	3.227ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	14.222m	4.949ms	98	100	98.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	37.084m	8.507ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	23.228m	6.365ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	9.407m	5.414ms	3	3	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	16.118m	5.745ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	5.690m	2.645ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	18.306m	6.494ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	29.327m	21.565ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	7.058m	3.044ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	41.900s	10.200us	0	3	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	12.294m	4.635ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	29.327m	21.565ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	29.327m	21.565ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	58.408m	20.099ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	58.408m	20.099ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	9.664m	5.487ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.906m	18.387ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	2.235h	34.322ms	10	10	100.00
		chip_sw_entropy_src_ast_rng_req	4.422m	2.595ms	3	3	100.00
		chip_sw_edn_entropy_reqs	19.859m	6.635ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	4.422m	2.595ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	23.228m	6.365ms	3	3	100.00
V2	chip_sw_entropy_src_fuse_en_fw_read	chip_sw_entropy_src_fuse_en_fw_read_test			0	0	--
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	5.681m	2.925ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	38.986m	21.353ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	19.902m	4.950ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	21.095m	5.803ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	12.127m	4.195ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	11.790m	3.775ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	6.543m	4.694ms	0	3	0.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	38.986m	21.353ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	7.128m	3.223ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	30.908m	10.710ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.048m	3.161ms	0	3	0.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	6.543m	4.694ms	0	3	0.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.048m	3.161ms	0	3	0.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.048m	3.161ms	0	3	0.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	5.048m	3.161ms	0	3	0.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.048m	3.161ms	0	3	0.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	14.222m	4.949ms	98	100	98.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	8.322m	13.220ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	20.830m	5.883ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	12.167m	5.045ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	12.167m	5.045ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	5.392m	3.060ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.058m	3.014ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.746m	2.933ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	14.110m	5.194ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	14.573m	5.049ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	14.848m	5.437ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	13.936m	3.992ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	30.908m	10.710ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	40.931m	13.542ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	37.264m	10.322ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	38.120m	10.608ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.101h	16.839ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	5.815m	2.623ms	3	3	100.00
		chip_sw_kmac_mode_kmac	6.773m	3.398ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.415m	3.188ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	30.908m	10.710ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	4.346m	4.254ms	0	15	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	4.086m	2.619ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.377m	2.666ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	5.109m	2.720ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	9.025m	5.066ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	37.406m	18.571ms	5	5	100.00
		chip_tap_straps_rma	13.425m	8.211ms	5	5	100.00
		chip_tap_straps_prod	14.360m	7.452ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	4.444m	2.545ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	4.346m	4.254ms	0	15	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	4.346m	4.254ms	0	15	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	4.346m	4.254ms	0	15	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	34.502m	10.253ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	5.048m	3.161ms	0	3	0.00
		chip_sw_flash_rma_unlocked	6.543m	4.694ms	0	3	0.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.389m	4.223ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	22.518m	7.146ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	22.732m	8.488ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	20.818m	8.525ms	3	3	100.00
		chip_sw_lc_ctrl_transition	4.346m	4.254ms	0	15	0.00
		chip_sw_keymgr_key_derivation	30.908m	10.710ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	9.886m	8.248ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	20.022m	9.840ms	3	3	100.00
		chip_prim_tl_access	8.322m	13.220ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	3.610m	3.875ms	0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.853m	3.914ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.315m	4.878ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.961m	4.235ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.173m	4.677ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.856m	4.192ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	14.088m	4.857ms	3	3	100.00
		chip_tap_straps_dev	37.406m	18.571ms	5	5	100.00
		chip_tap_straps_rma	13.425m	8.211ms	5	5	100.00
		chip_tap_straps_prod	14.360m	7.452ms	5	5	100.00
		chip_rv_dm_lc_disabled	6.236m	14.510ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.486m	3.405ms	0	1	0.00
		chip_sw_lc_ctrl_raw_to_scrap	2.693m	3.813ms	0	1	0.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.408m	4.324ms	0	1	0.00
		chip_sw_lc_ctrl_rand_to_scrap	8.569m	4.462ms	0	3	0.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	3.886m	4.158ms	0	3	0.00
		chip_rv_dm_lc_disabled	6.236m	14.510ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	3.423m	4.175ms	0	3	0.00
		chip_sw_lc_walkthrough_prod	3.307m	4.182ms	0	3	0.00
		chip_sw_lc_walkthrough_prodend	3.580m	3.013ms	0	3	0.00
		chip_sw_lc_walkthrough_rma	3.074m	4.324ms	0	3	0.00
		chip_sw_lc_walkthrough_testunlocks	3.886m	4.158ms	0	3	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	3.410m	4.084ms	0	3	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	3.236m	3.083ms	0	3	0.00
		rom_volatile_raw_unlock	2.669m	3.167ms	0	3	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	4.346m	4.254ms	0	15	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	38.986m	21.353ms	3	3	100.00
		chip_sw_otbn_mem_scramble	10.211m	3.318ms	3	3	100.00
		chip_sw_keymgr_key_derivation	30.908m	10.710ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	12.274m	5.555ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	6.108m	3.231ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	38.986m	21.353ms	3	3	100.00
		chip_sw_otbn_mem_scramble	10.211m	3.318ms	3	3	100.00
		chip_sw_keymgr_key_derivation	30.908m	10.710ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	12.274m	5.555ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	6.108m	3.231ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	4.346m	4.254ms	0	15	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	16.290m	14.968ms	0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	4.444m	2.545ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.389m	4.223ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	22.518m	7.146ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	22.732m	8.488ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	20.818m	8.525ms	3	3	100.00
		chip_sw_lc_ctrl_transition	4.346m	4.254ms	0	15	0.00
		chip_prim_tl_access	8.322m	13.220ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	8.322m	13.220ms	3	3	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	11.820m	9.500ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	31.658m	22.556ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	7.066m	7.143ms	2	3	66.67
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	14.252m	8.292ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	13.879m	7.553ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	34.033m	21.517ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	27.308m	16.477ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	16.275m	7.371ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	24.620m	10.758ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	14.250m	5.036ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	11.820m	9.500ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	6.632m	3.497ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	1.135h	28.363ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	9.566m	5.711ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	9.639m	4.696ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	46.279m	27.291ms	3	3	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	18.306m	6.494ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	26.044m	10.067ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	46.862m	25.269ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	4.918m	2.933ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	14.222m	4.949ms	98	100	98.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	9.886m	8.248ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	9.886m	8.248ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	26.044m	10.067ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	46.279m	27.291ms	3	3	100.00
		chip_sw_pwrmgr_wdog_reset	14.250m	5.036ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	6.407m	5.404ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	7.192m	4.284ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	11.259m	5.042ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	8.060m	4.787ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	31.857m	14.685ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	5.890m	3.368ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	14.222m	4.949ms	98	100	98.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	29.154m	6.703ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	21.278m	5.795ms	3	3	100.00
		chip_plic_all_irqs_10	11.148m	4.328ms	3	3	100.00
		chip_plic_all_irqs_20	14.570m	4.190ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	5.894m	3.422ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	4.487m	3.129ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	1.164h	14.522ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	14.067m	7.684ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	10.792m	4.379ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	7.375m	3.363ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	5.067m	2.634ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	12.274m	5.555ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.972m	4.368ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	13.573m	8.019ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	11.222m	7.723ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	20.022m	9.840ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	14.222m	4.949ms	98	100	98.00
		chip_sw_data_integrity_escalation	14.649m	5.758ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	3.236m	2.600ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	4.170m	3.094ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	8.487m	3.792ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	10.127m	3.761ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	29.403m	8.177ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.735h	31.546ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	53.237m	11.512ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	5.627m	2.896ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	9.025m	5.066ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	14.222m	4.949ms	98	100	98.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	5.203m	3.387ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	31.857m	14.685ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	10.175m	5.971ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	8.796m	4.310ms	90	90	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	27.159m	10.575ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	37.084m	8.507ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	29.154m	6.703ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.626h	255.680ms	3	3	100.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	44.073m	18.006ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	27.819m	13.309ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	7.192m	4.284ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	10.270m	4.116ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	9.996m	4.093ms	0	3	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	13.425m	8.211ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	6.236m	14.510ms	3	3	100.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			2555	2634	97.00
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	7.239m	3.121ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark			0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	15.133m	5.168ms	0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	1.673m	2.470ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.678m	2.412ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.933m	2.341ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	1.187h	57.559ms	0	1	0.00
		rom_e2e_jtag_inject_dev	1.091h	57.087ms	0	1	0.00
		rom_e2e_jtag_inject_rma	1.000h	58.561ms	0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash			0	0	--
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	6.549m	3.244ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	10.742m	3.380ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	25.308m	6.954ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	33.227m	8.878ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	12.891m	3.154ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	21.073m	5.414ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	//sw/device/tests:i2c_host_override_test			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	4.951m	3.279ms	0	3	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	12.167m	5.671ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	9.769m	5.831ms	3	3	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	10.184m	4.976ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	26.044m	10.067ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	14.222m	4.949ms	98	100	98.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	//sw/device/tests:spi_passthru_test			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	//sw/device/tests:spi_passthru_test			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	12.486m	4.665ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.185h	19.333ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	1.673m	2.470ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.678m	2.412ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.933m	2.341ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.053m	6.193ms	3	3	100.00
V3		TOTAL			29	45	64.44
	Unmapped tests	chip_sival_flash_info_access	5.361m	3.749ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	13.615m	4.937ms	3	3	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	4.644m	2.602ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	1.042h	17.145ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	16.261m	5.534ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	15.194m	4.945ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	9.114m	5.707ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	5.156m	2.604ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	2.433m	2.045ms	3	3	100.00
		chip_sw_flash_ctrl_write_clear	6.620m	3.653ms	3	3	100.00
		TOTAL			2816	2932	96.04

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	10	10	10	100.00
V1	18	18	16	88.89
V2	281	266	239	85.05
V2S	1	1	1	100.00
V3	90	21	11	12.22

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.45	95.51	94.13	92.03	--	94.96	96.47	99.59

Failure Buckets

UVM_ERROR @ * us: (cip_base_vseq.sv:829) [chip_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test chip_csr_mem_rw_with_rand_reset has 20 failures.
  - 0.chip_csr_mem_rw_with_rand_reset.58130283878469297528564261896940263871834292893241799616088602156372978810695
    Line 374, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2166.493568 us: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2166.493568 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_csr_mem_rw_with_rand_reset.36969768480588374002743704362740612059783321403641033579338711755573376577219
    Line 373, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1790.974961 us: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1790.974961 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.

UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_lc_ctrl_transition_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 18 failures:

Test chip_sw_lc_ctrl_transition has 15 failures.

0.chip_sw_lc_ctrl_transition.90865844338651903306207366350415427679052073284666783458276109437112599808498
Line 776, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_transition/latest/run.log

  UVM_FATAL @ 4135.676403 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_transition_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4135.676403 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_ctrl_transition.81738770461848876917467460310050311235763579849546272166850334370206244906973
Line 732, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_transition/latest/run.log

  UVM_FATAL @ 3352.795517 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_transition_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3352.795517 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 13 more failures.

Test chip_sw_clkmgr_external_clk_src_for_lc has 3 failures.

0.chip_sw_clkmgr_external_clk_src_for_lc.7740662458910746381142973172050973610985525234964639409613567489350370726926
Line 750, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_lc/latest/run.log

  UVM_FATAL @ 3874.547708 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_transition_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3874.547708 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_clkmgr_external_clk_src_for_lc.2115880137794788201864948462134017679543887881135603873201470195956446643136
Line 757, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_lc/latest/run.log

  UVM_FATAL @ 4026.559120 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_transition_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4026.559120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_lc_walkthrough_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 12 failures:

Test chip_sw_lc_walkthrough_dev has 3 failures.

0.chip_sw_lc_walkthrough_dev.94432684938739597595029210731404595361395371680194546759546500028985287650655
Line 871, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_dev/latest/run.log

  UVM_FATAL @ 3927.070317 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3927.070317 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_walkthrough_dev.64625580525164773667656653687163077554866676704169144044416409444937891721925
Line 764, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_dev/latest/run.log

  UVM_FATAL @ 4175.404094 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4175.404094 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_lc_walkthrough_prod has 3 failures.

0.chip_sw_lc_walkthrough_prod.60842219106531212769930710724891914977968966176103691766700510018174678176745
Line 842, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prod/latest/run.log

  UVM_FATAL @ 5094.643360 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 5094.643360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_walkthrough_prod.106349259382114200041262729848248493903053714450101530451882998384803795438238
Line 724, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_prod/latest/run.log

  UVM_FATAL @ 4787.381709 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4787.381709 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_lc_walkthrough_prodend has 3 failures.

0.chip_sw_lc_walkthrough_prodend.3548834427498928583992154175322041051579683182511378262059255178134619800497
Line 801, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prodend/latest/run.log

  UVM_FATAL @ 4109.625966 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4109.625966 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_walkthrough_prodend.27904231289933993335338388401198754303006101561085990701875290381421789946695
Line 756, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_prodend/latest/run.log

  UVM_FATAL @ 3013.010165 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3013.010165 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_lc_walkthrough_rma has 3 failures.

0.chip_sw_lc_walkthrough_rma.70554957467037849116665618632128470623923873167249606152053414378677204787553
Line 814, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_rma/latest/run.log

  UVM_FATAL @ 3521.972993 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3521.972993 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_walkthrough_rma.23887233324548130989392427068264659188878268522444360073854578547224373856722
Line 798, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_rma/latest/run.log

  UVM_FATAL @ 4324.403958 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4324.403958 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 10 failures:
- Test chip_sw_rv_timer_systick_test has 3 failures.
  - 0.chip_sw_rv_timer_systick_test.2095592299326562263688422891477681015200313033291641892408270269946219534663
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:d2fe3768-8c3c-454f-91ef-092f61d5dcfc
```
  - 1.chip_sw_rv_timer_systick_test.17722531470967083372859872591951818246529539320374914435106974247016095194289
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:ca5ef2b4-ba38-40b8-87c0-3ec21eb56acd
```
  - ... and 1 more failures.
- Test chip_sw_coremark has 1 failures.
  - 0.chip_sw_coremark.43004340041514489342347758417000598124177467576580506106133392260721586319271
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
```
  Job ID: smart:67ad4bf4-eb4c-4f6c-96bf-353f5bf92edf
```
- Test chip_sw_csrng_edn_concurrency_reduced_freq has 2 failures.
  - 0.chip_sw_csrng_edn_concurrency_reduced_freq.61665262995007431133916926174487595406985500806522647204335665605476850591960
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest/run.log
```
  Job ID: smart:4db3e75a-5588-40d3-b029-dfcc45a4ba4a
```
  - 1.chip_sw_csrng_edn_concurrency_reduced_freq.93822879798536798841566592729667944270457867528468312258820641015841622176386
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest/run.log
```
  Job ID: smart:8a282b58-391a-40a0-9f36-241b0ecc62b5
```
- Test chip_sw_power_virus has 2 failures.
  - 0.chip_sw_power_virus.110218065353782182591414908612695896677188319720534126787209682837205314042740
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:4a8f707e-098f-448f-9c5a-3daa50df234a
```
  - 1.chip_sw_power_virus.95852706586768759583071364769406736409336916479368260443398974329540977754521
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:8cc22097-90e5-4b09-901e-2349ba86469e
```
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 1.chip_sw_ast_clk_rst_inputs.8016120989655215944466928894203646153877064946442220777100438805100243535826
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:55ee7d19-54e8-40b5-8665-cac616069a77
```
- ... and 1 more tests.

UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 9 failures:

Test chip_sw_lc_ctrl_volatile_raw_unlock has 3 failures.

0.chip_sw_lc_ctrl_volatile_raw_unlock.49296544050029531099830982168168421298041952166268763681535708391082978414289
Line 798, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest/run.log

  UVM_FATAL @ 4723.625814 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4723.625814 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_ctrl_volatile_raw_unlock.26051517569331975751201901854253606007882739632648978978073356578907561690302
Line 780, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest/run.log

  UVM_FATAL @ 3171.893557 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3171.893557 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz has 3 failures.

0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.38718184572492561549534177106825923563732660462079248516351920606394072101630
Line 801, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest/run.log

  UVM_FATAL @ 4824.472886 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4824.472886 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.84804128440477915009053557439122037677995069415052086857877064559631705493825
Line 830, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest/run.log

  UVM_FATAL @ 3082.879807 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3082.879807 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test rom_volatile_raw_unlock has 3 failures.

0.rom_volatile_raw_unlock.67424193504605567016230400709611983621939127804387603373614907309215437887698
Line 766, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_volatile_raw_unlock/latest/run.log

  UVM_FATAL @ 3386.816879 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3386.816879 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.rom_volatile_raw_unlock.59660378572738766829081020513018086554277635990044038969307775017370537109279
Line 865, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_volatile_raw_unlock/latest/run.log

  UVM_FATAL @ 3166.797921 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3166.797921 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 6 failures:

Test chip_sw_lc_ctrl_rma_to_scrap has 1 failures.

0.chip_sw_lc_ctrl_rma_to_scrap.100131812204146377435549197326707884150198746349977611835774077261288707207734
Line 739, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_rma_to_scrap/latest/run.log

  UVM_FATAL @ 3404.890207 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3404.890207 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_lc_ctrl_raw_to_scrap has 1 failures.

0.chip_sw_lc_ctrl_raw_to_scrap.22513177548960771134863463388835187775090543271328926282008746133324024789599
Line 794, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_raw_to_scrap/latest/run.log

  UVM_FATAL @ 3812.812555 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3812.812555 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_lc_ctrl_test_locked0_to_scrap has 1 failures.

0.chip_sw_lc_ctrl_test_locked0_to_scrap.41738752641356602132390766845156465212098022470774817767924840113847144288237
Line 836, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest/run.log

  UVM_FATAL @ 4324.469288 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4324.469288 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_lc_ctrl_rand_to_scrap has 3 failures.

0.chip_sw_lc_ctrl_rand_to_scrap.52940807211756615730775179689578471738386585191666181008663201331025336359760
Line 823, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_rand_to_scrap/latest/run.log

  UVM_FATAL @ 4461.835751 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4461.835751 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_ctrl_rand_to_scrap.107728248351538672343401221862333223361171570807044606623388005506889736267133
Line 743, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_rand_to_scrap/latest/run.log

  UVM_FATAL @ 3164.017489 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3164.017489 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_exit_test_unlocked_bootstrap_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 3 failures:
- Test chip_sw_exit_test_unlocked_bootstrap has 3 failures.
  - 0.chip_sw_exit_test_unlocked_bootstrap.106717616800686497380399393621623876641584345358611799549258173745477683854635
    Line 738, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_exit_test_unlocked_bootstrap/latest/run.log
```
  UVM_FATAL @ 3413.141414 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_exit_test_unlocked_bootstrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3413.141414 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_exit_test_unlocked_bootstrap.76437923179272415985198242302205288733425211161846013484606533595346800125366
    Line 781, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_exit_test_unlocked_bootstrap/latest/run.log
```
  UVM_FATAL @ 3463.425302 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_exit_test_unlocked_bootstrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3463.425302 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c:101)] DIF-fail: dif_keymgr_advance_state(keymgr, params) returns * has 3 failures:
- Test chip_sw_flash_ctrl_lc_rw_en has 3 failures.
  - 0.chip_sw_flash_ctrl_lc_rw_en.102674775427190053210327841420544864847945867566523371481111607426615344814713
    Line 757, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_lc_rw_en/latest/run.log
```
  UVM_ERROR @ 3161.407918 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c:101)] DIF-fail: dif_keymgr_advance_state(keymgr, params) returns 3
  UVM_INFO @ 3161.407918 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_flash_ctrl_lc_rw_en.99106964322188783904167812102416751569613506985281765056283322635231146055183
    Line 813, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_lc_rw_en/latest/run.log
```
  UVM_ERROR @ 2498.695564 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c:101)] DIF-fail: dif_keymgr_advance_state(keymgr, params) returns 3
  UVM_INFO @ 2498.695564 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_flash_rma_unlocked_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 3 failures:
- Test chip_sw_flash_rma_unlocked has 3 failures.
  - 0.chip_sw_flash_rma_unlocked.79044628324621421353434743379592817233517484185558159901682459219787524789865
    Line 725, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_rma_unlocked/latest/run.log
```
  UVM_FATAL @ 3934.204721 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_flash_rma_unlocked_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3934.204721 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_flash_rma_unlocked.111809728940648778916193282372826106146818563662334221428345618754885141491723
    Line 729, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_rma_unlocked/latest/run.log
```
  UVM_FATAL @ 4693.996330 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_flash_rma_unlocked_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4693.996330 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_otp_ctrl_vendor_test_csr_access_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 3 failures:
- Test chip_sw_otp_ctrl_vendor_test_csr_access has 3 failures.
  - 0.chip_sw_otp_ctrl_vendor_test_csr_access.4459901012859417117487663856230988322650116728645255458427043279903140450277
    Line 817, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest/run.log
```
  UVM_FATAL @ 3921.933244 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_otp_ctrl_vendor_test_csr_access_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3921.933244 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_otp_ctrl_vendor_test_csr_access.94175778653674990889664641999414361191754634314621271863871239055992374992582
    Line 790, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest/run.log
```
  UVM_FATAL @ 4795.674850 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_otp_ctrl_vendor_test_csr_access_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4795.674850 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_lc_walkthrough_testunlocks_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 3 failures:
- Test chip_sw_lc_walkthrough_testunlocks has 3 failures.
  - 0.chip_sw_lc_walkthrough_testunlocks.24933788908427055206565361767131610593191133509937323962502710042367040167872
    Line 795, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_testunlocks/latest/run.log
```
  UVM_FATAL @ 3346.793788 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_testunlocks_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3346.793788 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_lc_walkthrough_testunlocks.103511334765954417627128369781918198042980819270628052087084501101182042269156
    Line 733, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_testunlocks/latest/run.log
```
  UVM_FATAL @ 3372.834608 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_testunlocks_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3372.834608 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat" has 3 failures:
- Test chip_sw_sysrst_ctrl_outputs has 3 failures.
  - 0.chip_sw_sysrst_ctrl_outputs.35069123044142482731048575252199824445045750204064285797898392603115499771146
    Line 767, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_sysrst_ctrl_outputs.24950713253458336514285883458763032516647577914882352153546599158238296162841
    Line 806, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.280001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:
- Test chip_sw_lc_ctrl_program_error has 3 failures.
  - 0.chip_sw_lc_ctrl_program_error.75945977328619600577626249717145249478146262240209656151896373318711203174177
    Line 868, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 14967.522396 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 14967.522396 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.chip_sw_lc_ctrl_program_error.42448822484353670813905960497244622532552840697258822597815127012977155602977
    Line 773, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 15169.472140 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 15169.472140 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep. has 3 failures:
- Test chip_sw_rv_dm_access_after_wakeup has 3 failures.
  - 0.chip_sw_rv_dm_access_after_wakeup.41473424939791798187946201124454172880314489443655611073133036569263692915004
    Line 748, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3953.767128 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3953.767128 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_rv_dm_access_after_wakeup.26890597776034949948916324349333728330504955540913376521914993181665389768615
    Line 818, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3571.716425 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3571.716425 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.108227576850551600217872373884485161159951450913252130486484324295207452326686
    Line 747, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 2469.884500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2469.884500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.30453171485362173503915948866665453936648926755148474015829715838086788616005
    Line 745, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 2411.831500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2411.831500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.39066899378564862829592853964964899964009774575735271116546566425614942565571
    Line 745, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 2340.709000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2340.709000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 3 failures:
- Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_inject_test_unlocked0.61308213403233139837391193400299411608609653500552253708781724906673728488924
    Line 870, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 57558.883940 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 57558.883940 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_dev has 1 failures.
  - 0.rom_e2e_jtag_inject_dev.78786123060792600123602676715184915489558696873347680379660967427723290966930
    Line 809, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log
```
  UVM_FATAL @ 57087.084593 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 57087.084593 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_rma has 1 failures.
  - 0.rom_e2e_jtag_inject_rma.4986229698897957623117363631465960022631755078485111903394015596939962756445
    Line 787, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log
```
  UVM_FATAL @ 58560.652599 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 58560.652599 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 3 failures:
- Test rom_e2e_static_critical has 3 failures.
  - 0.rom_e2e_static_critical.103083128211590883581561216244570387077160228343549037230476281079508439737787
    Line 800, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_static_critical/latest/run.log
```
  UVM_ERROR @ 20018.285257 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 20000000 ns
  
  UVM_INFO @ 20018.285257 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.rom_e2e_static_critical.108602349787127985863265077664622644797582155261985934217329937031144926204806
    Line 935, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_static_critical/latest/run.log
```
  UVM_ERROR @ 20015.239434 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 20000000 ns
  
  UVM_INFO @ 20015.239434 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.

UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_lc_raw_unlock_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 3 failures:

Test rom_raw_unlock has 3 failures.

0.rom_raw_unlock.67354318907388805625638102123743815773746038264344867519564829685427141282641
Line 788, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest/run.log

  UVM_FATAL @ 4540.410752 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4540.410752 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.rom_raw_unlock.67706525549883841367508181696112514369973660057192604708263874795768606900687
Line 757, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_raw_unlock/latest/run.log

  UVM_FATAL @ 3782.079661 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3782.079661 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 2 failures:
- Test chip_sw_all_escalation_resets has 2 failures.
  - 28.chip_sw_all_escalation_resets.22247456958046937417449233782469513271493134965319032078258981315392232672369
    Line 829, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/28.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3231.081800 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 3231.081800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 73.chip_sw_all_escalation_resets.61993139990278058646378480427236894285758949932781606289280850770803455974525
    Line 783, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/73.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3040.185236 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 3040.185236 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits * and * set in filter status, got status * has 1 failures:
- Test chip_sw_pwrmgr_normal_sleep_all_wake_ups has 1 failures.
  - 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.41496118030862264025777105119102725719113739504208407900058382250972443090527
    Line 768, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log
```
  UVM_ERROR @ 5776.020168 us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits 5 and 8 set in filter status, got status 0x100
  UVM_INFO @ 5776.020168 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:178) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 2.chip_sw_power_virus.81144215022335894601428894463170438670931321231791365164791400852114026332323
    Line 1090, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 5167.803866 us: (chip_sw_power_virus_vseq.sv:178) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 5167.803866 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job chip_earlgrey_asic-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test chip_csr_aliasing has 1 failures.
  - 4.chip_csr_aliasing.36711383643835680293272685237139111099902987450815758932160673588603027369350
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/4.chip_csr_aliasing/latest/run.log
```
  Job ID: smart:dae9561a-2e09-48ba-8890-674e55f6827f
```