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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.13 95.57 94.38 95.52 95.30 96.47 99.58


Total test records in report: 2874
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T893 /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.309576589 May 30 04:33:29 PM PDT 24 May 30 04:40:43 PM PDT 24 5208796369 ps
T652 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.431176235 May 30 04:16:30 PM PDT 24 May 30 04:18:33 PM PDT 24 1940297397 ps
T359 /workspace/coverage/default/1.chip_sival_flash_info_access.3811899023 May 30 04:13:41 PM PDT 24 May 30 04:18:50 PM PDT 24 3496937172 ps
T894 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.1939954046 May 30 04:09:31 PM PDT 24 May 30 04:21:23 PM PDT 24 4262629170 ps
T895 /workspace/coverage/default/1.chip_sw_edn_sw_mode.1264548039 May 30 04:18:41 PM PDT 24 May 30 04:42:55 PM PDT 24 6686377288 ps
T222 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.3707801090 May 30 04:11:21 PM PDT 24 May 30 04:44:31 PM PDT 24 22064374038 ps
T135 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2977894005 May 30 04:10:22 PM PDT 24 May 30 04:19:10 PM PDT 24 6742566104 ps
T896 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.2218822636 May 30 04:27:00 PM PDT 24 May 30 04:37:43 PM PDT 24 5190278084 ps
T897 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.4196160931 May 30 04:19:18 PM PDT 24 May 30 04:38:27 PM PDT 24 7855520482 ps
T898 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.3503416941 May 30 04:25:35 PM PDT 24 May 30 04:49:15 PM PDT 24 7743904950 ps
T439 /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.289435210 May 30 04:41:20 PM PDT 24 May 30 04:48:01 PM PDT 24 3631612706 ps
T429 /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.2019227852 May 30 04:16:13 PM PDT 24 May 30 04:19:58 PM PDT 24 2830792728 ps
T444 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2024114657 May 30 04:36:25 PM PDT 24 May 30 04:44:32 PM PDT 24 3039887650 ps
T140 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.2403334892 May 30 04:26:50 PM PDT 24 May 30 05:20:51 PM PDT 24 16473302208 ps
T107 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3730247286 May 30 04:28:03 PM PDT 24 May 30 04:39:58 PM PDT 24 5009173640 ps
T250 /workspace/coverage/default/56.chip_sw_all_escalation_resets.594171910 May 30 04:40:14 PM PDT 24 May 30 04:49:32 PM PDT 24 6309093818 ps
T30 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.3976098009 May 30 04:32:26 PM PDT 24 May 30 04:38:12 PM PDT 24 4748043516 ps
T162 /workspace/coverage/default/97.chip_sw_all_escalation_resets.3168478625 May 30 04:44:19 PM PDT 24 May 30 04:53:35 PM PDT 24 4635541754 ps
T899 /workspace/coverage/default/1.rom_e2e_asm_init_prod.2642140459 May 30 04:29:39 PM PDT 24 May 30 05:20:45 PM PDT 24 14695305203 ps
T745 /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.1361175647 May 30 04:37:28 PM PDT 24 May 30 04:44:22 PM PDT 24 3404982296 ps
T741 /workspace/coverage/default/0.chip_sw_all_escalation_resets.896873177 May 30 04:08:59 PM PDT 24 May 30 04:21:04 PM PDT 24 5462663250 ps
T141 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.526998029 May 30 04:27:39 PM PDT 24 May 30 05:25:47 PM PDT 24 18669082852 ps
T209 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.3273090887 May 30 04:17:06 PM PDT 24 May 30 04:26:42 PM PDT 24 4244392600 ps
T900 /workspace/coverage/default/70.chip_sw_all_escalation_resets.802552954 May 30 04:42:47 PM PDT 24 May 30 04:52:59 PM PDT 24 5217112620 ps
T901 /workspace/coverage/default/2.chip_sw_example_manufacturer.3308631054 May 30 04:25:13 PM PDT 24 May 30 04:29:38 PM PDT 24 3089006632 ps
T148 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.143071561 May 30 04:09:55 PM PDT 24 May 30 04:20:53 PM PDT 24 5666859782 ps
T753 /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3354502718 May 30 04:41:23 PM PDT 24 May 30 04:48:07 PM PDT 24 4552267750 ps
T76 /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.1499673692 May 30 04:07:58 PM PDT 24 May 30 07:20:26 PM PDT 24 58830219256 ps
T902 /workspace/coverage/default/0.chip_sw_kmac_idle.1590722307 May 30 04:13:08 PM PDT 24 May 30 04:18:21 PM PDT 24 3237699140 ps
T179 /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.700780624 May 30 04:17:43 PM PDT 24 May 30 05:47:09 PM PDT 24 43772295660 ps
T336 /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.1682350302 May 30 04:24:53 PM PDT 24 May 30 04:36:05 PM PDT 24 4094071264 ps
T903 /workspace/coverage/default/0.chip_sw_aes_smoketest.815929566 May 30 04:14:15 PM PDT 24 May 30 04:19:26 PM PDT 24 2990666474 ps
T738 /workspace/coverage/default/94.chip_sw_all_escalation_resets.3932240959 May 30 04:42:43 PM PDT 24 May 30 04:51:11 PM PDT 24 5519688768 ps
T904 /workspace/coverage/default/21.chip_sw_all_escalation_resets.4179997097 May 30 04:36:20 PM PDT 24 May 30 04:47:28 PM PDT 24 5738184888 ps
T232 /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.2937937753 May 30 04:23:50 PM PDT 24 May 30 05:00:53 PM PDT 24 12304037608 ps
T671 /workspace/coverage/default/78.chip_sw_all_escalation_resets.1236962791 May 30 04:41:36 PM PDT 24 May 30 04:51:36 PM PDT 24 5492133104 ps
T905 /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.3381083125 May 30 04:19:44 PM PDT 24 May 30 04:27:00 PM PDT 24 3426776400 ps
T100 /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.227511436 May 30 04:23:46 PM PDT 24 May 30 05:01:27 PM PDT 24 17901327393 ps
T146 /workspace/coverage/default/0.chip_plic_all_irqs_10.106567894 May 30 04:11:46 PM PDT 24 May 30 04:20:29 PM PDT 24 3874598186 ps
T14 /workspace/coverage/default/1.chip_sw_sleep_pin_retention.2102088838 May 30 04:14:22 PM PDT 24 May 30 04:18:45 PM PDT 24 2572246968 ps
T327 /workspace/coverage/default/0.chip_plic_all_irqs_20.2089444832 May 30 04:13:53 PM PDT 24 May 30 04:27:14 PM PDT 24 4405277176 ps
T649 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2748248125 May 30 04:11:49 PM PDT 24 May 30 04:19:04 PM PDT 24 5080464884 ps
T388 /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3089969479 May 30 04:36:55 PM PDT 24 May 30 04:41:29 PM PDT 24 3936605960 ps
T446 /workspace/coverage/default/0.chip_sw_power_idle_load.1740149031 May 30 04:12:48 PM PDT 24 May 30 04:19:47 PM PDT 24 4237218132 ps
T196 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1729542865 May 30 04:16:23 PM PDT 24 May 30 04:25:09 PM PDT 24 4373993938 ps
T349 /workspace/coverage/default/2.chip_sw_all_escalation_resets.3609617410 May 30 04:24:03 PM PDT 24 May 30 04:35:29 PM PDT 24 5446980102 ps
T377 /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.3183814008 May 30 04:36:58 PM PDT 24 May 30 04:43:37 PM PDT 24 4133929818 ps
T768 /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1935232806 May 30 04:41:03 PM PDT 24 May 30 04:47:23 PM PDT 24 3974264180 ps
T63 /workspace/coverage/default/1.chip_tap_straps_rma.1222652276 May 30 04:20:11 PM PDT 24 May 30 04:30:37 PM PDT 24 6802524188 ps
T906 /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3727802378 May 30 04:32:58 PM PDT 24 May 30 04:44:47 PM PDT 24 4373084344 ps
T207 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.397260143 May 30 04:10:08 PM PDT 24 May 30 04:24:12 PM PDT 24 4895812360 ps
T907 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.3289868665 May 30 04:36:29 PM PDT 24 May 30 05:40:35 PM PDT 24 15187131840 ps
T251 /workspace/coverage/default/63.chip_sw_all_escalation_resets.2689964901 May 30 04:42:24 PM PDT 24 May 30 04:51:33 PM PDT 24 6381209768 ps
T908 /workspace/coverage/default/0.chip_sw_example_flash.1570019608 May 30 04:09:37 PM PDT 24 May 30 04:12:36 PM PDT 24 2683530680 ps
T380 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.685678664 May 30 04:18:52 PM PDT 24 May 30 05:59:36 PM PDT 24 22239462360 ps
T909 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.646455140 May 30 04:11:32 PM PDT 24 May 30 07:41:12 PM PDT 24 76399534805 ps
T910 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.3756666876 May 30 04:34:53 PM PDT 24 May 30 04:45:06 PM PDT 24 10942020681 ps
T911 /workspace/coverage/default/1.rom_e2e_smoke.2565238744 May 30 04:27:18 PM PDT 24 May 30 05:27:10 PM PDT 24 14017377656 ps
T754 /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.446880634 May 30 04:42:34 PM PDT 24 May 30 04:48:09 PM PDT 24 3245519680 ps
T700 /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2599982848 May 30 04:41:06 PM PDT 24 May 30 04:47:06 PM PDT 24 3476661360 ps
T912 /workspace/coverage/default/0.chip_sw_csrng_kat_test.102772243 May 30 04:10:20 PM PDT 24 May 30 04:14:51 PM PDT 24 3100890478 ps
T913 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2535526758 May 30 04:23:04 PM PDT 24 May 30 04:51:12 PM PDT 24 12456052001 ps
T914 /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.4231805134 May 30 04:16:52 PM PDT 24 May 30 04:22:02 PM PDT 24 4487657788 ps
T915 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.2109384358 May 30 04:11:59 PM PDT 24 May 30 04:18:32 PM PDT 24 3209415038 ps
T916 /workspace/coverage/default/2.chip_sw_uart_smoketest.1032258335 May 30 04:32:18 PM PDT 24 May 30 04:37:54 PM PDT 24 3056176800 ps
T917 /workspace/coverage/default/1.chip_sw_csrng_kat_test.3080997656 May 30 04:18:31 PM PDT 24 May 30 04:23:23 PM PDT 24 2636893182 ps
T691 /workspace/coverage/default/64.chip_sw_all_escalation_resets.2757032842 May 30 04:42:21 PM PDT 24 May 30 04:51:37 PM PDT 24 4995387232 ps
T918 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.3300412606 May 30 04:28:31 PM PDT 24 May 30 04:32:12 PM PDT 24 2194450040 ps
T240 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2818363109 May 30 04:10:29 PM PDT 24 May 30 05:30:48 PM PDT 24 46977903400 ps
T919 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3945156235 May 30 04:30:10 PM PDT 24 May 30 04:39:07 PM PDT 24 6810478500 ps
T920 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.819829596 May 30 04:27:11 PM PDT 24 May 30 04:32:50 PM PDT 24 7615944920 ps
T921 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.2155015212 May 30 04:23:53 PM PDT 24 May 30 04:48:23 PM PDT 24 8843926780 ps
T355 /workspace/coverage/default/77.chip_sw_all_escalation_resets.2546669080 May 30 04:41:46 PM PDT 24 May 30 04:51:30 PM PDT 24 4931823588 ps
T922 /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.2175573106 May 30 04:17:54 PM PDT 24 May 30 04:22:47 PM PDT 24 2800313646 ps
T430 /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.2651574066 May 30 04:33:47 PM PDT 24 May 30 04:38:55 PM PDT 24 3081273490 ps
T124 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1546662315 May 30 04:28:29 PM PDT 24 May 30 04:39:38 PM PDT 24 6091671978 ps
T34 /workspace/coverage/default/0.chip_sw_usbdev_config_host.1049844781 May 30 04:09:26 PM PDT 24 May 30 04:41:33 PM PDT 24 8008131324 ps
T923 /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.3791805169 May 30 04:34:03 PM PDT 24 May 30 05:26:50 PM PDT 24 16397304532 ps
T924 /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2784240597 May 30 04:37:16 PM PDT 24 May 30 05:19:28 PM PDT 24 11559528059 ps
T441 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.1409664098 May 30 04:28:28 PM PDT 24 May 30 04:48:04 PM PDT 24 6825344378 ps
T142 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3626979168 May 30 04:21:41 PM PDT 24 May 30 05:19:23 PM PDT 24 24842932768 ps
T925 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.4218655129 May 30 04:14:57 PM PDT 24 May 30 04:22:36 PM PDT 24 5534040510 ps
T926 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.3067493342 May 30 04:27:46 PM PDT 24 May 30 04:51:09 PM PDT 24 8975902176 ps
T172 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1487290751 May 30 04:13:10 PM PDT 24 May 30 04:24:33 PM PDT 24 4746521677 ps
T927 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.519727604 May 30 04:11:12 PM PDT 24 May 30 04:24:15 PM PDT 24 7566294600 ps
T928 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.4183315742 May 30 04:20:15 PM PDT 24 May 30 05:07:17 PM PDT 24 10842394333 ps
T929 /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.3797273107 May 30 04:15:14 PM PDT 24 May 30 04:19:53 PM PDT 24 3489440302 ps
T51 /workspace/coverage/default/0.chip_sw_spi_device_tpm.165866070 May 30 04:12:07 PM PDT 24 May 30 04:17:46 PM PDT 24 3336809863 ps
T930 /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.570998576 May 30 04:33:42 PM PDT 24 May 30 04:39:03 PM PDT 24 2963573872 ps
T931 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3446773655 May 30 04:15:39 PM PDT 24 May 30 04:47:08 PM PDT 24 13213039930 ps
T932 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.2116272382 May 30 04:10:24 PM PDT 24 May 30 04:14:23 PM PDT 24 2102786136 ps
T323 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.83404662 May 30 04:17:04 PM PDT 24 May 30 04:44:38 PM PDT 24 6694794956 ps
T356 /workspace/coverage/default/36.chip_sw_all_escalation_resets.3562788615 May 30 04:39:29 PM PDT 24 May 30 04:47:46 PM PDT 24 4536073398 ps
T245 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.478183680 May 30 04:31:29 PM PDT 24 May 30 05:02:44 PM PDT 24 24584763737 ps
T153 /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3912521819 May 30 04:38:19 PM PDT 24 May 30 04:44:48 PM PDT 24 3658972500 ps
T933 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3095062546 May 30 04:19:39 PM PDT 24 May 30 05:22:26 PM PDT 24 14068691556 ps
T210 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.4128398116 May 30 04:24:05 PM PDT 24 May 30 04:32:18 PM PDT 24 4367651848 ps
T934 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.1719755303 May 30 04:09:54 PM PDT 24 May 30 04:27:54 PM PDT 24 6414770735 ps
T935 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.2465481485 May 30 04:23:20 PM PDT 24 May 30 04:26:21 PM PDT 24 2262435574 ps
T936 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2743963544 May 30 04:22:06 PM PDT 24 May 30 04:26:09 PM PDT 24 2587035109 ps
T937 /workspace/coverage/default/2.chip_tap_straps_rma.1060512843 May 30 04:29:53 PM PDT 24 May 30 04:41:32 PM PDT 24 6935650097 ps
T938 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.880227720 May 30 04:17:52 PM PDT 24 May 30 04:20:44 PM PDT 24 2227871912 ps
T939 /workspace/coverage/default/1.chip_sw_otbn_smoketest.219600424 May 30 04:24:02 PM PDT 24 May 30 05:00:27 PM PDT 24 10845419898 ps
T940 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.2759679705 May 30 04:25:31 PM PDT 24 May 30 04:45:59 PM PDT 24 8957897552 ps
T113 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2538462628 May 30 04:28:00 PM PDT 24 May 30 04:37:57 PM PDT 24 4623446392 ps
T941 /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.3412727720 May 30 04:36:31 PM PDT 24 May 30 04:46:45 PM PDT 24 10503703968 ps
T360 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.30724015 May 30 04:24:59 PM PDT 24 May 30 04:36:03 PM PDT 24 4363099368 ps
T942 /workspace/coverage/default/1.chip_tap_straps_dev.890228169 May 30 04:20:46 PM PDT 24 May 30 04:23:38 PM PDT 24 2174606877 ps
T325 /workspace/coverage/default/0.chip_plic_all_irqs_0.3278467739 May 30 04:11:21 PM PDT 24 May 30 04:30:30 PM PDT 24 5590370296 ps
T943 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1164694074 May 30 04:20:34 PM PDT 24 May 30 04:35:35 PM PDT 24 4955993600 ps
T727 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3507167481 May 30 04:34:16 PM PDT 24 May 30 04:40:38 PM PDT 24 3821322444 ps
T77 /workspace/coverage/default/2.chip_jtag_mem_access.3076127191 May 30 04:22:03 PM PDT 24 May 30 04:49:10 PM PDT 24 13578523221 ps
T213 /workspace/coverage/default/2.chip_sw_pattgen_ios.2665131687 May 30 04:24:47 PM PDT 24 May 30 04:28:48 PM PDT 24 3027743180 ps
T12 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.1511184325 May 30 04:15:09 PM PDT 24 May 30 04:22:50 PM PDT 24 4882813640 ps
T408 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2596638519 May 30 04:41:46 PM PDT 24 May 30 04:47:28 PM PDT 24 3906384760 ps
T409 /workspace/coverage/default/57.chip_sw_all_escalation_resets.1554648331 May 30 04:40:28 PM PDT 24 May 30 04:51:37 PM PDT 24 5773879962 ps
T410 /workspace/coverage/default/71.chip_sw_all_escalation_resets.3881376955 May 30 04:41:50 PM PDT 24 May 30 04:50:03 PM PDT 24 5815244980 ps
T171 /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1205274443 May 30 04:12:04 PM PDT 24 May 30 04:14:32 PM PDT 24 2608226049 ps
T115 /workspace/coverage/default/1.chip_sw_edn_kat.3389361761 May 30 04:17:38 PM PDT 24 May 30 04:26:57 PM PDT 24 3501774382 ps
T411 /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.762286166 May 30 04:31:07 PM PDT 24 May 30 04:38:11 PM PDT 24 3786598536 ps
T412 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2038297436 May 30 04:21:51 PM PDT 24 May 30 04:34:17 PM PDT 24 5068925724 ps
T35 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.1223416300 May 30 04:10:12 PM PDT 24 May 30 04:19:44 PM PDT 24 3973598500 ps
T413 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.3666994537 May 30 04:11:09 PM PDT 24 May 30 04:28:37 PM PDT 24 10282635262 ps
T653 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.2031877989 May 30 04:25:25 PM PDT 24 May 30 04:27:00 PM PDT 24 2305372937 ps
T944 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.2805890585 May 30 04:23:08 PM PDT 24 May 30 04:30:45 PM PDT 24 5878145272 ps
T945 /workspace/coverage/default/2.chip_sw_example_rom.2864410278 May 30 04:22:27 PM PDT 24 May 30 04:24:36 PM PDT 24 2083192480 ps
T33 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.2764435111 May 30 04:14:59 PM PDT 24 May 30 05:05:25 PM PDT 24 20337836976 ps
T759 /workspace/coverage/default/4.chip_sw_all_escalation_resets.3359062827 May 30 04:34:00 PM PDT 24 May 30 04:44:47 PM PDT 24 4703807166 ps
T37 /workspace/coverage/default/2.chip_sw_gpio.4272683807 May 30 04:24:40 PM PDT 24 May 30 04:34:24 PM PDT 24 4525224520 ps
T946 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.3871280338 May 30 04:09:36 PM PDT 24 May 30 04:29:40 PM PDT 24 6680904712 ps
T947 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3158982973 May 30 04:18:23 PM PDT 24 May 30 05:23:26 PM PDT 24 14639839350 ps
T346 /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.2953840348 May 30 04:23:46 PM PDT 24 May 30 07:59:38 PM PDT 24 78274972920 ps
T948 /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.2973766170 May 30 04:34:09 PM PDT 24 May 30 05:39:45 PM PDT 24 16357947588 ps
T949 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.2036209389 May 30 04:25:14 PM PDT 24 May 30 05:06:04 PM PDT 24 12864549433 ps
T950 /workspace/coverage/default/2.chip_sw_edn_kat.326740229 May 30 04:30:12 PM PDT 24 May 30 04:41:56 PM PDT 24 3062014520 ps
T951 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.2669366235 May 30 04:18:32 PM PDT 24 May 30 05:39:38 PM PDT 24 21832332976 ps
T952 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.794138551 May 30 04:26:50 PM PDT 24 May 30 04:39:03 PM PDT 24 7354150802 ps
T953 /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.2174340583 May 30 04:23:45 PM PDT 24 May 30 04:27:27 PM PDT 24 2254887094 ps
T692 /workspace/coverage/default/73.chip_sw_all_escalation_resets.168091671 May 30 04:44:21 PM PDT 24 May 30 04:54:12 PM PDT 24 5804368392 ps
T182 /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.3405250282 May 30 04:30:17 PM PDT 24 May 30 04:38:15 PM PDT 24 3379665128 ps
T954 /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.1343357841 May 30 04:27:24 PM PDT 24 May 30 04:31:29 PM PDT 24 3139408590 ps
T717 /workspace/coverage/default/30.chip_sw_all_escalation_resets.2740082366 May 30 04:36:15 PM PDT 24 May 30 04:47:03 PM PDT 24 4386354304 ps
T955 /workspace/coverage/default/0.chip_sw_power_sleep_load.666689183 May 30 04:13:32 PM PDT 24 May 30 04:23:10 PM PDT 24 9892632352 ps
T956 /workspace/coverage/default/4.chip_tap_straps_testunlock0.1336580219 May 30 04:31:52 PM PDT 24 May 30 04:34:17 PM PDT 24 2582082769 ps
T365 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.4077856300 May 30 04:40:54 PM PDT 24 May 30 04:47:15 PM PDT 24 3404934470 ps
T156 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2363401521 May 30 04:10:21 PM PDT 24 May 30 04:12:35 PM PDT 24 2463285998 ps
T366 /workspace/coverage/default/61.chip_sw_all_escalation_resets.2656840238 May 30 04:40:01 PM PDT 24 May 30 04:49:16 PM PDT 24 4145521450 ps
T312 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.260389457 May 30 04:46:29 PM PDT 24 May 30 04:52:51 PM PDT 24 3884473570 ps
T957 /workspace/coverage/default/2.chip_sw_example_concurrency.2893245400 May 30 04:25:00 PM PDT 24 May 30 04:30:13 PM PDT 24 2955456388 ps
T958 /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.2235312379 May 30 04:32:38 PM PDT 24 May 30 05:30:40 PM PDT 24 16649489230 ps
T442 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.2278270994 May 30 04:18:23 PM PDT 24 May 30 04:40:23 PM PDT 24 6524739288 ps
T959 /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.1036816237 May 30 04:12:48 PM PDT 24 May 30 04:17:31 PM PDT 24 2691343140 ps
T960 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.3474152646 May 30 04:10:20 PM PDT 24 May 30 04:33:40 PM PDT 24 7297445792 ps
T961 /workspace/coverage/default/2.chip_sw_csrng_smoketest.2259634035 May 30 04:32:54 PM PDT 24 May 30 04:35:51 PM PDT 24 2678961032 ps
T962 /workspace/coverage/default/1.chip_sw_example_manufacturer.435457066 May 30 04:16:26 PM PDT 24 May 30 04:21:56 PM PDT 24 3196911658 ps
T963 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.1047346695 May 30 04:25:00 PM PDT 24 May 30 04:38:04 PM PDT 24 6344266538 ps
T173 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2075738731 May 30 04:32:43 PM PDT 24 May 30 04:43:07 PM PDT 24 3886497514 ps
T964 /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.4045562802 May 30 04:14:18 PM PDT 24 May 30 07:58:22 PM PDT 24 78127030536 ps
T389 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1926955769 May 30 04:36:57 PM PDT 24 May 30 04:45:16 PM PDT 24 4466004456 ps
T965 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1009551870 May 30 04:12:36 PM PDT 24 May 30 04:17:45 PM PDT 24 3301688773 ps
T353 /workspace/coverage/default/1.chip_sw_pattgen_ios.789768730 May 30 04:14:30 PM PDT 24 May 30 04:17:55 PM PDT 24 2652434490 ps
T177 /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.1189297567 May 30 04:31:20 PM PDT 24 May 30 04:35:19 PM PDT 24 2286604744 ps
T966 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1131909971 May 30 04:10:14 PM PDT 24 May 30 04:37:47 PM PDT 24 16384357847 ps
T155 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1477058823 May 30 04:15:59 PM PDT 24 May 30 04:17:57 PM PDT 24 1908521995 ps
T326 /workspace/coverage/default/1.chip_plic_all_irqs_0.4130697781 May 30 04:18:40 PM PDT 24 May 30 04:39:00 PM PDT 24 5849832488 ps
T256 /workspace/coverage/default/0.chip_sw_plic_sw_irq.2781942609 May 30 04:10:52 PM PDT 24 May 30 04:15:42 PM PDT 24 2635163172 ps
T342 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2103790861 May 30 04:09:41 PM PDT 24 May 30 04:27:13 PM PDT 24 6132352432 ps
T358 /workspace/coverage/default/0.chip_sw_aon_timer_irq.535807177 May 30 04:11:24 PM PDT 24 May 30 04:17:55 PM PDT 24 4097477116 ps
T132 /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1856056324 May 30 04:12:54 PM PDT 24 May 30 04:22:33 PM PDT 24 6172230490 ps
T715 /workspace/coverage/default/54.chip_sw_all_escalation_resets.4162523593 May 30 04:42:37 PM PDT 24 May 30 04:53:21 PM PDT 24 6441443650 ps
T967 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3495933251 May 30 04:13:09 PM PDT 24 May 30 04:50:43 PM PDT 24 8725023800 ps
T968 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.4269919156 May 30 04:18:19 PM PDT 24 May 30 05:19:22 PM PDT 24 13845322268 ps
T969 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.2114767743 May 30 04:18:31 PM PDT 24 May 30 04:41:37 PM PDT 24 8811357920 ps
T970 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3977090349 May 30 04:11:55 PM PDT 24 May 30 04:23:41 PM PDT 24 4615790412 ps
T244 /workspace/coverage/default/1.chip_sw_flash_init.1366695575 May 30 04:15:32 PM PDT 24 May 30 04:52:43 PM PDT 24 19739000584 ps
T242 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.20002605 May 30 04:09:46 PM PDT 24 May 30 05:41:08 PM PDT 24 47606282490 ps
T243 /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.3320998154 May 30 04:27:48 PM PDT 24 May 30 05:50:44 PM PDT 24 48238852390 ps
T971 /workspace/coverage/default/0.chip_sw_csrng_smoketest.2389775329 May 30 04:13:23 PM PDT 24 May 30 04:17:18 PM PDT 24 2420077860 ps
T972 /workspace/coverage/default/91.chip_sw_all_escalation_resets.3347656023 May 30 04:42:46 PM PDT 24 May 30 04:50:29 PM PDT 24 4227835508 ps
T338 /workspace/coverage/default/1.chip_plic_all_irqs_20.3835949351 May 30 04:23:52 PM PDT 24 May 30 04:37:55 PM PDT 24 4716157120 ps
T718 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2665875251 May 30 04:27:43 PM PDT 24 May 30 04:36:42 PM PDT 24 4047398264 ps
T694 /workspace/coverage/default/35.chip_sw_all_escalation_resets.1526007763 May 30 04:36:26 PM PDT 24 May 30 04:46:50 PM PDT 24 6052770216 ps
T973 /workspace/coverage/default/2.rom_keymgr_functest.108151452 May 30 04:31:37 PM PDT 24 May 30 04:40:46 PM PDT 24 4986779260 ps
T974 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.2219632598 May 30 04:11:30 PM PDT 24 May 30 04:33:59 PM PDT 24 7289709970 ps
T975 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.3886200672 May 30 04:30:54 PM PDT 24 May 30 04:49:42 PM PDT 24 5376232282 ps
T976 /workspace/coverage/default/1.chip_sw_edn_auto_mode.1257077781 May 30 04:18:46 PM PDT 24 May 30 04:31:31 PM PDT 24 3281884384 ps
T688 /workspace/coverage/default/19.chip_sw_all_escalation_resets.2309305327 May 30 04:37:09 PM PDT 24 May 30 04:45:25 PM PDT 24 4719576802 ps
T977 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2998740358 May 30 04:13:40 PM PDT 24 May 30 04:23:12 PM PDT 24 3988461012 ps
T978 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3659688992 May 30 04:18:46 PM PDT 24 May 30 05:45:55 PM PDT 24 22323551614 ps
T979 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.501383834 May 30 04:17:19 PM PDT 24 May 30 04:33:20 PM PDT 24 9374278804 ps
T980 /workspace/coverage/default/2.chip_sw_flash_crash_alert.1732480749 May 30 04:31:09 PM PDT 24 May 30 04:41:50 PM PDT 24 5482968400 ps
T728 /workspace/coverage/default/69.chip_sw_all_escalation_resets.4195840523 May 30 04:41:09 PM PDT 24 May 30 04:50:07 PM PDT 24 4228491484 ps
T86 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.627715166 May 30 04:33:55 PM PDT 24 May 30 04:41:10 PM PDT 24 3444079420 ps
T739 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.418181591 May 30 04:33:06 PM PDT 24 May 30 04:40:44 PM PDT 24 3598349524 ps
T764 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1817555789 May 30 04:41:56 PM PDT 24 May 30 04:48:35 PM PDT 24 4290465064 ps
T749 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.126875867 May 30 04:40:32 PM PDT 24 May 30 04:45:53 PM PDT 24 3371116802 ps
T981 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.1980159737 May 30 04:19:59 PM PDT 24 May 30 05:37:40 PM PDT 24 16588021867 ps
T982 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.2918614545 May 30 04:34:40 PM PDT 24 May 30 04:51:14 PM PDT 24 11443444580 ps
T712 /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1136748820 May 30 04:43:34 PM PDT 24 May 30 04:49:25 PM PDT 24 4119074580 ps
T983 /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3707504355 May 30 04:18:13 PM PDT 24 May 30 04:25:06 PM PDT 24 6430203376 ps
T281 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.318438396 May 30 04:31:20 PM PDT 24 May 30 04:41:15 PM PDT 24 5228788700 ps
T81 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3768741533 May 30 04:30:44 PM PDT 24 May 30 04:52:47 PM PDT 24 11387668080 ps
T984 /workspace/coverage/default/1.chip_sw_uart_tx_rx.148683031 May 30 04:13:41 PM PDT 24 May 30 04:22:52 PM PDT 24 4314860660 ps
T708 /workspace/coverage/default/27.chip_sw_all_escalation_resets.3319407303 May 30 04:35:38 PM PDT 24 May 30 04:44:59 PM PDT 24 4528359400 ps
T985 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.945977036 May 30 04:11:05 PM PDT 24 May 30 04:15:41 PM PDT 24 2334956268 ps
T78 /workspace/coverage/default/1.chip_jtag_mem_access.4257359904 May 30 04:12:29 PM PDT 24 May 30 04:40:08 PM PDT 24 13649777530 ps
T986 /workspace/coverage/default/2.rom_e2e_asm_init_rma.3238484735 May 30 04:36:29 PM PDT 24 May 30 05:35:53 PM PDT 24 14669166760 ps
T987 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.630095949 May 30 04:12:55 PM PDT 24 May 30 04:31:28 PM PDT 24 5317726778 ps
T722 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.749044035 May 30 04:19:10 PM PDT 24 May 30 04:26:23 PM PDT 24 3857592520 ps
T988 /workspace/coverage/default/0.chip_sw_kmac_entropy.504715048 May 30 04:10:12 PM PDT 24 May 30 04:14:53 PM PDT 24 2503469798 ps
T8 /workspace/coverage/default/1.chip_jtag_csr_rw.2086984306 May 30 04:12:35 PM PDT 24 May 30 04:37:42 PM PDT 24 13991623432 ps
T400 /workspace/coverage/default/55.chip_sw_all_escalation_resets.1199464185 May 30 04:39:40 PM PDT 24 May 30 04:46:52 PM PDT 24 5267206022 ps
T401 /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2666984235 May 30 04:18:52 PM PDT 24 May 30 04:26:47 PM PDT 24 3832420664 ps
T343 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1283418351 May 30 04:10:34 PM PDT 24 May 30 04:25:11 PM PDT 24 5361018090 ps
T402 /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2879292842 May 30 04:40:07 PM PDT 24 May 30 04:46:35 PM PDT 24 3717348180 ps
T403 /workspace/coverage/default/1.chip_sw_flash_crash_alert.3714073232 May 30 04:20:39 PM PDT 24 May 30 04:30:10 PM PDT 24 5443029064 ps
T404 /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3879369151 May 30 04:42:10 PM PDT 24 May 30 04:48:48 PM PDT 24 3814401040 ps
T405 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.3444570886 May 30 04:27:29 PM PDT 24 May 30 05:42:02 PM PDT 24 14689283292 ps
T406 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.4273266107 May 30 04:27:03 PM PDT 24 May 30 05:08:18 PM PDT 24 9494917204 ps
T407 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.1896715348 May 30 04:11:17 PM PDT 24 May 30 04:18:34 PM PDT 24 4064573956 ps
T989 /workspace/coverage/default/4.chip_tap_straps_prod.65359714 May 30 04:31:55 PM PDT 24 May 30 04:43:43 PM PDT 24 6542692373 ps
T990 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2501426919 May 30 04:10:16 PM PDT 24 May 30 04:14:23 PM PDT 24 3143941988 ps
T991 /workspace/coverage/default/2.chip_sw_aes_masking_off.3555634034 May 30 04:30:00 PM PDT 24 May 30 04:34:21 PM PDT 24 2682753431 ps
T992 /workspace/coverage/default/2.chip_sw_hmac_enc_idle.1067487843 May 30 04:27:42 PM PDT 24 May 30 04:31:53 PM PDT 24 2665009440 ps
T724 /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1278270783 May 30 04:41:48 PM PDT 24 May 30 04:48:12 PM PDT 24 4197789060 ps
T993 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2875678744 May 30 04:22:48 PM PDT 24 May 30 04:39:59 PM PDT 24 7772908762 ps
T994 /workspace/coverage/default/85.chip_sw_all_escalation_resets.3306210295 May 30 04:47:15 PM PDT 24 May 30 04:58:47 PM PDT 24 5381841828 ps
T9 /workspace/coverage/default/0.chip_jtag_csr_rw.3081121853 May 30 04:03:14 PM PDT 24 May 30 04:48:24 PM PDT 24 20548844740 ps
T246 /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.2312159085 May 30 04:19:18 PM PDT 24 May 30 05:41:52 PM PDT 24 51004463032 ps
T220 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.1374942557 May 30 04:12:50 PM PDT 24 May 30 05:09:28 PM PDT 24 20155012511 ps
T654 /workspace/coverage/default/1.rom_volatile_raw_unlock.721569678 May 30 04:23:06 PM PDT 24 May 30 04:24:55 PM PDT 24 2233618133 ps
T995 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.2917240071 May 30 04:12:15 PM PDT 24 May 30 04:37:18 PM PDT 24 8624616358 ps
T996 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.561250636 May 30 04:16:59 PM PDT 24 May 30 05:10:53 PM PDT 24 16602814246 ps
T282 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.1880265970 May 30 04:18:14 PM PDT 24 May 30 04:32:00 PM PDT 24 5177537868 ps
T997 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3893807116 May 30 04:30:37 PM PDT 24 May 30 04:41:56 PM PDT 24 4055031828 ps
T48 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.687350101 May 30 04:26:30 PM PDT 24 May 30 04:34:06 PM PDT 24 5164372800 ps
T998 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.1134663641 May 30 04:13:53 PM PDT 24 May 30 07:31:57 PM PDT 24 65396092240 ps
T15 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3495760376 May 30 04:12:00 PM PDT 24 May 30 04:40:42 PM PDT 24 21789347796 ps
T13 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.2306866470 May 30 04:25:18 PM PDT 24 May 30 04:29:34 PM PDT 24 3275509916 ps
T664 /workspace/coverage/default/95.chip_sw_all_escalation_resets.998342975 May 30 04:46:31 PM PDT 24 May 30 04:57:18 PM PDT 24 4766531590 ps
T295 /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.3618661067 May 30 04:11:06 PM PDT 24 May 30 04:14:22 PM PDT 24 3205863822 ps
T999 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.185631454 May 30 04:20:54 PM PDT 24 May 30 04:30:28 PM PDT 24 3722131616 ps
T1000 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.821355926 May 30 04:25:26 PM PDT 24 May 30 04:58:10 PM PDT 24 21795418802 ps
T1001 /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1531397496 May 30 04:41:38 PM PDT 24 May 30 04:48:10 PM PDT 24 3690044828 ps
T1002 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.3717332486 May 30 04:37:13 PM PDT 24 May 30 04:58:43 PM PDT 24 8958317376 ps
T267 /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.2553354970 May 30 04:10:19 PM PDT 24 May 30 04:20:09 PM PDT 24 6317910808 ps
T1003 /workspace/coverage/default/1.chip_sw_alert_handler_escalation.1031173030 May 30 04:17:26 PM PDT 24 May 30 04:25:43 PM PDT 24 4491512996 ps
T1004 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.3939569002 May 30 04:17:50 PM PDT 24 May 30 05:16:49 PM PDT 24 19718442692 ps
T385 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.416468770 May 30 04:16:10 PM PDT 24 May 30 04:28:55 PM PDT 24 4570935264 ps
T1005 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.3642278473 May 30 04:26:49 PM PDT 24 May 30 04:33:26 PM PDT 24 4304482880 ps
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