| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.13 | 95.57 | 94.38 | 95.52 | 95.30 | 96.47 | 99.58 |
| T2762 | /workspace/coverage/cover_reg_top/41.xbar_same_source.2338548441 | May 30 03:52:44 PM PDT 24 | May 30 03:53:29 PM PDT 24 | 1435347896 ps | ||
| T2763 | /workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.1616578514 | May 30 03:51:54 PM PDT 24 | May 30 03:52:25 PM PDT 24 | 353983393 ps | ||
| T2764 | /workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.1292246536 | May 30 03:49:41 PM PDT 24 | May 30 04:43:01 PM PDT 24 | 28243088806 ps | ||
| T2765 | /workspace/coverage/cover_reg_top/2.xbar_random.3003063059 | May 30 03:48:37 PM PDT 24 | May 30 03:49:10 PM PDT 24 | 867248003 ps | ||
| T2766 | /workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.1814521582 | May 30 04:01:08 PM PDT 24 | May 30 04:02:43 PM PDT 24 | 5383786670 ps | ||
| T2767 | /workspace/coverage/cover_reg_top/64.xbar_random_large_delays.1181956249 | May 30 03:56:24 PM PDT 24 | May 30 04:09:41 PM PDT 24 | 67148580554 ps | ||
| T2768 | /workspace/coverage/cover_reg_top/46.xbar_random_large_delays.145050509 | May 30 03:53:27 PM PDT 24 | May 30 03:57:16 PM PDT 24 | 21769057936 ps | ||
| T2769 | /workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.3365946957 | May 30 03:49:10 PM PDT 24 | May 30 03:49:18 PM PDT 24 | 44112842 ps | ||
| T2770 | /workspace/coverage/cover_reg_top/29.xbar_smoke_large_delays.3477958359 | May 30 03:51:09 PM PDT 24 | May 30 03:52:38 PM PDT 24 | 8491600056 ps | ||
| T2771 | /workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.567521784 | May 30 03:55:57 PM PDT 24 | May 30 03:57:21 PM PDT 24 | 5141963536 ps | ||
| T2772 | /workspace/coverage/cover_reg_top/10.xbar_same_source.3129615370 | May 30 03:48:59 PM PDT 24 | May 30 03:49:27 PM PDT 24 | 410279391 ps | ||
| T2773 | /workspace/coverage/cover_reg_top/41.xbar_smoke.469331783 | May 30 03:52:46 PM PDT 24 | May 30 03:52:54 PM PDT 24 | 58355059 ps | ||
| T2774 | /workspace/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.2823153408 | May 30 03:58:31 PM PDT 24 | May 30 04:00:10 PM PDT 24 | 5724707986 ps | ||
| T2775 | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.1043844970 | May 30 03:53:26 PM PDT 24 | May 30 03:59:31 PM PDT 24 | 9664731875 ps | ||
| T2776 | /workspace/coverage/cover_reg_top/59.xbar_access_same_device.3453403635 | May 30 03:55:29 PM PDT 24 | May 30 03:57:15 PM PDT 24 | 2735193992 ps | ||
| T2777 | /workspace/coverage/cover_reg_top/11.xbar_same_source.4120305852 | May 30 03:49:00 PM PDT 24 | May 30 03:49:26 PM PDT 24 | 332836185 ps | ||
| T2778 | /workspace/coverage/cover_reg_top/33.xbar_smoke_zero_delays.114402472 | May 30 03:51:40 PM PDT 24 | May 30 03:51:47 PM PDT 24 | 46035182 ps | ||
| T2779 | /workspace/coverage/cover_reg_top/95.xbar_error_random.3861785101 | May 30 04:00:52 PM PDT 24 | May 30 04:01:35 PM PDT 24 | 1295456717 ps | ||
| T2780 | /workspace/coverage/cover_reg_top/86.xbar_same_source.1283516158 | May 30 03:59:34 PM PDT 24 | May 30 04:00:56 PM PDT 24 | 2461676383 ps | ||
| T2781 | /workspace/coverage/cover_reg_top/92.xbar_same_source.3560825215 | May 30 04:00:29 PM PDT 24 | May 30 04:00:52 PM PDT 24 | 294886553 ps | ||
| T2782 | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.2602598478 | May 30 03:49:10 PM PDT 24 | May 30 03:51:35 PM PDT 24 | 612764173 ps | ||
| T2783 | /workspace/coverage/cover_reg_top/43.xbar_random.1339298443 | May 30 03:53:08 PM PDT 24 | May 30 03:53:52 PM PDT 24 | 480923673 ps | ||
| T2784 | /workspace/coverage/cover_reg_top/73.xbar_unmapped_addr.3484326479 | May 30 03:57:40 PM PDT 24 | May 30 03:58:06 PM PDT 24 | 536178600 ps | ||
| T2785 | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.238428006 | May 30 04:00:04 PM PDT 24 | May 30 04:00:36 PM PDT 24 | 63934337 ps | ||
| T2786 | /workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.1676383778 | May 30 03:48:52 PM PDT 24 | May 30 03:59:39 PM PDT 24 | 44091543316 ps | ||
| T2787 | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.1515108902 | May 30 03:58:38 PM PDT 24 | May 30 04:00:48 PM PDT 24 | 1286314520 ps | ||
| T2788 | /workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.1385196225 | May 30 03:51:03 PM PDT 24 | May 30 03:51:10 PM PDT 24 | 48698090 ps | ||
| T2789 | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2890358361 | May 30 03:48:38 PM PDT 24 | May 30 03:57:31 PM PDT 24 | 3014463038 ps | ||
| T2790 | /workspace/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.4096218181 | May 30 04:01:23 PM PDT 24 | May 30 04:01:41 PM PDT 24 | 163155435 ps | ||
| T2791 | /workspace/coverage/cover_reg_top/5.chip_tl_errors.4273738422 | May 30 03:48:41 PM PDT 24 | May 30 03:54:18 PM PDT 24 | 4650419154 ps | ||
| T2792 | /workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.4012530684 | May 30 03:50:50 PM PDT 24 | May 30 03:51:50 PM PDT 24 | 5442537646 ps | ||
| T2793 | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.607292142 | May 30 04:00:39 PM PDT 24 | May 30 04:02:03 PM PDT 24 | 313973093 ps | ||
| T2794 | /workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.3716225424 | May 30 03:56:42 PM PDT 24 | May 30 03:57:35 PM PDT 24 | 606054931 ps | ||
| T2795 | /workspace/coverage/cover_reg_top/45.xbar_smoke_zero_delays.2221962707 | May 30 03:53:18 PM PDT 24 | May 30 03:53:26 PM PDT 24 | 45949452 ps | ||
| T2796 | /workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.1401783760 | May 30 03:49:19 PM PDT 24 | May 30 03:49:27 PM PDT 24 | 51292059 ps | ||
| T2797 | /workspace/coverage/cover_reg_top/4.xbar_unmapped_addr.3024561700 | May 30 03:48:59 PM PDT 24 | May 30 03:49:44 PM PDT 24 | 1015235906 ps | ||
| T2798 | /workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.563504642 | May 30 03:54:35 PM PDT 24 | May 30 04:11:51 PM PDT 24 | 52894036512 ps | ||
| T2799 | /workspace/coverage/cover_reg_top/89.xbar_same_source.1587201777 | May 30 04:00:05 PM PDT 24 | May 30 04:00:35 PM PDT 24 | 918929622 ps | ||
| T2800 | /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.790644393 | May 30 03:58:05 PM PDT 24 | May 30 04:18:45 PM PDT 24 | 64238422978 ps | ||
| T2801 | /workspace/coverage/cover_reg_top/32.xbar_access_same_device.3232323261 | May 30 03:51:40 PM PDT 24 | May 30 03:51:49 PM PDT 24 | 25693817 ps | ||
| T2802 | /workspace/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.2510934558 | May 30 03:54:03 PM PDT 24 | May 30 03:55:53 PM PDT 24 | 5915360358 ps | ||
| T2803 | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.2585456498 | May 30 03:57:29 PM PDT 24 | May 30 04:00:24 PM PDT 24 | 1225938721 ps | ||
| T2804 | /workspace/coverage/cover_reg_top/66.xbar_error_random.189774932 | May 30 03:56:34 PM PDT 24 | May 30 03:57:20 PM PDT 24 | 492958513 ps | ||
| T2805 | /workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.11106511 | May 30 03:49:15 PM PDT 24 | May 30 03:49:24 PM PDT 24 | 45431218 ps | ||
| T2806 | /workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.2010926728 | May 30 03:59:18 PM PDT 24 | May 30 04:00:30 PM PDT 24 | 6701017302 ps | ||
| T2807 | /workspace/coverage/cover_reg_top/49.xbar_smoke_zero_delays.1743305033 | May 30 03:54:02 PM PDT 24 | May 30 03:54:09 PM PDT 24 | 49298804 ps | ||
| T2808 | /workspace/coverage/cover_reg_top/47.xbar_random.2637179341 | May 30 03:53:36 PM PDT 24 | May 30 03:53:48 PM PDT 24 | 98079190 ps | ||
| T2809 | /workspace/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.4084096567 | May 30 03:59:11 PM PDT 24 | May 30 04:00:59 PM PDT 24 | 6245256750 ps | ||
| T2810 | /workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.1659747838 | May 30 03:54:25 PM PDT 24 | May 30 03:55:49 PM PDT 24 | 4713249657 ps | ||
| T2811 | /workspace/coverage/cover_reg_top/6.xbar_random_large_delays.478576576 | May 30 03:48:55 PM PDT 24 | May 30 04:06:24 PM PDT 24 | 99989662491 ps | ||
| T2812 | /workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.3401578898 | May 30 03:49:03 PM PDT 24 | May 30 03:50:15 PM PDT 24 | 7032572039 ps | ||
| T2813 | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.4185962042 | May 30 03:56:54 PM PDT 24 | May 30 03:57:17 PM PDT 24 | 25060388 ps | ||
| T2814 | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.3775329837 | May 30 03:56:34 PM PDT 24 | May 30 03:59:18 PM PDT 24 | 4992062745 ps | ||
| T2815 | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.4201290859 | May 30 03:53:26 PM PDT 24 | May 30 04:06:08 PM PDT 24 | 5602968775 ps | ||
| T2816 | /workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.2913468906 | May 30 03:49:30 PM PDT 24 | May 30 03:51:12 PM PDT 24 | 6236088526 ps | ||
| T2817 | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.2589670118 | May 30 03:58:29 PM PDT 24 | May 30 04:04:01 PM PDT 24 | 871801285 ps | ||
| T2818 | /workspace/coverage/cover_reg_top/81.xbar_random_zero_delays.2295773765 | May 30 03:58:48 PM PDT 24 | May 30 03:59:03 PM PDT 24 | 156629478 ps | ||
| T2819 | /workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.745564257 | May 30 03:49:51 PM PDT 24 | May 30 03:50:34 PM PDT 24 | 1157778658 ps | ||
| T2820 | /workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.1527151706 | May 30 03:59:48 PM PDT 24 | May 30 04:38:42 PM PDT 24 | 136344540138 ps | ||
| T2821 | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.1108049845 | May 30 04:01:16 PM PDT 24 | May 30 04:01:32 PM PDT 24 | 7554697 ps | ||
| T2822 | /workspace/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.2137909738 | May 30 03:50:25 PM PDT 24 | May 30 03:51:55 PM PDT 24 | 5598581933 ps | ||
| T2823 | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.2714004858 | May 30 03:58:40 PM PDT 24 | May 30 04:02:16 PM PDT 24 | 922690223 ps | ||
| T2824 | /workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.1481009961 | May 30 03:53:04 PM PDT 24 | May 30 04:01:52 PM PDT 24 | 30832663318 ps | ||
| T2825 | /workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.822354609 | May 30 03:49:14 PM PDT 24 | May 30 03:50:27 PM PDT 24 | 4033261115 ps | ||
| T2826 | /workspace/coverage/cover_reg_top/88.xbar_smoke.158899486 | May 30 03:59:53 PM PDT 24 | May 30 04:00:01 PM PDT 24 | 52466250 ps | ||
| T2827 | /workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.4270726534 | May 30 03:48:59 PM PDT 24 | May 30 03:50:16 PM PDT 24 | 7834358444 ps | ||
| T2828 | /workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.1906578917 | May 30 03:49:24 PM PDT 24 | May 30 03:49:31 PM PDT 24 | 38955641 ps | ||
| T2829 | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.1900919587 | May 30 04:01:26 PM PDT 24 | May 30 04:09:09 PM PDT 24 | 2638164283 ps | ||
| T2830 | /workspace/coverage/cover_reg_top/85.xbar_stress_all.2697351844 | May 30 03:59:32 PM PDT 24 | May 30 04:01:03 PM PDT 24 | 1202119389 ps | ||
| T2831 | /workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.2867458357 | May 30 03:49:38 PM PDT 24 | May 30 04:37:51 PM PDT 24 | 166813849259 ps | ||
| T2832 | /workspace/coverage/cover_reg_top/73.xbar_smoke.3129440659 | May 30 03:57:29 PM PDT 24 | May 30 03:57:36 PM PDT 24 | 44295401 ps | ||
| T2833 | /workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.98924948 | May 30 03:50:22 PM PDT 24 | May 30 03:50:53 PM PDT 24 | 334261457 ps | ||
| T2834 | /workspace/coverage/cover_reg_top/33.xbar_random_large_delays.2282339585 | May 30 03:51:40 PM PDT 24 | May 30 03:55:51 PM PDT 24 | 21431137679 ps | ||
| T2835 | /workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.1541369127 | May 30 04:00:36 PM PDT 24 | May 30 04:01:13 PM PDT 24 | 891547237 ps | ||
| T2836 | /workspace/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.1266313900 | May 30 03:58:51 PM PDT 24 | May 30 03:59:18 PM PDT 24 | 258463764 ps | ||
| T2837 | /workspace/coverage/cover_reg_top/75.xbar_smoke_zero_delays.2411912366 | May 30 03:57:49 PM PDT 24 | May 30 03:57:57 PM PDT 24 | 50564326 ps | ||
| T2838 | /workspace/coverage/cover_reg_top/48.xbar_random_slow_rsp.2747178029 | May 30 03:53:50 PM PDT 24 | May 30 04:11:12 PM PDT 24 | 60139141507 ps | ||
| T2839 | /workspace/coverage/cover_reg_top/31.xbar_error_random.3447626503 | May 30 03:51:33 PM PDT 24 | May 30 03:52:13 PM PDT 24 | 439339742 ps | ||
| T2840 | /workspace/coverage/cover_reg_top/42.xbar_smoke_zero_delays.323629737 | May 30 03:52:59 PM PDT 24 | May 30 03:53:07 PM PDT 24 | 53549051 ps | ||
| T2841 | /workspace/coverage/cover_reg_top/76.xbar_unmapped_addr.2892994829 | May 30 03:58:06 PM PDT 24 | May 30 03:58:21 PM PDT 24 | 246237226 ps | ||
| T2842 | /workspace/coverage/cover_reg_top/38.xbar_stress_all.613976823 | May 30 03:52:25 PM PDT 24 | May 30 03:57:33 PM PDT 24 | 3629813142 ps | ||
| T2843 | /workspace/coverage/cover_reg_top/50.xbar_stress_all.2124212508 | May 30 03:54:12 PM PDT 24 | May 30 03:57:36 PM PDT 24 | 2572141584 ps | ||
| T2844 | /workspace/coverage/cover_reg_top/96.xbar_stress_all.4275455706 | May 30 04:01:05 PM PDT 24 | May 30 04:06:50 PM PDT 24 | 9154226295 ps | ||
| T2845 | /workspace/coverage/cover_reg_top/3.chip_csr_bit_bash.4154239271 | May 30 03:48:58 PM PDT 24 | May 30 03:55:40 PM PDT 24 | 4301012150 ps | ||
| T2846 | /workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.1381023129 | May 30 03:48:29 PM PDT 24 | May 30 03:49:33 PM PDT 24 | 6051149730 ps | ||
| T2847 | /workspace/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.2435937557 | May 30 03:52:56 PM PDT 24 | May 30 03:54:21 PM PDT 24 | 4989395990 ps | ||
| T2848 | /workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.288540370 | May 30 03:49:18 PM PDT 24 | May 30 03:51:02 PM PDT 24 | 9914352809 ps | ||
| T2849 | /workspace/coverage/cover_reg_top/38.xbar_random_large_delays.2349579675 | May 30 03:52:24 PM PDT 24 | May 30 03:56:11 PM PDT 24 | 21759866627 ps | ||
| T2850 | /workspace/coverage/cover_reg_top/56.xbar_stress_all.1847301095 | May 30 03:55:19 PM PDT 24 | May 30 03:57:47 PM PDT 24 | 2140966657 ps | ||
| T627 | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.3513892904 | May 30 03:51:03 PM PDT 24 | May 30 03:59:25 PM PDT 24 | 13351184327 ps | ||
| T2851 | /workspace/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.1150703196 | May 30 03:56:34 PM PDT 24 | May 30 04:34:43 PM PDT 24 | 127644592137 ps | ||
| T2852 | /workspace/coverage/cover_reg_top/20.xbar_stress_all.1245976101 | May 30 03:50:02 PM PDT 24 | May 30 03:54:14 PM PDT 24 | 2801243021 ps | ||
| T2853 | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.1415475148 | May 30 04:01:05 PM PDT 24 | May 30 04:02:28 PM PDT 24 | 1038960396 ps | ||
| T2854 | /workspace/coverage/cover_reg_top/14.xbar_random_large_delays.3813620153 | May 30 03:49:15 PM PDT 24 | May 30 04:01:03 PM PDT 24 | 71255669328 ps | ||
| T2855 | /workspace/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.235967577 | May 30 03:55:37 PM PDT 24 | May 30 03:56:13 PM PDT 24 | 918689638 ps | ||
| T2856 | /workspace/coverage/cover_reg_top/15.xbar_access_same_device.3508849849 | May 30 03:49:25 PM PDT 24 | May 30 03:49:48 PM PDT 24 | 393423752 ps | ||
| T2857 | /workspace/coverage/cover_reg_top/84.xbar_random_zero_delays.3776027978 | May 30 03:59:09 PM PDT 24 | May 30 03:59:44 PM PDT 24 | 334063803 ps | ||
| T2858 | /workspace/coverage/cover_reg_top/89.xbar_error_random.2895041733 | May 30 04:00:08 PM PDT 24 | May 30 04:00:15 PM PDT 24 | 78100845 ps | ||
| T2859 | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.3851890385 | May 30 03:58:27 PM PDT 24 | May 30 04:00:45 PM PDT 24 | 3103910011 ps | ||
| T2860 | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.343476728 | May 30 04:01:24 PM PDT 24 | May 30 04:01:43 PM PDT 24 | 11110073 ps | ||
| T2861 | /workspace/coverage/cover_reg_top/7.chip_tl_errors.3586905671 | May 30 03:48:52 PM PDT 24 | May 30 03:51:15 PM PDT 24 | 3438349520 ps | ||
| T2862 | /workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.1696073211 | May 30 03:50:02 PM PDT 24 | May 30 03:50:21 PM PDT 24 | 154846926 ps | ||
| T2863 | /workspace/coverage/cover_reg_top/25.xbar_random_zero_delays.545849712 | May 30 03:50:42 PM PDT 24 | May 30 03:51:05 PM PDT 24 | 210866984 ps | ||
| T2864 | /workspace/coverage/cover_reg_top/86.xbar_stress_all.138623273 | May 30 03:59:49 PM PDT 24 | May 30 04:00:58 PM PDT 24 | 1666331589 ps | ||
| T2865 | /workspace/coverage/cover_reg_top/6.xbar_stress_all.1663662830 | May 30 03:48:52 PM PDT 24 | May 30 03:53:23 PM PDT 24 | 6219219059 ps | ||
| T2866 | /workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.2517534452 | May 30 03:51:13 PM PDT 24 | May 30 03:58:32 PM PDT 24 | 26270970274 ps | ||
| T2867 | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.3827826885 | May 30 03:50:31 PM PDT 24 | May 30 03:57:03 PM PDT 24 | 6814367819 ps | ||
| T2868 | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.1107716494 | May 30 03:52:02 PM PDT 24 | May 30 03:55:21 PM PDT 24 | 2769493755 ps | ||
| T2869 | /workspace/coverage/cover_reg_top/63.xbar_smoke.2068911746 | May 30 03:56:05 PM PDT 24 | May 30 03:56:15 PM PDT 24 | 225905714 ps | ||
| T2870 | /workspace/coverage/cover_reg_top/79.xbar_stress_all.2291807979 | May 30 03:58:32 PM PDT 24 | May 30 03:59:17 PM PDT 24 | 1287766658 ps | ||
| T2871 | /workspace/coverage/cover_reg_top/17.xbar_random_large_delays.1484297237 | May 30 03:49:16 PM PDT 24 | May 30 03:50:31 PM PDT 24 | 6889432780 ps | ||
| T2872 | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.968035245 | May 30 03:55:55 PM PDT 24 | May 30 03:58:49 PM PDT 24 | 532888557 ps | ||
| T2873 | /workspace/coverage/cover_reg_top/78.xbar_smoke_large_delays.1875892276 | May 30 03:58:31 PM PDT 24 | May 30 04:00:13 PM PDT 24 | 9594723378 ps | ||
| T2874 | /workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.2310963379 | May 30 03:48:42 PM PDT 24 | May 30 03:48:52 PM PDT 24 | 162348628 ps | ||
| T40 | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.481505429 | May 30 04:01:35 PM PDT 24 | May 30 04:04:50 PM PDT 24 | 5157809415 ps | ||
| T41 | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2542601044 | May 30 04:01:32 PM PDT 24 | May 30 04:05:39 PM PDT 24 | 4814500168 ps | ||
| T42 | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3465449281 | May 30 04:01:36 PM PDT 24 | May 30 04:05:33 PM PDT 24 | 4331547445 ps | ||
| T188 | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1341210892 | May 30 04:01:37 PM PDT 24 | May 30 04:05:53 PM PDT 24 | 4466690102 ps | ||
| T187 | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.704438347 | May 30 04:01:40 PM PDT 24 | May 30 04:06:40 PM PDT 24 | 4561731918 ps | ||
| T189 | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3671563782 | May 30 04:01:35 PM PDT 24 | May 30 04:06:48 PM PDT 24 | 4505717098 ps | ||
| T190 | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.3573255103 | May 30 04:01:39 PM PDT 24 | May 30 04:05:48 PM PDT 24 | 4134021570 ps | ||
| T191 | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3431310560 | May 30 04:01:38 PM PDT 24 | May 30 04:07:03 PM PDT 24 | 5395356800 ps | ||
| T192 | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3542712953 | May 30 04:01:36 PM PDT 24 | May 30 04:05:50 PM PDT 24 | 5071828776 ps | ||
| T193 | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2819108315 | May 30 04:01:32 PM PDT 24 | May 30 04:06:12 PM PDT 24 | 4804286284 ps |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4025569188 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 24297064426 ps |
| CPU time | 2261.94 seconds |
| Started | May 30 04:20:29 PM PDT 24 |
| Finished | May 30 04:58:12 PM PDT 24 |
| Peak memory | 605952 kb |
| Host | smart-0dd29bbd-beea-4939-8e58-def7f9fbd23e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4025569188 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4025569188 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_rw.1474063326 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 5874587214 ps |
| CPU time | 569.36 seconds |
| Started | May 30 03:48:49 PM PDT 24 |
| Finished | May 30 03:58:21 PM PDT 24 |
| Peak memory | 591872 kb |
| Host | smart-c7185b0e-530f-440d-a220-e053fdf4a9b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474063326 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_rw.1474063326 |
| Directory | /workspace/3.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.1227764513 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 9267554777 ps |
| CPU time | 341.69 seconds |
| Started | May 30 03:50:44 PM PDT 24 |
| Finished | May 30 03:56:27 PM PDT 24 |
| Peak memory | 573236 kb |
| Host | smart-0d0274eb-37c4-437d-aca3-4b52536e4d34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227764513 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.1227764513 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_10.1359490297 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 3741957496 ps |
| CPU time | 427.9 seconds |
| Started | May 30 04:17:24 PM PDT 24 |
| Finished | May 30 04:24:33 PM PDT 24 |
| Peak memory | 603760 kb |
| Host | smart-477a239c-bcdb-47b7-b1d1-c8f42af753bb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359490297 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_10.1359490297 |
| Directory | /workspace/1.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.3305502177 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 131595172913 ps |
| CPU time | 2262.65 seconds |
| Started | May 30 03:49:21 PM PDT 24 |
| Finished | May 30 04:27:05 PM PDT 24 |
| Peak memory | 573280 kb |
| Host | smart-27dabb2c-10dd-47c2-8f77-e9263531af2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305502177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_ device_slow_rsp.3305502177 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.481505429 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 5157809415 ps |
| CPU time | 194.41 seconds |
| Started | May 30 04:01:35 PM PDT 24 |
| Finished | May 30 04:04:50 PM PDT 24 |
| Peak memory | 639720 kb |
| Host | smart-84a7ce27-539b-4611-af5a-d468a9906768 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481505429 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 5.chip_padctrl_attributes.481505429 |
| Directory | /workspace/5.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.3303783661 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 12141236664 ps |
| CPU time | 2616.21 seconds |
| Started | May 30 04:19:08 PM PDT 24 |
| Finished | May 30 05:02:46 PM PDT 24 |
| Peak memory | 604652 kb |
| Host | smart-6c804998-4814-4bb3-bb0a-821c488013f2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33037 83661 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.3303783661 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.1903978873 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 73024574267 ps |
| CPU time | 1351.13 seconds |
| Started | May 30 03:54:14 PM PDT 24 |
| Finished | May 30 04:16:47 PM PDT 24 |
| Peak memory | 573360 kb |
| Host | smart-1c6d6398-18c7-4e79-888b-f163bd1a3928 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903978873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_ device_slow_rsp.1903978873 |
| Directory | /workspace/50.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_test.2595960547 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 3214120648 ps |
| CPU time | 372.48 seconds |
| Started | May 30 04:11:55 PM PDT 24 |
| Finished | May 30 04:18:08 PM PDT 24 |
| Peak memory | 603560 kb |
| Host | smart-730d0045-64ef-4b1f-997f-bafe41bd1995 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595960547 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.chip_sw_alert_test.2595960547 |
| Directory | /workspace/0.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3303016173 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 2463234726 ps |
| CPU time | 297.15 seconds |
| Started | May 30 04:25:29 PM PDT 24 |
| Finished | May 30 04:30:28 PM PDT 24 |
| Peak memory | 603568 kb |
| Host | smart-dfeee879-48b1-4709-8089-3fd5b2f6f021 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303 016173 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.3303016173 |
| Directory | /workspace/2.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.2190590216 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 5556329716 ps |
| CPU time | 475.77 seconds |
| Started | May 30 03:57:37 PM PDT 24 |
| Finished | May 30 04:05:33 PM PDT 24 |
| Peak memory | 573212 kb |
| Host | smart-d1086ee2-496a-4149-a1a4-a086922f3923 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190590216 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_al l_with_reset_error.2190590216 |
| Directory | /workspace/73.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.442172792 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 46705541102 ps |
| CPU time | 5009.93 seconds |
| Started | May 30 04:28:39 PM PDT 24 |
| Finished | May 30 05:52:11 PM PDT 24 |
| Peak memory | 612388 kb |
| Host | smart-918c92b9-bae9-4d8e-8c24-a6b9ebe52940 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442172792 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_prod.442172792 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.4064809813 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 106668848179 ps |
| CPU time | 1836.93 seconds |
| Started | May 30 03:51:39 PM PDT 24 |
| Finished | May 30 04:22:17 PM PDT 24 |
| Peak memory | 573380 kb |
| Host | smart-c1e595a6-7c00-4b1b-b393-a9960db8ffac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064809813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_ device_slow_rsp.4064809813 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_csr_rw.3081121853 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 20548844740 ps |
| CPU time | 2708.98 seconds |
| Started | May 30 04:03:14 PM PDT 24 |
| Finished | May 30 04:48:24 PM PDT 24 |
| Peak memory | 598736 kb |
| Host | smart-7a0b5118-8938-4714-a729-a1ae9c7b80bb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081121853 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_jtag_csr_rw.3081121853 |
| Directory | /workspace/0.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_0.3278467739 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 5590370296 ps |
| CPU time | 1148.42 seconds |
| Started | May 30 04:11:21 PM PDT 24 |
| Finished | May 30 04:30:30 PM PDT 24 |
| Peak memory | 603804 kb |
| Host | smart-af4cd6a9-b47e-42ca-ae5e-430f7fac7ad3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278467739 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_plic_all_irqs_0.3278467739 |
| Directory | /workspace/0.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2721688570 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 13694827084 ps |
| CPU time | 3242.03 seconds |
| Started | May 30 04:22:48 PM PDT 24 |
| Finished | May 30 05:16:51 PM PDT 24 |
| Peak memory | 604320 kb |
| Host | smart-7a796173-558b-439e-8934-47227210399f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721688570 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2721688570 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1441209509 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 2072824416 ps |
| CPU time | 273.57 seconds |
| Started | May 30 04:13:15 PM PDT 24 |
| Finished | May 30 04:17:50 PM PDT 24 |
| Peak memory | 603756 kb |
| Host | smart-c063a2f8-20fb-406b-9279-90d9f6df1966 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1441209509 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.1441209509 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.138641844 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 145406430003 ps |
| CPU time | 2680.01 seconds |
| Started | May 30 03:55:45 PM PDT 24 |
| Finished | May 30 04:40:27 PM PDT 24 |
| Peak memory | 573304 kb |
| Host | smart-2d231671-7e61-4048-af6a-00e51a3dd99e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138641844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_d evice_slow_rsp.138641844 |
| Directory | /workspace/61.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_20.2089444832 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 4405277176 ps |
| CPU time | 799.4 seconds |
| Started | May 30 04:13:53 PM PDT 24 |
| Finished | May 30 04:27:14 PM PDT 24 |
| Peak memory | 603848 kb |
| Host | smart-05f74e36-1182-4a82-800a-a0c559a98571 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089444832 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_20.2089444832 |
| Directory | /workspace/0.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.2338654005 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 113769377278 ps |
| CPU time | 2043.46 seconds |
| Started | May 30 03:52:13 PM PDT 24 |
| Finished | May 30 04:26:18 PM PDT 24 |
| Peak memory | 573276 kb |
| Host | smart-b00dec95-bdf7-457d-a828-5ea13df782ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338654005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_ device_slow_rsp.2338654005 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3057571140 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 70362931696 ps |
| CPU time | 1216.39 seconds |
| Started | May 30 03:49:18 PM PDT 24 |
| Finished | May 30 04:09:37 PM PDT 24 |
| Peak memory | 573168 kb |
| Host | smart-54451dac-e8a8-4f9d-bf3c-c5d395952d4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057571140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_ device_slow_rsp.3057571140 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3773361687 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 5011162604 ps |
| CPU time | 388.86 seconds |
| Started | May 30 04:29:29 PM PDT 24 |
| Finished | May 30 04:35:59 PM PDT 24 |
| Peak memory | 604148 kb |
| Host | smart-fc970f2f-e9a4-4d88-95e7-2848062cf01e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37733616 87 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3773361687 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_tl_errors.1576708760 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 4634488999 ps |
| CPU time | 404.5 seconds |
| Started | May 30 03:48:24 PM PDT 24 |
| Finished | May 30 03:55:09 PM PDT 24 |
| Peak memory | 594084 kb |
| Host | smart-0dfed42e-89a5-42c1-b04c-520841f961a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576708760 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_tl_errors.1576708760 |
| Directory | /workspace/0.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio_smoketest.1729523393 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 3409937456 ps |
| CPU time | 355.48 seconds |
| Started | May 30 04:22:44 PM PDT 24 |
| Finished | May 30 04:28:41 PM PDT 24 |
| Peak memory | 604864 kb |
| Host | smart-5a74031f-4298-4efe-9e96-791019fccb55 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729523393 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_gpio_smoketest.1729523393 |
| Directory | /workspace/1.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_plic_sw_irq.3867289078 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 2479758876 ps |
| CPU time | 265.91 seconds |
| Started | May 30 04:19:34 PM PDT 24 |
| Finished | May 30 04:24:00 PM PDT 24 |
| Peak memory | 604464 kb |
| Host | smart-22560362-9c48-46a5-8946-80c1097d0b29 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867289078 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_plic_sw_irq.3867289078 |
| Directory | /workspace/1.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device.3821589695 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 2767275884 ps |
| CPU time | 118.75 seconds |
| Started | May 30 03:57:06 PM PDT 24 |
| Finished | May 30 03:59:05 PM PDT 24 |
| Peak memory | 573068 kb |
| Host | smart-14e70834-94e1-4c6c-9bae-46aff50c62b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821589695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device .3821589695 |
| Directory | /workspace/70.xbar_access_same_device/latest |
| Test location | /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.3028648427 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 3550608972 ps |
| CPU time | 382.69 seconds |
| Started | May 30 04:35:46 PM PDT 24 |
| Finished | May 30 04:42:09 PM PDT 24 |
| Peak memory | 639496 kb |
| Host | smart-7705226a-3006-4d29-a2d1-13df5c48dbf8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028648427 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3028648427 |
| Directory | /workspace/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.3587098334 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 1411213643 ps |
| CPU time | 106.42 seconds |
| Started | May 30 03:57:18 PM PDT 24 |
| Finished | May 30 03:59:05 PM PDT 24 |
| Peak memory | 573076 kb |
| Host | smart-bc0003b9-531b-4338-ab5b-6aa47bfa9eb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587098334 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_error.3587098334 |
| Directory | /workspace/71.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.4060958121 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 18848866992 ps |
| CPU time | 1610.69 seconds |
| Started | May 30 04:20:23 PM PDT 24 |
| Finished | May 30 04:47:14 PM PDT 24 |
| Peak memory | 605408 kb |
| Host | smart-ce9c5b90-fa01-4900-b27e-c7a8f819d9cd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=4060958121 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.4060958121 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1127816375 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 30079727007 ps |
| CPU time | 4415.34 seconds |
| Started | May 30 04:12:44 PM PDT 24 |
| Finished | May 30 05:26:22 PM PDT 24 |
| Peak memory | 603820 kb |
| Host | smart-fc3007ac-da57-469e-91b4-49823f2cbe5a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=180_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127816375 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _csrng_edn_concurrency_reduced_freq.1127816375 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.2831076890 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 30416958382 ps |
| CPU time | 4251.07 seconds |
| Started | May 30 03:49:19 PM PDT 24 |
| Finished | May 30 05:00:13 PM PDT 24 |
| Peak memory | 588052 kb |
| Host | smart-b16987d0-5335-4c68-bbf2-aaeea44492c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831076890 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 16.chip_same_csr_outstanding.2831076890 |
| Directory | /workspace/16.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_large_delays.3123096337 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 45787869195 ps |
| CPU time | 471 seconds |
| Started | May 30 04:01:16 PM PDT 24 |
| Finished | May 30 04:09:08 PM PDT 24 |
| Peak memory | 573156 kb |
| Host | smart-bbf9b12f-53d4-4879-98fa-c21b06b36e83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123096337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_large_delays.3123096337 |
| Directory | /workspace/98.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_csr_rw.2086984306 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 13991623432 ps |
| CPU time | 1506.43 seconds |
| Started | May 30 04:12:35 PM PDT 24 |
| Finished | May 30 04:37:42 PM PDT 24 |
| Peak memory | 598268 kb |
| Host | smart-1ea03892-b268-485c-8beb-63f450585bff |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086984306 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_jtag_csr_rw.2086984306 |
| Directory | /workspace/1.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.1247453378 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 43495762492 ps |
| CPU time | 4275.68 seconds |
| Started | May 30 04:25:25 PM PDT 24 |
| Finished | May 30 05:36:43 PM PDT 24 |
| Peak memory | 612172 kb |
| Host | smart-fe5eba11-4036-4182-9aef-2a99d0b3fbd7 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1247453378 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_rma_unlocked.1247453378 |
| Directory | /workspace/2.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.1070449860 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 61713882321 ps |
| CPU time | 1190.52 seconds |
| Started | May 30 03:59:09 PM PDT 24 |
| Finished | May 30 04:19:01 PM PDT 24 |
| Peak memory | 573244 kb |
| Host | smart-46a47103-13ae-4ef3-a2a2-83cbcb7df6ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070449860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_ device_slow_rsp.1070449860 |
| Directory | /workspace/83.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.3485545225 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 21589579336 ps |
| CPU time | 1551.85 seconds |
| Started | May 30 04:28:07 PM PDT 24 |
| Finished | May 30 04:54:00 PM PDT 24 |
| Peak memory | 608656 kb |
| Host | smart-4a6a880f-aaeb-43c5-8b25-fa3b3c2b08f1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34855452 25 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.3485545225 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/3.chip_sw_all_escalation_resets.3527791789 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 5495474072 ps |
| CPU time | 706.05 seconds |
| Started | May 30 04:31:58 PM PDT 24 |
| Finished | May 30 04:43:45 PM PDT 24 |
| Peak memory | 611292 kb |
| Host | smart-07053a91-f179-4be0-881b-e072709fad02 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3527791789 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.3527791789 |
| Directory | /workspace/3.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.1630225156 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 89502362078 ps |
| CPU time | 1707.55 seconds |
| Started | May 30 03:56:47 PM PDT 24 |
| Finished | May 30 04:25:16 PM PDT 24 |
| Peak memory | 573332 kb |
| Host | smart-85b4bdb1-ce55-4c46-af3b-c200ee21d0e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630225156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_ device_slow_rsp.1630225156 |
| Directory | /workspace/68.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2168140122 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 7405300560 ps |
| CPU time | 634.44 seconds |
| Started | May 30 04:32:38 PM PDT 24 |
| Finished | May 30 04:43:14 PM PDT 24 |
| Peak memory | 604268 kb |
| Host | smart-7bc169a7-424e-4a9c-ae40-6ba28f8687e7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21681401 22 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.2168140122 |
| Directory | /workspace/4.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1235196643 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 3017049569 ps |
| CPU time | 291.21 seconds |
| Started | May 30 04:09:20 PM PDT 24 |
| Finished | May 30 04:14:13 PM PDT 24 |
| Peak memory | 603248 kb |
| Host | smart-75b9b233-9648-4f5d-aa1d-26bcdd1b3d11 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235 196643 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.1235196643 |
| Directory | /workspace/0.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3768741533 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 11387668080 ps |
| CPU time | 1322.81 seconds |
| Started | May 30 04:30:44 PM PDT 24 |
| Finished | May 30 04:52:47 PM PDT 24 |
| Peak memory | 605568 kb |
| Host | smart-b5d03602-5dff-4703-940d-7539f28c4e37 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768741533 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_sleep_mode_pings.3768741533 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.3586839302 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 58225587792 ps |
| CPU time | 9833.63 seconds |
| Started | May 30 04:23:56 PM PDT 24 |
| Finished | May 30 07:07:52 PM PDT 24 |
| Peak memory | 619492 kb |
| Host | smart-906c6a83-abce-412f-81bc-a6862d1b7622 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3586839302 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_exit_test_unlocked_bootstrap.3586839302 |
| Directory | /workspace/2.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all.3291665804 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 22468991167 ps |
| CPU time | 800.91 seconds |
| Started | May 30 03:54:15 PM PDT 24 |
| Finished | May 30 04:07:38 PM PDT 24 |
| Peak memory | 577856 kb |
| Host | smart-053427dc-45ee-4a4d-bb56-797e0a6780dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291665804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.3291665804 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_tl_errors.247020437 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 4229861263 ps |
| CPU time | 316.42 seconds |
| Started | May 30 03:48:57 PM PDT 24 |
| Finished | May 30 03:54:15 PM PDT 24 |
| Peak memory | 593928 kb |
| Host | smart-fd55b7c4-6ba9-45ee-a4cc-d678db912bed |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247020437 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_tl_errors.247020437 |
| Directory | /workspace/9.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_csr_rw.1396873104 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 20248339494 ps |
| CPU time | 2501.3 seconds |
| Started | May 30 04:21:54 PM PDT 24 |
| Finished | May 30 05:03:36 PM PDT 24 |
| Peak memory | 598644 kb |
| Host | smart-a6967705-fd7b-44cd-9b21-6d62ec42fd12 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396873104 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_jtag_csr_rw.1396873104 |
| Directory | /workspace/2.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/4.chip_sw_data_integrity_escalation.4170844596 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 5457590670 ps |
| CPU time | 750.87 seconds |
| Started | May 30 04:33:34 PM PDT 24 |
| Finished | May 30 04:46:06 PM PDT 24 |
| Peak memory | 604496 kb |
| Host | smart-9c00c79a-6643-403b-ba31-68eddfc81987 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4170844596 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.4170844596 |
| Directory | /workspace/4.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_retention.29725494 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4351348768 ps |
| CPU time | 419.3 seconds |
| Started | May 30 04:09:06 PM PDT 24 |
| Finished | May 30 04:16:06 PM PDT 24 |
| Peak memory | 604272 kb |
| Host | smart-7b6edabd-3b5e-4e12-9c88-0600bbd63eca |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29725494 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_retention.29725494 |
| Directory | /workspace/0.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.3365036702 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 4180825479 ps |
| CPU time | 502.78 seconds |
| Started | May 30 04:09:04 PM PDT 24 |
| Finished | May 30 04:17:27 PM PDT 24 |
| Peak memory | 621460 kb |
| Host | smart-b4d7176b-8d42-420f-99f3-9fc2d2c0afaa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365036702 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.3365036702 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2850284154 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 4777584008 ps |
| CPU time | 615.29 seconds |
| Started | May 30 04:33:13 PM PDT 24 |
| Finished | May 30 04:43:30 PM PDT 24 |
| Peak memory | 612048 kb |
| Host | smart-648ff933-4b59-4d39-87db-2e14efd20bfd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850284154 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.2850284154 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.2990304630 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 5919369933 ps |
| CPU time | 740.61 seconds |
| Started | May 30 03:56:55 PM PDT 24 |
| Finished | May 30 04:09:17 PM PDT 24 |
| Peak memory | 573232 kb |
| Host | smart-f1217ff9-bd1c-48ec-b8ce-bacde42f56f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990304630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all _with_rand_reset.2990304630 |
| Directory | /workspace/69.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1487290751 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 4746521677 ps |
| CPU time | 681.38 seconds |
| Started | May 30 04:13:10 PM PDT 24 |
| Finished | May 30 04:24:33 PM PDT 24 |
| Peak memory | 604384 kb |
| Host | smart-52e1fbfc-77ba-40f1-a7b2-923dd94add29 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487290751 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1487290751 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.1412601368 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 45289205375 ps |
| CPU time | 5210.79 seconds |
| Started | May 30 04:09:33 PM PDT 24 |
| Finished | May 30 05:36:25 PM PDT 24 |
| Peak memory | 611372 kb |
| Host | smart-92244623-dafb-465c-9f09-77598c7815e0 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412601368 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_rma.1412601368 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/24.chip_sw_all_escalation_resets.2857656701 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 4984438448 ps |
| CPU time | 540.58 seconds |
| Started | May 30 04:37:32 PM PDT 24 |
| Finished | May 30 04:46:34 PM PDT 24 |
| Peak memory | 640840 kb |
| Host | smart-d72a9d52-40f9-447f-92b3-3abad1890d94 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2857656701 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.2857656701 |
| Directory | /workspace/24.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_0.1189013651 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 5593372194 ps |
| CPU time | 808.15 seconds |
| Started | May 30 04:30:17 PM PDT 24 |
| Finished | May 30 04:43:46 PM PDT 24 |
| Peak memory | 603636 kb |
| Host | smart-024ee441-f55f-4c16-add3-7fddf34b122f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189013651 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_plic_all_irqs_0.1189013651 |
| Directory | /workspace/2.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.700780624 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 43772295660 ps |
| CPU time | 5364.96 seconds |
| Started | May 30 04:17:43 PM PDT 24 |
| Finished | May 30 05:47:09 PM PDT 24 |
| Peak memory | 620456 kb |
| Host | smart-ee5d95ea-808b-4fd5-a6fc-a5d3c4ceca15 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=700780624 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_rma_unlocked.700780624 |
| Directory | /workspace/1.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_entropy.1516758579 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 2950587898 ps |
| CPU time | 356.06 seconds |
| Started | May 30 04:25:20 PM PDT 24 |
| Finished | May 30 04:31:17 PM PDT 24 |
| Peak memory | 603444 kb |
| Host | smart-3c3af346-130f-40bd-b324-9978d2778d23 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516758579 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_entropy.1516758579 |
| Directory | /workspace/2.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3160230083 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 3398452248 ps |
| CPU time | 537.7 seconds |
| Started | May 30 04:37:33 PM PDT 24 |
| Finished | May 30 04:46:32 PM PDT 24 |
| Peak memory | 639496 kb |
| Host | smart-6bf21a63-fbc8-49bd-bf09-10ea64849550 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160230083 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3160230083 |
| Directory | /workspace/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/56.chip_sw_all_escalation_resets.594171910 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 6309093818 ps |
| CPU time | 557.01 seconds |
| Started | May 30 04:40:14 PM PDT 24 |
| Finished | May 30 04:49:32 PM PDT 24 |
| Peak memory | 640572 kb |
| Host | smart-1e5f0c73-2f81-4230-ace2-4a008bb43480 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 594171910 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.594171910 |
| Directory | /workspace/56.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_all_escalation_resets.11441257 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 5163401384 ps |
| CPU time | 698.67 seconds |
| Started | May 30 04:15:57 PM PDT 24 |
| Finished | May 30 04:27:37 PM PDT 24 |
| Peak memory | 640352 kb |
| Host | smart-2aabadd5-5319-4702-83f8-c368b2fe8798 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 11441257 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.11441257 |
| Directory | /workspace/1.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.4203698072 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 3591330394 ps |
| CPU time | 484.95 seconds |
| Started | May 30 04:37:31 PM PDT 24 |
| Finished | May 30 04:45:37 PM PDT 24 |
| Peak memory | 638152 kb |
| Host | smart-0fd8fa3f-f159-41aa-8ebc-ddbca6b272c5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203698072 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4203698072 |
| Directory | /workspace/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all.1976332368 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 21036871929 ps |
| CPU time | 657.69 seconds |
| Started | May 30 03:49:14 PM PDT 24 |
| Finished | May 30 04:00:15 PM PDT 24 |
| Peak memory | 573284 kb |
| Host | smart-9c35f65f-bec6-4dd1-9aa3-c52a09cb0b2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976332368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.1976332368 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.2937937753 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 12304037608 ps |
| CPU time | 2222.09 seconds |
| Started | May 30 04:23:50 PM PDT 24 |
| Finished | May 30 05:00:53 PM PDT 24 |
| Peak memory | 604708 kb |
| Host | smart-2beff83c-71f1-48ca-85f1-9b546b1e472d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293793 7753 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_aes.2937937753 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.476013744 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 2921104175 ps |
| CPU time | 255.24 seconds |
| Started | May 30 04:14:53 PM PDT 24 |
| Finished | May 30 04:19:09 PM PDT 24 |
| Peak memory | 603620 kb |
| Host | smart-d1eef1a9-6b95-4e6d-8094-5626197a94fc |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4760 13744 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.476013744 |
| Directory | /workspace/1.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_rma.1222652276 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 6802524188 ps |
| CPU time | 624.61 seconds |
| Started | May 30 04:20:11 PM PDT 24 |
| Finished | May 30 04:30:37 PM PDT 24 |
| Peak memory | 622632 kb |
| Host | smart-4e6abc10-c7eb-4307-9e25-b0843359c8aa |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222652276 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_rma.1222652276 |
| Directory | /workspace/1.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_tl_errors.2267014943 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 4465804330 ps |
| CPU time | 265.42 seconds |
| Started | May 30 03:48:35 PM PDT 24 |
| Finished | May 30 03:53:02 PM PDT 24 |
| Peak memory | 600728 kb |
| Host | smart-9c015e63-ea41-4a71-938e-1c199a1393b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267014943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_tl_errors.2267014943 |
| Directory | /workspace/2.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.1051125643 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 2687739953 ps |
| CPU time | 148.65 seconds |
| Started | May 30 04:10:20 PM PDT 24 |
| Finished | May 30 04:12:50 PM PDT 24 |
| Peak memory | 615900 kb |
| Host | smart-a1f679ed-73c2-4b84-ac59-82cf87cccea6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10511256 43 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.1051125643 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1154409977 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 17656059500 ps |
| CPU time | 5749.11 seconds |
| Started | May 30 04:21:42 PM PDT 24 |
| Finished | May 30 05:57:34 PM PDT 24 |
| Peak memory | 605032 kb |
| Host | smart-cca88563-1ce4-4260-8f5d-4f9afcc5d54f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154409977 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1154409977 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.3463812333 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 5486258080 ps |
| CPU time | 637.72 seconds |
| Started | May 30 03:52:58 PM PDT 24 |
| Finished | May 30 04:03:37 PM PDT 24 |
| Peak memory | 573332 kb |
| Host | smart-c0c95352-94fe-419f-9bbd-56e71946458d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463812333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all _with_rand_reset.3463812333 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_wake.1511184325 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4882813640 ps |
| CPU time | 461.03 seconds |
| Started | May 30 04:15:09 PM PDT 24 |
| Finished | May 30 04:22:50 PM PDT 24 |
| Peak memory | 604292 kb |
| Host | smart-6647e9dd-7f81-4f52-a590-65e6f5f45a9a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511184325 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.1511184325 |
| Directory | /workspace/1.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.646455140 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 76399534805 ps |
| CPU time | 12577.5 seconds |
| Started | May 30 04:11:32 PM PDT 24 |
| Finished | May 30 07:41:12 PM PDT 24 |
| Peak memory | 623500 kb |
| Host | smart-9a51440f-e93f-47e6-a742-c08e163793fb |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=80_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=646455140 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_bootstrap.646455140 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.1180066430 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 16722818355 ps |
| CPU time | 749.09 seconds |
| Started | May 30 03:49:00 PM PDT 24 |
| Finished | May 30 04:01:30 PM PDT 24 |
| Peak memory | 573292 kb |
| Host | smart-793625e6-1568-4d5d-9875-b20e677ab90c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180066430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_ with_rand_reset.1180066430 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init.4270656048 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 21889753516 ps |
| CPU time | 1880.98 seconds |
| Started | May 30 04:24:50 PM PDT 24 |
| Finished | May 30 04:56:13 PM PDT 24 |
| Peak memory | 607032 kb |
| Host | smart-71378bb4-4de3-4bff-a5b9-90ed696772d7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270656048 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init.4270656048 |
| Directory | /workspace/2.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_csr_rw.1258774426 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 4953141524 ps |
| CPU time | 472.32 seconds |
| Started | May 30 03:48:54 PM PDT 24 |
| Finished | May 30 03:56:48 PM PDT 24 |
| Peak memory | 593496 kb |
| Host | smart-09d4275f-e728-4dd8-9c4c-25d23b0a4eb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258774426 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_rw.1258774426 |
| Directory | /workspace/7.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.1545801394 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 4710272457 ps |
| CPU time | 241.77 seconds |
| Started | May 30 03:48:25 PM PDT 24 |
| Finished | May 30 03:52:28 PM PDT 24 |
| Peak memory | 658060 kb |
| Host | smart-5f6749f6-d5fc-48d6-9a85-1be9c7636975 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545801394 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_hw_r eset.1545801394 |
| Directory | /workspace/0.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.4042606821 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 44610161049 ps |
| CPU time | 4619.84 seconds |
| Started | May 30 04:09:48 PM PDT 24 |
| Finished | May 30 05:26:49 PM PDT 24 |
| Peak memory | 620248 kb |
| Host | smart-528a9084-2c33-4737-81f2-db649226185b |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4042606821 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_rma_unlocked.4042606821 |
| Directory | /workspace/0.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.2032455254 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 2696050718 ps |
| CPU time | 338.67 seconds |
| Started | May 30 03:59:24 PM PDT 24 |
| Finished | May 30 04:05:03 PM PDT 24 |
| Peak memory | 573180 kb |
| Host | smart-c256f24b-bffc-4d7c-ac29-8c68e49fb9d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032455254 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_al l_with_reset_error.2032455254 |
| Directory | /workspace/84.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_0.4130697781 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 5849832488 ps |
| CPU time | 1218.94 seconds |
| Started | May 30 04:18:40 PM PDT 24 |
| Finished | May 30 04:39:00 PM PDT 24 |
| Peak memory | 603840 kb |
| Host | smart-7d7548a1-0dca-4bf9-be61-ef6e35c54960 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130697781 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_plic_all_irqs_0.4130697781 |
| Directory | /workspace/1.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/cover_reg_top/27.chip_tl_errors.216603974 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 3679228032 ps |
| CPU time | 279.38 seconds |
| Started | May 30 03:50:50 PM PDT 24 |
| Finished | May 30 03:55:31 PM PDT 24 |
| Peak memory | 593980 kb |
| Host | smart-6f6d2300-c5f7-4504-b7f9-4ed2c06b2c33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216603974 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.chip_tl_errors.216603974 |
| Directory | /workspace/27.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1143664125 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 4046147428 ps |
| CPU time | 427.17 seconds |
| Started | May 30 04:10:20 PM PDT 24 |
| Finished | May 30 04:17:28 PM PDT 24 |
| Peak memory | 603520 kb |
| Host | smart-a1f3d1dd-2891-43dc-b303-151c7dac6dda |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_aon_pullup_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114366 4125 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_aon_pullup.1143664125 |
| Directory | /workspace/0.chip_sw_usbdev_aon_pullup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_wake.2571574610 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 3247107070 ps |
| CPU time | 361.66 seconds |
| Started | May 30 04:11:13 PM PDT 24 |
| Finished | May 30 04:17:17 PM PDT 24 |
| Peak memory | 603600 kb |
| Host | smart-0cea7755-4df4-4235-a7b8-4593473162ac |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571574610 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.2571574610 |
| Directory | /workspace/0.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_wake.2306866470 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 3275509916 ps |
| CPU time | 255.33 seconds |
| Started | May 30 04:25:18 PM PDT 24 |
| Finished | May 30 04:29:34 PM PDT 24 |
| Peak memory | 603844 kb |
| Host | smart-78748805-4ec6-4529-be36-161a527a4aef |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306866470 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.2306866470 |
| Directory | /workspace/2.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.3864348934 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 4675937746 ps |
| CPU time | 686.01 seconds |
| Started | May 30 04:11:29 PM PDT 24 |
| Finished | May 30 04:22:56 PM PDT 24 |
| Peak memory | 612500 kb |
| Host | smart-6e56feb9-d5eb-47cb-be14-184773239416 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864348934 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.3864348934 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.2360026659 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 2818927069 ps |
| CPU time | 423.36 seconds |
| Started | May 30 03:54:14 PM PDT 24 |
| Finished | May 30 04:01:19 PM PDT 24 |
| Peak memory | 573192 kb |
| Host | smart-36a76e14-caf5-4c0e-b051-655a7effe21d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360026659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all _with_rand_reset.2360026659 |
| Directory | /workspace/50.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_20.3835949351 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 4716157120 ps |
| CPU time | 842.62 seconds |
| Started | May 30 04:23:52 PM PDT 24 |
| Finished | May 30 04:37:55 PM PDT 24 |
| Peak memory | 603792 kb |
| Host | smart-facc0267-0c15-4f18-bc1b-a9885d2971dc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835949351 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_20.3835949351 |
| Directory | /workspace/1.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1371177402 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 5782239360 ps |
| CPU time | 628.42 seconds |
| Started | May 30 04:10:34 PM PDT 24 |
| Finished | May 30 04:21:04 PM PDT 24 |
| Peak memory | 605296 kb |
| Host | smart-8195aa65-5847-4dcd-8fba-7ae1041750f7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13711774 02 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.1371177402 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3607929083 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 4955171112 ps |
| CPU time | 824.83 seconds |
| Started | May 30 04:20:01 PM PDT 24 |
| Finished | May 30 04:33:47 PM PDT 24 |
| Peak memory | 604244 kb |
| Host | smart-cbd8dae0-7679-4dfd-a663-8df14357011f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36079290 83 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.3607929083 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.3306151329 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 13839994897 ps |
| CPU time | 795.37 seconds |
| Started | May 30 03:55:43 PM PDT 24 |
| Finished | May 30 04:09:00 PM PDT 24 |
| Peak memory | 581388 kb |
| Host | smart-8b80de66-c3b4-4375-869d-a8a3b997d8bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306151329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all _with_rand_reset.3306151329 |
| Directory | /workspace/61.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.2312159085 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 51004463032 ps |
| CPU time | 4952.36 seconds |
| Started | May 30 04:19:18 PM PDT 24 |
| Finished | May 30 05:41:52 PM PDT 24 |
| Peak memory | 611292 kb |
| Host | smart-5b5e2d20-1947-475e-9d1e-803cf2d6a1f6 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312159085 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_dev.2312159085 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.533121725 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 3928669000 ps |
| CPU time | 585.62 seconds |
| Started | May 30 04:31:53 PM PDT 24 |
| Finished | May 30 04:41:39 PM PDT 24 |
| Peak memory | 604056 kb |
| Host | smart-3b54cb06-8bd3-4de8-8186-c876b48b5f60 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53312172 5 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.533121725 |
| Directory | /workspace/3.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2363401521 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 2463285998 ps |
| CPU time | 132.66 seconds |
| Started | May 30 04:10:21 PM PDT 24 |
| Finished | May 30 04:12:35 PM PDT 24 |
| Peak memory | 610476 kb |
| Host | smart-e619098d-d041-46ea-a8c7-0c084598d2a2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363401521 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.2363401521 |
| Directory | /workspace/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.3285918314 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 2130580060 ps |
| CPU time | 279.23 seconds |
| Started | May 30 04:17:16 PM PDT 24 |
| Finished | May 30 04:21:56 PM PDT 24 |
| Peak memory | 603992 kb |
| Host | smart-9e4f6a79-133c-4d8d-96de-9d89a35cd057 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285918314 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_spi_host_tx_rx.3285918314 |
| Directory | /workspace/1.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.227511436 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 17901327393 ps |
| CPU time | 2258.76 seconds |
| Started | May 30 04:23:46 PM PDT 24 |
| Finished | May 30 05:01:27 PM PDT 24 |
| Peak memory | 604988 kb |
| Host | smart-709a1e31-7c89-4136-9e8f-372a5392884a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227511436 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_rst_inputs.227511436 |
| Directory | /workspace/1.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx.1542563806 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 4439756588 ps |
| CPU time | 646.83 seconds |
| Started | May 30 04:35:39 PM PDT 24 |
| Finished | May 30 04:46:28 PM PDT 24 |
| Peak memory | 612524 kb |
| Host | smart-89e6f4d5-402a-46a1-825d-7d9c06fb88e4 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542563806 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.1542563806 |
| Directory | /workspace/3.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.2568169421 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 15681597440 ps |
| CPU time | 930.09 seconds |
| Started | May 30 03:55:43 PM PDT 24 |
| Finished | May 30 04:11:14 PM PDT 24 |
| Peak memory | 573284 kb |
| Host | smart-1a905095-7f63-4cbd-9a36-4592c834cd89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568169421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all _with_rand_reset.2568169421 |
| Directory | /workspace/60.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/24.chip_tl_errors.4132861443 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 4559963788 ps |
| CPU time | 428.71 seconds |
| Started | May 30 03:50:32 PM PDT 24 |
| Finished | May 30 03:57:42 PM PDT 24 |
| Peak memory | 588644 kb |
| Host | smart-07c5a978-c1b4-4ef1-8e6c-084efd739514 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132861443 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.chip_tl_errors.4132861443 |
| Directory | /workspace/24.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_10.1454027995 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 4659884932 ps |
| CPU time | 757.56 seconds |
| Started | May 30 04:30:01 PM PDT 24 |
| Finished | May 30 04:42:40 PM PDT 24 |
| Peak memory | 603876 kb |
| Host | smart-5cf015ad-ef0b-4b1d-a4bf-63c3d7b5c9aa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454027995 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_10.1454027995 |
| Directory | /workspace/2.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.4059115659 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 8358304703 ps |
| CPU time | 434.97 seconds |
| Started | May 30 03:50:49 PM PDT 24 |
| Finished | May 30 03:58:05 PM PDT 24 |
| Peak memory | 573200 kb |
| Host | smart-f90c1cab-aa9f-48b1-a605-ecf277488e3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059115659 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_al l_with_reset_error.4059115659 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.2974614967 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 9104092172 ps |
| CPU time | 410.5 seconds |
| Started | May 30 03:50:51 PM PDT 24 |
| Finished | May 30 03:57:42 PM PDT 24 |
| Peak memory | 579888 kb |
| Host | smart-8c719e4f-8206-41be-b58e-0b39770f9b2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974614967 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_al l_with_reset_error.2974614967 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio.1325020322 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 3520682097 ps |
| CPU time | 388.1 seconds |
| Started | May 30 04:09:00 PM PDT 24 |
| Finished | May 30 04:15:29 PM PDT 24 |
| Peak memory | 603764 kb |
| Host | smart-2b7b1dd1-2fe7-4c78-8463-fb01acb81957 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325020322 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_gpio.1325020322 |
| Directory | /workspace/0.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.3945091280 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 4217722423 ps |
| CPU time | 721.43 seconds |
| Started | May 30 04:25:01 PM PDT 24 |
| Finished | May 30 04:37:04 PM PDT 24 |
| Peak memory | 603628 kb |
| Host | smart-33f94343-7140-439c-b0f8-1eeceb2853cf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3945091280 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.3945091280 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.498707034 |
| Short name | T2401 |
| Test name | |
| Test status | |
| Simulation time | 5961783256 ps |
| CPU time | 941.29 seconds |
| Started | May 30 03:52:45 PM PDT 24 |
| Finished | May 30 04:08:27 PM PDT 24 |
| Peak memory | 573192 kb |
| Host | smart-af90326c-7fbe-433e-82b1-7376afc5e515 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498707034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_ with_rand_reset.498707034 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.560931242 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 3861920332 ps |
| CPU time | 712.9 seconds |
| Started | May 30 04:11:14 PM PDT 24 |
| Finished | May 30 04:23:08 PM PDT 24 |
| Peak memory | 607752 kb |
| Host | smart-c57544d2-25a5-4ea8-be02-7b2ed1ca12c9 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560931242 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_cl kmgr_external_clk_src_for_sw_fast_dev.560931242 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.2471499035 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 7186919400 ps |
| CPU time | 767.2 seconds |
| Started | May 30 04:10:56 PM PDT 24 |
| Finished | May 30 04:23:45 PM PDT 24 |
| Peak memory | 604240 kb |
| Host | smart-18be9890-b66e-44bc-a4c1-cd27b0084bf0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471499035 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.2471499035 |
| Directory | /workspace/0.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.1247564612 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 5178246440 ps |
| CPU time | 194.36 seconds |
| Started | May 30 03:48:53 PM PDT 24 |
| Finished | May 30 03:52:09 PM PDT 24 |
| Peak memory | 657168 kb |
| Host | smart-b9cef041-c42a-4815-b4e2-c18f4eb80eb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247564612 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_hw_r eset.1247564612 |
| Directory | /workspace/3.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_tl_errors.2776376950 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 4043483693 ps |
| CPU time | 302.99 seconds |
| Started | May 30 03:48:59 PM PDT 24 |
| Finished | May 30 03:54:04 PM PDT 24 |
| Peak memory | 593952 kb |
| Host | smart-f40dfef4-d247-40d8-94e6-5bd1f13d0db5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776376950 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_tl_errors.2776376950 |
| Directory | /workspace/10.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/22.chip_tl_errors.2697071023 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 4572495600 ps |
| CPU time | 293.56 seconds |
| Started | May 30 03:50:20 PM PDT 24 |
| Finished | May 30 03:55:15 PM PDT 24 |
| Peak memory | 594092 kb |
| Host | smart-939d1404-0ab4-4628-8f47-4ee1d188064c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697071023 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.chip_tl_errors.2697071023 |
| Directory | /workspace/22.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_20.2157398787 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 4471762944 ps |
| CPU time | 825.26 seconds |
| Started | May 30 04:28:53 PM PDT 24 |
| Finished | May 30 04:42:40 PM PDT 24 |
| Peak memory | 603664 kb |
| Host | smart-c20d6add-1032-49c4-af1b-3cf51f4f1a8e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157398787 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_20.2157398787 |
| Directory | /workspace/2.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.28184308 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 4192457270 ps |
| CPU time | 625.38 seconds |
| Started | May 30 04:11:44 PM PDT 24 |
| Finished | May 30 04:22:11 PM PDT 24 |
| Peak memory | 612072 kb |
| Host | smart-5ffecc14-d41c-4772-8d5c-9243e8e75f34 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281843 08 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.28184308 |
| Directory | /workspace/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_config_host.1049844781 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 8008131324 ps |
| CPU time | 1925.23 seconds |
| Started | May 30 04:09:26 PM PDT 24 |
| Finished | May 30 04:41:33 PM PDT 24 |
| Peak memory | 603572 kb |
| Host | smart-e0b23db9-cd00-4962-9720-9ce878eebdd0 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_config_host_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10498 44781 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_config_host.1049844781 |
| Directory | /workspace/0.chip_sw_usbdev_config_host/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.2985709747 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 48165077879 ps |
| CPU time | 5260.96 seconds |
| Started | May 30 04:15:17 PM PDT 24 |
| Finished | May 30 05:43:00 PM PDT 24 |
| Peak memory | 610284 kb |
| Host | smart-821414c3-fe1e-4789-933e-701409bab1d9 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985709747 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chi p_sw_lc_walkthrough_prod.2985709747 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all.889277536 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 18489138543 ps |
| CPU time | 741.72 seconds |
| Started | May 30 03:56:46 PM PDT 24 |
| Finished | May 30 04:09:10 PM PDT 24 |
| Peak memory | 573244 kb |
| Host | smart-67ccbd56-195e-4d63-8b27-16c0d78d19db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889277536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all.889277536 |
| Directory | /workspace/68.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.3742718800 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 5322637696 ps |
| CPU time | 838.75 seconds |
| Started | May 30 04:27:40 PM PDT 24 |
| Finished | May 30 04:41:41 PM PDT 24 |
| Peak memory | 603580 kb |
| Host | smart-68b5f799-6b44-47e3-b67f-277f7fdda927 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742718800 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.3742718800 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2542601044 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 4814500168 ps |
| CPU time | 246.58 seconds |
| Started | May 30 04:01:32 PM PDT 24 |
| Finished | May 30 04:05:39 PM PDT 24 |
| Peak memory | 647948 kb |
| Host | smart-f89b98f6-f4e8-42e2-8424-88b8bedb7990 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542601044 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 0.chip_padctrl_attributes.2542601044 |
| Directory | /workspace/0.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/default/42.chip_sw_all_escalation_resets.203297577 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 5698277780 ps |
| CPU time | 523.13 seconds |
| Started | May 30 04:37:05 PM PDT 24 |
| Finished | May 30 04:45:49 PM PDT 24 |
| Peak memory | 639440 kb |
| Host | smart-45a3a0ba-d141-463c-a862-db0ba54e51c5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 203297577 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.203297577 |
| Directory | /workspace/42.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/72.chip_sw_all_escalation_resets.3697151083 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 5684026320 ps |
| CPU time | 652.94 seconds |
| Started | May 30 04:41:34 PM PDT 24 |
| Finished | May 30 04:52:28 PM PDT 24 |
| Peak memory | 639372 kb |
| Host | smart-c8154055-f294-4fd1-9a9d-d44c3b1ae0bd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3697151083 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.3697151083 |
| Directory | /workspace/72.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1477058823 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 1908521995 ps |
| CPU time | 117.76 seconds |
| Started | May 30 04:15:59 PM PDT 24 |
| Finished | May 30 04:17:57 PM PDT 24 |
| Peak memory | 612664 kb |
| Host | smart-9923c657-0be8-4739-9469-5ff46c8a1ae8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477058823 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.1477058823 |
| Directory | /workspace/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/36.chip_sw_all_escalation_resets.3562788615 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 4536073398 ps |
| CPU time | 496.29 seconds |
| Started | May 30 04:39:29 PM PDT 24 |
| Finished | May 30 04:47:46 PM PDT 24 |
| Peak memory | 639408 kb |
| Host | smart-d7c0b4e3-5d2d-40a9-8981-9babb9e7f2cb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3562788615 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.3562788615 |
| Directory | /workspace/36.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_large_delays.885887389 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 99653128937 ps |
| CPU time | 1167.37 seconds |
| Started | May 30 03:56:05 PM PDT 24 |
| Finished | May 30 04:15:34 PM PDT 24 |
| Peak memory | 573192 kb |
| Host | smart-03955140-b1b8-4806-b8d6-fdbc0572128c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885887389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_large_delays.885887389 |
| Directory | /workspace/63.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.4257958456 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 3188550748 ps |
| CPU time | 385.96 seconds |
| Started | May 30 04:38:02 PM PDT 24 |
| Finished | May 30 04:44:29 PM PDT 24 |
| Peak memory | 639808 kb |
| Host | smart-466ea148-cb29-40e5-b697-1d11262bfec8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257958456 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4257958456 |
| Directory | /workspace/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2748248125 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 5080464884 ps |
| CPU time | 434.82 seconds |
| Started | May 30 04:11:49 PM PDT 24 |
| Finished | May 30 04:19:04 PM PDT 24 |
| Peak memory | 613168 kb |
| Host | smart-f78e6197-61ce-410c-b5be-76aafecaf440 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748248125 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.2748248125 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.3108785231 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 1075833739 ps |
| CPU time | 212.39 seconds |
| Started | May 30 03:50:14 PM PDT 24 |
| Finished | May 30 03:53:47 PM PDT 24 |
| Peak memory | 573116 kb |
| Host | smart-50176998-f3d2-41bc-b8d0-ee4df57376be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108785231 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_al l_with_reset_error.3108785231 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2273102873 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 3815258590 ps |
| CPU time | 366.98 seconds |
| Started | May 30 04:11:37 PM PDT 24 |
| Finished | May 30 04:17:44 PM PDT 24 |
| Peak memory | 639452 kb |
| Host | smart-feb11031-6f20-442e-895b-daed1248c5fd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273102873 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_alert_handler_lpg_sleep_mode_alerts.2273102873 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/0.chip_sw_all_escalation_resets.896873177 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 5462663250 ps |
| CPU time | 724.26 seconds |
| Started | May 30 04:08:59 PM PDT 24 |
| Finished | May 30 04:21:04 PM PDT 24 |
| Peak memory | 639352 kb |
| Host | smart-27d2143e-69c1-4cd6-8306-2e1e86b51f62 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 896873177 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.896873177 |
| Directory | /workspace/0.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1926955769 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 4466004456 ps |
| CPU time | 498.28 seconds |
| Started | May 30 04:36:57 PM PDT 24 |
| Finished | May 30 04:45:16 PM PDT 24 |
| Peak memory | 639916 kb |
| Host | smart-ba8e048c-ecd4-4d32-8e51-5fa9f32cc215 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926955769 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1926955769 |
| Directory | /workspace/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3507167481 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 3821322444 ps |
| CPU time | 381.16 seconds |
| Started | May 30 04:34:16 PM PDT 24 |
| Finished | May 30 04:40:38 PM PDT 24 |
| Peak memory | 638184 kb |
| Host | smart-5368ec5e-a48f-4df9-b13e-981ea40756da |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507167481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3507167481 |
| Directory | /workspace/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/11.chip_sw_all_escalation_resets.1738300418 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 4706211582 ps |
| CPU time | 513.15 seconds |
| Started | May 30 04:34:15 PM PDT 24 |
| Finished | May 30 04:42:49 PM PDT 24 |
| Peak memory | 640560 kb |
| Host | smart-e8ba3ffd-33e3-41ff-b337-6b09f1ca6056 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1738300418 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.1738300418 |
| Directory | /workspace/11.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2233444011 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 2985725550 ps |
| CPU time | 439.02 seconds |
| Started | May 30 04:36:11 PM PDT 24 |
| Finished | May 30 04:43:31 PM PDT 24 |
| Peak memory | 639144 kb |
| Host | smart-b8c2f0d4-fca8-46a2-b739-0ee07ff0d2b9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233444011 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2233444011 |
| Directory | /workspace/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/12.chip_sw_all_escalation_resets.1425516703 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 4487885008 ps |
| CPU time | 651.41 seconds |
| Started | May 30 04:35:09 PM PDT 24 |
| Finished | May 30 04:46:01 PM PDT 24 |
| Peak memory | 639860 kb |
| Host | smart-6cf0b197-5f4c-4558-8a4f-9fa90dca08fc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1425516703 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.1425516703 |
| Directory | /workspace/12.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.3183814008 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 4133929818 ps |
| CPU time | 398.37 seconds |
| Started | May 30 04:36:58 PM PDT 24 |
| Finished | May 30 04:43:37 PM PDT 24 |
| Peak memory | 638648 kb |
| Host | smart-d34f4034-efcf-408b-b3ab-56ef3a68be6b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183814008 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3183814008 |
| Directory | /workspace/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/13.chip_sw_all_escalation_resets.606682589 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 5932492014 ps |
| CPU time | 545.52 seconds |
| Started | May 30 04:35:02 PM PDT 24 |
| Finished | May 30 04:44:09 PM PDT 24 |
| Peak memory | 639276 kb |
| Host | smart-c173997b-e28d-4004-98d5-1dd0c976ee48 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 606682589 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.606682589 |
| Directory | /workspace/13.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.1389571172 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 3491276438 ps |
| CPU time | 529.96 seconds |
| Started | May 30 04:35:03 PM PDT 24 |
| Finished | May 30 04:43:54 PM PDT 24 |
| Peak memory | 639568 kb |
| Host | smart-84d75062-a823-4de8-bdd1-e5293604b928 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389571172 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1389571172 |
| Directory | /workspace/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/15.chip_sw_all_escalation_resets.3708572067 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 5993239760 ps |
| CPU time | 708.08 seconds |
| Started | May 30 04:34:58 PM PDT 24 |
| Finished | May 30 04:46:46 PM PDT 24 |
| Peak memory | 639620 kb |
| Host | smart-e605f0be-054f-4cd7-b499-cc5ee62c80aa |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3708572067 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.3708572067 |
| Directory | /workspace/15.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2861627889 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 4372894520 ps |
| CPU time | 421.43 seconds |
| Started | May 30 04:35:15 PM PDT 24 |
| Finished | May 30 04:42:18 PM PDT 24 |
| Peak memory | 639712 kb |
| Host | smart-0d4d875b-8e32-422c-9d4e-13718f0a858f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861627889 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2861627889 |
| Directory | /workspace/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/17.chip_sw_all_escalation_resets.67267926 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 5079714292 ps |
| CPU time | 769.42 seconds |
| Started | May 30 04:34:28 PM PDT 24 |
| Finished | May 30 04:47:18 PM PDT 24 |
| Peak memory | 639412 kb |
| Host | smart-be5d04ab-c6b7-4b6d-a36d-c7b938c5dc24 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 67267926 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.67267926 |
| Directory | /workspace/17.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.1361175647 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 3404982296 ps |
| CPU time | 413.02 seconds |
| Started | May 30 04:37:28 PM PDT 24 |
| Finished | May 30 04:44:22 PM PDT 24 |
| Peak memory | 639584 kb |
| Host | smart-1c3f5c04-2817-4230-bd2a-c92f0462cf91 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361175647 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1361175647 |
| Directory | /workspace/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.225525544 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 4249830392 ps |
| CPU time | 336.2 seconds |
| Started | May 30 04:36:13 PM PDT 24 |
| Finished | May 30 04:41:50 PM PDT 24 |
| Peak memory | 638236 kb |
| Host | smart-f5380cc1-7606-4009-bc19-9c1d1a8d9ba3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225525544 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_s w_alert_handler_lpg_sleep_mode_alerts.225525544 |
| Directory | /workspace/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/19.chip_sw_all_escalation_resets.2309305327 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 4719576802 ps |
| CPU time | 494.33 seconds |
| Started | May 30 04:37:09 PM PDT 24 |
| Finished | May 30 04:45:25 PM PDT 24 |
| Peak memory | 639456 kb |
| Host | smart-d6ae0724-1886-4360-b946-6fe52dd7e8b9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2309305327 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.2309305327 |
| Directory | /workspace/19.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2665875251 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 4047398264 ps |
| CPU time | 537.51 seconds |
| Started | May 30 04:27:43 PM PDT 24 |
| Finished | May 30 04:36:42 PM PDT 24 |
| Peak memory | 639920 kb |
| Host | smart-6b3222ad-6996-478a-908d-092c8441f751 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665875251 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s w_alert_handler_lpg_sleep_mode_alerts.2665875251 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/2.chip_sw_all_escalation_resets.3609617410 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 5446980102 ps |
| CPU time | 684.66 seconds |
| Started | May 30 04:24:03 PM PDT 24 |
| Finished | May 30 04:35:29 PM PDT 24 |
| Peak memory | 639408 kb |
| Host | smart-9fd8fc83-c199-458f-8319-3d42f2027b72 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3609617410 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.3609617410 |
| Directory | /workspace/2.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/20.chip_sw_all_escalation_resets.4203951809 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 5037304936 ps |
| CPU time | 553.71 seconds |
| Started | May 30 04:35:38 PM PDT 24 |
| Finished | May 30 04:44:53 PM PDT 24 |
| Peak memory | 639356 kb |
| Host | smart-bc9a3913-138b-4251-ba7f-e596690246af |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4203951809 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.4203951809 |
| Directory | /workspace/20.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.854004978 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 3771431432 ps |
| CPU time | 388.9 seconds |
| Started | May 30 04:37:32 PM PDT 24 |
| Finished | May 30 04:44:02 PM PDT 24 |
| Peak memory | 639460 kb |
| Host | smart-6d232856-0299-4bba-917e-ce88368a74e6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854004978 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_s w_alert_handler_lpg_sleep_mode_alerts.854004978 |
| Directory | /workspace/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.1730543678 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 3870742948 ps |
| CPU time | 389.98 seconds |
| Started | May 30 04:35:34 PM PDT 24 |
| Finished | May 30 04:42:05 PM PDT 24 |
| Peak memory | 639576 kb |
| Host | smart-efc8928d-b1ba-4dad-b026-ec012f0b6635 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730543678 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1730543678 |
| Directory | /workspace/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.845922309 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 4242543848 ps |
| CPU time | 413.32 seconds |
| Started | May 30 04:36:15 PM PDT 24 |
| Finished | May 30 04:43:09 PM PDT 24 |
| Peak memory | 638172 kb |
| Host | smart-a1c6af3a-cb03-448a-8147-9447e5f874c3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845922309 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_s w_alert_handler_lpg_sleep_mode_alerts.845922309 |
| Directory | /workspace/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/25.chip_sw_all_escalation_resets.230527762 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 4814730800 ps |
| CPU time | 727.1 seconds |
| Started | May 30 04:36:14 PM PDT 24 |
| Finished | May 30 04:48:22 PM PDT 24 |
| Peak memory | 639596 kb |
| Host | smart-31deb489-ba78-420d-a716-68d7532df4ad |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 230527762 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.230527762 |
| Directory | /workspace/25.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/26.chip_sw_all_escalation_resets.3813922942 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 4563325360 ps |
| CPU time | 737.85 seconds |
| Started | May 30 04:36:04 PM PDT 24 |
| Finished | May 30 04:48:23 PM PDT 24 |
| Peak memory | 639508 kb |
| Host | smart-e4f54e41-4d43-4459-972d-8c4c2518d12e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3813922942 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.3813922942 |
| Directory | /workspace/26.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.107543059 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 3780952824 ps |
| CPU time | 428.99 seconds |
| Started | May 30 04:37:25 PM PDT 24 |
| Finished | May 30 04:44:36 PM PDT 24 |
| Peak memory | 638356 kb |
| Host | smart-2c3bb684-dfc2-45dd-802d-a3eb568d804e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107543059 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_s w_alert_handler_lpg_sleep_mode_alerts.107543059 |
| Directory | /workspace/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/27.chip_sw_all_escalation_resets.3319407303 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 4528359400 ps |
| CPU time | 559.93 seconds |
| Started | May 30 04:35:38 PM PDT 24 |
| Finished | May 30 04:44:59 PM PDT 24 |
| Peak memory | 639680 kb |
| Host | smart-0828158d-07e7-48ac-9b04-fc4c502c9a6c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3319407303 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.3319407303 |
| Directory | /workspace/27.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2024114657 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 3039887650 ps |
| CPU time | 486.18 seconds |
| Started | May 30 04:36:25 PM PDT 24 |
| Finished | May 30 04:44:32 PM PDT 24 |
| Peak memory | 639552 kb |
| Host | smart-254c1ad6-cda9-42cc-a65e-d0ba436ff41a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024114657 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2024114657 |
| Directory | /workspace/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.4002578072 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 3240326820 ps |
| CPU time | 477.2 seconds |
| Started | May 30 04:36:24 PM PDT 24 |
| Finished | May 30 04:44:22 PM PDT 24 |
| Peak memory | 639532 kb |
| Host | smart-cc89bc86-393e-401a-89f1-04ec9930ee53 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002578072 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4002578072 |
| Directory | /workspace/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.4117688525 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 3782214444 ps |
| CPU time | 364.56 seconds |
| Started | May 30 04:37:20 PM PDT 24 |
| Finished | May 30 04:43:26 PM PDT 24 |
| Peak memory | 639788 kb |
| Host | smart-17cb75f9-71a0-46d4-b250-16b35fbf5702 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117688525 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4117688525 |
| Directory | /workspace/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.703040679 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 3401095110 ps |
| CPU time | 404.4 seconds |
| Started | May 30 04:38:27 PM PDT 24 |
| Finished | May 30 04:45:12 PM PDT 24 |
| Peak memory | 639480 kb |
| Host | smart-c0b46060-5a31-4c0e-9909-ae95caac6960 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703040679 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_s w_alert_handler_lpg_sleep_mode_alerts.703040679 |
| Directory | /workspace/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/32.chip_sw_all_escalation_resets.3293553552 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 4471879530 ps |
| CPU time | 781.21 seconds |
| Started | May 30 04:37:01 PM PDT 24 |
| Finished | May 30 04:50:03 PM PDT 24 |
| Peak memory | 639320 kb |
| Host | smart-ca48de70-8e97-4863-8594-c8bc4e5f9a76 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3293553552 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_all_escalation_resets.3293553552 |
| Directory | /workspace/32.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3001137267 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 3956382444 ps |
| CPU time | 405.79 seconds |
| Started | May 30 04:37:52 PM PDT 24 |
| Finished | May 30 04:44:39 PM PDT 24 |
| Peak memory | 638284 kb |
| Host | smart-79accae0-4c32-4cf8-85f5-59e0acdc4521 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001137267 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3001137267 |
| Directory | /workspace/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2058060232 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 3416409172 ps |
| CPU time | 306.57 seconds |
| Started | May 30 04:37:23 PM PDT 24 |
| Finished | May 30 04:42:31 PM PDT 24 |
| Peak memory | 638244 kb |
| Host | smart-ce754b45-88b8-4dd3-ad90-bccd700803c7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058060232 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2058060232 |
| Directory | /workspace/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/38.chip_sw_all_escalation_resets.1062478392 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 4435606574 ps |
| CPU time | 653.54 seconds |
| Started | May 30 04:37:25 PM PDT 24 |
| Finished | May 30 04:48:19 PM PDT 24 |
| Peak memory | 639464 kb |
| Host | smart-f683bcf9-f50f-4756-bdfc-c9355877a5b5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1062478392 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.1062478392 |
| Directory | /workspace/38.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.885317949 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 3795840790 ps |
| CPU time | 442.99 seconds |
| Started | May 30 04:37:40 PM PDT 24 |
| Finished | May 30 04:45:05 PM PDT 24 |
| Peak memory | 639596 kb |
| Host | smart-149caab4-afc8-4f65-9456-33ca5ddfb1ea |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885317949 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_s w_alert_handler_lpg_sleep_mode_alerts.885317949 |
| Directory | /workspace/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/39.chip_sw_all_escalation_resets.2408185079 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 4892179074 ps |
| CPU time | 724 seconds |
| Started | May 30 04:37:29 PM PDT 24 |
| Finished | May 30 04:49:33 PM PDT 24 |
| Peak memory | 640416 kb |
| Host | smart-2cc30fe0-23e7-4c1c-8ad8-b473ed8cc5dd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2408185079 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.2408185079 |
| Directory | /workspace/39.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.418181591 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 3598349524 ps |
| CPU time | 457.37 seconds |
| Started | May 30 04:33:06 PM PDT 24 |
| Finished | May 30 04:40:44 PM PDT 24 |
| Peak memory | 639524 kb |
| Host | smart-64b786e0-0887-47c6-a9a2-c78de8b36f74 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418181591 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw _alert_handler_lpg_sleep_mode_alerts.418181591 |
| Directory | /workspace/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/41.chip_sw_all_escalation_resets.2997976241 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 5189724504 ps |
| CPU time | 611.8 seconds |
| Started | May 30 04:36:37 PM PDT 24 |
| Finished | May 30 04:46:50 PM PDT 24 |
| Peak memory | 639716 kb |
| Host | smart-62a9ead4-272a-4dd8-8e10-02e431f73aaa |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2997976241 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.2997976241 |
| Directory | /workspace/41.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.933496150 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 3645609340 ps |
| CPU time | 379.33 seconds |
| Started | May 30 04:37:50 PM PDT 24 |
| Finished | May 30 04:44:09 PM PDT 24 |
| Peak memory | 638228 kb |
| Host | smart-2bde42d6-c4f4-4a0b-8ffa-9d73e92a0f0f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933496150 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_s w_alert_handler_lpg_sleep_mode_alerts.933496150 |
| Directory | /workspace/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3089969479 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 3936605960 ps |
| CPU time | 273.67 seconds |
| Started | May 30 04:36:55 PM PDT 24 |
| Finished | May 30 04:41:29 PM PDT 24 |
| Peak memory | 639752 kb |
| Host | smart-59af5296-5e72-4b92-bc46-0f7017a9bcf0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089969479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3089969479 |
| Directory | /workspace/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/46.chip_sw_all_escalation_resets.3148332149 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 5794963552 ps |
| CPU time | 868.09 seconds |
| Started | May 30 04:38:57 PM PDT 24 |
| Finished | May 30 04:53:26 PM PDT 24 |
| Peak memory | 639492 kb |
| Host | smart-668d80f9-3ead-48d8-b783-5bc9db000016 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3148332149 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_all_escalation_resets.3148332149 |
| Directory | /workspace/46.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.126875867 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 3371116802 ps |
| CPU time | 320.56 seconds |
| Started | May 30 04:40:32 PM PDT 24 |
| Finished | May 30 04:45:53 PM PDT 24 |
| Peak memory | 639528 kb |
| Host | smart-f2ca039a-50bc-417e-99cb-4a183facb86e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126875867 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_s w_alert_handler_lpg_sleep_mode_alerts.126875867 |
| Directory | /workspace/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/5.chip_sw_all_escalation_resets.1682055088 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 5207137400 ps |
| CPU time | 576.4 seconds |
| Started | May 30 04:37:21 PM PDT 24 |
| Finished | May 30 04:46:59 PM PDT 24 |
| Peak memory | 639644 kb |
| Host | smart-0f0586ae-297a-4490-9cae-38e291e9e068 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1682055088 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.1682055088 |
| Directory | /workspace/5.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3214675965 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 4159992716 ps |
| CPU time | 370.72 seconds |
| Started | May 30 04:40:47 PM PDT 24 |
| Finished | May 30 04:46:59 PM PDT 24 |
| Peak memory | 638196 kb |
| Host | smart-ea9583d3-f138-41a1-ad71-d1415bb40eef |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214675965 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3214675965 |
| Directory | /workspace/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1074976079 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 3519383542 ps |
| CPU time | 371.33 seconds |
| Started | May 30 04:40:13 PM PDT 24 |
| Finished | May 30 04:46:25 PM PDT 24 |
| Peak memory | 638368 kb |
| Host | smart-227621d3-826d-4a00-9ba0-3e7baf6656ad |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074976079 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1074976079 |
| Directory | /workspace/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/55.chip_sw_all_escalation_resets.1199464185 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 5267206022 ps |
| CPU time | 431.67 seconds |
| Started | May 30 04:39:40 PM PDT 24 |
| Finished | May 30 04:46:52 PM PDT 24 |
| Peak memory | 639620 kb |
| Host | smart-9633b37c-b68a-48b6-942b-e90ad9c6548f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1199464185 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.1199464185 |
| Directory | /workspace/55.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.285375492 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 3104207870 ps |
| CPU time | 331.69 seconds |
| Started | May 30 04:41:29 PM PDT 24 |
| Finished | May 30 04:47:01 PM PDT 24 |
| Peak memory | 639504 kb |
| Host | smart-ab4ee7dc-1f72-4242-97c5-2d9f78dbfd1f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285375492 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_s w_alert_handler_lpg_sleep_mode_alerts.285375492 |
| Directory | /workspace/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/59.chip_sw_all_escalation_resets.2712189700 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 5753139272 ps |
| CPU time | 499.82 seconds |
| Started | May 30 04:39:51 PM PDT 24 |
| Finished | May 30 04:48:12 PM PDT 24 |
| Peak memory | 640424 kb |
| Host | smart-bfc4cf33-d062-4d8e-8f9b-608e9986cf2b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2712189700 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.2712189700 |
| Directory | /workspace/59.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/61.chip_sw_all_escalation_resets.2656840238 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 4145521450 ps |
| CPU time | 554.14 seconds |
| Started | May 30 04:40:01 PM PDT 24 |
| Finished | May 30 04:49:16 PM PDT 24 |
| Peak memory | 639052 kb |
| Host | smart-223daf6a-623d-462d-8a1c-2c3f491dcf82 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2656840238 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.2656840238 |
| Directory | /workspace/61.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/62.chip_sw_all_escalation_resets.187491013 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 5027260570 ps |
| CPU time | 501.78 seconds |
| Started | May 30 04:41:27 PM PDT 24 |
| Finished | May 30 04:49:49 PM PDT 24 |
| Peak memory | 639688 kb |
| Host | smart-d9a99309-973c-41e1-b0cb-6bb6cb849de7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 187491013 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.187491013 |
| Directory | /workspace/62.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2679644549 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 4034546480 ps |
| CPU time | 351.31 seconds |
| Started | May 30 04:41:57 PM PDT 24 |
| Finished | May 30 04:47:49 PM PDT 24 |
| Peak memory | 639848 kb |
| Host | smart-6ed4149a-cfe2-4d6a-b53c-6f16eeccda8a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679644549 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2679644549 |
| Directory | /workspace/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/63.chip_sw_all_escalation_resets.2689964901 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 6381209768 ps |
| CPU time | 547.96 seconds |
| Started | May 30 04:42:24 PM PDT 24 |
| Finished | May 30 04:51:33 PM PDT 24 |
| Peak memory | 639776 kb |
| Host | smart-9ee0fbc0-60ea-464e-a8a3-739fa106e8fa |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2689964901 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.2689964901 |
| Directory | /workspace/63.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2203725029 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 3353738760 ps |
| CPU time | 310.42 seconds |
| Started | May 30 04:42:27 PM PDT 24 |
| Finished | May 30 04:47:38 PM PDT 24 |
| Peak memory | 639596 kb |
| Host | smart-fcd7f240-9c31-4a2e-bbd5-9fa523f6daac |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203725029 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2203725029 |
| Directory | /workspace/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3354502718 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 4552267750 ps |
| CPU time | 403.07 seconds |
| Started | May 30 04:41:23 PM PDT 24 |
| Finished | May 30 04:48:07 PM PDT 24 |
| Peak memory | 639796 kb |
| Host | smart-348f37aa-242b-495d-8faa-64ae184858ca |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354502718 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3354502718 |
| Directory | /workspace/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/68.chip_sw_all_escalation_resets.3802482552 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 5425284232 ps |
| CPU time | 554.7 seconds |
| Started | May 30 04:41:57 PM PDT 24 |
| Finished | May 30 04:51:13 PM PDT 24 |
| Peak memory | 639320 kb |
| Host | smart-8787bcfb-b6d1-445b-9bbb-566e40545a97 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3802482552 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.3802482552 |
| Directory | /workspace/68.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/7.chip_sw_all_escalation_resets.1123700720 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 4885415762 ps |
| CPU time | 472.22 seconds |
| Started | May 30 04:33:21 PM PDT 24 |
| Finished | May 30 04:41:14 PM PDT 24 |
| Peak memory | 639356 kb |
| Host | smart-90d07cc8-030e-4c0c-bc01-3072961b6130 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1123700720 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.1123700720 |
| Directory | /workspace/7.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/71.chip_sw_all_escalation_resets.3881376955 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 5815244980 ps |
| CPU time | 491.7 seconds |
| Started | May 30 04:41:50 PM PDT 24 |
| Finished | May 30 04:50:03 PM PDT 24 |
| Peak memory | 639492 kb |
| Host | smart-bc7be5b3-92bc-4772-9192-96eeda447e4a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3881376955 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.3881376955 |
| Directory | /workspace/71.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.446880634 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 3245519680 ps |
| CPU time | 333.37 seconds |
| Started | May 30 04:42:34 PM PDT 24 |
| Finished | May 30 04:48:09 PM PDT 24 |
| Peak memory | 639472 kb |
| Host | smart-b8c697ae-77cb-40ad-a12f-280365bf3824 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446880634 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_s w_alert_handler_lpg_sleep_mode_alerts.446880634 |
| Directory | /workspace/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.793281380 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 3601868500 ps |
| CPU time | 278.56 seconds |
| Started | May 30 04:41:39 PM PDT 24 |
| Finished | May 30 04:46:18 PM PDT 24 |
| Peak memory | 639576 kb |
| Host | smart-32f3e9d1-900c-42cd-a35f-b033ffbf5b36 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793281380 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_s w_alert_handler_lpg_sleep_mode_alerts.793281380 |
| Directory | /workspace/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1817555789 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 4290465064 ps |
| CPU time | 398.28 seconds |
| Started | May 30 04:41:56 PM PDT 24 |
| Finished | May 30 04:48:35 PM PDT 24 |
| Peak memory | 639612 kb |
| Host | smart-8d673fca-91ba-4300-9f75-1c02a14fa90e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817555789 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1817555789 |
| Directory | /workspace/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2868897928 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 3811249820 ps |
| CPU time | 443.01 seconds |
| Started | May 30 04:42:46 PM PDT 24 |
| Finished | May 30 04:50:16 PM PDT 24 |
| Peak memory | 639648 kb |
| Host | smart-d270ccc0-c075-446a-9d4c-78216ffc6b68 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868897928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2868897928 |
| Directory | /workspace/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.4280558396 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 3034183706 ps |
| CPU time | 375.4 seconds |
| Started | May 30 04:41:54 PM PDT 24 |
| Finished | May 30 04:48:10 PM PDT 24 |
| Peak memory | 639424 kb |
| Host | smart-ff6d4136-d8dc-4ae2-848d-5782e885a106 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280558396 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4280558396 |
| Directory | /workspace/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3414957386 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 3355794096 ps |
| CPU time | 380.59 seconds |
| Started | May 30 04:46:58 PM PDT 24 |
| Finished | May 30 04:53:19 PM PDT 24 |
| Peak memory | 639592 kb |
| Host | smart-1c076b6b-9865-4158-a8f8-0077ed7bd2c7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414957386 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3414957386 |
| Directory | /workspace/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/9.chip_sw_all_escalation_resets.2578445731 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 5421456870 ps |
| CPU time | 471.49 seconds |
| Started | May 30 04:34:10 PM PDT 24 |
| Finished | May 30 04:42:04 PM PDT 24 |
| Peak memory | 639816 kb |
| Host | smart-7e360ea7-5886-436d-8c24-a2b097776d4e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2578445731 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.2578445731 |
| Directory | /workspace/9.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1856056324 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 6172230490 ps |
| CPU time | 578.38 seconds |
| Started | May 30 04:12:54 PM PDT 24 |
| Finished | May 30 04:22:33 PM PDT 24 |
| Peak memory | 605812 kb |
| Host | smart-f1868b7a-055a-41b1-977c-46ae6afc4608 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1856056324 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.1856056324 |
| Directory | /workspace/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.876084629 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 13167032573 ps |
| CPU time | 2746.22 seconds |
| Started | May 30 04:08:59 PM PDT 24 |
| Finished | May 30 04:54:47 PM PDT 24 |
| Peak memory | 611980 kb |
| Host | smart-12bc13a9-32ab-4996-8c06-1e908fc5c4aa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876084629 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_ alt_clk_freq.876084629 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.862135281 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 5234560074 ps |
| CPU time | 890.69 seconds |
| Started | May 30 04:13:00 PM PDT 24 |
| Finished | May 30 04:27:53 PM PDT 24 |
| Peak memory | 603508 kb |
| Host | smart-fd9af267-c110-436f-abd4-76b182b40194 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86213 5281 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.862135281 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/23.chip_sw_all_escalation_resets.3959634344 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 5504194080 ps |
| CPU time | 628.68 seconds |
| Started | May 30 04:35:27 PM PDT 24 |
| Finished | May 30 04:45:57 PM PDT 24 |
| Peak memory | 605380 kb |
| Host | smart-35de277a-4f03-46a5-99e5-c63bdd471edf |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3959634344 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.3959634344 |
| Directory | /workspace/23.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.491136340 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 3867705511 ps |
| CPU time | 227.8 seconds |
| Started | May 30 03:48:53 PM PDT 24 |
| Finished | May 30 03:52:42 PM PDT 24 |
| Peak memory | 655948 kb |
| Host | smart-90aea641-41f0-4560-af51-c32fce23e98b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491136340 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_hw_re set.491136340 |
| Directory | /workspace/4.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_idle.2992791558 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 3126371160 ps |
| CPU time | 382.59 seconds |
| Started | May 30 04:18:50 PM PDT 24 |
| Finished | May 30 04:25:15 PM PDT 24 |
| Peak memory | 603788 kb |
| Host | smart-f3e8fe8f-529c-43a2-a630-e8871455b7c5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992791558 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_hmac_enc_idle.2992791558 |
| Directory | /workspace/0.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2977894005 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 6742566104 ps |
| CPU time | 527.2 seconds |
| Started | May 30 04:10:22 PM PDT 24 |
| Finished | May 30 04:19:10 PM PDT 24 |
| Peak memory | 604224 kb |
| Host | smart-0a91158e-8ccf-4949-a51c-f8254c4f91e9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977894005 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_full_aon_reset.2977894005 |
| Directory | /workspace/0.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_tl_errors.702361316 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 4185179027 ps |
| CPU time | 255.4 seconds |
| Started | May 30 03:48:58 PM PDT 24 |
| Finished | May 30 03:53:15 PM PDT 24 |
| Peak memory | 594032 kb |
| Host | smart-dac6dc89-394d-4e85-aa24-2ba61ee24e61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702361316 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_tl_errors.702361316 |
| Directory | /workspace/11.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all.2897767293 |
| Short name | T1963 |
| Test name | |
| Test status | |
| Simulation time | 14980770917 ps |
| CPU time | 582.97 seconds |
| Started | May 30 03:49:12 PM PDT 24 |
| Finished | May 30 03:58:57 PM PDT 24 |
| Peak memory | 573232 kb |
| Host | smart-789c895a-233e-48b0-843e-9ae42928b5e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897767293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.2897767293 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.1466060051 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 21479330894 ps |
| CPU time | 753.24 seconds |
| Started | May 30 03:55:54 PM PDT 24 |
| Finished | May 30 04:08:29 PM PDT 24 |
| Peak memory | 573184 kb |
| Host | smart-1a6945d2-11b7-4d19-b5bf-c8eb634f1d2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466060051 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_error.1466060051 |
| Directory | /workspace/61.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_csrng.1113895113 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 5603290680 ps |
| CPU time | 1263.15 seconds |
| Started | May 30 04:19:24 PM PDT 24 |
| Finished | May 30 04:40:28 PM PDT 24 |
| Peak memory | 603960 kb |
| Host | smart-c68c531e-9181-411b-96c8-fc5a7a5dcec7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1113895113 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.1113895113 |
| Directory | /workspace/0.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.762622579 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 11825691360 ps |
| CPU time | 1446.91 seconds |
| Started | May 30 04:11:28 PM PDT 24 |
| Finished | May 30 04:35:36 PM PDT 24 |
| Peak memory | 605436 kb |
| Host | smart-a9d02ecc-7dac-4dea-91d2-4cc8700ce248 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=762622579 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.762622579 |
| Directory | /workspace/0.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio.2627285285 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 3369106206 ps |
| CPU time | 473.65 seconds |
| Started | May 30 04:14:53 PM PDT 24 |
| Finished | May 30 04:22:47 PM PDT 24 |
| Peak memory | 603744 kb |
| Host | smart-b082c9df-d474-40f1-8057-b051f764971b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627285285 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_gpio.2627285285 |
| Directory | /workspace/1.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio.4272683807 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 4525224520 ps |
| CPU time | 583.5 seconds |
| Started | May 30 04:24:40 PM PDT 24 |
| Finished | May 30 04:34:24 PM PDT 24 |
| Peak memory | 603724 kb |
| Host | smart-2bb77ad1-8000-41b2-bf3a-c17365f6cacf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272683807 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_gpio.4272683807 |
| Directory | /workspace/2.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1679729334 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 18715057400 ps |
| CPU time | 562.11 seconds |
| Started | May 30 04:10:54 PM PDT 24 |
| Finished | May 30 04:20:18 PM PDT 24 |
| Peak memory | 611096 kb |
| Host | smart-5cb91874-1dde-4fa0-bae0-68844b088579 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1679729334 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1679729334 |
| Directory | /workspace/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pattgen_ios.1939778900 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 3052362384 ps |
| CPU time | 321.83 seconds |
| Started | May 30 04:08:54 PM PDT 24 |
| Finished | May 30 04:14:17 PM PDT 24 |
| Peak memory | 604212 kb |
| Host | smart-7df19685-749d-4094-b048-dcb3fc17cd22 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939778900 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.1939778900 |
| Directory | /workspace/0.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pattgen_ios.789768730 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 2652434490 ps |
| CPU time | 204.44 seconds |
| Started | May 30 04:14:30 PM PDT 24 |
| Finished | May 30 04:17:55 PM PDT 24 |
| Peak memory | 603932 kb |
| Host | smart-276a3e59-a91f-4b28-9c43-b7e27c8631f7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789768730 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.789768730 |
| Directory | /workspace/1.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.903235604 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 26095178491 ps |
| CPU time | 2410.15 seconds |
| Started | May 30 04:11:46 PM PDT 24 |
| Finished | May 30 04:51:58 PM PDT 24 |
| Peak memory | 608076 kb |
| Host | smart-2ea2f11f-b59c-4596-bfce-c52d17cd5a98 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=903235604 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.903235604 |
| Directory | /workspace/0.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1271959140 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 6598739576 ps |
| CPU time | 569.5 seconds |
| Started | May 30 04:12:21 PM PDT 24 |
| Finished | May 30 04:21:52 PM PDT 24 |
| Peak memory | 610588 kb |
| Host | smart-86b54533-58f0-4c65-bbd6-11ef5d30c030 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1271959140 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1271959140 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.2278270994 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 6524739288 ps |
| CPU time | 1318.57 seconds |
| Started | May 30 04:18:23 PM PDT 24 |
| Finished | May 30 04:40:23 PM PDT 24 |
| Peak memory | 605328 kb |
| Host | smart-c895df55-63d4-4b9f-97c9-d1f6e811eb5a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2278270994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.2278270994 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.4119739212 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 2141965154 ps |
| CPU time | 127.08 seconds |
| Started | May 30 04:25:53 PM PDT 24 |
| Finished | May 30 04:28:01 PM PDT 24 |
| Peak memory | 612612 kb |
| Host | smart-94e07ba6-8c80-42e6-b575-1d0e76b77c83 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119739212 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.4119739212 |
| Directory | /workspace/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all.2489762348 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 750583875 ps |
| CPU time | 71.39 seconds |
| Started | May 30 03:49:17 PM PDT 24 |
| Finished | May 30 03:50:31 PM PDT 24 |
| Peak memory | 573076 kb |
| Host | smart-d57ea200-b8f6-48df-a441-1b67ee1f31ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489762348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.2489762348 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_tl_errors.983099746 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 3854732344 ps |
| CPU time | 269.44 seconds |
| Started | May 30 03:49:06 PM PDT 24 |
| Finished | May 30 03:53:37 PM PDT 24 |
| Peak memory | 595084 kb |
| Host | smart-c9ab289a-5675-4cb5-820e-b0acffbfb63b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983099746 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_tl_errors.983099746 |
| Directory | /workspace/14.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.3513892904 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 13351184327 ps |
| CPU time | 500.77 seconds |
| Started | May 30 03:51:03 PM PDT 24 |
| Finished | May 30 03:59:25 PM PDT 24 |
| Peak memory | 573184 kb |
| Host | smart-6d215e1f-8bf3-4c34-a647-30dc1a9c3a9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513892904 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.3513892904 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.4101317666 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 4986089326 ps |
| CPU time | 168.77 seconds |
| Started | May 30 03:51:30 PM PDT 24 |
| Finished | May 30 03:54:20 PM PDT 24 |
| Peak memory | 573096 kb |
| Host | smart-00377dfe-2162-4030-8b53-c12517f40447 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101317666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.4101317666 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.2550944870 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 2966560177 ps |
| CPU time | 285.68 seconds |
| Started | May 30 03:51:48 PM PDT 24 |
| Finished | May 30 03:56:35 PM PDT 24 |
| Peak memory | 573148 kb |
| Host | smart-821ee6ad-1863-4f38-bfaf-df5a21a08042 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550944870 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_al l_with_reset_error.2550944870 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.1171694778 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 6248484793 ps |
| CPU time | 214.48 seconds |
| Started | May 30 03:52:59 PM PDT 24 |
| Finished | May 30 03:56:35 PM PDT 24 |
| Peak memory | 575172 kb |
| Host | smart-70f24bae-0b1b-4849-9e19-878dce3378e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171694778 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.1171694778 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_error.954712974 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 10546545555 ps |
| CPU time | 376.7 seconds |
| Started | May 30 03:56:25 PM PDT 24 |
| Finished | May 30 04:02:42 PM PDT 24 |
| Peak memory | 573220 kb |
| Host | smart-016ed935-f6e6-4bcd-8efa-e15ee439d90d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954712974 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_error.954712974 |
| Directory | /workspace/65.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_10.106567894 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 3874598186 ps |
| CPU time | 521.6 seconds |
| Started | May 30 04:11:46 PM PDT 24 |
| Finished | May 30 04:20:29 PM PDT 24 |
| Peak memory | 603528 kb |
| Host | smart-ad3c0faf-35e4-41ea-b63f-7ec69d6f9f24 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106567894 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_plic_all_irqs_10.106567894 |
| Directory | /workspace/0.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.169170451 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 3856563910 ps |
| CPU time | 649.1 seconds |
| Started | May 30 04:09:06 PM PDT 24 |
| Finished | May 30 04:19:56 PM PDT 24 |
| Peak memory | 603888 kb |
| Host | smart-5d7c682b-9727-4f91-8526-468454cf5928 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169170451 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.169170451 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_testunlock0.3627178125 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 9434709982 ps |
| CPU time | 925.15 seconds |
| Started | May 30 04:20:23 PM PDT 24 |
| Finished | May 30 04:35:49 PM PDT 24 |
| Peak memory | 618644 kb |
| Host | smart-bac2d451-dd09-40fe-bb86-47eb8e5ae0b8 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3627178125 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_testunlock0.3627178125 |
| Directory | /workspace/1.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.1806482241 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 4211551912 ps |
| CPU time | 514.37 seconds |
| Started | May 30 04:08:53 PM PDT 24 |
| Finished | May 30 04:17:28 PM PDT 24 |
| Peak memory | 604212 kb |
| Host | smart-eac1dfab-bccb-4e9a-a4f3-2ac7d3d7434e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806482241 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_i2c_device_tx_rx.1806482241 |
| Directory | /workspace/0.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.4244330930 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 4795462758 ps |
| CPU time | 203.94 seconds |
| Started | May 30 03:48:31 PM PDT 24 |
| Finished | May 30 03:51:55 PM PDT 24 |
| Peak memory | 656968 kb |
| Host | smart-bddbdae2-d274-45b2-bf2a-1a8a19398b61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244330930 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_hw_r eset.4244330930 |
| Directory | /workspace/1.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc.2202278874 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 3832652100 ps |
| CPU time | 339.75 seconds |
| Started | May 30 04:11:05 PM PDT 24 |
| Finished | May 30 04:16:46 PM PDT 24 |
| Peak memory | 603660 kb |
| Host | smart-c2dcdad6-bda3-4b0e-8951-bab80f5f2894 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202278874 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.2202278874 |
| Directory | /workspace/0.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_irq.535807177 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 4097477116 ps |
| CPU time | 390.59 seconds |
| Started | May 30 04:11:24 PM PDT 24 |
| Finished | May 30 04:17:55 PM PDT 24 |
| Peak memory | 603828 kb |
| Host | smart-16555016-86dd-4288-9137-5e61422ecc08 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535807177 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.535807177 |
| Directory | /workspace/0.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3090811811 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 3433018540 ps |
| CPU time | 367.62 seconds |
| Started | May 30 04:18:01 PM PDT 24 |
| Finished | May 30 04:24:11 PM PDT 24 |
| Peak memory | 604596 kb |
| Host | smart-30cc3ba0-b6b1-4542-97fc-ad10d45b9ab3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30908 11811 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.3090811811 |
| Directory | /workspace/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_boot_mode.1943316000 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 3438616520 ps |
| CPU time | 533.33 seconds |
| Started | May 30 04:11:40 PM PDT 24 |
| Finished | May 30 04:20:35 PM PDT 24 |
| Peak memory | 604020 kb |
| Host | smart-0e376713-64d1-47cb-a64b-9079d717caf9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943316000 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ boot_mode.1943316000 |
| Directory | /workspace/0.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.3106311458 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 2757195760 ps |
| CPU time | 256.24 seconds |
| Started | May 30 04:21:55 PM PDT 24 |
| Finished | May 30 04:26:12 PM PDT 24 |
| Peak memory | 610008 kb |
| Host | smart-7fc1899f-491d-4605-99e4-594627ad158e |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106311458 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_lockstep_glitch.3106311458 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_aliasing.645635006 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 28211336607 ps |
| CPU time | 4809.5 seconds |
| Started | May 30 03:48:37 PM PDT 24 |
| Finished | May 30 05:08:49 PM PDT 24 |
| Peak memory | 588256 kb |
| Host | smart-3bc1c53c-d80c-4f70-9295-28921642a809 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645635006 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 0.chip_csr_aliasing.645635006 |
| Directory | /workspace/0.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.4182690945 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 11823258445 ps |
| CPU time | 1625.8 seconds |
| Started | May 30 03:48:37 PM PDT 24 |
| Finished | May 30 04:15:44 PM PDT 24 |
| Peak memory | 586024 kb |
| Host | smart-fda286c6-5a12-4688-b657-bd065eb4a6af |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182690945 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 0.chip_csr_bit_bash.4182690945 |
| Directory | /workspace/0.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_rw.2106456761 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 6448117072 ps |
| CPU time | 638.17 seconds |
| Started | May 30 03:48:38 PM PDT 24 |
| Finished | May 30 03:59:17 PM PDT 24 |
| Peak memory | 592368 kb |
| Host | smart-086d1763-c0f4-4007-a17f-a3b761395b15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106456761 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_rw.2106456761 |
| Directory | /workspace/0.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_prim_tl_access.2873896821 |
| Short name | T1370 |
| Test name | |
| Test status | |
| Simulation time | 15501418612 ps |
| CPU time | 516.03 seconds |
| Started | May 30 03:48:51 PM PDT 24 |
| Finished | May 30 03:57:29 PM PDT 24 |
| Peak memory | 585756 kb |
| Host | smart-e2526ed4-a917-4276-9141-a19df79b8331 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873896821 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_prim_tl_access.2873896821 |
| Directory | /workspace/0.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.225239955 |
| Short name | T2540 |
| Test name | |
| Test status | |
| Simulation time | 8883390766 ps |
| CPU time | 340.54 seconds |
| Started | May 30 03:48:34 PM PDT 24 |
| Finished | May 30 03:54:15 PM PDT 24 |
| Peak memory | 584404 kb |
| Host | smart-4d1a1e94-69ce-4000-8489-fdfeb6b17188 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225239955 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 0.chip_rv_dm_lc_disabled.225239955 |
| Directory | /workspace/0.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.1504642145 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 15332096362 ps |
| CPU time | 1788.03 seconds |
| Started | May 30 03:48:21 PM PDT 24 |
| Finished | May 30 04:18:11 PM PDT 24 |
| Peak memory | 586700 kb |
| Host | smart-1c2828d5-da5e-4aa9-9617-76d17aa0458e |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504642145 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 0.chip_same_csr_outstanding.1504642145 |
| Directory | /workspace/0.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device.1933470915 |
| Short name | T1674 |
| Test name | |
| Test status | |
| Simulation time | 725526630 ps |
| CPU time | 45.75 seconds |
| Started | May 30 03:48:24 PM PDT 24 |
| Finished | May 30 03:49:10 PM PDT 24 |
| Peak memory | 572984 kb |
| Host | smart-c50d409a-74b2-463d-80b7-05b491de28ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933470915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device. 1933470915 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2348819636 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 42240834156 ps |
| CPU time | 736.76 seconds |
| Started | May 30 03:48:35 PM PDT 24 |
| Finished | May 30 04:00:53 PM PDT 24 |
| Peak memory | 573244 kb |
| Host | smart-6cdcb9b1-a985-434b-857d-6a0c00365eab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348819636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_d evice_slow_rsp.2348819636 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.1479088771 |
| Short name | T2218 |
| Test name | |
| Test status | |
| Simulation time | 186707732 ps |
| CPU time | 9.44 seconds |
| Started | May 30 03:48:33 PM PDT 24 |
| Finished | May 30 03:48:44 PM PDT 24 |
| Peak memory | 564696 kb |
| Host | smart-f89a0dfa-b7aa-4f38-af31-cf25d9044902 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479088771 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr .1479088771 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_random.720411559 |
| Short name | T1582 |
| Test name | |
| Test status | |
| Simulation time | 1334112398 ps |
| CPU time | 42.73 seconds |
| Started | May 30 03:48:36 PM PDT 24 |
| Finished | May 30 03:49:19 PM PDT 24 |
| Peak memory | 572896 kb |
| Host | smart-49f0259e-b5a0-4058-91d6-7fa41eafdcd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720411559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.720411559 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random.3666388696 |
| Short name | T2230 |
| Test name | |
| Test status | |
| Simulation time | 566226549 ps |
| CPU time | 45.23 seconds |
| Started | May 30 03:48:28 PM PDT 24 |
| Finished | May 30 03:49:14 PM PDT 24 |
| Peak memory | 572984 kb |
| Host | smart-2999ed07-db9b-4be0-a866-b5a11e57c1a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666388696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random.3666388696 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_large_delays.1883309075 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 91359371968 ps |
| CPU time | 1038.3 seconds |
| Started | May 30 03:48:35 PM PDT 24 |
| Finished | May 30 04:05:55 PM PDT 24 |
| Peak memory | 573120 kb |
| Host | smart-1c6eef4c-5586-4a2f-ac40-fc16d5b59f81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883309075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.1883309075 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.3036459229 |
| Short name | T1793 |
| Test name | |
| Test status | |
| Simulation time | 7591931117 ps |
| CPU time | 132.44 seconds |
| Started | May 30 03:48:35 PM PDT 24 |
| Finished | May 30 03:50:54 PM PDT 24 |
| Peak memory | 564988 kb |
| Host | smart-8f2eb698-5eb6-4fca-ab4b-74fea5530763 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036459229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.3036459229 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.2673447243 |
| Short name | T2077 |
| Test name | |
| Test status | |
| Simulation time | 317998746 ps |
| CPU time | 29.46 seconds |
| Started | May 30 03:48:40 PM PDT 24 |
| Finished | May 30 03:49:11 PM PDT 24 |
| Peak memory | 573016 kb |
| Host | smart-8106ae05-d18e-4ef6-a9af-636ba4efd793 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673447243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_dela ys.2673447243 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_same_source.98743534 |
| Short name | T2488 |
| Test name | |
| Test status | |
| Simulation time | 2402876300 ps |
| CPU time | 67.95 seconds |
| Started | May 30 03:48:34 PM PDT 24 |
| Finished | May 30 03:49:42 PM PDT 24 |
| Peak memory | 573136 kb |
| Host | smart-04f13837-1313-4c1a-bf73-260ee12673e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98743534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.98743534 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke.1129738446 |
| Short name | T2587 |
| Test name | |
| Test status | |
| Simulation time | 231578672 ps |
| CPU time | 9.75 seconds |
| Started | May 30 03:48:40 PM PDT 24 |
| Finished | May 30 03:48:52 PM PDT 24 |
| Peak memory | 564824 kb |
| Host | smart-86a1f6f1-aeae-4779-ba45-cdbe77a3813d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129738446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.1129738446 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.3063697405 |
| Short name | T2327 |
| Test name | |
| Test status | |
| Simulation time | 9175478072 ps |
| CPU time | 96.1 seconds |
| Started | May 30 03:48:29 PM PDT 24 |
| Finished | May 30 03:50:06 PM PDT 24 |
| Peak memory | 564880 kb |
| Host | smart-dd48e1cc-4468-47e9-b15a-19329ef5dfcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063697405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.3063697405 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.1707240062 |
| Short name | T1509 |
| Test name | |
| Test status | |
| Simulation time | 5017659807 ps |
| CPU time | 88.16 seconds |
| Started | May 30 03:48:41 PM PDT 24 |
| Finished | May 30 03:50:11 PM PDT 24 |
| Peak memory | 563484 kb |
| Host | smart-d0dd8fd9-3ec9-4268-9b7f-98818e5e9f9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707240062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.1707240062 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.432660403 |
| Short name | T2207 |
| Test name | |
| Test status | |
| Simulation time | 46666386 ps |
| CPU time | 5.84 seconds |
| Started | May 30 03:48:29 PM PDT 24 |
| Finished | May 30 03:48:35 PM PDT 24 |
| Peak memory | 564676 kb |
| Host | smart-f303427c-178f-4d8d-aa1a-efe1f87c9cdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432660403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays. 432660403 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all.30878064 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 1489343536 ps |
| CPU time | 117.79 seconds |
| Started | May 30 03:48:35 PM PDT 24 |
| Finished | May 30 03:50:34 PM PDT 24 |
| Peak memory | 573104 kb |
| Host | smart-4117ec02-727e-4f5a-a373-25420fe8aaca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30878064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.30878064 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.1293315630 |
| Short name | T1705 |
| Test name | |
| Test status | |
| Simulation time | 1059389171 ps |
| CPU time | 76.75 seconds |
| Started | May 30 03:48:25 PM PDT 24 |
| Finished | May 30 03:49:42 PM PDT 24 |
| Peak memory | 573096 kb |
| Host | smart-b08138cb-37d1-4cfa-b47b-5ec1f982f873 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293315630 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.1293315630 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.1320977803 |
| Short name | T2391 |
| Test name | |
| Test status | |
| Simulation time | 251243212 ps |
| CPU time | 96.7 seconds |
| Started | May 30 03:48:40 PM PDT 24 |
| Finished | May 30 03:50:18 PM PDT 24 |
| Peak memory | 573112 kb |
| Host | smart-54283334-f327-437c-94db-42fda115fcd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320977803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_ with_rand_reset.1320977803 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.1762598395 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 5427955785 ps |
| CPU time | 398.26 seconds |
| Started | May 30 03:48:23 PM PDT 24 |
| Finished | May 30 03:55:03 PM PDT 24 |
| Peak memory | 573232 kb |
| Host | smart-eed44f97-eae2-4d3c-9286-41ca1ae22345 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762598395 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all _with_reset_error.1762598395 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.543255932 |
| Short name | T1419 |
| Test name | |
| Test status | |
| Simulation time | 668382009 ps |
| CPU time | 27.59 seconds |
| Started | May 30 03:48:33 PM PDT 24 |
| Finished | May 30 03:49:02 PM PDT 24 |
| Peak memory | 573084 kb |
| Host | smart-c8255592-a838-4b1c-8b24-36dec668987a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543255932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.543255932 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.1804048129 |
| Short name | T1899 |
| Test name | |
| Test status | |
| Simulation time | 5109040480 ps |
| CPU time | 400.73 seconds |
| Started | May 30 03:48:38 PM PDT 24 |
| Finished | May 30 03:55:20 PM PDT 24 |
| Peak memory | 585836 kb |
| Host | smart-c88f4d0a-3f81-4140-9192-ef2223d4d251 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804048129 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 1.chip_csr_bit_bash.1804048129 |
| Directory | /workspace/1.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_rw.3237858874 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 3947806890 ps |
| CPU time | 281.72 seconds |
| Started | May 30 03:48:41 PM PDT 24 |
| Finished | May 30 03:53:24 PM PDT 24 |
| Peak memory | 592108 kb |
| Host | smart-60090e0e-da9d-4ad7-8fdd-fbb97150ef4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237858874 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_rw.3237858874 |
| Directory | /workspace/1.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_prim_tl_access.898094976 |
| Short name | T2454 |
| Test name | |
| Test status | |
| Simulation time | 7984540820 ps |
| CPU time | 355.22 seconds |
| Started | May 30 03:48:35 PM PDT 24 |
| Finished | May 30 03:54:32 PM PDT 24 |
| Peak memory | 586700 kb |
| Host | smart-46c87e7b-04d9-45a7-b0d6-cf4875bf689b |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898094976 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 .chip_prim_tl_access.898094976 |
| Directory | /workspace/1.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2750662472 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 11839280059 ps |
| CPU time | 369.06 seconds |
| Started | May 30 03:48:39 PM PDT 24 |
| Finished | May 30 03:54:50 PM PDT 24 |
| Peak memory | 584124 kb |
| Host | smart-0c38436d-9454-47ab-b509-b63511a980f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750662472 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_lc_disabled.2750662472 |
| Directory | /workspace/1.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.485872528 |
| Short name | T2028 |
| Test name | |
| Test status | |
| Simulation time | 28975828294 ps |
| CPU time | 4371.27 seconds |
| Started | May 30 03:48:42 PM PDT 24 |
| Finished | May 30 05:01:35 PM PDT 24 |
| Peak memory | 587820 kb |
| Host | smart-063cb333-2626-4e41-b6f6-c05bf89478b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485872528 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 1.chip_same_csr_outstanding.485872528 |
| Directory | /workspace/1.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_tl_errors.3973283769 |
| Short name | T2312 |
| Test name | |
| Test status | |
| Simulation time | 5038299591 ps |
| CPU time | 422.01 seconds |
| Started | May 30 03:48:34 PM PDT 24 |
| Finished | May 30 03:55:37 PM PDT 24 |
| Peak memory | 594112 kb |
| Host | smart-6c235528-7c02-4b30-b6ed-6bed7540e995 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973283769 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_tl_errors.3973283769 |
| Directory | /workspace/1.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device.4009625121 |
| Short name | T1561 |
| Test name | |
| Test status | |
| Simulation time | 382369895 ps |
| CPU time | 29.67 seconds |
| Started | May 30 03:48:29 PM PDT 24 |
| Finished | May 30 03:48:59 PM PDT 24 |
| Peak memory | 573068 kb |
| Host | smart-240f4841-1cc1-4b75-95ea-b40b44dca67a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009625121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device. 4009625121 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2270617706 |
| Short name | T1821 |
| Test name | |
| Test status | |
| Simulation time | 126079790276 ps |
| CPU time | 2114.44 seconds |
| Started | May 30 03:48:42 PM PDT 24 |
| Finished | May 30 04:23:58 PM PDT 24 |
| Peak memory | 573352 kb |
| Host | smart-1b5b3706-8e2d-410a-9be9-1bcd49ba6a92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270617706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_d evice_slow_rsp.2270617706 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.2310963379 |
| Short name | T2874 |
| Test name | |
| Test status | |
| Simulation time | 162348628 ps |
| CPU time | 8.99 seconds |
| Started | May 30 03:48:42 PM PDT 24 |
| Finished | May 30 03:48:52 PM PDT 24 |
| Peak memory | 564716 kb |
| Host | smart-af0f66f2-c114-4b83-a321-46ec747938e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310963379 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr .2310963379 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_random.3450202816 |
| Short name | T2636 |
| Test name | |
| Test status | |
| Simulation time | 132180511 ps |
| CPU time | 11.89 seconds |
| Started | May 30 03:48:37 PM PDT 24 |
| Finished | May 30 03:48:50 PM PDT 24 |
| Peak memory | 573940 kb |
| Host | smart-7de955ef-7671-4db1-a573-82af68583efb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450202816 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.3450202816 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random.3806570691 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 820133142 ps |
| CPU time | 29.63 seconds |
| Started | May 30 03:48:30 PM PDT 24 |
| Finished | May 30 03:49:00 PM PDT 24 |
| Peak memory | 573000 kb |
| Host | smart-1a68b3d5-227d-4b4a-b8d4-16e4bc7a1554 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806570691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random.3806570691 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_large_delays.592843013 |
| Short name | T1521 |
| Test name | |
| Test status | |
| Simulation time | 31550769638 ps |
| CPU time | 336.67 seconds |
| Started | May 30 03:48:36 PM PDT 24 |
| Finished | May 30 03:54:14 PM PDT 24 |
| Peak memory | 573136 kb |
| Host | smart-4e2cbc14-9a38-419f-9fa3-03282b9ae32f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592843013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.592843013 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.4241130519 |
| Short name | T1454 |
| Test name | |
| Test status | |
| Simulation time | 30215082932 ps |
| CPU time | 524.84 seconds |
| Started | May 30 03:48:30 PM PDT 24 |
| Finished | May 30 03:57:16 PM PDT 24 |
| Peak memory | 573184 kb |
| Host | smart-41de9ca7-6994-44b6-b23c-94d2ebbf4b0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241130519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.4241130519 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.2089561170 |
| Short name | T1560 |
| Test name | |
| Test status | |
| Simulation time | 239953194 ps |
| CPU time | 21.71 seconds |
| Started | May 30 03:48:38 PM PDT 24 |
| Finished | May 30 03:49:01 PM PDT 24 |
| Peak memory | 572964 kb |
| Host | smart-ebb6785e-cde1-4c82-94de-2520f7f290e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089561170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_dela ys.2089561170 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_same_source.2515824830 |
| Short name | T1631 |
| Test name | |
| Test status | |
| Simulation time | 383371543 ps |
| CPU time | 27.63 seconds |
| Started | May 30 03:48:36 PM PDT 24 |
| Finished | May 30 03:49:05 PM PDT 24 |
| Peak memory | 573096 kb |
| Host | smart-6b7122d7-3d06-462a-a633-64bc4a011823 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515824830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.2515824830 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke.1966777632 |
| Short name | T1314 |
| Test name | |
| Test status | |
| Simulation time | 122528790 ps |
| CPU time | 6.75 seconds |
| Started | May 30 03:48:42 PM PDT 24 |
| Finished | May 30 03:48:50 PM PDT 24 |
| Peak memory | 564852 kb |
| Host | smart-660eb7c8-f175-4f75-b629-a60b65724d69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966777632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.1966777632 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.1381023129 |
| Short name | T2846 |
| Test name | |
| Test status | |
| Simulation time | 6051149730 ps |
| CPU time | 63.75 seconds |
| Started | May 30 03:48:29 PM PDT 24 |
| Finished | May 30 03:49:33 PM PDT 24 |
| Peak memory | 564972 kb |
| Host | smart-26e2e36d-8809-4d75-881f-adece2c1bd6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381023129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.1381023129 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.3920621564 |
| Short name | T2413 |
| Test name | |
| Test status | |
| Simulation time | 5583364071 ps |
| CPU time | 88.95 seconds |
| Started | May 30 03:48:39 PM PDT 24 |
| Finished | May 30 03:50:10 PM PDT 24 |
| Peak memory | 564952 kb |
| Host | smart-aec2f0cd-6b5b-4f24-ac73-df0d035f6a47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920621564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.3920621564 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.4102219844 |
| Short name | T1600 |
| Test name | |
| Test status | |
| Simulation time | 39812510 ps |
| CPU time | 5.37 seconds |
| Started | May 30 03:48:31 PM PDT 24 |
| Finished | May 30 03:48:37 PM PDT 24 |
| Peak memory | 563292 kb |
| Host | smart-c18cd972-8e55-4f23-921f-2d81201cef5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102219844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays .4102219844 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all.2088743706 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 4314945652 ps |
| CPU time | 168 seconds |
| Started | May 30 03:48:35 PM PDT 24 |
| Finished | May 30 03:51:24 PM PDT 24 |
| Peak memory | 573288 kb |
| Host | smart-9e9b9cb4-aaa3-4135-a7a5-3c965ca78ee4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088743706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.2088743706 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.3454566116 |
| Short name | T2430 |
| Test name | |
| Test status | |
| Simulation time | 10086358316 ps |
| CPU time | 386.9 seconds |
| Started | May 30 03:48:40 PM PDT 24 |
| Finished | May 30 03:55:09 PM PDT 24 |
| Peak memory | 573088 kb |
| Host | smart-d6e6ce74-f5bb-4012-a79c-a8cde8ef6f16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454566116 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.3454566116 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2890358361 |
| Short name | T2789 |
| Test name | |
| Test status | |
| Simulation time | 3014463038 ps |
| CPU time | 531.46 seconds |
| Started | May 30 03:48:38 PM PDT 24 |
| Finished | May 30 03:57:31 PM PDT 24 |
| Peak memory | 573208 kb |
| Host | smart-ec305ba5-c80b-47a5-af0e-318106dee245 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890358361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_ with_rand_reset.2890358361 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.1686987294 |
| Short name | T1861 |
| Test name | |
| Test status | |
| Simulation time | 8262817666 ps |
| CPU time | 443.87 seconds |
| Started | May 30 03:48:30 PM PDT 24 |
| Finished | May 30 03:55:55 PM PDT 24 |
| Peak memory | 581372 kb |
| Host | smart-cd63fae9-9b5a-4216-b11c-b54a4700bd98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686987294 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all _with_reset_error.1686987294 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.2513484468 |
| Short name | T2530 |
| Test name | |
| Test status | |
| Simulation time | 243696770 ps |
| CPU time | 25.91 seconds |
| Started | May 30 03:48:41 PM PDT 24 |
| Finished | May 30 03:49:09 PM PDT 24 |
| Peak memory | 573052 kb |
| Host | smart-029e8fee-0925-4a45-ab5a-44aee2bd8d5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513484468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.2513484468 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_csr_rw.1932055544 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 5912566384 ps |
| CPU time | 545.79 seconds |
| Started | May 30 03:48:59 PM PDT 24 |
| Finished | May 30 03:58:06 PM PDT 24 |
| Peak memory | 592656 kb |
| Host | smart-006023d3-b824-4a20-9511-9942c08127ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932055544 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_rw.1932055544 |
| Directory | /workspace/10.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.3051457586 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 30627872532 ps |
| CPU time | 3538.7 seconds |
| Started | May 30 03:49:00 PM PDT 24 |
| Finished | May 30 04:48:01 PM PDT 24 |
| Peak memory | 588076 kb |
| Host | smart-1b6d353c-a1b5-4048-9cf8-19ba777c56b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051457586 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 10.chip_same_csr_outstanding.3051457586 |
| Directory | /workspace/10.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device.1731465709 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 971607990 ps |
| CPU time | 80.02 seconds |
| Started | May 30 03:48:56 PM PDT 24 |
| Finished | May 30 03:50:18 PM PDT 24 |
| Peak memory | 573012 kb |
| Host | smart-3c4aeece-b94e-44dc-b841-30e2e382a393 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731465709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device .1731465709 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.3375289362 |
| Short name | T1819 |
| Test name | |
| Test status | |
| Simulation time | 1452908632 ps |
| CPU time | 60.48 seconds |
| Started | May 30 03:48:59 PM PDT 24 |
| Finished | May 30 03:50:01 PM PDT 24 |
| Peak memory | 573936 kb |
| Host | smart-416f6e31-fd01-481c-8345-d2f9bfdc0c56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375289362 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_add r.3375289362 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_random.2361076604 |
| Short name | T2732 |
| Test name | |
| Test status | |
| Simulation time | 197189327 ps |
| CPU time | 17.36 seconds |
| Started | May 30 03:49:00 PM PDT 24 |
| Finished | May 30 03:49:19 PM PDT 24 |
| Peak memory | 572852 kb |
| Host | smart-18fe81e7-bfc1-4d54-9ccb-cde170ecf1e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361076604 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.2361076604 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random.1950555250 |
| Short name | T2179 |
| Test name | |
| Test status | |
| Simulation time | 1190561216 ps |
| CPU time | 45.7 seconds |
| Started | May 30 03:49:00 PM PDT 24 |
| Finished | May 30 03:49:47 PM PDT 24 |
| Peak memory | 572996 kb |
| Host | smart-fc5c4c9b-1c41-418a-950e-03d3cad00566 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950555250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random.1950555250 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_large_delays.887202195 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 62505589563 ps |
| CPU time | 655.61 seconds |
| Started | May 30 03:48:57 PM PDT 24 |
| Finished | May 30 03:59:55 PM PDT 24 |
| Peak memory | 573200 kb |
| Host | smart-9b132197-0ca4-4f50-a042-3a9dda2a9a84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887202195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.887202195 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.1700350131 |
| Short name | T2166 |
| Test name | |
| Test status | |
| Simulation time | 38097970228 ps |
| CPU time | 651.21 seconds |
| Started | May 30 03:48:54 PM PDT 24 |
| Finished | May 30 03:59:47 PM PDT 24 |
| Peak memory | 573072 kb |
| Host | smart-17135364-787c-48ad-99ef-aed68daa5a9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700350131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.1700350131 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.3325452910 |
| Short name | T1817 |
| Test name | |
| Test status | |
| Simulation time | 252074868 ps |
| CPU time | 24.79 seconds |
| Started | May 30 03:49:09 PM PDT 24 |
| Finished | May 30 03:49:35 PM PDT 24 |
| Peak memory | 573028 kb |
| Host | smart-f1bd00b0-9467-4ef3-8dab-077054accb2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325452910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_del ays.3325452910 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_same_source.3129615370 |
| Short name | T2772 |
| Test name | |
| Test status | |
| Simulation time | 410279391 ps |
| CPU time | 26.23 seconds |
| Started | May 30 03:48:59 PM PDT 24 |
| Finished | May 30 03:49:27 PM PDT 24 |
| Peak memory | 573052 kb |
| Host | smart-6d153541-2d15-42d1-af75-050dbd1f885e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129615370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.3129615370 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke.4068786876 |
| Short name | T1542 |
| Test name | |
| Test status | |
| Simulation time | 225396139 ps |
| CPU time | 9.47 seconds |
| Started | May 30 03:49:18 PM PDT 24 |
| Finished | May 30 03:49:30 PM PDT 24 |
| Peak memory | 564756 kb |
| Host | smart-23278472-cf71-4e46-9478-756c56b1a03d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068786876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.4068786876 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.3074053738 |
| Short name | T2597 |
| Test name | |
| Test status | |
| Simulation time | 9009114464 ps |
| CPU time | 88.04 seconds |
| Started | May 30 03:48:57 PM PDT 24 |
| Finished | May 30 03:50:27 PM PDT 24 |
| Peak memory | 563516 kb |
| Host | smart-05bbc93c-ea2f-4ced-8a8f-fa432bdca644 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074053738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.3074053738 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.3270494099 |
| Short name | T2011 |
| Test name | |
| Test status | |
| Simulation time | 3860607110 ps |
| CPU time | 66.02 seconds |
| Started | May 30 03:49:17 PM PDT 24 |
| Finished | May 30 03:50:26 PM PDT 24 |
| Peak memory | 564776 kb |
| Host | smart-41810de4-d411-4b8a-9bbb-d94c9c7c652b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270494099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.3270494099 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.1401783760 |
| Short name | T2796 |
| Test name | |
| Test status | |
| Simulation time | 51292059 ps |
| CPU time | 6.19 seconds |
| Started | May 30 03:49:19 PM PDT 24 |
| Finished | May 30 03:49:27 PM PDT 24 |
| Peak memory | 564712 kb |
| Host | smart-ef7e55e9-aa7d-4980-9861-5a9b4c1e6fef |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401783760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delay s.1401783760 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all.1834961774 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 2224015009 ps |
| CPU time | 174.66 seconds |
| Started | May 30 03:49:02 PM PDT 24 |
| Finished | May 30 03:51:58 PM PDT 24 |
| Peak memory | 573208 kb |
| Host | smart-2d24e381-62e1-4cb7-a08a-a32f0a116831 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834961774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.1834961774 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.2034428566 |
| Short name | T1715 |
| Test name | |
| Test status | |
| Simulation time | 2369688804 ps |
| CPU time | 146.88 seconds |
| Started | May 30 03:49:01 PM PDT 24 |
| Finished | May 30 03:51:30 PM PDT 24 |
| Peak memory | 573100 kb |
| Host | smart-8379f9b6-598e-4acd-92c4-989722771e3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034428566 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.2034428566 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.2384053874 |
| Short name | T1503 |
| Test name | |
| Test status | |
| Simulation time | 200236350 ps |
| CPU time | 41.27 seconds |
| Started | May 30 03:49:03 PM PDT 24 |
| Finished | May 30 03:49:46 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-baa4c7a8-0304-48d0-95e2-4021dc99c1e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384053874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all _with_rand_reset.2384053874 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.2696396637 |
| Short name | T2252 |
| Test name | |
| Test status | |
| Simulation time | 93707151 ps |
| CPU time | 11.44 seconds |
| Started | May 30 03:48:59 PM PDT 24 |
| Finished | May 30 03:49:12 PM PDT 24 |
| Peak memory | 564824 kb |
| Host | smart-6a142628-284d-4ae1-8b2c-24bd88804d61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696396637 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_al l_with_reset_error.2696396637 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.3432220479 |
| Short name | T1474 |
| Test name | |
| Test status | |
| Simulation time | 204158015 ps |
| CPU time | 22.74 seconds |
| Started | May 30 03:49:04 PM PDT 24 |
| Finished | May 30 03:49:28 PM PDT 24 |
| Peak memory | 573084 kb |
| Host | smart-f7cf1046-8bc0-43d2-bd8b-e2b074df8e6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432220479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.3432220479 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_csr_rw.4106634700 |
| Short name | T1695 |
| Test name | |
| Test status | |
| Simulation time | 5888754692 ps |
| CPU time | 564.52 seconds |
| Started | May 30 03:49:24 PM PDT 24 |
| Finished | May 30 03:58:50 PM PDT 24 |
| Peak memory | 591992 kb |
| Host | smart-ae6ebb07-5a92-4484-aba4-be1310314792 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106634700 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_rw.4106634700 |
| Directory | /workspace/11.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.116944678 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 15050810837 ps |
| CPU time | 1798.37 seconds |
| Started | May 30 03:49:03 PM PDT 24 |
| Finished | May 30 04:19:03 PM PDT 24 |
| Peak memory | 587372 kb |
| Host | smart-33055586-098f-43ac-9499-3d47adb1d188 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116944678 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 11.chip_same_csr_outstanding.116944678 |
| Directory | /workspace/11.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device.2207686198 |
| Short name | T2603 |
| Test name | |
| Test status | |
| Simulation time | 145586501 ps |
| CPU time | 12.2 seconds |
| Started | May 30 03:48:57 PM PDT 24 |
| Finished | May 30 03:49:11 PM PDT 24 |
| Peak memory | 564820 kb |
| Host | smart-3e004212-1f28-463f-8207-89458c69a6d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207686198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device .2207686198 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.2014796783 |
| Short name | T1627 |
| Test name | |
| Test status | |
| Simulation time | 35447215242 ps |
| CPU time | 620.4 seconds |
| Started | May 30 03:49:12 PM PDT 24 |
| Finished | May 30 03:59:34 PM PDT 24 |
| Peak memory | 573252 kb |
| Host | smart-02a859c9-f2fc-4114-8bdf-10be0c8dc6e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014796783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_ device_slow_rsp.2014796783 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.1040222912 |
| Short name | T1897 |
| Test name | |
| Test status | |
| Simulation time | 320580358 ps |
| CPU time | 12.89 seconds |
| Started | May 30 03:49:02 PM PDT 24 |
| Finished | May 30 03:49:17 PM PDT 24 |
| Peak memory | 572904 kb |
| Host | smart-6d82dad8-e361-46c8-aa01-5333ba95c9d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040222912 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_add r.1040222912 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_random.3787400254 |
| Short name | T2283 |
| Test name | |
| Test status | |
| Simulation time | 208444950 ps |
| CPU time | 17.89 seconds |
| Started | May 30 03:48:57 PM PDT 24 |
| Finished | May 30 03:49:17 PM PDT 24 |
| Peak memory | 572740 kb |
| Host | smart-a1479c46-f557-490a-8ea3-198153b53643 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787400254 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.3787400254 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random.2402221842 |
| Short name | T2228 |
| Test name | |
| Test status | |
| Simulation time | 323970930 ps |
| CPU time | 27.1 seconds |
| Started | May 30 03:49:23 PM PDT 24 |
| Finished | May 30 03:49:51 PM PDT 24 |
| Peak memory | 572960 kb |
| Host | smart-a429a34f-0248-467d-8565-2ad63f00f053 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402221842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random.2402221842 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_large_delays.1520224933 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 77381385123 ps |
| CPU time | 892.34 seconds |
| Started | May 30 03:49:07 PM PDT 24 |
| Finished | May 30 04:04:00 PM PDT 24 |
| Peak memory | 573164 kb |
| Host | smart-83cc6768-fad3-4296-a067-3c6119aa99bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520224933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.1520224933 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.2104647700 |
| Short name | T1703 |
| Test name | |
| Test status | |
| Simulation time | 45083895722 ps |
| CPU time | 792.54 seconds |
| Started | May 30 03:49:01 PM PDT 24 |
| Finished | May 30 04:02:16 PM PDT 24 |
| Peak memory | 573084 kb |
| Host | smart-9404bcfd-980e-4c82-bd15-68341a386768 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104647700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.2104647700 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.4265708305 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 490485182 ps |
| CPU time | 39.42 seconds |
| Started | May 30 03:48:57 PM PDT 24 |
| Finished | May 30 03:49:38 PM PDT 24 |
| Peak memory | 573060 kb |
| Host | smart-df35b1bb-63a2-4245-9e30-325a27b98069 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265708305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_del ays.4265708305 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_same_source.4120305852 |
| Short name | T2777 |
| Test name | |
| Test status | |
| Simulation time | 332836185 ps |
| CPU time | 24.32 seconds |
| Started | May 30 03:49:00 PM PDT 24 |
| Finished | May 30 03:49:26 PM PDT 24 |
| Peak memory | 573048 kb |
| Host | smart-825d666c-b8b3-4dc8-b298-43b716140a8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120305852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.4120305852 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke.3337474923 |
| Short name | T1321 |
| Test name | |
| Test status | |
| Simulation time | 137560021 ps |
| CPU time | 6.73 seconds |
| Started | May 30 03:48:55 PM PDT 24 |
| Finished | May 30 03:49:04 PM PDT 24 |
| Peak memory | 564820 kb |
| Host | smart-ed1d045b-7b01-475b-bfc8-0621c4b641a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337474923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.3337474923 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.4270726534 |
| Short name | T2827 |
| Test name | |
| Test status | |
| Simulation time | 7834358444 ps |
| CPU time | 74.99 seconds |
| Started | May 30 03:48:59 PM PDT 24 |
| Finished | May 30 03:50:16 PM PDT 24 |
| Peak memory | 564972 kb |
| Host | smart-7cd290a1-2e7e-406c-9897-ad1981ee6362 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270726534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.4270726534 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.237042419 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 4919899058 ps |
| CPU time | 84.17 seconds |
| Started | May 30 03:49:01 PM PDT 24 |
| Finished | May 30 03:50:27 PM PDT 24 |
| Peak memory | 564960 kb |
| Host | smart-f11a1acd-32e8-4af8-bbed-ad9083cfee71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237042419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.237042419 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.3163691769 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 35767762 ps |
| CPU time | 5.55 seconds |
| Started | May 30 03:49:04 PM PDT 24 |
| Finished | May 30 03:49:10 PM PDT 24 |
| Peak memory | 564780 kb |
| Host | smart-2d0a4d59-a3db-4463-a9e0-cf0007f9405c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163691769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delay s.3163691769 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.3496909598 |
| Short name | T1404 |
| Test name | |
| Test status | |
| Simulation time | 2887007305 ps |
| CPU time | 226.9 seconds |
| Started | May 30 03:49:23 PM PDT 24 |
| Finished | May 30 03:53:11 PM PDT 24 |
| Peak memory | 573068 kb |
| Host | smart-1ddd153d-4284-4679-b99a-510f0a1f18b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496909598 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.3496909598 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.1070869876 |
| Short name | T2720 |
| Test name | |
| Test status | |
| Simulation time | 41945683 ps |
| CPU time | 14.05 seconds |
| Started | May 30 03:48:59 PM PDT 24 |
| Finished | May 30 03:49:15 PM PDT 24 |
| Peak memory | 564908 kb |
| Host | smart-14b8ff1d-7814-4595-8879-4808909c9c96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070869876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all _with_rand_reset.1070869876 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1414574113 |
| Short name | T1787 |
| Test name | |
| Test status | |
| Simulation time | 355347566 ps |
| CPU time | 70.43 seconds |
| Started | May 30 03:48:58 PM PDT 24 |
| Finished | May 30 03:50:10 PM PDT 24 |
| Peak memory | 573100 kb |
| Host | smart-6490ff37-8974-4da6-bdb4-444ad7486a1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414574113 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_al l_with_reset_error.1414574113 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.1032766844 |
| Short name | T2515 |
| Test name | |
| Test status | |
| Simulation time | 993370975 ps |
| CPU time | 40.26 seconds |
| Started | May 30 03:49:01 PM PDT 24 |
| Finished | May 30 03:49:43 PM PDT 24 |
| Peak memory | 572980 kb |
| Host | smart-bc363d54-644c-477b-9be8-37a4a5c8fca8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032766844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.1032766844 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_csr_rw.774856251 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 3828570028 ps |
| CPU time | 305.05 seconds |
| Started | May 30 03:49:07 PM PDT 24 |
| Finished | May 30 03:54:13 PM PDT 24 |
| Peak memory | 591768 kb |
| Host | smart-377f33a3-a938-449a-b4d4-97f6d5a9cdd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774856251 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_rw.774856251 |
| Directory | /workspace/12.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.3800400059 |
| Short name | T2300 |
| Test name | |
| Test status | |
| Simulation time | 15394911223 ps |
| CPU time | 1957.74 seconds |
| Started | May 30 03:49:01 PM PDT 24 |
| Finished | May 30 04:21:41 PM PDT 24 |
| Peak memory | 587724 kb |
| Host | smart-4ceaa416-307a-4758-af6b-3406c61ae696 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800400059 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 12.chip_same_csr_outstanding.3800400059 |
| Directory | /workspace/12.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_tl_errors.3210788054 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 3057994891 ps |
| CPU time | 180.32 seconds |
| Started | May 30 03:49:17 PM PDT 24 |
| Finished | May 30 03:52:20 PM PDT 24 |
| Peak memory | 593904 kb |
| Host | smart-2588fe87-c45a-497f-a782-98378bfa5391 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210788054 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_tl_errors.3210788054 |
| Directory | /workspace/12.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device.629242428 |
| Short name | T1500 |
| Test name | |
| Test status | |
| Simulation time | 3835271023 ps |
| CPU time | 155.23 seconds |
| Started | May 30 03:49:06 PM PDT 24 |
| Finished | May 30 03:51:42 PM PDT 24 |
| Peak memory | 573188 kb |
| Host | smart-c3cf33a3-0eeb-4d5a-82be-3b81e8e2a872 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629242428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device. 629242428 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.87596179 |
| Short name | T1734 |
| Test name | |
| Test status | |
| Simulation time | 107231311842 ps |
| CPU time | 1971.99 seconds |
| Started | May 30 03:49:09 PM PDT 24 |
| Finished | May 30 04:22:02 PM PDT 24 |
| Peak memory | 573312 kb |
| Host | smart-d0bf5952-a451-42b0-9879-9437fff24619 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87596179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_de vice_slow_rsp.87596179 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.237826640 |
| Short name | T1520 |
| Test name | |
| Test status | |
| Simulation time | 75221097 ps |
| CPU time | 6.11 seconds |
| Started | May 30 03:49:09 PM PDT 24 |
| Finished | May 30 03:49:16 PM PDT 24 |
| Peak memory | 564736 kb |
| Host | smart-06a6fb00-f94c-43fa-9679-66befbd17b82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237826640 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr .237826640 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_random.4017563956 |
| Short name | T1738 |
| Test name | |
| Test status | |
| Simulation time | 394408030 ps |
| CPU time | 15.9 seconds |
| Started | May 30 03:49:09 PM PDT 24 |
| Finished | May 30 03:49:27 PM PDT 24 |
| Peak memory | 573928 kb |
| Host | smart-05e06078-c8ab-4c86-9668-009c08becce9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017563956 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.4017563956 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random.2818886195 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 1897462079 ps |
| CPU time | 65.29 seconds |
| Started | May 30 03:49:03 PM PDT 24 |
| Finished | May 30 03:50:10 PM PDT 24 |
| Peak memory | 573096 kb |
| Host | smart-4f98b552-a066-430b-b032-6802d50d2c4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818886195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random.2818886195 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_large_delays.2143271007 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 27460911009 ps |
| CPU time | 294.69 seconds |
| Started | May 30 03:49:04 PM PDT 24 |
| Finished | May 30 03:54:00 PM PDT 24 |
| Peak memory | 573168 kb |
| Host | smart-5b4325f6-14c9-4ab1-ba0e-43c15bd49745 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143271007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.2143271007 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.2508278392 |
| Short name | T1316 |
| Test name | |
| Test status | |
| Simulation time | 3281888201 ps |
| CPU time | 56.19 seconds |
| Started | May 30 03:49:09 PM PDT 24 |
| Finished | May 30 03:50:07 PM PDT 24 |
| Peak memory | 564896 kb |
| Host | smart-686e3bc8-9a77-424b-afe9-050c6699ceb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508278392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.2508278392 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.2815325513 |
| Short name | T2576 |
| Test name | |
| Test status | |
| Simulation time | 227911095 ps |
| CPU time | 20.7 seconds |
| Started | May 30 03:49:08 PM PDT 24 |
| Finished | May 30 03:49:30 PM PDT 24 |
| Peak memory | 573048 kb |
| Host | smart-aa535029-a590-4f99-bc30-5e71641b69e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815325513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_del ays.2815325513 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_same_source.443283999 |
| Short name | T2244 |
| Test name | |
| Test status | |
| Simulation time | 1774103309 ps |
| CPU time | 51.6 seconds |
| Started | May 30 03:49:17 PM PDT 24 |
| Finished | May 30 03:50:11 PM PDT 24 |
| Peak memory | 573036 kb |
| Host | smart-3aa0f9a4-a706-4a6a-9fdb-7ba5a5015a30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443283999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.443283999 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke.3517405800 |
| Short name | T2498 |
| Test name | |
| Test status | |
| Simulation time | 45250421 ps |
| CPU time | 5.98 seconds |
| Started | May 30 03:49:18 PM PDT 24 |
| Finished | May 30 03:49:27 PM PDT 24 |
| Peak memory | 564836 kb |
| Host | smart-b6737c4e-05c7-47eb-ad7d-ad5d886de111 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517405800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.3517405800 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.3235199680 |
| Short name | T2238 |
| Test name | |
| Test status | |
| Simulation time | 8787710938 ps |
| CPU time | 95.42 seconds |
| Started | May 30 03:49:09 PM PDT 24 |
| Finished | May 30 03:50:46 PM PDT 24 |
| Peak memory | 564932 kb |
| Host | smart-e761f4e0-1da3-41e2-be6e-d56abdaaa1dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235199680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.3235199680 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.3525978585 |
| Short name | T1351 |
| Test name | |
| Test status | |
| Simulation time | 6424349220 ps |
| CPU time | 113.51 seconds |
| Started | May 30 03:49:10 PM PDT 24 |
| Finished | May 30 03:51:05 PM PDT 24 |
| Peak memory | 564928 kb |
| Host | smart-6dadd59c-8b10-43c9-bbfd-6b56f0f31663 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525978585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.3525978585 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.292154093 |
| Short name | T1518 |
| Test name | |
| Test status | |
| Simulation time | 52260058 ps |
| CPU time | 6.67 seconds |
| Started | May 30 03:49:05 PM PDT 24 |
| Finished | May 30 03:49:13 PM PDT 24 |
| Peak memory | 564764 kb |
| Host | smart-8a8b6ba6-d3a3-4572-8b48-5136e29149b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292154093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays .292154093 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.2336183516 |
| Short name | T1728 |
| Test name | |
| Test status | |
| Simulation time | 6403882654 ps |
| CPU time | 218.36 seconds |
| Started | May 30 03:49:26 PM PDT 24 |
| Finished | May 30 03:53:05 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-ffd80ce9-cf32-4adf-8f1c-c3c4946954a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336183516 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.2336183516 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.4278712006 |
| Short name | T2356 |
| Test name | |
| Test status | |
| Simulation time | 3912387253 ps |
| CPU time | 293.73 seconds |
| Started | May 30 03:49:06 PM PDT 24 |
| Finished | May 30 03:54:01 PM PDT 24 |
| Peak memory | 573184 kb |
| Host | smart-fa1a4e04-a339-4c0f-aee7-ad4db84a026d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278712006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all _with_rand_reset.4278712006 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.2586209765 |
| Short name | T2173 |
| Test name | |
| Test status | |
| Simulation time | 31628614 ps |
| CPU time | 18.72 seconds |
| Started | May 30 03:49:07 PM PDT 24 |
| Finished | May 30 03:49:27 PM PDT 24 |
| Peak memory | 564888 kb |
| Host | smart-28a23649-9d39-4582-a0f4-73bcdae9af3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586209765 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_al l_with_reset_error.2586209765 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.1159882469 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 710212846 ps |
| CPU time | 30.15 seconds |
| Started | May 30 03:49:20 PM PDT 24 |
| Finished | May 30 03:49:52 PM PDT 24 |
| Peak memory | 572996 kb |
| Host | smart-d0d6552b-57c2-44d9-9c6a-28628ee06b31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159882469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.1159882469 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_csr_rw.859858219 |
| Short name | T2261 |
| Test name | |
| Test status | |
| Simulation time | 3420568452 ps |
| CPU time | 296.54 seconds |
| Started | May 30 03:49:09 PM PDT 24 |
| Finished | May 30 03:54:07 PM PDT 24 |
| Peak memory | 592276 kb |
| Host | smart-72938c6a-6dd0-41fd-8586-df9b5307c3c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859858219 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_rw.859858219 |
| Directory | /workspace/13.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.1580007135 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 16179107478 ps |
| CPU time | 2028.75 seconds |
| Started | May 30 03:49:03 PM PDT 24 |
| Finished | May 30 04:22:53 PM PDT 24 |
| Peak memory | 587660 kb |
| Host | smart-06e6442c-ed52-48f2-9228-c08a374336e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580007135 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 13.chip_same_csr_outstanding.1580007135 |
| Directory | /workspace/13.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_tl_errors.790300054 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 4668888014 ps |
| CPU time | 356.46 seconds |
| Started | May 30 03:49:21 PM PDT 24 |
| Finished | May 30 03:55:19 PM PDT 24 |
| Peak memory | 594380 kb |
| Host | smart-543a93a0-50b7-4c84-8dc0-7b5063b22476 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790300054 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_tl_errors.790300054 |
| Directory | /workspace/13.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device.4081895368 |
| Short name | T2416 |
| Test name | |
| Test status | |
| Simulation time | 3550903627 ps |
| CPU time | 147.81 seconds |
| Started | May 30 03:49:20 PM PDT 24 |
| Finished | May 30 03:51:50 PM PDT 24 |
| Peak memory | 573172 kb |
| Host | smart-6fd8e756-74f4-41db-808a-15603e6e7ffa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081895368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device .4081895368 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.915664136 |
| Short name | T2348 |
| Test name | |
| Test status | |
| Simulation time | 62631570391 ps |
| CPU time | 1057.92 seconds |
| Started | May 30 03:49:16 PM PDT 24 |
| Finished | May 30 04:06:57 PM PDT 24 |
| Peak memory | 573340 kb |
| Host | smart-88d18e4e-f826-4584-a89a-c727f2b188ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915664136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_d evice_slow_rsp.915664136 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.470482071 |
| Short name | T1392 |
| Test name | |
| Test status | |
| Simulation time | 919853585 ps |
| CPU time | 42.42 seconds |
| Started | May 30 03:49:13 PM PDT 24 |
| Finished | May 30 03:49:58 PM PDT 24 |
| Peak memory | 572920 kb |
| Host | smart-7e71f7f7-15bd-4ea4-9f9b-895832c0483c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470482071 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr .470482071 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_random.1064701792 |
| Short name | T1921 |
| Test name | |
| Test status | |
| Simulation time | 816043725 ps |
| CPU time | 26.02 seconds |
| Started | May 30 03:49:09 PM PDT 24 |
| Finished | May 30 03:49:36 PM PDT 24 |
| Peak memory | 572916 kb |
| Host | smart-3391f9c5-4596-4466-80ff-2f3f4094615d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064701792 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.1064701792 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random.612683944 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 349522223 ps |
| CPU time | 32.23 seconds |
| Started | May 30 03:49:11 PM PDT 24 |
| Finished | May 30 03:49:45 PM PDT 24 |
| Peak memory | 572976 kb |
| Host | smart-c976abac-54ad-4bd7-8e76-d0031dee7a0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612683944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random.612683944 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_large_delays.1029618735 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 76905153644 ps |
| CPU time | 774.51 seconds |
| Started | May 30 03:49:24 PM PDT 24 |
| Finished | May 30 04:02:19 PM PDT 24 |
| Peak memory | 573136 kb |
| Host | smart-0afd68b5-69be-4735-b905-6781c8ec4260 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029618735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.1029618735 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.2759178278 |
| Short name | T1512 |
| Test name | |
| Test status | |
| Simulation time | 43521955014 ps |
| CPU time | 720.16 seconds |
| Started | May 30 03:49:19 PM PDT 24 |
| Finished | May 30 04:01:21 PM PDT 24 |
| Peak memory | 573188 kb |
| Host | smart-ff712996-bf1a-49ba-b0e5-0564f13942b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759178278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.2759178278 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.3221212444 |
| Short name | T1443 |
| Test name | |
| Test status | |
| Simulation time | 495181581 ps |
| CPU time | 43.52 seconds |
| Started | May 30 03:49:10 PM PDT 24 |
| Finished | May 30 03:49:55 PM PDT 24 |
| Peak memory | 573052 kb |
| Host | smart-3af30646-f47a-4726-8c65-aa8e4e85f0f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221212444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_del ays.3221212444 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_same_source.1210857390 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 2738281234 ps |
| CPU time | 88.81 seconds |
| Started | May 30 03:49:19 PM PDT 24 |
| Finished | May 30 03:50:50 PM PDT 24 |
| Peak memory | 573068 kb |
| Host | smart-3066dbad-28ad-4949-ad22-86db229b33ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210857390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.1210857390 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke.1638047884 |
| Short name | T1565 |
| Test name | |
| Test status | |
| Simulation time | 189932315 ps |
| CPU time | 8.78 seconds |
| Started | May 30 03:49:15 PM PDT 24 |
| Finished | May 30 03:49:27 PM PDT 24 |
| Peak memory | 563400 kb |
| Host | smart-d11e3a2c-a46a-45b8-8028-cbf850ba6184 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638047884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.1638047884 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.4095072797 |
| Short name | T2565 |
| Test name | |
| Test status | |
| Simulation time | 9104576477 ps |
| CPU time | 95.66 seconds |
| Started | May 30 03:49:10 PM PDT 24 |
| Finished | May 30 03:50:47 PM PDT 24 |
| Peak memory | 563516 kb |
| Host | smart-fb48acc8-09ef-4879-bbbb-77e6254f1eec |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095072797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.4095072797 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.2863022404 |
| Short name | T1954 |
| Test name | |
| Test status | |
| Simulation time | 6172659864 ps |
| CPU time | 107.75 seconds |
| Started | May 30 03:49:07 PM PDT 24 |
| Finished | May 30 03:50:56 PM PDT 24 |
| Peak memory | 564968 kb |
| Host | smart-e09598d7-2945-429b-ab13-b904665a2c24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863022404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.2863022404 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.2216276706 |
| Short name | T2066 |
| Test name | |
| Test status | |
| Simulation time | 44806384 ps |
| CPU time | 6.18 seconds |
| Started | May 30 03:49:05 PM PDT 24 |
| Finished | May 30 03:49:12 PM PDT 24 |
| Peak memory | 564816 kb |
| Host | smart-b8f8a2fc-09fd-45bd-a36f-3d53fdb70f9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216276706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delay s.2216276706 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all.130895264 |
| Short name | T2206 |
| Test name | |
| Test status | |
| Simulation time | 11846595488 ps |
| CPU time | 518.39 seconds |
| Started | May 30 03:49:09 PM PDT 24 |
| Finished | May 30 03:57:49 PM PDT 24 |
| Peak memory | 573300 kb |
| Host | smart-1f610cfa-08be-4458-9d1f-ae1fd5e26506 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130895264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.130895264 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.3064543871 |
| Short name | T1651 |
| Test name | |
| Test status | |
| Simulation time | 5452769083 ps |
| CPU time | 182.45 seconds |
| Started | May 30 03:49:10 PM PDT 24 |
| Finished | May 30 03:52:14 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-931cd226-845a-4fe8-8097-c4fed9a1e1f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064543871 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.3064543871 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.1997338543 |
| Short name | T2466 |
| Test name | |
| Test status | |
| Simulation time | 351841737 ps |
| CPU time | 250.06 seconds |
| Started | May 30 03:49:17 PM PDT 24 |
| Finished | May 30 03:53:30 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-68d0377f-9e2a-4fa8-9846-089ea367f566 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997338543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all _with_rand_reset.1997338543 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.3769133073 |
| Short name | T2456 |
| Test name | |
| Test status | |
| Simulation time | 92743428 ps |
| CPU time | 63.93 seconds |
| Started | May 30 03:49:09 PM PDT 24 |
| Finished | May 30 03:50:15 PM PDT 24 |
| Peak memory | 564828 kb |
| Host | smart-babbc223-0b17-4fc1-8002-697f72554764 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769133073 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_al l_with_reset_error.3769133073 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.2338600029 |
| Short name | T1888 |
| Test name | |
| Test status | |
| Simulation time | 308291445 ps |
| CPU time | 32.68 seconds |
| Started | May 30 03:49:10 PM PDT 24 |
| Finished | May 30 03:49:45 PM PDT 24 |
| Peak memory | 573056 kb |
| Host | smart-a99e8fbc-585f-4207-8ba5-3429cb38765f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338600029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.2338600029 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_csr_rw.2494509008 |
| Short name | T1534 |
| Test name | |
| Test status | |
| Simulation time | 6110504948 ps |
| CPU time | 694.28 seconds |
| Started | May 30 03:49:10 PM PDT 24 |
| Finished | May 30 04:00:46 PM PDT 24 |
| Peak memory | 593876 kb |
| Host | smart-ff6dbe67-66a2-42f8-b565-418267fc49f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494509008 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_csr_rw.2494509008 |
| Directory | /workspace/14.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.2882424739 |
| Short name | T2190 |
| Test name | |
| Test status | |
| Simulation time | 15784400356 ps |
| CPU time | 2420.49 seconds |
| Started | May 30 03:49:13 PM PDT 24 |
| Finished | May 30 04:29:36 PM PDT 24 |
| Peak memory | 587660 kb |
| Host | smart-4ad8a257-4c99-4338-9612-a923f29580ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882424739 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 14.chip_same_csr_outstanding.2882424739 |
| Directory | /workspace/14.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device.3614609841 |
| Short name | T1679 |
| Test name | |
| Test status | |
| Simulation time | 1282289448 ps |
| CPU time | 92.94 seconds |
| Started | May 30 03:49:10 PM PDT 24 |
| Finished | May 30 03:50:45 PM PDT 24 |
| Peak memory | 573092 kb |
| Host | smart-3e0f7071-61f1-43d6-ae09-3d3b606b8ea6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614609841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device .3614609841 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.1065315043 |
| Short name | T2618 |
| Test name | |
| Test status | |
| Simulation time | 123186868230 ps |
| CPU time | 2131.6 seconds |
| Started | May 30 03:49:08 PM PDT 24 |
| Finished | May 30 04:24:41 PM PDT 24 |
| Peak memory | 573316 kb |
| Host | smart-df7c3765-0102-4807-bdf3-7a903ebab0c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065315043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_ device_slow_rsp.1065315043 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.739537917 |
| Short name | T1383 |
| Test name | |
| Test status | |
| Simulation time | 909466074 ps |
| CPU time | 31.73 seconds |
| Started | May 30 03:49:09 PM PDT 24 |
| Finished | May 30 03:49:42 PM PDT 24 |
| Peak memory | 572904 kb |
| Host | smart-d822d7ef-041f-4bce-afee-4c07cb718a28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739537917 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr .739537917 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_random.3285924405 |
| Short name | T1807 |
| Test name | |
| Test status | |
| Simulation time | 547961489 ps |
| CPU time | 49.65 seconds |
| Started | May 30 03:49:14 PM PDT 24 |
| Finished | May 30 03:50:06 PM PDT 24 |
| Peak memory | 572920 kb |
| Host | smart-1653205a-4113-44c2-9a4d-1a4f57588022 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285924405 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.3285924405 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random.2970929369 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 382303112 ps |
| CPU time | 32.12 seconds |
| Started | May 30 03:49:14 PM PDT 24 |
| Finished | May 30 03:49:48 PM PDT 24 |
| Peak memory | 573048 kb |
| Host | smart-14a4258c-0b8a-463a-8d1f-b1068b5d4083 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970929369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random.2970929369 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_large_delays.3813620153 |
| Short name | T2854 |
| Test name | |
| Test status | |
| Simulation time | 71255669328 ps |
| CPU time | 706.21 seconds |
| Started | May 30 03:49:15 PM PDT 24 |
| Finished | May 30 04:01:03 PM PDT 24 |
| Peak memory | 573104 kb |
| Host | smart-2ae3efcf-c095-4a93-a9a0-1528cf5e773e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813620153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.3813620153 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.267502462 |
| Short name | T1547 |
| Test name | |
| Test status | |
| Simulation time | 22578200060 ps |
| CPU time | 389.94 seconds |
| Started | May 30 03:49:10 PM PDT 24 |
| Finished | May 30 03:55:42 PM PDT 24 |
| Peak memory | 573208 kb |
| Host | smart-8e34d1d8-321c-4c80-9dfb-bcf9115ef16f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267502462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.267502462 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.1014373734 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 260287907 ps |
| CPU time | 24.04 seconds |
| Started | May 30 03:49:07 PM PDT 24 |
| Finished | May 30 03:49:32 PM PDT 24 |
| Peak memory | 573068 kb |
| Host | smart-64df3ba6-16f5-4e7f-9383-8a9911d745d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014373734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_del ays.1014373734 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_same_source.2542061297 |
| Short name | T1642 |
| Test name | |
| Test status | |
| Simulation time | 2717452200 ps |
| CPU time | 78.34 seconds |
| Started | May 30 03:49:17 PM PDT 24 |
| Finished | May 30 03:50:38 PM PDT 24 |
| Peak memory | 573112 kb |
| Host | smart-59cad7c0-f794-4ec9-ac03-3f7c140d2f99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542061297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.2542061297 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke.2427702534 |
| Short name | T2649 |
| Test name | |
| Test status | |
| Simulation time | 48527957 ps |
| CPU time | 6.07 seconds |
| Started | May 30 03:49:09 PM PDT 24 |
| Finished | May 30 03:49:17 PM PDT 24 |
| Peak memory | 564852 kb |
| Host | smart-8ed4c33e-035c-480a-b43e-1fde138c660d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427702534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.2427702534 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.4009337292 |
| Short name | T2268 |
| Test name | |
| Test status | |
| Simulation time | 7463102805 ps |
| CPU time | 74.76 seconds |
| Started | May 30 03:49:10 PM PDT 24 |
| Finished | May 30 03:50:27 PM PDT 24 |
| Peak memory | 564948 kb |
| Host | smart-a13141a2-1dfd-4058-9518-89e387bb86cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009337292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.4009337292 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.2947972092 |
| Short name | T2309 |
| Test name | |
| Test status | |
| Simulation time | 5758247671 ps |
| CPU time | 96.77 seconds |
| Started | May 30 03:49:22 PM PDT 24 |
| Finished | May 30 03:51:00 PM PDT 24 |
| Peak memory | 564956 kb |
| Host | smart-5edd0cd6-d8ec-48eb-9a6f-5ddde2db2ea6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947972092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.2947972092 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.2410950191 |
| Short name | T2600 |
| Test name | |
| Test status | |
| Simulation time | 44168435 ps |
| CPU time | 6.15 seconds |
| Started | May 30 03:49:15 PM PDT 24 |
| Finished | May 30 03:49:23 PM PDT 24 |
| Peak memory | 563352 kb |
| Host | smart-2dc82708-1409-480f-89c8-abd4c18924fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410950191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delay s.2410950191 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all.1273548355 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 15823780756 ps |
| CPU time | 601.89 seconds |
| Started | May 30 03:49:13 PM PDT 24 |
| Finished | May 30 03:59:17 PM PDT 24 |
| Peak memory | 573292 kb |
| Host | smart-27d3b489-96fa-46c9-966a-afce8c02db30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273548355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.1273548355 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.2102703257 |
| Short name | T2343 |
| Test name | |
| Test status | |
| Simulation time | 12006646211 ps |
| CPU time | 416.16 seconds |
| Started | May 30 03:49:22 PM PDT 24 |
| Finished | May 30 03:56:20 PM PDT 24 |
| Peak memory | 573160 kb |
| Host | smart-f9da2880-8f4a-4e0e-a72f-840ef133a0ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102703257 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.2102703257 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.1557592343 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 246039914 ps |
| CPU time | 117.47 seconds |
| Started | May 30 03:49:09 PM PDT 24 |
| Finished | May 30 03:51:08 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-acc15f37-2da2-4296-b343-1e8f89d6dcb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557592343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all _with_rand_reset.1557592343 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.2602598478 |
| Short name | T2782 |
| Test name | |
| Test status | |
| Simulation time | 612764173 ps |
| CPU time | 143.08 seconds |
| Started | May 30 03:49:10 PM PDT 24 |
| Finished | May 30 03:51:35 PM PDT 24 |
| Peak memory | 573092 kb |
| Host | smart-762283a5-ccfb-4144-bf43-7d5c5a70d23f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602598478 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_al l_with_reset_error.2602598478 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.3814500715 |
| Short name | T2514 |
| Test name | |
| Test status | |
| Simulation time | 42955803 ps |
| CPU time | 7.3 seconds |
| Started | May 30 03:49:12 PM PDT 24 |
| Finished | May 30 03:49:21 PM PDT 24 |
| Peak memory | 563492 kb |
| Host | smart-da98d15b-c1ee-4dda-977a-e02c543c4a0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814500715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.3814500715 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_csr_rw.1164471071 |
| Short name | T2316 |
| Test name | |
| Test status | |
| Simulation time | 5024227700 ps |
| CPU time | 469.39 seconds |
| Started | May 30 03:49:24 PM PDT 24 |
| Finished | May 30 03:57:14 PM PDT 24 |
| Peak memory | 592160 kb |
| Host | smart-13a7d87f-8f6c-41c6-bc4a-82f5d6758797 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164471071 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_rw.1164471071 |
| Directory | /workspace/15.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.3311266492 |
| Short name | T2545 |
| Test name | |
| Test status | |
| Simulation time | 31773568186 ps |
| CPU time | 4432.98 seconds |
| Started | May 30 03:49:30 PM PDT 24 |
| Finished | May 30 05:03:25 PM PDT 24 |
| Peak memory | 587772 kb |
| Host | smart-80ad8505-b68d-4e8f-a892-d64c43a0d338 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311266492 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 15.chip_same_csr_outstanding.3311266492 |
| Directory | /workspace/15.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_tl_errors.2485993587 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 4337927312 ps |
| CPU time | 251.79 seconds |
| Started | May 30 03:49:06 PM PDT 24 |
| Finished | May 30 03:53:19 PM PDT 24 |
| Peak memory | 594020 kb |
| Host | smart-e3c204bf-006b-410a-a8fb-ecec4d242759 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485993587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_tl_errors.2485993587 |
| Directory | /workspace/15.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device.3508849849 |
| Short name | T2856 |
| Test name | |
| Test status | |
| Simulation time | 393423752 ps |
| CPU time | 21.22 seconds |
| Started | May 30 03:49:25 PM PDT 24 |
| Finished | May 30 03:49:48 PM PDT 24 |
| Peak memory | 573052 kb |
| Host | smart-ee135e5f-7092-4f16-9be5-03c4287823a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508849849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device .3508849849 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.3749539857 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 41154540538 ps |
| CPU time | 667.37 seconds |
| Started | May 30 03:49:14 PM PDT 24 |
| Finished | May 30 04:00:24 PM PDT 24 |
| Peak memory | 573368 kb |
| Host | smart-ed3237c2-ed36-4d04-972d-6e786d753ffc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749539857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_ device_slow_rsp.3749539857 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.99386414 |
| Short name | T1919 |
| Test name | |
| Test status | |
| Simulation time | 200342914 ps |
| CPU time | 22.2 seconds |
| Started | May 30 03:49:15 PM PDT 24 |
| Finished | May 30 03:49:40 PM PDT 24 |
| Peak memory | 573932 kb |
| Host | smart-02143165-301a-4656-9b2b-7f567e1df903 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99386414 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.99386414 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_random.895123121 |
| Short name | T1889 |
| Test name | |
| Test status | |
| Simulation time | 672997660 ps |
| CPU time | 25.43 seconds |
| Started | May 30 03:49:20 PM PDT 24 |
| Finished | May 30 03:49:48 PM PDT 24 |
| Peak memory | 572912 kb |
| Host | smart-8edd3e65-5793-4f15-ac4d-dfc6c6a5baa5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895123121 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.895123121 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random.1647724820 |
| Short name | T1571 |
| Test name | |
| Test status | |
| Simulation time | 614306158 ps |
| CPU time | 53.56 seconds |
| Started | May 30 03:49:15 PM PDT 24 |
| Finished | May 30 03:50:11 PM PDT 24 |
| Peak memory | 573032 kb |
| Host | smart-bc6f4507-1a6c-4c42-a513-23fba5796ca1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647724820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random.1647724820 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_large_delays.402249099 |
| Short name | T1484 |
| Test name | |
| Test status | |
| Simulation time | 80945005584 ps |
| CPU time | 907.34 seconds |
| Started | May 30 03:49:29 PM PDT 24 |
| Finished | May 30 04:04:37 PM PDT 24 |
| Peak memory | 573204 kb |
| Host | smart-2b1486f7-7c02-432b-81b0-517c10504475 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402249099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.402249099 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.3649706150 |
| Short name | T1492 |
| Test name | |
| Test status | |
| Simulation time | 51898089452 ps |
| CPU time | 889.37 seconds |
| Started | May 30 03:49:22 PM PDT 24 |
| Finished | May 30 04:04:13 PM PDT 24 |
| Peak memory | 573140 kb |
| Host | smart-34e0aeb2-0b6e-40e3-8c61-221d84c37662 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649706150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.3649706150 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.1479111213 |
| Short name | T1873 |
| Test name | |
| Test status | |
| Simulation time | 408557319 ps |
| CPU time | 35.05 seconds |
| Started | May 30 03:49:31 PM PDT 24 |
| Finished | May 30 03:50:08 PM PDT 24 |
| Peak memory | 573032 kb |
| Host | smart-1e3995f1-8828-41d9-be5a-5907d5ccd7a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479111213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_del ays.1479111213 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_same_source.1966766481 |
| Short name | T2175 |
| Test name | |
| Test status | |
| Simulation time | 1925942780 ps |
| CPU time | 59.03 seconds |
| Started | May 30 03:49:16 PM PDT 24 |
| Finished | May 30 03:50:18 PM PDT 24 |
| Peak memory | 572620 kb |
| Host | smart-c4682f5b-df5b-4c0c-bc9c-5dafe6de27b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966766481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.1966766481 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke.3589942844 |
| Short name | T1942 |
| Test name | |
| Test status | |
| Simulation time | 178391738 ps |
| CPU time | 8.4 seconds |
| Started | May 30 03:49:17 PM PDT 24 |
| Finished | May 30 03:49:28 PM PDT 24 |
| Peak memory | 564820 kb |
| Host | smart-c90e2f0a-64e8-43c0-bcb2-c05e509c155b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589942844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.3589942844 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.288540370 |
| Short name | T2848 |
| Test name | |
| Test status | |
| Simulation time | 9914352809 ps |
| CPU time | 101.68 seconds |
| Started | May 30 03:49:18 PM PDT 24 |
| Finished | May 30 03:51:02 PM PDT 24 |
| Peak memory | 564940 kb |
| Host | smart-57d07662-361a-4cd7-8b39-b7add395f646 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288540370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.288540370 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.1487700950 |
| Short name | T1325 |
| Test name | |
| Test status | |
| Simulation time | 5925959036 ps |
| CPU time | 104.67 seconds |
| Started | May 30 03:49:15 PM PDT 24 |
| Finished | May 30 03:51:02 PM PDT 24 |
| Peak memory | 564964 kb |
| Host | smart-1420aed9-e450-4100-89f2-786100f0da30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487700950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.1487700950 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.3365946957 |
| Short name | T2769 |
| Test name | |
| Test status | |
| Simulation time | 44112842 ps |
| CPU time | 5.96 seconds |
| Started | May 30 03:49:10 PM PDT 24 |
| Finished | May 30 03:49:18 PM PDT 24 |
| Peak memory | 564772 kb |
| Host | smart-2706f169-d341-4336-93db-a06e1efbfb45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365946957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delay s.3365946957 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.771879211 |
| Short name | T1545 |
| Test name | |
| Test status | |
| Simulation time | 18488366251 ps |
| CPU time | 684.4 seconds |
| Started | May 30 03:49:15 PM PDT 24 |
| Finished | May 30 04:00:42 PM PDT 24 |
| Peak memory | 573224 kb |
| Host | smart-b6852a79-a57d-4b18-a7e7-a9b97c2a957b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771879211 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.771879211 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.3676834342 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 520283952 ps |
| CPU time | 203.81 seconds |
| Started | May 30 03:49:18 PM PDT 24 |
| Finished | May 30 03:52:44 PM PDT 24 |
| Peak memory | 573116 kb |
| Host | smart-95bcdcf7-c73d-4b10-9ce5-e1cc05e71c03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676834342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all _with_rand_reset.3676834342 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.2543461755 |
| Short name | T2742 |
| Test name | |
| Test status | |
| Simulation time | 113981522 ps |
| CPU time | 33.51 seconds |
| Started | May 30 03:49:15 PM PDT 24 |
| Finished | May 30 03:49:51 PM PDT 24 |
| Peak memory | 573108 kb |
| Host | smart-801961bf-52cf-4a83-bc9e-681f912eba5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543461755 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_al l_with_reset_error.2543461755 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.3345820590 |
| Short name | T1601 |
| Test name | |
| Test status | |
| Simulation time | 252330489 ps |
| CPU time | 15.08 seconds |
| Started | May 30 03:49:19 PM PDT 24 |
| Finished | May 30 03:49:36 PM PDT 24 |
| Peak memory | 573000 kb |
| Host | smart-5c385799-6d73-435d-abbe-837293b7611d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345820590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.3345820590 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_csr_rw.291633195 |
| Short name | T2502 |
| Test name | |
| Test status | |
| Simulation time | 5836200108 ps |
| CPU time | 532.11 seconds |
| Started | May 30 03:49:21 PM PDT 24 |
| Finished | May 30 03:58:15 PM PDT 24 |
| Peak memory | 592116 kb |
| Host | smart-9d22bef7-214f-4929-b978-df5319f93d39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291633195 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_csr_rw.291633195 |
| Directory | /workspace/16.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_tl_errors.353380465 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 3341404920 ps |
| CPU time | 252.4 seconds |
| Started | May 30 03:49:14 PM PDT 24 |
| Finished | May 30 03:53:29 PM PDT 24 |
| Peak memory | 594024 kb |
| Host | smart-2f380f9c-d114-4663-9d22-86eb7934e539 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353380465 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_tl_errors.353380465 |
| Directory | /workspace/16.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device.1061559416 |
| Short name | T2117 |
| Test name | |
| Test status | |
| Simulation time | 265953027 ps |
| CPU time | 16.41 seconds |
| Started | May 30 03:49:25 PM PDT 24 |
| Finished | May 30 03:49:43 PM PDT 24 |
| Peak memory | 573044 kb |
| Host | smart-d8f98556-4e47-46c4-8a21-939329a5e4d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061559416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device .1061559416 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.1296184149 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 146453539975 ps |
| CPU time | 2691.14 seconds |
| Started | May 30 03:49:21 PM PDT 24 |
| Finished | May 30 04:34:14 PM PDT 24 |
| Peak memory | 573272 kb |
| Host | smart-aba12547-c46f-4470-b231-5b03763e5f45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296184149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_ device_slow_rsp.1296184149 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.1136637902 |
| Short name | T2140 |
| Test name | |
| Test status | |
| Simulation time | 949896979 ps |
| CPU time | 36.2 seconds |
| Started | May 30 03:49:16 PM PDT 24 |
| Finished | May 30 03:49:55 PM PDT 24 |
| Peak memory | 572916 kb |
| Host | smart-5a117e1d-347b-46db-aa9c-fbc2ccab0327 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136637902 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_add r.1136637902 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_random.678463538 |
| Short name | T2537 |
| Test name | |
| Test status | |
| Simulation time | 32688343 ps |
| CPU time | 6.17 seconds |
| Started | May 30 03:49:21 PM PDT 24 |
| Finished | May 30 03:49:28 PM PDT 24 |
| Peak memory | 564436 kb |
| Host | smart-a95e8cd9-1c8e-4ea3-a902-aef52ae25c4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678463538 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.678463538 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random.2900143291 |
| Short name | T2317 |
| Test name | |
| Test status | |
| Simulation time | 255780029 ps |
| CPU time | 11.4 seconds |
| Started | May 30 03:49:19 PM PDT 24 |
| Finished | May 30 03:49:32 PM PDT 24 |
| Peak memory | 564840 kb |
| Host | smart-0ca0f562-43e5-4045-b881-33f0bcf8dfc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900143291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random.2900143291 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_large_delays.3215656601 |
| Short name | T1781 |
| Test name | |
| Test status | |
| Simulation time | 56400586438 ps |
| CPU time | 634.01 seconds |
| Started | May 30 03:49:18 PM PDT 24 |
| Finished | May 30 03:59:55 PM PDT 24 |
| Peak memory | 573128 kb |
| Host | smart-01c4e56b-4836-45b9-baab-35bd4b9ca79b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215656601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.3215656601 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.3844750786 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 63029024382 ps |
| CPU time | 1079.76 seconds |
| Started | May 30 03:49:21 PM PDT 24 |
| Finished | May 30 04:07:22 PM PDT 24 |
| Peak memory | 573208 kb |
| Host | smart-b5159cf9-c155-4b9b-9dbf-d4e863a2f123 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844750786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.3844750786 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.1906578917 |
| Short name | T2828 |
| Test name | |
| Test status | |
| Simulation time | 38955641 ps |
| CPU time | 6.58 seconds |
| Started | May 30 03:49:24 PM PDT 24 |
| Finished | May 30 03:49:31 PM PDT 24 |
| Peak memory | 564824 kb |
| Host | smart-8ee0f313-0408-427f-804a-7b16ee0f1b96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906578917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_del ays.1906578917 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_same_source.1465018062 |
| Short name | T1900 |
| Test name | |
| Test status | |
| Simulation time | 1250289201 ps |
| CPU time | 37.55 seconds |
| Started | May 30 03:49:26 PM PDT 24 |
| Finished | May 30 03:50:05 PM PDT 24 |
| Peak memory | 573008 kb |
| Host | smart-300d8bc0-d808-44f3-8c66-ecc145581244 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465018062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.1465018062 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke.529889525 |
| Short name | T1386 |
| Test name | |
| Test status | |
| Simulation time | 43672793 ps |
| CPU time | 6.6 seconds |
| Started | May 30 03:49:21 PM PDT 24 |
| Finished | May 30 03:49:29 PM PDT 24 |
| Peak memory | 564840 kb |
| Host | smart-dd402378-4a6a-4f98-a3ac-82f88dc640e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529889525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.529889525 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.911635845 |
| Short name | T1805 |
| Test name | |
| Test status | |
| Simulation time | 5787269616 ps |
| CPU time | 61.99 seconds |
| Started | May 30 03:49:25 PM PDT 24 |
| Finished | May 30 03:50:28 PM PDT 24 |
| Peak memory | 564924 kb |
| Host | smart-6c4f1062-f753-4880-b710-0ff4185511b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911635845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.911635845 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.501621227 |
| Short name | T2681 |
| Test name | |
| Test status | |
| Simulation time | 5573840077 ps |
| CPU time | 89.59 seconds |
| Started | May 30 03:49:13 PM PDT 24 |
| Finished | May 30 03:50:44 PM PDT 24 |
| Peak memory | 563472 kb |
| Host | smart-088625bd-82e2-4574-923e-b93e2978df92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501621227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.501621227 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.11106511 |
| Short name | T2805 |
| Test name | |
| Test status | |
| Simulation time | 45431218 ps |
| CPU time | 6.33 seconds |
| Started | May 30 03:49:15 PM PDT 24 |
| Finished | May 30 03:49:24 PM PDT 24 |
| Peak memory | 563288 kb |
| Host | smart-59caabca-accb-4f98-a128-9e56a2c1a08b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11106511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.11106511 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all.1837329465 |
| Short name | T2436 |
| Test name | |
| Test status | |
| Simulation time | 5097676016 ps |
| CPU time | 173.88 seconds |
| Started | May 30 03:49:18 PM PDT 24 |
| Finished | May 30 03:52:15 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-544cb3f5-595b-4c76-bade-fdc4584bb5fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837329465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.1837329465 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.124522734 |
| Short name | T2020 |
| Test name | |
| Test status | |
| Simulation time | 20368344081 ps |
| CPU time | 876.96 seconds |
| Started | May 30 03:49:15 PM PDT 24 |
| Finished | May 30 04:03:55 PM PDT 24 |
| Peak memory | 578320 kb |
| Host | smart-44050e8c-84e8-4b0c-ac10-78030d7b1b41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124522734 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.124522734 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.279559306 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 550160556 ps |
| CPU time | 166.82 seconds |
| Started | May 30 03:49:22 PM PDT 24 |
| Finished | May 30 03:52:10 PM PDT 24 |
| Peak memory | 573140 kb |
| Host | smart-d1391271-3165-4337-998b-8b00f2eaa98e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279559306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_ with_rand_reset.279559306 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.1995072599 |
| Short name | T1770 |
| Test name | |
| Test status | |
| Simulation time | 461258695 ps |
| CPU time | 141.18 seconds |
| Started | May 30 03:49:19 PM PDT 24 |
| Finished | May 30 03:51:42 PM PDT 24 |
| Peak memory | 573108 kb |
| Host | smart-6cd24bcd-bace-4d14-96da-ddedc3b663b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995072599 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_al l_with_reset_error.1995072599 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.643376673 |
| Short name | T2664 |
| Test name | |
| Test status | |
| Simulation time | 1140424435 ps |
| CPU time | 48.55 seconds |
| Started | May 30 03:49:16 PM PDT 24 |
| Finished | May 30 03:50:07 PM PDT 24 |
| Peak memory | 572980 kb |
| Host | smart-ac575c70-d71c-4cb8-98bb-b1fafd22607c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643376673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.643376673 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_csr_rw.2630944381 |
| Short name | T1588 |
| Test name | |
| Test status | |
| Simulation time | 4320461810 ps |
| CPU time | 304.77 seconds |
| Started | May 30 03:49:38 PM PDT 24 |
| Finished | May 30 03:54:45 PM PDT 24 |
| Peak memory | 593064 kb |
| Host | smart-5e193b39-d417-4ba1-ac74-9dcba8075138 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630944381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_rw.2630944381 |
| Directory | /workspace/17.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.1394120454 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 31412705367 ps |
| CPU time | 3992.7 seconds |
| Started | May 30 03:49:29 PM PDT 24 |
| Finished | May 30 04:56:03 PM PDT 24 |
| Peak memory | 587984 kb |
| Host | smart-21475b01-7e3a-4414-85f9-19e39baae55a |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394120454 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 17.chip_same_csr_outstanding.1394120454 |
| Directory | /workspace/17.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_tl_errors.2960094064 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 3405710109 ps |
| CPU time | 145.49 seconds |
| Started | May 30 03:49:18 PM PDT 24 |
| Finished | May 30 03:51:46 PM PDT 24 |
| Peak memory | 593972 kb |
| Host | smart-e74c7cb2-9e3e-487f-bf06-4c5a407ae946 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960094064 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_tl_errors.2960094064 |
| Directory | /workspace/17.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device.1416642822 |
| Short name | T1940 |
| Test name | |
| Test status | |
| Simulation time | 2400014277 ps |
| CPU time | 108.6 seconds |
| Started | May 30 03:49:22 PM PDT 24 |
| Finished | May 30 03:51:12 PM PDT 24 |
| Peak memory | 573100 kb |
| Host | smart-2b703848-a446-4d88-a486-38b2706c624f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416642822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device .1416642822 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.849065551 |
| Short name | T2053 |
| Test name | |
| Test status | |
| Simulation time | 468831236 ps |
| CPU time | 20.01 seconds |
| Started | May 30 03:49:37 PM PDT 24 |
| Finished | May 30 03:49:59 PM PDT 24 |
| Peak memory | 572832 kb |
| Host | smart-5cb310cd-62b6-4265-bc07-aadf24f4c0e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849065551 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr .849065551 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_random.3303424774 |
| Short name | T2737 |
| Test name | |
| Test status | |
| Simulation time | 161909949 ps |
| CPU time | 8.12 seconds |
| Started | May 30 03:49:25 PM PDT 24 |
| Finished | May 30 03:49:34 PM PDT 24 |
| Peak memory | 564716 kb |
| Host | smart-1f223f6e-70d8-4506-b9a0-9e9048ef183e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303424774 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.3303424774 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random.495818330 |
| Short name | T1977 |
| Test name | |
| Test status | |
| Simulation time | 2116798149 ps |
| CPU time | 65.3 seconds |
| Started | May 30 03:49:29 PM PDT 24 |
| Finished | May 30 03:50:35 PM PDT 24 |
| Peak memory | 573040 kb |
| Host | smart-4e71d1a5-af0d-4d37-9e38-60d154de8ab5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495818330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random.495818330 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_large_delays.1484297237 |
| Short name | T2871 |
| Test name | |
| Test status | |
| Simulation time | 6889432780 ps |
| CPU time | 73.07 seconds |
| Started | May 30 03:49:16 PM PDT 24 |
| Finished | May 30 03:50:31 PM PDT 24 |
| Peak memory | 563540 kb |
| Host | smart-921f9a3e-b9ab-4f9f-ab0c-cd835aad84a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484297237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.1484297237 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.4221007988 |
| Short name | T2644 |
| Test name | |
| Test status | |
| Simulation time | 20644557943 ps |
| CPU time | 371.23 seconds |
| Started | May 30 03:49:15 PM PDT 24 |
| Finished | May 30 03:55:28 PM PDT 24 |
| Peak memory | 573140 kb |
| Host | smart-99f0a83c-4490-452a-8f12-b43358eec571 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221007988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.4221007988 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.2931130845 |
| Short name | T2613 |
| Test name | |
| Test status | |
| Simulation time | 482053627 ps |
| CPU time | 40.16 seconds |
| Started | May 30 03:49:19 PM PDT 24 |
| Finished | May 30 03:50:02 PM PDT 24 |
| Peak memory | 573032 kb |
| Host | smart-18e75296-0022-407e-bc31-e3b5d7c0b653 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931130845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_del ays.2931130845 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_same_source.769680494 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 888145593 ps |
| CPU time | 27.11 seconds |
| Started | May 30 03:49:29 PM PDT 24 |
| Finished | May 30 03:49:57 PM PDT 24 |
| Peak memory | 572768 kb |
| Host | smart-8e52ed94-491e-420a-b138-e2d004650899 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769680494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.769680494 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke.1887185753 |
| Short name | T2194 |
| Test name | |
| Test status | |
| Simulation time | 44031712 ps |
| CPU time | 6.45 seconds |
| Started | May 30 03:49:20 PM PDT 24 |
| Finished | May 30 03:49:28 PM PDT 24 |
| Peak memory | 564816 kb |
| Host | smart-7c111fe0-2d3c-4dd7-8bc8-d6082133fcf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887185753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.1887185753 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.1772638154 |
| Short name | T1448 |
| Test name | |
| Test status | |
| Simulation time | 7616152734 ps |
| CPU time | 82.23 seconds |
| Started | May 30 03:49:25 PM PDT 24 |
| Finished | May 30 03:50:48 PM PDT 24 |
| Peak memory | 563520 kb |
| Host | smart-377f7e89-63cd-4aee-b3ed-3b196d2eb634 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772638154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.1772638154 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.822354609 |
| Short name | T2825 |
| Test name | |
| Test status | |
| Simulation time | 4033261115 ps |
| CPU time | 70.41 seconds |
| Started | May 30 03:49:14 PM PDT 24 |
| Finished | May 30 03:50:27 PM PDT 24 |
| Peak memory | 563428 kb |
| Host | smart-4ca54dfc-5017-4c1a-b8a8-cd18b62c0f27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822354609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.822354609 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.1054463203 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 37695147 ps |
| CPU time | 5.65 seconds |
| Started | May 30 03:49:24 PM PDT 24 |
| Finished | May 30 03:49:30 PM PDT 24 |
| Peak memory | 564772 kb |
| Host | smart-0b264500-d187-4b72-a471-b79bfc621a90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054463203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delay s.1054463203 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all.2238563341 |
| Short name | T2147 |
| Test name | |
| Test status | |
| Simulation time | 6878619188 ps |
| CPU time | 218.16 seconds |
| Started | May 30 03:49:41 PM PDT 24 |
| Finished | May 30 03:53:20 PM PDT 24 |
| Peak memory | 573244 kb |
| Host | smart-3361c348-3bce-44fa-b6b6-4afb5e4f7594 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238563341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.2238563341 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.3397382929 |
| Short name | T2069 |
| Test name | |
| Test status | |
| Simulation time | 8537795842 ps |
| CPU time | 304.08 seconds |
| Started | May 30 03:49:28 PM PDT 24 |
| Finished | May 30 03:54:33 PM PDT 24 |
| Peak memory | 575204 kb |
| Host | smart-d63daa87-1a38-4979-aa1f-ecc6a57c3f1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397382929 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.3397382929 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.85965077 |
| Short name | T1982 |
| Test name | |
| Test status | |
| Simulation time | 3301595298 ps |
| CPU time | 452.16 seconds |
| Started | May 30 03:49:37 PM PDT 24 |
| Finished | May 30 03:57:10 PM PDT 24 |
| Peak memory | 575220 kb |
| Host | smart-c965ebde-5b0d-4812-999e-732e779a34a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85965077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_w ith_rand_reset.85965077 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.862407562 |
| Short name | T1992 |
| Test name | |
| Test status | |
| Simulation time | 2167004723 ps |
| CPU time | 207.99 seconds |
| Started | May 30 03:49:41 PM PDT 24 |
| Finished | May 30 03:53:10 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-45209f1f-001d-441f-8e2f-2be7567bf76a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862407562 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all _with_reset_error.862407562 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.4107123938 |
| Short name | T2527 |
| Test name | |
| Test status | |
| Simulation time | 422047104 ps |
| CPU time | 19.6 seconds |
| Started | May 30 03:49:24 PM PDT 24 |
| Finished | May 30 03:49:45 PM PDT 24 |
| Peak memory | 573004 kb |
| Host | smart-25a3393d-d5b9-4fa4-a078-b7250e823941 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107123938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.4107123938 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_csr_rw.3488185799 |
| Short name | T1562 |
| Test name | |
| Test status | |
| Simulation time | 3873467864 ps |
| CPU time | 253.76 seconds |
| Started | May 30 03:49:40 PM PDT 24 |
| Finished | May 30 03:53:55 PM PDT 24 |
| Peak memory | 591284 kb |
| Host | smart-02f26ade-885e-4f0f-b277-6f53cdd82b89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488185799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_rw.3488185799 |
| Directory | /workspace/18.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.1292246536 |
| Short name | T2764 |
| Test name | |
| Test status | |
| Simulation time | 28243088806 ps |
| CPU time | 3198.61 seconds |
| Started | May 30 03:49:41 PM PDT 24 |
| Finished | May 30 04:43:01 PM PDT 24 |
| Peak memory | 588068 kb |
| Host | smart-0e1e099f-6074-4610-a443-9ed65cd561d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292246536 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 18.chip_same_csr_outstanding.1292246536 |
| Directory | /workspace/18.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_tl_errors.461413442 |
| Short name | T2074 |
| Test name | |
| Test status | |
| Simulation time | 3162684497 ps |
| CPU time | 98.44 seconds |
| Started | May 30 03:49:42 PM PDT 24 |
| Finished | May 30 03:51:21 PM PDT 24 |
| Peak memory | 593940 kb |
| Host | smart-c283b4c0-835e-49ca-a6d2-b81ba1787fba |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461413442 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_tl_errors.461413442 |
| Directory | /workspace/18.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device.3772446625 |
| Short name | T2614 |
| Test name | |
| Test status | |
| Simulation time | 759385871 ps |
| CPU time | 34.25 seconds |
| Started | May 30 03:49:30 PM PDT 24 |
| Finished | May 30 03:50:05 PM PDT 24 |
| Peak memory | 564832 kb |
| Host | smart-04a3d794-34d8-4a8a-af4d-b4fc82c62371 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772446625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device .3772446625 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.3481875898 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 98689299021 ps |
| CPU time | 1867.35 seconds |
| Started | May 30 03:49:29 PM PDT 24 |
| Finished | May 30 04:20:37 PM PDT 24 |
| Peak memory | 573188 kb |
| Host | smart-757f45f9-c2e8-4348-b96d-58272790881c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481875898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_ device_slow_rsp.3481875898 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.1461944602 |
| Short name | T1371 |
| Test name | |
| Test status | |
| Simulation time | 1096539190 ps |
| CPU time | 41.85 seconds |
| Started | May 30 03:49:40 PM PDT 24 |
| Finished | May 30 03:50:23 PM PDT 24 |
| Peak memory | 572900 kb |
| Host | smart-241ed13c-1212-405c-8d1c-20370e991876 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461944602 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_add r.1461944602 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_random.3110549482 |
| Short name | T1357 |
| Test name | |
| Test status | |
| Simulation time | 412324454 ps |
| CPU time | 31.52 seconds |
| Started | May 30 03:49:32 PM PDT 24 |
| Finished | May 30 03:50:05 PM PDT 24 |
| Peak memory | 572880 kb |
| Host | smart-ec89f134-7558-4a5d-a4be-9b9965a85793 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110549482 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.3110549482 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random.118519698 |
| Short name | T1635 |
| Test name | |
| Test status | |
| Simulation time | 2392884901 ps |
| CPU time | 80.38 seconds |
| Started | May 30 03:49:25 PM PDT 24 |
| Finished | May 30 03:50:47 PM PDT 24 |
| Peak memory | 573104 kb |
| Host | smart-434bb907-6646-47fb-95dd-25beb8789255 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118519698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random.118519698 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_large_delays.601821235 |
| Short name | T2138 |
| Test name | |
| Test status | |
| Simulation time | 44188247317 ps |
| CPU time | 446.11 seconds |
| Started | May 30 03:49:27 PM PDT 24 |
| Finished | May 30 03:56:54 PM PDT 24 |
| Peak memory | 573172 kb |
| Host | smart-ccb7268a-1ded-48d5-981c-05b26f6d6214 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601821235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.601821235 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.1508285053 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 39252434988 ps |
| CPU time | 696.98 seconds |
| Started | May 30 03:49:29 PM PDT 24 |
| Finished | May 30 04:01:06 PM PDT 24 |
| Peak memory | 573144 kb |
| Host | smart-e213c58f-67b3-4d81-bff1-95556ccf4ed8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508285053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.1508285053 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.3197527693 |
| Short name | T2232 |
| Test name | |
| Test status | |
| Simulation time | 62393118 ps |
| CPU time | 8.96 seconds |
| Started | May 30 03:49:28 PM PDT 24 |
| Finished | May 30 03:49:37 PM PDT 24 |
| Peak memory | 564848 kb |
| Host | smart-b0841aae-8089-449f-a089-0ba0c48b88d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197527693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_del ays.3197527693 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_same_source.3024137302 |
| Short name | T1775 |
| Test name | |
| Test status | |
| Simulation time | 178459373 ps |
| CPU time | 15.19 seconds |
| Started | May 30 03:49:37 PM PDT 24 |
| Finished | May 30 03:49:53 PM PDT 24 |
| Peak memory | 573012 kb |
| Host | smart-7f71adcf-e62a-4b84-9a97-4a6709499960 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024137302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.3024137302 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke.3328003837 |
| Short name | T1344 |
| Test name | |
| Test status | |
| Simulation time | 48444105 ps |
| CPU time | 5.91 seconds |
| Started | May 30 03:49:24 PM PDT 24 |
| Finished | May 30 03:49:30 PM PDT 24 |
| Peak memory | 564816 kb |
| Host | smart-e6f0a4e7-5967-42a4-ad64-a4d3d736f4ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328003837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.3328003837 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.697527761 |
| Short name | T1416 |
| Test name | |
| Test status | |
| Simulation time | 8898227416 ps |
| CPU time | 89.26 seconds |
| Started | May 30 03:49:32 PM PDT 24 |
| Finished | May 30 03:51:02 PM PDT 24 |
| Peak memory | 564920 kb |
| Host | smart-dafca466-094a-4a7a-87da-8911fde75814 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697527761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.697527761 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.2913468906 |
| Short name | T2816 |
| Test name | |
| Test status | |
| Simulation time | 6236088526 ps |
| CPU time | 101.13 seconds |
| Started | May 30 03:49:30 PM PDT 24 |
| Finished | May 30 03:51:12 PM PDT 24 |
| Peak memory | 564968 kb |
| Host | smart-c7909f73-a764-4a57-bf5f-f121c103ade5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913468906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.2913468906 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.615793662 |
| Short name | T2524 |
| Test name | |
| Test status | |
| Simulation time | 47508077 ps |
| CPU time | 6.18 seconds |
| Started | May 30 03:49:24 PM PDT 24 |
| Finished | May 30 03:49:31 PM PDT 24 |
| Peak memory | 564804 kb |
| Host | smart-ccffb1ed-4e0e-4ed0-a119-f31e005d4f95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615793662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays .615793662 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all.2006754475 |
| Short name | T1535 |
| Test name | |
| Test status | |
| Simulation time | 2169750711 ps |
| CPU time | 83.81 seconds |
| Started | May 30 03:49:29 PM PDT 24 |
| Finished | May 30 03:50:54 PM PDT 24 |
| Peak memory | 575216 kb |
| Host | smart-63aa0703-a75d-479b-b314-0c4d22be6cee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006754475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.2006754475 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.1162214060 |
| Short name | T2387 |
| Test name | |
| Test status | |
| Simulation time | 1124085477 ps |
| CPU time | 75.94 seconds |
| Started | May 30 03:49:38 PM PDT 24 |
| Finished | May 30 03:50:56 PM PDT 24 |
| Peak memory | 572988 kb |
| Host | smart-4218c434-866f-4ba9-8f95-813a83ae6975 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162214060 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.1162214060 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.1335333520 |
| Short name | T2384 |
| Test name | |
| Test status | |
| Simulation time | 3427455004 ps |
| CPU time | 260.37 seconds |
| Started | May 30 03:49:31 PM PDT 24 |
| Finished | May 30 03:53:52 PM PDT 24 |
| Peak memory | 573172 kb |
| Host | smart-ed7ca9cb-e84c-442a-b530-49b2ab582d9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335333520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all _with_rand_reset.1335333520 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.1458959479 |
| Short name | T1740 |
| Test name | |
| Test status | |
| Simulation time | 578197228 ps |
| CPU time | 192.38 seconds |
| Started | May 30 03:49:33 PM PDT 24 |
| Finished | May 30 03:52:46 PM PDT 24 |
| Peak memory | 579344 kb |
| Host | smart-23a5ab28-93a1-4ba3-9cbe-85d1fdaba735 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458959479 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_al l_with_reset_error.1458959479 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.2980437679 |
| Short name | T1971 |
| Test name | |
| Test status | |
| Simulation time | 1058692533 ps |
| CPU time | 44.95 seconds |
| Started | May 30 03:49:41 PM PDT 24 |
| Finished | May 30 03:50:27 PM PDT 24 |
| Peak memory | 573048 kb |
| Host | smart-e757e262-e088-4ff8-bb41-894e2acb8217 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980437679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.2980437679 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_csr_rw.3843916034 |
| Short name | T2673 |
| Test name | |
| Test status | |
| Simulation time | 4387452772 ps |
| CPU time | 251.83 seconds |
| Started | May 30 03:49:51 PM PDT 24 |
| Finished | May 30 03:54:04 PM PDT 24 |
| Peak memory | 593332 kb |
| Host | smart-f6556104-8acb-4f7f-94e1-26ad70e8037d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843916034 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_csr_rw.3843916034 |
| Directory | /workspace/19.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.2894782051 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 27530966098 ps |
| CPU time | 4303.45 seconds |
| Started | May 30 03:49:32 PM PDT 24 |
| Finished | May 30 05:01:17 PM PDT 24 |
| Peak memory | 587844 kb |
| Host | smart-9bf3b133-136d-45cb-80d2-35a94bd4cb1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894782051 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 19.chip_same_csr_outstanding.2894782051 |
| Directory | /workspace/19.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_tl_errors.4272738738 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 3592814187 ps |
| CPU time | 252.45 seconds |
| Started | May 30 03:49:33 PM PDT 24 |
| Finished | May 30 03:53:46 PM PDT 24 |
| Peak memory | 594028 kb |
| Host | smart-26da0fe1-18e0-4d65-86e0-b6c321fd1c65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272738738 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_tl_errors.4272738738 |
| Directory | /workspace/19.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device.2504095099 |
| Short name | T2381 |
| Test name | |
| Test status | |
| Simulation time | 490309459 ps |
| CPU time | 23.38 seconds |
| Started | May 30 03:49:35 PM PDT 24 |
| Finished | May 30 03:50:00 PM PDT 24 |
| Peak memory | 573024 kb |
| Host | smart-1523a309-cea3-4c1c-8ccc-996063cc0ac9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504095099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device .2504095099 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.2867458357 |
| Short name | T2831 |
| Test name | |
| Test status | |
| Simulation time | 166813849259 ps |
| CPU time | 2891.3 seconds |
| Started | May 30 03:49:38 PM PDT 24 |
| Finished | May 30 04:37:51 PM PDT 24 |
| Peak memory | 573292 kb |
| Host | smart-154749ba-a74b-4dd5-80d1-a228c4ae67c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867458357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_ device_slow_rsp.2867458357 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.745564257 |
| Short name | T2819 |
| Test name | |
| Test status | |
| Simulation time | 1157778658 ps |
| CPU time | 41.33 seconds |
| Started | May 30 03:49:51 PM PDT 24 |
| Finished | May 30 03:50:34 PM PDT 24 |
| Peak memory | 572880 kb |
| Host | smart-bffbd677-6c61-45ae-9c82-daea9e7391bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745564257 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr .745564257 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_random.2208654353 |
| Short name | T1413 |
| Test name | |
| Test status | |
| Simulation time | 1928039487 ps |
| CPU time | 70.41 seconds |
| Started | May 30 03:49:52 PM PDT 24 |
| Finished | May 30 03:51:03 PM PDT 24 |
| Peak memory | 572932 kb |
| Host | smart-88f42f46-f670-42ef-8db1-435da477c774 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208654353 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.2208654353 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random.3723435902 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 778727334 ps |
| CPU time | 27.73 seconds |
| Started | May 30 03:49:44 PM PDT 24 |
| Finished | May 30 03:50:12 PM PDT 24 |
| Peak memory | 573080 kb |
| Host | smart-a754c893-9c95-4165-8449-22903f5d5faa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723435902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random.3723435902 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_large_delays.3558082870 |
| Short name | T2256 |
| Test name | |
| Test status | |
| Simulation time | 27497186440 ps |
| CPU time | 291.85 seconds |
| Started | May 30 03:49:34 PM PDT 24 |
| Finished | May 30 03:54:27 PM PDT 24 |
| Peak memory | 573188 kb |
| Host | smart-83908fc5-cade-4318-8326-5069f3c821bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558082870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.3558082870 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.3102189914 |
| Short name | T2010 |
| Test name | |
| Test status | |
| Simulation time | 14469694420 ps |
| CPU time | 242.1 seconds |
| Started | May 30 03:49:45 PM PDT 24 |
| Finished | May 30 03:53:47 PM PDT 24 |
| Peak memory | 573208 kb |
| Host | smart-c7031437-755f-43b8-9e38-3db1affcbd11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102189914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.3102189914 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.818438585 |
| Short name | T2282 |
| Test name | |
| Test status | |
| Simulation time | 603719889 ps |
| CPU time | 45.7 seconds |
| Started | May 30 03:49:44 PM PDT 24 |
| Finished | May 30 03:50:30 PM PDT 24 |
| Peak memory | 572952 kb |
| Host | smart-8a16611f-85c3-4c32-8210-eb81c62caa4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818438585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_dela ys.818438585 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_same_source.2076191136 |
| Short name | T1917 |
| Test name | |
| Test status | |
| Simulation time | 2245647296 ps |
| CPU time | 71.78 seconds |
| Started | May 30 03:49:38 PM PDT 24 |
| Finished | May 30 03:50:52 PM PDT 24 |
| Peak memory | 573104 kb |
| Host | smart-916df2ed-1d38-46d0-8f84-3bbbe7bd03a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076191136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.2076191136 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke.3678246208 |
| Short name | T1730 |
| Test name | |
| Test status | |
| Simulation time | 42671110 ps |
| CPU time | 6.56 seconds |
| Started | May 30 03:49:27 PM PDT 24 |
| Finished | May 30 03:49:34 PM PDT 24 |
| Peak memory | 563372 kb |
| Host | smart-ca94e747-03f9-404f-879f-6c41c035ada9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678246208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.3678246208 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_large_delays.4106134424 |
| Short name | T2148 |
| Test name | |
| Test status | |
| Simulation time | 10223194134 ps |
| CPU time | 105.78 seconds |
| Started | May 30 03:49:38 PM PDT 24 |
| Finished | May 30 03:51:25 PM PDT 24 |
| Peak memory | 564960 kb |
| Host | smart-c4163004-dcdb-4e76-b9e9-57d86873aaa1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106134424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.4106134424 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.2300559230 |
| Short name | T1572 |
| Test name | |
| Test status | |
| Simulation time | 4609188482 ps |
| CPU time | 79.1 seconds |
| Started | May 30 03:49:44 PM PDT 24 |
| Finished | May 30 03:51:04 PM PDT 24 |
| Peak memory | 564964 kb |
| Host | smart-fd3de7f3-7b0f-4a53-8655-c2550b4d5ca8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300559230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.2300559230 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.4017666344 |
| Short name | T2405 |
| Test name | |
| Test status | |
| Simulation time | 41460748 ps |
| CPU time | 5.88 seconds |
| Started | May 30 03:49:25 PM PDT 24 |
| Finished | May 30 03:49:32 PM PDT 24 |
| Peak memory | 563340 kb |
| Host | smart-0f95fcce-123a-4fed-a717-fccab2d93508 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017666344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delay s.4017666344 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all.3479137937 |
| Short name | T2101 |
| Test name | |
| Test status | |
| Simulation time | 1934722606 ps |
| CPU time | 190.44 seconds |
| Started | May 30 03:49:53 PM PDT 24 |
| Finished | May 30 03:53:04 PM PDT 24 |
| Peak memory | 573172 kb |
| Host | smart-e0f191a3-c38c-4daa-9790-be12b851be7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479137937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.3479137937 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.3561959598 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 6313367950 ps |
| CPU time | 233.83 seconds |
| Started | May 30 03:49:52 PM PDT 24 |
| Finished | May 30 03:53:46 PM PDT 24 |
| Peak memory | 581400 kb |
| Host | smart-2bf9dfc0-baf1-4de1-8ba9-f2906ff34bf6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561959598 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.3561959598 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.1353105975 |
| Short name | T1849 |
| Test name | |
| Test status | |
| Simulation time | 1895946997 ps |
| CPU time | 223.28 seconds |
| Started | May 30 03:49:51 PM PDT 24 |
| Finished | May 30 03:53:36 PM PDT 24 |
| Peak memory | 573176 kb |
| Host | smart-cc1d2e30-a7c3-4cd5-abf5-699023f6f153 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353105975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all _with_rand_reset.1353105975 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.3102407640 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 15685614911 ps |
| CPU time | 742.97 seconds |
| Started | May 30 03:49:53 PM PDT 24 |
| Finished | May 30 04:02:17 PM PDT 24 |
| Peak memory | 581368 kb |
| Host | smart-cb4160aa-f588-4124-a878-2783453dc406 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102407640 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_al l_with_reset_error.3102407640 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.311748348 |
| Short name | T1876 |
| Test name | |
| Test status | |
| Simulation time | 1059812032 ps |
| CPU time | 44.49 seconds |
| Started | May 30 03:49:51 PM PDT 24 |
| Finished | May 30 03:50:36 PM PDT 24 |
| Peak memory | 573044 kb |
| Host | smart-8cbf3405-fbfd-424a-8c69-b365964f1eb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311748348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.311748348 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_aliasing.3192796496 |
| Short name | T2240 |
| Test name | |
| Test status | |
| Simulation time | 30948318146 ps |
| CPU time | 5945.89 seconds |
| Started | May 30 03:48:36 PM PDT 24 |
| Finished | May 30 05:27:44 PM PDT 24 |
| Peak memory | 588228 kb |
| Host | smart-768d653d-d815-46fc-86a9-41c58f6efb90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192796496 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 2.chip_csr_aliasing.3192796496 |
| Directory | /workspace/2.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.1213121240 |
| Short name | T2298 |
| Test name | |
| Test status | |
| Simulation time | 7255664776 ps |
| CPU time | 680.56 seconds |
| Started | May 30 03:48:35 PM PDT 24 |
| Finished | May 30 03:59:56 PM PDT 24 |
| Peak memory | 586012 kb |
| Host | smart-5141f29c-6f6d-4def-ac81-96623b57593c |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213121240 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 2.chip_csr_bit_bash.1213121240 |
| Directory | /workspace/2.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.4085586397 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 4524182439 ps |
| CPU time | 194.26 seconds |
| Started | May 30 03:48:48 PM PDT 24 |
| Finished | May 30 03:52:04 PM PDT 24 |
| Peak memory | 658124 kb |
| Host | smart-ee343b49-89b9-4096-954b-53a65beeb5e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085586397 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_hw_r eset.4085586397 |
| Directory | /workspace/2.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_rw.3139791687 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 5044063149 ps |
| CPU time | 513.11 seconds |
| Started | May 30 03:48:48 PM PDT 24 |
| Finished | May 30 03:57:23 PM PDT 24 |
| Peak memory | 591688 kb |
| Host | smart-a87703c3-6919-46d0-b2a0-d6496b208ac6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139791687 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_rw.3139791687 |
| Directory | /workspace/2.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_prim_tl_access.2983281201 |
| Short name | T2692 |
| Test name | |
| Test status | |
| Simulation time | 5326375428 ps |
| CPU time | 188.12 seconds |
| Started | May 30 03:48:42 PM PDT 24 |
| Finished | May 30 03:51:51 PM PDT 24 |
| Peak memory | 586780 kb |
| Host | smart-4117aa18-ec7c-48f3-a4ed-e6ca10d07360 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983281201 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_prim_tl_access.2983281201 |
| Directory | /workspace/2.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.3159120347 |
| Short name | T1317 |
| Test name | |
| Test status | |
| Simulation time | 8940123369 ps |
| CPU time | 255.01 seconds |
| Started | May 30 03:48:37 PM PDT 24 |
| Finished | May 30 03:52:53 PM PDT 24 |
| Peak memory | 583224 kb |
| Host | smart-9f94d504-8e34-4a00-9aba-61c140e483b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159120347 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_lc_disabled.3159120347 |
| Directory | /workspace/2.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.174460539 |
| Short name | T2500 |
| Test name | |
| Test status | |
| Simulation time | 14476588798 ps |
| CPU time | 2139.04 seconds |
| Started | May 30 03:48:29 PM PDT 24 |
| Finished | May 30 04:24:09 PM PDT 24 |
| Peak memory | 587360 kb |
| Host | smart-c719faed-a3fa-440b-8223-5119638f01a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174460539 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 2.chip_same_csr_outstanding.174460539 |
| Directory | /workspace/2.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device.2661536006 |
| Short name | T1970 |
| Test name | |
| Test status | |
| Simulation time | 1670157530 ps |
| CPU time | 80.32 seconds |
| Started | May 30 03:48:37 PM PDT 24 |
| Finished | May 30 03:49:58 PM PDT 24 |
| Peak memory | 573124 kb |
| Host | smart-a995fb6e-ad83-42a7-a0fa-7b587af9b654 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661536006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device. 2661536006 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.2863211151 |
| Short name | T2078 |
| Test name | |
| Test status | |
| Simulation time | 103050371495 ps |
| CPU time | 1994.95 seconds |
| Started | May 30 03:48:39 PM PDT 24 |
| Finished | May 30 04:21:56 PM PDT 24 |
| Peak memory | 573228 kb |
| Host | smart-39925f88-eb58-47a8-814e-90abc773d0da |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863211151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_d evice_slow_rsp.2863211151 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.1998892422 |
| Short name | T1353 |
| Test name | |
| Test status | |
| Simulation time | 1400381629 ps |
| CPU time | 51.35 seconds |
| Started | May 30 03:48:33 PM PDT 24 |
| Finished | May 30 03:49:25 PM PDT 24 |
| Peak memory | 572864 kb |
| Host | smart-924e93e6-4e1a-478c-937d-4b8dd70deaf3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998892422 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr .1998892422 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_random.3809440491 |
| Short name | T1894 |
| Test name | |
| Test status | |
| Simulation time | 594341998 ps |
| CPU time | 43.11 seconds |
| Started | May 30 03:48:40 PM PDT 24 |
| Finished | May 30 03:49:25 PM PDT 24 |
| Peak memory | 572852 kb |
| Host | smart-fdae87c0-3c05-4fa8-808f-1b627bd8a4d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809440491 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.3809440491 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random.3003063059 |
| Short name | T2765 |
| Test name | |
| Test status | |
| Simulation time | 867248003 ps |
| CPU time | 31.43 seconds |
| Started | May 30 03:48:37 PM PDT 24 |
| Finished | May 30 03:49:10 PM PDT 24 |
| Peak memory | 573068 kb |
| Host | smart-c3f7fb51-158a-4530-ae48-5dbb0cf9e045 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003063059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random.3003063059 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_large_delays.150954921 |
| Short name | T1630 |
| Test name | |
| Test status | |
| Simulation time | 97516112685 ps |
| CPU time | 1017.52 seconds |
| Started | May 30 03:48:28 PM PDT 24 |
| Finished | May 30 04:05:26 PM PDT 24 |
| Peak memory | 573068 kb |
| Host | smart-601f2268-ef54-4fc2-94f5-2ba79dfa3e84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150954921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.150954921 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_slow_rsp.2211555813 |
| Short name | T2058 |
| Test name | |
| Test status | |
| Simulation time | 49735472794 ps |
| CPU time | 814.33 seconds |
| Started | May 30 03:48:38 PM PDT 24 |
| Finished | May 30 04:02:14 PM PDT 24 |
| Peak memory | 573212 kb |
| Host | smart-f3c24dcc-b9fb-465d-9e66-56cf6d706dfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211555813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.2211555813 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_zero_delays.905776381 |
| Short name | T1502 |
| Test name | |
| Test status | |
| Simulation time | 596085201 ps |
| CPU time | 48.33 seconds |
| Started | May 30 03:48:36 PM PDT 24 |
| Finished | May 30 03:49:26 PM PDT 24 |
| Peak memory | 573048 kb |
| Host | smart-63965ab0-cf4c-4a91-bf49-c8a3701ceaf3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905776381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delay s.905776381 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_same_source.778690914 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 358320428 ps |
| CPU time | 23.28 seconds |
| Started | May 30 03:48:39 PM PDT 24 |
| Finished | May 30 03:49:03 PM PDT 24 |
| Peak memory | 573028 kb |
| Host | smart-da4d8253-3457-437c-8fa7-aa729193259c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778690914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.778690914 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke.82395596 |
| Short name | T2326 |
| Test name | |
| Test status | |
| Simulation time | 196018398 ps |
| CPU time | 7.95 seconds |
| Started | May 30 03:48:37 PM PDT 24 |
| Finished | May 30 03:48:46 PM PDT 24 |
| Peak memory | 564840 kb |
| Host | smart-b4ac9686-39a4-4705-afcd-8367b33a5e41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82395596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.82395596 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.66509147 |
| Short name | T1430 |
| Test name | |
| Test status | |
| Simulation time | 9316819081 ps |
| CPU time | 95.71 seconds |
| Started | May 30 03:48:36 PM PDT 24 |
| Finished | May 30 03:50:12 PM PDT 24 |
| Peak memory | 564924 kb |
| Host | smart-d00f89e9-a4f6-4792-acd0-f5c26a8234ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66509147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.66509147 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.2935780699 |
| Short name | T1369 |
| Test name | |
| Test status | |
| Simulation time | 6746207402 ps |
| CPU time | 105.63 seconds |
| Started | May 30 03:48:42 PM PDT 24 |
| Finished | May 30 03:50:29 PM PDT 24 |
| Peak memory | 564976 kb |
| Host | smart-9383562e-e142-4de4-aa7f-78a8bccdf0d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935780699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.2935780699 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_zero_delays.1972967963 |
| Short name | T1440 |
| Test name | |
| Test status | |
| Simulation time | 48741483 ps |
| CPU time | 6.06 seconds |
| Started | May 30 03:48:35 PM PDT 24 |
| Finished | May 30 03:48:42 PM PDT 24 |
| Peak memory | 564800 kb |
| Host | smart-39d168cc-38fa-4569-b7ae-bfb000bf1069 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972967963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays .1972967963 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all.2498065847 |
| Short name | T1974 |
| Test name | |
| Test status | |
| Simulation time | 1911123365 ps |
| CPU time | 135.04 seconds |
| Started | May 30 03:48:48 PM PDT 24 |
| Finished | May 30 03:51:04 PM PDT 24 |
| Peak memory | 573144 kb |
| Host | smart-fdf50984-decd-45e0-9797-595bf057e06b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498065847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.2498065847 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.1450608168 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 4014000869 ps |
| CPU time | 271.9 seconds |
| Started | May 30 03:48:39 PM PDT 24 |
| Finished | May 30 03:53:13 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-5d12d97c-420f-47fd-9900-096959a4cc07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450608168 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.1450608168 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.1027284996 |
| Short name | T1575 |
| Test name | |
| Test status | |
| Simulation time | 254064780 ps |
| CPU time | 73.1 seconds |
| Started | May 30 03:48:37 PM PDT 24 |
| Finished | May 30 03:49:51 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-ec7312f2-ade0-4161-b024-8bffc85429ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027284996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_ with_rand_reset.1027284996 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.988138149 |
| Short name | T2733 |
| Test name | |
| Test status | |
| Simulation time | 368287789 ps |
| CPU time | 134.27 seconds |
| Started | May 30 03:48:39 PM PDT 24 |
| Finished | May 30 03:50:55 PM PDT 24 |
| Peak memory | 573116 kb |
| Host | smart-b5ee3a29-b504-49eb-8e3e-217be0931320 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988138149 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_ with_reset_error.988138149 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_unmapped_addr.2351992294 |
| Short name | T2730 |
| Test name | |
| Test status | |
| Simulation time | 248603475 ps |
| CPU time | 29.11 seconds |
| Started | May 30 03:48:38 PM PDT 24 |
| Finished | May 30 03:49:09 PM PDT 24 |
| Peak memory | 573108 kb |
| Host | smart-f708075a-8803-4034-84cc-eb5e8424f549 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351992294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.2351992294 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.chip_tl_errors.2037060200 |
| Short name | T2564 |
| Test name | |
| Test status | |
| Simulation time | 3161556476 ps |
| CPU time | 139.61 seconds |
| Started | May 30 03:49:54 PM PDT 24 |
| Finished | May 30 03:52:14 PM PDT 24 |
| Peak memory | 594044 kb |
| Host | smart-95b352a7-0959-470e-93c8-c149d58c6b22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037060200 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.chip_tl_errors.2037060200 |
| Directory | /workspace/20.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device.3400227713 |
| Short name | T2151 |
| Test name | |
| Test status | |
| Simulation time | 117542249 ps |
| CPU time | 11.86 seconds |
| Started | May 30 03:50:03 PM PDT 24 |
| Finished | May 30 03:50:16 PM PDT 24 |
| Peak memory | 564804 kb |
| Host | smart-2214b952-61bf-43e8-bcf3-211cd2251445 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400227713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device .3400227713 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.4057029168 |
| Short name | T1859 |
| Test name | |
| Test status | |
| Simulation time | 90583818218 ps |
| CPU time | 1578.29 seconds |
| Started | May 30 03:50:03 PM PDT 24 |
| Finished | May 30 04:16:24 PM PDT 24 |
| Peak memory | 573228 kb |
| Host | smart-63de2c61-cd5a-4933-bb51-dfcd6b1362cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057029168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_ device_slow_rsp.4057029168 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.1698398121 |
| Short name | T2330 |
| Test name | |
| Test status | |
| Simulation time | 893001664 ps |
| CPU time | 35.19 seconds |
| Started | May 30 03:50:03 PM PDT 24 |
| Finished | May 30 03:50:40 PM PDT 24 |
| Peak memory | 573952 kb |
| Host | smart-8acd8044-90b9-4b1f-8bb8-a864d19279f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698398121 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_add r.1698398121 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_random.1271159159 |
| Short name | T1918 |
| Test name | |
| Test status | |
| Simulation time | 218928759 ps |
| CPU time | 19 seconds |
| Started | May 30 03:50:03 PM PDT 24 |
| Finished | May 30 03:50:23 PM PDT 24 |
| Peak memory | 572784 kb |
| Host | smart-d52caec5-00af-4727-aef5-eb7c69f2d6a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271159159 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.1271159159 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random.3736884869 |
| Short name | T2707 |
| Test name | |
| Test status | |
| Simulation time | 1248443132 ps |
| CPU time | 46.26 seconds |
| Started | May 30 03:50:00 PM PDT 24 |
| Finished | May 30 03:50:48 PM PDT 24 |
| Peak memory | 573072 kb |
| Host | smart-b6d82831-56c0-4b9f-82a3-7f94a9b1eab6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736884869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random.3736884869 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_large_delays.661775055 |
| Short name | T2507 |
| Test name | |
| Test status | |
| Simulation time | 59078478152 ps |
| CPU time | 608.31 seconds |
| Started | May 30 03:50:00 PM PDT 24 |
| Finished | May 30 04:00:10 PM PDT 24 |
| Peak memory | 573172 kb |
| Host | smart-f49c1f3b-eb03-4606-b77c-f4110bf31017 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661775055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.661775055 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_slow_rsp.342745803 |
| Short name | T1979 |
| Test name | |
| Test status | |
| Simulation time | 17447766299 ps |
| CPU time | 321.76 seconds |
| Started | May 30 03:50:02 PM PDT 24 |
| Finished | May 30 03:55:25 PM PDT 24 |
| Peak memory | 573104 kb |
| Host | smart-0bbd32e6-5bd1-4b80-a98f-31cca53b94e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342745803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.342745803 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.1696073211 |
| Short name | T2862 |
| Test name | |
| Test status | |
| Simulation time | 154846926 ps |
| CPU time | 17.64 seconds |
| Started | May 30 03:50:02 PM PDT 24 |
| Finished | May 30 03:50:21 PM PDT 24 |
| Peak memory | 572904 kb |
| Host | smart-344cf986-6e2b-466a-a85d-74efbd7cfb7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696073211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_del ays.1696073211 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_same_source.3339110176 |
| Short name | T2344 |
| Test name | |
| Test status | |
| Simulation time | 465412807 ps |
| CPU time | 38.42 seconds |
| Started | May 30 03:50:02 PM PDT 24 |
| Finished | May 30 03:50:42 PM PDT 24 |
| Peak memory | 573040 kb |
| Host | smart-8bc054fb-31d6-4b3b-b81b-d8eed47508d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339110176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.3339110176 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke.811100527 |
| Short name | T2145 |
| Test name | |
| Test status | |
| Simulation time | 222962607 ps |
| CPU time | 10.18 seconds |
| Started | May 30 03:50:05 PM PDT 24 |
| Finished | May 30 03:50:16 PM PDT 24 |
| Peak memory | 563392 kb |
| Host | smart-88cd3a88-8236-4210-9ebe-d9067ce9a20a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811100527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.811100527 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.682103992 |
| Short name | T2158 |
| Test name | |
| Test status | |
| Simulation time | 7931850753 ps |
| CPU time | 77.21 seconds |
| Started | May 30 03:50:01 PM PDT 24 |
| Finished | May 30 03:51:19 PM PDT 24 |
| Peak memory | 563524 kb |
| Host | smart-80a22e99-c11b-4691-850a-97f64ac6fef6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682103992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.682103992 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.123521852 |
| Short name | T1329 |
| Test name | |
| Test status | |
| Simulation time | 5048760207 ps |
| CPU time | 89.24 seconds |
| Started | May 30 03:50:03 PM PDT 24 |
| Finished | May 30 03:51:34 PM PDT 24 |
| Peak memory | 564944 kb |
| Host | smart-2517bd49-d299-488a-aa84-2db4ddf22589 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123521852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.123521852 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_zero_delays.2375643277 |
| Short name | T1845 |
| Test name | |
| Test status | |
| Simulation time | 45823627 ps |
| CPU time | 5.85 seconds |
| Started | May 30 03:50:03 PM PDT 24 |
| Finished | May 30 03:50:10 PM PDT 24 |
| Peak memory | 564780 kb |
| Host | smart-7732b708-b03d-49e8-8c79-f49b80c93db1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375643277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delay s.2375643277 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all.1245976101 |
| Short name | T2852 |
| Test name | |
| Test status | |
| Simulation time | 2801243021 ps |
| CPU time | 250.17 seconds |
| Started | May 30 03:50:02 PM PDT 24 |
| Finished | May 30 03:54:14 PM PDT 24 |
| Peak memory | 573172 kb |
| Host | smart-6b66c829-3874-4671-adb0-e6b8d07c5838 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245976101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.1245976101 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.679108220 |
| Short name | T1998 |
| Test name | |
| Test status | |
| Simulation time | 8958325367 ps |
| CPU time | 308.34 seconds |
| Started | May 30 03:50:02 PM PDT 24 |
| Finished | May 30 03:55:12 PM PDT 24 |
| Peak memory | 573188 kb |
| Host | smart-d138011c-91d6-4552-8849-360bd4435d6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679108220 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.679108220 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.3970709571 |
| Short name | T2485 |
| Test name | |
| Test status | |
| Simulation time | 3667342134 ps |
| CPU time | 538.5 seconds |
| Started | May 30 03:50:03 PM PDT 24 |
| Finished | May 30 03:59:04 PM PDT 24 |
| Peak memory | 580108 kb |
| Host | smart-4009430f-6ac3-4cae-bbfb-d3a8fddf7851 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970709571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all _with_rand_reset.3970709571 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.2521867682 |
| Short name | T2624 |
| Test name | |
| Test status | |
| Simulation time | 9025135143 ps |
| CPU time | 547.06 seconds |
| Started | May 30 03:50:04 PM PDT 24 |
| Finished | May 30 03:59:13 PM PDT 24 |
| Peak memory | 573224 kb |
| Host | smart-cef4824b-ef33-40bf-9ae8-dd3ef8aac599 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521867682 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_al l_with_reset_error.2521867682 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.2751720127 |
| Short name | T1908 |
| Test name | |
| Test status | |
| Simulation time | 167509552 ps |
| CPU time | 10.3 seconds |
| Started | May 30 03:50:04 PM PDT 24 |
| Finished | May 30 03:50:16 PM PDT 24 |
| Peak memory | 564876 kb |
| Host | smart-37bb3a36-fb5a-4132-9a69-8ea902edc770 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751720127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.2751720127 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.chip_tl_errors.3262586744 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 3507739449 ps |
| CPU time | 169.58 seconds |
| Started | May 30 03:50:15 PM PDT 24 |
| Finished | May 30 03:53:05 PM PDT 24 |
| Peak memory | 602152 kb |
| Host | smart-8f856285-5c5d-4ded-bfcf-70b2620027aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262586744 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.chip_tl_errors.3262586744 |
| Directory | /workspace/21.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device.2856272362 |
| Short name | T2017 |
| Test name | |
| Test status | |
| Simulation time | 1119770192 ps |
| CPU time | 71.8 seconds |
| Started | May 30 03:50:12 PM PDT 24 |
| Finished | May 30 03:51:25 PM PDT 24 |
| Peak memory | 572984 kb |
| Host | smart-cd7905c3-e53d-4d4c-becc-19ce0641c094 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856272362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device .2856272362 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.3481258695 |
| Short name | T2756 |
| Test name | |
| Test status | |
| Simulation time | 41497499041 ps |
| CPU time | 707.52 seconds |
| Started | May 30 03:50:12 PM PDT 24 |
| Finished | May 30 04:02:01 PM PDT 24 |
| Peak memory | 573260 kb |
| Host | smart-5257aba3-993b-4938-a0ea-feb4d797ce57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481258695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_ device_slow_rsp.3481258695 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.3223524443 |
| Short name | T1322 |
| Test name | |
| Test status | |
| Simulation time | 258268454 ps |
| CPU time | 25.97 seconds |
| Started | May 30 03:50:13 PM PDT 24 |
| Finished | May 30 03:50:40 PM PDT 24 |
| Peak memory | 573956 kb |
| Host | smart-34ed24a9-42d3-4520-b5f5-f4fcab1b4b0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223524443 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_add r.3223524443 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_random.3297446025 |
| Short name | T1333 |
| Test name | |
| Test status | |
| Simulation time | 200163035 ps |
| CPU time | 19.19 seconds |
| Started | May 30 03:50:12 PM PDT 24 |
| Finished | May 30 03:50:32 PM PDT 24 |
| Peak memory | 572900 kb |
| Host | smart-f342b385-4bad-4876-8efc-6362cbb3a53a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297446025 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.3297446025 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random.3414172790 |
| Short name | T2086 |
| Test name | |
| Test status | |
| Simulation time | 1483849912 ps |
| CPU time | 55.7 seconds |
| Started | May 30 03:50:11 PM PDT 24 |
| Finished | May 30 03:51:07 PM PDT 24 |
| Peak memory | 572996 kb |
| Host | smart-bc5e5ee2-2d25-4a69-a373-0e0275ab1898 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414172790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random.3414172790 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_large_delays.3522125176 |
| Short name | T2307 |
| Test name | |
| Test status | |
| Simulation time | 88895699252 ps |
| CPU time | 913.05 seconds |
| Started | May 30 03:50:12 PM PDT 24 |
| Finished | May 30 04:05:27 PM PDT 24 |
| Peak memory | 573188 kb |
| Host | smart-8a469b3f-1f05-4137-93ba-ceb2d9851a62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522125176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.3522125176 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_slow_rsp.3509718554 |
| Short name | T1609 |
| Test name | |
| Test status | |
| Simulation time | 24559278446 ps |
| CPU time | 432.13 seconds |
| Started | May 30 03:50:20 PM PDT 24 |
| Finished | May 30 03:57:33 PM PDT 24 |
| Peak memory | 573176 kb |
| Host | smart-2d5348ea-52f8-43fc-aeff-9fa26b84da18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509718554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.3509718554 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.785565398 |
| Short name | T1458 |
| Test name | |
| Test status | |
| Simulation time | 523549457 ps |
| CPU time | 48.2 seconds |
| Started | May 30 03:50:11 PM PDT 24 |
| Finished | May 30 03:51:00 PM PDT 24 |
| Peak memory | 572944 kb |
| Host | smart-de534b1e-bbc6-45af-b9b6-19d86a976dd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785565398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_dela ys.785565398 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_same_source.1452381732 |
| Short name | T1948 |
| Test name | |
| Test status | |
| Simulation time | 2150638461 ps |
| CPU time | 69.31 seconds |
| Started | May 30 03:50:13 PM PDT 24 |
| Finished | May 30 03:51:23 PM PDT 24 |
| Peak memory | 573124 kb |
| Host | smart-f90695b3-579c-4030-bb2f-c46e8b585ebd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452381732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.1452381732 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke.1269832058 |
| Short name | T1478 |
| Test name | |
| Test status | |
| Simulation time | 44478078 ps |
| CPU time | 5.93 seconds |
| Started | May 30 03:50:15 PM PDT 24 |
| Finished | May 30 03:50:22 PM PDT 24 |
| Peak memory | 564856 kb |
| Host | smart-275f61a2-f301-42e8-b27e-374ca1b0e0d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269832058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.1269832058 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_large_delays.3238469891 |
| Short name | T2172 |
| Test name | |
| Test status | |
| Simulation time | 10434847193 ps |
| CPU time | 122.5 seconds |
| Started | May 30 03:50:13 PM PDT 24 |
| Finished | May 30 03:52:17 PM PDT 24 |
| Peak memory | 565000 kb |
| Host | smart-7671ae05-47bb-4438-9d91-d3bd05f1d9ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238469891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.3238469891 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.2896983332 |
| Short name | T2703 |
| Test name | |
| Test status | |
| Simulation time | 5327385590 ps |
| CPU time | 92.81 seconds |
| Started | May 30 03:50:14 PM PDT 24 |
| Finished | May 30 03:51:48 PM PDT 24 |
| Peak memory | 564968 kb |
| Host | smart-6870d90d-0b9b-4b06-97ed-81fe9ac0b3ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896983332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.2896983332 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.200268683 |
| Short name | T2215 |
| Test name | |
| Test status | |
| Simulation time | 55443577 ps |
| CPU time | 6.63 seconds |
| Started | May 30 03:50:20 PM PDT 24 |
| Finished | May 30 03:50:27 PM PDT 24 |
| Peak memory | 564796 kb |
| Host | smart-edea3fad-683d-42f7-8424-dc93de819b64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200268683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays .200268683 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all.1401268316 |
| Short name | T1618 |
| Test name | |
| Test status | |
| Simulation time | 1626252037 ps |
| CPU time | 123.2 seconds |
| Started | May 30 03:50:13 PM PDT 24 |
| Finished | May 30 03:52:18 PM PDT 24 |
| Peak memory | 573100 kb |
| Host | smart-0f1298a6-593f-40e4-94fe-104bec1fd72a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401268316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.1401268316 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.63371507 |
| Short name | T1964 |
| Test name | |
| Test status | |
| Simulation time | 1238220876 ps |
| CPU time | 88.61 seconds |
| Started | May 30 03:50:15 PM PDT 24 |
| Finished | May 30 03:51:45 PM PDT 24 |
| Peak memory | 575068 kb |
| Host | smart-884552d5-2603-471f-a143-c131d3fc60bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63371507 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.63371507 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.3676852586 |
| Short name | T2631 |
| Test name | |
| Test status | |
| Simulation time | 521710653 ps |
| CPU time | 242.58 seconds |
| Started | May 30 03:50:12 PM PDT 24 |
| Finished | May 30 03:54:16 PM PDT 24 |
| Peak memory | 576644 kb |
| Host | smart-4bf5bebf-6ef0-4f4a-be90-d73026e2049b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676852586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all _with_rand_reset.3676852586 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.2867114311 |
| Short name | T1362 |
| Test name | |
| Test status | |
| Simulation time | 157772776 ps |
| CPU time | 19.81 seconds |
| Started | May 30 03:50:13 PM PDT 24 |
| Finished | May 30 03:50:34 PM PDT 24 |
| Peak memory | 573044 kb |
| Host | smart-73e53daa-68b1-4de1-8fd2-7c267de8d000 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867114311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.2867114311 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device.2290264170 |
| Short name | T2578 |
| Test name | |
| Test status | |
| Simulation time | 1484708775 ps |
| CPU time | 74.98 seconds |
| Started | May 30 03:50:23 PM PDT 24 |
| Finished | May 30 03:51:39 PM PDT 24 |
| Peak memory | 573000 kb |
| Host | smart-b681eb19-a2b9-4acd-9693-c3ed2b679260 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290264170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device .2290264170 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.223770716 |
| Short name | T2114 |
| Test name | |
| Test status | |
| Simulation time | 139235744998 ps |
| CPU time | 2598.87 seconds |
| Started | May 30 03:50:23 PM PDT 24 |
| Finished | May 30 04:33:43 PM PDT 24 |
| Peak memory | 573332 kb |
| Host | smart-fcae2a29-7357-4204-8bb7-b5c07001fcce |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223770716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_d evice_slow_rsp.223770716 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.3485814353 |
| Short name | T2546 |
| Test name | |
| Test status | |
| Simulation time | 149783048 ps |
| CPU time | 17.25 seconds |
| Started | May 30 03:50:24 PM PDT 24 |
| Finished | May 30 03:50:43 PM PDT 24 |
| Peak memory | 572916 kb |
| Host | smart-333a57ad-aa5f-430a-a147-986881f80cdb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485814353 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_add r.3485814353 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_random.2579379211 |
| Short name | T2406 |
| Test name | |
| Test status | |
| Simulation time | 284398148 ps |
| CPU time | 25.53 seconds |
| Started | May 30 03:50:22 PM PDT 24 |
| Finished | May 30 03:50:49 PM PDT 24 |
| Peak memory | 573932 kb |
| Host | smart-e0130050-9def-4e35-9ed4-5c09edba52e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579379211 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.2579379211 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random.3700943749 |
| Short name | T2354 |
| Test name | |
| Test status | |
| Simulation time | 1925431342 ps |
| CPU time | 71.04 seconds |
| Started | May 30 03:50:20 PM PDT 24 |
| Finished | May 30 03:51:32 PM PDT 24 |
| Peak memory | 573056 kb |
| Host | smart-836edc84-77f9-461f-a7a6-cdb4ed3be594 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700943749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random.3700943749 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_large_delays.3972003467 |
| Short name | T2132 |
| Test name | |
| Test status | |
| Simulation time | 72984670568 ps |
| CPU time | 767.61 seconds |
| Started | May 30 03:50:25 PM PDT 24 |
| Finished | May 30 04:03:14 PM PDT 24 |
| Peak memory | 573192 kb |
| Host | smart-819427ad-a84d-4488-8db3-cbbb23259950 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972003467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.3972003467 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_slow_rsp.171929963 |
| Short name | T2459 |
| Test name | |
| Test status | |
| Simulation time | 57875892569 ps |
| CPU time | 1128.18 seconds |
| Started | May 30 03:50:21 PM PDT 24 |
| Finished | May 30 04:09:11 PM PDT 24 |
| Peak memory | 573164 kb |
| Host | smart-f4786188-e6bb-49fa-bb31-165e435955ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171929963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.171929963 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.98924948 |
| Short name | T2833 |
| Test name | |
| Test status | |
| Simulation time | 334261457 ps |
| CPU time | 29.54 seconds |
| Started | May 30 03:50:22 PM PDT 24 |
| Finished | May 30 03:50:53 PM PDT 24 |
| Peak memory | 573056 kb |
| Host | smart-2ce237e4-9511-4dfb-bdb2-8f925ab38427 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98924948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delay s.98924948 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_same_source.623447045 |
| Short name | T2453 |
| Test name | |
| Test status | |
| Simulation time | 335989279 ps |
| CPU time | 27.96 seconds |
| Started | May 30 03:50:21 PM PDT 24 |
| Finished | May 30 03:50:50 PM PDT 24 |
| Peak memory | 572948 kb |
| Host | smart-ddb1c9f1-0f8b-4afa-82df-89cf92d69c5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623447045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.623447045 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke.2114254802 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 40039618 ps |
| CPU time | 5.92 seconds |
| Started | May 30 03:50:11 PM PDT 24 |
| Finished | May 30 03:50:18 PM PDT 24 |
| Peak memory | 563340 kb |
| Host | smart-9855f3a2-12a5-46f5-ad61-dec1a900ad88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114254802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.2114254802 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_large_delays.3918576257 |
| Short name | T2554 |
| Test name | |
| Test status | |
| Simulation time | 9718111936 ps |
| CPU time | 96.45 seconds |
| Started | May 30 03:50:14 PM PDT 24 |
| Finished | May 30 03:51:51 PM PDT 24 |
| Peak memory | 565016 kb |
| Host | smart-2bb19f9d-77f2-45da-8f99-6fcbcac4884c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918576257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.3918576257 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.3397374936 |
| Short name | T2351 |
| Test name | |
| Test status | |
| Simulation time | 4686539356 ps |
| CPU time | 82.67 seconds |
| Started | May 30 03:50:22 PM PDT 24 |
| Finished | May 30 03:51:47 PM PDT 24 |
| Peak memory | 564948 kb |
| Host | smart-bc88ca86-9c23-4f3d-a9d5-be6e7ed4855a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397374936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.3397374936 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_zero_delays.4135407221 |
| Short name | T2064 |
| Test name | |
| Test status | |
| Simulation time | 42583737 ps |
| CPU time | 6.35 seconds |
| Started | May 30 03:50:12 PM PDT 24 |
| Finished | May 30 03:50:19 PM PDT 24 |
| Peak memory | 563364 kb |
| Host | smart-ab481c55-7cfe-4f29-9344-bf151caa4b27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135407221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delay s.4135407221 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all.2596126194 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 4006791866 ps |
| CPU time | 338.68 seconds |
| Started | May 30 03:50:20 PM PDT 24 |
| Finished | May 30 03:56:00 PM PDT 24 |
| Peak memory | 573112 kb |
| Host | smart-8ef23d76-4749-4e66-88a9-96f68dd84c65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596126194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.2596126194 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.2377065678 |
| Short name | T1938 |
| Test name | |
| Test status | |
| Simulation time | 3811523746 ps |
| CPU time | 279.88 seconds |
| Started | May 30 03:50:21 PM PDT 24 |
| Finished | May 30 03:55:02 PM PDT 24 |
| Peak memory | 573092 kb |
| Host | smart-2058e636-f020-4edb-81c9-7f02afcceaa0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377065678 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.2377065678 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.2416461498 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 1880486905 ps |
| CPU time | 232.75 seconds |
| Started | May 30 03:50:24 PM PDT 24 |
| Finished | May 30 03:54:18 PM PDT 24 |
| Peak memory | 573160 kb |
| Host | smart-ebb29f53-3e30-4991-8bce-f9f399995f01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416461498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all _with_rand_reset.2416461498 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.3865022118 |
| Short name | T2517 |
| Test name | |
| Test status | |
| Simulation time | 488305292 ps |
| CPU time | 197.5 seconds |
| Started | May 30 03:50:24 PM PDT 24 |
| Finished | May 30 03:53:43 PM PDT 24 |
| Peak memory | 573064 kb |
| Host | smart-c655bfbf-b7cc-4e63-938f-2b3ebe2ec572 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865022118 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_al l_with_reset_error.3865022118 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_unmapped_addr.3454265476 |
| Short name | T2019 |
| Test name | |
| Test status | |
| Simulation time | 1308457666 ps |
| CPU time | 54.15 seconds |
| Started | May 30 03:50:22 PM PDT 24 |
| Finished | May 30 03:51:17 PM PDT 24 |
| Peak memory | 573020 kb |
| Host | smart-e94c69c8-d1f5-4669-8011-13131a2d91ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454265476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.3454265476 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.chip_tl_errors.4194547944 |
| Short name | T2558 |
| Test name | |
| Test status | |
| Simulation time | 3887004488 ps |
| CPU time | 281.67 seconds |
| Started | May 30 03:50:20 PM PDT 24 |
| Finished | May 30 03:55:03 PM PDT 24 |
| Peak memory | 593928 kb |
| Host | smart-3ebcb6ee-b994-49c0-95e0-a04e9223d9d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194547944 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.chip_tl_errors.4194547944 |
| Directory | /workspace/23.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device.585188661 |
| Short name | T1620 |
| Test name | |
| Test status | |
| Simulation time | 817466698 ps |
| CPU time | 62.02 seconds |
| Started | May 30 03:50:25 PM PDT 24 |
| Finished | May 30 03:51:29 PM PDT 24 |
| Peak memory | 573012 kb |
| Host | smart-8ff504df-e9da-481f-bd08-d4e03331546a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585188661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device. 585188661 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.2579607910 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 69164384795 ps |
| CPU time | 1054.26 seconds |
| Started | May 30 03:50:20 PM PDT 24 |
| Finished | May 30 04:07:55 PM PDT 24 |
| Peak memory | 573276 kb |
| Host | smart-495925fc-c4f2-4542-ab6f-dd9ddffce2ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579607910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_ device_slow_rsp.2579607910 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.3939844186 |
| Short name | T1906 |
| Test name | |
| Test status | |
| Simulation time | 297928661 ps |
| CPU time | 32.78 seconds |
| Started | May 30 03:50:31 PM PDT 24 |
| Finished | May 30 03:51:06 PM PDT 24 |
| Peak memory | 573944 kb |
| Host | smart-637d2f1d-d90c-4c2f-9c22-4cb783e6f1e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939844186 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_add r.3939844186 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_random.1948041468 |
| Short name | T2363 |
| Test name | |
| Test status | |
| Simulation time | 188168425 ps |
| CPU time | 16.79 seconds |
| Started | May 30 03:50:30 PM PDT 24 |
| Finished | May 30 03:50:48 PM PDT 24 |
| Peak memory | 572912 kb |
| Host | smart-6acd8114-5c85-46b3-a04e-3233c30b9ca3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948041468 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.1948041468 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random.258910651 |
| Short name | T1528 |
| Test name | |
| Test status | |
| Simulation time | 380223326 ps |
| CPU time | 35.73 seconds |
| Started | May 30 03:50:20 PM PDT 24 |
| Finished | May 30 03:50:57 PM PDT 24 |
| Peak memory | 573056 kb |
| Host | smart-a4993e3f-d2c3-422f-83c4-b2a817bc26db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258910651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random.258910651 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_large_delays.4023879580 |
| Short name | T2023 |
| Test name | |
| Test status | |
| Simulation time | 61929224259 ps |
| CPU time | 623.65 seconds |
| Started | May 30 03:50:25 PM PDT 24 |
| Finished | May 30 04:00:50 PM PDT 24 |
| Peak memory | 573164 kb |
| Host | smart-17f67586-91a6-40f0-acd0-17e45347ba68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023879580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.4023879580 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.2149782810 |
| Short name | T1993 |
| Test name | |
| Test status | |
| Simulation time | 68086250064 ps |
| CPU time | 1277.76 seconds |
| Started | May 30 03:50:18 PM PDT 24 |
| Finished | May 30 04:11:38 PM PDT 24 |
| Peak memory | 573128 kb |
| Host | smart-e302268e-1f06-4e11-842c-16e171950f77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149782810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.2149782810 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_zero_delays.4019716139 |
| Short name | T1754 |
| Test name | |
| Test status | |
| Simulation time | 141181227 ps |
| CPU time | 17.28 seconds |
| Started | May 30 03:50:24 PM PDT 24 |
| Finished | May 30 03:50:43 PM PDT 24 |
| Peak memory | 573012 kb |
| Host | smart-e4f35460-d7e6-4936-86e8-a38e329e65eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019716139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_del ays.4019716139 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_same_source.3701645771 |
| Short name | T2717 |
| Test name | |
| Test status | |
| Simulation time | 675069127 ps |
| CPU time | 22.12 seconds |
| Started | May 30 03:50:20 PM PDT 24 |
| Finished | May 30 03:50:44 PM PDT 24 |
| Peak memory | 573036 kb |
| Host | smart-9b5efe2b-7f18-4ffa-a0b6-99987afd4bc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701645771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.3701645771 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke.585927891 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 43058285 ps |
| CPU time | 6.12 seconds |
| Started | May 30 03:50:21 PM PDT 24 |
| Finished | May 30 03:50:28 PM PDT 24 |
| Peak memory | 564816 kb |
| Host | smart-6e199df3-98db-40e3-b407-66c8e1c7c97b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585927891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.585927891 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_large_delays.976657390 |
| Short name | T2438 |
| Test name | |
| Test status | |
| Simulation time | 7470907597 ps |
| CPU time | 78.04 seconds |
| Started | May 30 03:50:25 PM PDT 24 |
| Finished | May 30 03:51:44 PM PDT 24 |
| Peak memory | 564932 kb |
| Host | smart-25932d6b-4573-4189-8d10-f293f3d76459 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976657390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.976657390 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.2137909738 |
| Short name | T2822 |
| Test name | |
| Test status | |
| Simulation time | 5598581933 ps |
| CPU time | 87.77 seconds |
| Started | May 30 03:50:25 PM PDT 24 |
| Finished | May 30 03:51:55 PM PDT 24 |
| Peak memory | 563516 kb |
| Host | smart-c327147c-b423-4a44-abd5-012f7588a2e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137909738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.2137909738 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_zero_delays.2492128497 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 42211643 ps |
| CPU time | 6.32 seconds |
| Started | May 30 03:50:23 PM PDT 24 |
| Finished | May 30 03:50:31 PM PDT 24 |
| Peak memory | 564736 kb |
| Host | smart-ba1e3cb1-5ced-4909-b0ed-86cbec2b8c8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492128497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delay s.2492128497 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all.325342330 |
| Short name | T2496 |
| Test name | |
| Test status | |
| Simulation time | 13350120467 ps |
| CPU time | 464.4 seconds |
| Started | May 30 03:50:34 PM PDT 24 |
| Finished | May 30 03:58:19 PM PDT 24 |
| Peak memory | 573248 kb |
| Host | smart-fdf53040-6022-405c-a720-2df0c68840a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325342330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.325342330 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.2945158223 |
| Short name | T2705 |
| Test name | |
| Test status | |
| Simulation time | 3671882462 ps |
| CPU time | 142.33 seconds |
| Started | May 30 03:50:33 PM PDT 24 |
| Finished | May 30 03:52:57 PM PDT 24 |
| Peak memory | 573008 kb |
| Host | smart-3f7af684-ef1b-470f-a47e-f024fe33eae8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945158223 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.2945158223 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.3827826885 |
| Short name | T2867 |
| Test name | |
| Test status | |
| Simulation time | 6814367819 ps |
| CPU time | 390.71 seconds |
| Started | May 30 03:50:31 PM PDT 24 |
| Finished | May 30 03:57:03 PM PDT 24 |
| Peak memory | 573272 kb |
| Host | smart-c23aa6f7-dd97-4045-ad5b-91061f1ef19f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827826885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all _with_rand_reset.3827826885 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.2046560756 |
| Short name | T1628 |
| Test name | |
| Test status | |
| Simulation time | 3863755635 ps |
| CPU time | 398.92 seconds |
| Started | May 30 03:50:31 PM PDT 24 |
| Finished | May 30 03:57:12 PM PDT 24 |
| Peak memory | 573184 kb |
| Host | smart-917969aa-01c3-459f-acbb-4391db7389d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046560756 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_al l_with_reset_error.2046560756 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.1341159332 |
| Short name | T2164 |
| Test name | |
| Test status | |
| Simulation time | 548137734 ps |
| CPU time | 23.74 seconds |
| Started | May 30 03:50:29 PM PDT 24 |
| Finished | May 30 03:50:54 PM PDT 24 |
| Peak memory | 573104 kb |
| Host | smart-08dae282-c5ab-4cd6-bccd-cb612184a229 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341159332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.1341159332 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device.568180693 |
| Short name | T2718 |
| Test name | |
| Test status | |
| Simulation time | 1725321185 ps |
| CPU time | 65.06 seconds |
| Started | May 30 03:50:29 PM PDT 24 |
| Finished | May 30 03:51:36 PM PDT 24 |
| Peak memory | 573096 kb |
| Host | smart-2c190af9-76b5-4574-ad79-8cde3a5f5abf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568180693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device. 568180693 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.2438253333 |
| Short name | T1689 |
| Test name | |
| Test status | |
| Simulation time | 34420875744 ps |
| CPU time | 568.94 seconds |
| Started | May 30 03:50:32 PM PDT 24 |
| Finished | May 30 04:00:03 PM PDT 24 |
| Peak memory | 573204 kb |
| Host | smart-4523e312-2dc3-477a-bbef-e1815af51f57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438253333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_ device_slow_rsp.2438253333 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.3459032787 |
| Short name | T1472 |
| Test name | |
| Test status | |
| Simulation time | 991199898 ps |
| CPU time | 39 seconds |
| Started | May 30 03:50:34 PM PDT 24 |
| Finished | May 30 03:51:14 PM PDT 24 |
| Peak memory | 573988 kb |
| Host | smart-fa8b4057-d4a9-47ff-8135-c6b51ca03c81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459032787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_add r.3459032787 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_random.490762621 |
| Short name | T2556 |
| Test name | |
| Test status | |
| Simulation time | 369216895 ps |
| CPU time | 17.14 seconds |
| Started | May 30 03:50:31 PM PDT 24 |
| Finished | May 30 03:50:50 PM PDT 24 |
| Peak memory | 572776 kb |
| Host | smart-189f8e48-34d0-4538-a612-51689fa79393 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490762621 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.490762621 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random.3783417964 |
| Short name | T2099 |
| Test name | |
| Test status | |
| Simulation time | 373681031 ps |
| CPU time | 35.19 seconds |
| Started | May 30 03:50:34 PM PDT 24 |
| Finished | May 30 03:51:10 PM PDT 24 |
| Peak memory | 572976 kb |
| Host | smart-e5e3e0eb-ae71-4901-b973-b7e74db1eaef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783417964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random.3783417964 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.443469591 |
| Short name | T1554 |
| Test name | |
| Test status | |
| Simulation time | 113236771403 ps |
| CPU time | 1141.44 seconds |
| Started | May 30 03:50:31 PM PDT 24 |
| Finished | May 30 04:09:34 PM PDT 24 |
| Peak memory | 573156 kb |
| Host | smart-bf654bd3-2708-4108-8f94-3fca9aa46d06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443469591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.443469591 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_slow_rsp.1103024057 |
| Short name | T2062 |
| Test name | |
| Test status | |
| Simulation time | 12961588582 ps |
| CPU time | 234.61 seconds |
| Started | May 30 03:50:30 PM PDT 24 |
| Finished | May 30 03:54:26 PM PDT 24 |
| Peak memory | 573124 kb |
| Host | smart-e9c483fe-8398-4747-869a-7252f73b457a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103024057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.1103024057 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_zero_delays.169634394 |
| Short name | T1810 |
| Test name | |
| Test status | |
| Simulation time | 304467377 ps |
| CPU time | 30.56 seconds |
| Started | May 30 03:50:30 PM PDT 24 |
| Finished | May 30 03:51:02 PM PDT 24 |
| Peak memory | 573056 kb |
| Host | smart-3d5123ad-57c2-491a-8c04-028d4c62c136 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169634394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_dela ys.169634394 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_same_source.2536935831 |
| Short name | T1463 |
| Test name | |
| Test status | |
| Simulation time | 996808304 ps |
| CPU time | 33.61 seconds |
| Started | May 30 03:50:31 PM PDT 24 |
| Finished | May 30 03:51:06 PM PDT 24 |
| Peak memory | 573064 kb |
| Host | smart-ec63e3c4-ee36-469b-9386-6faceb315a37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536935831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.2536935831 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke.1096616499 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 45319645 ps |
| CPU time | 6.12 seconds |
| Started | May 30 03:50:32 PM PDT 24 |
| Finished | May 30 03:50:39 PM PDT 24 |
| Peak memory | 563400 kb |
| Host | smart-681e5793-040a-48ce-9a5d-86c21e4fefc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096616499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.1096616499 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.2946766200 |
| Short name | T2608 |
| Test name | |
| Test status | |
| Simulation time | 7444106076 ps |
| CPU time | 79.42 seconds |
| Started | May 30 03:50:32 PM PDT 24 |
| Finished | May 30 03:51:53 PM PDT 24 |
| Peak memory | 564928 kb |
| Host | smart-f9b38e35-d722-4d1b-91d3-86fc6947c482 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946766200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.2946766200 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.1784004944 |
| Short name | T2751 |
| Test name | |
| Test status | |
| Simulation time | 5344546159 ps |
| CPU time | 94.5 seconds |
| Started | May 30 03:50:34 PM PDT 24 |
| Finished | May 30 03:52:10 PM PDT 24 |
| Peak memory | 563476 kb |
| Host | smart-566714b8-1d5c-453a-ba10-6231a5676e38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784004944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.1784004944 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_zero_delays.2320391349 |
| Short name | T1863 |
| Test name | |
| Test status | |
| Simulation time | 49481054 ps |
| CPU time | 6.06 seconds |
| Started | May 30 03:50:32 PM PDT 24 |
| Finished | May 30 03:50:39 PM PDT 24 |
| Peak memory | 564756 kb |
| Host | smart-9d15be5f-86a8-4469-9f52-a35968a584fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320391349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delay s.2320391349 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all.4071448420 |
| Short name | T1773 |
| Test name | |
| Test status | |
| Simulation time | 7885030381 ps |
| CPU time | 298.83 seconds |
| Started | May 30 03:50:34 PM PDT 24 |
| Finished | May 30 03:55:34 PM PDT 24 |
| Peak memory | 573304 kb |
| Host | smart-9ff3c2a3-f46c-4da8-9875-08aabe446e42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071448420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.4071448420 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.2171472536 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 3027460141 ps |
| CPU time | 205.82 seconds |
| Started | May 30 03:50:39 PM PDT 24 |
| Finished | May 30 03:54:06 PM PDT 24 |
| Peak memory | 573204 kb |
| Host | smart-3cf929f9-f087-4513-bdae-7a3acf5c50e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171472536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all _with_rand_reset.2171472536 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.1780595155 |
| Short name | T1384 |
| Test name | |
| Test status | |
| Simulation time | 77435980 ps |
| CPU time | 29.54 seconds |
| Started | May 30 03:50:39 PM PDT 24 |
| Finished | May 30 03:51:10 PM PDT 24 |
| Peak memory | 573100 kb |
| Host | smart-61251250-0d9e-4fe5-9f73-a7767d4dfd3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780595155 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_al l_with_reset_error.1780595155 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_unmapped_addr.343910911 |
| Short name | T2070 |
| Test name | |
| Test status | |
| Simulation time | 695012908 ps |
| CPU time | 34.68 seconds |
| Started | May 30 03:50:32 PM PDT 24 |
| Finished | May 30 03:51:08 PM PDT 24 |
| Peak memory | 573056 kb |
| Host | smart-a67f5369-19ce-4283-8c9b-fee4fdfc27cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343910911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.343910911 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.chip_tl_errors.471480104 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 3463579128 ps |
| CPU time | 268.25 seconds |
| Started | May 30 03:50:41 PM PDT 24 |
| Finished | May 30 03:55:10 PM PDT 24 |
| Peak memory | 594056 kb |
| Host | smart-3e5385a3-86bf-4198-888a-a1633ab077e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471480104 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.chip_tl_errors.471480104 |
| Directory | /workspace/25.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device.2733530674 |
| Short name | T2120 |
| Test name | |
| Test status | |
| Simulation time | 339957095 ps |
| CPU time | 26.19 seconds |
| Started | May 30 03:50:43 PM PDT 24 |
| Finished | May 30 03:51:10 PM PDT 24 |
| Peak memory | 573056 kb |
| Host | smart-119c3339-81e5-4cc5-b18b-d327268ca917 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733530674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device .2733530674 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.660987760 |
| Short name | T1783 |
| Test name | |
| Test status | |
| Simulation time | 75035397102 ps |
| CPU time | 1173.55 seconds |
| Started | May 30 03:50:50 PM PDT 24 |
| Finished | May 30 04:10:25 PM PDT 24 |
| Peak memory | 573212 kb |
| Host | smart-613c0977-28d0-4b86-9cfa-60fb37afa671 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660987760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_d evice_slow_rsp.660987760 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.4101858494 |
| Short name | T1445 |
| Test name | |
| Test status | |
| Simulation time | 118017948 ps |
| CPU time | 14.43 seconds |
| Started | May 30 03:50:39 PM PDT 24 |
| Finished | May 30 03:50:55 PM PDT 24 |
| Peak memory | 572912 kb |
| Host | smart-0d401c9f-4f10-4ee5-a166-079e037cbaf3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101858494 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_add r.4101858494 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_random.4069994338 |
| Short name | T2178 |
| Test name | |
| Test status | |
| Simulation time | 696084424 ps |
| CPU time | 24.94 seconds |
| Started | May 30 03:50:40 PM PDT 24 |
| Finished | May 30 03:51:06 PM PDT 24 |
| Peak memory | 573932 kb |
| Host | smart-5cc37acb-8b89-48f5-8529-0bb7bea1616e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069994338 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.4069994338 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random.408962610 |
| Short name | T2188 |
| Test name | |
| Test status | |
| Simulation time | 562903195 ps |
| CPU time | 54.89 seconds |
| Started | May 30 03:50:39 PM PDT 24 |
| Finished | May 30 03:51:35 PM PDT 24 |
| Peak memory | 573096 kb |
| Host | smart-7aff4823-40db-4272-81bc-5394fd57cb11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408962610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random.408962610 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_large_delays.46625069 |
| Short name | T2231 |
| Test name | |
| Test status | |
| Simulation time | 77548148484 ps |
| CPU time | 874.22 seconds |
| Started | May 30 03:50:44 PM PDT 24 |
| Finished | May 30 04:05:19 PM PDT 24 |
| Peak memory | 573144 kb |
| Host | smart-602a7924-c87e-4681-9e3f-ac6a4fbff8be |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46625069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.46625069 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_slow_rsp.466231495 |
| Short name | T2675 |
| Test name | |
| Test status | |
| Simulation time | 70660672371 ps |
| CPU time | 1302.09 seconds |
| Started | May 30 03:50:43 PM PDT 24 |
| Finished | May 30 04:12:26 PM PDT 24 |
| Peak memory | 573188 kb |
| Host | smart-19d18d38-1691-4fba-ba0c-2ce84307480b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466231495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.466231495 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_zero_delays.545849712 |
| Short name | T2863 |
| Test name | |
| Test status | |
| Simulation time | 210866984 ps |
| CPU time | 22.56 seconds |
| Started | May 30 03:50:42 PM PDT 24 |
| Finished | May 30 03:51:05 PM PDT 24 |
| Peak memory | 572992 kb |
| Host | smart-dfebb92a-a28e-45b0-8ca9-02bfb00531c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545849712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_dela ys.545849712 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_same_source.3469912715 |
| Short name | T2640 |
| Test name | |
| Test status | |
| Simulation time | 133507509 ps |
| CPU time | 11.9 seconds |
| Started | May 30 03:50:41 PM PDT 24 |
| Finished | May 30 03:50:54 PM PDT 24 |
| Peak memory | 573072 kb |
| Host | smart-5034862b-b8f8-4ee6-acaa-cad25115b723 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469912715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.3469912715 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke.1330448836 |
| Short name | T2691 |
| Test name | |
| Test status | |
| Simulation time | 43518342 ps |
| CPU time | 6.16 seconds |
| Started | May 30 03:50:43 PM PDT 24 |
| Finished | May 30 03:50:50 PM PDT 24 |
| Peak memory | 564824 kb |
| Host | smart-198d9a8b-9fd2-4037-8281-5a096a96892d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330448836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.1330448836 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_large_delays.1478147332 |
| Short name | T1471 |
| Test name | |
| Test status | |
| Simulation time | 9447064197 ps |
| CPU time | 94.64 seconds |
| Started | May 30 03:50:39 PM PDT 24 |
| Finished | May 30 03:52:15 PM PDT 24 |
| Peak memory | 564988 kb |
| Host | smart-92aed669-2167-4ef4-996b-329fecc94267 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478147332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.1478147332 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.376562861 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 5410128549 ps |
| CPU time | 91.44 seconds |
| Started | May 30 03:50:40 PM PDT 24 |
| Finished | May 30 03:52:12 PM PDT 24 |
| Peak memory | 564976 kb |
| Host | smart-14b84b2a-5ee0-468a-9366-dae87faa7c02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376562861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.376562861 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_zero_delays.189848613 |
| Short name | T1480 |
| Test name | |
| Test status | |
| Simulation time | 59972120 ps |
| CPU time | 7.27 seconds |
| Started | May 30 03:50:43 PM PDT 24 |
| Finished | May 30 03:50:52 PM PDT 24 |
| Peak memory | 564720 kb |
| Host | smart-374926eb-6515-43dc-9f24-1a3a16a2d549 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189848613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays .189848613 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all.2690998963 |
| Short name | T2167 |
| Test name | |
| Test status | |
| Simulation time | 11038275202 ps |
| CPU time | 468.99 seconds |
| Started | May 30 03:50:40 PM PDT 24 |
| Finished | May 30 03:58:30 PM PDT 24 |
| Peak memory | 573172 kb |
| Host | smart-5990179b-8f02-48ad-82b3-65b66b952f6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690998963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.2690998963 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.2509198030 |
| Short name | T1743 |
| Test name | |
| Test status | |
| Simulation time | 11732037638 ps |
| CPU time | 437.19 seconds |
| Started | May 30 03:50:42 PM PDT 24 |
| Finished | May 30 03:58:00 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-8ab57fbc-d36a-4e12-aadf-398ab10d1179 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509198030 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.2509198030 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.779187338 |
| Short name | T1760 |
| Test name | |
| Test status | |
| Simulation time | 2072924598 ps |
| CPU time | 277.51 seconds |
| Started | May 30 03:50:43 PM PDT 24 |
| Finished | May 30 03:55:22 PM PDT 24 |
| Peak memory | 573076 kb |
| Host | smart-a98fbe6c-650b-4c51-8bcc-de6ac1a15ae3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779187338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_ with_rand_reset.779187338 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_unmapped_addr.2812120089 |
| Short name | T2067 |
| Test name | |
| Test status | |
| Simulation time | 271447019 ps |
| CPU time | 32.25 seconds |
| Started | May 30 03:50:40 PM PDT 24 |
| Finished | May 30 03:51:13 PM PDT 24 |
| Peak memory | 572980 kb |
| Host | smart-a9433be7-cf74-48ed-b193-4f543d9dd79b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812120089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.2812120089 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.chip_tl_errors.748129093 |
| Short name | T2619 |
| Test name | |
| Test status | |
| Simulation time | 4089239960 ps |
| CPU time | 273.25 seconds |
| Started | May 30 03:50:40 PM PDT 24 |
| Finished | May 30 03:55:14 PM PDT 24 |
| Peak memory | 594028 kb |
| Host | smart-6b802c00-0703-443b-9546-11272c19a0c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748129093 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.chip_tl_errors.748129093 |
| Directory | /workspace/26.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device.3854050976 |
| Short name | T1708 |
| Test name | |
| Test status | |
| Simulation time | 2700486966 ps |
| CPU time | 114.17 seconds |
| Started | May 30 03:50:40 PM PDT 24 |
| Finished | May 30 03:52:35 PM PDT 24 |
| Peak memory | 573100 kb |
| Host | smart-977d872a-bdb0-4411-abda-6f9e9752ee4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854050976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device .3854050976 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.3067514306 |
| Short name | T2109 |
| Test name | |
| Test status | |
| Simulation time | 42137413368 ps |
| CPU time | 721.79 seconds |
| Started | May 30 03:50:52 PM PDT 24 |
| Finished | May 30 04:02:55 PM PDT 24 |
| Peak memory | 573240 kb |
| Host | smart-cb80947d-c557-47d5-aa8b-24264fc0bee0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067514306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_ device_slow_rsp.3067514306 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.1882172369 |
| Short name | T1864 |
| Test name | |
| Test status | |
| Simulation time | 273634387 ps |
| CPU time | 13.7 seconds |
| Started | May 30 03:50:51 PM PDT 24 |
| Finished | May 30 03:51:06 PM PDT 24 |
| Peak memory | 573964 kb |
| Host | smart-b20ff629-c0df-431e-8eca-de6c7976185e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882172369 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_add r.1882172369 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_random.2310721726 |
| Short name | T2054 |
| Test name | |
| Test status | |
| Simulation time | 135560395 ps |
| CPU time | 12.82 seconds |
| Started | May 30 03:51:03 PM PDT 24 |
| Finished | May 30 03:51:18 PM PDT 24 |
| Peak memory | 572924 kb |
| Host | smart-9c44c6c5-e03c-48dd-ba15-ebc6c889d9e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310721726 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.2310721726 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random.3716139512 |
| Short name | T2711 |
| Test name | |
| Test status | |
| Simulation time | 1727062250 ps |
| CPU time | 54.16 seconds |
| Started | May 30 03:50:50 PM PDT 24 |
| Finished | May 30 03:51:46 PM PDT 24 |
| Peak memory | 573096 kb |
| Host | smart-34725c92-5970-42d8-a2b6-7c6b56960e6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716139512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random.3716139512 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_large_delays.4012068229 |
| Short name | T1766 |
| Test name | |
| Test status | |
| Simulation time | 11976379367 ps |
| CPU time | 121.28 seconds |
| Started | May 30 03:50:50 PM PDT 24 |
| Finished | May 30 03:52:52 PM PDT 24 |
| Peak memory | 564952 kb |
| Host | smart-91de4c36-79bc-42c8-a106-7253ee6d240f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012068229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.4012068229 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_slow_rsp.1008074626 |
| Short name | T2434 |
| Test name | |
| Test status | |
| Simulation time | 8534566748 ps |
| CPU time | 150.9 seconds |
| Started | May 30 03:50:42 PM PDT 24 |
| Finished | May 30 03:53:13 PM PDT 24 |
| Peak memory | 573188 kb |
| Host | smart-9f809fe9-14cb-4521-917c-96c7817f1617 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008074626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.1008074626 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.1369479055 |
| Short name | T1816 |
| Test name | |
| Test status | |
| Simulation time | 423751882 ps |
| CPU time | 32.1 seconds |
| Started | May 30 03:50:43 PM PDT 24 |
| Finished | May 30 03:51:15 PM PDT 24 |
| Peak memory | 573028 kb |
| Host | smart-c1de8e01-6cd2-4b98-870e-9837db6f98aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369479055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_del ays.1369479055 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_same_source.2510530892 |
| Short name | T2000 |
| Test name | |
| Test status | |
| Simulation time | 2493192811 ps |
| CPU time | 75.73 seconds |
| Started | May 30 03:50:52 PM PDT 24 |
| Finished | May 30 03:52:08 PM PDT 24 |
| Peak memory | 572948 kb |
| Host | smart-02634411-5422-41c3-9104-d2f6bcd2d19e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510530892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.2510530892 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke.1476284842 |
| Short name | T2460 |
| Test name | |
| Test status | |
| Simulation time | 217126138 ps |
| CPU time | 10.25 seconds |
| Started | May 30 03:50:44 PM PDT 24 |
| Finished | May 30 03:50:55 PM PDT 24 |
| Peak memory | 564860 kb |
| Host | smart-0644816d-cd75-443b-952a-d92eef4d15da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476284842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.1476284842 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_large_delays.2888947987 |
| Short name | T1507 |
| Test name | |
| Test status | |
| Simulation time | 8958229570 ps |
| CPU time | 91.67 seconds |
| Started | May 30 03:50:43 PM PDT 24 |
| Finished | May 30 03:52:15 PM PDT 24 |
| Peak memory | 564928 kb |
| Host | smart-8d234d0c-d9fd-4509-bcc6-20d3d0178570 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888947987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.2888947987 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.2746948880 |
| Short name | T2509 |
| Test name | |
| Test status | |
| Simulation time | 5701815999 ps |
| CPU time | 96.84 seconds |
| Started | May 30 03:50:51 PM PDT 24 |
| Finished | May 30 03:52:29 PM PDT 24 |
| Peak memory | 564988 kb |
| Host | smart-46092a46-0de2-46b8-b528-62fc7639d92d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746948880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.2746948880 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.2462632672 |
| Short name | T2180 |
| Test name | |
| Test status | |
| Simulation time | 47401010 ps |
| CPU time | 6.52 seconds |
| Started | May 30 03:50:41 PM PDT 24 |
| Finished | May 30 03:50:48 PM PDT 24 |
| Peak memory | 564804 kb |
| Host | smart-ce005f99-a4f2-4a2a-b89b-1299611addd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462632672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delay s.2462632672 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all.3107555959 |
| Short name | T2727 |
| Test name | |
| Test status | |
| Simulation time | 8384827970 ps |
| CPU time | 276.95 seconds |
| Started | May 30 03:50:50 PM PDT 24 |
| Finished | May 30 03:55:27 PM PDT 24 |
| Peak memory | 573228 kb |
| Host | smart-a9d8efbc-627d-47eb-aaf0-c44990d0fb8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107555959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.3107555959 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.2099357859 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 15121400730 ps |
| CPU time | 494.36 seconds |
| Started | May 30 03:50:50 PM PDT 24 |
| Finished | May 30 03:59:06 PM PDT 24 |
| Peak memory | 573108 kb |
| Host | smart-eee7c1c9-b58f-4827-bfef-6f2d719cfbc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099357859 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.2099357859 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.2311980905 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 2128770330 ps |
| CPU time | 303.08 seconds |
| Started | May 30 03:51:02 PM PDT 24 |
| Finished | May 30 03:56:06 PM PDT 24 |
| Peak memory | 573152 kb |
| Host | smart-1a32f83c-c8c9-4af1-8be0-a74cce07b465 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311980905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all _with_rand_reset.2311980905 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_unmapped_addr.3280441125 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 1361377671 ps |
| CPU time | 60.24 seconds |
| Started | May 30 03:50:51 PM PDT 24 |
| Finished | May 30 03:51:52 PM PDT 24 |
| Peak memory | 572960 kb |
| Host | smart-318e08a6-a880-4455-8cc7-394c9b5f1659 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280441125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.3280441125 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device.78381338 |
| Short name | T2593 |
| Test name | |
| Test status | |
| Simulation time | 1951019991 ps |
| CPU time | 75.41 seconds |
| Started | May 30 03:50:50 PM PDT 24 |
| Finished | May 30 03:52:06 PM PDT 24 |
| Peak memory | 573052 kb |
| Host | smart-02184da2-d3f4-4515-9e7d-82338bc5490a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78381338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.78381338 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.1334819113 |
| Short name | T2678 |
| Test name | |
| Test status | |
| Simulation time | 104165450423 ps |
| CPU time | 2006.98 seconds |
| Started | May 30 03:50:52 PM PDT 24 |
| Finished | May 30 04:24:20 PM PDT 24 |
| Peak memory | 573312 kb |
| Host | smart-a1b7d51d-0e96-4206-b2c3-63554fc07b9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334819113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_ device_slow_rsp.1334819113 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.2388762297 |
| Short name | T2704 |
| Test name | |
| Test status | |
| Simulation time | 305427650 ps |
| CPU time | 35.88 seconds |
| Started | May 30 03:50:52 PM PDT 24 |
| Finished | May 30 03:51:29 PM PDT 24 |
| Peak memory | 573980 kb |
| Host | smart-6f09dec4-f241-4693-9388-c7f8604cb04f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388762297 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_add r.2388762297 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_random.2561770946 |
| Short name | T2419 |
| Test name | |
| Test status | |
| Simulation time | 239420978 ps |
| CPU time | 19.15 seconds |
| Started | May 30 03:51:04 PM PDT 24 |
| Finished | May 30 03:51:24 PM PDT 24 |
| Peak memory | 572912 kb |
| Host | smart-ca069a54-5ab2-4501-984a-8bb8e72fc156 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561770946 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.2561770946 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random.1839885486 |
| Short name | T2032 |
| Test name | |
| Test status | |
| Simulation time | 352995087 ps |
| CPU time | 35.55 seconds |
| Started | May 30 03:50:51 PM PDT 24 |
| Finished | May 30 03:51:27 PM PDT 24 |
| Peak memory | 573056 kb |
| Host | smart-e0e43a6c-a7de-48b2-933d-24bf18546eda |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839885486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random.1839885486 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_large_delays.254326753 |
| Short name | T2637 |
| Test name | |
| Test status | |
| Simulation time | 110065036237 ps |
| CPU time | 1154.24 seconds |
| Started | May 30 03:50:55 PM PDT 24 |
| Finished | May 30 04:10:11 PM PDT 24 |
| Peak memory | 573120 kb |
| Host | smart-82bcd7fb-84e2-4c8e-a9fd-8a8f1abb096e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254326753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.254326753 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.410335266 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 50689143887 ps |
| CPU time | 915.26 seconds |
| Started | May 30 03:50:50 PM PDT 24 |
| Finished | May 30 04:06:07 PM PDT 24 |
| Peak memory | 573176 kb |
| Host | smart-5b9ac734-5942-42d8-b764-d4ec32afe0b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410335266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.410335266 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_zero_delays.1278874213 |
| Short name | T2715 |
| Test name | |
| Test status | |
| Simulation time | 423018643 ps |
| CPU time | 32.78 seconds |
| Started | May 30 03:50:50 PM PDT 24 |
| Finished | May 30 03:51:24 PM PDT 24 |
| Peak memory | 572940 kb |
| Host | smart-650952ec-9552-44db-b921-c5def3ef008a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278874213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_del ays.1278874213 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_same_source.2423892744 |
| Short name | T1985 |
| Test name | |
| Test status | |
| Simulation time | 494968130 ps |
| CPU time | 32.48 seconds |
| Started | May 30 03:50:50 PM PDT 24 |
| Finished | May 30 03:51:24 PM PDT 24 |
| Peak memory | 573056 kb |
| Host | smart-1c399bf7-d428-4883-897d-dbd4cbeac404 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423892744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.2423892744 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke.2015354410 |
| Short name | T1865 |
| Test name | |
| Test status | |
| Simulation time | 162981210 ps |
| CPU time | 8.13 seconds |
| Started | May 30 03:50:55 PM PDT 24 |
| Finished | May 30 03:51:04 PM PDT 24 |
| Peak memory | 564800 kb |
| Host | smart-1f8ec428-c987-44e8-bd12-cd32d099c05f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015354410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.2015354410 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.4012530684 |
| Short name | T2792 |
| Test name | |
| Test status | |
| Simulation time | 5442537646 ps |
| CPU time | 58.63 seconds |
| Started | May 30 03:50:50 PM PDT 24 |
| Finished | May 30 03:51:50 PM PDT 24 |
| Peak memory | 563444 kb |
| Host | smart-cdb2b726-5855-4acd-b745-d1670ca625cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012530684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.4012530684 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.475204010 |
| Short name | T1319 |
| Test name | |
| Test status | |
| Simulation time | 5492184015 ps |
| CPU time | 98.83 seconds |
| Started | May 30 03:50:52 PM PDT 24 |
| Finished | May 30 03:52:31 PM PDT 24 |
| Peak memory | 564960 kb |
| Host | smart-5d0af71f-9eab-4780-b4b5-def00027b271 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475204010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.475204010 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.1385196225 |
| Short name | T2788 |
| Test name | |
| Test status | |
| Simulation time | 48698090 ps |
| CPU time | 6.09 seconds |
| Started | May 30 03:51:03 PM PDT 24 |
| Finished | May 30 03:51:10 PM PDT 24 |
| Peak memory | 564784 kb |
| Host | smart-5442cdb6-d5b9-498d-af75-ecd19657b317 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385196225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delay s.1385196225 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all.1214215407 |
| Short name | T2243 |
| Test name | |
| Test status | |
| Simulation time | 6886040777 ps |
| CPU time | 252.69 seconds |
| Started | May 30 03:51:03 PM PDT 24 |
| Finished | May 30 03:55:16 PM PDT 24 |
| Peak memory | 573132 kb |
| Host | smart-2948d8cf-7513-4799-9edc-0ed2c8ffd827 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214215407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.1214215407 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.251640046 |
| Short name | T2663 |
| Test name | |
| Test status | |
| Simulation time | 102683681 ps |
| CPU time | 61.23 seconds |
| Started | May 30 03:51:00 PM PDT 24 |
| Finished | May 30 03:52:02 PM PDT 24 |
| Peak memory | 573104 kb |
| Host | smart-60929ea1-edcd-4dc8-b763-1591b986a8a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251640046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_ with_rand_reset.251640046 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.1249224467 |
| Short name | T1639 |
| Test name | |
| Test status | |
| Simulation time | 493491032 ps |
| CPU time | 142.78 seconds |
| Started | May 30 03:50:59 PM PDT 24 |
| Finished | May 30 03:53:22 PM PDT 24 |
| Peak memory | 573080 kb |
| Host | smart-de2757e3-aef2-4963-8675-0c8e93bb411b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249224467 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_al l_with_reset_error.1249224467 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_unmapped_addr.3006488285 |
| Short name | T1505 |
| Test name | |
| Test status | |
| Simulation time | 229229070 ps |
| CPU time | 25.59 seconds |
| Started | May 30 03:50:51 PM PDT 24 |
| Finished | May 30 03:51:17 PM PDT 24 |
| Peak memory | 573100 kb |
| Host | smart-78d240e8-698e-43e3-98ab-9d2d6d7a5b4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006488285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.3006488285 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.chip_tl_errors.1764168969 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 4207990130 ps |
| CPU time | 330.64 seconds |
| Started | May 30 03:51:08 PM PDT 24 |
| Finished | May 30 03:56:40 PM PDT 24 |
| Peak memory | 594032 kb |
| Host | smart-dc578419-75b2-4486-960e-7fdc5c4e7e61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764168969 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.chip_tl_errors.1764168969 |
| Directory | /workspace/28.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device.2918402793 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 1498498756 ps |
| CPU time | 59.11 seconds |
| Started | May 30 03:51:00 PM PDT 24 |
| Finished | May 30 03:52:00 PM PDT 24 |
| Peak memory | 573020 kb |
| Host | smart-08d4e530-452a-4ab8-a746-0e007c9d48f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918402793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device .2918402793 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.2871940899 |
| Short name | T2265 |
| Test name | |
| Test status | |
| Simulation time | 168067737848 ps |
| CPU time | 2866.29 seconds |
| Started | May 30 03:51:01 PM PDT 24 |
| Finished | May 30 04:38:48 PM PDT 24 |
| Peak memory | 573232 kb |
| Host | smart-ac91df3e-2d21-42d9-b46a-8ce65f9c1c83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871940899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_ device_slow_rsp.2871940899 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.1931652320 |
| Short name | T2489 |
| Test name | |
| Test status | |
| Simulation time | 47188855 ps |
| CPU time | 8.24 seconds |
| Started | May 30 03:51:10 PM PDT 24 |
| Finished | May 30 03:51:19 PM PDT 24 |
| Peak memory | 564800 kb |
| Host | smart-64fedc25-0796-4cfa-ab93-9921489b41e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931652320 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_add r.1931652320 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_random.3916581119 |
| Short name | T2191 |
| Test name | |
| Test status | |
| Simulation time | 847755144 ps |
| CPU time | 32.74 seconds |
| Started | May 30 03:51:04 PM PDT 24 |
| Finished | May 30 03:51:38 PM PDT 24 |
| Peak memory | 572884 kb |
| Host | smart-3f1c6732-0dc8-47b1-a3b9-0dba5d39c998 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916581119 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.3916581119 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random.1322184979 |
| Short name | T2035 |
| Test name | |
| Test status | |
| Simulation time | 1447360924 ps |
| CPU time | 54.87 seconds |
| Started | May 30 03:51:04 PM PDT 24 |
| Finished | May 30 03:52:00 PM PDT 24 |
| Peak memory | 572908 kb |
| Host | smart-dc97993a-fe86-4db1-8e4b-f55aa7ec485f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322184979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random.1322184979 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_large_delays.319357893 |
| Short name | T2370 |
| Test name | |
| Test status | |
| Simulation time | 89634968611 ps |
| CPU time | 939.87 seconds |
| Started | May 30 03:51:01 PM PDT 24 |
| Finished | May 30 04:06:42 PM PDT 24 |
| Peak memory | 573160 kb |
| Host | smart-b090828d-d26d-451f-aec7-cb3acffffc52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319357893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.319357893 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_slow_rsp.1696122880 |
| Short name | T1602 |
| Test name | |
| Test status | |
| Simulation time | 10583679959 ps |
| CPU time | 193.14 seconds |
| Started | May 30 03:51:02 PM PDT 24 |
| Finished | May 30 03:54:16 PM PDT 24 |
| Peak memory | 573176 kb |
| Host | smart-69dbbaf1-0eee-452f-905b-4eb69369ca58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696122880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.1696122880 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_zero_delays.3470297793 |
| Short name | T2222 |
| Test name | |
| Test status | |
| Simulation time | 176287089 ps |
| CPU time | 18.93 seconds |
| Started | May 30 03:51:03 PM PDT 24 |
| Finished | May 30 03:51:23 PM PDT 24 |
| Peak memory | 573032 kb |
| Host | smart-26b2cd1c-7c2a-4c80-ac3f-875396029b7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470297793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_del ays.3470297793 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_same_source.844729428 |
| Short name | T2299 |
| Test name | |
| Test status | |
| Simulation time | 238021816 ps |
| CPU time | 20.1 seconds |
| Started | May 30 03:51:02 PM PDT 24 |
| Finished | May 30 03:51:23 PM PDT 24 |
| Peak memory | 573076 kb |
| Host | smart-a2c7b960-41a9-460d-b348-3722490ee18b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844729428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.844729428 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke.1452416560 |
| Short name | T1327 |
| Test name | |
| Test status | |
| Simulation time | 203009492 ps |
| CPU time | 9.05 seconds |
| Started | May 30 03:51:00 PM PDT 24 |
| Finished | May 30 03:51:10 PM PDT 24 |
| Peak memory | 564888 kb |
| Host | smart-805068bf-e17b-4fec-bdd6-c6be95fa2e61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452416560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.1452416560 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_large_delays.262710530 |
| Short name | T1414 |
| Test name | |
| Test status | |
| Simulation time | 7222053005 ps |
| CPU time | 70.85 seconds |
| Started | May 30 03:51:08 PM PDT 24 |
| Finished | May 30 03:52:20 PM PDT 24 |
| Peak memory | 563468 kb |
| Host | smart-b9f1788f-19da-4a28-b737-31c4babaf7dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262710530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.262710530 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.4278620778 |
| Short name | T2616 |
| Test name | |
| Test status | |
| Simulation time | 3564714302 ps |
| CPU time | 65.93 seconds |
| Started | May 30 03:51:00 PM PDT 24 |
| Finished | May 30 03:52:07 PM PDT 24 |
| Peak memory | 564908 kb |
| Host | smart-dc73954d-6de9-4dba-85f5-5d089c22d0d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278620778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.4278620778 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.802046177 |
| Short name | T1418 |
| Test name | |
| Test status | |
| Simulation time | 44614620 ps |
| CPU time | 5.86 seconds |
| Started | May 30 03:51:07 PM PDT 24 |
| Finished | May 30 03:51:14 PM PDT 24 |
| Peak memory | 563356 kb |
| Host | smart-8d85089a-9f0d-439d-91d1-f6942afefe25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802046177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays .802046177 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all.4170866071 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 2923727149 ps |
| CPU time | 103.51 seconds |
| Started | May 30 03:51:08 PM PDT 24 |
| Finished | May 30 03:52:53 PM PDT 24 |
| Peak memory | 573072 kb |
| Host | smart-29174c85-c747-4a55-9e87-a58ec6590a7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170866071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.4170866071 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.1608421937 |
| Short name | T2543 |
| Test name | |
| Test status | |
| Simulation time | 1748018387 ps |
| CPU time | 126.48 seconds |
| Started | May 30 03:51:11 PM PDT 24 |
| Finished | May 30 03:53:19 PM PDT 24 |
| Peak memory | 575088 kb |
| Host | smart-f8a3719e-7680-40fe-aaba-6a0ea6d201e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608421937 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.1608421937 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.2569982000 |
| Short name | T2239 |
| Test name | |
| Test status | |
| Simulation time | 129069578 ps |
| CPU time | 37.24 seconds |
| Started | May 30 03:51:09 PM PDT 24 |
| Finished | May 30 03:51:48 PM PDT 24 |
| Peak memory | 573116 kb |
| Host | smart-ab9e8dc0-6efc-4ea7-9d4d-01102aa382a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569982000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all _with_rand_reset.2569982000 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.146436901 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 3902354454 ps |
| CPU time | 346.78 seconds |
| Started | May 30 03:51:09 PM PDT 24 |
| Finished | May 30 03:56:57 PM PDT 24 |
| Peak memory | 581264 kb |
| Host | smart-482df671-9086-4f1e-9de5-40741ebf950f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146436901 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all _with_reset_error.146436901 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_unmapped_addr.1961865802 |
| Short name | T1335 |
| Test name | |
| Test status | |
| Simulation time | 302252688 ps |
| CPU time | 33.94 seconds |
| Started | May 30 03:51:03 PM PDT 24 |
| Finished | May 30 03:51:37 PM PDT 24 |
| Peak memory | 573092 kb |
| Host | smart-8adf70b0-e11c-4365-aba1-d889470b0a95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961865802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.1961865802 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.chip_tl_errors.3122582142 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 3063810877 ps |
| CPU time | 230.95 seconds |
| Started | May 30 03:51:09 PM PDT 24 |
| Finished | May 30 03:55:00 PM PDT 24 |
| Peak memory | 593988 kb |
| Host | smart-48a39bc3-5da8-4cd4-baed-8f5486e0676c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122582142 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.chip_tl_errors.3122582142 |
| Directory | /workspace/29.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device.2507000281 |
| Short name | T2520 |
| Test name | |
| Test status | |
| Simulation time | 2761410036 ps |
| CPU time | 118.61 seconds |
| Started | May 30 03:51:10 PM PDT 24 |
| Finished | May 30 03:53:10 PM PDT 24 |
| Peak memory | 573028 kb |
| Host | smart-da766d31-2e8d-4691-8fb8-e7835c066021 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507000281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device .2507000281 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.2031235062 |
| Short name | T2650 |
| Test name | |
| Test status | |
| Simulation time | 42408629494 ps |
| CPU time | 710.8 seconds |
| Started | May 30 03:51:13 PM PDT 24 |
| Finished | May 30 04:03:05 PM PDT 24 |
| Peak memory | 573264 kb |
| Host | smart-f87a8deb-ba1e-4452-873c-4d217a6eb220 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031235062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_ device_slow_rsp.2031235062 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.3333808224 |
| Short name | T1555 |
| Test name | |
| Test status | |
| Simulation time | 228163875 ps |
| CPU time | 29.85 seconds |
| Started | May 30 03:51:18 PM PDT 24 |
| Finished | May 30 03:51:49 PM PDT 24 |
| Peak memory | 573984 kb |
| Host | smart-a446c39b-5b39-4f64-bf88-51acb7c9dd0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333808224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_add r.3333808224 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_random.1758449493 |
| Short name | T1606 |
| Test name | |
| Test status | |
| Simulation time | 127268210 ps |
| CPU time | 12.52 seconds |
| Started | May 30 03:51:09 PM PDT 24 |
| Finished | May 30 03:51:22 PM PDT 24 |
| Peak memory | 572940 kb |
| Host | smart-37f00b90-7f08-4e01-b521-3f3d4d313747 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758449493 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.1758449493 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random.453140797 |
| Short name | T1661 |
| Test name | |
| Test status | |
| Simulation time | 2189240471 ps |
| CPU time | 76.48 seconds |
| Started | May 30 03:51:09 PM PDT 24 |
| Finished | May 30 03:52:26 PM PDT 24 |
| Peak memory | 573084 kb |
| Host | smart-5036caf1-3018-4002-8e98-8bfa1da32f05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453140797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random.453140797 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_large_delays.676377038 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 92253359855 ps |
| CPU time | 1024.23 seconds |
| Started | May 30 03:51:08 PM PDT 24 |
| Finished | May 30 04:08:14 PM PDT 24 |
| Peak memory | 573172 kb |
| Host | smart-f6a19449-6933-4fe7-a654-5a9bf7b6d32b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676377038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.676377038 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.2517534452 |
| Short name | T2866 |
| Test name | |
| Test status | |
| Simulation time | 26270970274 ps |
| CPU time | 438.34 seconds |
| Started | May 30 03:51:13 PM PDT 24 |
| Finished | May 30 03:58:32 PM PDT 24 |
| Peak memory | 573196 kb |
| Host | smart-49b513c0-fae6-4db6-bd8a-57c10129881e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517534452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.2517534452 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_zero_delays.1500546687 |
| Short name | T2112 |
| Test name | |
| Test status | |
| Simulation time | 116771915 ps |
| CPU time | 14.24 seconds |
| Started | May 30 03:51:09 PM PDT 24 |
| Finished | May 30 03:51:25 PM PDT 24 |
| Peak memory | 573012 kb |
| Host | smart-126cdf41-762c-4865-954a-1e401a9f9176 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500546687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_del ays.1500546687 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_same_source.2431080488 |
| Short name | T2506 |
| Test name | |
| Test status | |
| Simulation time | 416337075 ps |
| CPU time | 34.35 seconds |
| Started | May 30 03:51:09 PM PDT 24 |
| Finished | May 30 03:51:44 PM PDT 24 |
| Peak memory | 572956 kb |
| Host | smart-616f4987-999f-4fea-90d4-8af16d51c904 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431080488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.2431080488 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke.3534492729 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 227202065 ps |
| CPU time | 9.82 seconds |
| Started | May 30 03:51:13 PM PDT 24 |
| Finished | May 30 03:51:24 PM PDT 24 |
| Peak memory | 564820 kb |
| Host | smart-4f0e319e-376f-4b73-a470-4ed637bde1f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534492729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.3534492729 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_large_delays.3477958359 |
| Short name | T2770 |
| Test name | |
| Test status | |
| Simulation time | 8491600056 ps |
| CPU time | 88.6 seconds |
| Started | May 30 03:51:09 PM PDT 24 |
| Finished | May 30 03:52:38 PM PDT 24 |
| Peak memory | 564972 kb |
| Host | smart-8eca2941-85ff-4719-91ff-e0e4c10b8185 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477958359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.3477958359 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.1703694028 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 4770222925 ps |
| CPU time | 86.57 seconds |
| Started | May 30 03:51:11 PM PDT 24 |
| Finished | May 30 03:52:38 PM PDT 24 |
| Peak memory | 564884 kb |
| Host | smart-0b9ca940-e440-4830-b028-fd580db70359 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703694028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.1703694028 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_zero_delays.1421483466 |
| Short name | T2030 |
| Test name | |
| Test status | |
| Simulation time | 36771927 ps |
| CPU time | 5.64 seconds |
| Started | May 30 03:51:10 PM PDT 24 |
| Finished | May 30 03:51:16 PM PDT 24 |
| Peak memory | 564792 kb |
| Host | smart-168f6b2a-72ce-4629-8df6-b4b21c52417c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421483466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delay s.1421483466 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all.1203909980 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 6058136084 ps |
| CPU time | 273.01 seconds |
| Started | May 30 03:51:21 PM PDT 24 |
| Finished | May 30 03:55:55 PM PDT 24 |
| Peak memory | 573308 kb |
| Host | smart-5f7aae5f-908b-4904-aa89-c4f1641b8da8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203909980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.1203909980 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.3079262142 |
| Short name | T1696 |
| Test name | |
| Test status | |
| Simulation time | 15158806680 ps |
| CPU time | 604.28 seconds |
| Started | May 30 03:51:20 PM PDT 24 |
| Finished | May 30 04:01:25 PM PDT 24 |
| Peak memory | 573152 kb |
| Host | smart-12ad54a6-86bd-4e13-9d60-354a408fdf32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079262142 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.3079262142 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.1096378950 |
| Short name | T1486 |
| Test name | |
| Test status | |
| Simulation time | 419742013 ps |
| CPU time | 144.71 seconds |
| Started | May 30 03:51:20 PM PDT 24 |
| Finished | May 30 03:53:46 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-c858ff76-c3b8-4502-a80c-443091caef19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096378950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all _with_rand_reset.1096378950 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.4152695504 |
| Short name | T1706 |
| Test name | |
| Test status | |
| Simulation time | 3293373694 ps |
| CPU time | 271.48 seconds |
| Started | May 30 03:51:19 PM PDT 24 |
| Finished | May 30 03:55:51 PM PDT 24 |
| Peak memory | 573184 kb |
| Host | smart-31e5ba94-5da3-48ba-b28a-bbd9df6002a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152695504 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_al l_with_reset_error.4152695504 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_unmapped_addr.179269313 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 474399809 ps |
| CPU time | 22.97 seconds |
| Started | May 30 03:51:21 PM PDT 24 |
| Finished | May 30 03:51:45 PM PDT 24 |
| Peak memory | 573048 kb |
| Host | smart-5f4a4e13-b698-4863-ad61-5c41f15c0f6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179269313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.179269313 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_aliasing.2285349814 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 62980754428 ps |
| CPU time | 9883.06 seconds |
| Started | May 30 03:48:39 PM PDT 24 |
| Finished | May 30 06:33:24 PM PDT 24 |
| Peak memory | 639648 kb |
| Host | smart-8b9a82ea-fc20-4ecf-9273-bd26c3451e1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285349814 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.chip_csr_aliasing.2285349814 |
| Directory | /workspace/3.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_bit_bash.4154239271 |
| Short name | T2845 |
| Test name | |
| Test status | |
| Simulation time | 4301012150 ps |
| CPU time | 399.99 seconds |
| Started | May 30 03:48:58 PM PDT 24 |
| Finished | May 30 03:55:40 PM PDT 24 |
| Peak memory | 586184 kb |
| Host | smart-e4b06cb3-c044-44ac-9a98-8bd3dc08bb44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154239271 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 3.chip_csr_bit_bash.4154239271 |
| Directory | /workspace/3.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.2462222157 |
| Short name | T2332 |
| Test name | |
| Test status | |
| Simulation time | 31803276748 ps |
| CPU time | 5374.21 seconds |
| Started | May 30 03:48:34 PM PDT 24 |
| Finished | May 30 05:18:10 PM PDT 24 |
| Peak memory | 588096 kb |
| Host | smart-20965c6d-971a-4135-96c1-d44435754bf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462222157 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 3.chip_same_csr_outstanding.2462222157 |
| Directory | /workspace/3.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_tl_errors.4050105553 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 3532471347 ps |
| CPU time | 280.02 seconds |
| Started | May 30 03:48:39 PM PDT 24 |
| Finished | May 30 03:53:20 PM PDT 24 |
| Peak memory | 594036 kb |
| Host | smart-607ac6c2-ba6e-44f4-8447-1fa79fe37af2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050105553 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_tl_errors.4050105553 |
| Directory | /workspace/3.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device.2655207061 |
| Short name | T1656 |
| Test name | |
| Test status | |
| Simulation time | 289438204 ps |
| CPU time | 21.33 seconds |
| Started | May 30 03:48:48 PM PDT 24 |
| Finished | May 30 03:49:10 PM PDT 24 |
| Peak memory | 573052 kb |
| Host | smart-453a6300-1f99-4512-8f21-764b12491234 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655207061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device. 2655207061 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.2711826824 |
| Short name | T2111 |
| Test name | |
| Test status | |
| Simulation time | 2763381486 ps |
| CPU time | 45.02 seconds |
| Started | May 30 03:48:47 PM PDT 24 |
| Finished | May 30 03:49:34 PM PDT 24 |
| Peak memory | 564952 kb |
| Host | smart-10f7998b-77ed-4b8d-80a2-f8a88b7f5e62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711826824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_d evice_slow_rsp.2711826824 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.3181726907 |
| Short name | T1823 |
| Test name | |
| Test status | |
| Simulation time | 687359387 ps |
| CPU time | 25.06 seconds |
| Started | May 30 03:48:38 PM PDT 24 |
| Finished | May 30 03:49:05 PM PDT 24 |
| Peak memory | 572940 kb |
| Host | smart-817f4360-31a9-4747-8076-03b0670c40f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181726907 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr .3181726907 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_random.1844854543 |
| Short name | T1336 |
| Test name | |
| Test status | |
| Simulation time | 883854156 ps |
| CPU time | 31.92 seconds |
| Started | May 30 03:48:35 PM PDT 24 |
| Finished | May 30 03:49:08 PM PDT 24 |
| Peak memory | 572880 kb |
| Host | smart-b5a5d283-c3e4-48ad-8f0f-59b70b043928 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844854543 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.1844854543 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random.3696686295 |
| Short name | T1541 |
| Test name | |
| Test status | |
| Simulation time | 31161617 ps |
| CPU time | 5.58 seconds |
| Started | May 30 03:48:41 PM PDT 24 |
| Finished | May 30 03:48:48 PM PDT 24 |
| Peak memory | 564864 kb |
| Host | smart-5b3944d3-5970-489e-9e74-56329bffdb90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696686295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random.3696686295 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_large_delays.91246118 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 64431698954 ps |
| CPU time | 726.39 seconds |
| Started | May 30 03:48:40 PM PDT 24 |
| Finished | May 30 04:00:48 PM PDT 24 |
| Peak memory | 573096 kb |
| Host | smart-e9afb867-77a2-43e1-86f5-6bbcabbeb2ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91246118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.91246118 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.2648091735 |
| Short name | T2494 |
| Test name | |
| Test status | |
| Simulation time | 35229435508 ps |
| CPU time | 589.87 seconds |
| Started | May 30 03:48:41 PM PDT 24 |
| Finished | May 30 03:58:33 PM PDT 24 |
| Peak memory | 573136 kb |
| Host | smart-8fff9676-4cdf-49a8-af33-a686733436f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648091735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.2648091735 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_zero_delays.360328228 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 175207397 ps |
| CPU time | 14.54 seconds |
| Started | May 30 03:48:44 PM PDT 24 |
| Finished | May 30 03:49:00 PM PDT 24 |
| Peak memory | 573040 kb |
| Host | smart-0578e399-3531-447b-94cb-7dfa976ecce0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360328228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delay s.360328228 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_same_source.2297282547 |
| Short name | T1624 |
| Test name | |
| Test status | |
| Simulation time | 134129496 ps |
| CPU time | 12.46 seconds |
| Started | May 30 03:48:40 PM PDT 24 |
| Finished | May 30 03:48:54 PM PDT 24 |
| Peak memory | 573048 kb |
| Host | smart-fe6919e5-1ff7-489c-b007-6fdf44fc6f8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297282547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.2297282547 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke.3266583341 |
| Short name | T2146 |
| Test name | |
| Test status | |
| Simulation time | 43590640 ps |
| CPU time | 5.47 seconds |
| Started | May 30 03:48:48 PM PDT 24 |
| Finished | May 30 03:48:55 PM PDT 24 |
| Peak memory | 564816 kb |
| Host | smart-571be511-292a-4f86-a6c8-453233bd9f8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266583341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.3266583341 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_large_delays.717686339 |
| Short name | T1377 |
| Test name | |
| Test status | |
| Simulation time | 9629476098 ps |
| CPU time | 102.44 seconds |
| Started | May 30 03:48:41 PM PDT 24 |
| Finished | May 30 03:50:25 PM PDT 24 |
| Peak memory | 564948 kb |
| Host | smart-7254424e-8503-45dc-a2ed-7920b3742ce5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717686339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.717686339 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.238908249 |
| Short name | T1446 |
| Test name | |
| Test status | |
| Simulation time | 6617563494 ps |
| CPU time | 103.7 seconds |
| Started | May 30 03:48:41 PM PDT 24 |
| Finished | May 30 03:50:27 PM PDT 24 |
| Peak memory | 564952 kb |
| Host | smart-6a8b5e7b-2773-48d6-82eb-216742726b68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238908249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.238908249 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.786372363 |
| Short name | T2615 |
| Test name | |
| Test status | |
| Simulation time | 48732753 ps |
| CPU time | 6.08 seconds |
| Started | May 30 03:48:37 PM PDT 24 |
| Finished | May 30 03:48:44 PM PDT 24 |
| Peak memory | 564776 kb |
| Host | smart-9fe7f1dc-c613-4cf5-a18e-b7f8b3e3c7b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786372363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays. 786372363 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all.546357280 |
| Short name | T1836 |
| Test name | |
| Test status | |
| Simulation time | 3826126606 ps |
| CPU time | 144.8 seconds |
| Started | May 30 03:48:40 PM PDT 24 |
| Finished | May 30 03:51:07 PM PDT 24 |
| Peak memory | 572828 kb |
| Host | smart-5effde7c-c8fd-4554-a3a0-d181358dbf10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546357280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.546357280 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.4053235359 |
| Short name | T1437 |
| Test name | |
| Test status | |
| Simulation time | 18365781528 ps |
| CPU time | 743.63 seconds |
| Started | May 30 03:48:50 PM PDT 24 |
| Finished | May 30 04:01:15 PM PDT 24 |
| Peak memory | 573196 kb |
| Host | smart-9bd6853e-3e41-47db-83b0-c4560ae5eae8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053235359 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.4053235359 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.2754767881 |
| Short name | T2018 |
| Test name | |
| Test status | |
| Simulation time | 27114056 ps |
| CPU time | 35.32 seconds |
| Started | May 30 03:48:57 PM PDT 24 |
| Finished | May 30 03:49:34 PM PDT 24 |
| Peak memory | 564924 kb |
| Host | smart-13253e8d-6807-4edb-a9ed-826739206ba9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754767881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_ with_rand_reset.2754767881 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.4127352028 |
| Short name | T1950 |
| Test name | |
| Test status | |
| Simulation time | 20568250466 ps |
| CPU time | 949.31 seconds |
| Started | May 30 03:49:00 PM PDT 24 |
| Finished | May 30 04:04:51 PM PDT 24 |
| Peak memory | 580416 kb |
| Host | smart-916db45b-2add-4feb-816e-916c41cfca68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127352028 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all _with_reset_error.4127352028 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_unmapped_addr.1826060527 |
| Short name | T1539 |
| Test name | |
| Test status | |
| Simulation time | 67777350 ps |
| CPU time | 9.62 seconds |
| Started | May 30 03:48:45 PM PDT 24 |
| Finished | May 30 03:48:57 PM PDT 24 |
| Peak memory | 573036 kb |
| Host | smart-15acdc92-9a08-4eb5-b7e7-a2d64af44362 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826060527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.1826060527 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device.2081841166 |
| Short name | T1585 |
| Test name | |
| Test status | |
| Simulation time | 168997884 ps |
| CPU time | 13.89 seconds |
| Started | May 30 03:51:23 PM PDT 24 |
| Finished | May 30 03:51:38 PM PDT 24 |
| Peak memory | 564836 kb |
| Host | smart-992c9a92-a8b7-4dcb-9c51-8488067a8150 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081841166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device .2081841166 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.3116322617 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 104961261771 ps |
| CPU time | 1865.63 seconds |
| Started | May 30 03:51:21 PM PDT 24 |
| Finished | May 30 04:22:28 PM PDT 24 |
| Peak memory | 573328 kb |
| Host | smart-f7d1d23f-b676-4827-a018-0b14ed4a3690 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116322617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_ device_slow_rsp.3116322617 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.4264275382 |
| Short name | T1354 |
| Test name | |
| Test status | |
| Simulation time | 73063463 ps |
| CPU time | 6.41 seconds |
| Started | May 30 03:51:30 PM PDT 24 |
| Finished | May 30 03:51:37 PM PDT 24 |
| Peak memory | 564696 kb |
| Host | smart-5ac9e386-ca72-4fe2-9b73-27a10ed05e89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264275382 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_add r.4264275382 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_random.3713352923 |
| Short name | T2677 |
| Test name | |
| Test status | |
| Simulation time | 1249062761 ps |
| CPU time | 46.56 seconds |
| Started | May 30 03:51:20 PM PDT 24 |
| Finished | May 30 03:52:08 PM PDT 24 |
| Peak memory | 572888 kb |
| Host | smart-be401558-e87e-4a16-ab97-f3d79fd4d0c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713352923 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.3713352923 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random.459619524 |
| Short name | T2305 |
| Test name | |
| Test status | |
| Simulation time | 1234356710 ps |
| CPU time | 47.12 seconds |
| Started | May 30 03:51:19 PM PDT 24 |
| Finished | May 30 03:52:08 PM PDT 24 |
| Peak memory | 573064 kb |
| Host | smart-3dceb05e-c30b-47ad-85af-cbe3e4c77dbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459619524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random.459619524 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_large_delays.473423986 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 6703109327 ps |
| CPU time | 75.47 seconds |
| Started | May 30 03:51:19 PM PDT 24 |
| Finished | May 30 03:52:35 PM PDT 24 |
| Peak memory | 564980 kb |
| Host | smart-179a82cd-b535-4bb8-8aa4-ec7bcb9800eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473423986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.473423986 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_slow_rsp.3867047402 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 38340549590 ps |
| CPU time | 598.84 seconds |
| Started | May 30 03:51:22 PM PDT 24 |
| Finished | May 30 04:01:21 PM PDT 24 |
| Peak memory | 573164 kb |
| Host | smart-87be744a-ba6e-45fb-ae55-6e641be1234b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867047402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.3867047402 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_zero_delays.562591088 |
| Short name | T1510 |
| Test name | |
| Test status | |
| Simulation time | 567706750 ps |
| CPU time | 48.5 seconds |
| Started | May 30 03:51:21 PM PDT 24 |
| Finished | May 30 03:52:11 PM PDT 24 |
| Peak memory | 573044 kb |
| Host | smart-bf82e739-a018-48bc-876d-1b0ccaa13993 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562591088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_dela ys.562591088 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_same_source.2910043451 |
| Short name | T2353 |
| Test name | |
| Test status | |
| Simulation time | 1857027497 ps |
| CPU time | 58.08 seconds |
| Started | May 30 03:51:19 PM PDT 24 |
| Finished | May 30 03:52:18 PM PDT 24 |
| Peak memory | 573064 kb |
| Host | smart-9a69185b-601b-4271-bfb6-69d934fd24bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910043451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.2910043451 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke.2019044927 |
| Short name | T1681 |
| Test name | |
| Test status | |
| Simulation time | 40754614 ps |
| CPU time | 6.24 seconds |
| Started | May 30 03:51:22 PM PDT 24 |
| Finished | May 30 03:51:29 PM PDT 24 |
| Peak memory | 563400 kb |
| Host | smart-25a9a20f-bf54-4df8-93ae-ef76f1d8eb20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019044927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.2019044927 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_large_delays.586186037 |
| Short name | T1892 |
| Test name | |
| Test status | |
| Simulation time | 8972216513 ps |
| CPU time | 89.64 seconds |
| Started | May 30 03:51:24 PM PDT 24 |
| Finished | May 30 03:52:54 PM PDT 24 |
| Peak memory | 564928 kb |
| Host | smart-9e0a45fd-fb52-4873-9d54-900f9e6bc97b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586186037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.586186037 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.3348512799 |
| Short name | T2734 |
| Test name | |
| Test status | |
| Simulation time | 5499514127 ps |
| CPU time | 98.13 seconds |
| Started | May 30 03:51:20 PM PDT 24 |
| Finished | May 30 03:52:59 PM PDT 24 |
| Peak memory | 564948 kb |
| Host | smart-a71d2aa4-68aa-4497-862c-937049ab033f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348512799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.3348512799 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_zero_delays.2285848059 |
| Short name | T2505 |
| Test name | |
| Test status | |
| Simulation time | 43163008 ps |
| CPU time | 5.84 seconds |
| Started | May 30 03:51:21 PM PDT 24 |
| Finished | May 30 03:51:27 PM PDT 24 |
| Peak memory | 563364 kb |
| Host | smart-80a8de57-17da-47d1-9f07-5693191f9bdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285848059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delay s.2285848059 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all.2621523050 |
| Short name | T2493 |
| Test name | |
| Test status | |
| Simulation time | 6473918 ps |
| CPU time | 3.66 seconds |
| Started | May 30 03:51:30 PM PDT 24 |
| Finished | May 30 03:51:35 PM PDT 24 |
| Peak memory | 564576 kb |
| Host | smart-23ddeeae-7127-4cda-994c-90b56be8add4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621523050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.2621523050 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.3666755896 |
| Short name | T2504 |
| Test name | |
| Test status | |
| Simulation time | 21862399917 ps |
| CPU time | 928.88 seconds |
| Started | May 30 03:51:37 PM PDT 24 |
| Finished | May 30 04:07:07 PM PDT 24 |
| Peak memory | 573268 kb |
| Host | smart-34ddfd24-de84-4fcf-9482-aecd7d5c33f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666755896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all _with_rand_reset.3666755896 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.3328794463 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 199508340 ps |
| CPU time | 88.92 seconds |
| Started | May 30 03:51:34 PM PDT 24 |
| Finished | May 30 03:53:03 PM PDT 24 |
| Peak memory | 573084 kb |
| Host | smart-7903c358-a292-4cb9-9348-1ebf34fbae7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328794463 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_al l_with_reset_error.3328794463 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_unmapped_addr.2730074174 |
| Short name | T2284 |
| Test name | |
| Test status | |
| Simulation time | 530595925 ps |
| CPU time | 23.66 seconds |
| Started | May 30 03:51:20 PM PDT 24 |
| Finished | May 30 03:51:44 PM PDT 24 |
| Peak memory | 573072 kb |
| Host | smart-a5d801ad-b3c4-43b0-813c-8c93c5788c0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730074174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.2730074174 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device.1504597029 |
| Short name | T2744 |
| Test name | |
| Test status | |
| Simulation time | 253151112 ps |
| CPU time | 24.47 seconds |
| Started | May 30 03:51:30 PM PDT 24 |
| Finished | May 30 03:51:55 PM PDT 24 |
| Peak memory | 573004 kb |
| Host | smart-91ce0190-0922-4212-8ba8-b794eabae267 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504597029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device .1504597029 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.3047760370 |
| Short name | T1487 |
| Test name | |
| Test status | |
| Simulation time | 24662294927 ps |
| CPU time | 430.26 seconds |
| Started | May 30 03:51:32 PM PDT 24 |
| Finished | May 30 03:58:44 PM PDT 24 |
| Peak memory | 573240 kb |
| Host | smart-a7f0ae2d-a044-4370-aecb-6d19bc5bd499 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047760370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_ device_slow_rsp.3047760370 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.1252842154 |
| Short name | T1802 |
| Test name | |
| Test status | |
| Simulation time | 171228754 ps |
| CPU time | 22.37 seconds |
| Started | May 30 03:51:32 PM PDT 24 |
| Finished | May 30 03:51:56 PM PDT 24 |
| Peak memory | 572788 kb |
| Host | smart-a97f57f0-1aff-48a1-8b37-c10faa7ecaf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252842154 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_add r.1252842154 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_random.3447626503 |
| Short name | T2839 |
| Test name | |
| Test status | |
| Simulation time | 439339742 ps |
| CPU time | 39.04 seconds |
| Started | May 30 03:51:33 PM PDT 24 |
| Finished | May 30 03:52:13 PM PDT 24 |
| Peak memory | 572820 kb |
| Host | smart-69c3d789-a3d7-4d63-914f-098f5adf1aaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447626503 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.3447626503 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random.3926788756 |
| Short name | T1405 |
| Test name | |
| Test status | |
| Simulation time | 2168454987 ps |
| CPU time | 88.56 seconds |
| Started | May 30 03:51:30 PM PDT 24 |
| Finished | May 30 03:53:00 PM PDT 24 |
| Peak memory | 573128 kb |
| Host | smart-46100fec-7f98-4012-aeeb-36f2ace1c6b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926788756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random.3926788756 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_large_delays.2343300949 |
| Short name | T1867 |
| Test name | |
| Test status | |
| Simulation time | 23565360380 ps |
| CPU time | 232.93 seconds |
| Started | May 30 03:51:32 PM PDT 24 |
| Finished | May 30 03:55:26 PM PDT 24 |
| Peak memory | 573048 kb |
| Host | smart-2d72a1e6-3cd4-411b-9127-049cb5db4dbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343300949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.2343300949 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_slow_rsp.2893005729 |
| Short name | T1782 |
| Test name | |
| Test status | |
| Simulation time | 12868946735 ps |
| CPU time | 246.72 seconds |
| Started | May 30 03:51:30 PM PDT 24 |
| Finished | May 30 03:55:39 PM PDT 24 |
| Peak memory | 573192 kb |
| Host | smart-c7bb6968-977f-4827-81f6-3f6a7f65734f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893005729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.2893005729 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_zero_delays.2775562267 |
| Short name | T1978 |
| Test name | |
| Test status | |
| Simulation time | 498080155 ps |
| CPU time | 42.39 seconds |
| Started | May 30 03:51:41 PM PDT 24 |
| Finished | May 30 03:52:24 PM PDT 24 |
| Peak memory | 573076 kb |
| Host | smart-33248209-8ae5-45a5-bdb6-2c11e8a6c96a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775562267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_del ays.2775562267 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_same_source.379919955 |
| Short name | T2713 |
| Test name | |
| Test status | |
| Simulation time | 221479489 ps |
| CPU time | 18.89 seconds |
| Started | May 30 03:51:30 PM PDT 24 |
| Finished | May 30 03:51:50 PM PDT 24 |
| Peak memory | 573056 kb |
| Host | smart-177491e9-67c8-464a-a2eb-0ccb31b83030 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379919955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.379919955 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke.3524973772 |
| Short name | T1352 |
| Test name | |
| Test status | |
| Simulation time | 45210321 ps |
| CPU time | 6.29 seconds |
| Started | May 30 03:51:29 PM PDT 24 |
| Finished | May 30 03:51:36 PM PDT 24 |
| Peak memory | 563412 kb |
| Host | smart-56fb6e17-8b4a-419b-b696-baf6fd8853db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524973772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.3524973772 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_large_delays.3354211752 |
| Short name | T1829 |
| Test name | |
| Test status | |
| Simulation time | 7306023035 ps |
| CPU time | 79.12 seconds |
| Started | May 30 03:51:30 PM PDT 24 |
| Finished | May 30 03:52:50 PM PDT 24 |
| Peak memory | 564944 kb |
| Host | smart-3ddfd0ba-24f1-466e-840e-7f2302c4dfbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354211752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.3354211752 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.154650042 |
| Short name | T2045 |
| Test name | |
| Test status | |
| Simulation time | 4841389348 ps |
| CPU time | 82 seconds |
| Started | May 30 03:51:40 PM PDT 24 |
| Finished | May 30 03:53:03 PM PDT 24 |
| Peak memory | 564948 kb |
| Host | smart-5dac9968-7a31-493f-8db3-68afdb485ed1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154650042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.154650042 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.187192584 |
| Short name | T1799 |
| Test name | |
| Test status | |
| Simulation time | 49105521 ps |
| CPU time | 6.31 seconds |
| Started | May 30 03:51:41 PM PDT 24 |
| Finished | May 30 03:51:48 PM PDT 24 |
| Peak memory | 564804 kb |
| Host | smart-22a36eaf-82ba-4ef2-a472-bb25d36fec58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187192584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays .187192584 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all.1957932188 |
| Short name | T2724 |
| Test name | |
| Test status | |
| Simulation time | 6781741202 ps |
| CPU time | 276.95 seconds |
| Started | May 30 03:51:32 PM PDT 24 |
| Finished | May 30 03:56:11 PM PDT 24 |
| Peak memory | 573272 kb |
| Host | smart-4cdd0cd7-8a8e-4e14-ae99-ef48216d1fab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957932188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.1957932188 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_error.2167686058 |
| Short name | T1376 |
| Test name | |
| Test status | |
| Simulation time | 1825782464 ps |
| CPU time | 147.05 seconds |
| Started | May 30 03:51:35 PM PDT 24 |
| Finished | May 30 03:54:03 PM PDT 24 |
| Peak memory | 575124 kb |
| Host | smart-f4654617-2e9c-441e-93a3-7e354a199275 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167686058 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.2167686058 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.2484324132 |
| Short name | T1994 |
| Test name | |
| Test status | |
| Simulation time | 20217780229 ps |
| CPU time | 987.87 seconds |
| Started | May 30 03:51:31 PM PDT 24 |
| Finished | May 30 04:08:00 PM PDT 24 |
| Peak memory | 581452 kb |
| Host | smart-b1229953-8aee-4923-96ee-e8154b67fef8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484324132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all _with_rand_reset.2484324132 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.484516744 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 6409761645 ps |
| CPU time | 338.3 seconds |
| Started | May 30 03:51:32 PM PDT 24 |
| Finished | May 30 03:57:12 PM PDT 24 |
| Peak memory | 573156 kb |
| Host | smart-c17090b4-5c8c-41b0-9fa8-cfca274671cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484516744 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all _with_reset_error.484516744 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_unmapped_addr.560977461 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 250470647 ps |
| CPU time | 31.8 seconds |
| Started | May 30 03:51:33 PM PDT 24 |
| Finished | May 30 03:52:06 PM PDT 24 |
| Peak memory | 573064 kb |
| Host | smart-6fcbdc7f-3892-4377-aea5-6660014e6e2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560977461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.560977461 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device.3232323261 |
| Short name | T2801 |
| Test name | |
| Test status | |
| Simulation time | 25693817 ps |
| CPU time | 8.4 seconds |
| Started | May 30 03:51:40 PM PDT 24 |
| Finished | May 30 03:51:49 PM PDT 24 |
| Peak memory | 564856 kb |
| Host | smart-0fdf9a28-6655-40ad-955a-9af2926d2c07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232323261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device .3232323261 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.3556676831 |
| Short name | T2404 |
| Test name | |
| Test status | |
| Simulation time | 73753589123 ps |
| CPU time | 1305.73 seconds |
| Started | May 30 03:51:30 PM PDT 24 |
| Finished | May 30 04:13:17 PM PDT 24 |
| Peak memory | 573316 kb |
| Host | smart-2eae255c-6451-46f3-8727-06e1739c6acf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556676831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_ device_slow_rsp.3556676831 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.18804167 |
| Short name | T2695 |
| Test name | |
| Test status | |
| Simulation time | 397241741 ps |
| CPU time | 17.9 seconds |
| Started | May 30 03:51:55 PM PDT 24 |
| Finished | May 30 03:52:14 PM PDT 24 |
| Peak memory | 572892 kb |
| Host | smart-03e0a21a-e963-475f-8f82-c9e4160dc4cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18804167 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.18804167 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_random.2349071293 |
| Short name | T1490 |
| Test name | |
| Test status | |
| Simulation time | 678647895 ps |
| CPU time | 27.03 seconds |
| Started | May 30 03:51:40 PM PDT 24 |
| Finished | May 30 03:52:08 PM PDT 24 |
| Peak memory | 573964 kb |
| Host | smart-b95805fb-97c3-4c89-b1d7-c27f3ef95806 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349071293 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.2349071293 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random.3688158138 |
| Short name | T2694 |
| Test name | |
| Test status | |
| Simulation time | 216486479 ps |
| CPU time | 17.88 seconds |
| Started | May 30 03:51:38 PM PDT 24 |
| Finished | May 30 03:51:57 PM PDT 24 |
| Peak memory | 572724 kb |
| Host | smart-5b33b9a1-ef45-4d6a-8345-7d5d3921fd85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688158138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random.3688158138 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_large_delays.3373800128 |
| Short name | T1680 |
| Test name | |
| Test status | |
| Simulation time | 5229446123 ps |
| CPU time | 62.87 seconds |
| Started | May 30 03:51:33 PM PDT 24 |
| Finished | May 30 03:52:37 PM PDT 24 |
| Peak memory | 564916 kb |
| Host | smart-77e42619-fbd8-4a3c-b3cc-3347e2947018 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373800128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.3373800128 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.2326230961 |
| Short name | T1932 |
| Test name | |
| Test status | |
| Simulation time | 26775374779 ps |
| CPU time | 487.21 seconds |
| Started | May 30 03:51:31 PM PDT 24 |
| Finished | May 30 03:59:39 PM PDT 24 |
| Peak memory | 573172 kb |
| Host | smart-4762a86c-4c44-4d20-a19a-178de85c7e5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326230961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.2326230961 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.2200885913 |
| Short name | T1621 |
| Test name | |
| Test status | |
| Simulation time | 90638152 ps |
| CPU time | 10.9 seconds |
| Started | May 30 03:51:29 PM PDT 24 |
| Finished | May 30 03:51:41 PM PDT 24 |
| Peak memory | 573040 kb |
| Host | smart-0aa719fc-8b76-4b9c-ad80-e18c5a2b97ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200885913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_del ays.2200885913 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_same_source.1847379026 |
| Short name | T2366 |
| Test name | |
| Test status | |
| Simulation time | 485531212 ps |
| CPU time | 37.6 seconds |
| Started | May 30 03:51:41 PM PDT 24 |
| Finished | May 30 03:52:20 PM PDT 24 |
| Peak memory | 573060 kb |
| Host | smart-8444a5bd-129d-4963-b76c-ac53515513df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847379026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.1847379026 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke.3057954389 |
| Short name | T2073 |
| Test name | |
| Test status | |
| Simulation time | 49414653 ps |
| CPU time | 6.2 seconds |
| Started | May 30 03:51:32 PM PDT 24 |
| Finished | May 30 03:51:39 PM PDT 24 |
| Peak memory | 564812 kb |
| Host | smart-b8391d3c-3ace-4dc0-a317-734b1bdaee15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057954389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.3057954389 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.681197752 |
| Short name | T1363 |
| Test name | |
| Test status | |
| Simulation time | 8808619350 ps |
| CPU time | 94.04 seconds |
| Started | May 30 03:51:33 PM PDT 24 |
| Finished | May 30 03:53:08 PM PDT 24 |
| Peak memory | 564976 kb |
| Host | smart-3013973d-542e-42a4-9488-7672e1175de0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681197752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.681197752 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.3021942241 |
| Short name | T2007 |
| Test name | |
| Test status | |
| Simulation time | 4292945273 ps |
| CPU time | 74.71 seconds |
| Started | May 30 03:51:30 PM PDT 24 |
| Finished | May 30 03:52:46 PM PDT 24 |
| Peak memory | 564816 kb |
| Host | smart-4d891c97-96e8-4839-8fd1-76ee39ee2be8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021942241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.3021942241 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.678558468 |
| Short name | T2511 |
| Test name | |
| Test status | |
| Simulation time | 39819885 ps |
| CPU time | 6.05 seconds |
| Started | May 30 03:51:36 PM PDT 24 |
| Finished | May 30 03:51:42 PM PDT 24 |
| Peak memory | 564748 kb |
| Host | smart-65cec914-e656-439d-b260-1e938aebffd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678558468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays .678558468 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all.1972377536 |
| Short name | T2684 |
| Test name | |
| Test status | |
| Simulation time | 8558442789 ps |
| CPU time | 320.83 seconds |
| Started | May 30 03:51:41 PM PDT 24 |
| Finished | May 30 03:57:02 PM PDT 24 |
| Peak memory | 573252 kb |
| Host | smart-1812d129-a7b0-4121-9b01-dce9bc152b4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972377536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.1972377536 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.2847755616 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 2076951247 ps |
| CPU time | 77.52 seconds |
| Started | May 30 03:51:55 PM PDT 24 |
| Finished | May 30 03:53:14 PM PDT 24 |
| Peak memory | 574024 kb |
| Host | smart-1c1179e7-56c3-4b5d-85e9-f20c3f80cf72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847755616 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.2847755616 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.2402779199 |
| Short name | T2719 |
| Test name | |
| Test status | |
| Simulation time | 12625592147 ps |
| CPU time | 839.45 seconds |
| Started | May 30 03:51:42 PM PDT 24 |
| Finished | May 30 04:05:43 PM PDT 24 |
| Peak memory | 580932 kb |
| Host | smart-3cc05cac-31d7-4a0d-a0b5-7f23ee2b2960 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402779199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all _with_rand_reset.2402779199 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.2630142567 |
| Short name | T2229 |
| Test name | |
| Test status | |
| Simulation time | 7516330134 ps |
| CPU time | 250.58 seconds |
| Started | May 30 03:51:43 PM PDT 24 |
| Finished | May 30 03:55:54 PM PDT 24 |
| Peak memory | 573132 kb |
| Host | smart-6d5c198e-05be-446d-b225-88ea1c144ff9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630142567 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_al l_with_reset_error.2630142567 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_unmapped_addr.4206744984 |
| Short name | T1786 |
| Test name | |
| Test status | |
| Simulation time | 1095971322 ps |
| CPU time | 48.42 seconds |
| Started | May 30 03:51:41 PM PDT 24 |
| Finished | May 30 03:52:31 PM PDT 24 |
| Peak memory | 573068 kb |
| Host | smart-90b906a4-c042-4eea-a70c-0002fa07623a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206744984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.4206744984 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device.2645209562 |
| Short name | T2057 |
| Test name | |
| Test status | |
| Simulation time | 580948024 ps |
| CPU time | 40.08 seconds |
| Started | May 30 03:51:39 PM PDT 24 |
| Finished | May 30 03:52:20 PM PDT 24 |
| Peak memory | 573060 kb |
| Host | smart-8f7e1367-36e4-4629-8928-3bc35b4a232d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645209562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device .2645209562 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.2306613686 |
| Short name | T2393 |
| Test name | |
| Test status | |
| Simulation time | 916001520 ps |
| CPU time | 37.21 seconds |
| Started | May 30 03:51:49 PM PDT 24 |
| Finished | May 30 03:52:27 PM PDT 24 |
| Peak memory | 572908 kb |
| Host | smart-8b0b9023-66db-4bcd-8414-4dc988b15326 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306613686 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_add r.2306613686 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_random.3866619324 |
| Short name | T2495 |
| Test name | |
| Test status | |
| Simulation time | 418843134 ps |
| CPU time | 15.74 seconds |
| Started | May 30 03:51:53 PM PDT 24 |
| Finished | May 30 03:52:10 PM PDT 24 |
| Peak memory | 572924 kb |
| Host | smart-935251a0-204c-4909-9faa-be63fc9bfe70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866619324 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.3866619324 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random.3779020034 |
| Short name | T1654 |
| Test name | |
| Test status | |
| Simulation time | 250968555 ps |
| CPU time | 11.33 seconds |
| Started | May 30 03:51:40 PM PDT 24 |
| Finished | May 30 03:51:52 PM PDT 24 |
| Peak memory | 564836 kb |
| Host | smart-f6895a02-c5bb-4dcc-bf3d-58ccb9ee87a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779020034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random.3779020034 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_large_delays.2282339585 |
| Short name | T2834 |
| Test name | |
| Test status | |
| Simulation time | 21431137679 ps |
| CPU time | 250.01 seconds |
| Started | May 30 03:51:40 PM PDT 24 |
| Finished | May 30 03:55:51 PM PDT 24 |
| Peak memory | 573152 kb |
| Host | smart-81e89816-d660-462d-997f-2e4ecab77d2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282339585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.2282339585 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.1134669104 |
| Short name | T2358 |
| Test name | |
| Test status | |
| Simulation time | 55458969744 ps |
| CPU time | 870.41 seconds |
| Started | May 30 03:51:40 PM PDT 24 |
| Finished | May 30 04:06:11 PM PDT 24 |
| Peak memory | 573096 kb |
| Host | smart-b69ceb77-f2e7-4cb6-89a3-0424d2c29e5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134669104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.1134669104 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.1616578514 |
| Short name | T2763 |
| Test name | |
| Test status | |
| Simulation time | 353983393 ps |
| CPU time | 30.14 seconds |
| Started | May 30 03:51:54 PM PDT 24 |
| Finished | May 30 03:52:25 PM PDT 24 |
| Peak memory | 572968 kb |
| Host | smart-15c65705-2d87-4d49-bac5-76732b53b7e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616578514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_del ays.1616578514 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_same_source.4006696084 |
| Short name | T1619 |
| Test name | |
| Test status | |
| Simulation time | 567810220 ps |
| CPU time | 39.53 seconds |
| Started | May 30 03:51:55 PM PDT 24 |
| Finished | May 30 03:52:36 PM PDT 24 |
| Peak memory | 572940 kb |
| Host | smart-7522bb8a-d534-4f76-a427-647577574cc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006696084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.4006696084 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke.4250532047 |
| Short name | T1701 |
| Test name | |
| Test status | |
| Simulation time | 59615921 ps |
| CPU time | 6.73 seconds |
| Started | May 30 03:51:54 PM PDT 24 |
| Finished | May 30 03:52:02 PM PDT 24 |
| Peak memory | 564836 kb |
| Host | smart-0f8c862e-e0e2-4674-8a4c-09ed5941a7c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250532047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.4250532047 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_large_delays.948215633 |
| Short name | T1872 |
| Test name | |
| Test status | |
| Simulation time | 8026710575 ps |
| CPU time | 84.79 seconds |
| Started | May 30 03:51:39 PM PDT 24 |
| Finished | May 30 03:53:05 PM PDT 24 |
| Peak memory | 564964 kb |
| Host | smart-c0094280-5b03-45ed-9403-a3e646a44888 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948215633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.948215633 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.3851083910 |
| Short name | T2378 |
| Test name | |
| Test status | |
| Simulation time | 5325741684 ps |
| CPU time | 86.55 seconds |
| Started | May 30 03:51:55 PM PDT 24 |
| Finished | May 30 03:53:23 PM PDT 24 |
| Peak memory | 564956 kb |
| Host | smart-eb3b2da0-9bd2-4e5f-ac7d-1025436227f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851083910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.3851083910 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_zero_delays.114402472 |
| Short name | T2778 |
| Test name | |
| Test status | |
| Simulation time | 46035182 ps |
| CPU time | 6.45 seconds |
| Started | May 30 03:51:40 PM PDT 24 |
| Finished | May 30 03:51:47 PM PDT 24 |
| Peak memory | 563288 kb |
| Host | smart-4a5a6e94-97b6-437e-96f7-924df735dff2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114402472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays .114402472 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all.839960498 |
| Short name | T1587 |
| Test name | |
| Test status | |
| Simulation time | 1055098497 ps |
| CPU time | 96.14 seconds |
| Started | May 30 03:51:49 PM PDT 24 |
| Finished | May 30 03:53:26 PM PDT 24 |
| Peak memory | 573164 kb |
| Host | smart-9f8e3faf-ba2a-40e7-b02f-b34250aff6f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839960498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.839960498 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.4127608632 |
| Short name | T2735 |
| Test name | |
| Test status | |
| Simulation time | 4886069821 ps |
| CPU time | 388.68 seconds |
| Started | May 30 03:51:56 PM PDT 24 |
| Finished | May 30 03:58:26 PM PDT 24 |
| Peak memory | 573216 kb |
| Host | smart-4abe4c18-9c41-42b8-b155-63e61cd71acf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127608632 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.4127608632 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.1334848278 |
| Short name | T2235 |
| Test name | |
| Test status | |
| Simulation time | 151067387 ps |
| CPU time | 85.57 seconds |
| Started | May 30 03:51:56 PM PDT 24 |
| Finished | May 30 03:53:23 PM PDT 24 |
| Peak memory | 573152 kb |
| Host | smart-fa4ef0e7-c061-4ede-bc2f-20e522b21c2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334848278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all _with_rand_reset.1334848278 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_unmapped_addr.189935309 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 955405787 ps |
| CPU time | 41.65 seconds |
| Started | May 30 03:51:53 PM PDT 24 |
| Finished | May 30 03:52:35 PM PDT 24 |
| Peak memory | 573128 kb |
| Host | smart-62d231d9-a380-4535-a34f-4847fe464d10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189935309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.189935309 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device.2277636838 |
| Short name | T2276 |
| Test name | |
| Test status | |
| Simulation time | 339567708 ps |
| CPU time | 17.62 seconds |
| Started | May 30 03:51:50 PM PDT 24 |
| Finished | May 30 03:52:08 PM PDT 24 |
| Peak memory | 572916 kb |
| Host | smart-b8037ae1-1100-4455-b6c5-305b255035b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277636838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device .2277636838 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.4205776218 |
| Short name | T1665 |
| Test name | |
| Test status | |
| Simulation time | 96899288858 ps |
| CPU time | 1679.72 seconds |
| Started | May 30 03:51:50 PM PDT 24 |
| Finished | May 30 04:19:51 PM PDT 24 |
| Peak memory | 573240 kb |
| Host | smart-1c12216c-9b34-45c1-ad36-454b8e48f70f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205776218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_ device_slow_rsp.4205776218 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.3739946568 |
| Short name | T2383 |
| Test name | |
| Test status | |
| Simulation time | 410423316 ps |
| CPU time | 18.46 seconds |
| Started | May 30 03:51:50 PM PDT 24 |
| Finished | May 30 03:52:09 PM PDT 24 |
| Peak memory | 572904 kb |
| Host | smart-6791efda-3fb6-4df7-9a19-33773954ad8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739946568 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_add r.3739946568 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_random.489818039 |
| Short name | T2323 |
| Test name | |
| Test status | |
| Simulation time | 823773681 ps |
| CPU time | 30.17 seconds |
| Started | May 30 03:51:46 PM PDT 24 |
| Finished | May 30 03:52:17 PM PDT 24 |
| Peak memory | 572940 kb |
| Host | smart-e7506e5f-e765-40a4-9464-72f112e1de3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489818039 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.489818039 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random.3259035020 |
| Short name | T1475 |
| Test name | |
| Test status | |
| Simulation time | 313769370 ps |
| CPU time | 15.4 seconds |
| Started | May 30 03:51:47 PM PDT 24 |
| Finished | May 30 03:52:04 PM PDT 24 |
| Peak memory | 564868 kb |
| Host | smart-021e1ada-319f-45e0-915c-d2269da2eb15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259035020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random.3259035020 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_large_delays.3456436705 |
| Short name | T2368 |
| Test name | |
| Test status | |
| Simulation time | 19942375373 ps |
| CPU time | 214.15 seconds |
| Started | May 30 03:51:54 PM PDT 24 |
| Finished | May 30 03:55:30 PM PDT 24 |
| Peak memory | 573180 kb |
| Host | smart-2e5987f8-67e6-4a3b-99bb-f787473f8be4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456436705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.3456436705 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_slow_rsp.3818375861 |
| Short name | T2255 |
| Test name | |
| Test status | |
| Simulation time | 21089110571 ps |
| CPU time | 350.83 seconds |
| Started | May 30 03:51:52 PM PDT 24 |
| Finished | May 30 03:57:43 PM PDT 24 |
| Peak memory | 573176 kb |
| Host | smart-3869826c-cbc1-4efb-bb99-0e0bf820d0f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818375861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.3818375861 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_zero_delays.292032452 |
| Short name | T1902 |
| Test name | |
| Test status | |
| Simulation time | 545914919 ps |
| CPU time | 47.8 seconds |
| Started | May 30 03:51:48 PM PDT 24 |
| Finished | May 30 03:52:37 PM PDT 24 |
| Peak memory | 572588 kb |
| Host | smart-db23e222-08c7-45a5-94ec-2b2b4e73fb3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292032452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_dela ys.292032452 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_same_source.4207313714 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 529644421 ps |
| CPU time | 36.6 seconds |
| Started | May 30 03:51:50 PM PDT 24 |
| Finished | May 30 03:52:28 PM PDT 24 |
| Peak memory | 572988 kb |
| Host | smart-d954a1bc-9baa-441b-95bc-b5908b168f48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207313714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.4207313714 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke.2591099796 |
| Short name | T2076 |
| Test name | |
| Test status | |
| Simulation time | 231091376 ps |
| CPU time | 9.37 seconds |
| Started | May 30 03:51:45 PM PDT 24 |
| Finished | May 30 03:51:56 PM PDT 24 |
| Peak memory | 563384 kb |
| Host | smart-b843e25c-4403-4489-b8e4-f4d29696f7ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591099796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.2591099796 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_large_delays.1747815880 |
| Short name | T1648 |
| Test name | |
| Test status | |
| Simulation time | 7060401880 ps |
| CPU time | 81.34 seconds |
| Started | May 30 03:51:50 PM PDT 24 |
| Finished | May 30 03:53:12 PM PDT 24 |
| Peak memory | 563464 kb |
| Host | smart-b6efec00-1c47-4825-ad4c-878d5933dc2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747815880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.1747815880 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.3469912503 |
| Short name | T2121 |
| Test name | |
| Test status | |
| Simulation time | 5956853317 ps |
| CPU time | 103.11 seconds |
| Started | May 30 03:51:56 PM PDT 24 |
| Finished | May 30 03:53:40 PM PDT 24 |
| Peak memory | 563544 kb |
| Host | smart-4b8b4ec3-3569-4707-9753-f53b23ae16f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469912503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.3469912503 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_zero_delays.3036011801 |
| Short name | T2577 |
| Test name | |
| Test status | |
| Simulation time | 43972568 ps |
| CPU time | 6.58 seconds |
| Started | May 30 03:51:52 PM PDT 24 |
| Finished | May 30 03:51:59 PM PDT 24 |
| Peak memory | 564776 kb |
| Host | smart-48acdc59-1536-4978-b528-b2c0f8dd728a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036011801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delay s.3036011801 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all.3698131898 |
| Short name | T2071 |
| Test name | |
| Test status | |
| Simulation time | 756870294 ps |
| CPU time | 30.87 seconds |
| Started | May 30 03:51:51 PM PDT 24 |
| Finished | May 30 03:52:23 PM PDT 24 |
| Peak memory | 573104 kb |
| Host | smart-97ed83c6-8a56-449b-930e-074c9c730ea5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698131898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.3698131898 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.1107716494 |
| Short name | T2868 |
| Test name | |
| Test status | |
| Simulation time | 2769493755 ps |
| CPU time | 198.9 seconds |
| Started | May 30 03:52:02 PM PDT 24 |
| Finished | May 30 03:55:21 PM PDT 24 |
| Peak memory | 573068 kb |
| Host | smart-5f384319-90fc-46c8-a224-179e70a3fa31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107716494 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.1107716494 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.941409459 |
| Short name | T1987 |
| Test name | |
| Test status | |
| Simulation time | 70773660 ps |
| CPU time | 25.01 seconds |
| Started | May 30 03:52:01 PM PDT 24 |
| Finished | May 30 03:52:27 PM PDT 24 |
| Peak memory | 564944 kb |
| Host | smart-df18fb9a-ef3a-4b4d-8b3d-0c2f65f96435 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941409459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_ with_rand_reset.941409459 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.242831285 |
| Short name | T1397 |
| Test name | |
| Test status | |
| Simulation time | 84070686 ps |
| CPU time | 12.68 seconds |
| Started | May 30 03:52:02 PM PDT 24 |
| Finished | May 30 03:52:16 PM PDT 24 |
| Peak memory | 573076 kb |
| Host | smart-f38f937b-7cd0-4e3e-a09e-e227ba42d752 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242831285 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all _with_reset_error.242831285 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_unmapped_addr.292379876 |
| Short name | T2602 |
| Test name | |
| Test status | |
| Simulation time | 52195289 ps |
| CPU time | 8.79 seconds |
| Started | May 30 03:51:48 PM PDT 24 |
| Finished | May 30 03:51:58 PM PDT 24 |
| Peak memory | 564896 kb |
| Host | smart-61e77591-4d41-4fff-bb95-d30d4513d5f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292379876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.292379876 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device.2805202343 |
| Short name | T1980 |
| Test name | |
| Test status | |
| Simulation time | 833538776 ps |
| CPU time | 70.59 seconds |
| Started | May 30 03:52:04 PM PDT 24 |
| Finished | May 30 03:53:16 PM PDT 24 |
| Peak memory | 573064 kb |
| Host | smart-0eb320cd-ee0a-46f6-a85b-8ba9cd62becf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805202343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device .2805202343 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.2556919042 |
| Short name | T1735 |
| Test name | |
| Test status | |
| Simulation time | 2969856633 ps |
| CPU time | 55.29 seconds |
| Started | May 30 03:52:03 PM PDT 24 |
| Finished | May 30 03:52:59 PM PDT 24 |
| Peak memory | 564928 kb |
| Host | smart-13359d8f-d147-45b5-86ff-737d16890daa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556919042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_ device_slow_rsp.2556919042 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.927382913 |
| Short name | T1911 |
| Test name | |
| Test status | |
| Simulation time | 1371952167 ps |
| CPU time | 50.68 seconds |
| Started | May 30 03:52:00 PM PDT 24 |
| Finished | May 30 03:52:51 PM PDT 24 |
| Peak memory | 572896 kb |
| Host | smart-b297db91-eef8-4086-8f42-d1ccbd526c0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927382913 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr .927382913 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_random.2492332158 |
| Short name | T1411 |
| Test name | |
| Test status | |
| Simulation time | 266473758 ps |
| CPU time | 11.74 seconds |
| Started | May 30 03:52:01 PM PDT 24 |
| Finished | May 30 03:52:14 PM PDT 24 |
| Peak memory | 564612 kb |
| Host | smart-38fa8fce-18e6-4d1a-90f1-1fbc7ea89fe6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492332158 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.2492332158 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random.4164236849 |
| Short name | T1470 |
| Test name | |
| Test status | |
| Simulation time | 29950728 ps |
| CPU time | 5.51 seconds |
| Started | May 30 03:52:02 PM PDT 24 |
| Finished | May 30 03:52:08 PM PDT 24 |
| Peak memory | 564864 kb |
| Host | smart-8621b2f7-1c5a-477c-b690-304cb16826c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164236849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random.4164236849 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_large_delays.3079579026 |
| Short name | T2063 |
| Test name | |
| Test status | |
| Simulation time | 54849717519 ps |
| CPU time | 593.02 seconds |
| Started | May 30 03:52:04 PM PDT 24 |
| Finished | May 30 04:01:57 PM PDT 24 |
| Peak memory | 573180 kb |
| Host | smart-cb78cf00-c6ad-4076-917d-c31acc490d07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079579026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.3079579026 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_slow_rsp.400499377 |
| Short name | T2313 |
| Test name | |
| Test status | |
| Simulation time | 36954766633 ps |
| CPU time | 643.54 seconds |
| Started | May 30 03:52:04 PM PDT 24 |
| Finished | May 30 04:02:49 PM PDT 24 |
| Peak memory | 573168 kb |
| Host | smart-204b5c9d-682c-499a-afa4-1b043caf8404 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400499377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.400499377 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_zero_delays.989893156 |
| Short name | T1603 |
| Test name | |
| Test status | |
| Simulation time | 142752852 ps |
| CPU time | 16 seconds |
| Started | May 30 03:52:05 PM PDT 24 |
| Finished | May 30 03:52:21 PM PDT 24 |
| Peak memory | 573020 kb |
| Host | smart-c1373652-81ee-4bb2-bd07-fbb6c07b4606 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989893156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_dela ys.989893156 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_same_source.1067410575 |
| Short name | T1424 |
| Test name | |
| Test status | |
| Simulation time | 334347396 ps |
| CPU time | 23.47 seconds |
| Started | May 30 03:52:00 PM PDT 24 |
| Finished | May 30 03:52:24 PM PDT 24 |
| Peak memory | 573044 kb |
| Host | smart-4ca2e674-2aa9-43dc-9135-826d5358164b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067410575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.1067410575 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke.217142320 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 39463802 ps |
| CPU time | 6.26 seconds |
| Started | May 30 03:52:02 PM PDT 24 |
| Finished | May 30 03:52:10 PM PDT 24 |
| Peak memory | 564864 kb |
| Host | smart-65691de7-d6e1-469c-81d7-bf105e14b8ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217142320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.217142320 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_large_delays.19046038 |
| Short name | T1589 |
| Test name | |
| Test status | |
| Simulation time | 9062933879 ps |
| CPU time | 96.45 seconds |
| Started | May 30 03:52:02 PM PDT 24 |
| Finished | May 30 03:53:39 PM PDT 24 |
| Peak memory | 564948 kb |
| Host | smart-4dee9daa-2fc8-4eb1-8add-f766fa82c5a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19046038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.19046038 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.2243514198 |
| Short name | T1346 |
| Test name | |
| Test status | |
| Simulation time | 4600158569 ps |
| CPU time | 75.97 seconds |
| Started | May 30 03:52:05 PM PDT 24 |
| Finished | May 30 03:53:22 PM PDT 24 |
| Peak memory | 563536 kb |
| Host | smart-5f63e532-a3b3-4549-aadc-b8a6eaa13d9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243514198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.2243514198 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.3903164133 |
| Short name | T2093 |
| Test name | |
| Test status | |
| Simulation time | 43077073 ps |
| CPU time | 6.54 seconds |
| Started | May 30 03:52:05 PM PDT 24 |
| Finished | May 30 03:52:13 PM PDT 24 |
| Peak memory | 563316 kb |
| Host | smart-3b990cba-756b-4942-8c06-734b7d8b1234 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903164133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delay s.3903164133 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all.1480463420 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 2419990558 ps |
| CPU time | 220.8 seconds |
| Started | May 30 03:52:02 PM PDT 24 |
| Finished | May 30 03:55:43 PM PDT 24 |
| Peak memory | 573220 kb |
| Host | smart-8b223681-41bd-4e26-b739-c953976f64f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480463420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.1480463420 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.2782384719 |
| Short name | T1556 |
| Test name | |
| Test status | |
| Simulation time | 10500298881 ps |
| CPU time | 372.48 seconds |
| Started | May 30 03:52:02 PM PDT 24 |
| Finished | May 30 03:58:16 PM PDT 24 |
| Peak memory | 573232 kb |
| Host | smart-c89fb21a-7d8f-48dc-a6a1-bdf004b14fb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782384719 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.2782384719 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.152410466 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 167544217 ps |
| CPU time | 64.71 seconds |
| Started | May 30 03:52:01 PM PDT 24 |
| Finished | May 30 03:53:06 PM PDT 24 |
| Peak memory | 573140 kb |
| Host | smart-16b84dd8-c0ae-412c-8c97-6b5788e014cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152410466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_ with_rand_reset.152410466 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.1657358580 |
| Short name | T2599 |
| Test name | |
| Test status | |
| Simulation time | 99128279 ps |
| CPU time | 35.04 seconds |
| Started | May 30 03:52:01 PM PDT 24 |
| Finished | May 30 03:52:37 PM PDT 24 |
| Peak memory | 564856 kb |
| Host | smart-f7015b3e-bf6b-405c-9b23-c9ab80c1faac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657358580 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_al l_with_reset_error.1657358580 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_unmapped_addr.2472156098 |
| Short name | T1763 |
| Test name | |
| Test status | |
| Simulation time | 109171070 ps |
| CPU time | 14.67 seconds |
| Started | May 30 03:52:01 PM PDT 24 |
| Finished | May 30 03:52:17 PM PDT 24 |
| Peak memory | 573036 kb |
| Host | smart-ceea08e3-0d5e-4e84-acd6-316d11c95223 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472156098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.2472156098 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device.3017270772 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 1220892809 ps |
| CPU time | 60.55 seconds |
| Started | May 30 03:52:13 PM PDT 24 |
| Finished | May 30 03:53:15 PM PDT 24 |
| Peak memory | 572888 kb |
| Host | smart-aef8aa84-6c3a-42f8-93e2-08251cbb108e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017270772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device .3017270772 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.3672850390 |
| Short name | T2320 |
| Test name | |
| Test status | |
| Simulation time | 1025874590 ps |
| CPU time | 42.4 seconds |
| Started | May 30 03:52:14 PM PDT 24 |
| Finished | May 30 03:52:58 PM PDT 24 |
| Peak memory | 572952 kb |
| Host | smart-8e394be6-f4a8-4763-bef2-7188ab8a68d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672850390 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_add r.3672850390 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_random.4292305717 |
| Short name | T1925 |
| Test name | |
| Test status | |
| Simulation time | 444838651 ps |
| CPU time | 43.5 seconds |
| Started | May 30 03:52:17 PM PDT 24 |
| Finished | May 30 03:53:02 PM PDT 24 |
| Peak memory | 572920 kb |
| Host | smart-22b0759d-00fd-48a0-ac1a-14303ba684e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292305717 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.4292305717 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random.3347971377 |
| Short name | T1943 |
| Test name | |
| Test status | |
| Simulation time | 1351473163 ps |
| CPU time | 46.04 seconds |
| Started | May 30 03:52:23 PM PDT 24 |
| Finished | May 30 03:53:11 PM PDT 24 |
| Peak memory | 572984 kb |
| Host | smart-6138316a-3e7b-403d-b1a4-a083c8ac9bf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347971377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random.3347971377 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_large_delays.3495712 |
| Short name | T2113 |
| Test name | |
| Test status | |
| Simulation time | 109073991664 ps |
| CPU time | 1284.59 seconds |
| Started | May 30 03:52:20 PM PDT 24 |
| Finished | May 30 04:13:46 PM PDT 24 |
| Peak memory | 573192 kb |
| Host | smart-0d235c68-36db-428a-a2fc-2333929d428e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.3495712 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.2521026538 |
| Short name | T1890 |
| Test name | |
| Test status | |
| Simulation time | 66438859730 ps |
| CPU time | 1279.99 seconds |
| Started | May 30 03:52:15 PM PDT 24 |
| Finished | May 30 04:13:37 PM PDT 24 |
| Peak memory | 573216 kb |
| Host | smart-f178985e-ebd2-4df2-9688-398123236ce7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521026538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.2521026538 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.356586359 |
| Short name | T2553 |
| Test name | |
| Test status | |
| Simulation time | 70401003 ps |
| CPU time | 8.78 seconds |
| Started | May 30 03:52:16 PM PDT 24 |
| Finished | May 30 03:52:26 PM PDT 24 |
| Peak memory | 564812 kb |
| Host | smart-2162e43b-a6bb-4f0e-a2b9-5312eda59720 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356586359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_dela ys.356586359 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_same_source.4134409596 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 1916546587 ps |
| CPU time | 58.78 seconds |
| Started | May 30 03:52:12 PM PDT 24 |
| Finished | May 30 03:53:13 PM PDT 24 |
| Peak memory | 573052 kb |
| Host | smart-d62431a5-0fdf-498e-8b7f-f78fcc1ace26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134409596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.4134409596 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke.3367301232 |
| Short name | T1853 |
| Test name | |
| Test status | |
| Simulation time | 204940381 ps |
| CPU time | 8.93 seconds |
| Started | May 30 03:52:01 PM PDT 24 |
| Finished | May 30 03:52:11 PM PDT 24 |
| Peak memory | 564828 kb |
| Host | smart-65821b21-573a-4109-8500-69da3d6834bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367301232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.3367301232 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_large_delays.1485152579 |
| Short name | T2254 |
| Test name | |
| Test status | |
| Simulation time | 9131707281 ps |
| CPU time | 97.77 seconds |
| Started | May 30 03:52:02 PM PDT 24 |
| Finished | May 30 03:53:40 PM PDT 24 |
| Peak memory | 564972 kb |
| Host | smart-efab9ba5-702a-4e06-8207-05ab03bebbc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485152579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.1485152579 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.981528905 |
| Short name | T2566 |
| Test name | |
| Test status | |
| Simulation time | 5918628828 ps |
| CPU time | 95.47 seconds |
| Started | May 30 03:52:02 PM PDT 24 |
| Finished | May 30 03:53:39 PM PDT 24 |
| Peak memory | 564940 kb |
| Host | smart-1579639c-ea73-4385-bbc8-584a943c9b52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981528905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.981528905 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_zero_delays.3546247420 |
| Short name | T2432 |
| Test name | |
| Test status | |
| Simulation time | 53418572 ps |
| CPU time | 7.03 seconds |
| Started | May 30 03:52:01 PM PDT 24 |
| Finished | May 30 03:52:09 PM PDT 24 |
| Peak memory | 564796 kb |
| Host | smart-3bd8155f-ce6b-4fee-bffc-3dc692f94c26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546247420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delay s.3546247420 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all.3869365550 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 1972002314 ps |
| CPU time | 164.46 seconds |
| Started | May 30 03:52:15 PM PDT 24 |
| Finished | May 30 03:55:01 PM PDT 24 |
| Peak memory | 573112 kb |
| Host | smart-3aab6783-6b00-4959-8cd5-35306140f022 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869365550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.3869365550 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_error.3408086372 |
| Short name | T1862 |
| Test name | |
| Test status | |
| Simulation time | 1797913478 ps |
| CPU time | 135.04 seconds |
| Started | May 30 03:52:13 PM PDT 24 |
| Finished | May 30 03:54:30 PM PDT 24 |
| Peak memory | 573124 kb |
| Host | smart-cbe7bd8a-0fd7-49de-8c6f-66642878ab58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408086372 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.3408086372 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.773046640 |
| Short name | T2439 |
| Test name | |
| Test status | |
| Simulation time | 92975366 ps |
| CPU time | 43.3 seconds |
| Started | May 30 03:52:14 PM PDT 24 |
| Finished | May 30 03:52:59 PM PDT 24 |
| Peak memory | 564960 kb |
| Host | smart-450bfd64-1363-4746-b0de-1ce22b32df8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773046640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_ with_rand_reset.773046640 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.3833722748 |
| Short name | T1506 |
| Test name | |
| Test status | |
| Simulation time | 14168599375 ps |
| CPU time | 550.17 seconds |
| Started | May 30 03:52:15 PM PDT 24 |
| Finished | May 30 04:01:26 PM PDT 24 |
| Peak memory | 578020 kb |
| Host | smart-bf809052-a179-41de-8480-3728a8e4b374 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833722748 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_al l_with_reset_error.3833722748 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_unmapped_addr.1339402239 |
| Short name | T2003 |
| Test name | |
| Test status | |
| Simulation time | 1196825302 ps |
| CPU time | 48.96 seconds |
| Started | May 30 03:52:17 PM PDT 24 |
| Finished | May 30 03:53:07 PM PDT 24 |
| Peak memory | 573048 kb |
| Host | smart-0162899c-7da2-4935-963e-e3be6dd23f1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339402239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.1339402239 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device.2941972125 |
| Short name | T2647 |
| Test name | |
| Test status | |
| Simulation time | 881621209 ps |
| CPU time | 65.4 seconds |
| Started | May 30 03:52:12 PM PDT 24 |
| Finished | May 30 03:53:19 PM PDT 24 |
| Peak memory | 573008 kb |
| Host | smart-762039d8-31b5-4c7b-955d-e9e19c7f2c0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941972125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device .2941972125 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.2745762663 |
| Short name | T2470 |
| Test name | |
| Test status | |
| Simulation time | 119485743311 ps |
| CPU time | 2206.01 seconds |
| Started | May 30 03:52:23 PM PDT 24 |
| Finished | May 30 04:29:11 PM PDT 24 |
| Peak memory | 573344 kb |
| Host | smart-f0c4d9aa-47e5-4a3d-b878-186ce3160e76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745762663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_ device_slow_rsp.2745762663 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.4114536849 |
| Short name | T1595 |
| Test name | |
| Test status | |
| Simulation time | 279897923 ps |
| CPU time | 13.25 seconds |
| Started | May 30 03:52:17 PM PDT 24 |
| Finished | May 30 03:52:31 PM PDT 24 |
| Peak memory | 572864 kb |
| Host | smart-7e819da0-6260-4258-8cfb-0160f906c79e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114536849 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_add r.4114536849 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_random.2146102234 |
| Short name | T1915 |
| Test name | |
| Test status | |
| Simulation time | 1750898703 ps |
| CPU time | 55.33 seconds |
| Started | May 30 03:52:14 PM PDT 24 |
| Finished | May 30 03:53:11 PM PDT 24 |
| Peak memory | 572908 kb |
| Host | smart-6a231932-4ab9-4fbe-92a6-8f95d161004e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146102234 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.2146102234 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random.590128754 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 229531802 ps |
| CPU time | 24.89 seconds |
| Started | May 30 03:52:15 PM PDT 24 |
| Finished | May 30 03:52:41 PM PDT 24 |
| Peak memory | 573060 kb |
| Host | smart-8111bf0f-056d-4c50-967d-6c846807fd43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590128754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random.590128754 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_large_delays.2811366767 |
| Short name | T1825 |
| Test name | |
| Test status | |
| Simulation time | 34209018558 ps |
| CPU time | 367.2 seconds |
| Started | May 30 03:52:20 PM PDT 24 |
| Finished | May 30 03:58:28 PM PDT 24 |
| Peak memory | 573168 kb |
| Host | smart-b6eda602-a942-426d-a83d-6d564ce107f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811366767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.2811366767 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_slow_rsp.2303533742 |
| Short name | T2429 |
| Test name | |
| Test status | |
| Simulation time | 59074982978 ps |
| CPU time | 1072.06 seconds |
| Started | May 30 03:52:21 PM PDT 24 |
| Finished | May 30 04:10:14 PM PDT 24 |
| Peak memory | 573172 kb |
| Host | smart-fcd19c4e-f650-4ff8-886c-7837e7fd7299 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303533742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.2303533742 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.2235328758 |
| Short name | T1739 |
| Test name | |
| Test status | |
| Simulation time | 402068871 ps |
| CPU time | 36.86 seconds |
| Started | May 30 03:52:22 PM PDT 24 |
| Finished | May 30 03:53:00 PM PDT 24 |
| Peak memory | 573028 kb |
| Host | smart-f7461338-0a1c-4a38-9397-928769a0bf98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235328758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_del ays.2235328758 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_same_source.3859597662 |
| Short name | T1522 |
| Test name | |
| Test status | |
| Simulation time | 132928546 ps |
| CPU time | 11.38 seconds |
| Started | May 30 03:52:13 PM PDT 24 |
| Finished | May 30 03:52:26 PM PDT 24 |
| Peak memory | 573020 kb |
| Host | smart-e6c3d120-8a0f-48cd-8fe9-f6428a9bd5e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859597662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.3859597662 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke.3564058221 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 199023029 ps |
| CPU time | 9.41 seconds |
| Started | May 30 03:52:14 PM PDT 24 |
| Finished | May 30 03:52:25 PM PDT 24 |
| Peak memory | 564884 kb |
| Host | smart-84c33ab7-e687-4500-a71c-77c90edcc4e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564058221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.3564058221 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_large_delays.2734253884 |
| Short name | T2685 |
| Test name | |
| Test status | |
| Simulation time | 8182554992 ps |
| CPU time | 94.34 seconds |
| Started | May 30 03:52:16 PM PDT 24 |
| Finished | May 30 03:53:52 PM PDT 24 |
| Peak memory | 564956 kb |
| Host | smart-889135ac-e90f-4072-9759-c5242ff6c1ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734253884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.2734253884 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.2192046867 |
| Short name | T1844 |
| Test name | |
| Test status | |
| Simulation time | 4334849268 ps |
| CPU time | 74.99 seconds |
| Started | May 30 03:52:14 PM PDT 24 |
| Finished | May 30 03:53:30 PM PDT 24 |
| Peak memory | 564888 kb |
| Host | smart-f8588dd7-33ba-45b5-b453-02f88f033744 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192046867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.2192046867 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_zero_delays.1929554511 |
| Short name | T1835 |
| Test name | |
| Test status | |
| Simulation time | 47072766 ps |
| CPU time | 6.22 seconds |
| Started | May 30 03:52:13 PM PDT 24 |
| Finished | May 30 03:52:21 PM PDT 24 |
| Peak memory | 564820 kb |
| Host | smart-d0f1fa82-67e4-491a-a85e-d0fed9961d72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929554511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delay s.1929554511 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all.2261589251 |
| Short name | T2688 |
| Test name | |
| Test status | |
| Simulation time | 568202069 ps |
| CPU time | 23.33 seconds |
| Started | May 30 03:52:15 PM PDT 24 |
| Finished | May 30 03:52:40 PM PDT 24 |
| Peak memory | 573056 kb |
| Host | smart-f9f24219-f46f-4a16-a865-0a7d68eae4ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261589251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.2261589251 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.705681792 |
| Short name | T1403 |
| Test name | |
| Test status | |
| Simulation time | 8841270315 ps |
| CPU time | 330.11 seconds |
| Started | May 30 03:52:12 PM PDT 24 |
| Finished | May 30 03:57:43 PM PDT 24 |
| Peak memory | 573204 kb |
| Host | smart-2550de66-1efc-463e-8917-472df929e3b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705681792 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.705681792 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.1613448223 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 4606907562 ps |
| CPU time | 396.9 seconds |
| Started | May 30 03:52:12 PM PDT 24 |
| Finished | May 30 03:58:51 PM PDT 24 |
| Peak memory | 573184 kb |
| Host | smart-a594be8e-7a42-44e1-8fd0-f50940141637 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613448223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all _with_rand_reset.1613448223 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.847874850 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 1248483302 ps |
| CPU time | 196.53 seconds |
| Started | May 30 03:52:12 PM PDT 24 |
| Finished | May 30 03:55:30 PM PDT 24 |
| Peak memory | 573072 kb |
| Host | smart-ee6a2d09-8776-4b1f-90bb-2834bdc05be6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847874850 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all _with_reset_error.847874850 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_unmapped_addr.1452587345 |
| Short name | T2674 |
| Test name | |
| Test status | |
| Simulation time | 99801168 ps |
| CPU time | 7.2 seconds |
| Started | May 30 03:52:16 PM PDT 24 |
| Finished | May 30 03:52:24 PM PDT 24 |
| Peak memory | 564868 kb |
| Host | smart-fa8e3d1d-8600-4962-88bc-469ac05607c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452587345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.1452587345 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device.1148169973 |
| Short name | T1923 |
| Test name | |
| Test status | |
| Simulation time | 300829249 ps |
| CPU time | 32.42 seconds |
| Started | May 30 03:52:26 PM PDT 24 |
| Finished | May 30 03:53:00 PM PDT 24 |
| Peak memory | 573080 kb |
| Host | smart-696f0572-02f0-4bee-a971-56fc035fae74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148169973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device .1148169973 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.3296106507 |
| Short name | T2667 |
| Test name | |
| Test status | |
| Simulation time | 152936986583 ps |
| CPU time | 2879.07 seconds |
| Started | May 30 03:52:26 PM PDT 24 |
| Finished | May 30 04:40:27 PM PDT 24 |
| Peak memory | 573304 kb |
| Host | smart-827bce81-690e-4d4f-a8bf-a87a55831055 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296106507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_ device_slow_rsp.3296106507 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.3180940128 |
| Short name | T2219 |
| Test name | |
| Test status | |
| Simulation time | 154757759 ps |
| CPU time | 16.67 seconds |
| Started | May 30 03:52:31 PM PDT 24 |
| Finished | May 30 03:52:48 PM PDT 24 |
| Peak memory | 572884 kb |
| Host | smart-4111384a-e04c-487a-81ea-7ac1b73a66ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180940128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_add r.3180940128 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_random.3344865671 |
| Short name | T2360 |
| Test name | |
| Test status | |
| Simulation time | 1616215283 ps |
| CPU time | 48.49 seconds |
| Started | May 30 03:52:25 PM PDT 24 |
| Finished | May 30 03:53:15 PM PDT 24 |
| Peak memory | 572860 kb |
| Host | smart-22def2bc-26b4-421b-8455-d2f118f3b00a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344865671 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.3344865671 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random.782233789 |
| Short name | T2198 |
| Test name | |
| Test status | |
| Simulation time | 1606279643 ps |
| CPU time | 67.85 seconds |
| Started | May 30 03:52:26 PM PDT 24 |
| Finished | May 30 03:53:35 PM PDT 24 |
| Peak memory | 573044 kb |
| Host | smart-f6a30032-2409-47c2-8a3f-1a9f9ee17bb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782233789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random.782233789 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_large_delays.2349579675 |
| Short name | T2849 |
| Test name | |
| Test status | |
| Simulation time | 21759866627 ps |
| CPU time | 223.03 seconds |
| Started | May 30 03:52:24 PM PDT 24 |
| Finished | May 30 03:56:11 PM PDT 24 |
| Peak memory | 573180 kb |
| Host | smart-ba1a4e09-0f5e-4db1-96f8-9a655d8f16b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349579675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.2349579675 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.2970453864 |
| Short name | T2014 |
| Test name | |
| Test status | |
| Simulation time | 12412577305 ps |
| CPU time | 222.51 seconds |
| Started | May 30 03:52:29 PM PDT 24 |
| Finished | May 30 03:56:13 PM PDT 24 |
| Peak memory | 573200 kb |
| Host | smart-7c5bb76c-22b3-47e8-ba16-acff4363056a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970453864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.2970453864 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.2281751699 |
| Short name | T1768 |
| Test name | |
| Test status | |
| Simulation time | 489739710 ps |
| CPU time | 42.55 seconds |
| Started | May 30 03:52:28 PM PDT 24 |
| Finished | May 30 03:53:12 PM PDT 24 |
| Peak memory | 573060 kb |
| Host | smart-663e8089-03be-4a21-9042-530badf62d5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281751699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_del ays.2281751699 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_same_source.1764589527 |
| Short name | T2128 |
| Test name | |
| Test status | |
| Simulation time | 2153674685 ps |
| CPU time | 68.98 seconds |
| Started | May 30 03:52:26 PM PDT 24 |
| Finished | May 30 03:53:37 PM PDT 24 |
| Peak memory | 573012 kb |
| Host | smart-5895cb8d-9ec1-4d1b-aa31-ff4a6bfd75dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764589527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.1764589527 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke.171843313 |
| Short name | T1485 |
| Test name | |
| Test status | |
| Simulation time | 51470580 ps |
| CPU time | 6.49 seconds |
| Started | May 30 03:52:15 PM PDT 24 |
| Finished | May 30 03:52:22 PM PDT 24 |
| Peak memory | 563400 kb |
| Host | smart-5704ac79-53d7-44c9-a197-f408e26577f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171843313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.171843313 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_large_delays.36276279 |
| Short name | T2654 |
| Test name | |
| Test status | |
| Simulation time | 6047928312 ps |
| CPU time | 69.77 seconds |
| Started | May 30 03:52:28 PM PDT 24 |
| Finished | May 30 03:53:39 PM PDT 24 |
| Peak memory | 562868 kb |
| Host | smart-1febd20f-17d1-45e7-9036-61c26557abe8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36276279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.36276279 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.3348226038 |
| Short name | T2409 |
| Test name | |
| Test status | |
| Simulation time | 6011795180 ps |
| CPU time | 101.55 seconds |
| Started | May 30 03:52:25 PM PDT 24 |
| Finished | May 30 03:54:08 PM PDT 24 |
| Peak memory | 563500 kb |
| Host | smart-62e75dba-01c1-4815-8e96-58685cc378a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348226038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.3348226038 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.1493475389 |
| Short name | T2749 |
| Test name | |
| Test status | |
| Simulation time | 44282593 ps |
| CPU time | 5.84 seconds |
| Started | May 30 03:52:25 PM PDT 24 |
| Finished | May 30 03:52:32 PM PDT 24 |
| Peak memory | 563352 kb |
| Host | smart-952ad749-96f4-4d4d-be94-d5dd960e3ccd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493475389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delay s.1493475389 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all.613976823 |
| Short name | T2842 |
| Test name | |
| Test status | |
| Simulation time | 3629813142 ps |
| CPU time | 306 seconds |
| Started | May 30 03:52:25 PM PDT 24 |
| Finished | May 30 03:57:33 PM PDT 24 |
| Peak memory | 573232 kb |
| Host | smart-50223c4d-f362-43d4-be32-c6f9f2f37f1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613976823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.613976823 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.2380107267 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 4347915570 ps |
| CPU time | 169.33 seconds |
| Started | May 30 03:52:28 PM PDT 24 |
| Finished | May 30 03:55:19 PM PDT 24 |
| Peak memory | 573032 kb |
| Host | smart-a8172c0a-63ff-41ea-98f3-a27c130d7be3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380107267 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.2380107267 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.4267066983 |
| Short name | T1914 |
| Test name | |
| Test status | |
| Simulation time | 97469411 ps |
| CPU time | 55.27 seconds |
| Started | May 30 03:52:28 PM PDT 24 |
| Finished | May 30 03:53:24 PM PDT 24 |
| Peak memory | 572548 kb |
| Host | smart-1c2b4c5a-b6b8-43e4-a5b0-b59c4d6ae088 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267066983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all _with_rand_reset.4267066983 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.2242777621 |
| Short name | T1959 |
| Test name | |
| Test status | |
| Simulation time | 1043831488 ps |
| CPU time | 80.58 seconds |
| Started | May 30 03:52:25 PM PDT 24 |
| Finished | May 30 03:53:48 PM PDT 24 |
| Peak memory | 573120 kb |
| Host | smart-ba8965f6-715e-4fa3-b431-68ee899ba254 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242777621 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_al l_with_reset_error.2242777621 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_unmapped_addr.3209533119 |
| Short name | T1348 |
| Test name | |
| Test status | |
| Simulation time | 32162028 ps |
| CPU time | 6.28 seconds |
| Started | May 30 03:52:28 PM PDT 24 |
| Finished | May 30 03:52:36 PM PDT 24 |
| Peak memory | 564788 kb |
| Host | smart-23525891-35c6-4b3b-9116-6f372aecc10e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209533119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.3209533119 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device.4227722138 |
| Short name | T2701 |
| Test name | |
| Test status | |
| Simulation time | 2483234632 ps |
| CPU time | 110.68 seconds |
| Started | May 30 03:52:37 PM PDT 24 |
| Finished | May 30 03:54:29 PM PDT 24 |
| Peak memory | 573016 kb |
| Host | smart-a4bb9309-ac6b-4f90-997b-342b50a179ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227722138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device .4227722138 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.1318266444 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 64411685049 ps |
| CPU time | 1256.79 seconds |
| Started | May 30 03:52:37 PM PDT 24 |
| Finished | May 30 04:13:35 PM PDT 24 |
| Peak memory | 573268 kb |
| Host | smart-073b2922-3f3a-4aa7-b3a4-cb410cdcc2da |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318266444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_ device_slow_rsp.1318266444 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.161381391 |
| Short name | T2241 |
| Test name | |
| Test status | |
| Simulation time | 348156725 ps |
| CPU time | 16.44 seconds |
| Started | May 30 03:52:36 PM PDT 24 |
| Finished | May 30 03:52:54 PM PDT 24 |
| Peak memory | 572940 kb |
| Host | smart-17274ad1-5fbd-4dd9-b8b3-37341600aa5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161381391 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr .161381391 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_random.2888111115 |
| Short name | T2541 |
| Test name | |
| Test status | |
| Simulation time | 1397976607 ps |
| CPU time | 47.08 seconds |
| Started | May 30 03:52:55 PM PDT 24 |
| Finished | May 30 03:53:43 PM PDT 24 |
| Peak memory | 572888 kb |
| Host | smart-a4eeb433-0708-44d9-95cc-44c4a240327e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888111115 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.2888111115 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random.1051890736 |
| Short name | T2001 |
| Test name | |
| Test status | |
| Simulation time | 565477021 ps |
| CPU time | 46.82 seconds |
| Started | May 30 03:52:27 PM PDT 24 |
| Finished | May 30 03:53:15 PM PDT 24 |
| Peak memory | 573080 kb |
| Host | smart-209526ac-c5b7-4c27-9b2a-058adfe0fc36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051890736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random.1051890736 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_large_delays.3281114327 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 40244547421 ps |
| CPU time | 438.6 seconds |
| Started | May 30 03:52:44 PM PDT 24 |
| Finished | May 30 04:00:04 PM PDT 24 |
| Peak memory | 573140 kb |
| Host | smart-eedd7afd-bc1a-446a-a2a0-23145fde4297 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281114327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.3281114327 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_slow_rsp.3456652403 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 32838579847 ps |
| CPU time | 562.27 seconds |
| Started | May 30 03:52:36 PM PDT 24 |
| Finished | May 30 04:01:59 PM PDT 24 |
| Peak memory | 573188 kb |
| Host | smart-ae6ed757-f8d9-4c42-a639-e54b24803d2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456652403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.3456652403 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_zero_delays.3591977780 |
| Short name | T2203 |
| Test name | |
| Test status | |
| Simulation time | 105669937 ps |
| CPU time | 12.16 seconds |
| Started | May 30 03:52:25 PM PDT 24 |
| Finished | May 30 03:52:39 PM PDT 24 |
| Peak memory | 572960 kb |
| Host | smart-e41a0953-cd4c-4c97-9b27-452edbccbe21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591977780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_del ays.3591977780 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_same_source.1721351751 |
| Short name | T1880 |
| Test name | |
| Test status | |
| Simulation time | 357580908 ps |
| CPU time | 28.04 seconds |
| Started | May 30 03:52:43 PM PDT 24 |
| Finished | May 30 03:53:12 PM PDT 24 |
| Peak memory | 573060 kb |
| Host | smart-746e0e35-7088-4904-afbd-21ba8123d9d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721351751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.1721351751 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke.2523897046 |
| Short name | T1388 |
| Test name | |
| Test status | |
| Simulation time | 149991522 ps |
| CPU time | 8.26 seconds |
| Started | May 30 03:52:28 PM PDT 24 |
| Finished | May 30 03:52:38 PM PDT 24 |
| Peak memory | 564852 kb |
| Host | smart-a334c317-cda6-4279-b81a-af3b86b45e84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523897046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.2523897046 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_large_delays.1759938469 |
| Short name | T2133 |
| Test name | |
| Test status | |
| Simulation time | 5041437106 ps |
| CPU time | 55.4 seconds |
| Started | May 30 03:52:26 PM PDT 24 |
| Finished | May 30 03:53:23 PM PDT 24 |
| Peak memory | 563516 kb |
| Host | smart-d671c0f5-6f96-43a9-a353-d7ddec4f88d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759938469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.1759938469 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.2399868385 |
| Short name | T1387 |
| Test name | |
| Test status | |
| Simulation time | 3750974501 ps |
| CPU time | 67.71 seconds |
| Started | May 30 03:52:30 PM PDT 24 |
| Finished | May 30 03:53:39 PM PDT 24 |
| Peak memory | 564876 kb |
| Host | smart-91e2164d-7442-411c-a80a-d1965b734ac3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399868385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.2399868385 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_zero_delays.671881881 |
| Short name | T1465 |
| Test name | |
| Test status | |
| Simulation time | 44851260 ps |
| CPU time | 6.19 seconds |
| Started | May 30 03:52:26 PM PDT 24 |
| Finished | May 30 03:52:34 PM PDT 24 |
| Peak memory | 564844 kb |
| Host | smart-6d44452a-57d4-494a-b75a-0a357b4f159d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671881881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays .671881881 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all.123267322 |
| Short name | T1733 |
| Test name | |
| Test status | |
| Simulation time | 2023528284 ps |
| CPU time | 91.61 seconds |
| Started | May 30 03:52:38 PM PDT 24 |
| Finished | May 30 03:54:12 PM PDT 24 |
| Peak memory | 573088 kb |
| Host | smart-d4a0f211-6f72-4c0a-a4d6-c8b3b5559238 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123267322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.123267322 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.3810345504 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 3750940728 ps |
| CPU time | 123.61 seconds |
| Started | May 30 03:52:44 PM PDT 24 |
| Finished | May 30 03:54:49 PM PDT 24 |
| Peak memory | 575192 kb |
| Host | smart-b5048da0-d509-4aea-8b17-240e34b1ccc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810345504 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.3810345504 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.2169764707 |
| Short name | T1813 |
| Test name | |
| Test status | |
| Simulation time | 761245500 ps |
| CPU time | 246.06 seconds |
| Started | May 30 03:52:40 PM PDT 24 |
| Finished | May 30 03:56:48 PM PDT 24 |
| Peak memory | 581344 kb |
| Host | smart-89a2ca89-5202-48a5-bec5-fea8e9f7eec9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169764707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all _with_rand_reset.2169764707 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.1816907168 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 8494266676 ps |
| CPU time | 354.98 seconds |
| Started | May 30 03:52:56 PM PDT 24 |
| Finished | May 30 03:58:53 PM PDT 24 |
| Peak memory | 577772 kb |
| Host | smart-e11e63af-645a-4ded-bc7d-dcac6da30ac4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816907168 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_al l_with_reset_error.1816907168 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_unmapped_addr.1349294156 |
| Short name | T2570 |
| Test name | |
| Test status | |
| Simulation time | 1112369802 ps |
| CPU time | 42.37 seconds |
| Started | May 30 03:52:35 PM PDT 24 |
| Finished | May 30 03:53:18 PM PDT 24 |
| Peak memory | 573056 kb |
| Host | smart-00d57524-ded3-485d-8d5a-eb98f2675233 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349294156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.1349294156 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_aliasing.4102643340 |
| Short name | T2676 |
| Test name | |
| Test status | |
| Simulation time | 29138817220 ps |
| CPU time | 5145.01 seconds |
| Started | May 30 03:48:38 PM PDT 24 |
| Finished | May 30 05:14:26 PM PDT 24 |
| Peak memory | 588384 kb |
| Host | smart-690ff6b1-9818-415a-aba6-e2002a25929e |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102643340 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.chip_csr_aliasing.4102643340 |
| Directory | /workspace/4.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_bit_bash.666825205 |
| Short name | T1355 |
| Test name | |
| Test status | |
| Simulation time | 9674027844 ps |
| CPU time | 972.4 seconds |
| Started | May 30 03:49:03 PM PDT 24 |
| Finished | May 30 04:05:17 PM PDT 24 |
| Peak memory | 586200 kb |
| Host | smart-be83ebcb-cefb-43ed-b23d-477e49f9d95f |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666825205 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 4.chip_csr_bit_bash.666825205 |
| Directory | /workspace/4.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_rw.1190475347 |
| Short name | T2251 |
| Test name | |
| Test status | |
| Simulation time | 4483050784 ps |
| CPU time | 370.94 seconds |
| Started | May 30 03:49:01 PM PDT 24 |
| Finished | May 30 03:55:14 PM PDT 24 |
| Peak memory | 592304 kb |
| Host | smart-18cb0f99-388d-4e10-9006-95906aaaf927 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190475347 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_rw.1190475347 |
| Directory | /workspace/4.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.4097211310 |
| Short name | T2122 |
| Test name | |
| Test status | |
| Simulation time | 31810522782 ps |
| CPU time | 4419.06 seconds |
| Started | May 30 03:48:54 PM PDT 24 |
| Finished | May 30 05:02:36 PM PDT 24 |
| Peak memory | 587672 kb |
| Host | smart-971bab78-124c-403c-9692-b80661fa4fa0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097211310 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 4.chip_same_csr_outstanding.4097211310 |
| Directory | /workspace/4.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_tl_errors.17334659 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 3303204300 ps |
| CPU time | 134.6 seconds |
| Started | May 30 03:48:42 PM PDT 24 |
| Finished | May 30 03:50:58 PM PDT 24 |
| Peak memory | 594048 kb |
| Host | smart-0480deee-0f74-40ab-bd97-59da9a1f6ceb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17334659 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_tl_errors.17334659 |
| Directory | /workspace/4.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device.1417118963 |
| Short name | T1438 |
| Test name | |
| Test status | |
| Simulation time | 439835217 ps |
| CPU time | 20.79 seconds |
| Started | May 30 03:48:58 PM PDT 24 |
| Finished | May 30 03:49:21 PM PDT 24 |
| Peak memory | 564844 kb |
| Host | smart-504d7833-afa9-415a-aed5-506456d81dfa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417118963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device. 1417118963 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.255689758 |
| Short name | T2560 |
| Test name | |
| Test status | |
| Simulation time | 9688896920 ps |
| CPU time | 174.39 seconds |
| Started | May 30 03:48:39 PM PDT 24 |
| Finished | May 30 03:51:35 PM PDT 24 |
| Peak memory | 573124 kb |
| Host | smart-239c08c6-6e00-4bb1-a26f-6dead30ccfa3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255689758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_de vice_slow_rsp.255689758 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.1230697645 |
| Short name | T1439 |
| Test name | |
| Test status | |
| Simulation time | 490806541 ps |
| CPU time | 18.14 seconds |
| Started | May 30 03:48:40 PM PDT 24 |
| Finished | May 30 03:49:00 PM PDT 24 |
| Peak memory | 572904 kb |
| Host | smart-252fca56-3a0a-4976-80ae-1fada9ab7398 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230697645 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr .1230697645 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_random.333044474 |
| Short name | T1433 |
| Test name | |
| Test status | |
| Simulation time | 567052102 ps |
| CPU time | 46.35 seconds |
| Started | May 30 03:48:58 PM PDT 24 |
| Finished | May 30 03:49:46 PM PDT 24 |
| Peak memory | 573944 kb |
| Host | smart-736b3d78-5df3-43cb-b4ce-2961a1e6fb1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333044474 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.333044474 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random.2171039200 |
| Short name | T2591 |
| Test name | |
| Test status | |
| Simulation time | 2014377854 ps |
| CPU time | 74.23 seconds |
| Started | May 30 03:49:03 PM PDT 24 |
| Finished | May 30 03:50:18 PM PDT 24 |
| Peak memory | 573064 kb |
| Host | smart-62015053-67df-4de5-9c83-c4987fd3c949 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171039200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random.2171039200 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_large_delays.3250707347 |
| Short name | T2126 |
| Test name | |
| Test status | |
| Simulation time | 15408071475 ps |
| CPU time | 159.94 seconds |
| Started | May 30 03:49:02 PM PDT 24 |
| Finished | May 30 03:51:44 PM PDT 24 |
| Peak memory | 573116 kb |
| Host | smart-47d2ffc5-3b08-4970-b0e3-183442fcc84e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250707347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.3250707347 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_slow_rsp.1679931973 |
| Short name | T1598 |
| Test name | |
| Test status | |
| Simulation time | 52741413940 ps |
| CPU time | 917.91 seconds |
| Started | May 30 03:48:45 PM PDT 24 |
| Finished | May 30 04:04:05 PM PDT 24 |
| Peak memory | 573180 kb |
| Host | smart-bdf193ab-de79-4ed5-9a60-dd07006e9f1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679931973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.1679931973 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_zero_delays.3439202726 |
| Short name | T2211 |
| Test name | |
| Test status | |
| Simulation time | 146809510 ps |
| CPU time | 14.8 seconds |
| Started | May 30 03:48:39 PM PDT 24 |
| Finished | May 30 03:48:56 PM PDT 24 |
| Peak memory | 572932 kb |
| Host | smart-32566306-f23c-4c3e-9824-8fc35fa16086 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439202726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_dela ys.3439202726 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_same_source.4186170569 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 244666728 ps |
| CPU time | 18.12 seconds |
| Started | May 30 03:48:54 PM PDT 24 |
| Finished | May 30 03:49:14 PM PDT 24 |
| Peak memory | 573036 kb |
| Host | smart-fa5048e9-3022-4c15-b7f5-2c59c89c8ae4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186170569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.4186170569 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke.1101404127 |
| Short name | T1842 |
| Test name | |
| Test status | |
| Simulation time | 184380251 ps |
| CPU time | 8.22 seconds |
| Started | May 30 03:48:41 PM PDT 24 |
| Finished | May 30 03:48:51 PM PDT 24 |
| Peak memory | 564788 kb |
| Host | smart-aa97b281-0826-4103-9546-138202b1adba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101404127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.1101404127 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.3401578898 |
| Short name | T2812 |
| Test name | |
| Test status | |
| Simulation time | 7032572039 ps |
| CPU time | 70.58 seconds |
| Started | May 30 03:49:03 PM PDT 24 |
| Finished | May 30 03:50:15 PM PDT 24 |
| Peak memory | 564956 kb |
| Host | smart-dcc84ec1-8277-4f9a-9fb5-2fd4b7aeaf44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401578898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.3401578898 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.2005625214 |
| Short name | T2349 |
| Test name | |
| Test status | |
| Simulation time | 5486218501 ps |
| CPU time | 89.67 seconds |
| Started | May 30 03:48:50 PM PDT 24 |
| Finished | May 30 03:50:22 PM PDT 24 |
| Peak memory | 564972 kb |
| Host | smart-c2eaa478-1af4-41be-8bca-a64b565c031a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005625214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.2005625214 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_zero_delays.4206171931 |
| Short name | T2357 |
| Test name | |
| Test status | |
| Simulation time | 50196446 ps |
| CPU time | 6.13 seconds |
| Started | May 30 03:48:45 PM PDT 24 |
| Finished | May 30 03:48:52 PM PDT 24 |
| Peak memory | 564784 kb |
| Host | smart-26a6c239-1741-4356-b759-1d80439a7d6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206171931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays .4206171931 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all.3888263202 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 17920306847 ps |
| CPU time | 629.9 seconds |
| Started | May 30 03:49:02 PM PDT 24 |
| Finished | May 30 03:59:34 PM PDT 24 |
| Peak memory | 573288 kb |
| Host | smart-c8c1c8de-0da4-4940-8151-182dccdcc87c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888263202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.3888263202 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.2570380815 |
| Short name | T1515 |
| Test name | |
| Test status | |
| Simulation time | 4303841758 ps |
| CPU time | 373.98 seconds |
| Started | May 30 03:48:51 PM PDT 24 |
| Finished | May 30 03:55:07 PM PDT 24 |
| Peak memory | 573240 kb |
| Host | smart-e20f54bd-2300-4dc7-b9bd-35eeaa0f1d1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570380815 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.2570380815 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.1970300552 |
| Short name | T1393 |
| Test name | |
| Test status | |
| Simulation time | 371534111 ps |
| CPU time | 130.38 seconds |
| Started | May 30 03:48:40 PM PDT 24 |
| Finished | May 30 03:50:52 PM PDT 24 |
| Peak memory | 573152 kb |
| Host | smart-29ba6f64-776b-460e-8f4f-eaf1db70bcac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970300552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_ with_rand_reset.1970300552 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.1565151001 |
| Short name | T2083 |
| Test name | |
| Test status | |
| Simulation time | 163609874 ps |
| CPU time | 49.68 seconds |
| Started | May 30 03:48:40 PM PDT 24 |
| Finished | May 30 03:49:31 PM PDT 24 |
| Peak memory | 573092 kb |
| Host | smart-c4006b61-67f5-4c9c-b057-813c2c760355 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565151001 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all _with_reset_error.1565151001 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_unmapped_addr.3024561700 |
| Short name | T2797 |
| Test name | |
| Test status | |
| Simulation time | 1015235906 ps |
| CPU time | 43.33 seconds |
| Started | May 30 03:48:59 PM PDT 24 |
| Finished | May 30 03:49:44 PM PDT 24 |
| Peak memory | 573064 kb |
| Host | smart-f335ee60-8c5c-443d-9cc9-eae3e261775d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024561700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.3024561700 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device.1607644423 |
| Short name | T1668 |
| Test name | |
| Test status | |
| Simulation time | 2451282869 ps |
| CPU time | 86.83 seconds |
| Started | May 30 03:52:55 PM PDT 24 |
| Finished | May 30 03:54:23 PM PDT 24 |
| Peak memory | 573076 kb |
| Host | smart-8d76c5b8-8969-4437-a54e-6d19afa8c10a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607644423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device .1607644423 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.471915823 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 52691509962 ps |
| CPU time | 933.61 seconds |
| Started | May 30 03:52:42 PM PDT 24 |
| Finished | May 30 04:08:17 PM PDT 24 |
| Peak memory | 573284 kb |
| Host | smart-d5da5c85-7734-4f58-9248-c2c10d6b58f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471915823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_d evice_slow_rsp.471915823 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.2376994590 |
| Short name | T1530 |
| Test name | |
| Test status | |
| Simulation time | 768435539 ps |
| CPU time | 32.4 seconds |
| Started | May 30 03:52:46 PM PDT 24 |
| Finished | May 30 03:53:19 PM PDT 24 |
| Peak memory | 573916 kb |
| Host | smart-62ebff5a-42b4-423e-a601-69471bed1eff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376994590 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_add r.2376994590 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_random.534050116 |
| Short name | T2625 |
| Test name | |
| Test status | |
| Simulation time | 1036952631 ps |
| CPU time | 38.46 seconds |
| Started | May 30 03:52:38 PM PDT 24 |
| Finished | May 30 03:53:18 PM PDT 24 |
| Peak memory | 572836 kb |
| Host | smart-04fd4137-72e4-4f18-b908-63ba322df83d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534050116 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.534050116 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random.3033838795 |
| Short name | T2259 |
| Test name | |
| Test status | |
| Simulation time | 94736438 ps |
| CPU time | 11.49 seconds |
| Started | May 30 03:52:35 PM PDT 24 |
| Finished | May 30 03:52:47 PM PDT 24 |
| Peak memory | 573048 kb |
| Host | smart-c630cc6a-3d68-49a0-8409-54e68fceda41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033838795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random.3033838795 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_large_delays.4217141454 |
| Short name | T2090 |
| Test name | |
| Test status | |
| Simulation time | 107221945312 ps |
| CPU time | 1211.15 seconds |
| Started | May 30 03:52:36 PM PDT 24 |
| Finished | May 30 04:12:49 PM PDT 24 |
| Peak memory | 573160 kb |
| Host | smart-e4170b91-a0f5-4fe8-84a5-0d0cb3e11b88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217141454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.4217141454 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_slow_rsp.2207858694 |
| Short name | T2490 |
| Test name | |
| Test status | |
| Simulation time | 40318211226 ps |
| CPU time | 683.45 seconds |
| Started | May 30 03:52:33 PM PDT 24 |
| Finished | May 30 04:03:57 PM PDT 24 |
| Peak memory | 573128 kb |
| Host | smart-b66533ea-87e1-4b47-b897-d6952c223d08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207858694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.2207858694 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.1713624281 |
| Short name | T2171 |
| Test name | |
| Test status | |
| Simulation time | 373731978 ps |
| CPU time | 32.22 seconds |
| Started | May 30 03:52:56 PM PDT 24 |
| Finished | May 30 03:53:30 PM PDT 24 |
| Peak memory | 572992 kb |
| Host | smart-60d1b7ea-ceb2-4bd4-bd1a-acc3d1645cd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713624281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_del ays.1713624281 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_same_source.194737123 |
| Short name | T1607 |
| Test name | |
| Test status | |
| Simulation time | 2530908722 ps |
| CPU time | 71.54 seconds |
| Started | May 30 03:52:44 PM PDT 24 |
| Finished | May 30 03:53:57 PM PDT 24 |
| Peak memory | 573124 kb |
| Host | smart-a386a0a7-0539-4fde-ad25-25ebd4ea6cb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194737123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.194737123 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke.1239834385 |
| Short name | T2029 |
| Test name | |
| Test status | |
| Simulation time | 237551685 ps |
| CPU time | 11 seconds |
| Started | May 30 03:52:35 PM PDT 24 |
| Finished | May 30 03:52:47 PM PDT 24 |
| Peak memory | 564876 kb |
| Host | smart-4a94a30f-bb66-49bf-8bd5-8b4b544a25b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239834385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.1239834385 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.1847084195 |
| Short name | T2033 |
| Test name | |
| Test status | |
| Simulation time | 10067482663 ps |
| CPU time | 118.18 seconds |
| Started | May 30 03:52:38 PM PDT 24 |
| Finished | May 30 03:54:38 PM PDT 24 |
| Peak memory | 564964 kb |
| Host | smart-fb98af42-5fdb-40a8-81e1-0087bb7bda59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847084195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.1847084195 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.2435937557 |
| Short name | T2847 |
| Test name | |
| Test status | |
| Simulation time | 4989395990 ps |
| CPU time | 83.98 seconds |
| Started | May 30 03:52:56 PM PDT 24 |
| Finished | May 30 03:54:21 PM PDT 24 |
| Peak memory | 563416 kb |
| Host | smart-8971f108-9155-45da-a627-29756cf9d023 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435937557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.2435937557 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_zero_delays.2822373954 |
| Short name | T1526 |
| Test name | |
| Test status | |
| Simulation time | 48721820 ps |
| CPU time | 6.55 seconds |
| Started | May 30 03:52:37 PM PDT 24 |
| Finished | May 30 03:52:45 PM PDT 24 |
| Peak memory | 564792 kb |
| Host | smart-ae2ffabe-f34d-46c0-bb4d-4c778982ffc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822373954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delay s.2822373954 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all.3448331509 |
| Short name | T2039 |
| Test name | |
| Test status | |
| Simulation time | 1342696351 ps |
| CPU time | 103.62 seconds |
| Started | May 30 03:52:44 PM PDT 24 |
| Finished | May 30 03:54:29 PM PDT 24 |
| Peak memory | 573092 kb |
| Host | smart-cef54447-d4ef-438f-81b7-f05a895b8a7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448331509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.3448331509 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.340240772 |
| Short name | T2075 |
| Test name | |
| Test status | |
| Simulation time | 4171973482 ps |
| CPU time | 364.61 seconds |
| Started | May 30 03:52:45 PM PDT 24 |
| Finished | May 30 03:58:50 PM PDT 24 |
| Peak memory | 575164 kb |
| Host | smart-ec6bcf25-29b2-4bdd-9609-d9c15bbe8b42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340240772 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.340240772 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.1758310881 |
| Short name | T2052 |
| Test name | |
| Test status | |
| Simulation time | 679100662 ps |
| CPU time | 210.76 seconds |
| Started | May 30 03:52:45 PM PDT 24 |
| Finished | May 30 03:56:17 PM PDT 24 |
| Peak memory | 573064 kb |
| Host | smart-c603497e-5703-4919-ae29-af528be22093 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758310881 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_al l_with_reset_error.1758310881 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_unmapped_addr.1594623391 |
| Short name | T2177 |
| Test name | |
| Test status | |
| Simulation time | 101612033 ps |
| CPU time | 14.39 seconds |
| Started | May 30 03:53:05 PM PDT 24 |
| Finished | May 30 03:53:20 PM PDT 24 |
| Peak memory | 573060 kb |
| Host | smart-caddc8c2-bfe8-4770-82c7-09f6e09db22d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594623391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.1594623391 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device.4135361453 |
| Short name | T1887 |
| Test name | |
| Test status | |
| Simulation time | 1073862953 ps |
| CPU time | 85.69 seconds |
| Started | May 30 03:52:46 PM PDT 24 |
| Finished | May 30 03:54:13 PM PDT 24 |
| Peak memory | 572972 kb |
| Host | smart-d5a31b55-a60e-4919-acbf-38c1545d7c2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135361453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device .4135361453 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.2570229895 |
| Short name | T2247 |
| Test name | |
| Test status | |
| Simulation time | 42433827675 ps |
| CPU time | 773.49 seconds |
| Started | May 30 03:52:47 PM PDT 24 |
| Finished | May 30 04:05:41 PM PDT 24 |
| Peak memory | 573280 kb |
| Host | smart-ef9bd4fc-ca70-41bf-aeea-0534526b7bf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570229895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_ device_slow_rsp.2570229895 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.4218615458 |
| Short name | T1338 |
| Test name | |
| Test status | |
| Simulation time | 841780987 ps |
| CPU time | 32.7 seconds |
| Started | May 30 03:52:56 PM PDT 24 |
| Finished | May 30 03:53:30 PM PDT 24 |
| Peak memory | 573988 kb |
| Host | smart-c19d46f8-bd33-4c36-bc1b-602d19b2b392 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218615458 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_add r.4218615458 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_random.1924147523 |
| Short name | T2426 |
| Test name | |
| Test status | |
| Simulation time | 582004987 ps |
| CPU time | 19.83 seconds |
| Started | May 30 03:52:46 PM PDT 24 |
| Finished | May 30 03:53:07 PM PDT 24 |
| Peak memory | 572904 kb |
| Host | smart-7d9e1355-b073-460b-a1a6-bff2cf7ef3fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924147523 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.1924147523 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random.3416129643 |
| Short name | T2435 |
| Test name | |
| Test status | |
| Simulation time | 1133497906 ps |
| CPU time | 39.2 seconds |
| Started | May 30 03:52:47 PM PDT 24 |
| Finished | May 30 03:53:27 PM PDT 24 |
| Peak memory | 573084 kb |
| Host | smart-ee7a9066-e5c0-4900-9af5-051aaa537a37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416129643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random.3416129643 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_large_delays.1697154806 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 68210840367 ps |
| CPU time | 782.41 seconds |
| Started | May 30 03:52:43 PM PDT 24 |
| Finished | May 30 04:05:47 PM PDT 24 |
| Peak memory | 573168 kb |
| Host | smart-ea6f2482-7b74-4707-8cdf-42f81c9cb9cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697154806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.1697154806 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.4084946088 |
| Short name | T1747 |
| Test name | |
| Test status | |
| Simulation time | 33428653334 ps |
| CPU time | 608.13 seconds |
| Started | May 30 03:52:45 PM PDT 24 |
| Finished | May 30 04:02:55 PM PDT 24 |
| Peak memory | 573180 kb |
| Host | smart-27cffa46-ea02-4fa1-b71e-1360711af81c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084946088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.4084946088 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_zero_delays.4071961121 |
| Short name | T2386 |
| Test name | |
| Test status | |
| Simulation time | 70955347 ps |
| CPU time | 9.05 seconds |
| Started | May 30 03:52:45 PM PDT 24 |
| Finished | May 30 03:52:55 PM PDT 24 |
| Peak memory | 564388 kb |
| Host | smart-478d0d65-1feb-4b02-afb6-bcd11f371d63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071961121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_del ays.4071961121 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_same_source.2338548441 |
| Short name | T2762 |
| Test name | |
| Test status | |
| Simulation time | 1435347896 ps |
| CPU time | 44 seconds |
| Started | May 30 03:52:44 PM PDT 24 |
| Finished | May 30 03:53:29 PM PDT 24 |
| Peak memory | 572896 kb |
| Host | smart-0e8eac81-3747-4dac-a4d0-06db42de138f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338548441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.2338548441 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke.469331783 |
| Short name | T2773 |
| Test name | |
| Test status | |
| Simulation time | 58355059 ps |
| CPU time | 7.14 seconds |
| Started | May 30 03:52:46 PM PDT 24 |
| Finished | May 30 03:52:54 PM PDT 24 |
| Peak memory | 564816 kb |
| Host | smart-a9c50f59-f35f-49b4-a2e7-fe9e569345db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469331783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.469331783 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.2994742946 |
| Short name | T2266 |
| Test name | |
| Test status | |
| Simulation time | 8059285579 ps |
| CPU time | 83.31 seconds |
| Started | May 30 03:53:05 PM PDT 24 |
| Finished | May 30 03:54:29 PM PDT 24 |
| Peak memory | 564896 kb |
| Host | smart-392e4b8f-c221-43a9-a39b-7e74aa72dbf6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994742946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.2994742946 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.1340404911 |
| Short name | T2752 |
| Test name | |
| Test status | |
| Simulation time | 4047810005 ps |
| CPU time | 75.51 seconds |
| Started | May 30 03:52:46 PM PDT 24 |
| Finished | May 30 03:54:03 PM PDT 24 |
| Peak memory | 563424 kb |
| Host | smart-c7db8b22-857f-42c9-b71a-7461eaa175f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340404911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.1340404911 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_zero_delays.3766029314 |
| Short name | T1732 |
| Test name | |
| Test status | |
| Simulation time | 38262481 ps |
| CPU time | 5.71 seconds |
| Started | May 30 03:52:45 PM PDT 24 |
| Finished | May 30 03:52:51 PM PDT 24 |
| Peak memory | 563372 kb |
| Host | smart-df2646e7-73c1-4857-bd28-a883e11da59e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766029314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delay s.3766029314 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all.2828641957 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 6362039178 ps |
| CPU time | 240.75 seconds |
| Started | May 30 03:52:58 PM PDT 24 |
| Finished | May 30 03:57:00 PM PDT 24 |
| Peak memory | 573268 kb |
| Host | smart-e3acb9dc-1333-4013-850d-de16e1235051 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828641957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.2828641957 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.3412576007 |
| Short name | T1815 |
| Test name | |
| Test status | |
| Simulation time | 12018663947 ps |
| CPU time | 421.75 seconds |
| Started | May 30 03:52:57 PM PDT 24 |
| Finished | May 30 04:00:00 PM PDT 24 |
| Peak memory | 573228 kb |
| Host | smart-952f9671-4589-46da-853c-d65203e85923 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412576007 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.3412576007 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.1188348666 |
| Short name | T2165 |
| Test name | |
| Test status | |
| Simulation time | 15166567496 ps |
| CPU time | 816.87 seconds |
| Started | May 30 03:52:56 PM PDT 24 |
| Finished | May 30 04:06:35 PM PDT 24 |
| Peak memory | 573196 kb |
| Host | smart-3b19d08c-48e3-4739-b3a0-ffc090203ee4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188348666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_al l_with_reset_error.1188348666 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_unmapped_addr.2368547036 |
| Short name | T2293 |
| Test name | |
| Test status | |
| Simulation time | 195092327 ps |
| CPU time | 25.96 seconds |
| Started | May 30 03:52:58 PM PDT 24 |
| Finished | May 30 03:53:25 PM PDT 24 |
| Peak memory | 573020 kb |
| Host | smart-36649a69-a390-486d-9321-4c8ac10e4117 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368547036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.2368547036 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device.1338203192 |
| Short name | T2648 |
| Test name | |
| Test status | |
| Simulation time | 292018918 ps |
| CPU time | 21.29 seconds |
| Started | May 30 03:52:55 PM PDT 24 |
| Finished | May 30 03:53:17 PM PDT 24 |
| Peak memory | 564788 kb |
| Host | smart-6f6a1647-c502-4b59-9b0a-168a477ab204 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338203192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device .1338203192 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.731687769 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 36305639351 ps |
| CPU time | 592.53 seconds |
| Started | May 30 03:52:55 PM PDT 24 |
| Finished | May 30 04:02:49 PM PDT 24 |
| Peak memory | 573240 kb |
| Host | smart-6a8d76fe-3e2c-4f75-82bb-d71e2ff72156 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731687769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_d evice_slow_rsp.731687769 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.3554844218 |
| Short name | T2573 |
| Test name | |
| Test status | |
| Simulation time | 882630657 ps |
| CPU time | 34.96 seconds |
| Started | May 30 03:52:55 PM PDT 24 |
| Finished | May 30 03:53:31 PM PDT 24 |
| Peak memory | 573932 kb |
| Host | smart-24999863-3713-48a7-a77a-237a71f25ada |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554844218 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_add r.3554844218 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_random.826374208 |
| Short name | T1753 |
| Test name | |
| Test status | |
| Simulation time | 210165876 ps |
| CPU time | 10.07 seconds |
| Started | May 30 03:53:07 PM PDT 24 |
| Finished | May 30 03:53:18 PM PDT 24 |
| Peak memory | 564676 kb |
| Host | smart-32c99567-9bcb-4a9b-91d7-91d5f2b0377d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826374208 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.826374208 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random.1333265181 |
| Short name | T2199 |
| Test name | |
| Test status | |
| Simulation time | 2084885824 ps |
| CPU time | 74.78 seconds |
| Started | May 30 03:53:00 PM PDT 24 |
| Finished | May 30 03:54:16 PM PDT 24 |
| Peak memory | 573008 kb |
| Host | smart-f25344c0-b87b-423b-8ca4-b6de94046337 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333265181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random.1333265181 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_large_delays.3671587488 |
| Short name | T2174 |
| Test name | |
| Test status | |
| Simulation time | 83632867795 ps |
| CPU time | 906.45 seconds |
| Started | May 30 03:53:06 PM PDT 24 |
| Finished | May 30 04:08:15 PM PDT 24 |
| Peak memory | 573152 kb |
| Host | smart-89324033-029c-4f8c-8325-3dd1685848e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671587488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.3671587488 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_slow_rsp.1984538424 |
| Short name | T2089 |
| Test name | |
| Test status | |
| Simulation time | 69723448386 ps |
| CPU time | 1168.48 seconds |
| Started | May 30 03:53:06 PM PDT 24 |
| Finished | May 30 04:12:36 PM PDT 24 |
| Peak memory | 573128 kb |
| Host | smart-2b2c1184-639f-449e-b469-355e8ceaf23f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984538424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.1984538424 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_zero_delays.4014805803 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 154395057 ps |
| CPU time | 15.98 seconds |
| Started | May 30 03:52:56 PM PDT 24 |
| Finished | May 30 03:53:13 PM PDT 24 |
| Peak memory | 572896 kb |
| Host | smart-f8cbc82b-b2d1-46e1-aee6-5552ddb755cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014805803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_del ays.4014805803 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_same_source.3698783263 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 188295831 ps |
| CPU time | 16.26 seconds |
| Started | May 30 03:52:55 PM PDT 24 |
| Finished | May 30 03:53:12 PM PDT 24 |
| Peak memory | 573032 kb |
| Host | smart-c80aa0e8-ff25-4b74-9b7c-43021392d58e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698783263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.3698783263 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke.2521984507 |
| Short name | T1538 |
| Test name | |
| Test status | |
| Simulation time | 236224917 ps |
| CPU time | 10.18 seconds |
| Started | May 30 03:53:01 PM PDT 24 |
| Finished | May 30 03:53:12 PM PDT 24 |
| Peak memory | 563292 kb |
| Host | smart-69ecb7d6-61c7-4f87-aca5-75335020c0f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521984507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.2521984507 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_large_delays.2580444904 |
| Short name | T1682 |
| Test name | |
| Test status | |
| Simulation time | 8847834468 ps |
| CPU time | 89.21 seconds |
| Started | May 30 03:52:58 PM PDT 24 |
| Finished | May 30 03:54:28 PM PDT 24 |
| Peak memory | 564968 kb |
| Host | smart-b991067e-3833-4684-9889-68758456154a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580444904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.2580444904 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.1296474076 |
| Short name | T1677 |
| Test name | |
| Test status | |
| Simulation time | 2749665268 ps |
| CPU time | 47.9 seconds |
| Started | May 30 03:52:56 PM PDT 24 |
| Finished | May 30 03:53:45 PM PDT 24 |
| Peak memory | 564860 kb |
| Host | smart-3e092371-2d31-4705-be18-31db89ac512f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296474076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.1296474076 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_zero_delays.323629737 |
| Short name | T2840 |
| Test name | |
| Test status | |
| Simulation time | 53549051 ps |
| CPU time | 7.13 seconds |
| Started | May 30 03:52:59 PM PDT 24 |
| Finished | May 30 03:53:07 PM PDT 24 |
| Peak memory | 564808 kb |
| Host | smart-71ce05ac-8035-4904-a1eb-03015719bc6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323629737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays .323629737 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all.1315522405 |
| Short name | T1846 |
| Test name | |
| Test status | |
| Simulation time | 651358291 ps |
| CPU time | 61.65 seconds |
| Started | May 30 03:52:58 PM PDT 24 |
| Finished | May 30 03:54:01 PM PDT 24 |
| Peak memory | 573172 kb |
| Host | smart-d0455eff-ca5e-4d18-aca9-1e8d7bad7334 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315522405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.1315522405 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.2803848387 |
| Short name | T2759 |
| Test name | |
| Test status | |
| Simulation time | 4207422429 ps |
| CPU time | 507.43 seconds |
| Started | May 30 03:52:56 PM PDT 24 |
| Finished | May 30 04:01:24 PM PDT 24 |
| Peak memory | 573160 kb |
| Host | smart-27a74c66-ddbe-4965-be15-a4200f817d78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803848387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all _with_rand_reset.2803848387 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.894190872 |
| Short name | T1653 |
| Test name | |
| Test status | |
| Simulation time | 189213938 ps |
| CPU time | 46.65 seconds |
| Started | May 30 03:52:59 PM PDT 24 |
| Finished | May 30 03:53:46 PM PDT 24 |
| Peak memory | 575192 kb |
| Host | smart-e3c95c3a-a369-416c-b0a6-47387e305811 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894190872 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all _with_reset_error.894190872 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_unmapped_addr.2839791461 |
| Short name | T2262 |
| Test name | |
| Test status | |
| Simulation time | 550059826 ps |
| CPU time | 26.67 seconds |
| Started | May 30 03:52:56 PM PDT 24 |
| Finished | May 30 03:53:24 PM PDT 24 |
| Peak memory | 572968 kb |
| Host | smart-0da03076-5775-4ce5-ad9c-a2014239cdc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839791461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.2839791461 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device.1536949776 |
| Short name | T1896 |
| Test name | |
| Test status | |
| Simulation time | 736300355 ps |
| CPU time | 71.93 seconds |
| Started | May 30 03:53:05 PM PDT 24 |
| Finished | May 30 03:54:18 PM PDT 24 |
| Peak memory | 573120 kb |
| Host | smart-fbfda0c1-4813-404b-85a8-7a0aa22a0d16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536949776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device .1536949776 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.1481009961 |
| Short name | T2824 |
| Test name | |
| Test status | |
| Simulation time | 30832663318 ps |
| CPU time | 527.02 seconds |
| Started | May 30 03:53:04 PM PDT 24 |
| Finished | May 30 04:01:52 PM PDT 24 |
| Peak memory | 573240 kb |
| Host | smart-8ecc4b27-eedb-4536-a65b-4857cc16c2b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481009961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_ device_slow_rsp.1481009961 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.798218298 |
| Short name | T2437 |
| Test name | |
| Test status | |
| Simulation time | 263597215 ps |
| CPU time | 14.33 seconds |
| Started | May 30 03:53:05 PM PDT 24 |
| Finished | May 30 03:53:21 PM PDT 24 |
| Peak memory | 572920 kb |
| Host | smart-824d1715-1b4e-43c7-8953-b8630ec8b8a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798218298 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr .798218298 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_random.878805879 |
| Short name | T1401 |
| Test name | |
| Test status | |
| Simulation time | 351671401 ps |
| CPU time | 31.92 seconds |
| Started | May 30 03:53:05 PM PDT 24 |
| Finished | May 30 03:53:38 PM PDT 24 |
| Peak memory | 573920 kb |
| Host | smart-313b9d74-5d6c-4b94-9d70-f2c629d43e67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878805879 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.878805879 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random.1339298443 |
| Short name | T2783 |
| Test name | |
| Test status | |
| Simulation time | 480923673 ps |
| CPU time | 43.83 seconds |
| Started | May 30 03:53:08 PM PDT 24 |
| Finished | May 30 03:53:52 PM PDT 24 |
| Peak memory | 573064 kb |
| Host | smart-a113db02-1f85-4582-b5ab-75ae323690a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339298443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random.1339298443 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_large_delays.915933634 |
| Short name | T1855 |
| Test name | |
| Test status | |
| Simulation time | 16969408089 ps |
| CPU time | 166.65 seconds |
| Started | May 30 03:53:05 PM PDT 24 |
| Finished | May 30 03:55:53 PM PDT 24 |
| Peak memory | 573172 kb |
| Host | smart-6da995fa-e29f-45f8-a519-8397a7027ed5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915933634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.915933634 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_slow_rsp.2218797773 |
| Short name | T2341 |
| Test name | |
| Test status | |
| Simulation time | 38032457134 ps |
| CPU time | 654.08 seconds |
| Started | May 30 03:53:07 PM PDT 24 |
| Finished | May 30 04:04:02 PM PDT 24 |
| Peak memory | 573156 kb |
| Host | smart-985cc5e1-8247-4b7b-b57b-238950f6f7ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218797773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.2218797773 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_zero_delays.485076134 |
| Short name | T1750 |
| Test name | |
| Test status | |
| Simulation time | 510029702 ps |
| CPU time | 39.72 seconds |
| Started | May 30 03:53:10 PM PDT 24 |
| Finished | May 30 03:53:51 PM PDT 24 |
| Peak memory | 572916 kb |
| Host | smart-6884725d-4d54-4ff8-99cf-171c02442fa4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485076134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_dela ys.485076134 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_same_source.905893549 |
| Short name | T2389 |
| Test name | |
| Test status | |
| Simulation time | 362786515 ps |
| CPU time | 30.75 seconds |
| Started | May 30 03:53:06 PM PDT 24 |
| Finished | May 30 03:53:38 PM PDT 24 |
| Peak memory | 573060 kb |
| Host | smart-753d2b73-7353-480c-9eb7-530d846ecfe7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905893549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.905893549 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke.907095839 |
| Short name | T2143 |
| Test name | |
| Test status | |
| Simulation time | 154914928 ps |
| CPU time | 8.57 seconds |
| Started | May 30 03:52:57 PM PDT 24 |
| Finished | May 30 03:53:06 PM PDT 24 |
| Peak memory | 564868 kb |
| Host | smart-f76eb0c1-577c-4d1a-8d1e-160606377dc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907095839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.907095839 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.1183186862 |
| Short name | T2467 |
| Test name | |
| Test status | |
| Simulation time | 6297963807 ps |
| CPU time | 71.3 seconds |
| Started | May 30 03:53:06 PM PDT 24 |
| Finished | May 30 03:54:19 PM PDT 24 |
| Peak memory | 564932 kb |
| Host | smart-7a89d776-555f-4e86-afc5-5fae5242e31d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183186862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.1183186862 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.2143434250 |
| Short name | T2501 |
| Test name | |
| Test status | |
| Simulation time | 4550609427 ps |
| CPU time | 79.84 seconds |
| Started | May 30 03:53:06 PM PDT 24 |
| Finished | May 30 03:54:27 PM PDT 24 |
| Peak memory | 564952 kb |
| Host | smart-fddfac52-9f94-4f76-8be4-2af1a4e5e4e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143434250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.2143434250 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_zero_delays.4282035826 |
| Short name | T1632 |
| Test name | |
| Test status | |
| Simulation time | 44872422 ps |
| CPU time | 6.27 seconds |
| Started | May 30 03:53:07 PM PDT 24 |
| Finished | May 30 03:53:14 PM PDT 24 |
| Peak memory | 564740 kb |
| Host | smart-f8eff205-2009-47c8-8202-2a073bca6a90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282035826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delay s.4282035826 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all.3219491246 |
| Short name | T2098 |
| Test name | |
| Test status | |
| Simulation time | 10032344085 ps |
| CPU time | 357.38 seconds |
| Started | May 30 03:53:05 PM PDT 24 |
| Finished | May 30 03:59:04 PM PDT 24 |
| Peak memory | 573200 kb |
| Host | smart-d830d009-c60e-4715-b8a7-ee59e6471754 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219491246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.3219491246 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.2884927306 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 2793244263 ps |
| CPU time | 241.61 seconds |
| Started | May 30 03:53:15 PM PDT 24 |
| Finished | May 30 03:57:18 PM PDT 24 |
| Peak memory | 573172 kb |
| Host | smart-07cf1c6b-7eff-442d-be59-5df9406a07e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884927306 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.2884927306 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.1852558029 |
| Short name | T1869 |
| Test name | |
| Test status | |
| Simulation time | 353927774 ps |
| CPU time | 115.1 seconds |
| Started | May 30 03:53:10 PM PDT 24 |
| Finished | May 30 03:55:07 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-14bb5afd-ccba-40b8-85ae-f09f62ad8d68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852558029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all _with_rand_reset.1852558029 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.1812065788 |
| Short name | T2157 |
| Test name | |
| Test status | |
| Simulation time | 13279701054 ps |
| CPU time | 593.46 seconds |
| Started | May 30 03:53:15 PM PDT 24 |
| Finished | May 30 04:03:10 PM PDT 24 |
| Peak memory | 573224 kb |
| Host | smart-0198b7a0-62a1-4556-b493-317adaffb359 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812065788 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_al l_with_reset_error.1812065788 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_unmapped_addr.3170922347 |
| Short name | T2508 |
| Test name | |
| Test status | |
| Simulation time | 363072188 ps |
| CPU time | 19.68 seconds |
| Started | May 30 03:53:06 PM PDT 24 |
| Finished | May 30 03:53:27 PM PDT 24 |
| Peak memory | 572992 kb |
| Host | smart-64c7d269-3320-4b34-b850-1f3dd4af00d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170922347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.3170922347 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device.3788611948 |
| Short name | T2047 |
| Test name | |
| Test status | |
| Simulation time | 881090776 ps |
| CPU time | 65.03 seconds |
| Started | May 30 03:53:14 PM PDT 24 |
| Finished | May 30 03:54:21 PM PDT 24 |
| Peak memory | 573012 kb |
| Host | smart-de088a87-a501-4313-8c31-7ee32cd96395 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788611948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device .3788611948 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.2785827736 |
| Short name | T2392 |
| Test name | |
| Test status | |
| Simulation time | 141747566902 ps |
| CPU time | 2812.94 seconds |
| Started | May 30 03:53:21 PM PDT 24 |
| Finished | May 30 04:40:16 PM PDT 24 |
| Peak memory | 573360 kb |
| Host | smart-eaad9159-eccf-4d38-9913-d12cef3ca6c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785827736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_ device_slow_rsp.2785827736 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.1573975260 |
| Short name | T1944 |
| Test name | |
| Test status | |
| Simulation time | 483837269 ps |
| CPU time | 20.47 seconds |
| Started | May 30 03:53:15 PM PDT 24 |
| Finished | May 30 03:53:37 PM PDT 24 |
| Peak memory | 572888 kb |
| Host | smart-18973da4-4e27-4607-9079-755270c76bb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573975260 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_add r.1573975260 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_random.2046556870 |
| Short name | T1435 |
| Test name | |
| Test status | |
| Simulation time | 1959980030 ps |
| CPU time | 62.3 seconds |
| Started | May 30 03:53:16 PM PDT 24 |
| Finished | May 30 03:54:19 PM PDT 24 |
| Peak memory | 573972 kb |
| Host | smart-707d549d-32fe-4b37-8397-f19c7a05ab3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046556870 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.2046556870 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random.2314987970 |
| Short name | T2394 |
| Test name | |
| Test status | |
| Simulation time | 1785806584 ps |
| CPU time | 68.57 seconds |
| Started | May 30 03:53:18 PM PDT 24 |
| Finished | May 30 03:54:28 PM PDT 24 |
| Peak memory | 573072 kb |
| Host | smart-2042aebd-73c7-4c7c-ba6e-ab112a3797a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314987970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random.2314987970 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_large_delays.1105571620 |
| Short name | T2226 |
| Test name | |
| Test status | |
| Simulation time | 4659394196 ps |
| CPU time | 56.95 seconds |
| Started | May 30 03:53:16 PM PDT 24 |
| Finished | May 30 03:54:14 PM PDT 24 |
| Peak memory | 564988 kb |
| Host | smart-16376520-b2aa-4f7c-a9b8-5150c8a977f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105571620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.1105571620 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_slow_rsp.3462480872 |
| Short name | T1916 |
| Test name | |
| Test status | |
| Simulation time | 43078243583 ps |
| CPU time | 718.85 seconds |
| Started | May 30 03:53:18 PM PDT 24 |
| Finished | May 30 04:05:19 PM PDT 24 |
| Peak memory | 573216 kb |
| Host | smart-efc0e316-c39e-4a7d-adec-954aae9d7086 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462480872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.3462480872 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_zero_delays.1210284515 |
| Short name | T2225 |
| Test name | |
| Test status | |
| Simulation time | 356682484 ps |
| CPU time | 36.85 seconds |
| Started | May 30 03:53:15 PM PDT 24 |
| Finished | May 30 03:53:53 PM PDT 24 |
| Peak memory | 573056 kb |
| Host | smart-81ebf133-80d8-4683-91a4-d371991bcca1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210284515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_del ays.1210284515 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_same_source.3647923321 |
| Short name | T2761 |
| Test name | |
| Test status | |
| Simulation time | 46194070 ps |
| CPU time | 6.54 seconds |
| Started | May 30 03:53:16 PM PDT 24 |
| Finished | May 30 03:53:24 PM PDT 24 |
| Peak memory | 563300 kb |
| Host | smart-e38a5bd9-f2b8-4442-baa1-10821b711582 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647923321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.3647923321 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke.3488147323 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 52387100 ps |
| CPU time | 6.69 seconds |
| Started | May 30 03:53:15 PM PDT 24 |
| Finished | May 30 03:53:23 PM PDT 24 |
| Peak memory | 564828 kb |
| Host | smart-fe9bb46b-ffdf-436d-99c5-8788ced2dd9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488147323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.3488147323 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_large_delays.317822564 |
| Short name | T2340 |
| Test name | |
| Test status | |
| Simulation time | 7742558782 ps |
| CPU time | 83.09 seconds |
| Started | May 30 03:53:17 PM PDT 24 |
| Finished | May 30 03:54:42 PM PDT 24 |
| Peak memory | 564944 kb |
| Host | smart-2a6c2369-f4d0-4345-92a3-2d1873e563f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317822564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.317822564 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.1586287240 |
| Short name | T2137 |
| Test name | |
| Test status | |
| Simulation time | 3369062717 ps |
| CPU time | 57.85 seconds |
| Started | May 30 03:53:18 PM PDT 24 |
| Finished | May 30 03:54:18 PM PDT 24 |
| Peak memory | 563380 kb |
| Host | smart-5f5c1a25-505f-4340-ad84-81a892e88a73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586287240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.1586287240 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_zero_delays.1153342682 |
| Short name | T2048 |
| Test name | |
| Test status | |
| Simulation time | 43696184 ps |
| CPU time | 6.51 seconds |
| Started | May 30 03:53:21 PM PDT 24 |
| Finished | May 30 03:53:29 PM PDT 24 |
| Peak memory | 564804 kb |
| Host | smart-5f9dffa4-d1cf-45e4-b816-5465c6bff25e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153342682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delay s.1153342682 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all.518150245 |
| Short name | T2390 |
| Test name | |
| Test status | |
| Simulation time | 5205051425 ps |
| CPU time | 185.56 seconds |
| Started | May 30 03:53:14 PM PDT 24 |
| Finished | May 30 03:56:21 PM PDT 24 |
| Peak memory | 573236 kb |
| Host | smart-5c129cd5-0ba5-496b-933e-10a61b2ce480 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518150245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.518150245 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.2189247953 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 3225604189 ps |
| CPU time | 131.19 seconds |
| Started | May 30 03:53:18 PM PDT 24 |
| Finished | May 30 03:55:31 PM PDT 24 |
| Peak memory | 573068 kb |
| Host | smart-f6437611-83b7-4b33-b42f-6860a2c99f99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189247953 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.2189247953 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.1007032079 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 2521925306 ps |
| CPU time | 134.44 seconds |
| Started | May 30 03:53:16 PM PDT 24 |
| Finished | May 30 03:55:32 PM PDT 24 |
| Peak memory | 573208 kb |
| Host | smart-482989b5-a977-4dd5-99b5-eb97945ee218 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007032079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all _with_rand_reset.1007032079 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.2092245511 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 49632600 ps |
| CPU time | 20.19 seconds |
| Started | May 30 03:53:22 PM PDT 24 |
| Finished | May 30 03:53:43 PM PDT 24 |
| Peak memory | 573076 kb |
| Host | smart-672c31f1-a3da-46b9-a861-27661f79d525 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092245511 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_al l_with_reset_error.2092245511 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_unmapped_addr.2233534430 |
| Short name | T2094 |
| Test name | |
| Test status | |
| Simulation time | 95428935 ps |
| CPU time | 14.5 seconds |
| Started | May 30 03:53:18 PM PDT 24 |
| Finished | May 30 03:53:34 PM PDT 24 |
| Peak memory | 573120 kb |
| Host | smart-004567cf-53e7-4a69-9459-85bad9a4df06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233534430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.2233534430 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device.2394693556 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 1271334605 ps |
| CPU time | 45.22 seconds |
| Started | May 30 03:53:23 PM PDT 24 |
| Finished | May 30 03:54:10 PM PDT 24 |
| Peak memory | 573052 kb |
| Host | smart-17a45bb4-a022-4e9f-8893-dacad7fa83c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394693556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device .2394693556 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.170967505 |
| Short name | T1947 |
| Test name | |
| Test status | |
| Simulation time | 67115366220 ps |
| CPU time | 1243.84 seconds |
| Started | May 30 03:53:26 PM PDT 24 |
| Finished | May 30 04:14:11 PM PDT 24 |
| Peak memory | 573312 kb |
| Host | smart-9b82dcb4-1a6e-4831-af55-deba11132cc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170967505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_d evice_slow_rsp.170967505 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.1676426058 |
| Short name | T2561 |
| Test name | |
| Test status | |
| Simulation time | 1481195339 ps |
| CPU time | 62.31 seconds |
| Started | May 30 03:53:33 PM PDT 24 |
| Finished | May 30 03:54:36 PM PDT 24 |
| Peak memory | 572920 kb |
| Host | smart-87400920-4d25-418e-a5b6-0d00ff43e1cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676426058 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_add r.1676426058 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_random.582984207 |
| Short name | T2708 |
| Test name | |
| Test status | |
| Simulation time | 68886443 ps |
| CPU time | 7.49 seconds |
| Started | May 30 03:53:25 PM PDT 24 |
| Finished | May 30 03:53:34 PM PDT 24 |
| Peak memory | 564616 kb |
| Host | smart-17c46a07-9391-4093-94bd-b622703130dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582984207 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.582984207 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random.242542970 |
| Short name | T1451 |
| Test name | |
| Test status | |
| Simulation time | 481991880 ps |
| CPU time | 43.77 seconds |
| Started | May 30 03:53:14 PM PDT 24 |
| Finished | May 30 03:53:59 PM PDT 24 |
| Peak memory | 573044 kb |
| Host | smart-e36bb1a8-ae8e-46b1-bec3-624ed80ae71a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242542970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random.242542970 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_large_delays.4137917374 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 45629506059 ps |
| CPU time | 542.56 seconds |
| Started | May 30 03:53:25 PM PDT 24 |
| Finished | May 30 04:02:29 PM PDT 24 |
| Peak memory | 573180 kb |
| Host | smart-f4dbde6f-348d-40b8-9829-d5ac8219ffaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137917374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.4137917374 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.3109819964 |
| Short name | T2289 |
| Test name | |
| Test status | |
| Simulation time | 37450124498 ps |
| CPU time | 591.15 seconds |
| Started | May 30 03:53:25 PM PDT 24 |
| Finished | May 30 04:03:18 PM PDT 24 |
| Peak memory | 573216 kb |
| Host | smart-e9bd902d-876f-40c9-b9cf-896037741be8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109819964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.3109819964 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_zero_delays.2120974453 |
| Short name | T1361 |
| Test name | |
| Test status | |
| Simulation time | 38257170 ps |
| CPU time | 6.49 seconds |
| Started | May 30 03:53:22 PM PDT 24 |
| Finished | May 30 03:53:30 PM PDT 24 |
| Peak memory | 564812 kb |
| Host | smart-377ddce5-f48a-404c-85a9-d9f9a6678745 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120974453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_del ays.2120974453 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_same_source.4073981380 |
| Short name | T2280 |
| Test name | |
| Test status | |
| Simulation time | 370164937 ps |
| CPU time | 13.58 seconds |
| Started | May 30 03:53:32 PM PDT 24 |
| Finished | May 30 03:53:46 PM PDT 24 |
| Peak memory | 572536 kb |
| Host | smart-ce716c04-eb35-491a-9fd5-5d58c798a4e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073981380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.4073981380 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke.241365777 |
| Short name | T2442 |
| Test name | |
| Test status | |
| Simulation time | 42387223 ps |
| CPU time | 6.21 seconds |
| Started | May 30 03:53:17 PM PDT 24 |
| Finished | May 30 03:53:25 PM PDT 24 |
| Peak memory | 563380 kb |
| Host | smart-86148b22-9b45-48b4-b226-e933c627ba07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241365777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.241365777 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_large_delays.2950958088 |
| Short name | T1820 |
| Test name | |
| Test status | |
| Simulation time | 8356037747 ps |
| CPU time | 93.95 seconds |
| Started | May 30 03:53:15 PM PDT 24 |
| Finished | May 30 03:54:50 PM PDT 24 |
| Peak memory | 564928 kb |
| Host | smart-aaba060d-11db-4e36-88f6-fc761a5397ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950958088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.2950958088 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.4136356329 |
| Short name | T2022 |
| Test name | |
| Test status | |
| Simulation time | 5558458377 ps |
| CPU time | 89.33 seconds |
| Started | May 30 03:53:14 PM PDT 24 |
| Finished | May 30 03:54:45 PM PDT 24 |
| Peak memory | 564916 kb |
| Host | smart-73eac9f2-15ba-4a4d-b867-0a69b32665fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136356329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.4136356329 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_zero_delays.2221962707 |
| Short name | T2795 |
| Test name | |
| Test status | |
| Simulation time | 45949452 ps |
| CPU time | 6.28 seconds |
| Started | May 30 03:53:18 PM PDT 24 |
| Finished | May 30 03:53:26 PM PDT 24 |
| Peak memory | 564772 kb |
| Host | smart-d2883b89-a31b-45b4-8e7e-04ddf6e00815 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221962707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delay s.2221962707 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all.3941321281 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 4408080468 ps |
| CPU time | 165 seconds |
| Started | May 30 03:53:23 PM PDT 24 |
| Finished | May 30 03:56:10 PM PDT 24 |
| Peak memory | 573292 kb |
| Host | smart-46069d6d-f468-47b3-b4dd-d0387a808134 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941321281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.3941321281 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.1043844970 |
| Short name | T2775 |
| Test name | |
| Test status | |
| Simulation time | 9664731875 ps |
| CPU time | 364.39 seconds |
| Started | May 30 03:53:26 PM PDT 24 |
| Finished | May 30 03:59:31 PM PDT 24 |
| Peak memory | 573196 kb |
| Host | smart-1200e326-e72a-4317-b202-034ad7b30c47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043844970 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.1043844970 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.4201290859 |
| Short name | T2815 |
| Test name | |
| Test status | |
| Simulation time | 5602968775 ps |
| CPU time | 760.61 seconds |
| Started | May 30 03:53:26 PM PDT 24 |
| Finished | May 30 04:06:08 PM PDT 24 |
| Peak memory | 573248 kb |
| Host | smart-9253bcbb-6920-41d5-ae33-a4d1318957b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201290859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all _with_rand_reset.4201290859 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.2907912348 |
| Short name | T2550 |
| Test name | |
| Test status | |
| Simulation time | 736692520 ps |
| CPU time | 202.38 seconds |
| Started | May 30 03:53:25 PM PDT 24 |
| Finished | May 30 03:56:49 PM PDT 24 |
| Peak memory | 573028 kb |
| Host | smart-83ce8e5a-c25a-424f-b52f-91197775e129 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907912348 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_al l_with_reset_error.2907912348 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_unmapped_addr.1665902995 |
| Short name | T1806 |
| Test name | |
| Test status | |
| Simulation time | 390077945 ps |
| CPU time | 17.89 seconds |
| Started | May 30 03:53:29 PM PDT 24 |
| Finished | May 30 03:53:48 PM PDT 24 |
| Peak memory | 573008 kb |
| Host | smart-5230769d-0615-41b7-8151-f361b830f909 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665902995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.1665902995 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device.1079209466 |
| Short name | T1640 |
| Test name | |
| Test status | |
| Simulation time | 848260706 ps |
| CPU time | 72.81 seconds |
| Started | May 30 03:53:25 PM PDT 24 |
| Finished | May 30 03:54:39 PM PDT 24 |
| Peak memory | 573116 kb |
| Host | smart-5801966a-d0fe-4c5d-bd8c-8fe9c848642e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079209466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device .1079209466 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.3778684185 |
| Short name | T1791 |
| Test name | |
| Test status | |
| Simulation time | 28907004103 ps |
| CPU time | 498.49 seconds |
| Started | May 30 03:53:25 PM PDT 24 |
| Finished | May 30 04:01:45 PM PDT 24 |
| Peak memory | 573304 kb |
| Host | smart-473c8aa9-3a26-4c94-ba02-389fa12741a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778684185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_ device_slow_rsp.3778684185 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.4137458255 |
| Short name | T2679 |
| Test name | |
| Test status | |
| Simulation time | 898043131 ps |
| CPU time | 37.58 seconds |
| Started | May 30 03:53:35 PM PDT 24 |
| Finished | May 30 03:54:13 PM PDT 24 |
| Peak memory | 572848 kb |
| Host | smart-863ef93b-970c-4c71-ba42-19c1cda659ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137458255 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_add r.4137458255 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_random.2489407207 |
| Short name | T1599 |
| Test name | |
| Test status | |
| Simulation time | 725198461 ps |
| CPU time | 23.6 seconds |
| Started | May 30 03:53:36 PM PDT 24 |
| Finished | May 30 03:54:01 PM PDT 24 |
| Peak memory | 572792 kb |
| Host | smart-957e66c9-06e0-4810-9e1e-9e8317d8dd0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489407207 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.2489407207 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random.2490265629 |
| Short name | T2046 |
| Test name | |
| Test status | |
| Simulation time | 1207075114 ps |
| CPU time | 40.45 seconds |
| Started | May 30 03:53:26 PM PDT 24 |
| Finished | May 30 03:54:08 PM PDT 24 |
| Peak memory | 573052 kb |
| Host | smart-2e28b716-83ed-4a34-9cfd-6476808d9c68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490265629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random.2490265629 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_large_delays.145050509 |
| Short name | T2768 |
| Test name | |
| Test status | |
| Simulation time | 21769057936 ps |
| CPU time | 227.91 seconds |
| Started | May 30 03:53:27 PM PDT 24 |
| Finished | May 30 03:57:16 PM PDT 24 |
| Peak memory | 573208 kb |
| Host | smart-938cc121-3728-4b27-8833-b5e625609b40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145050509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.145050509 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_slow_rsp.2110600754 |
| Short name | T2322 |
| Test name | |
| Test status | |
| Simulation time | 38957936287 ps |
| CPU time | 770.13 seconds |
| Started | May 30 03:53:24 PM PDT 24 |
| Finished | May 30 04:06:16 PM PDT 24 |
| Peak memory | 573168 kb |
| Host | smart-34e8d032-acb1-428b-b090-a5dfbddefc36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110600754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.2110600754 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_zero_delays.660580276 |
| Short name | T1724 |
| Test name | |
| Test status | |
| Simulation time | 655978283 ps |
| CPU time | 47.91 seconds |
| Started | May 30 03:53:33 PM PDT 24 |
| Finished | May 30 03:54:22 PM PDT 24 |
| Peak memory | 573024 kb |
| Host | smart-bd810270-de94-471a-a940-eb599acc9837 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660580276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_dela ys.660580276 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_same_source.3614090376 |
| Short name | T2081 |
| Test name | |
| Test status | |
| Simulation time | 1975346756 ps |
| CPU time | 64.45 seconds |
| Started | May 30 03:53:36 PM PDT 24 |
| Finished | May 30 03:54:41 PM PDT 24 |
| Peak memory | 573048 kb |
| Host | smart-0d022f7c-a067-4abf-9f5d-9f2b7fe5df8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614090376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.3614090376 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke.2616772891 |
| Short name | T2292 |
| Test name | |
| Test status | |
| Simulation time | 56320193 ps |
| CPU time | 6.89 seconds |
| Started | May 30 03:53:25 PM PDT 24 |
| Finished | May 30 03:53:33 PM PDT 24 |
| Peak memory | 564848 kb |
| Host | smart-b6dbc290-f1ee-4701-b4bb-39e1dd582289 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616772891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.2616772891 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_large_delays.2966585105 |
| Short name | T2757 |
| Test name | |
| Test status | |
| Simulation time | 9120599576 ps |
| CPU time | 97.76 seconds |
| Started | May 30 03:53:33 PM PDT 24 |
| Finished | May 30 03:55:12 PM PDT 24 |
| Peak memory | 564924 kb |
| Host | smart-0a0ebe35-4b16-4106-ab1c-8fd15c0d92bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966585105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.2966585105 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.1649466917 |
| Short name | T1402 |
| Test name | |
| Test status | |
| Simulation time | 3374715418 ps |
| CPU time | 59.17 seconds |
| Started | May 30 03:53:25 PM PDT 24 |
| Finished | May 30 03:54:25 PM PDT 24 |
| Peak memory | 564804 kb |
| Host | smart-2a3433a9-a996-4e9f-910f-dbb2417074d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649466917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.1649466917 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_zero_delays.1256282638 |
| Short name | T1375 |
| Test name | |
| Test status | |
| Simulation time | 58972266 ps |
| CPU time | 7.01 seconds |
| Started | May 30 03:53:26 PM PDT 24 |
| Finished | May 30 03:53:34 PM PDT 24 |
| Peak memory | 563312 kb |
| Host | smart-7aef4eb0-0d15-4a50-94d5-e4ab4dcd50e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256282638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delay s.1256282638 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all.2450473697 |
| Short name | T1877 |
| Test name | |
| Test status | |
| Simulation time | 4649299854 ps |
| CPU time | 196.01 seconds |
| Started | May 30 03:53:37 PM PDT 24 |
| Finished | May 30 03:56:55 PM PDT 24 |
| Peak memory | 573264 kb |
| Host | smart-3068be8e-e949-4fc1-b00a-4b1fbbf44b7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450473697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.2450473697 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_error.1321412931 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 2849594627 ps |
| CPU time | 223.38 seconds |
| Started | May 30 03:53:37 PM PDT 24 |
| Finished | May 30 03:57:22 PM PDT 24 |
| Peak memory | 573148 kb |
| Host | smart-3d765c86-15c2-4978-af82-d5279cce6570 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321412931 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.1321412931 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.2789959554 |
| Short name | T1529 |
| Test name | |
| Test status | |
| Simulation time | 568114586 ps |
| CPU time | 220.64 seconds |
| Started | May 30 03:53:36 PM PDT 24 |
| Finished | May 30 03:57:18 PM PDT 24 |
| Peak memory | 573164 kb |
| Host | smart-de2b3b74-a0b2-4c35-b48a-06c8b29b6243 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789959554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all _with_rand_reset.2789959554 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.2409808675 |
| Short name | T2361 |
| Test name | |
| Test status | |
| Simulation time | 3518162562 ps |
| CPU time | 375.7 seconds |
| Started | May 30 03:53:38 PM PDT 24 |
| Finished | May 30 03:59:55 PM PDT 24 |
| Peak memory | 574736 kb |
| Host | smart-5e45adaa-a781-4e08-8049-acb6ee7acd7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409808675 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_al l_with_reset_error.2409808675 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_unmapped_addr.1860361899 |
| Short name | T1951 |
| Test name | |
| Test status | |
| Simulation time | 88927555 ps |
| CPU time | 6.68 seconds |
| Started | May 30 03:53:37 PM PDT 24 |
| Finished | May 30 03:53:45 PM PDT 24 |
| Peak memory | 563432 kb |
| Host | smart-7022d07a-fcfd-402b-8165-5b6d285d8ef7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860361899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.1860361899 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device.3456972888 |
| Short name | T1389 |
| Test name | |
| Test status | |
| Simulation time | 297419329 ps |
| CPU time | 25.52 seconds |
| Started | May 30 03:53:37 PM PDT 24 |
| Finished | May 30 03:54:03 PM PDT 24 |
| Peak memory | 572992 kb |
| Host | smart-5527ee12-0e33-443e-83ae-31b4d9c7903f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456972888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device .3456972888 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.1402336408 |
| Short name | T2042 |
| Test name | |
| Test status | |
| Simulation time | 77215216966 ps |
| CPU time | 1431.15 seconds |
| Started | May 30 03:53:37 PM PDT 24 |
| Finished | May 30 04:17:29 PM PDT 24 |
| Peak memory | 573320 kb |
| Host | smart-a17333e9-f112-4ae7-819b-7e48292d7dd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402336408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_ device_slow_rsp.1402336408 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.2931517641 |
| Short name | T2155 |
| Test name | |
| Test status | |
| Simulation time | 142553055 ps |
| CPU time | 19.53 seconds |
| Started | May 30 03:53:51 PM PDT 24 |
| Finished | May 30 03:54:11 PM PDT 24 |
| Peak memory | 572880 kb |
| Host | smart-e06f76de-f2ac-495e-9cc1-12a3517332e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931517641 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_add r.2931517641 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_random.3670485066 |
| Short name | T2491 |
| Test name | |
| Test status | |
| Simulation time | 934433867 ps |
| CPU time | 31.39 seconds |
| Started | May 30 03:53:46 PM PDT 24 |
| Finished | May 30 03:54:19 PM PDT 24 |
| Peak memory | 572840 kb |
| Host | smart-847e3345-5073-478f-8a84-0ed096570146 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670485066 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.3670485066 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random.2637179341 |
| Short name | T2808 |
| Test name | |
| Test status | |
| Simulation time | 98079190 ps |
| CPU time | 11.06 seconds |
| Started | May 30 03:53:36 PM PDT 24 |
| Finished | May 30 03:53:48 PM PDT 24 |
| Peak memory | 572976 kb |
| Host | smart-314eb949-c8bf-4b01-a431-14a68468bea7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637179341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random.2637179341 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_large_delays.2379984212 |
| Short name | T2201 |
| Test name | |
| Test status | |
| Simulation time | 5268773712 ps |
| CPU time | 55.02 seconds |
| Started | May 30 03:53:39 PM PDT 24 |
| Finished | May 30 03:54:35 PM PDT 24 |
| Peak memory | 564948 kb |
| Host | smart-96ba275e-c272-4902-bcf8-336686833758 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379984212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.2379984212 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_slow_rsp.566051323 |
| Short name | T2629 |
| Test name | |
| Test status | |
| Simulation time | 18549430902 ps |
| CPU time | 340.32 seconds |
| Started | May 30 03:53:37 PM PDT 24 |
| Finished | May 30 03:59:18 PM PDT 24 |
| Peak memory | 573176 kb |
| Host | smart-ea27b1fb-f3f1-4fd5-9334-b702020d2aad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566051323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.566051323 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_zero_delays.1155768099 |
| Short name | T1765 |
| Test name | |
| Test status | |
| Simulation time | 91983103 ps |
| CPU time | 11.82 seconds |
| Started | May 30 03:53:37 PM PDT 24 |
| Finished | May 30 03:53:50 PM PDT 24 |
| Peak memory | 572868 kb |
| Host | smart-74fc6a8c-4929-4a44-9210-317ae845c2ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155768099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_del ays.1155768099 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_same_source.2587808065 |
| Short name | T1457 |
| Test name | |
| Test status | |
| Simulation time | 617088606 ps |
| CPU time | 21.6 seconds |
| Started | May 30 03:53:39 PM PDT 24 |
| Finished | May 30 03:54:02 PM PDT 24 |
| Peak memory | 573032 kb |
| Host | smart-4db23d36-e426-44ee-8dcb-1c77cad9b4a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587808065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.2587808065 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke.2256327290 |
| Short name | T1937 |
| Test name | |
| Test status | |
| Simulation time | 212270097 ps |
| CPU time | 9.05 seconds |
| Started | May 30 03:53:36 PM PDT 24 |
| Finished | May 30 03:53:46 PM PDT 24 |
| Peak memory | 564816 kb |
| Host | smart-9ec10417-d652-4b82-8c6c-25143a49a9d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256327290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.2256327290 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_large_delays.1625538298 |
| Short name | T2687 |
| Test name | |
| Test status | |
| Simulation time | 9895137121 ps |
| CPU time | 106.78 seconds |
| Started | May 30 03:53:35 PM PDT 24 |
| Finished | May 30 03:55:22 PM PDT 24 |
| Peak memory | 564972 kb |
| Host | smart-96f3e82f-a997-4652-b38b-35dbf5b5f41c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625538298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.1625538298 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.1363563870 |
| Short name | T1769 |
| Test name | |
| Test status | |
| Simulation time | 6148860969 ps |
| CPU time | 96.75 seconds |
| Started | May 30 03:53:38 PM PDT 24 |
| Finished | May 30 03:55:16 PM PDT 24 |
| Peak memory | 564920 kb |
| Host | smart-d5b98244-f00c-4e3a-bf11-40716e210851 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363563870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.1363563870 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_zero_delays.2138717817 |
| Short name | T1811 |
| Test name | |
| Test status | |
| Simulation time | 52612967 ps |
| CPU time | 6.21 seconds |
| Started | May 30 03:53:36 PM PDT 24 |
| Finished | May 30 03:53:43 PM PDT 24 |
| Peak memory | 564808 kb |
| Host | smart-ac10d97c-5d1b-4a86-aba0-52823d571b07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138717817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delay s.2138717817 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all.4129008936 |
| Short name | T1687 |
| Test name | |
| Test status | |
| Simulation time | 452891120 ps |
| CPU time | 44.16 seconds |
| Started | May 30 03:53:46 PM PDT 24 |
| Finished | May 30 03:54:31 PM PDT 24 |
| Peak memory | 573084 kb |
| Host | smart-535e36f9-38b7-4892-96aa-1a24c25edbeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129008936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.4129008936 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_error.52794106 |
| Short name | T1493 |
| Test name | |
| Test status | |
| Simulation time | 1178979085 ps |
| CPU time | 85.37 seconds |
| Started | May 30 03:53:50 PM PDT 24 |
| Finished | May 30 03:55:16 PM PDT 24 |
| Peak memory | 572996 kb |
| Host | smart-bae8e3cb-be4b-4fc4-9151-5ef4835fbb43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52794106 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.52794106 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.1883172455 |
| Short name | T2638 |
| Test name | |
| Test status | |
| Simulation time | 726609061 ps |
| CPU time | 255.04 seconds |
| Started | May 30 03:53:51 PM PDT 24 |
| Finished | May 30 03:58:07 PM PDT 24 |
| Peak memory | 581296 kb |
| Host | smart-92d0dc49-42e5-425a-b568-6f88f34725f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883172455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all _with_rand_reset.1883172455 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.3526524226 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 4500428123 ps |
| CPU time | 444.29 seconds |
| Started | May 30 03:53:48 PM PDT 24 |
| Finished | May 30 04:01:13 PM PDT 24 |
| Peak memory | 581332 kb |
| Host | smart-e5a9fa2a-9c48-437a-a103-c9e6d4e5e505 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526524226 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_al l_with_reset_error.3526524226 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_unmapped_addr.1263067194 |
| Short name | T1949 |
| Test name | |
| Test status | |
| Simulation time | 110428000 ps |
| CPU time | 13.99 seconds |
| Started | May 30 03:53:49 PM PDT 24 |
| Finished | May 30 03:54:04 PM PDT 24 |
| Peak memory | 573072 kb |
| Host | smart-62e87733-08a7-4e98-8b4a-1199ce501af5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263067194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.1263067194 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device.3957762625 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 1322118289 ps |
| CPU time | 59.55 seconds |
| Started | May 30 03:53:46 PM PDT 24 |
| Finished | May 30 03:54:47 PM PDT 24 |
| Peak memory | 572976 kb |
| Host | smart-2e990ebf-2356-4fd9-9dde-e8c444fe2fc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957762625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device .3957762625 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.1100587424 |
| Short name | T2642 |
| Test name | |
| Test status | |
| Simulation time | 47632777450 ps |
| CPU time | 849.06 seconds |
| Started | May 30 03:53:52 PM PDT 24 |
| Finished | May 30 04:08:01 PM PDT 24 |
| Peak memory | 573276 kb |
| Host | smart-24342da4-f128-4be8-a584-ca9497dd56b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100587424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_ device_slow_rsp.1100587424 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.4150495264 |
| Short name | T1395 |
| Test name | |
| Test status | |
| Simulation time | 347558018 ps |
| CPU time | 37.53 seconds |
| Started | May 30 03:54:06 PM PDT 24 |
| Finished | May 30 03:54:44 PM PDT 24 |
| Peak memory | 572908 kb |
| Host | smart-98665264-4143-41e3-a657-a698ccfa2c2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150495264 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_add r.4150495264 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_random.3563918586 |
| Short name | T2726 |
| Test name | |
| Test status | |
| Simulation time | 577117709 ps |
| CPU time | 55.41 seconds |
| Started | May 30 03:53:51 PM PDT 24 |
| Finished | May 30 03:54:47 PM PDT 24 |
| Peak memory | 573952 kb |
| Host | smart-147bebf9-2c7e-4362-a7eb-3d34d521ec8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563918586 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.3563918586 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random.1982816582 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 944906951 ps |
| CPU time | 32.83 seconds |
| Started | May 30 03:53:47 PM PDT 24 |
| Finished | May 30 03:54:21 PM PDT 24 |
| Peak memory | 573040 kb |
| Host | smart-e426b83c-ff0f-44c5-bda2-8dc9e6eb410a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982816582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random.1982816582 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_large_delays.191949702 |
| Short name | T2480 |
| Test name | |
| Test status | |
| Simulation time | 60775324388 ps |
| CPU time | 622.18 seconds |
| Started | May 30 03:53:46 PM PDT 24 |
| Finished | May 30 04:04:10 PM PDT 24 |
| Peak memory | 573132 kb |
| Host | smart-94ac06e5-42f2-4327-8309-e4d3d267422f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191949702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.191949702 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_slow_rsp.2747178029 |
| Short name | T2838 |
| Test name | |
| Test status | |
| Simulation time | 60139141507 ps |
| CPU time | 1041.1 seconds |
| Started | May 30 03:53:50 PM PDT 24 |
| Finished | May 30 04:11:12 PM PDT 24 |
| Peak memory | 573076 kb |
| Host | smart-14394667-a3e8-4c27-ae7e-d5e1bdd9f221 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747178029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.2747178029 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_zero_delays.2021645854 |
| Short name | T2195 |
| Test name | |
| Test status | |
| Simulation time | 40446939 ps |
| CPU time | 6.31 seconds |
| Started | May 30 03:53:46 PM PDT 24 |
| Finished | May 30 03:53:54 PM PDT 24 |
| Peak memory | 564800 kb |
| Host | smart-798307bf-d6f3-442d-aa66-cea9343f6cc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021645854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_del ays.2021645854 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_same_source.1508126638 |
| Short name | T1380 |
| Test name | |
| Test status | |
| Simulation time | 283636073 ps |
| CPU time | 22.91 seconds |
| Started | May 30 03:53:47 PM PDT 24 |
| Finished | May 30 03:54:11 PM PDT 24 |
| Peak memory | 572956 kb |
| Host | smart-564bf772-1e77-489c-b2a1-4da78ccfe5d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508126638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.1508126638 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke.976590482 |
| Short name | T2574 |
| Test name | |
| Test status | |
| Simulation time | 178563363 ps |
| CPU time | 8.52 seconds |
| Started | May 30 03:53:48 PM PDT 24 |
| Finished | May 30 03:53:57 PM PDT 24 |
| Peak memory | 563264 kb |
| Host | smart-ea033ea2-66bd-47de-a00f-e1e428cf68dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976590482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.976590482 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_large_delays.2100573880 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 6625698717 ps |
| CPU time | 74.46 seconds |
| Started | May 30 03:53:48 PM PDT 24 |
| Finished | May 30 03:55:03 PM PDT 24 |
| Peak memory | 564964 kb |
| Host | smart-c50f870f-9ddb-46b1-9251-3ae96f370be9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100573880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.2100573880 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.41835727 |
| Short name | T2009 |
| Test name | |
| Test status | |
| Simulation time | 3720761593 ps |
| CPU time | 72.31 seconds |
| Started | May 30 03:53:47 PM PDT 24 |
| Finished | May 30 03:55:00 PM PDT 24 |
| Peak memory | 564872 kb |
| Host | smart-f7593b1d-c906-4f2d-bb8f-d083f6de0a53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41835727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.41835727 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_zero_delays.2075003591 |
| Short name | T1461 |
| Test name | |
| Test status | |
| Simulation time | 45626716 ps |
| CPU time | 6.93 seconds |
| Started | May 30 03:53:46 PM PDT 24 |
| Finished | May 30 03:53:53 PM PDT 24 |
| Peak memory | 563372 kb |
| Host | smart-a5315809-2069-4255-bf41-2bd87189464d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075003591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delay s.2075003591 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all.674584232 |
| Short name | T2513 |
| Test name | |
| Test status | |
| Simulation time | 8653441948 ps |
| CPU time | 360.56 seconds |
| Started | May 30 03:54:03 PM PDT 24 |
| Finished | May 30 04:00:05 PM PDT 24 |
| Peak memory | 573252 kb |
| Host | smart-9c462697-9ffc-4cd1-91b9-a2bc66ca469d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674584232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.674584232 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.716784655 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 10167066553 ps |
| CPU time | 368.03 seconds |
| Started | May 30 03:54:02 PM PDT 24 |
| Finished | May 30 04:00:11 PM PDT 24 |
| Peak memory | 576408 kb |
| Host | smart-b0767151-7550-4a19-b70e-044275b6d0a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716784655 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.716784655 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.1119472169 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 173980627 ps |
| CPU time | 47.86 seconds |
| Started | May 30 03:54:02 PM PDT 24 |
| Finished | May 30 03:54:51 PM PDT 24 |
| Peak memory | 573064 kb |
| Host | smart-d2bc597d-2503-4938-a923-d4f5b6fe9f71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119472169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all _with_rand_reset.1119472169 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.113720952 |
| Short name | T1884 |
| Test name | |
| Test status | |
| Simulation time | 4281523356 ps |
| CPU time | 526.92 seconds |
| Started | May 30 03:54:05 PM PDT 24 |
| Finished | May 30 04:02:53 PM PDT 24 |
| Peak memory | 574652 kb |
| Host | smart-6a4a13fb-5257-43cf-83c9-5f952afb86c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113720952 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all _with_reset_error.113720952 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.1265334765 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 1010918350 ps |
| CPU time | 40.9 seconds |
| Started | May 30 03:53:49 PM PDT 24 |
| Finished | May 30 03:54:31 PM PDT 24 |
| Peak memory | 573084 kb |
| Host | smart-53aaad88-8f41-40a7-8dfd-dea842f7f051 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265334765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.1265334765 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device.1708122438 |
| Short name | T2611 |
| Test name | |
| Test status | |
| Simulation time | 243412390 ps |
| CPU time | 13.3 seconds |
| Started | May 30 03:54:02 PM PDT 24 |
| Finished | May 30 03:54:17 PM PDT 24 |
| Peak memory | 563348 kb |
| Host | smart-34a4977d-e750-4583-a1f8-efed8b365a0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708122438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device .1708122438 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.3366883802 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 87330295804 ps |
| CPU time | 1671.23 seconds |
| Started | May 30 03:54:03 PM PDT 24 |
| Finished | May 30 04:21:55 PM PDT 24 |
| Peak memory | 573200 kb |
| Host | smart-d49ea982-2777-4cd5-8b16-6e0546e1fab2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366883802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_ device_slow_rsp.3366883802 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.1502711786 |
| Short name | T1464 |
| Test name | |
| Test status | |
| Simulation time | 566677476 ps |
| CPU time | 24.87 seconds |
| Started | May 30 03:54:14 PM PDT 24 |
| Finished | May 30 03:54:40 PM PDT 24 |
| Peak memory | 572864 kb |
| Host | smart-72e25638-bc45-461d-81e1-a1c741deaeaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502711786 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_add r.1502711786 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_random.3395243289 |
| Short name | T1391 |
| Test name | |
| Test status | |
| Simulation time | 532580328 ps |
| CPU time | 40.53 seconds |
| Started | May 30 03:54:17 PM PDT 24 |
| Finished | May 30 03:54:59 PM PDT 24 |
| Peak memory | 572932 kb |
| Host | smart-faac2cef-03d0-4038-8785-d2a8dba41420 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395243289 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.3395243289 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random.1086978536 |
| Short name | T1847 |
| Test name | |
| Test status | |
| Simulation time | 855654782 ps |
| CPU time | 31.95 seconds |
| Started | May 30 03:54:01 PM PDT 24 |
| Finished | May 30 03:54:34 PM PDT 24 |
| Peak memory | 573076 kb |
| Host | smart-fa42645d-202f-499e-b2a9-b7cdb9092fb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086978536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random.1086978536 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_large_delays.1168238199 |
| Short name | T1501 |
| Test name | |
| Test status | |
| Simulation time | 54115803925 ps |
| CPU time | 546.7 seconds |
| Started | May 30 03:54:03 PM PDT 24 |
| Finished | May 30 04:03:11 PM PDT 24 |
| Peak memory | 573212 kb |
| Host | smart-e3aaffae-16aa-45f4-b2b2-2cc9c4228b97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168238199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.1168238199 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_slow_rsp.4017070032 |
| Short name | T1564 |
| Test name | |
| Test status | |
| Simulation time | 31126380533 ps |
| CPU time | 554.1 seconds |
| Started | May 30 03:54:03 PM PDT 24 |
| Finished | May 30 04:03:18 PM PDT 24 |
| Peak memory | 573200 kb |
| Host | smart-f0506b12-8141-4f73-92c8-6e39c0a9bdef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017070032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.4017070032 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.3186331525 |
| Short name | T1613 |
| Test name | |
| Test status | |
| Simulation time | 619960272 ps |
| CPU time | 46.86 seconds |
| Started | May 30 03:54:03 PM PDT 24 |
| Finished | May 30 03:54:51 PM PDT 24 |
| Peak memory | 573028 kb |
| Host | smart-0c2f0aee-85bb-4e4d-9baa-e86fd7a7beda |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186331525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_del ays.3186331525 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_same_source.1764591775 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 321637939 ps |
| CPU time | 25.59 seconds |
| Started | May 30 03:54:03 PM PDT 24 |
| Finished | May 30 03:54:30 PM PDT 24 |
| Peak memory | 573064 kb |
| Host | smart-7d2db5ce-fa3c-4f22-92af-e307c526eb63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764591775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.1764591775 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke.2493998624 |
| Short name | T1394 |
| Test name | |
| Test status | |
| Simulation time | 49209987 ps |
| CPU time | 6.43 seconds |
| Started | May 30 03:54:04 PM PDT 24 |
| Finished | May 30 03:54:11 PM PDT 24 |
| Peak memory | 564836 kb |
| Host | smart-45b94735-c4a6-40f0-b6ef-1e433ae07ed1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493998624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.2493998624 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_large_delays.1255889171 |
| Short name | T1907 |
| Test name | |
| Test status | |
| Simulation time | 7795382992 ps |
| CPU time | 87.85 seconds |
| Started | May 30 03:54:04 PM PDT 24 |
| Finished | May 30 03:55:32 PM PDT 24 |
| Peak memory | 564940 kb |
| Host | smart-5bb06420-5dbd-4ff8-83f2-d261d8c670df |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255889171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.1255889171 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.2510934558 |
| Short name | T2802 |
| Test name | |
| Test status | |
| Simulation time | 5915360358 ps |
| CPU time | 108.37 seconds |
| Started | May 30 03:54:03 PM PDT 24 |
| Finished | May 30 03:55:53 PM PDT 24 |
| Peak memory | 563548 kb |
| Host | smart-a9ccaf76-5331-42d7-a0a6-12f43d5b4aec |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510934558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.2510934558 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_zero_delays.1743305033 |
| Short name | T2807 |
| Test name | |
| Test status | |
| Simulation time | 49298804 ps |
| CPU time | 6.53 seconds |
| Started | May 30 03:54:02 PM PDT 24 |
| Finished | May 30 03:54:09 PM PDT 24 |
| Peak memory | 563352 kb |
| Host | smart-4136493b-cbac-476c-8480-a69af37ee47f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743305033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delay s.1743305033 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.1709548758 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 12994517192 ps |
| CPU time | 502.04 seconds |
| Started | May 30 03:54:15 PM PDT 24 |
| Finished | May 30 04:02:39 PM PDT 24 |
| Peak memory | 577928 kb |
| Host | smart-ed11857e-515b-4f10-8633-6bcf71c7a2b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709548758 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.1709548758 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.2543250771 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 217863040 ps |
| CPU time | 107.73 seconds |
| Started | May 30 03:54:15 PM PDT 24 |
| Finished | May 30 03:56:04 PM PDT 24 |
| Peak memory | 573112 kb |
| Host | smart-aa199f4c-21bf-4316-aba0-924cd67bb695 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543250771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all _with_rand_reset.2543250771 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.2589935142 |
| Short name | T2072 |
| Test name | |
| Test status | |
| Simulation time | 1520902205 ps |
| CPU time | 204.78 seconds |
| Started | May 30 03:54:13 PM PDT 24 |
| Finished | May 30 03:57:39 PM PDT 24 |
| Peak memory | 578164 kb |
| Host | smart-63540319-2b38-4490-9124-6166df37a9cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589935142 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_al l_with_reset_error.2589935142 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_unmapped_addr.3870078055 |
| Short name | T1946 |
| Test name | |
| Test status | |
| Simulation time | 472535480 ps |
| CPU time | 19.19 seconds |
| Started | May 30 03:54:11 PM PDT 24 |
| Finished | May 30 03:54:31 PM PDT 24 |
| Peak memory | 573076 kb |
| Host | smart-edb7d8f8-1cff-4528-bf7a-29a558ec1d99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870078055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.3870078055 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_csr_rw.935733194 |
| Short name | T1826 |
| Test name | |
| Test status | |
| Simulation time | 4620726104 ps |
| CPU time | 301.88 seconds |
| Started | May 30 03:48:57 PM PDT 24 |
| Finished | May 30 03:54:01 PM PDT 24 |
| Peak memory | 591648 kb |
| Host | smart-fd8254fc-39f0-489b-ab2a-0f38e5e9c466 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935733194 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_rw.935733194 |
| Directory | /workspace/5.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.2174583183 |
| Short name | T1436 |
| Test name | |
| Test status | |
| Simulation time | 16480680018 ps |
| CPU time | 1925.73 seconds |
| Started | May 30 03:48:38 PM PDT 24 |
| Finished | May 30 04:20:46 PM PDT 24 |
| Peak memory | 586344 kb |
| Host | smart-03e113c4-6d11-4d99-8dd6-bf94b10eceee |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174583183 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 5.chip_same_csr_outstanding.2174583183 |
| Directory | /workspace/5.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_tl_errors.4273738422 |
| Short name | T2791 |
| Test name | |
| Test status | |
| Simulation time | 4650419154 ps |
| CPU time | 335.74 seconds |
| Started | May 30 03:48:41 PM PDT 24 |
| Finished | May 30 03:54:18 PM PDT 24 |
| Peak memory | 594072 kb |
| Host | smart-29a6c63b-75f4-4d2f-b1e0-52ba36986171 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273738422 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_tl_errors.4273738422 |
| Directory | /workspace/5.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device.1546554516 |
| Short name | T2584 |
| Test name | |
| Test status | |
| Simulation time | 380784481 ps |
| CPU time | 23.73 seconds |
| Started | May 30 03:48:53 PM PDT 24 |
| Finished | May 30 03:49:18 PM PDT 24 |
| Peak memory | 572940 kb |
| Host | smart-678876de-0abc-49bc-83bb-8d5c4d41cf7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546554516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device. 1546554516 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.1205906547 |
| Short name | T2656 |
| Test name | |
| Test status | |
| Simulation time | 130886454531 ps |
| CPU time | 2487.51 seconds |
| Started | May 30 03:48:46 PM PDT 24 |
| Finished | May 30 04:30:15 PM PDT 24 |
| Peak memory | 573292 kb |
| Host | smart-4d27d4ec-228f-4131-8306-2fc9b3fd333d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205906547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_d evice_slow_rsp.1205906547 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.3305070923 |
| Short name | T2526 |
| Test name | |
| Test status | |
| Simulation time | 1153900577 ps |
| CPU time | 42.77 seconds |
| Started | May 30 03:49:02 PM PDT 24 |
| Finished | May 30 03:49:46 PM PDT 24 |
| Peak memory | 573960 kb |
| Host | smart-cd102b68-117c-4509-bf3d-430468da2a37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305070923 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr .3305070923 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_random.4017641141 |
| Short name | T2623 |
| Test name | |
| Test status | |
| Simulation time | 1800455711 ps |
| CPU time | 62.45 seconds |
| Started | May 30 03:48:57 PM PDT 24 |
| Finished | May 30 03:50:01 PM PDT 24 |
| Peak memory | 573936 kb |
| Host | smart-fe9ce06d-33dd-42e7-bf00-79302bed3dad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017641141 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.4017641141 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random.553708408 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 96337887 ps |
| CPU time | 10.29 seconds |
| Started | May 30 03:48:39 PM PDT 24 |
| Finished | May 30 03:48:51 PM PDT 24 |
| Peak memory | 572968 kb |
| Host | smart-2b9bca40-463e-43cf-b8e3-444881952441 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553708408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random.553708408 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_large_delays.4012725397 |
| Short name | T2274 |
| Test name | |
| Test status | |
| Simulation time | 11916926982 ps |
| CPU time | 130.34 seconds |
| Started | May 30 03:48:49 PM PDT 24 |
| Finished | May 30 03:51:01 PM PDT 24 |
| Peak memory | 564992 kb |
| Host | smart-bca793d4-ac8e-4e4f-9a5a-592e0d57be38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012725397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.4012725397 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.643592347 |
| Short name | T1833 |
| Test name | |
| Test status | |
| Simulation time | 6308092143 ps |
| CPU time | 103.24 seconds |
| Started | May 30 03:48:39 PM PDT 24 |
| Finished | May 30 03:50:24 PM PDT 24 |
| Peak memory | 563552 kb |
| Host | smart-669e1d73-b98d-4ece-9395-cddbc057ef25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643592347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.643592347 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_zero_delays.412792132 |
| Short name | T1719 |
| Test name | |
| Test status | |
| Simulation time | 595195733 ps |
| CPU time | 49.93 seconds |
| Started | May 30 03:48:41 PM PDT 24 |
| Finished | May 30 03:49:32 PM PDT 24 |
| Peak memory | 572952 kb |
| Host | smart-b2fdfcba-41bf-426f-840c-d833713a19a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412792132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delay s.412792132 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_same_source.2665568435 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 1518395280 ps |
| CPU time | 46.41 seconds |
| Started | May 30 03:48:54 PM PDT 24 |
| Finished | May 30 03:49:42 PM PDT 24 |
| Peak memory | 572868 kb |
| Host | smart-19608a19-26bb-4cda-a44e-dbe245d311d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665568435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.2665568435 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke.4119680287 |
| Short name | T2016 |
| Test name | |
| Test status | |
| Simulation time | 51468232 ps |
| CPU time | 6.34 seconds |
| Started | May 30 03:48:40 PM PDT 24 |
| Finished | May 30 03:48:48 PM PDT 24 |
| Peak memory | 564832 kb |
| Host | smart-4b501ebb-7e54-4d9d-a796-0af5c1d5e0dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119680287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.4119680287 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_large_delays.753474372 |
| Short name | T1690 |
| Test name | |
| Test status | |
| Simulation time | 9808346587 ps |
| CPU time | 97.66 seconds |
| Started | May 30 03:48:38 PM PDT 24 |
| Finished | May 30 03:50:18 PM PDT 24 |
| Peak memory | 564960 kb |
| Host | smart-9c87d5e3-8df1-41d7-979a-01a524bb2a62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753474372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.753474372 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.1068460517 |
| Short name | T2689 |
| Test name | |
| Test status | |
| Simulation time | 5548159860 ps |
| CPU time | 87.03 seconds |
| Started | May 30 03:48:52 PM PDT 24 |
| Finished | May 30 03:50:21 PM PDT 24 |
| Peak memory | 563488 kb |
| Host | smart-62d778fd-cb5b-4994-b710-621dcb5e878e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068460517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.1068460517 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_zero_delays.3594463689 |
| Short name | T2134 |
| Test name | |
| Test status | |
| Simulation time | 39315328 ps |
| CPU time | 5.5 seconds |
| Started | May 30 03:48:54 PM PDT 24 |
| Finished | May 30 03:49:01 PM PDT 24 |
| Peak memory | 564768 kb |
| Host | smart-645b9eeb-ac47-42e1-9cc0-c683d6c753cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594463689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays .3594463689 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all.844755496 |
| Short name | T2670 |
| Test name | |
| Test status | |
| Simulation time | 3867948995 ps |
| CPU time | 134.24 seconds |
| Started | May 30 03:49:01 PM PDT 24 |
| Finished | May 30 03:51:18 PM PDT 24 |
| Peak memory | 573216 kb |
| Host | smart-e5fc8333-c22a-435c-85bd-04c269cc1805 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844755496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.844755496 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.1583059560 |
| Short name | T2186 |
| Test name | |
| Test status | |
| Simulation time | 2630696130 ps |
| CPU time | 192.44 seconds |
| Started | May 30 03:48:58 PM PDT 24 |
| Finished | May 30 03:52:12 PM PDT 24 |
| Peak memory | 573100 kb |
| Host | smart-463106ae-cb67-4878-a7fa-a66b86b53995 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583059560 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.1583059560 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.820142452 |
| Short name | T2583 |
| Test name | |
| Test status | |
| Simulation time | 294384340 ps |
| CPU time | 77.11 seconds |
| Started | May 30 03:49:02 PM PDT 24 |
| Finished | May 30 03:50:21 PM PDT 24 |
| Peak memory | 575208 kb |
| Host | smart-e4a1524e-379f-4ce1-8c72-bddd00cbddb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820142452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_w ith_rand_reset.820142452 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.2865973193 |
| Short name | T2444 |
| Test name | |
| Test status | |
| Simulation time | 157348219 ps |
| CPU time | 35.75 seconds |
| Started | May 30 03:49:03 PM PDT 24 |
| Finished | May 30 03:49:40 PM PDT 24 |
| Peak memory | 573084 kb |
| Host | smart-12d27bdd-dc06-4dbf-ab75-f3fee61ce070 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865973193 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all _with_reset_error.2865973193 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.3244165081 |
| Short name | T2516 |
| Test name | |
| Test status | |
| Simulation time | 1407920084 ps |
| CPU time | 57 seconds |
| Started | May 30 03:48:59 PM PDT 24 |
| Finished | May 30 03:49:57 PM PDT 24 |
| Peak memory | 573088 kb |
| Host | smart-be815b83-60b8-4112-aab1-3e1a9ad2ccdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244165081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.3244165081 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device.3532320043 |
| Short name | T1551 |
| Test name | |
| Test status | |
| Simulation time | 733694552 ps |
| CPU time | 57.32 seconds |
| Started | May 30 03:54:13 PM PDT 24 |
| Finished | May 30 03:55:12 PM PDT 24 |
| Peak memory | 573080 kb |
| Host | smart-5884357a-e926-4cb4-a7f3-8ea9e9d7d5c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532320043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device .3532320043 |
| Directory | /workspace/50.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.762904702 |
| Short name | T1883 |
| Test name | |
| Test status | |
| Simulation time | 92544296 ps |
| CPU time | 12.27 seconds |
| Started | May 30 03:54:12 PM PDT 24 |
| Finished | May 30 03:54:26 PM PDT 24 |
| Peak memory | 572860 kb |
| Host | smart-7674365b-60f7-43ea-9135-2e7481a3dd4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762904702 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_and_unmapped_addr .762904702 |
| Directory | /workspace/50.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_random.234101745 |
| Short name | T1496 |
| Test name | |
| Test status | |
| Simulation time | 1766940713 ps |
| CPU time | 56.79 seconds |
| Started | May 30 03:54:14 PM PDT 24 |
| Finished | May 30 03:55:12 PM PDT 24 |
| Peak memory | 572940 kb |
| Host | smart-ffe127c3-ee86-4ac3-b325-f1f5cdb13c0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234101745 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_random.234101745 |
| Directory | /workspace/50.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random.593336565 |
| Short name | T2441 |
| Test name | |
| Test status | |
| Simulation time | 371484787 ps |
| CPU time | 15.25 seconds |
| Started | May 30 03:54:14 PM PDT 24 |
| Finished | May 30 03:54:31 PM PDT 24 |
| Peak memory | 573060 kb |
| Host | smart-ee2318e0-a762-452c-a39b-3b94a5bf44aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593336565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random.593336565 |
| Directory | /workspace/50.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_large_delays.3526749155 |
| Short name | T1741 |
| Test name | |
| Test status | |
| Simulation time | 43874500376 ps |
| CPU time | 495.75 seconds |
| Started | May 30 03:54:13 PM PDT 24 |
| Finished | May 30 04:02:30 PM PDT 24 |
| Peak memory | 573116 kb |
| Host | smart-9363d2f8-ea95-4c11-aeb9-9737c17e696f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526749155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_large_delays.3526749155 |
| Directory | /workspace/50.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.4012914068 |
| Short name | T1722 |
| Test name | |
| Test status | |
| Simulation time | 54717992055 ps |
| CPU time | 1099 seconds |
| Started | May 30 03:54:12 PM PDT 24 |
| Finished | May 30 04:12:32 PM PDT 24 |
| Peak memory | 573228 kb |
| Host | smart-8dfb6960-4f41-4655-bb94-0aad3711da72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012914068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_slow_rsp.4012914068 |
| Directory | /workspace/50.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_zero_delays.1805233162 |
| Short name | T2144 |
| Test name | |
| Test status | |
| Simulation time | 36626427 ps |
| CPU time | 6.03 seconds |
| Started | May 30 03:54:13 PM PDT 24 |
| Finished | May 30 03:54:20 PM PDT 24 |
| Peak memory | 564784 kb |
| Host | smart-df3261af-e1c0-4d35-96af-fd603ea1244e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805233162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_zero_del ays.1805233162 |
| Directory | /workspace/50.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_same_source.3944507736 |
| Short name | T2272 |
| Test name | |
| Test status | |
| Simulation time | 1100867458 ps |
| CPU time | 32.22 seconds |
| Started | May 30 03:54:13 PM PDT 24 |
| Finished | May 30 03:54:46 PM PDT 24 |
| Peak memory | 572928 kb |
| Host | smart-7a05ed5b-f6ff-4b16-b79c-153754ad9d59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944507736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_same_source.3944507736 |
| Directory | /workspace/50.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke.3957149537 |
| Short name | T1427 |
| Test name | |
| Test status | |
| Simulation time | 43050273 ps |
| CPU time | 6.59 seconds |
| Started | May 30 03:54:14 PM PDT 24 |
| Finished | May 30 03:54:22 PM PDT 24 |
| Peak memory | 563372 kb |
| Host | smart-e05ee749-a26b-4d39-938b-8fa5e1452bc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957149537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke.3957149537 |
| Directory | /workspace/50.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_large_delays.3367228604 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 9173894957 ps |
| CPU time | 97.81 seconds |
| Started | May 30 03:54:12 PM PDT 24 |
| Finished | May 30 03:55:51 PM PDT 24 |
| Peak memory | 563488 kb |
| Host | smart-61e26b48-7e61-4ce4-b346-40d044efbebb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367228604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_large_delays.3367228604 |
| Directory | /workspace/50.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.1117571356 |
| Short name | T2269 |
| Test name | |
| Test status | |
| Simulation time | 2252655308 ps |
| CPU time | 40.71 seconds |
| Started | May 30 03:54:17 PM PDT 24 |
| Finished | May 30 03:54:58 PM PDT 24 |
| Peak memory | 564880 kb |
| Host | smart-0d3e2f7e-9058-47d4-8451-c4ff351a80ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117571356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_slow_rsp.1117571356 |
| Directory | /workspace/50.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_zero_delays.1399621477 |
| Short name | T1952 |
| Test name | |
| Test status | |
| Simulation time | 44782616 ps |
| CPU time | 5.79 seconds |
| Started | May 30 03:54:13 PM PDT 24 |
| Finished | May 30 03:54:20 PM PDT 24 |
| Peak memory | 564760 kb |
| Host | smart-648683e3-7f40-4d8e-bd41-8fc6de023bed |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399621477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_zero_delay s.1399621477 |
| Directory | /workspace/50.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all.2124212508 |
| Short name | T2843 |
| Test name | |
| Test status | |
| Simulation time | 2572141584 ps |
| CPU time | 202.78 seconds |
| Started | May 30 03:54:12 PM PDT 24 |
| Finished | May 30 03:57:36 PM PDT 24 |
| Peak memory | 573204 kb |
| Host | smart-066a55e8-8edb-4d8e-85e5-00a59aa26abd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124212508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all.2124212508 |
| Directory | /workspace/50.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.1286200407 |
| Short name | T2580 |
| Test name | |
| Test status | |
| Simulation time | 1913342750 ps |
| CPU time | 161.55 seconds |
| Started | May 30 03:54:14 PM PDT 24 |
| Finished | May 30 03:56:57 PM PDT 24 |
| Peak memory | 575120 kb |
| Host | smart-d092d1fb-db30-41dd-9a7d-b119788185f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286200407 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_error.1286200407 |
| Directory | /workspace/50.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.2685653651 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 196079657 ps |
| CPU time | 44.2 seconds |
| Started | May 30 03:54:24 PM PDT 24 |
| Finished | May 30 03:55:09 PM PDT 24 |
| Peak memory | 573096 kb |
| Host | smart-052b119d-eb63-4513-85c4-d6db34385742 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685653651 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_al l_with_reset_error.2685653651 |
| Directory | /workspace/50.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.2349119455 |
| Short name | T1634 |
| Test name | |
| Test status | |
| Simulation time | 666019294 ps |
| CPU time | 32.94 seconds |
| Started | May 30 03:54:13 PM PDT 24 |
| Finished | May 30 03:54:47 PM PDT 24 |
| Peak memory | 573044 kb |
| Host | smart-98e57a68-b08f-44d6-b033-490f8f099acd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349119455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_unmapped_addr.2349119455 |
| Directory | /workspace/50.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device.4221294631 |
| Short name | T1871 |
| Test name | |
| Test status | |
| Simulation time | 2437697247 ps |
| CPU time | 95.93 seconds |
| Started | May 30 03:54:24 PM PDT 24 |
| Finished | May 30 03:56:01 PM PDT 24 |
| Peak memory | 573108 kb |
| Host | smart-cc3f896b-ccda-4ab8-a5b4-af5a9adb8017 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221294631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device .4221294631 |
| Directory | /workspace/51.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.784335080 |
| Short name | T2227 |
| Test name | |
| Test status | |
| Simulation time | 26079950703 ps |
| CPU time | 456.32 seconds |
| Started | May 30 03:54:25 PM PDT 24 |
| Finished | May 30 04:02:02 PM PDT 24 |
| Peak memory | 573192 kb |
| Host | smart-025ae68a-948b-4b52-b6b3-64b08c76791d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784335080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_d evice_slow_rsp.784335080 |
| Directory | /workspace/51.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.561163448 |
| Short name | T2012 |
| Test name | |
| Test status | |
| Simulation time | 633374790 ps |
| CPU time | 25.23 seconds |
| Started | May 30 03:54:31 PM PDT 24 |
| Finished | May 30 03:54:58 PM PDT 24 |
| Peak memory | 572940 kb |
| Host | smart-8853fd04-0622-4a44-af5c-7e2f6924e6db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561163448 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_and_unmapped_addr .561163448 |
| Directory | /workspace/51.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_random.3875931806 |
| Short name | T1523 |
| Test name | |
| Test status | |
| Simulation time | 2104930440 ps |
| CPU time | 76.33 seconds |
| Started | May 30 03:54:24 PM PDT 24 |
| Finished | May 30 03:55:41 PM PDT 24 |
| Peak memory | 572784 kb |
| Host | smart-303ffdc5-840c-49e0-b6e4-ac62d3367293 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875931806 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_random.3875931806 |
| Directory | /workspace/51.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random.2490875094 |
| Short name | T2192 |
| Test name | |
| Test status | |
| Simulation time | 2262280982 ps |
| CPU time | 79.46 seconds |
| Started | May 30 03:54:24 PM PDT 24 |
| Finished | May 30 03:55:44 PM PDT 24 |
| Peak memory | 573056 kb |
| Host | smart-8bfe70a4-36ef-42b7-889e-3fa71070ccb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490875094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random.2490875094 |
| Directory | /workspace/51.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_large_delays.1494143707 |
| Short name | T2084 |
| Test name | |
| Test status | |
| Simulation time | 108733628633 ps |
| CPU time | 1113.3 seconds |
| Started | May 30 03:54:32 PM PDT 24 |
| Finished | May 30 04:13:06 PM PDT 24 |
| Peak memory | 573144 kb |
| Host | smart-749c19c1-52c4-4a0e-9536-3dcfc3291e73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494143707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_large_delays.1494143707 |
| Directory | /workspace/51.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_slow_rsp.23912009 |
| Short name | T1989 |
| Test name | |
| Test status | |
| Simulation time | 56483118270 ps |
| CPU time | 967.77 seconds |
| Started | May 30 03:54:31 PM PDT 24 |
| Finished | May 30 04:10:40 PM PDT 24 |
| Peak memory | 573216 kb |
| Host | smart-e3427232-36a6-4eec-aeca-02457ce078b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23912009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_slow_rsp.23912009 |
| Directory | /workspace/51.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_zero_delays.302743609 |
| Short name | T1968 |
| Test name | |
| Test status | |
| Simulation time | 468103608 ps |
| CPU time | 40.72 seconds |
| Started | May 30 03:54:28 PM PDT 24 |
| Finished | May 30 03:55:10 PM PDT 24 |
| Peak memory | 572924 kb |
| Host | smart-9133a911-d92e-47ca-abe7-8e08d21c0219 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302743609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_zero_dela ys.302743609 |
| Directory | /workspace/51.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_same_source.4187019687 |
| Short name | T1827 |
| Test name | |
| Test status | |
| Simulation time | 2783041591 ps |
| CPU time | 82.46 seconds |
| Started | May 30 03:54:41 PM PDT 24 |
| Finished | May 30 03:56:05 PM PDT 24 |
| Peak memory | 573132 kb |
| Host | smart-412d41f7-5918-44ce-9c5a-b1c1169e558e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187019687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_same_source.4187019687 |
| Directory | /workspace/51.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke.1783203591 |
| Short name | T2079 |
| Test name | |
| Test status | |
| Simulation time | 183358561 ps |
| CPU time | 8.19 seconds |
| Started | May 30 03:54:23 PM PDT 24 |
| Finished | May 30 03:54:32 PM PDT 24 |
| Peak memory | 564824 kb |
| Host | smart-68552af4-d24c-4336-bf74-e43ada6bec1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783203591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke.1783203591 |
| Directory | /workspace/51.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_large_delays.1012024262 |
| Short name | T2519 |
| Test name | |
| Test status | |
| Simulation time | 5158709437 ps |
| CPU time | 56.67 seconds |
| Started | May 30 03:54:26 PM PDT 24 |
| Finished | May 30 03:55:24 PM PDT 24 |
| Peak memory | 563484 kb |
| Host | smart-10bc092c-2827-4276-a23e-87b18a7e5e33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012024262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_large_delays.1012024262 |
| Directory | /workspace/51.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.1659747838 |
| Short name | T2810 |
| Test name | |
| Test status | |
| Simulation time | 4713249657 ps |
| CPU time | 82.5 seconds |
| Started | May 30 03:54:25 PM PDT 24 |
| Finished | May 30 03:55:49 PM PDT 24 |
| Peak memory | 564940 kb |
| Host | smart-552ce5e1-7853-4232-a185-354fb2f6400a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659747838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_slow_rsp.1659747838 |
| Directory | /workspace/51.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_zero_delays.1772305811 |
| Short name | T2428 |
| Test name | |
| Test status | |
| Simulation time | 49242513 ps |
| CPU time | 6.32 seconds |
| Started | May 30 03:54:42 PM PDT 24 |
| Finished | May 30 03:54:49 PM PDT 24 |
| Peak memory | 564808 kb |
| Host | smart-0f6e2cd1-5815-4fc4-83b9-a69e2ab9d81c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772305811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_zero_delay s.1772305811 |
| Directory | /workspace/51.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all.3706456345 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 6630606965 ps |
| CPU time | 231.63 seconds |
| Started | May 30 03:54:26 PM PDT 24 |
| Finished | May 30 03:58:19 PM PDT 24 |
| Peak memory | 573256 kb |
| Host | smart-918423e4-dd4e-423e-935c-fa3f4f813149 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706456345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all.3706456345 |
| Directory | /workspace/51.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.3371107481 |
| Short name | T2163 |
| Test name | |
| Test status | |
| Simulation time | 12847565212 ps |
| CPU time | 432.48 seconds |
| Started | May 30 03:54:27 PM PDT 24 |
| Finished | May 30 04:01:41 PM PDT 24 |
| Peak memory | 573204 kb |
| Host | smart-171e109b-6c91-47ce-b641-26cc8aeda239 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371107481 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_error.3371107481 |
| Directory | /workspace/51.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.2228580552 |
| Short name | T2535 |
| Test name | |
| Test status | |
| Simulation time | 502826954 ps |
| CPU time | 100.61 seconds |
| Started | May 30 03:54:24 PM PDT 24 |
| Finished | May 30 03:56:05 PM PDT 24 |
| Peak memory | 575200 kb |
| Host | smart-4de1c37b-3143-4c69-9c8c-540007a91f9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228580552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all _with_rand_reset.2228580552 |
| Directory | /workspace/51.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.1613255715 |
| Short name | T2606 |
| Test name | |
| Test status | |
| Simulation time | 212123923 ps |
| CPU time | 41.56 seconds |
| Started | May 30 03:54:27 PM PDT 24 |
| Finished | May 30 03:55:10 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-bd3e640e-2692-429d-ad71-621c654ae51c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613255715 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_al l_with_reset_error.1613255715 |
| Directory | /workspace/51.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.2757397013 |
| Short name | T2049 |
| Test name | |
| Test status | |
| Simulation time | 533362469 ps |
| CPU time | 24.56 seconds |
| Started | May 30 03:54:41 PM PDT 24 |
| Finished | May 30 03:55:07 PM PDT 24 |
| Peak memory | 573092 kb |
| Host | smart-8a8004df-e5ca-4eac-95f4-6731a2c7905e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757397013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_unmapped_addr.2757397013 |
| Directory | /workspace/51.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device.2827205003 |
| Short name | T2539 |
| Test name | |
| Test status | |
| Simulation time | 3354186018 ps |
| CPU time | 147.03 seconds |
| Started | May 30 03:54:23 PM PDT 24 |
| Finished | May 30 03:56:51 PM PDT 24 |
| Peak memory | 573128 kb |
| Host | smart-732b2c5b-a96a-41ee-9758-330069aade1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827205003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device .2827205003 |
| Directory | /workspace/52.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.3407619222 |
| Short name | T2671 |
| Test name | |
| Test status | |
| Simulation time | 107305949667 ps |
| CPU time | 1903.07 seconds |
| Started | May 30 03:54:41 PM PDT 24 |
| Finished | May 30 04:26:25 PM PDT 24 |
| Peak memory | 573216 kb |
| Host | smart-74cdbea8-98a3-406b-b2e0-4c0ec2f6946d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407619222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_ device_slow_rsp.3407619222 |
| Directory | /workspace/52.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.3677775257 |
| Short name | T1540 |
| Test name | |
| Test status | |
| Simulation time | 68478016 ps |
| CPU time | 10.45 seconds |
| Started | May 30 03:54:44 PM PDT 24 |
| Finished | May 30 03:54:56 PM PDT 24 |
| Peak memory | 573968 kb |
| Host | smart-b43fabf7-bfb8-4c35-b300-b9fa20cfa7c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677775257 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_and_unmapped_add r.3677775257 |
| Directory | /workspace/52.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_random.866811291 |
| Short name | T1434 |
| Test name | |
| Test status | |
| Simulation time | 599188298 ps |
| CPU time | 47.14 seconds |
| Started | May 30 03:54:42 PM PDT 24 |
| Finished | May 30 03:55:30 PM PDT 24 |
| Peak memory | 572964 kb |
| Host | smart-35518be2-6ede-4966-a969-e39d6087ce46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866811291 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_random.866811291 |
| Directory | /workspace/52.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random.92432838 |
| Short name | T2571 |
| Test name | |
| Test status | |
| Simulation time | 191967969 ps |
| CPU time | 18.78 seconds |
| Started | May 30 03:54:27 PM PDT 24 |
| Finished | May 30 03:54:47 PM PDT 24 |
| Peak memory | 573008 kb |
| Host | smart-8df4b104-2a89-4328-90c8-2c5e06abfcba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92432838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random.92432838 |
| Directory | /workspace/52.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_large_delays.3932224877 |
| Short name | T1616 |
| Test name | |
| Test status | |
| Simulation time | 16476937355 ps |
| CPU time | 177.61 seconds |
| Started | May 30 03:54:26 PM PDT 24 |
| Finished | May 30 03:57:25 PM PDT 24 |
| Peak memory | 572960 kb |
| Host | smart-50058f32-4f8f-4184-aafc-3cef5c79ed72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932224877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_large_delays.3932224877 |
| Directory | /workspace/52.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.3476584177 |
| Short name | T2021 |
| Test name | |
| Test status | |
| Simulation time | 4228964641 ps |
| CPU time | 73.34 seconds |
| Started | May 30 03:54:26 PM PDT 24 |
| Finished | May 30 03:55:41 PM PDT 24 |
| Peak memory | 563448 kb |
| Host | smart-a0f48fd5-745c-4139-b68c-1d4b1f7ebb95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476584177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_slow_rsp.3476584177 |
| Directory | /workspace/52.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_zero_delays.256085475 |
| Short name | T2036 |
| Test name | |
| Test status | |
| Simulation time | 187484169 ps |
| CPU time | 18.83 seconds |
| Started | May 30 03:54:26 PM PDT 24 |
| Finished | May 30 03:54:47 PM PDT 24 |
| Peak memory | 572864 kb |
| Host | smart-f68b3f19-89d6-4814-85ac-38be017109b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256085475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_zero_dela ys.256085475 |
| Directory | /workspace/52.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_same_source.3604770914 |
| Short name | T1614 |
| Test name | |
| Test status | |
| Simulation time | 774126089 ps |
| CPU time | 26.57 seconds |
| Started | May 30 03:54:25 PM PDT 24 |
| Finished | May 30 03:54:52 PM PDT 24 |
| Peak memory | 573084 kb |
| Host | smart-e50fe8e6-f632-449a-a3ca-cd5f5059eb0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604770914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_same_source.3604770914 |
| Directory | /workspace/52.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke.315975838 |
| Short name | T1784 |
| Test name | |
| Test status | |
| Simulation time | 54854966 ps |
| CPU time | 6.33 seconds |
| Started | May 30 03:54:30 PM PDT 24 |
| Finished | May 30 03:54:38 PM PDT 24 |
| Peak memory | 564820 kb |
| Host | smart-4a24ef5f-c117-4675-85fb-125a0597c862 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315975838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke.315975838 |
| Directory | /workspace/52.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.628117937 |
| Short name | T1339 |
| Test name | |
| Test status | |
| Simulation time | 6693678939 ps |
| CPU time | 67.21 seconds |
| Started | May 30 03:54:27 PM PDT 24 |
| Finished | May 30 03:55:35 PM PDT 24 |
| Peak memory | 563452 kb |
| Host | smart-10b83163-c68d-443c-a181-722ba04b131c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628117937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_large_delays.628117937 |
| Directory | /workspace/52.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.1732955599 |
| Short name | T1452 |
| Test name | |
| Test status | |
| Simulation time | 3033510758 ps |
| CPU time | 53.47 seconds |
| Started | May 30 03:54:24 PM PDT 24 |
| Finished | May 30 03:55:18 PM PDT 24 |
| Peak memory | 563400 kb |
| Host | smart-8e6c7439-91c1-4d14-8881-6e94b43c1362 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732955599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_slow_rsp.1732955599 |
| Directory | /workspace/52.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.3711108590 |
| Short name | T2253 |
| Test name | |
| Test status | |
| Simulation time | 45798783 ps |
| CPU time | 6.25 seconds |
| Started | May 30 03:54:31 PM PDT 24 |
| Finished | May 30 03:54:38 PM PDT 24 |
| Peak memory | 564820 kb |
| Host | smart-a5e64662-b087-4d13-b8a1-12e2b5d1d5a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711108590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_zero_delay s.3711108590 |
| Directory | /workspace/52.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all.2825319928 |
| Short name | T1798 |
| Test name | |
| Test status | |
| Simulation time | 2330078448 ps |
| CPU time | 176.78 seconds |
| Started | May 30 03:54:56 PM PDT 24 |
| Finished | May 30 03:57:54 PM PDT 24 |
| Peak memory | 573220 kb |
| Host | smart-d765c73c-c05b-48f5-81de-17c14474a20b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825319928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all.2825319928 |
| Directory | /workspace/52.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.2731948640 |
| Short name | T2110 |
| Test name | |
| Test status | |
| Simulation time | 12643365805 ps |
| CPU time | 363.84 seconds |
| Started | May 30 03:54:36 PM PDT 24 |
| Finished | May 30 04:00:41 PM PDT 24 |
| Peak memory | 573152 kb |
| Host | smart-74d6406f-337f-47c8-8952-f851c0969bd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731948640 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_error.2731948640 |
| Directory | /workspace/52.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.2648657126 |
| Short name | T2213 |
| Test name | |
| Test status | |
| Simulation time | 813215329 ps |
| CPU time | 207.78 seconds |
| Started | May 30 03:54:36 PM PDT 24 |
| Finished | May 30 03:58:05 PM PDT 24 |
| Peak memory | 573028 kb |
| Host | smart-ecb22765-af01-42d1-acf6-8d482107b53f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648657126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all _with_rand_reset.2648657126 |
| Directory | /workspace/52.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.376149904 |
| Short name | T2388 |
| Test name | |
| Test status | |
| Simulation time | 2572831418 ps |
| CPU time | 325.21 seconds |
| Started | May 30 03:54:36 PM PDT 24 |
| Finished | May 30 04:00:03 PM PDT 24 |
| Peak memory | 573108 kb |
| Host | smart-8a144426-baf1-459e-a4a5-94da628559ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376149904 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all _with_reset_error.376149904 |
| Directory | /workspace/52.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_unmapped_addr.2634611732 |
| Short name | T2124 |
| Test name | |
| Test status | |
| Simulation time | 54867074 ps |
| CPU time | 8.66 seconds |
| Started | May 30 03:54:30 PM PDT 24 |
| Finished | May 30 03:54:40 PM PDT 24 |
| Peak memory | 564900 kb |
| Host | smart-452ab249-f227-420b-a97e-ff1742b96f1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634611732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_unmapped_addr.2634611732 |
| Directory | /workspace/52.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device.2714759775 |
| Short name | T2374 |
| Test name | |
| Test status | |
| Simulation time | 787949225 ps |
| CPU time | 31.26 seconds |
| Started | May 30 03:54:56 PM PDT 24 |
| Finished | May 30 03:55:29 PM PDT 24 |
| Peak memory | 564732 kb |
| Host | smart-6d4be388-88ca-44f3-bdd8-42fd89be8b8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714759775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device .2714759775 |
| Directory | /workspace/53.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.2248513575 |
| Short name | T1749 |
| Test name | |
| Test status | |
| Simulation time | 31228612386 ps |
| CPU time | 518.47 seconds |
| Started | May 30 03:54:56 PM PDT 24 |
| Finished | May 30 04:03:36 PM PDT 24 |
| Peak memory | 573200 kb |
| Host | smart-ad9cba7b-f942-4fea-bc6e-3ea778b7a1de |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248513575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_ device_slow_rsp.2248513575 |
| Directory | /workspace/53.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.3597083079 |
| Short name | T2380 |
| Test name | |
| Test status | |
| Simulation time | 875595516 ps |
| CPU time | 34.63 seconds |
| Started | May 30 03:54:57 PM PDT 24 |
| Finished | May 30 03:55:33 PM PDT 24 |
| Peak memory | 572924 kb |
| Host | smart-4f1e5af4-14d9-4c80-b61a-5f9f1514a1bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597083079 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_and_unmapped_add r.3597083079 |
| Directory | /workspace/53.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_random.3880808108 |
| Short name | T2683 |
| Test name | |
| Test status | |
| Simulation time | 1763457735 ps |
| CPU time | 61.99 seconds |
| Started | May 30 03:54:37 PM PDT 24 |
| Finished | May 30 03:55:41 PM PDT 24 |
| Peak memory | 572948 kb |
| Host | smart-69c36230-580d-4979-a325-c95a22dc4e7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880808108 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_random.3880808108 |
| Directory | /workspace/53.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random.264864908 |
| Short name | T2424 |
| Test name | |
| Test status | |
| Simulation time | 974216903 ps |
| CPU time | 35.21 seconds |
| Started | May 30 03:54:56 PM PDT 24 |
| Finished | May 30 03:55:33 PM PDT 24 |
| Peak memory | 573048 kb |
| Host | smart-f8bd70ac-5231-436f-ac96-7ced60e55041 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264864908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random.264864908 |
| Directory | /workspace/53.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_large_delays.2434471573 |
| Short name | T1525 |
| Test name | |
| Test status | |
| Simulation time | 9492199173 ps |
| CPU time | 101.51 seconds |
| Started | May 30 03:54:53 PM PDT 24 |
| Finished | May 30 03:56:36 PM PDT 24 |
| Peak memory | 564972 kb |
| Host | smart-dc05af96-25a2-4df0-9c28-1e2dd891a677 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434471573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_large_delays.2434471573 |
| Directory | /workspace/53.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.563504642 |
| Short name | T2798 |
| Test name | |
| Test status | |
| Simulation time | 52894036512 ps |
| CPU time | 1034.98 seconds |
| Started | May 30 03:54:35 PM PDT 24 |
| Finished | May 30 04:11:51 PM PDT 24 |
| Peak memory | 573096 kb |
| Host | smart-543c2a95-d242-43a1-9d1c-3d9b311a538f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563504642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_slow_rsp.563504642 |
| Directory | /workspace/53.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_zero_delays.1789268068 |
| Short name | T2304 |
| Test name | |
| Test status | |
| Simulation time | 421356924 ps |
| CPU time | 39.64 seconds |
| Started | May 30 03:54:35 PM PDT 24 |
| Finished | May 30 03:55:16 PM PDT 24 |
| Peak memory | 573008 kb |
| Host | smart-8288fe25-9786-4a22-8a09-9dbe8856c883 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789268068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_zero_del ays.1789268068 |
| Directory | /workspace/53.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_same_source.1349165122 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 431108786 ps |
| CPU time | 14.46 seconds |
| Started | May 30 03:54:36 PM PDT 24 |
| Finished | May 30 03:54:52 PM PDT 24 |
| Peak memory | 573036 kb |
| Host | smart-4874e5f4-ba71-44ae-a88f-a42ab1c03ff7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349165122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_same_source.1349165122 |
| Directory | /workspace/53.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke.1349459741 |
| Short name | T1462 |
| Test name | |
| Test status | |
| Simulation time | 52163253 ps |
| CPU time | 6.62 seconds |
| Started | May 30 03:54:56 PM PDT 24 |
| Finished | May 30 03:55:04 PM PDT 24 |
| Peak memory | 563392 kb |
| Host | smart-c20b4f79-2be8-4599-95c0-dee6c4f29678 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349459741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke.1349459741 |
| Directory | /workspace/53.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_large_delays.869383139 |
| Short name | T1331 |
| Test name | |
| Test status | |
| Simulation time | 9463075706 ps |
| CPU time | 104.6 seconds |
| Started | May 30 03:54:37 PM PDT 24 |
| Finished | May 30 03:56:22 PM PDT 24 |
| Peak memory | 564932 kb |
| Host | smart-44c6109a-a435-4746-9ce2-9441bab4f7ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869383139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_large_delays.869383139 |
| Directory | /workspace/53.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.3208053409 |
| Short name | T2668 |
| Test name | |
| Test status | |
| Simulation time | 3959926076 ps |
| CPU time | 73.88 seconds |
| Started | May 30 03:54:35 PM PDT 24 |
| Finished | May 30 03:55:50 PM PDT 24 |
| Peak memory | 564900 kb |
| Host | smart-4969a120-9620-42fa-b04e-574ed1ea4fab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208053409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_slow_rsp.3208053409 |
| Directory | /workspace/53.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_zero_delays.541345761 |
| Short name | T1893 |
| Test name | |
| Test status | |
| Simulation time | 52424419 ps |
| CPU time | 6.48 seconds |
| Started | May 30 03:54:38 PM PDT 24 |
| Finished | May 30 03:54:46 PM PDT 24 |
| Peak memory | 564796 kb |
| Host | smart-33303217-74ac-4b72-b4ca-55eae85dc9a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541345761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_zero_delays .541345761 |
| Directory | /workspace/53.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all.1167236820 |
| Short name | T2371 |
| Test name | |
| Test status | |
| Simulation time | 6575545718 ps |
| CPU time | 257.11 seconds |
| Started | May 30 03:54:45 PM PDT 24 |
| Finished | May 30 03:59:04 PM PDT 24 |
| Peak memory | 573288 kb |
| Host | smart-43e3084b-dc00-484b-ae3b-401c8a2102da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167236820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all.1167236820 |
| Directory | /workspace/53.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.457320068 |
| Short name | T2015 |
| Test name | |
| Test status | |
| Simulation time | 941079023 ps |
| CPU time | 36.4 seconds |
| Started | May 30 03:54:34 PM PDT 24 |
| Finished | May 30 03:55:11 PM PDT 24 |
| Peak memory | 572944 kb |
| Host | smart-8321d5ce-0a98-440c-bb7e-c9e6a331863d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457320068 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_error.457320068 |
| Directory | /workspace/53.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.2157354740 |
| Short name | T1930 |
| Test name | |
| Test status | |
| Simulation time | 474742504 ps |
| CPU time | 177.23 seconds |
| Started | May 30 03:54:38 PM PDT 24 |
| Finished | May 30 03:57:37 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-55e3ef74-c5eb-479e-9223-5886cd33f6bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157354740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all _with_rand_reset.2157354740 |
| Directory | /workspace/53.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.3968645307 |
| Short name | T1495 |
| Test name | |
| Test status | |
| Simulation time | 988535141 ps |
| CPU time | 232.37 seconds |
| Started | May 30 03:54:37 PM PDT 24 |
| Finished | May 30 03:58:31 PM PDT 24 |
| Peak memory | 573088 kb |
| Host | smart-8379be6b-7859-4cc4-b2fc-d0bab1acc75e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968645307 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_al l_with_reset_error.3968645307 |
| Directory | /workspace/53.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_unmapped_addr.3382898626 |
| Short name | T1477 |
| Test name | |
| Test status | |
| Simulation time | 343396005 ps |
| CPU time | 16.51 seconds |
| Started | May 30 03:54:36 PM PDT 24 |
| Finished | May 30 03:54:54 PM PDT 24 |
| Peak memory | 572948 kb |
| Host | smart-e3344aab-966b-4fee-91f0-770dc7920d1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382898626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_unmapped_addr.3382898626 |
| Directory | /workspace/53.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device.4202572343 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 600764530 ps |
| CPU time | 50.82 seconds |
| Started | May 30 03:54:47 PM PDT 24 |
| Finished | May 30 03:55:39 PM PDT 24 |
| Peak memory | 573064 kb |
| Host | smart-63ffd956-0802-4bb4-990e-37c59d3e8935 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202572343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device .4202572343 |
| Directory | /workspace/54.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.315235884 |
| Short name | T1638 |
| Test name | |
| Test status | |
| Simulation time | 104603192137 ps |
| CPU time | 2062.03 seconds |
| Started | May 30 03:54:49 PM PDT 24 |
| Finished | May 30 04:29:13 PM PDT 24 |
| Peak memory | 573264 kb |
| Host | smart-2bd0d9b2-8057-4c63-8a73-9ecd4affee27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315235884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_d evice_slow_rsp.315235884 |
| Directory | /workspace/54.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.868870163 |
| Short name | T1936 |
| Test name | |
| Test status | |
| Simulation time | 1180560273 ps |
| CPU time | 46.5 seconds |
| Started | May 30 03:54:46 PM PDT 24 |
| Finished | May 30 03:55:34 PM PDT 24 |
| Peak memory | 572948 kb |
| Host | smart-b3fdd4b6-5e25-44e5-affb-d6c29fbd69e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868870163 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_and_unmapped_addr .868870163 |
| Directory | /workspace/54.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_random.2218529529 |
| Short name | T1657 |
| Test name | |
| Test status | |
| Simulation time | 301744231 ps |
| CPU time | 23.83 seconds |
| Started | May 30 03:54:55 PM PDT 24 |
| Finished | May 30 03:55:20 PM PDT 24 |
| Peak memory | 572952 kb |
| Host | smart-85b18acb-7fb8-424e-92d1-899c2ed965bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218529529 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_random.2218529529 |
| Directory | /workspace/54.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random.1618009519 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 485240161 ps |
| CPU time | 45.8 seconds |
| Started | May 30 03:54:35 PM PDT 24 |
| Finished | May 30 03:55:22 PM PDT 24 |
| Peak memory | 573000 kb |
| Host | smart-276a952a-965a-4a7a-928c-16e0ff4dcfb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618009519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random.1618009519 |
| Directory | /workspace/54.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_large_delays.3976950865 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 85786804788 ps |
| CPU time | 947.06 seconds |
| Started | May 30 03:54:35 PM PDT 24 |
| Finished | May 30 04:10:24 PM PDT 24 |
| Peak memory | 573188 kb |
| Host | smart-d5440fd7-86d7-452b-b6ab-b16fa13eac24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976950865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_large_delays.3976950865 |
| Directory | /workspace/54.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.56873380 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 56147449748 ps |
| CPU time | 1081.82 seconds |
| Started | May 30 03:54:49 PM PDT 24 |
| Finished | May 30 04:12:52 PM PDT 24 |
| Peak memory | 573172 kb |
| Host | smart-dbdb7a79-7878-48f5-8901-90af214c022a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56873380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_slow_rsp.56873380 |
| Directory | /workspace/54.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_zero_delays.2638891211 |
| Short name | T1573 |
| Test name | |
| Test status | |
| Simulation time | 176358116 ps |
| CPU time | 16.34 seconds |
| Started | May 30 03:54:38 PM PDT 24 |
| Finished | May 30 03:54:56 PM PDT 24 |
| Peak memory | 573004 kb |
| Host | smart-71a94a52-56b2-4642-96fb-1acb94c164b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638891211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_zero_del ays.2638891211 |
| Directory | /workspace/54.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_same_source.420469679 |
| Short name | T2548 |
| Test name | |
| Test status | |
| Simulation time | 2596157423 ps |
| CPU time | 79.43 seconds |
| Started | May 30 03:54:45 PM PDT 24 |
| Finished | May 30 03:56:06 PM PDT 24 |
| Peak memory | 573084 kb |
| Host | smart-03b814f8-473f-420d-8e7c-51b479113fcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420469679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_same_source.420469679 |
| Directory | /workspace/54.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke.313974985 |
| Short name | T2523 |
| Test name | |
| Test status | |
| Simulation time | 242708370 ps |
| CPU time | 10.85 seconds |
| Started | May 30 03:54:35 PM PDT 24 |
| Finished | May 30 03:54:48 PM PDT 24 |
| Peak memory | 563360 kb |
| Host | smart-cc8ccf10-2e3d-4653-92ca-66d8655dcd03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313974985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke.313974985 |
| Directory | /workspace/54.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_large_delays.794878951 |
| Short name | T1771 |
| Test name | |
| Test status | |
| Simulation time | 6507339643 ps |
| CPU time | 70.92 seconds |
| Started | May 30 03:54:43 PM PDT 24 |
| Finished | May 30 03:55:55 PM PDT 24 |
| Peak memory | 563544 kb |
| Host | smart-5d049496-0ff7-4c21-bc7a-02cea56b9b4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794878951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_large_delays.794878951 |
| Directory | /workspace/54.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.571995954 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 3154164827 ps |
| CPU time | 51.6 seconds |
| Started | May 30 03:54:35 PM PDT 24 |
| Finished | May 30 03:55:28 PM PDT 24 |
| Peak memory | 563488 kb |
| Host | smart-4b9f5c46-ec7a-4f35-8580-f99351b4ad03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571995954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_slow_rsp.571995954 |
| Directory | /workspace/54.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_zero_delays.3558625254 |
| Short name | T1415 |
| Test name | |
| Test status | |
| Simulation time | 60222536 ps |
| CPU time | 7.07 seconds |
| Started | May 30 03:54:37 PM PDT 24 |
| Finished | May 30 03:54:46 PM PDT 24 |
| Peak memory | 564800 kb |
| Host | smart-5d266527-1ef0-4db7-8e07-b5457addb309 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558625254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_zero_delay s.3558625254 |
| Directory | /workspace/54.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all.4022365987 |
| Short name | T2621 |
| Test name | |
| Test status | |
| Simulation time | 1330044190 ps |
| CPU time | 131.6 seconds |
| Started | May 30 03:54:51 PM PDT 24 |
| Finished | May 30 03:57:03 PM PDT 24 |
| Peak memory | 573160 kb |
| Host | smart-e884d364-1682-4e36-8ee2-f82d38a5a8e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022365987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all.4022365987 |
| Directory | /workspace/54.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.853478122 |
| Short name | T2059 |
| Test name | |
| Test status | |
| Simulation time | 1972136684 ps |
| CPU time | 70.17 seconds |
| Started | May 30 03:54:47 PM PDT 24 |
| Finished | May 30 03:55:58 PM PDT 24 |
| Peak memory | 572968 kb |
| Host | smart-575129b2-787d-4c3e-aaf9-bafaddfadc22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853478122 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_error.853478122 |
| Directory | /workspace/54.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.863134393 |
| Short name | T2585 |
| Test name | |
| Test status | |
| Simulation time | 9385777601 ps |
| CPU time | 628.16 seconds |
| Started | May 30 03:54:47 PM PDT 24 |
| Finished | May 30 04:05:17 PM PDT 24 |
| Peak memory | 573308 kb |
| Host | smart-80e3cb32-6cbe-45d1-aeec-54dbcbb3f771 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863134393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_ with_rand_reset.863134393 |
| Directory | /workspace/54.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.1636773766 |
| Short name | T1774 |
| Test name | |
| Test status | |
| Simulation time | 262374091 ps |
| CPU time | 101.37 seconds |
| Started | May 30 03:54:46 PM PDT 24 |
| Finished | May 30 03:56:29 PM PDT 24 |
| Peak memory | 575124 kb |
| Host | smart-afd0488b-7d24-43ee-bf7b-80a775b5fa5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636773766 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_al l_with_reset_error.1636773766 |
| Directory | /workspace/54.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_unmapped_addr.731015229 |
| Short name | T1962 |
| Test name | |
| Test status | |
| Simulation time | 238301235 ps |
| CPU time | 13.32 seconds |
| Started | May 30 03:54:55 PM PDT 24 |
| Finished | May 30 03:55:09 PM PDT 24 |
| Peak memory | 564904 kb |
| Host | smart-814c737f-8d83-43d4-b2ea-0dd8bcae5483 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731015229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_unmapped_addr.731015229 |
| Directory | /workspace/54.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device.2428728092 |
| Short name | T2525 |
| Test name | |
| Test status | |
| Simulation time | 770687404 ps |
| CPU time | 42.08 seconds |
| Started | May 30 03:54:57 PM PDT 24 |
| Finished | May 30 03:55:41 PM PDT 24 |
| Peak memory | 573040 kb |
| Host | smart-76dbcbea-0b49-471e-b45d-a8e2bb8f3e94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428728092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device .2428728092 |
| Directory | /workspace/55.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.3666086331 |
| Short name | T1928 |
| Test name | |
| Test status | |
| Simulation time | 31268227473 ps |
| CPU time | 523.98 seconds |
| Started | May 30 03:54:51 PM PDT 24 |
| Finished | May 30 04:03:36 PM PDT 24 |
| Peak memory | 573284 kb |
| Host | smart-e56d9eac-9188-459a-902a-f4415090874c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666086331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_ device_slow_rsp.3666086331 |
| Directory | /workspace/55.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.3178476750 |
| Short name | T2002 |
| Test name | |
| Test status | |
| Simulation time | 649411786 ps |
| CPU time | 25.37 seconds |
| Started | May 30 03:54:55 PM PDT 24 |
| Finished | May 30 03:55:22 PM PDT 24 |
| Peak memory | 572948 kb |
| Host | smart-3819958a-2659-4195-bae7-44d46f0fe255 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178476750 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_and_unmapped_add r.3178476750 |
| Directory | /workspace/55.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_random.3473678405 |
| Short name | T2337 |
| Test name | |
| Test status | |
| Simulation time | 1861436454 ps |
| CPU time | 69.81 seconds |
| Started | May 30 03:54:57 PM PDT 24 |
| Finished | May 30 03:56:08 PM PDT 24 |
| Peak memory | 572876 kb |
| Host | smart-fb37774e-cc65-4ad5-82d6-fe5549258d26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473678405 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_random.3473678405 |
| Directory | /workspace/55.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random.257289301 |
| Short name | T2462 |
| Test name | |
| Test status | |
| Simulation time | 619003976 ps |
| CPU time | 52.37 seconds |
| Started | May 30 03:54:46 PM PDT 24 |
| Finished | May 30 03:55:40 PM PDT 24 |
| Peak memory | 573044 kb |
| Host | smart-505e508c-fb3d-457b-93d6-2de8164ccac2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257289301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random.257289301 |
| Directory | /workspace/55.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_large_delays.851340181 |
| Short name | T1568 |
| Test name | |
| Test status | |
| Simulation time | 36167298636 ps |
| CPU time | 411.31 seconds |
| Started | May 30 03:54:45 PM PDT 24 |
| Finished | May 30 04:01:39 PM PDT 24 |
| Peak memory | 573192 kb |
| Host | smart-69bb71f1-0cb7-4a75-a9c1-f0f44b7545af |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851340181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_large_delays.851340181 |
| Directory | /workspace/55.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_slow_rsp.1789738809 |
| Short name | T1373 |
| Test name | |
| Test status | |
| Simulation time | 31756044340 ps |
| CPU time | 550.31 seconds |
| Started | May 30 03:54:51 PM PDT 24 |
| Finished | May 30 04:04:02 PM PDT 24 |
| Peak memory | 573108 kb |
| Host | smart-36a5e3a2-e6e3-4015-88a4-3af33cda16a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789738809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_slow_rsp.1789738809 |
| Directory | /workspace/55.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.2110299834 |
| Short name | T2125 |
| Test name | |
| Test status | |
| Simulation time | 318452597 ps |
| CPU time | 28.31 seconds |
| Started | May 30 03:54:47 PM PDT 24 |
| Finished | May 30 03:55:17 PM PDT 24 |
| Peak memory | 572940 kb |
| Host | smart-f991fb97-dfa3-4ed9-909f-9251599cbe80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110299834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_zero_del ays.2110299834 |
| Directory | /workspace/55.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_same_source.3956862595 |
| Short name | T2476 |
| Test name | |
| Test status | |
| Simulation time | 186498748 ps |
| CPU time | 14.4 seconds |
| Started | May 30 03:55:01 PM PDT 24 |
| Finished | May 30 03:55:16 PM PDT 24 |
| Peak memory | 572984 kb |
| Host | smart-5b9bbaa4-d3ee-41b8-8803-9be28b96c596 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956862595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_same_source.3956862595 |
| Directory | /workspace/55.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke.1051860821 |
| Short name | T1758 |
| Test name | |
| Test status | |
| Simulation time | 247719204 ps |
| CPU time | 9.78 seconds |
| Started | May 30 03:54:57 PM PDT 24 |
| Finished | May 30 03:55:08 PM PDT 24 |
| Peak memory | 564816 kb |
| Host | smart-a2e53286-cce7-4043-bb87-f9e112d60a44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051860821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke.1051860821 |
| Directory | /workspace/55.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_large_delays.1414529040 |
| Short name | T2423 |
| Test name | |
| Test status | |
| Simulation time | 9088548798 ps |
| CPU time | 98.88 seconds |
| Started | May 30 03:54:46 PM PDT 24 |
| Finished | May 30 03:56:27 PM PDT 24 |
| Peak memory | 563524 kb |
| Host | smart-8d379d06-07d7-4ef4-be0d-84387e4ac68f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414529040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_large_delays.1414529040 |
| Directory | /workspace/55.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.1112099932 |
| Short name | T2431 |
| Test name | |
| Test status | |
| Simulation time | 5923702641 ps |
| CPU time | 102.94 seconds |
| Started | May 30 03:54:55 PM PDT 24 |
| Finished | May 30 03:56:39 PM PDT 24 |
| Peak memory | 563564 kb |
| Host | smart-469645a7-132d-463d-92c5-6c3dadc1439c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112099932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_slow_rsp.1112099932 |
| Directory | /workspace/55.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_zero_delays.106250791 |
| Short name | T1549 |
| Test name | |
| Test status | |
| Simulation time | 46959856 ps |
| CPU time | 6.65 seconds |
| Started | May 30 03:54:47 PM PDT 24 |
| Finished | May 30 03:54:55 PM PDT 24 |
| Peak memory | 564824 kb |
| Host | smart-d3cc8cc9-8ce8-41bd-bf3c-1dffeeb36961 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106250791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_zero_delays .106250791 |
| Directory | /workspace/55.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all.944647284 |
| Short name | T2181 |
| Test name | |
| Test status | |
| Simulation time | 2396809126 ps |
| CPU time | 76.19 seconds |
| Started | May 30 03:55:04 PM PDT 24 |
| Finished | May 30 03:56:22 PM PDT 24 |
| Peak memory | 573184 kb |
| Host | smart-3b475f5c-4f7c-4005-bd80-bcdba22073d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944647284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all.944647284 |
| Directory | /workspace/55.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.2653449450 |
| Short name | T2555 |
| Test name | |
| Test status | |
| Simulation time | 2456432239 ps |
| CPU time | 84.2 seconds |
| Started | May 30 03:54:57 PM PDT 24 |
| Finished | May 30 03:56:23 PM PDT 24 |
| Peak memory | 572932 kb |
| Host | smart-589d17dc-f1ad-4b76-840b-88f603cef2f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653449450 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_error.2653449450 |
| Directory | /workspace/55.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.3749033181 |
| Short name | T1399 |
| Test name | |
| Test status | |
| Simulation time | 957553621 ps |
| CPU time | 252.18 seconds |
| Started | May 30 03:54:58 PM PDT 24 |
| Finished | May 30 03:59:11 PM PDT 24 |
| Peak memory | 573128 kb |
| Host | smart-38fc9d24-6895-436b-92b9-2f917f1e8857 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749033181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all _with_rand_reset.3749033181 |
| Directory | /workspace/55.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.1355991927 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 12565244057 ps |
| CPU time | 515.62 seconds |
| Started | May 30 03:54:57 PM PDT 24 |
| Finished | May 30 04:03:35 PM PDT 24 |
| Peak memory | 573216 kb |
| Host | smart-1d3ce435-0c6c-4839-9126-2b2a3e42106e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355991927 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_al l_with_reset_error.1355991927 |
| Directory | /workspace/55.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_unmapped_addr.3588941175 |
| Short name | T2246 |
| Test name | |
| Test status | |
| Simulation time | 827850454 ps |
| CPU time | 39.88 seconds |
| Started | May 30 03:54:59 PM PDT 24 |
| Finished | May 30 03:55:40 PM PDT 24 |
| Peak memory | 573084 kb |
| Host | smart-ae2ea017-4b00-4f64-937a-58f7a1b0efe0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588941175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_unmapped_addr.3588941175 |
| Directory | /workspace/55.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device.1762056972 |
| Short name | T2182 |
| Test name | |
| Test status | |
| Simulation time | 530321156 ps |
| CPU time | 43.5 seconds |
| Started | May 30 03:55:00 PM PDT 24 |
| Finished | May 30 03:55:44 PM PDT 24 |
| Peak memory | 573060 kb |
| Host | smart-0c05d00e-c1c9-4dc5-8cb5-34e67f5f26bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762056972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device .1762056972 |
| Directory | /workspace/56.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.3109907078 |
| Short name | T2104 |
| Test name | |
| Test status | |
| Simulation time | 89300181693 ps |
| CPU time | 1655.6 seconds |
| Started | May 30 03:55:04 PM PDT 24 |
| Finished | May 30 04:22:41 PM PDT 24 |
| Peak memory | 573224 kb |
| Host | smart-4a6e407b-ac98-47c2-9de8-c3ff7d313888 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109907078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_ device_slow_rsp.3109907078 |
| Directory | /workspace/56.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.3415941917 |
| Short name | T1324 |
| Test name | |
| Test status | |
| Simulation time | 65445072 ps |
| CPU time | 9.53 seconds |
| Started | May 30 03:54:58 PM PDT 24 |
| Finished | May 30 03:55:09 PM PDT 24 |
| Peak memory | 572880 kb |
| Host | smart-53de547e-40da-4743-ba15-2f5b3db20aa2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415941917 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_and_unmapped_add r.3415941917 |
| Directory | /workspace/56.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_random.2215201785 |
| Short name | T2359 |
| Test name | |
| Test status | |
| Simulation time | 1983160194 ps |
| CPU time | 63.48 seconds |
| Started | May 30 03:55:02 PM PDT 24 |
| Finished | May 30 03:56:07 PM PDT 24 |
| Peak memory | 572928 kb |
| Host | smart-180e0b96-7d64-42fc-8014-ddc0c028679c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215201785 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_random.2215201785 |
| Directory | /workspace/56.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random.2597696399 |
| Short name | T1707 |
| Test name | |
| Test status | |
| Simulation time | 356800714 ps |
| CPU time | 15.42 seconds |
| Started | May 30 03:54:58 PM PDT 24 |
| Finished | May 30 03:55:15 PM PDT 24 |
| Peak memory | 572976 kb |
| Host | smart-5d8f971f-7fae-4d0d-9868-82f531b4e447 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597696399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random.2597696399 |
| Directory | /workspace/56.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.1329752468 |
| Short name | T2118 |
| Test name | |
| Test status | |
| Simulation time | 30401108108 ps |
| CPU time | 295.7 seconds |
| Started | May 30 03:55:02 PM PDT 24 |
| Finished | May 30 03:59:59 PM PDT 24 |
| Peak memory | 573164 kb |
| Host | smart-46cecaeb-0b94-4eed-a897-f816467cea0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329752468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_large_delays.1329752468 |
| Directory | /workspace/56.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_slow_rsp.3280724602 |
| Short name | T2100 |
| Test name | |
| Test status | |
| Simulation time | 31687097863 ps |
| CPU time | 569.53 seconds |
| Started | May 30 03:55:05 PM PDT 24 |
| Finished | May 30 04:04:35 PM PDT 24 |
| Peak memory | 573156 kb |
| Host | smart-29ab1015-1469-4a87-944a-ce8419fc3cb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280724602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_slow_rsp.3280724602 |
| Directory | /workspace/56.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_zero_delays.47956622 |
| Short name | T2355 |
| Test name | |
| Test status | |
| Simulation time | 487213365 ps |
| CPU time | 44.07 seconds |
| Started | May 30 03:55:01 PM PDT 24 |
| Finished | May 30 03:55:46 PM PDT 24 |
| Peak memory | 572984 kb |
| Host | smart-a1898e79-aaf6-49f5-9531-d13243e4c5e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47956622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_zero_delay s.47956622 |
| Directory | /workspace/56.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_same_source.1506431620 |
| Short name | T2743 |
| Test name | |
| Test status | |
| Simulation time | 386767725 ps |
| CPU time | 13.76 seconds |
| Started | May 30 03:55:03 PM PDT 24 |
| Finished | May 30 03:55:17 PM PDT 24 |
| Peak memory | 573032 kb |
| Host | smart-a865dc40-6858-447a-be28-2622b65acbbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506431620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_same_source.1506431620 |
| Directory | /workspace/56.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke.1467253517 |
| Short name | T2131 |
| Test name | |
| Test status | |
| Simulation time | 209466963 ps |
| CPU time | 8.7 seconds |
| Started | May 30 03:54:57 PM PDT 24 |
| Finished | May 30 03:55:07 PM PDT 24 |
| Peak memory | 564800 kb |
| Host | smart-d46be08d-5b54-471c-a2e5-922d27778b3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467253517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke.1467253517 |
| Directory | /workspace/56.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_large_delays.3861808873 |
| Short name | T2200 |
| Test name | |
| Test status | |
| Simulation time | 7289248514 ps |
| CPU time | 77.51 seconds |
| Started | May 30 03:54:58 PM PDT 24 |
| Finished | May 30 03:56:17 PM PDT 24 |
| Peak memory | 564944 kb |
| Host | smart-3f82f10a-ac73-414c-869d-7e73ac84da1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861808873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_large_delays.3861808873 |
| Directory | /workspace/56.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.4069440072 |
| Short name | T2400 |
| Test name | |
| Test status | |
| Simulation time | 5223103173 ps |
| CPU time | 86.36 seconds |
| Started | May 30 03:54:58 PM PDT 24 |
| Finished | May 30 03:56:26 PM PDT 24 |
| Peak memory | 564904 kb |
| Host | smart-47cae036-8d57-48d1-b348-c0de280ce044 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069440072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_slow_rsp.4069440072 |
| Directory | /workspace/56.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_zero_delays.129556035 |
| Short name | T2136 |
| Test name | |
| Test status | |
| Simulation time | 57738129 ps |
| CPU time | 6.71 seconds |
| Started | May 30 03:55:02 PM PDT 24 |
| Finished | May 30 03:55:10 PM PDT 24 |
| Peak memory | 563348 kb |
| Host | smart-6c1d9177-8050-4cf7-a30a-5a64aa04c341 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129556035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_zero_delays .129556035 |
| Directory | /workspace/56.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all.1847301095 |
| Short name | T2850 |
| Test name | |
| Test status | |
| Simulation time | 2140966657 ps |
| CPU time | 147.83 seconds |
| Started | May 30 03:55:19 PM PDT 24 |
| Finished | May 30 03:57:47 PM PDT 24 |
| Peak memory | 573104 kb |
| Host | smart-473b6870-3e9f-434f-afa0-cd9613bc0d9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847301095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all.1847301095 |
| Directory | /workspace/56.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.3631631300 |
| Short name | T1990 |
| Test name | |
| Test status | |
| Simulation time | 1443876152 ps |
| CPU time | 132.14 seconds |
| Started | May 30 03:55:07 PM PDT 24 |
| Finished | May 30 03:57:20 PM PDT 24 |
| Peak memory | 575128 kb |
| Host | smart-7808811b-2a4c-4b6f-b3ee-1abac08da6ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631631300 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_error.3631631300 |
| Directory | /workspace/56.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.2650542514 |
| Short name | T2395 |
| Test name | |
| Test status | |
| Simulation time | 2842841705 ps |
| CPU time | 227.15 seconds |
| Started | May 30 03:55:05 PM PDT 24 |
| Finished | May 30 03:58:53 PM PDT 24 |
| Peak memory | 573136 kb |
| Host | smart-10e93d9e-3584-4c54-86d3-0fe52e6dd550 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650542514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all _with_rand_reset.2650542514 |
| Directory | /workspace/56.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.354189121 |
| Short name | T2721 |
| Test name | |
| Test status | |
| Simulation time | 139750802 ps |
| CPU time | 46.23 seconds |
| Started | May 30 03:55:07 PM PDT 24 |
| Finished | May 30 03:55:55 PM PDT 24 |
| Peak memory | 573032 kb |
| Host | smart-26b9ad23-824e-40f4-a2e2-23c9c990ade8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354189121 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all _with_reset_error.354189121 |
| Directory | /workspace/56.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_unmapped_addr.677397247 |
| Short name | T2350 |
| Test name | |
| Test status | |
| Simulation time | 587146781 ps |
| CPU time | 25.8 seconds |
| Started | May 30 03:54:57 PM PDT 24 |
| Finished | May 30 03:55:25 PM PDT 24 |
| Peak memory | 573108 kb |
| Host | smart-9f54b3b3-b610-433e-bbd1-61f4752cf260 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677397247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_unmapped_addr.677397247 |
| Directory | /workspace/56.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device.3136458174 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 1707696278 ps |
| CPU time | 68.78 seconds |
| Started | May 30 03:55:18 PM PDT 24 |
| Finished | May 30 03:56:28 PM PDT 24 |
| Peak memory | 573056 kb |
| Host | smart-9503eaa2-3139-4e7f-8de1-28ceef0ff793 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136458174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device .3136458174 |
| Directory | /workspace/57.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.1932514930 |
| Short name | T2362 |
| Test name | |
| Test status | |
| Simulation time | 84355422982 ps |
| CPU time | 1593.45 seconds |
| Started | May 30 03:55:12 PM PDT 24 |
| Finished | May 30 04:21:47 PM PDT 24 |
| Peak memory | 573300 kb |
| Host | smart-d3fa5839-44da-46eb-9551-2abe06b293bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932514930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_ device_slow_rsp.1932514930 |
| Directory | /workspace/57.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.2127394166 |
| Short name | T2418 |
| Test name | |
| Test status | |
| Simulation time | 487356311 ps |
| CPU time | 23.48 seconds |
| Started | May 30 03:55:15 PM PDT 24 |
| Finished | May 30 03:55:40 PM PDT 24 |
| Peak memory | 572872 kb |
| Host | smart-cb90f555-f26d-41ed-b815-42e1019a6154 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127394166 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_and_unmapped_add r.2127394166 |
| Directory | /workspace/57.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_random.2448310242 |
| Short name | T1850 |
| Test name | |
| Test status | |
| Simulation time | 214944345 ps |
| CPU time | 18.3 seconds |
| Started | May 30 03:55:08 PM PDT 24 |
| Finished | May 30 03:55:28 PM PDT 24 |
| Peak memory | 572820 kb |
| Host | smart-653afca5-f0da-46a7-b92d-72b005cc5309 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448310242 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_random.2448310242 |
| Directory | /workspace/57.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random.1407152910 |
| Short name | T2399 |
| Test name | |
| Test status | |
| Simulation time | 76755092 ps |
| CPU time | 6.84 seconds |
| Started | May 30 03:55:08 PM PDT 24 |
| Finished | May 30 03:55:16 PM PDT 24 |
| Peak memory | 564832 kb |
| Host | smart-78154ac6-c2c1-4fcd-9be3-9dedb162dc38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407152910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random.1407152910 |
| Directory | /workspace/57.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_large_delays.3520833704 |
| Short name | T1953 |
| Test name | |
| Test status | |
| Simulation time | 40170531794 ps |
| CPU time | 445.18 seconds |
| Started | May 30 03:55:08 PM PDT 24 |
| Finished | May 30 04:02:34 PM PDT 24 |
| Peak memory | 573124 kb |
| Host | smart-4bb43222-710a-4b83-a3b1-a324d13823ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520833704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_large_delays.3520833704 |
| Directory | /workspace/57.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_slow_rsp.3737581247 |
| Short name | T2465 |
| Test name | |
| Test status | |
| Simulation time | 51252464727 ps |
| CPU time | 947.3 seconds |
| Started | May 30 03:55:12 PM PDT 24 |
| Finished | May 30 04:11:00 PM PDT 24 |
| Peak memory | 573184 kb |
| Host | smart-f455bf93-f937-40d3-ba3d-82ddd802131e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737581247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_slow_rsp.3737581247 |
| Directory | /workspace/57.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_zero_delays.2472161907 |
| Short name | T1455 |
| Test name | |
| Test status | |
| Simulation time | 527137376 ps |
| CPU time | 44.67 seconds |
| Started | May 30 03:55:18 PM PDT 24 |
| Finished | May 30 03:56:04 PM PDT 24 |
| Peak memory | 573028 kb |
| Host | smart-2d64b2ab-2cf8-4504-8e7c-c3c774b6c254 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472161907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_zero_del ays.2472161907 |
| Directory | /workspace/57.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_same_source.2828259499 |
| Short name | T2609 |
| Test name | |
| Test status | |
| Simulation time | 162330839 ps |
| CPU time | 13.73 seconds |
| Started | May 30 03:55:18 PM PDT 24 |
| Finished | May 30 03:55:33 PM PDT 24 |
| Peak memory | 573040 kb |
| Host | smart-a50a3939-a095-484a-a48d-e2e6fb17af91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828259499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_same_source.2828259499 |
| Directory | /workspace/57.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke.3337477283 |
| Short name | T1504 |
| Test name | |
| Test status | |
| Simulation time | 209028522 ps |
| CPU time | 8.76 seconds |
| Started | May 30 03:55:07 PM PDT 24 |
| Finished | May 30 03:55:17 PM PDT 24 |
| Peak memory | 563312 kb |
| Host | smart-d74b1615-fc72-4e10-9ffc-55e11537c02b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337477283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke.3337477283 |
| Directory | /workspace/57.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_large_delays.1649622582 |
| Short name | T2249 |
| Test name | |
| Test status | |
| Simulation time | 10385125598 ps |
| CPU time | 103.52 seconds |
| Started | May 30 03:55:08 PM PDT 24 |
| Finished | May 30 03:56:53 PM PDT 24 |
| Peak memory | 564924 kb |
| Host | smart-91f11a84-2c3b-47af-acec-17ff3cd93156 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649622582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_large_delays.1649622582 |
| Directory | /workspace/57.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.3169782203 |
| Short name | T2461 |
| Test name | |
| Test status | |
| Simulation time | 6410747130 ps |
| CPU time | 102.81 seconds |
| Started | May 30 03:55:11 PM PDT 24 |
| Finished | May 30 03:56:55 PM PDT 24 |
| Peak memory | 563508 kb |
| Host | smart-fc26693d-d2cd-411a-9849-d5492acf1335 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169782203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_slow_rsp.3169782203 |
| Directory | /workspace/57.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_zero_delays.4224652261 |
| Short name | T2189 |
| Test name | |
| Test status | |
| Simulation time | 43537379 ps |
| CPU time | 6.19 seconds |
| Started | May 30 03:55:08 PM PDT 24 |
| Finished | May 30 03:55:16 PM PDT 24 |
| Peak memory | 564736 kb |
| Host | smart-8fd0f974-f62b-460b-a375-14488c24600d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224652261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_zero_delay s.4224652261 |
| Directory | /workspace/57.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all.3141775314 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 998383087 ps |
| CPU time | 80.85 seconds |
| Started | May 30 03:55:17 PM PDT 24 |
| Finished | May 30 03:56:39 PM PDT 24 |
| Peak memory | 573176 kb |
| Host | smart-6fecd881-b453-41ed-a539-a3e615f09808 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141775314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all.3141775314 |
| Directory | /workspace/57.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.2607099420 |
| Short name | T2185 |
| Test name | |
| Test status | |
| Simulation time | 555940351 ps |
| CPU time | 23.53 seconds |
| Started | May 30 03:55:17 PM PDT 24 |
| Finished | May 30 03:55:42 PM PDT 24 |
| Peak memory | 572960 kb |
| Host | smart-e80e10b6-fb48-4518-b18b-6f8ce8413c70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607099420 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_error.2607099420 |
| Directory | /workspace/57.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.1480763320 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 169641680 ps |
| CPU time | 44.19 seconds |
| Started | May 30 03:55:18 PM PDT 24 |
| Finished | May 30 03:56:03 PM PDT 24 |
| Peak memory | 573160 kb |
| Host | smart-04f13722-77c4-4142-8c28-d801f4af1900 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480763320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all _with_rand_reset.1480763320 |
| Directory | /workspace/57.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.340553261 |
| Short name | T1469 |
| Test name | |
| Test status | |
| Simulation time | 3170277263 ps |
| CPU time | 318.13 seconds |
| Started | May 30 03:55:20 PM PDT 24 |
| Finished | May 30 04:00:39 PM PDT 24 |
| Peak memory | 577648 kb |
| Host | smart-7b25680f-90f3-4b36-a88d-7af4e6375ff8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340553261 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all _with_reset_error.340553261 |
| Directory | /workspace/57.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.1579881295 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 855837725 ps |
| CPU time | 35.87 seconds |
| Started | May 30 03:55:11 PM PDT 24 |
| Finished | May 30 03:55:48 PM PDT 24 |
| Peak memory | 573100 kb |
| Host | smart-5ceeb336-a45d-4e09-87b0-b3f29a60f269 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579881295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_unmapped_addr.1579881295 |
| Directory | /workspace/57.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device.707699625 |
| Short name | T1431 |
| Test name | |
| Test status | |
| Simulation time | 387878259 ps |
| CPU time | 31.12 seconds |
| Started | May 30 03:55:16 PM PDT 24 |
| Finished | May 30 03:55:48 PM PDT 24 |
| Peak memory | 573060 kb |
| Host | smart-3a9e642b-95fa-42f0-81dc-126d76de93f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707699625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device. 707699625 |
| Directory | /workspace/58.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.176184259 |
| Short name | T2633 |
| Test name | |
| Test status | |
| Simulation time | 27540712141 ps |
| CPU time | 474.7 seconds |
| Started | May 30 03:55:17 PM PDT 24 |
| Finished | May 30 04:03:13 PM PDT 24 |
| Peak memory | 573280 kb |
| Host | smart-d38a8e75-4dd5-4c75-a70d-c7354740122b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176184259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_d evice_slow_rsp.176184259 |
| Directory | /workspace/58.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.2914011992 |
| Short name | T1536 |
| Test name | |
| Test status | |
| Simulation time | 37055501 ps |
| CPU time | 7.13 seconds |
| Started | May 30 03:55:28 PM PDT 24 |
| Finished | May 30 03:55:36 PM PDT 24 |
| Peak memory | 564720 kb |
| Host | smart-4a2b744d-7cc6-4d5c-a06e-afb8a5a71709 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914011992 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_and_unmapped_add r.2914011992 |
| Directory | /workspace/58.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_random.1970878176 |
| Short name | T1641 |
| Test name | |
| Test status | |
| Simulation time | 1703542007 ps |
| CPU time | 56.77 seconds |
| Started | May 30 03:55:16 PM PDT 24 |
| Finished | May 30 03:56:14 PM PDT 24 |
| Peak memory | 572888 kb |
| Host | smart-264a8637-3457-4cee-a42f-a26c64fb358d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970878176 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_random.1970878176 |
| Directory | /workspace/58.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random.4254247732 |
| Short name | T1340 |
| Test name | |
| Test status | |
| Simulation time | 1190356870 ps |
| CPU time | 46.86 seconds |
| Started | May 30 03:55:17 PM PDT 24 |
| Finished | May 30 03:56:06 PM PDT 24 |
| Peak memory | 573040 kb |
| Host | smart-fd365cbf-b89d-4162-9e7a-f9e6a26e326a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254247732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random.4254247732 |
| Directory | /workspace/58.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_large_delays.3203866977 |
| Short name | T2026 |
| Test name | |
| Test status | |
| Simulation time | 30876956583 ps |
| CPU time | 300.15 seconds |
| Started | May 30 03:55:15 PM PDT 24 |
| Finished | May 30 04:00:16 PM PDT 24 |
| Peak memory | 573132 kb |
| Host | smart-1e0c7c11-91da-4500-8c6b-b140db74cd5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203866977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_large_delays.3203866977 |
| Directory | /workspace/58.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.3446971086 |
| Short name | T1700 |
| Test name | |
| Test status | |
| Simulation time | 68191837793 ps |
| CPU time | 1356.3 seconds |
| Started | May 30 03:55:17 PM PDT 24 |
| Finished | May 30 04:17:55 PM PDT 24 |
| Peak memory | 573192 kb |
| Host | smart-5ac5a245-2ebc-4032-9867-9a2fc6508248 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446971086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_slow_rsp.3446971086 |
| Directory | /workspace/58.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_zero_delays.1777969384 |
| Short name | T1497 |
| Test name | |
| Test status | |
| Simulation time | 141737187 ps |
| CPU time | 13.8 seconds |
| Started | May 30 03:55:17 PM PDT 24 |
| Finished | May 30 03:55:31 PM PDT 24 |
| Peak memory | 573008 kb |
| Host | smart-41d6c56c-cfd3-42a4-9728-e1c23f00812b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777969384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_zero_del ays.1777969384 |
| Directory | /workspace/58.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_same_source.3460746882 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 132828929 ps |
| CPU time | 12.07 seconds |
| Started | May 30 03:55:17 PM PDT 24 |
| Finished | May 30 03:55:30 PM PDT 24 |
| Peak memory | 573076 kb |
| Host | smart-c8164f53-3084-4042-b276-73ec0067fdcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460746882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_same_source.3460746882 |
| Directory | /workspace/58.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke.2613472888 |
| Short name | T1374 |
| Test name | |
| Test status | |
| Simulation time | 249250848 ps |
| CPU time | 9.95 seconds |
| Started | May 30 03:55:18 PM PDT 24 |
| Finished | May 30 03:55:29 PM PDT 24 |
| Peak memory | 564848 kb |
| Host | smart-502eb9c1-dc4d-43cf-b699-479cdae9b57f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613472888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke.2613472888 |
| Directory | /workspace/58.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.1590471507 |
| Short name | T1831 |
| Test name | |
| Test status | |
| Simulation time | 8143910528 ps |
| CPU time | 89.5 seconds |
| Started | May 30 03:55:17 PM PDT 24 |
| Finished | May 30 03:56:48 PM PDT 24 |
| Peak memory | 564960 kb |
| Host | smart-68ac5233-13d3-45ba-9828-561afe0f627e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590471507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_large_delays.1590471507 |
| Directory | /workspace/58.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.2777149965 |
| Short name | T2204 |
| Test name | |
| Test status | |
| Simulation time | 4527078789 ps |
| CPU time | 75.71 seconds |
| Started | May 30 03:55:18 PM PDT 24 |
| Finished | May 30 03:56:35 PM PDT 24 |
| Peak memory | 563472 kb |
| Host | smart-5b06a9fe-4caf-40f4-b4b8-226a6571d063 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777149965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_slow_rsp.2777149965 |
| Directory | /workspace/58.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.686547814 |
| Short name | T1841 |
| Test name | |
| Test status | |
| Simulation time | 46055241 ps |
| CPU time | 6.53 seconds |
| Started | May 30 03:55:18 PM PDT 24 |
| Finished | May 30 03:55:26 PM PDT 24 |
| Peak memory | 563328 kb |
| Host | smart-63e3f89a-5f42-4ff2-a65e-19818877368d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686547814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_zero_delays .686547814 |
| Directory | /workspace/58.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all.2153594225 |
| Short name | T2379 |
| Test name | |
| Test status | |
| Simulation time | 1478459735 ps |
| CPU time | 112.74 seconds |
| Started | May 30 03:55:27 PM PDT 24 |
| Finished | May 30 03:57:20 PM PDT 24 |
| Peak memory | 573072 kb |
| Host | smart-84b9a8c8-a98b-4bb9-afdf-aeb627748d8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153594225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all.2153594225 |
| Directory | /workspace/58.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.381594508 |
| Short name | T1494 |
| Test name | |
| Test status | |
| Simulation time | 5069841057 ps |
| CPU time | 160.42 seconds |
| Started | May 30 03:55:27 PM PDT 24 |
| Finished | May 30 03:58:08 PM PDT 24 |
| Peak memory | 573096 kb |
| Host | smart-46b76218-1b65-4ec4-85ec-5df3ccb7cfc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381594508 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_error.381594508 |
| Directory | /workspace/58.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.728991454 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 2626023800 ps |
| CPU time | 225.75 seconds |
| Started | May 30 03:55:28 PM PDT 24 |
| Finished | May 30 03:59:15 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-ef953878-86c2-4d61-85df-eee3dda3389a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728991454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_ with_rand_reset.728991454 |
| Directory | /workspace/58.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.3843871128 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 8763845665 ps |
| CPU time | 527.44 seconds |
| Started | May 30 03:55:28 PM PDT 24 |
| Finished | May 30 04:04:16 PM PDT 24 |
| Peak memory | 573240 kb |
| Host | smart-44fdbf6a-3fd3-407b-bad4-72a10d377381 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843871128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_al l_with_reset_error.3843871128 |
| Directory | /workspace/58.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_unmapped_addr.3072880254 |
| Short name | T1516 |
| Test name | |
| Test status | |
| Simulation time | 1470676601 ps |
| CPU time | 60.32 seconds |
| Started | May 30 03:55:15 PM PDT 24 |
| Finished | May 30 03:56:17 PM PDT 24 |
| Peak memory | 573036 kb |
| Host | smart-da52f664-c19e-4811-95f7-c15be1990641 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072880254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_unmapped_addr.3072880254 |
| Directory | /workspace/58.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device.3453403635 |
| Short name | T2776 |
| Test name | |
| Test status | |
| Simulation time | 2735193992 ps |
| CPU time | 104.69 seconds |
| Started | May 30 03:55:29 PM PDT 24 |
| Finished | May 30 03:57:15 PM PDT 24 |
| Peak memory | 573112 kb |
| Host | smart-8094279d-34b4-4323-880b-e117f5781c54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453403635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device .3453403635 |
| Directory | /workspace/59.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.3433997027 |
| Short name | T1891 |
| Test name | |
| Test status | |
| Simulation time | 66818240772 ps |
| CPU time | 1106.01 seconds |
| Started | May 30 03:55:33 PM PDT 24 |
| Finished | May 30 04:14:00 PM PDT 24 |
| Peak memory | 573248 kb |
| Host | smart-f0fbc2dd-1a91-4188-96ff-632955e8371a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433997027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_ device_slow_rsp.3433997027 |
| Directory | /workspace/59.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.2331778121 |
| Short name | T1421 |
| Test name | |
| Test status | |
| Simulation time | 340810238 ps |
| CPU time | 18 seconds |
| Started | May 30 03:55:32 PM PDT 24 |
| Finished | May 30 03:55:51 PM PDT 24 |
| Peak memory | 572936 kb |
| Host | smart-f9104f13-9136-4d23-9628-054b833b538e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331778121 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_and_unmapped_add r.2331778121 |
| Directory | /workspace/59.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_random.212449271 |
| Short name | T1576 |
| Test name | |
| Test status | |
| Simulation time | 30599136 ps |
| CPU time | 6.43 seconds |
| Started | May 30 03:55:25 PM PDT 24 |
| Finished | May 30 03:55:32 PM PDT 24 |
| Peak memory | 564452 kb |
| Host | smart-b577214f-68db-490c-a25b-678532c0f8fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212449271 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_random.212449271 |
| Directory | /workspace/59.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random.1126642664 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1474549408 ps |
| CPU time | 52.39 seconds |
| Started | May 30 03:55:28 PM PDT 24 |
| Finished | May 30 03:56:22 PM PDT 24 |
| Peak memory | 573060 kb |
| Host | smart-ef73dba0-ab74-4512-be6c-468a5835b2b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126642664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random.1126642664 |
| Directory | /workspace/59.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_large_delays.1276237781 |
| Short name | T2034 |
| Test name | |
| Test status | |
| Simulation time | 19955854522 ps |
| CPU time | 219.94 seconds |
| Started | May 30 03:55:26 PM PDT 24 |
| Finished | May 30 03:59:07 PM PDT 24 |
| Peak memory | 573128 kb |
| Host | smart-61ee4d07-3f8c-4808-bc8e-c10876e1bfb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276237781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_large_delays.1276237781 |
| Directory | /workspace/59.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.570775280 |
| Short name | T1868 |
| Test name | |
| Test status | |
| Simulation time | 6505313332 ps |
| CPU time | 117.54 seconds |
| Started | May 30 03:55:30 PM PDT 24 |
| Finished | May 30 03:57:28 PM PDT 24 |
| Peak memory | 564960 kb |
| Host | smart-fb2829a6-e611-4ae6-9488-e2edf5c73342 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570775280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_slow_rsp.570775280 |
| Directory | /workspace/59.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_zero_delays.2592299323 |
| Short name | T2318 |
| Test name | |
| Test status | |
| Simulation time | 570168356 ps |
| CPU time | 53.86 seconds |
| Started | May 30 03:55:28 PM PDT 24 |
| Finished | May 30 03:56:22 PM PDT 24 |
| Peak memory | 572920 kb |
| Host | smart-2de7bf60-dbda-41d4-88e7-6d1412c597c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592299323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_zero_del ays.2592299323 |
| Directory | /workspace/59.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_same_source.1898812210 |
| Short name | T2632 |
| Test name | |
| Test status | |
| Simulation time | 530138420 ps |
| CPU time | 34.56 seconds |
| Started | May 30 03:55:34 PM PDT 24 |
| Finished | May 30 03:56:09 PM PDT 24 |
| Peak memory | 573052 kb |
| Host | smart-a32a164a-e227-4e4a-a030-d5247cf80d1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898812210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_same_source.1898812210 |
| Directory | /workspace/59.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke.1860372925 |
| Short name | T2521 |
| Test name | |
| Test status | |
| Simulation time | 50276916 ps |
| CPU time | 6.52 seconds |
| Started | May 30 03:55:27 PM PDT 24 |
| Finished | May 30 03:55:35 PM PDT 24 |
| Peak memory | 564780 kb |
| Host | smart-c5f8121c-8548-4496-ad43-c5f8709aa3a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860372925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke.1860372925 |
| Directory | /workspace/59.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.1145188265 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 6251533339 ps |
| CPU time | 70.49 seconds |
| Started | May 30 03:55:32 PM PDT 24 |
| Finished | May 30 03:56:43 PM PDT 24 |
| Peak memory | 564940 kb |
| Host | smart-38766de4-dfad-42ab-a1b3-d9749bbdcd1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145188265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_large_delays.1145188265 |
| Directory | /workspace/59.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.3516715510 |
| Short name | T1347 |
| Test name | |
| Test status | |
| Simulation time | 5375924658 ps |
| CPU time | 99.82 seconds |
| Started | May 30 03:55:28 PM PDT 24 |
| Finished | May 30 03:57:09 PM PDT 24 |
| Peak memory | 564948 kb |
| Host | smart-74b84c88-bca5-4656-93e1-574b88f60a4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516715510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_slow_rsp.3516715510 |
| Directory | /workspace/59.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_zero_delays.2145179743 |
| Short name | T1623 |
| Test name | |
| Test status | |
| Simulation time | 42555907 ps |
| CPU time | 6.21 seconds |
| Started | May 30 03:55:29 PM PDT 24 |
| Finished | May 30 03:55:37 PM PDT 24 |
| Peak memory | 563320 kb |
| Host | smart-ef4b4562-767f-4875-bcd0-36e01d463f78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145179743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_zero_delay s.2145179743 |
| Directory | /workspace/59.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all.1707046973 |
| Short name | T1456 |
| Test name | |
| Test status | |
| Simulation time | 6207946010 ps |
| CPU time | 241.97 seconds |
| Started | May 30 03:55:28 PM PDT 24 |
| Finished | May 30 03:59:31 PM PDT 24 |
| Peak memory | 573252 kb |
| Host | smart-362241d3-25e7-4bc1-bfe3-eeae68952338 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707046973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all.1707046973 |
| Directory | /workspace/59.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.2295177594 |
| Short name | T2725 |
| Test name | |
| Test status | |
| Simulation time | 2524133773 ps |
| CPU time | 180.66 seconds |
| Started | May 30 03:55:32 PM PDT 24 |
| Finished | May 30 03:58:34 PM PDT 24 |
| Peak memory | 573044 kb |
| Host | smart-afce3869-45c4-42af-9208-ee490d48c983 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295177594 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_error.2295177594 |
| Directory | /workspace/59.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.2706253620 |
| Short name | T2533 |
| Test name | |
| Test status | |
| Simulation time | 678381195 ps |
| CPU time | 160.88 seconds |
| Started | May 30 03:55:30 PM PDT 24 |
| Finished | May 30 03:58:11 PM PDT 24 |
| Peak memory | 573184 kb |
| Host | smart-f0e1b026-6ad4-4ac1-9e27-88f5e6821583 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706253620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all _with_rand_reset.2706253620 |
| Directory | /workspace/59.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.1522221551 |
| Short name | T2483 |
| Test name | |
| Test status | |
| Simulation time | 1622008684 ps |
| CPU time | 323.22 seconds |
| Started | May 30 03:55:32 PM PDT 24 |
| Finished | May 30 04:00:56 PM PDT 24 |
| Peak memory | 573056 kb |
| Host | smart-67e07e75-a381-48a9-a48a-19443949d5e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522221551 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_al l_with_reset_error.1522221551 |
| Directory | /workspace/59.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_unmapped_addr.3008554898 |
| Short name | T1717 |
| Test name | |
| Test status | |
| Simulation time | 268942527 ps |
| CPU time | 31.44 seconds |
| Started | May 30 03:55:26 PM PDT 24 |
| Finished | May 30 03:55:58 PM PDT 24 |
| Peak memory | 573052 kb |
| Host | smart-e07fd24d-15f6-4147-99db-9f680cdb728f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008554898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_unmapped_addr.3008554898 |
| Directory | /workspace/59.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_csr_rw.3404398260 |
| Short name | T2303 |
| Test name | |
| Test status | |
| Simulation time | 5457009536 ps |
| CPU time | 439.31 seconds |
| Started | May 30 03:48:52 PM PDT 24 |
| Finished | May 30 03:56:13 PM PDT 24 |
| Peak memory | 592092 kb |
| Host | smart-971b090d-5972-42ac-8a0e-d6ddeae248aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404398260 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_csr_rw.3404398260 |
| Directory | /workspace/6.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.1157393223 |
| Short name | T1779 |
| Test name | |
| Test status | |
| Simulation time | 15160857018 ps |
| CPU time | 1889.09 seconds |
| Started | May 30 03:49:01 PM PDT 24 |
| Finished | May 30 04:20:32 PM PDT 24 |
| Peak memory | 587748 kb |
| Host | smart-e582b4a4-78c9-4ab1-847b-c4733da2f32b |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157393223 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 6.chip_same_csr_outstanding.1157393223 |
| Directory | /workspace/6.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_tl_errors.2843652038 |
| Short name | T2492 |
| Test name | |
| Test status | |
| Simulation time | 2198248952 ps |
| CPU time | 75.29 seconds |
| Started | May 30 03:48:58 PM PDT 24 |
| Finished | May 30 03:50:15 PM PDT 24 |
| Peak memory | 594056 kb |
| Host | smart-3dc2a2ee-4f33-41d5-9915-d8515ad6bf80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843652038 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_tl_errors.2843652038 |
| Directory | /workspace/6.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device.4128707778 |
| Short name | T2264 |
| Test name | |
| Test status | |
| Simulation time | 199843420 ps |
| CPU time | 13.43 seconds |
| Started | May 30 03:48:48 PM PDT 24 |
| Finished | May 30 03:49:03 PM PDT 24 |
| Peak memory | 564836 kb |
| Host | smart-f4782f92-c823-464e-93e2-a9a25ee7e119 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128707778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device. 4128707778 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.1718781731 |
| Short name | T1875 |
| Test name | |
| Test status | |
| Simulation time | 35288218422 ps |
| CPU time | 591.49 seconds |
| Started | May 30 03:49:05 PM PDT 24 |
| Finished | May 30 03:58:57 PM PDT 24 |
| Peak memory | 573216 kb |
| Host | smart-fbd83e08-98c6-4a73-905b-4725e2752eca |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718781731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_d evice_slow_rsp.1718781731 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.3400374959 |
| Short name | T2443 |
| Test name | |
| Test status | |
| Simulation time | 320587920 ps |
| CPU time | 33.85 seconds |
| Started | May 30 03:48:50 PM PDT 24 |
| Finished | May 30 03:49:25 PM PDT 24 |
| Peak memory | 572936 kb |
| Host | smart-30a8388a-20a2-4f67-8efa-d6d8698bf527 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400374959 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr .3400374959 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_random.1994220679 |
| Short name | T2712 |
| Test name | |
| Test status | |
| Simulation time | 2381802105 ps |
| CPU time | 79.02 seconds |
| Started | May 30 03:48:52 PM PDT 24 |
| Finished | May 30 03:50:13 PM PDT 24 |
| Peak memory | 574052 kb |
| Host | smart-ccd02b0e-b52a-4a7a-b120-84d2cb1e9914 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994220679 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.1994220679 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random.4112715712 |
| Short name | T1481 |
| Test name | |
| Test status | |
| Simulation time | 1996034935 ps |
| CPU time | 67.66 seconds |
| Started | May 30 03:49:04 PM PDT 24 |
| Finished | May 30 03:50:13 PM PDT 24 |
| Peak memory | 573004 kb |
| Host | smart-42e3d78d-7aa4-4b53-908c-b0beea52b285 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112715712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random.4112715712 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_large_delays.478576576 |
| Short name | T2811 |
| Test name | |
| Test status | |
| Simulation time | 99989662491 ps |
| CPU time | 1047.33 seconds |
| Started | May 30 03:48:55 PM PDT 24 |
| Finished | May 30 04:06:24 PM PDT 24 |
| Peak memory | 573172 kb |
| Host | smart-dc7477ea-7cb0-4842-943c-5f909b3ab6b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478576576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.478576576 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_slow_rsp.766373807 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 51748972923 ps |
| CPU time | 908.27 seconds |
| Started | May 30 03:48:55 PM PDT 24 |
| Finished | May 30 04:04:05 PM PDT 24 |
| Peak memory | 573188 kb |
| Host | smart-e93b5d0d-cf22-4f54-a11b-a38084d88204 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766373807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.766373807 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_zero_delays.758583451 |
| Short name | T2275 |
| Test name | |
| Test status | |
| Simulation time | 400052072 ps |
| CPU time | 34.1 seconds |
| Started | May 30 03:48:54 PM PDT 24 |
| Finished | May 30 03:49:29 PM PDT 24 |
| Peak memory | 573080 kb |
| Host | smart-0528b510-f891-49b6-af4b-f72369c3149d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758583451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delay s.758583451 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_same_source.4047928875 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 442523441 ps |
| CPU time | 35.29 seconds |
| Started | May 30 03:48:54 PM PDT 24 |
| Finished | May 30 03:49:31 PM PDT 24 |
| Peak memory | 572968 kb |
| Host | smart-ef4f9098-c16f-42de-8300-beec44de4433 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047928875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.4047928875 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke.2619550271 |
| Short name | T2367 |
| Test name | |
| Test status | |
| Simulation time | 177927774 ps |
| CPU time | 8.57 seconds |
| Started | May 30 03:48:51 PM PDT 24 |
| Finished | May 30 03:49:02 PM PDT 24 |
| Peak memory | 564832 kb |
| Host | smart-407e5df8-9fc3-4445-9423-515ed84cd544 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619550271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.2619550271 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_large_delays.2223131380 |
| Short name | T2440 |
| Test name | |
| Test status | |
| Simulation time | 8514220497 ps |
| CPU time | 90.3 seconds |
| Started | May 30 03:48:57 PM PDT 24 |
| Finished | May 30 03:50:29 PM PDT 24 |
| Peak memory | 564976 kb |
| Host | smart-8a451acb-a664-4aef-9c88-9244e38802a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223131380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.2223131380 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.2370480388 |
| Short name | T1670 |
| Test name | |
| Test status | |
| Simulation time | 6995126644 ps |
| CPU time | 106.37 seconds |
| Started | May 30 03:48:55 PM PDT 24 |
| Finished | May 30 03:50:43 PM PDT 24 |
| Peak memory | 564940 kb |
| Host | smart-bc85cd11-bdf7-44e6-ac1f-b6a44cfa2762 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370480388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.2370480388 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.3796345606 |
| Short name | T1460 |
| Test name | |
| Test status | |
| Simulation time | 49428902 ps |
| CPU time | 6.11 seconds |
| Started | May 30 03:48:58 PM PDT 24 |
| Finished | May 30 03:49:06 PM PDT 24 |
| Peak memory | 564780 kb |
| Host | smart-38b2e8f8-3316-4af5-8671-5eeed596e6f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796345606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays .3796345606 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all.1663662830 |
| Short name | T2865 |
| Test name | |
| Test status | |
| Simulation time | 6219219059 ps |
| CPU time | 269.18 seconds |
| Started | May 30 03:48:52 PM PDT 24 |
| Finished | May 30 03:53:23 PM PDT 24 |
| Peak memory | 573248 kb |
| Host | smart-ebda7fe8-3c5a-4a2c-bdeb-893b99b5e921 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663662830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.1663662830 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_error.3190677881 |
| Short name | T1903 |
| Test name | |
| Test status | |
| Simulation time | 1851000268 ps |
| CPU time | 145.17 seconds |
| Started | May 30 03:48:56 PM PDT 24 |
| Finished | May 30 03:51:23 PM PDT 24 |
| Peak memory | 573000 kb |
| Host | smart-87182b04-49e2-4322-ab52-d329e579a411 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190677881 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.3190677881 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.148622139 |
| Short name | T1742 |
| Test name | |
| Test status | |
| Simulation time | 1972699569 ps |
| CPU time | 221.33 seconds |
| Started | May 30 03:48:53 PM PDT 24 |
| Finished | May 30 03:52:36 PM PDT 24 |
| Peak memory | 573128 kb |
| Host | smart-7113d335-209d-4ffc-a495-3e71e499af4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148622139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_w ith_rand_reset.148622139 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.2046054842 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 3392683518 ps |
| CPU time | 230.09 seconds |
| Started | May 30 03:48:52 PM PDT 24 |
| Finished | May 30 03:52:44 PM PDT 24 |
| Peak memory | 573092 kb |
| Host | smart-2250fd5f-26df-434b-9d5a-2a1b0b487229 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046054842 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all _with_reset_error.2046054842 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_unmapped_addr.2707474926 |
| Short name | T1409 |
| Test name | |
| Test status | |
| Simulation time | 35165075 ps |
| CPU time | 7.18 seconds |
| Started | May 30 03:48:51 PM PDT 24 |
| Finished | May 30 03:49:00 PM PDT 24 |
| Peak memory | 564864 kb |
| Host | smart-2dbf0e67-831a-4cb3-b500-7e34324994de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707474926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.2707474926 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device.714725013 |
| Short name | T1685 |
| Test name | |
| Test status | |
| Simulation time | 2078631162 ps |
| CPU time | 78.93 seconds |
| Started | May 30 03:55:42 PM PDT 24 |
| Finished | May 30 03:57:02 PM PDT 24 |
| Peak memory | 573036 kb |
| Host | smart-34d203cc-3263-489c-98b1-95b7f13156da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714725013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device. 714725013 |
| Directory | /workspace/60.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.4124466102 |
| Short name | T1822 |
| Test name | |
| Test status | |
| Simulation time | 56364882435 ps |
| CPU time | 1010.61 seconds |
| Started | May 30 03:55:38 PM PDT 24 |
| Finished | May 30 04:12:30 PM PDT 24 |
| Peak memory | 573164 kb |
| Host | smart-6ba2c79d-71a4-4229-8db1-b65f72a310a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124466102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_ device_slow_rsp.4124466102 |
| Directory | /workspace/60.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.235967577 |
| Short name | T2855 |
| Test name | |
| Test status | |
| Simulation time | 918689638 ps |
| CPU time | 35.95 seconds |
| Started | May 30 03:55:37 PM PDT 24 |
| Finished | May 30 03:56:13 PM PDT 24 |
| Peak memory | 572920 kb |
| Host | smart-71b3e617-6912-48a9-a909-801960b7683a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235967577 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_and_unmapped_addr .235967577 |
| Directory | /workspace/60.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_random.2762339050 |
| Short name | T1997 |
| Test name | |
| Test status | |
| Simulation time | 761309722 ps |
| CPU time | 29.09 seconds |
| Started | May 30 03:55:37 PM PDT 24 |
| Finished | May 30 03:56:08 PM PDT 24 |
| Peak memory | 573968 kb |
| Host | smart-cf96d1fe-01eb-4ace-91bc-b514e27aaeea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762339050 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_random.2762339050 |
| Directory | /workspace/60.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random.3280471283 |
| Short name | T2329 |
| Test name | |
| Test status | |
| Simulation time | 176724169 ps |
| CPU time | 18.7 seconds |
| Started | May 30 03:55:37 PM PDT 24 |
| Finished | May 30 03:55:57 PM PDT 24 |
| Peak memory | 573032 kb |
| Host | smart-6fbb78d2-30a1-4849-9b6d-37ea5d25f70a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280471283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random.3280471283 |
| Directory | /workspace/60.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_large_delays.3008851053 |
| Short name | T1755 |
| Test name | |
| Test status | |
| Simulation time | 79802588926 ps |
| CPU time | 948.01 seconds |
| Started | May 30 03:55:46 PM PDT 24 |
| Finished | May 30 04:11:36 PM PDT 24 |
| Peak memory | 573216 kb |
| Host | smart-07fa5b86-f5e4-4b2c-99af-ab6062ff7db7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008851053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_large_delays.3008851053 |
| Directory | /workspace/60.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.648540739 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 11029634121 ps |
| CPU time | 190.39 seconds |
| Started | May 30 03:55:37 PM PDT 24 |
| Finished | May 30 03:58:48 PM PDT 24 |
| Peak memory | 573180 kb |
| Host | smart-97cd8bd4-1750-4586-9ead-96c13d5a4fd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648540739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_slow_rsp.648540739 |
| Directory | /workspace/60.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_zero_delays.934376746 |
| Short name | T1579 |
| Test name | |
| Test status | |
| Simulation time | 320634083 ps |
| CPU time | 30.71 seconds |
| Started | May 30 03:55:47 PM PDT 24 |
| Finished | May 30 03:56:20 PM PDT 24 |
| Peak memory | 572964 kb |
| Host | smart-7017d50b-ae00-4854-ae34-7bba60883710 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934376746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_zero_dela ys.934376746 |
| Directory | /workspace/60.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_same_source.562656047 |
| Short name | T2643 |
| Test name | |
| Test status | |
| Simulation time | 1723592084 ps |
| CPU time | 51.55 seconds |
| Started | May 30 03:55:38 PM PDT 24 |
| Finished | May 30 03:56:31 PM PDT 24 |
| Peak memory | 572960 kb |
| Host | smart-4adc8d4b-4edc-4712-9d37-b91bd19fe579 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562656047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_same_source.562656047 |
| Directory | /workspace/60.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke.2296335189 |
| Short name | T1792 |
| Test name | |
| Test status | |
| Simulation time | 241827009 ps |
| CPU time | 9.92 seconds |
| Started | May 30 03:55:28 PM PDT 24 |
| Finished | May 30 03:55:39 PM PDT 24 |
| Peak memory | 564848 kb |
| Host | smart-edf38201-ce67-4528-ba2a-4b15188f652c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296335189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke.2296335189 |
| Directory | /workspace/60.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.1294977438 |
| Short name | T1447 |
| Test name | |
| Test status | |
| Simulation time | 7103548975 ps |
| CPU time | 68.79 seconds |
| Started | May 30 03:55:37 PM PDT 24 |
| Finished | May 30 03:56:47 PM PDT 24 |
| Peak memory | 564888 kb |
| Host | smart-6adb026e-3e41-49a1-bf79-aa82a79dc6e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294977438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_large_delays.1294977438 |
| Directory | /workspace/60.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.860659984 |
| Short name | T2223 |
| Test name | |
| Test status | |
| Simulation time | 5136856789 ps |
| CPU time | 86.43 seconds |
| Started | May 30 03:55:40 PM PDT 24 |
| Finished | May 30 03:57:08 PM PDT 24 |
| Peak memory | 563532 kb |
| Host | smart-35961e3b-4f64-4a3a-85cb-b7e1b4106e78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860659984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_slow_rsp.860659984 |
| Directory | /workspace/60.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.2791434982 |
| Short name | T2641 |
| Test name | |
| Test status | |
| Simulation time | 47928756 ps |
| CPU time | 6.31 seconds |
| Started | May 30 03:55:27 PM PDT 24 |
| Finished | May 30 03:55:34 PM PDT 24 |
| Peak memory | 563336 kb |
| Host | smart-587e5fbe-c407-4e53-a6cb-8ab21a89e063 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791434982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_zero_delay s.2791434982 |
| Directory | /workspace/60.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all.1606962820 |
| Short name | T2421 |
| Test name | |
| Test status | |
| Simulation time | 2363607721 ps |
| CPU time | 196.83 seconds |
| Started | May 30 03:55:48 PM PDT 24 |
| Finished | May 30 03:59:06 PM PDT 24 |
| Peak memory | 573224 kb |
| Host | smart-3658846f-0949-4869-a32f-42f7d34c0d3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606962820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all.1606962820 |
| Directory | /workspace/60.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.2002889439 |
| Short name | T1752 |
| Test name | |
| Test status | |
| Simulation time | 12401475117 ps |
| CPU time | 476.42 seconds |
| Started | May 30 03:55:36 PM PDT 24 |
| Finished | May 30 04:03:34 PM PDT 24 |
| Peak memory | 575164 kb |
| Host | smart-ecce57ed-7393-48d7-acac-02529b295160 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002889439 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_error.2002889439 |
| Directory | /workspace/60.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.287901366 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 15474294675 ps |
| CPU time | 654.87 seconds |
| Started | May 30 03:55:36 PM PDT 24 |
| Finished | May 30 04:06:32 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-ee5cc868-c3b2-40bd-bfb9-6e2275b41c7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287901366 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all _with_reset_error.287901366 |
| Directory | /workspace/60.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_unmapped_addr.3890769725 |
| Short name | T1537 |
| Test name | |
| Test status | |
| Simulation time | 217954295 ps |
| CPU time | 26.4 seconds |
| Started | May 30 03:55:49 PM PDT 24 |
| Finished | May 30 03:56:16 PM PDT 24 |
| Peak memory | 573096 kb |
| Host | smart-6af872e9-acf8-4351-bf92-78ecf8783b54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890769725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_unmapped_addr.3890769725 |
| Directory | /workspace/60.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device.4203880721 |
| Short name | T1995 |
| Test name | |
| Test status | |
| Simulation time | 2965192976 ps |
| CPU time | 111.49 seconds |
| Started | May 30 03:55:43 PM PDT 24 |
| Finished | May 30 03:57:35 PM PDT 24 |
| Peak memory | 573020 kb |
| Host | smart-eec97f4d-668d-42a3-a295-78ed26d59b0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203880721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device .4203880721 |
| Directory | /workspace/61.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.1530955407 |
| Short name | T2162 |
| Test name | |
| Test status | |
| Simulation time | 959643714 ps |
| CPU time | 39.5 seconds |
| Started | May 30 03:55:48 PM PDT 24 |
| Finished | May 30 03:56:29 PM PDT 24 |
| Peak memory | 573980 kb |
| Host | smart-3322be67-4222-45d7-ba6f-621afd175723 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530955407 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_and_unmapped_add r.1530955407 |
| Directory | /workspace/61.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_random.3051748124 |
| Short name | T2044 |
| Test name | |
| Test status | |
| Simulation time | 296189937 ps |
| CPU time | 12.78 seconds |
| Started | May 30 03:55:44 PM PDT 24 |
| Finished | May 30 03:55:58 PM PDT 24 |
| Peak memory | 564708 kb |
| Host | smart-2cd6a035-384c-4d2f-982b-7c9c382b1557 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051748124 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_random.3051748124 |
| Directory | /workspace/61.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random.1110828275 |
| Short name | T2458 |
| Test name | |
| Test status | |
| Simulation time | 243099224 ps |
| CPU time | 22.82 seconds |
| Started | May 30 03:55:44 PM PDT 24 |
| Finished | May 30 03:56:08 PM PDT 24 |
| Peak memory | 573048 kb |
| Host | smart-3d6ec2e6-7922-4482-8481-a39884533c42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110828275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random.1110828275 |
| Directory | /workspace/61.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_large_delays.1728402914 |
| Short name | T1965 |
| Test name | |
| Test status | |
| Simulation time | 52298221990 ps |
| CPU time | 581.78 seconds |
| Started | May 30 03:55:47 PM PDT 24 |
| Finished | May 30 04:05:30 PM PDT 24 |
| Peak memory | 573168 kb |
| Host | smart-f47251f6-ec61-46d1-b8ab-d173585be689 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728402914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_large_delays.1728402914 |
| Directory | /workspace/61.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_slow_rsp.3103585192 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 45160406961 ps |
| CPU time | 808 seconds |
| Started | May 30 03:55:43 PM PDT 24 |
| Finished | May 30 04:09:13 PM PDT 24 |
| Peak memory | 573208 kb |
| Host | smart-4fec1257-3815-43c7-8cf9-9d34fe7089d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103585192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_slow_rsp.3103585192 |
| Directory | /workspace/61.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_zero_delays.1794957776 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 321793354 ps |
| CPU time | 30.21 seconds |
| Started | May 30 03:55:45 PM PDT 24 |
| Finished | May 30 03:56:17 PM PDT 24 |
| Peak memory | 573028 kb |
| Host | smart-396565de-431d-4691-bc6b-83db0c100132 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794957776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_zero_del ays.1794957776 |
| Directory | /workspace/61.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_same_source.318522920 |
| Short name | T2250 |
| Test name | |
| Test status | |
| Simulation time | 558489987 ps |
| CPU time | 37.83 seconds |
| Started | May 30 03:55:43 PM PDT 24 |
| Finished | May 30 03:56:22 PM PDT 24 |
| Peak memory | 572944 kb |
| Host | smart-921a486b-6511-425a-81c7-b361798283de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318522920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_same_source.318522920 |
| Directory | /workspace/61.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke.1450288884 |
| Short name | T1531 |
| Test name | |
| Test status | |
| Simulation time | 214235134 ps |
| CPU time | 9.8 seconds |
| Started | May 30 03:55:36 PM PDT 24 |
| Finished | May 30 03:55:46 PM PDT 24 |
| Peak memory | 564784 kb |
| Host | smart-d690fe08-903a-4b70-8afd-898201ba1104 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450288884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke.1450288884 |
| Directory | /workspace/61.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_large_delays.1678750270 |
| Short name | T2450 |
| Test name | |
| Test status | |
| Simulation time | 9677497175 ps |
| CPU time | 100.01 seconds |
| Started | May 30 03:55:41 PM PDT 24 |
| Finished | May 30 03:57:22 PM PDT 24 |
| Peak memory | 564952 kb |
| Host | smart-43abca2e-241a-490a-8cb0-b9faad199fae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678750270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_large_delays.1678750270 |
| Directory | /workspace/61.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.640672044 |
| Short name | T2414 |
| Test name | |
| Test status | |
| Simulation time | 4326931611 ps |
| CPU time | 76.22 seconds |
| Started | May 30 03:55:46 PM PDT 24 |
| Finished | May 30 03:57:04 PM PDT 24 |
| Peak memory | 564940 kb |
| Host | smart-0c7aa254-1686-4091-912c-afa3af0e3125 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640672044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_slow_rsp.640672044 |
| Directory | /workspace/61.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_zero_delays.2655049437 |
| Short name | T2297 |
| Test name | |
| Test status | |
| Simulation time | 39802787 ps |
| CPU time | 5.66 seconds |
| Started | May 30 03:55:37 PM PDT 24 |
| Finished | May 30 03:55:43 PM PDT 24 |
| Peak memory | 563348 kb |
| Host | smart-f26625fa-451d-4d42-89fd-08c48b5c6d7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655049437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_zero_delay s.2655049437 |
| Directory | /workspace/61.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all.4224668585 |
| Short name | T2448 |
| Test name | |
| Test status | |
| Simulation time | 11978753823 ps |
| CPU time | 406.96 seconds |
| Started | May 30 03:55:45 PM PDT 24 |
| Finished | May 30 04:02:34 PM PDT 24 |
| Peak memory | 573228 kb |
| Host | smart-92a1f83f-b2f4-4809-a55c-e53e83bbd52e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224668585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all.4224668585 |
| Directory | /workspace/61.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.4072372440 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 552622626 ps |
| CPU time | 118.35 seconds |
| Started | May 30 03:55:56 PM PDT 24 |
| Finished | May 30 03:57:55 PM PDT 24 |
| Peak memory | 573060 kb |
| Host | smart-8b24f771-6c5a-40d3-87b6-dcdd27c22e2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072372440 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_al l_with_reset_error.4072372440 |
| Directory | /workspace/61.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_unmapped_addr.404168615 |
| Short name | T2716 |
| Test name | |
| Test status | |
| Simulation time | 169390137 ps |
| CPU time | 23.16 seconds |
| Started | May 30 03:55:43 PM PDT 24 |
| Finished | May 30 03:56:07 PM PDT 24 |
| Peak memory | 573132 kb |
| Host | smart-f6035e54-745f-4005-b9f1-821dbc285baf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404168615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_unmapped_addr.404168615 |
| Directory | /workspace/61.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device.3514744715 |
| Short name | T2544 |
| Test name | |
| Test status | |
| Simulation time | 1103245774 ps |
| CPU time | 41.68 seconds |
| Started | May 30 03:55:56 PM PDT 24 |
| Finished | May 30 03:56:39 PM PDT 24 |
| Peak memory | 572944 kb |
| Host | smart-ec2c8c95-6bbe-41b5-ae79-f6d4143865f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514744715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device .3514744715 |
| Directory | /workspace/62.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.1940212901 |
| Short name | T2630 |
| Test name | |
| Test status | |
| Simulation time | 32802466110 ps |
| CPU time | 610.27 seconds |
| Started | May 30 03:55:54 PM PDT 24 |
| Finished | May 30 04:06:05 PM PDT 24 |
| Peak memory | 573240 kb |
| Host | smart-9591087e-8062-4237-bf8e-96dd5b8b7e7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940212901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_ device_slow_rsp.1940212901 |
| Directory | /workspace/62.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.2055011801 |
| Short name | T1459 |
| Test name | |
| Test status | |
| Simulation time | 991061930 ps |
| CPU time | 39.56 seconds |
| Started | May 30 03:55:55 PM PDT 24 |
| Finished | May 30 03:56:35 PM PDT 24 |
| Peak memory | 573988 kb |
| Host | smart-a6b5ceeb-a01e-4fa6-8ea5-43bd9c2a91fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055011801 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_and_unmapped_add r.2055011801 |
| Directory | /workspace/62.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_random.1743208918 |
| Short name | T1420 |
| Test name | |
| Test status | |
| Simulation time | 1827447530 ps |
| CPU time | 71.1 seconds |
| Started | May 30 03:55:54 PM PDT 24 |
| Finished | May 30 03:57:06 PM PDT 24 |
| Peak memory | 572944 kb |
| Host | smart-2deaddc2-f43c-4a65-ba13-e7a2a16601b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743208918 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_random.1743208918 |
| Directory | /workspace/62.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random.3342238940 |
| Short name | T1617 |
| Test name | |
| Test status | |
| Simulation time | 771863273 ps |
| CPU time | 31.41 seconds |
| Started | May 30 03:55:55 PM PDT 24 |
| Finished | May 30 03:56:27 PM PDT 24 |
| Peak memory | 573040 kb |
| Host | smart-022ca1af-255f-4814-9f65-8489bd90ec96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342238940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random.3342238940 |
| Directory | /workspace/62.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_large_delays.3926223660 |
| Short name | T2156 |
| Test name | |
| Test status | |
| Simulation time | 15806797898 ps |
| CPU time | 171.52 seconds |
| Started | May 30 03:55:57 PM PDT 24 |
| Finished | May 30 03:58:49 PM PDT 24 |
| Peak memory | 573180 kb |
| Host | smart-33ab8f67-263f-4736-837d-32bde85735df |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926223660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_large_delays.3926223660 |
| Directory | /workspace/62.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_slow_rsp.3161505098 |
| Short name | T2569 |
| Test name | |
| Test status | |
| Simulation time | 40421497774 ps |
| CPU time | 736.35 seconds |
| Started | May 30 03:55:57 PM PDT 24 |
| Finished | May 30 04:08:14 PM PDT 24 |
| Peak memory | 573160 kb |
| Host | smart-70b7793c-1add-4956-b911-cb24095e98cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161505098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_slow_rsp.3161505098 |
| Directory | /workspace/62.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_zero_delays.3790374152 |
| Short name | T1843 |
| Test name | |
| Test status | |
| Simulation time | 600329298 ps |
| CPU time | 48.41 seconds |
| Started | May 30 03:55:54 PM PDT 24 |
| Finished | May 30 03:56:44 PM PDT 24 |
| Peak memory | 573040 kb |
| Host | smart-5659dbc7-f3ed-4092-9621-4ae5d8ea8848 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790374152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_zero_del ays.3790374152 |
| Directory | /workspace/62.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_same_source.2700901212 |
| Short name | T2347 |
| Test name | |
| Test status | |
| Simulation time | 1713609641 ps |
| CPU time | 53.22 seconds |
| Started | May 30 03:55:54 PM PDT 24 |
| Finished | May 30 03:56:48 PM PDT 24 |
| Peak memory | 573052 kb |
| Host | smart-2aae39bc-b96f-43de-a3cf-533455986a97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700901212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_same_source.2700901212 |
| Directory | /workspace/62.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke.2266800211 |
| Short name | T2639 |
| Test name | |
| Test status | |
| Simulation time | 218494197 ps |
| CPU time | 9.81 seconds |
| Started | May 30 03:55:55 PM PDT 24 |
| Finished | May 30 03:56:05 PM PDT 24 |
| Peak memory | 564856 kb |
| Host | smart-5bb1c965-d1fc-451a-896a-12e8c952a0b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266800211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke.2266800211 |
| Directory | /workspace/62.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_large_delays.1275490206 |
| Short name | T1372 |
| Test name | |
| Test status | |
| Simulation time | 8128058651 ps |
| CPU time | 79.62 seconds |
| Started | May 30 03:55:57 PM PDT 24 |
| Finished | May 30 03:57:17 PM PDT 24 |
| Peak memory | 564960 kb |
| Host | smart-dfd77dce-db2b-4ead-8a04-aa27588f37d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275490206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_large_delays.1275490206 |
| Directory | /workspace/62.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.567521784 |
| Short name | T2771 |
| Test name | |
| Test status | |
| Simulation time | 5141963536 ps |
| CPU time | 83.67 seconds |
| Started | May 30 03:55:57 PM PDT 24 |
| Finished | May 30 03:57:21 PM PDT 24 |
| Peak memory | 564956 kb |
| Host | smart-57b035d4-9ae4-4e16-b65f-1fd84caace19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567521784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_slow_rsp.567521784 |
| Directory | /workspace/62.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_zero_delays.730419492 |
| Short name | T1633 |
| Test name | |
| Test status | |
| Simulation time | 52322402 ps |
| CPU time | 6.87 seconds |
| Started | May 30 03:55:58 PM PDT 24 |
| Finished | May 30 03:56:05 PM PDT 24 |
| Peak memory | 564784 kb |
| Host | smart-b0ce60e2-5ad5-4279-aa82-08009acfc217 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730419492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_zero_delays .730419492 |
| Directory | /workspace/62.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all.3898999566 |
| Short name | T1684 |
| Test name | |
| Test status | |
| Simulation time | 14401041896 ps |
| CPU time | 571.34 seconds |
| Started | May 30 03:55:57 PM PDT 24 |
| Finished | May 30 04:05:30 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-74031834-e12b-4220-8228-14827bbc81c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898999566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all.3898999566 |
| Directory | /workspace/62.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.1364177445 |
| Short name | T1905 |
| Test name | |
| Test status | |
| Simulation time | 5924647457 ps |
| CPU time | 168.49 seconds |
| Started | May 30 03:55:56 PM PDT 24 |
| Finished | May 30 03:58:45 PM PDT 24 |
| Peak memory | 573132 kb |
| Host | smart-b1fc2652-efcb-428e-95d9-25dfbe016f11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364177445 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_error.1364177445 |
| Directory | /workspace/62.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.968035245 |
| Short name | T2872 |
| Test name | |
| Test status | |
| Simulation time | 532888557 ps |
| CPU time | 173.39 seconds |
| Started | May 30 03:55:55 PM PDT 24 |
| Finished | May 30 03:58:49 PM PDT 24 |
| Peak memory | 573072 kb |
| Host | smart-a32120e0-c1b2-4ed8-88b2-91c460f204b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968035245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_ with_rand_reset.968035245 |
| Directory | /workspace/62.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.1114904985 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 16527970490 ps |
| CPU time | 710.6 seconds |
| Started | May 30 03:55:53 PM PDT 24 |
| Finished | May 30 04:07:44 PM PDT 24 |
| Peak memory | 573212 kb |
| Host | smart-ef206532-f601-4c28-af03-749125def76a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114904985 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_al l_with_reset_error.1114904985 |
| Directory | /workspace/62.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.693986390 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 339994374 ps |
| CPU time | 16.65 seconds |
| Started | May 30 03:55:56 PM PDT 24 |
| Finished | May 30 03:56:14 PM PDT 24 |
| Peak memory | 573092 kb |
| Host | smart-41fef9e4-409e-48d4-a0db-9311668e00ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693986390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_unmapped_addr.693986390 |
| Directory | /workspace/62.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device.661040525 |
| Short name | T2097 |
| Test name | |
| Test status | |
| Simulation time | 351438840 ps |
| CPU time | 20.84 seconds |
| Started | May 30 03:56:05 PM PDT 24 |
| Finished | May 30 03:56:26 PM PDT 24 |
| Peak memory | 564836 kb |
| Host | smart-fcb5e620-5073-4668-b689-7fe79ecd7995 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661040525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device. 661040525 |
| Directory | /workspace/63.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.1025135468 |
| Short name | T2091 |
| Test name | |
| Test status | |
| Simulation time | 139816897350 ps |
| CPU time | 2763.74 seconds |
| Started | May 30 03:56:05 PM PDT 24 |
| Finished | May 30 04:42:11 PM PDT 24 |
| Peak memory | 573360 kb |
| Host | smart-ad2aa9c4-f7ad-4002-89dd-ca47c92d7128 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025135468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_ device_slow_rsp.1025135468 |
| Directory | /workspace/63.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.2185327742 |
| Short name | T2512 |
| Test name | |
| Test status | |
| Simulation time | 289281846 ps |
| CPU time | 31.04 seconds |
| Started | May 30 03:56:14 PM PDT 24 |
| Finished | May 30 03:56:46 PM PDT 24 |
| Peak memory | 572916 kb |
| Host | smart-bb822b0d-6ea8-49cd-be43-00555bef26cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185327742 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_and_unmapped_add r.2185327742 |
| Directory | /workspace/63.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_random.1461749376 |
| Short name | T2216 |
| Test name | |
| Test status | |
| Simulation time | 548732295 ps |
| CPU time | 22.65 seconds |
| Started | May 30 03:56:07 PM PDT 24 |
| Finished | May 30 03:56:30 PM PDT 24 |
| Peak memory | 573968 kb |
| Host | smart-da1407c8-f428-4310-83e3-a55b90c10197 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461749376 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_random.1461749376 |
| Directory | /workspace/63.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random.1777391259 |
| Short name | T2043 |
| Test name | |
| Test status | |
| Simulation time | 1009893908 ps |
| CPU time | 33.9 seconds |
| Started | May 30 03:56:06 PM PDT 24 |
| Finished | May 30 03:56:41 PM PDT 24 |
| Peak memory | 572952 kb |
| Host | smart-ca56c144-aac4-4202-a478-4f8ba6a8fdc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777391259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random.1777391259 |
| Directory | /workspace/63.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_slow_rsp.3719283214 |
| Short name | T1969 |
| Test name | |
| Test status | |
| Simulation time | 67275975516 ps |
| CPU time | 1298.85 seconds |
| Started | May 30 03:56:04 PM PDT 24 |
| Finished | May 30 04:17:44 PM PDT 24 |
| Peak memory | 573160 kb |
| Host | smart-e5e3df03-9934-41c8-af82-7219406de50f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719283214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_slow_rsp.3719283214 |
| Directory | /workspace/63.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_zero_delays.3720689285 |
| Short name | T2481 |
| Test name | |
| Test status | |
| Simulation time | 156467864 ps |
| CPU time | 15.73 seconds |
| Started | May 30 03:56:05 PM PDT 24 |
| Finished | May 30 03:56:22 PM PDT 24 |
| Peak memory | 572968 kb |
| Host | smart-d5338a6d-88dd-4e10-b5b5-9dd9a13b955d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720689285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_zero_del ays.3720689285 |
| Directory | /workspace/63.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_same_source.3968461619 |
| Short name | T2234 |
| Test name | |
| Test status | |
| Simulation time | 2606764760 ps |
| CPU time | 82.62 seconds |
| Started | May 30 03:56:06 PM PDT 24 |
| Finished | May 30 03:57:30 PM PDT 24 |
| Peak memory | 573148 kb |
| Host | smart-f0df1a00-5b63-49ef-8229-6c7410bffe7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968461619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_same_source.3968461619 |
| Directory | /workspace/63.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke.2068911746 |
| Short name | T2869 |
| Test name | |
| Test status | |
| Simulation time | 225905714 ps |
| CPU time | 9.15 seconds |
| Started | May 30 03:56:05 PM PDT 24 |
| Finished | May 30 03:56:15 PM PDT 24 |
| Peak memory | 564848 kb |
| Host | smart-3e68c019-0e1c-4549-b601-8e9d24c18b8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068911746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke.2068911746 |
| Directory | /workspace/63.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_large_delays.1476912482 |
| Short name | T1605 |
| Test name | |
| Test status | |
| Simulation time | 8914647433 ps |
| CPU time | 102.94 seconds |
| Started | May 30 03:56:06 PM PDT 24 |
| Finished | May 30 03:57:50 PM PDT 24 |
| Peak memory | 564976 kb |
| Host | smart-b07ee09e-581a-48e7-9f93-5ff00bbd70e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476912482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_large_delays.1476912482 |
| Directory | /workspace/63.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.904490462 |
| Short name | T2590 |
| Test name | |
| Test status | |
| Simulation time | 4776683411 ps |
| CPU time | 79.74 seconds |
| Started | May 30 03:56:06 PM PDT 24 |
| Finished | May 30 03:57:27 PM PDT 24 |
| Peak memory | 563472 kb |
| Host | smart-54e39ba5-ffa0-45b7-b6e9-db1ea2e31970 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904490462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_slow_rsp.904490462 |
| Directory | /workspace/63.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_zero_delays.542552207 |
| Short name | T2291 |
| Test name | |
| Test status | |
| Simulation time | 39113570 ps |
| CPU time | 6.22 seconds |
| Started | May 30 03:56:09 PM PDT 24 |
| Finished | May 30 03:56:16 PM PDT 24 |
| Peak memory | 564796 kb |
| Host | smart-263cce6b-cb7e-4791-8459-3dc2d1f883b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542552207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_zero_delays .542552207 |
| Directory | /workspace/63.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all.395039044 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 3169131219 ps |
| CPU time | 108.04 seconds |
| Started | May 30 03:56:16 PM PDT 24 |
| Finished | May 30 03:58:06 PM PDT 24 |
| Peak memory | 573220 kb |
| Host | smart-664bb79c-96c0-4676-a9d4-5820c732856f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395039044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all.395039044 |
| Directory | /workspace/63.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.3433574568 |
| Short name | T1553 |
| Test name | |
| Test status | |
| Simulation time | 3294070804 ps |
| CPU time | 126.57 seconds |
| Started | May 30 03:56:17 PM PDT 24 |
| Finished | May 30 03:58:25 PM PDT 24 |
| Peak memory | 573112 kb |
| Host | smart-51399547-7580-49ee-b9ae-f78d47be853d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433574568 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_error.3433574568 |
| Directory | /workspace/63.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.3978743942 |
| Short name | T2706 |
| Test name | |
| Test status | |
| Simulation time | 4760565655 ps |
| CPU time | 473.11 seconds |
| Started | May 30 03:56:13 PM PDT 24 |
| Finished | May 30 04:04:08 PM PDT 24 |
| Peak memory | 573152 kb |
| Host | smart-518424c2-9d9b-4f6d-91b4-e6a13c4c7adf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978743942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all _with_rand_reset.3978743942 |
| Directory | /workspace/63.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.3978993797 |
| Short name | T2139 |
| Test name | |
| Test status | |
| Simulation time | 240141092 ps |
| CPU time | 45.18 seconds |
| Started | May 30 03:56:16 PM PDT 24 |
| Finished | May 30 03:57:03 PM PDT 24 |
| Peak memory | 573104 kb |
| Host | smart-4d0cd1f0-de04-45cd-8327-804e8267bde9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978993797 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_al l_with_reset_error.3978993797 |
| Directory | /workspace/63.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_unmapped_addr.1294967023 |
| Short name | T2479 |
| Test name | |
| Test status | |
| Simulation time | 213182984 ps |
| CPU time | 12.02 seconds |
| Started | May 30 03:56:23 PM PDT 24 |
| Finished | May 30 03:56:36 PM PDT 24 |
| Peak memory | 572968 kb |
| Host | smart-cbd1820d-4c38-4888-b034-c7d6621c8309 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294967023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_unmapped_addr.1294967023 |
| Directory | /workspace/63.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device.126240177 |
| Short name | T2116 |
| Test name | |
| Test status | |
| Simulation time | 1389963820 ps |
| CPU time | 65.57 seconds |
| Started | May 30 03:56:14 PM PDT 24 |
| Finished | May 30 03:57:21 PM PDT 24 |
| Peak memory | 572972 kb |
| Host | smart-83a8de4b-eb59-432a-8796-189c2618e59d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126240177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device. 126240177 |
| Directory | /workspace/64.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.3525493498 |
| Short name | T1874 |
| Test name | |
| Test status | |
| Simulation time | 89624165436 ps |
| CPU time | 1710.73 seconds |
| Started | May 30 03:56:16 PM PDT 24 |
| Finished | May 30 04:24:48 PM PDT 24 |
| Peak memory | 573272 kb |
| Host | smart-acd6d6fe-c809-470f-962d-08d077f603d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525493498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_ device_slow_rsp.3525493498 |
| Directory | /workspace/64.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.3960991762 |
| Short name | T1368 |
| Test name | |
| Test status | |
| Simulation time | 288414954 ps |
| CPU time | 31.57 seconds |
| Started | May 30 03:56:15 PM PDT 24 |
| Finished | May 30 03:56:47 PM PDT 24 |
| Peak memory | 572864 kb |
| Host | smart-18c30548-5133-460d-9d5b-115a55f0fa3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960991762 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_and_unmapped_add r.3960991762 |
| Directory | /workspace/64.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_random.1908848036 |
| Short name | T1444 |
| Test name | |
| Test status | |
| Simulation time | 248679645 ps |
| CPU time | 19.65 seconds |
| Started | May 30 03:56:21 PM PDT 24 |
| Finished | May 30 03:56:42 PM PDT 24 |
| Peak memory | 572828 kb |
| Host | smart-117b30a3-8ab6-4904-a12d-5faece6c4000 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908848036 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_random.1908848036 |
| Directory | /workspace/64.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random.1900117255 |
| Short name | T2050 |
| Test name | |
| Test status | |
| Simulation time | 1897178662 ps |
| CPU time | 79.82 seconds |
| Started | May 30 03:56:15 PM PDT 24 |
| Finished | May 30 03:57:36 PM PDT 24 |
| Peak memory | 573056 kb |
| Host | smart-8614c995-fecc-4cb8-ba9b-f1831a8356be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900117255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random.1900117255 |
| Directory | /workspace/64.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_large_delays.1181956249 |
| Short name | T2767 |
| Test name | |
| Test status | |
| Simulation time | 67148580554 ps |
| CPU time | 795.74 seconds |
| Started | May 30 03:56:24 PM PDT 24 |
| Finished | May 30 04:09:41 PM PDT 24 |
| Peak memory | 573148 kb |
| Host | smart-d183b2ed-a458-4841-b23c-752f7bbe8df9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181956249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_large_delays.1181956249 |
| Directory | /workspace/64.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.1258047355 |
| Short name | T1675 |
| Test name | |
| Test status | |
| Simulation time | 23246019116 ps |
| CPU time | 400.58 seconds |
| Started | May 30 03:56:13 PM PDT 24 |
| Finished | May 30 04:02:55 PM PDT 24 |
| Peak memory | 573180 kb |
| Host | smart-d5c9c758-cfa3-4d27-8771-acad3f76fb4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258047355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_slow_rsp.1258047355 |
| Directory | /workspace/64.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_zero_delays.4032962228 |
| Short name | T2212 |
| Test name | |
| Test status | |
| Simulation time | 257380369 ps |
| CPU time | 23.09 seconds |
| Started | May 30 03:56:24 PM PDT 24 |
| Finished | May 30 03:56:48 PM PDT 24 |
| Peak memory | 573004 kb |
| Host | smart-f0644f0f-a7fa-4c8e-9e13-5a7d228d0001 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032962228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_zero_del ays.4032962228 |
| Directory | /workspace/64.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_same_source.2041160962 |
| Short name | T1999 |
| Test name | |
| Test status | |
| Simulation time | 302203304 ps |
| CPU time | 25.65 seconds |
| Started | May 30 03:56:16 PM PDT 24 |
| Finished | May 30 03:56:43 PM PDT 24 |
| Peak memory | 573060 kb |
| Host | smart-6149fd36-7871-43c6-b513-b7a7a72eff45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041160962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_same_source.2041160962 |
| Directory | /workspace/64.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke.555623348 |
| Short name | T2013 |
| Test name | |
| Test status | |
| Simulation time | 43788430 ps |
| CPU time | 5.82 seconds |
| Started | May 30 03:56:15 PM PDT 24 |
| Finished | May 30 03:56:21 PM PDT 24 |
| Peak memory | 564812 kb |
| Host | smart-f50d9360-63f1-422e-9bea-a9f21b1c3ba2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555623348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke.555623348 |
| Directory | /workspace/64.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_large_delays.3450201984 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 8438551997 ps |
| CPU time | 90.54 seconds |
| Started | May 30 03:56:16 PM PDT 24 |
| Finished | May 30 03:57:48 PM PDT 24 |
| Peak memory | 564884 kb |
| Host | smart-2b8692a8-975f-43cb-bdea-8dcd031fe154 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450201984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_large_delays.3450201984 |
| Directory | /workspace/64.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.3259274712 |
| Short name | T1417 |
| Test name | |
| Test status | |
| Simulation time | 6190258547 ps |
| CPU time | 105.63 seconds |
| Started | May 30 03:56:13 PM PDT 24 |
| Finished | May 30 03:57:59 PM PDT 24 |
| Peak memory | 564924 kb |
| Host | smart-b4c52f13-da58-461f-acb5-05fffce94205 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259274712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_slow_rsp.3259274712 |
| Directory | /workspace/64.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.854937682 |
| Short name | T1476 |
| Test name | |
| Test status | |
| Simulation time | 41802267 ps |
| CPU time | 5.97 seconds |
| Started | May 30 03:56:24 PM PDT 24 |
| Finished | May 30 03:56:31 PM PDT 24 |
| Peak memory | 564744 kb |
| Host | smart-500aa6d5-7636-4633-9012-1f5210b306c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854937682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_zero_delays .854937682 |
| Directory | /workspace/64.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all.1497837400 |
| Short name | T2152 |
| Test name | |
| Test status | |
| Simulation time | 6302520048 ps |
| CPU time | 241.06 seconds |
| Started | May 30 03:56:14 PM PDT 24 |
| Finished | May 30 04:00:17 PM PDT 24 |
| Peak memory | 573228 kb |
| Host | smart-e12d71f3-78fe-4ed8-aa5f-41a54f534d72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497837400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all.1497837400 |
| Directory | /workspace/64.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_error.1973792118 |
| Short name | T1326 |
| Test name | |
| Test status | |
| Simulation time | 5607494 ps |
| CPU time | 3.86 seconds |
| Started | May 30 03:56:14 PM PDT 24 |
| Finished | May 30 03:56:19 PM PDT 24 |
| Peak memory | 564504 kb |
| Host | smart-da30eddd-2684-400f-948c-f5b3240fca31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973792118 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_error.1973792118 |
| Directory | /workspace/64.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.363324112 |
| Short name | T2365 |
| Test name | |
| Test status | |
| Simulation time | 5159631627 ps |
| CPU time | 490.37 seconds |
| Started | May 30 03:56:16 PM PDT 24 |
| Finished | May 30 04:04:28 PM PDT 24 |
| Peak memory | 573288 kb |
| Host | smart-6b81d637-c2d2-4e0a-bb28-166a86b84ca8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363324112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_ with_rand_reset.363324112 |
| Directory | /workspace/64.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.3229256457 |
| Short name | T2135 |
| Test name | |
| Test status | |
| Simulation time | 278823902 ps |
| CPU time | 52.69 seconds |
| Started | May 30 03:56:15 PM PDT 24 |
| Finished | May 30 03:57:09 PM PDT 24 |
| Peak memory | 575160 kb |
| Host | smart-1e8bab0f-4837-4b6d-b329-cbb06da5c09f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229256457 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_al l_with_reset_error.3229256457 |
| Directory | /workspace/64.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.2545835192 |
| Short name | T2635 |
| Test name | |
| Test status | |
| Simulation time | 940467417 ps |
| CPU time | 38.9 seconds |
| Started | May 30 03:56:24 PM PDT 24 |
| Finished | May 30 03:57:04 PM PDT 24 |
| Peak memory | 573016 kb |
| Host | smart-863dbeae-495c-44af-bd0e-3bc45660f1b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545835192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_unmapped_addr.2545835192 |
| Directory | /workspace/64.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device.3865353723 |
| Short name | T1709 |
| Test name | |
| Test status | |
| Simulation time | 227552580 ps |
| CPU time | 22.1 seconds |
| Started | May 30 03:56:30 PM PDT 24 |
| Finished | May 30 03:56:53 PM PDT 24 |
| Peak memory | 573048 kb |
| Host | smart-99b746f5-8f40-4129-84b0-0dd3642de6b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865353723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device .3865353723 |
| Directory | /workspace/65.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.4135014184 |
| Short name | T2270 |
| Test name | |
| Test status | |
| Simulation time | 104623571906 ps |
| CPU time | 1858.89 seconds |
| Started | May 30 03:56:28 PM PDT 24 |
| Finished | May 30 04:27:28 PM PDT 24 |
| Peak memory | 573268 kb |
| Host | smart-c30eb1ae-1efa-43b3-9b6b-b6e21665bfef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135014184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_ device_slow_rsp.4135014184 |
| Directory | /workspace/65.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.1172697972 |
| Short name | T1625 |
| Test name | |
| Test status | |
| Simulation time | 521182553 ps |
| CPU time | 23.08 seconds |
| Started | May 30 03:56:23 PM PDT 24 |
| Finished | May 30 03:56:47 PM PDT 24 |
| Peak memory | 572920 kb |
| Host | smart-5b160800-fa37-4b7f-a957-c1373ef5ec63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172697972 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_and_unmapped_add r.1172697972 |
| Directory | /workspace/65.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_random.2800280033 |
| Short name | T1358 |
| Test name | |
| Test status | |
| Simulation time | 156370419 ps |
| CPU time | 15.04 seconds |
| Started | May 30 03:56:24 PM PDT 24 |
| Finished | May 30 03:56:40 PM PDT 24 |
| Peak memory | 572920 kb |
| Host | smart-43570449-3389-4121-8317-ab295f7b0a5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800280033 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_random.2800280033 |
| Directory | /workspace/65.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random.2365998762 |
| Short name | T2296 |
| Test name | |
| Test status | |
| Simulation time | 457450778 ps |
| CPU time | 42.1 seconds |
| Started | May 30 03:56:24 PM PDT 24 |
| Finished | May 30 03:57:07 PM PDT 24 |
| Peak memory | 572940 kb |
| Host | smart-15efed0a-f896-4cf5-b81b-a7b63d3eee30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365998762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random.2365998762 |
| Directory | /workspace/65.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_large_delays.2259624566 |
| Short name | T1711 |
| Test name | |
| Test status | |
| Simulation time | 24648046686 ps |
| CPU time | 262.85 seconds |
| Started | May 30 03:56:27 PM PDT 24 |
| Finished | May 30 04:00:50 PM PDT 24 |
| Peak memory | 573100 kb |
| Host | smart-7adba8d2-193d-4bb5-b2b8-c26ab600c9ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259624566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_large_delays.2259624566 |
| Directory | /workspace/65.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.1538649372 |
| Short name | T2402 |
| Test name | |
| Test status | |
| Simulation time | 35726421301 ps |
| CPU time | 578.33 seconds |
| Started | May 30 03:56:32 PM PDT 24 |
| Finished | May 30 04:06:12 PM PDT 24 |
| Peak memory | 573104 kb |
| Host | smart-9c319224-d681-4908-a090-3ca360f1bbb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538649372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_slow_rsp.1538649372 |
| Directory | /workspace/65.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.3823122454 |
| Short name | T1957 |
| Test name | |
| Test status | |
| Simulation time | 416610891 ps |
| CPU time | 38.96 seconds |
| Started | May 30 03:56:23 PM PDT 24 |
| Finished | May 30 03:57:03 PM PDT 24 |
| Peak memory | 572964 kb |
| Host | smart-a5651508-fd02-4b97-ba68-e62ea7564c18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823122454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_zero_del ays.3823122454 |
| Directory | /workspace/65.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_same_source.4241301799 |
| Short name | T1840 |
| Test name | |
| Test status | |
| Simulation time | 1836959549 ps |
| CPU time | 56.89 seconds |
| Started | May 30 03:56:25 PM PDT 24 |
| Finished | May 30 03:57:22 PM PDT 24 |
| Peak memory | 573080 kb |
| Host | smart-8b77e3a1-c93a-456d-a6f3-5d4e37015f87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241301799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_same_source.4241301799 |
| Directory | /workspace/65.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke.2603554410 |
| Short name | T1356 |
| Test name | |
| Test status | |
| Simulation time | 161634100 ps |
| CPU time | 7.51 seconds |
| Started | May 30 03:56:16 PM PDT 24 |
| Finished | May 30 03:56:25 PM PDT 24 |
| Peak memory | 564816 kb |
| Host | smart-e0f8b67e-c2f8-4bc3-b293-f3912935c0c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603554410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke.2603554410 |
| Directory | /workspace/65.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_large_delays.4048604969 |
| Short name | T1904 |
| Test name | |
| Test status | |
| Simulation time | 8448758183 ps |
| CPU time | 86.07 seconds |
| Started | May 30 03:56:15 PM PDT 24 |
| Finished | May 30 03:57:42 PM PDT 24 |
| Peak memory | 564916 kb |
| Host | smart-4291304c-6274-4fbb-9270-ab15c39148c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048604969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_large_delays.4048604969 |
| Directory | /workspace/65.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.2129228035 |
| Short name | T1364 |
| Test name | |
| Test status | |
| Simulation time | 6446807084 ps |
| CPU time | 111.83 seconds |
| Started | May 30 03:56:22 PM PDT 24 |
| Finished | May 30 03:58:15 PM PDT 24 |
| Peak memory | 564968 kb |
| Host | smart-c0f69948-9d26-45de-8009-7e1bf93fb2a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129228035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_slow_rsp.2129228035 |
| Directory | /workspace/65.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.3145784228 |
| Short name | T1574 |
| Test name | |
| Test status | |
| Simulation time | 43688676 ps |
| CPU time | 6.09 seconds |
| Started | May 30 03:56:16 PM PDT 24 |
| Finished | May 30 03:56:24 PM PDT 24 |
| Peak memory | 564792 kb |
| Host | smart-21ff850c-9df5-4d28-b375-03f6d0b24fb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145784228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_zero_delay s.3145784228 |
| Directory | /workspace/65.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all.4003412215 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 3400999938 ps |
| CPU time | 267.55 seconds |
| Started | May 30 03:56:26 PM PDT 24 |
| Finished | May 30 04:00:54 PM PDT 24 |
| Peak memory | 573116 kb |
| Host | smart-9c61e0a9-39c1-4b18-a886-0d784e4529a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003412215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all.4003412215 |
| Directory | /workspace/65.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.4236283362 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 408842319 ps |
| CPU time | 183.4 seconds |
| Started | May 30 03:56:30 PM PDT 24 |
| Finished | May 30 03:59:34 PM PDT 24 |
| Peak memory | 573100 kb |
| Host | smart-218c3f55-68bb-49af-b916-febc509f91c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236283362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all _with_rand_reset.4236283362 |
| Directory | /workspace/65.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.771562361 |
| Short name | T2004 |
| Test name | |
| Test status | |
| Simulation time | 17161995514 ps |
| CPU time | 760.52 seconds |
| Started | May 30 03:56:29 PM PDT 24 |
| Finished | May 30 04:09:10 PM PDT 24 |
| Peak memory | 580144 kb |
| Host | smart-fcc04810-6e58-47fc-b59b-02ca0e910430 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771562361 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all _with_reset_error.771562361 |
| Directory | /workspace/65.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_unmapped_addr.4036586198 |
| Short name | T2160 |
| Test name | |
| Test status | |
| Simulation time | 112965400 ps |
| CPU time | 14.26 seconds |
| Started | May 30 03:56:30 PM PDT 24 |
| Finished | May 30 03:56:45 PM PDT 24 |
| Peak memory | 572976 kb |
| Host | smart-ab3faa8d-9cb1-4570-9c53-d4873e029b79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036586198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_unmapped_addr.4036586198 |
| Directory | /workspace/65.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device.2967905470 |
| Short name | T2528 |
| Test name | |
| Test status | |
| Simulation time | 1077388738 ps |
| CPU time | 45.03 seconds |
| Started | May 30 03:56:25 PM PDT 24 |
| Finished | May 30 03:57:11 PM PDT 24 |
| Peak memory | 564848 kb |
| Host | smart-e97f2b6f-c659-4f0d-8cf3-b169c17db632 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967905470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device .2967905470 |
| Directory | /workspace/66.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.3716026852 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 65980892611 ps |
| CPU time | 1196.75 seconds |
| Started | May 30 03:56:35 PM PDT 24 |
| Finished | May 30 04:16:34 PM PDT 24 |
| Peak memory | 573268 kb |
| Host | smart-61486822-1c24-4500-8ce1-0a8c8c8fd6b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716026852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_ device_slow_rsp.3716026852 |
| Directory | /workspace/66.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.1503088662 |
| Short name | T2652 |
| Test name | |
| Test status | |
| Simulation time | 108385938 ps |
| CPU time | 7.56 seconds |
| Started | May 30 03:56:34 PM PDT 24 |
| Finished | May 30 03:56:44 PM PDT 24 |
| Peak memory | 564736 kb |
| Host | smart-808bcf4b-6c7d-475e-8b56-4970e2ebc5f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503088662 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_and_unmapped_add r.1503088662 |
| Directory | /workspace/66.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_random.189774932 |
| Short name | T2804 |
| Test name | |
| Test status | |
| Simulation time | 492958513 ps |
| CPU time | 45.21 seconds |
| Started | May 30 03:56:34 PM PDT 24 |
| Finished | May 30 03:57:20 PM PDT 24 |
| Peak memory | 572892 kb |
| Host | smart-86a758c2-8daf-4382-89b6-1d6575c89471 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189774932 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_random.189774932 |
| Directory | /workspace/66.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random.4093508104 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 1044521110 ps |
| CPU time | 36.14 seconds |
| Started | May 30 03:56:24 PM PDT 24 |
| Finished | May 30 03:57:01 PM PDT 24 |
| Peak memory | 572620 kb |
| Host | smart-d32da569-bc50-4adf-9efd-084232af0dcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093508104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random.4093508104 |
| Directory | /workspace/66.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_large_delays.3461276548 |
| Short name | T2056 |
| Test name | |
| Test status | |
| Simulation time | 5641020837 ps |
| CPU time | 60.25 seconds |
| Started | May 30 03:56:32 PM PDT 24 |
| Finished | May 30 03:57:33 PM PDT 24 |
| Peak memory | 564936 kb |
| Host | smart-75c9822a-804c-48cf-bcfd-22a0b52bd420 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461276548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_large_delays.3461276548 |
| Directory | /workspace/66.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_slow_rsp.2226380824 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 40065804240 ps |
| CPU time | 747.02 seconds |
| Started | May 30 03:56:32 PM PDT 24 |
| Finished | May 30 04:09:00 PM PDT 24 |
| Peak memory | 573168 kb |
| Host | smart-cc67d38a-6299-4974-ac31-26304388f666 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226380824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_slow_rsp.2226380824 |
| Directory | /workspace/66.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_zero_delays.1957489197 |
| Short name | T1567 |
| Test name | |
| Test status | |
| Simulation time | 307744219 ps |
| CPU time | 27.65 seconds |
| Started | May 30 03:56:27 PM PDT 24 |
| Finished | May 30 03:56:55 PM PDT 24 |
| Peak memory | 573056 kb |
| Host | smart-70ad5f79-c43c-4700-86ed-dcd6f4f69233 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957489197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_zero_del ays.1957489197 |
| Directory | /workspace/66.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_same_source.667987017 |
| Short name | T1646 |
| Test name | |
| Test status | |
| Simulation time | 2340564031 ps |
| CPU time | 70.34 seconds |
| Started | May 30 03:56:35 PM PDT 24 |
| Finished | May 30 03:57:47 PM PDT 24 |
| Peak memory | 573004 kb |
| Host | smart-8ca41e02-5a6d-4f01-86d6-9ec59f8e76cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667987017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_same_source.667987017 |
| Directory | /workspace/66.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke.1248297125 |
| Short name | T2551 |
| Test name | |
| Test status | |
| Simulation time | 42835895 ps |
| CPU time | 5.97 seconds |
| Started | May 30 03:56:28 PM PDT 24 |
| Finished | May 30 03:56:35 PM PDT 24 |
| Peak memory | 564832 kb |
| Host | smart-06342039-0ef1-4e9a-8785-ce8fa9d42820 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248297125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke.1248297125 |
| Directory | /workspace/66.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_large_delays.3778199126 |
| Short name | T1532 |
| Test name | |
| Test status | |
| Simulation time | 9086071812 ps |
| CPU time | 103.44 seconds |
| Started | May 30 03:56:31 PM PDT 24 |
| Finished | May 30 03:58:15 PM PDT 24 |
| Peak memory | 564944 kb |
| Host | smart-fa851e32-85bc-494e-9d58-db5ac9ac5644 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778199126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_large_delays.3778199126 |
| Directory | /workspace/66.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.2896753082 |
| Short name | T1423 |
| Test name | |
| Test status | |
| Simulation time | 6322366981 ps |
| CPU time | 113.27 seconds |
| Started | May 30 03:56:29 PM PDT 24 |
| Finished | May 30 03:58:23 PM PDT 24 |
| Peak memory | 564944 kb |
| Host | smart-d11bb7ee-4329-426d-9e77-1fdde0c9703c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896753082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_slow_rsp.2896753082 |
| Directory | /workspace/66.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.2299825944 |
| Short name | T2686 |
| Test name | |
| Test status | |
| Simulation time | 50766366 ps |
| CPU time | 6.57 seconds |
| Started | May 30 03:56:27 PM PDT 24 |
| Finished | May 30 03:56:34 PM PDT 24 |
| Peak memory | 564784 kb |
| Host | smart-a0e78fa3-5a05-4042-8b61-d5e5282779b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299825944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_zero_delay s.2299825944 |
| Directory | /workspace/66.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all.2907811340 |
| Short name | T1669 |
| Test name | |
| Test status | |
| Simulation time | 15417158054 ps |
| CPU time | 600.25 seconds |
| Started | May 30 03:56:39 PM PDT 24 |
| Finished | May 30 04:06:41 PM PDT 24 |
| Peak memory | 573248 kb |
| Host | smart-12a2836c-c418-451f-9300-f128ad5b3f94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907811340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all.2907811340 |
| Directory | /workspace/66.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.3775329837 |
| Short name | T2814 |
| Test name | |
| Test status | |
| Simulation time | 4992062745 ps |
| CPU time | 163.08 seconds |
| Started | May 30 03:56:34 PM PDT 24 |
| Finished | May 30 03:59:18 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-19ed3b6e-b52c-4a10-beaa-40a26278f2fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775329837 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_error.3775329837 |
| Directory | /workspace/66.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.2963315511 |
| Short name | T1809 |
| Test name | |
| Test status | |
| Simulation time | 5946415854 ps |
| CPU time | 384.11 seconds |
| Started | May 30 03:56:39 PM PDT 24 |
| Finished | May 30 04:03:05 PM PDT 24 |
| Peak memory | 573304 kb |
| Host | smart-21d45c65-5eaa-413b-af30-4b2723b5d133 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963315511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all _with_rand_reset.2963315511 |
| Directory | /workspace/66.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.4243122639 |
| Short name | T1839 |
| Test name | |
| Test status | |
| Simulation time | 82096489 ps |
| CPU time | 11.33 seconds |
| Started | May 30 03:56:34 PM PDT 24 |
| Finished | May 30 03:56:46 PM PDT 24 |
| Peak memory | 564760 kb |
| Host | smart-f7dd3468-f6d7-41de-830f-509f21705d9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243122639 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_al l_with_reset_error.4243122639 |
| Directory | /workspace/66.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.885347049 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 1025938047 ps |
| CPU time | 41.68 seconds |
| Started | May 30 03:56:35 PM PDT 24 |
| Finished | May 30 03:57:18 PM PDT 24 |
| Peak memory | 573008 kb |
| Host | smart-5c875303-418b-42a4-bbf5-ad01f1526510 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885347049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_unmapped_addr.885347049 |
| Directory | /workspace/66.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device.438890287 |
| Short name | T1343 |
| Test name | |
| Test status | |
| Simulation time | 248941588 ps |
| CPU time | 13.98 seconds |
| Started | May 30 03:56:34 PM PDT 24 |
| Finished | May 30 03:56:50 PM PDT 24 |
| Peak memory | 564752 kb |
| Host | smart-b35b218f-4b7f-4abc-993f-09ea0d63b5b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438890287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device. 438890287 |
| Directory | /workspace/67.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.1150703196 |
| Short name | T2851 |
| Test name | |
| Test status | |
| Simulation time | 127644592137 ps |
| CPU time | 2288.13 seconds |
| Started | May 30 03:56:34 PM PDT 24 |
| Finished | May 30 04:34:43 PM PDT 24 |
| Peak memory | 573332 kb |
| Host | smart-d5fb7a78-3126-434c-a710-157f50229f66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150703196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_ device_slow_rsp.1150703196 |
| Directory | /workspace/67.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.1582398131 |
| Short name | T1407 |
| Test name | |
| Test status | |
| Simulation time | 198034702 ps |
| CPU time | 23.17 seconds |
| Started | May 30 03:56:43 PM PDT 24 |
| Finished | May 30 03:57:07 PM PDT 24 |
| Peak memory | 572936 kb |
| Host | smart-b548c419-454d-4c4a-80a0-e94a3b4cd984 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582398131 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_and_unmapped_add r.1582398131 |
| Directory | /workspace/67.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_random.2451693469 |
| Short name | T1828 |
| Test name | |
| Test status | |
| Simulation time | 2016811892 ps |
| CPU time | 70.69 seconds |
| Started | May 30 03:56:40 PM PDT 24 |
| Finished | May 30 03:57:52 PM PDT 24 |
| Peak memory | 572876 kb |
| Host | smart-1a4bd859-f675-42ff-bf63-82532b62d403 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451693469 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_random.2451693469 |
| Directory | /workspace/67.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random.4233349548 |
| Short name | T2628 |
| Test name | |
| Test status | |
| Simulation time | 243701692 ps |
| CPU time | 21.89 seconds |
| Started | May 30 03:56:34 PM PDT 24 |
| Finished | May 30 03:56:58 PM PDT 24 |
| Peak memory | 573020 kb |
| Host | smart-10b05915-5081-4c5e-ac53-fc847b85f18a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233349548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random.4233349548 |
| Directory | /workspace/67.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_large_delays.1199063562 |
| Short name | T1647 |
| Test name | |
| Test status | |
| Simulation time | 25003275207 ps |
| CPU time | 282.35 seconds |
| Started | May 30 03:56:36 PM PDT 24 |
| Finished | May 30 04:01:20 PM PDT 24 |
| Peak memory | 573188 kb |
| Host | smart-d8068ccc-df77-43c5-8903-438ccbeb4bb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199063562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_large_delays.1199063562 |
| Directory | /workspace/67.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_slow_rsp.2214499590 |
| Short name | T2748 |
| Test name | |
| Test status | |
| Simulation time | 55632972054 ps |
| CPU time | 920.1 seconds |
| Started | May 30 03:56:35 PM PDT 24 |
| Finished | May 30 04:11:57 PM PDT 24 |
| Peak memory | 573192 kb |
| Host | smart-bbfe3308-8f25-4f7a-8f24-e804d9e43d74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214499590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_slow_rsp.2214499590 |
| Directory | /workspace/67.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.3716225424 |
| Short name | T2794 |
| Test name | |
| Test status | |
| Simulation time | 606054931 ps |
| CPU time | 52.84 seconds |
| Started | May 30 03:56:42 PM PDT 24 |
| Finished | May 30 03:57:35 PM PDT 24 |
| Peak memory | 573040 kb |
| Host | smart-fb94e855-9b09-4dea-82ea-7362042c9734 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716225424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_zero_del ays.3716225424 |
| Directory | /workspace/67.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_same_source.3333658515 |
| Short name | T2552 |
| Test name | |
| Test status | |
| Simulation time | 2350139004 ps |
| CPU time | 74.53 seconds |
| Started | May 30 03:56:37 PM PDT 24 |
| Finished | May 30 03:57:53 PM PDT 24 |
| Peak memory | 573100 kb |
| Host | smart-79514b96-81a9-4650-baeb-9600a61153af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333658515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_same_source.3333658515 |
| Directory | /workspace/67.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke.3453538756 |
| Short name | T2105 |
| Test name | |
| Test status | |
| Simulation time | 178718183 ps |
| CPU time | 8.53 seconds |
| Started | May 30 03:56:34 PM PDT 24 |
| Finished | May 30 03:56:45 PM PDT 24 |
| Peak memory | 564836 kb |
| Host | smart-0b37a1d7-1ed4-4441-99a3-73b15f42028c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453538756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke.3453538756 |
| Directory | /workspace/67.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_large_delays.2301806516 |
| Short name | T1704 |
| Test name | |
| Test status | |
| Simulation time | 8075333715 ps |
| CPU time | 81.9 seconds |
| Started | May 30 03:56:34 PM PDT 24 |
| Finished | May 30 03:57:58 PM PDT 24 |
| Peak memory | 564968 kb |
| Host | smart-a14ddde1-3333-4ccc-af76-15763bbcc25c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301806516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_large_delays.2301806516 |
| Directory | /workspace/67.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.4016228198 |
| Short name | T2346 |
| Test name | |
| Test status | |
| Simulation time | 4062855178 ps |
| CPU time | 73.08 seconds |
| Started | May 30 03:56:36 PM PDT 24 |
| Finished | May 30 03:57:51 PM PDT 24 |
| Peak memory | 564892 kb |
| Host | smart-f8dd9f4f-9e75-4755-88e9-211a9cce6df9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016228198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_slow_rsp.4016228198 |
| Directory | /workspace/67.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_zero_delays.3478021104 |
| Short name | T1432 |
| Test name | |
| Test status | |
| Simulation time | 51547511 ps |
| CPU time | 6.66 seconds |
| Started | May 30 03:56:40 PM PDT 24 |
| Finished | May 30 03:56:48 PM PDT 24 |
| Peak memory | 564796 kb |
| Host | smart-d19880d2-573b-468b-80bd-be0fa6aea9f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478021104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_zero_delay s.3478021104 |
| Directory | /workspace/67.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all.2262829073 |
| Short name | T2149 |
| Test name | |
| Test status | |
| Simulation time | 2241710578 ps |
| CPU time | 82.97 seconds |
| Started | May 30 03:56:50 PM PDT 24 |
| Finished | May 30 03:58:13 PM PDT 24 |
| Peak memory | 573096 kb |
| Host | smart-e49fe087-5f2c-4cf1-af42-ec005a83e39b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262829073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all.2262829073 |
| Directory | /workspace/67.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_error.1035226649 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 7520158073 ps |
| CPU time | 262.44 seconds |
| Started | May 30 03:56:49 PM PDT 24 |
| Finished | May 30 04:01:12 PM PDT 24 |
| Peak memory | 573124 kb |
| Host | smart-1d343768-d1ac-4ad7-99f0-77727aba8248 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035226649 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_error.1035226649 |
| Directory | /workspace/67.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.891701589 |
| Short name | T2472 |
| Test name | |
| Test status | |
| Simulation time | 582653466 ps |
| CPU time | 221.89 seconds |
| Started | May 30 03:56:46 PM PDT 24 |
| Finished | May 30 04:00:28 PM PDT 24 |
| Peak memory | 577412 kb |
| Host | smart-105c47d0-bc4c-43b8-8a27-87c74b728acc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891701589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_ with_rand_reset.891701589 |
| Directory | /workspace/67.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.1369031901 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 466441789 ps |
| CPU time | 119.37 seconds |
| Started | May 30 03:56:46 PM PDT 24 |
| Finished | May 30 03:58:46 PM PDT 24 |
| Peak memory | 573036 kb |
| Host | smart-e67055d0-81e3-4a19-bef9-9042316b3d02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369031901 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_al l_with_reset_error.1369031901 |
| Directory | /workspace/67.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_unmapped_addr.3369867004 |
| Short name | T2702 |
| Test name | |
| Test status | |
| Simulation time | 565856604 ps |
| CPU time | 24.62 seconds |
| Started | May 30 03:56:45 PM PDT 24 |
| Finished | May 30 03:57:10 PM PDT 24 |
| Peak memory | 573100 kb |
| Host | smart-bb92ea81-f4cb-4429-9711-918408eae362 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369867004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_unmapped_addr.3369867004 |
| Directory | /workspace/67.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device.1254131298 |
| Short name | T2267 |
| Test name | |
| Test status | |
| Simulation time | 3006569919 ps |
| CPU time | 127.59 seconds |
| Started | May 30 03:56:44 PM PDT 24 |
| Finished | May 30 03:58:52 PM PDT 24 |
| Peak memory | 573132 kb |
| Host | smart-239357fa-6d0d-4215-8bfc-021a13791d3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254131298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device .1254131298 |
| Directory | /workspace/68.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.3789086609 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 57667655 ps |
| CPU time | 8.46 seconds |
| Started | May 30 03:56:48 PM PDT 24 |
| Finished | May 30 03:56:57 PM PDT 24 |
| Peak memory | 572896 kb |
| Host | smart-338c6465-c1fc-47f0-8fc3-799b8ff7ba41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789086609 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_and_unmapped_add r.3789086609 |
| Directory | /workspace/68.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_random.1009229706 |
| Short name | T1910 |
| Test name | |
| Test status | |
| Simulation time | 1288820344 ps |
| CPU time | 35.78 seconds |
| Started | May 30 03:56:47 PM PDT 24 |
| Finished | May 30 03:57:24 PM PDT 24 |
| Peak memory | 572940 kb |
| Host | smart-851a08f5-6430-4ca0-a4aa-d70c80d806e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009229706 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_random.1009229706 |
| Directory | /workspace/68.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random.4098078936 |
| Short name | T1511 |
| Test name | |
| Test status | |
| Simulation time | 1604418024 ps |
| CPU time | 57.81 seconds |
| Started | May 30 03:56:45 PM PDT 24 |
| Finished | May 30 03:57:44 PM PDT 24 |
| Peak memory | 573076 kb |
| Host | smart-99bcfa4a-8e0b-4b05-a21a-818dab42fc31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098078936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random.4098078936 |
| Directory | /workspace/68.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_large_delays.1857188759 |
| Short name | T1513 |
| Test name | |
| Test status | |
| Simulation time | 58030705275 ps |
| CPU time | 670.92 seconds |
| Started | May 30 03:56:45 PM PDT 24 |
| Finished | May 30 04:07:56 PM PDT 24 |
| Peak memory | 573120 kb |
| Host | smart-40a8810a-b2f9-423a-ac7e-0ec2626ef2be |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857188759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_large_delays.1857188759 |
| Directory | /workspace/68.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_slow_rsp.2138240807 |
| Short name | T2449 |
| Test name | |
| Test status | |
| Simulation time | 47166293122 ps |
| CPU time | 899.06 seconds |
| Started | May 30 03:56:48 PM PDT 24 |
| Finished | May 30 04:11:48 PM PDT 24 |
| Peak memory | 573180 kb |
| Host | smart-721c3e7c-b67a-424e-87bf-fa663668a76e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138240807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_slow_rsp.2138240807 |
| Directory | /workspace/68.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_zero_delays.4080024875 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 505541360 ps |
| CPU time | 42.99 seconds |
| Started | May 30 03:56:45 PM PDT 24 |
| Finished | May 30 03:57:29 PM PDT 24 |
| Peak memory | 573020 kb |
| Host | smart-07ea8f2c-fd40-439c-a2a1-d7015fdb49b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080024875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_zero_del ays.4080024875 |
| Directory | /workspace/68.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_same_source.1716152967 |
| Short name | T2123 |
| Test name | |
| Test status | |
| Simulation time | 1939507168 ps |
| CPU time | 60.26 seconds |
| Started | May 30 03:56:46 PM PDT 24 |
| Finished | May 30 03:57:48 PM PDT 24 |
| Peak memory | 573064 kb |
| Host | smart-8d970ed3-29a4-4a1f-8070-f0cce63ff2b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716152967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_same_source.1716152967 |
| Directory | /workspace/68.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke.3435788680 |
| Short name | T1360 |
| Test name | |
| Test status | |
| Simulation time | 181188109 ps |
| CPU time | 9 seconds |
| Started | May 30 03:56:45 PM PDT 24 |
| Finished | May 30 03:56:55 PM PDT 24 |
| Peak memory | 564836 kb |
| Host | smart-56f27351-d6cd-4533-8f47-88815fe50b2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435788680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke.3435788680 |
| Directory | /workspace/68.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_large_delays.167969725 |
| Short name | T1318 |
| Test name | |
| Test status | |
| Simulation time | 8112011372 ps |
| CPU time | 93.74 seconds |
| Started | May 30 03:56:46 PM PDT 24 |
| Finished | May 30 03:58:21 PM PDT 24 |
| Peak memory | 563520 kb |
| Host | smart-fc8f787c-68b2-40e7-a89a-36aca00631ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167969725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_large_delays.167969725 |
| Directory | /workspace/68.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.2377934100 |
| Short name | T1860 |
| Test name | |
| Test status | |
| Simulation time | 5472855943 ps |
| CPU time | 96.3 seconds |
| Started | May 30 03:56:52 PM PDT 24 |
| Finished | May 30 03:58:29 PM PDT 24 |
| Peak memory | 563536 kb |
| Host | smart-7d9c4374-0d91-4613-bbcc-2f92bebf8860 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377934100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_slow_rsp.2377934100 |
| Directory | /workspace/68.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_zero_delays.1074276481 |
| Short name | T2422 |
| Test name | |
| Test status | |
| Simulation time | 40706271 ps |
| CPU time | 5.77 seconds |
| Started | May 30 03:56:45 PM PDT 24 |
| Finished | May 30 03:56:52 PM PDT 24 |
| Peak memory | 564824 kb |
| Host | smart-12983116-bea2-4077-bf63-6b39a06297ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074276481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_zero_delay s.1074276481 |
| Directory | /workspace/68.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.558150930 |
| Short name | T2563 |
| Test name | |
| Test status | |
| Simulation time | 3536569639 ps |
| CPU time | 129.13 seconds |
| Started | May 30 03:56:44 PM PDT 24 |
| Finished | May 30 03:58:54 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-679aabf3-1fb7-441a-b0ff-fa96503428c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558150930 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_error.558150930 |
| Directory | /workspace/68.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.3145203536 |
| Short name | T2040 |
| Test name | |
| Test status | |
| Simulation time | 38528306 ps |
| CPU time | 28.6 seconds |
| Started | May 30 03:56:46 PM PDT 24 |
| Finished | May 30 03:57:16 PM PDT 24 |
| Peak memory | 564964 kb |
| Host | smart-e2e3060e-3c6e-4d30-8d5e-3909523e27f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145203536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all _with_rand_reset.3145203536 |
| Directory | /workspace/68.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.1438196045 |
| Short name | T2586 |
| Test name | |
| Test status | |
| Simulation time | 5999321340 ps |
| CPU time | 212.68 seconds |
| Started | May 30 03:56:49 PM PDT 24 |
| Finished | May 30 04:00:22 PM PDT 24 |
| Peak memory | 573156 kb |
| Host | smart-21dc0924-a06f-4488-b00c-158a975b6a31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438196045 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_al l_with_reset_error.1438196045 |
| Directory | /workspace/68.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_unmapped_addr.302523297 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 1326161153 ps |
| CPU time | 53.82 seconds |
| Started | May 30 03:56:45 PM PDT 24 |
| Finished | May 30 03:57:40 PM PDT 24 |
| Peak memory | 573028 kb |
| Host | smart-2343acf2-d79f-48d9-ae89-724469406d65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302523297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_unmapped_addr.302523297 |
| Directory | /workspace/68.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device.4167837437 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 3362818657 ps |
| CPU time | 127.51 seconds |
| Started | May 30 03:56:54 PM PDT 24 |
| Finished | May 30 03:59:02 PM PDT 24 |
| Peak memory | 573036 kb |
| Host | smart-f9033e73-da19-443b-badb-29b094fce34c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167837437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device .4167837437 |
| Directory | /workspace/69.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.3726763045 |
| Short name | T2224 |
| Test name | |
| Test status | |
| Simulation time | 59706550957 ps |
| CPU time | 1063.67 seconds |
| Started | May 30 03:56:55 PM PDT 24 |
| Finished | May 30 04:14:40 PM PDT 24 |
| Peak memory | 573180 kb |
| Host | smart-499d6927-328a-48d7-978c-9cc4c97ab0ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726763045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_ device_slow_rsp.3726763045 |
| Directory | /workspace/69.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.617731470 |
| Short name | T1803 |
| Test name | |
| Test status | |
| Simulation time | 1361420996 ps |
| CPU time | 49.26 seconds |
| Started | May 30 03:56:57 PM PDT 24 |
| Finished | May 30 03:57:47 PM PDT 24 |
| Peak memory | 572836 kb |
| Host | smart-48900c8e-22aa-4073-8acf-77e09942760a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617731470 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_and_unmapped_addr .617731470 |
| Directory | /workspace/69.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_random.1243192595 |
| Short name | T1482 |
| Test name | |
| Test status | |
| Simulation time | 2199511946 ps |
| CPU time | 80.88 seconds |
| Started | May 30 03:56:54 PM PDT 24 |
| Finished | May 30 03:58:16 PM PDT 24 |
| Peak memory | 572952 kb |
| Host | smart-a370a260-1874-4a3d-b2aa-abb1b41fde48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243192595 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_random.1243192595 |
| Directory | /workspace/69.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random.29776685 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 2055754624 ps |
| CPU time | 68.64 seconds |
| Started | May 30 03:56:55 PM PDT 24 |
| Finished | May 30 03:58:04 PM PDT 24 |
| Peak memory | 573092 kb |
| Host | smart-2d40b6a3-a60a-4a08-82fa-5688168a960c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29776685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random.29776685 |
| Directory | /workspace/69.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_large_delays.3215176026 |
| Short name | T2285 |
| Test name | |
| Test status | |
| Simulation time | 105224402411 ps |
| CPU time | 1154.61 seconds |
| Started | May 30 03:56:54 PM PDT 24 |
| Finished | May 30 04:16:10 PM PDT 24 |
| Peak memory | 573224 kb |
| Host | smart-6c23482f-be3e-4ce7-943b-861458812bbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215176026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_large_delays.3215176026 |
| Directory | /workspace/69.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_slow_rsp.751954663 |
| Short name | T1748 |
| Test name | |
| Test status | |
| Simulation time | 61202659883 ps |
| CPU time | 1081.02 seconds |
| Started | May 30 03:56:57 PM PDT 24 |
| Finished | May 30 04:14:59 PM PDT 24 |
| Peak memory | 573100 kb |
| Host | smart-a6724ad7-8d00-4f7c-a6fc-13a7719d8453 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751954663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_slow_rsp.751954663 |
| Directory | /workspace/69.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_zero_delays.318056193 |
| Short name | T2082 |
| Test name | |
| Test status | |
| Simulation time | 221022859 ps |
| CPU time | 19.44 seconds |
| Started | May 30 03:56:55 PM PDT 24 |
| Finished | May 30 03:57:16 PM PDT 24 |
| Peak memory | 573016 kb |
| Host | smart-5a97b920-0204-4f44-abed-0f4c86390b1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318056193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_zero_dela ys.318056193 |
| Directory | /workspace/69.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_same_source.634868872 |
| Short name | T1546 |
| Test name | |
| Test status | |
| Simulation time | 1714299913 ps |
| CPU time | 45.61 seconds |
| Started | May 30 03:56:56 PM PDT 24 |
| Finished | May 30 03:57:43 PM PDT 24 |
| Peak memory | 573060 kb |
| Host | smart-2caedcb3-a2b2-4b73-bcd4-926442df0b76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634868872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_same_source.634868872 |
| Directory | /workspace/69.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke.1295041240 |
| Short name | T1442 |
| Test name | |
| Test status | |
| Simulation time | 47007925 ps |
| CPU time | 6.32 seconds |
| Started | May 30 03:56:51 PM PDT 24 |
| Finished | May 30 03:56:58 PM PDT 24 |
| Peak memory | 564840 kb |
| Host | smart-687ac5c4-797a-47f6-8fd5-19f4dd9da71e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295041240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke.1295041240 |
| Directory | /workspace/69.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_large_delays.2397181536 |
| Short name | T1498 |
| Test name | |
| Test status | |
| Simulation time | 7423073107 ps |
| CPU time | 77.56 seconds |
| Started | May 30 03:56:44 PM PDT 24 |
| Finished | May 30 03:58:02 PM PDT 24 |
| Peak memory | 563512 kb |
| Host | smart-763bb4d6-3e2f-49f4-a663-6f495c0bff17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397181536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_large_delays.2397181536 |
| Directory | /workspace/69.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.3371210138 |
| Short name | T2193 |
| Test name | |
| Test status | |
| Simulation time | 5869306644 ps |
| CPU time | 99.55 seconds |
| Started | May 30 03:56:55 PM PDT 24 |
| Finished | May 30 03:58:35 PM PDT 24 |
| Peak memory | 563536 kb |
| Host | smart-94ed4284-3c6b-4897-8336-7123e22c1493 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371210138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_slow_rsp.3371210138 |
| Directory | /workspace/69.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_zero_delays.848176890 |
| Short name | T1848 |
| Test name | |
| Test status | |
| Simulation time | 47855993 ps |
| CPU time | 6.55 seconds |
| Started | May 30 03:56:46 PM PDT 24 |
| Finished | May 30 03:56:54 PM PDT 24 |
| Peak memory | 564776 kb |
| Host | smart-2e70a8c4-cee7-42d7-be6c-33310ce2bce0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848176890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_zero_delays .848176890 |
| Directory | /workspace/69.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all.36127985 |
| Short name | T1983 |
| Test name | |
| Test status | |
| Simulation time | 2374804231 ps |
| CPU time | 183.88 seconds |
| Started | May 30 03:56:56 PM PDT 24 |
| Finished | May 30 04:00:00 PM PDT 24 |
| Peak memory | 573256 kb |
| Host | smart-e78d0dc2-70ab-49d0-baa3-f1181cff128c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36127985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all.36127985 |
| Directory | /workspace/69.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.2836638674 |
| Short name | T1778 |
| Test name | |
| Test status | |
| Simulation time | 1682140252 ps |
| CPU time | 121.1 seconds |
| Started | May 30 03:56:57 PM PDT 24 |
| Finished | May 30 03:58:59 PM PDT 24 |
| Peak memory | 573076 kb |
| Host | smart-f49762de-1ca8-4ce7-a7bb-e0c9c0c2d390 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836638674 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_error.2836638674 |
| Directory | /workspace/69.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.4185962042 |
| Short name | T2813 |
| Test name | |
| Test status | |
| Simulation time | 25060388 ps |
| CPU time | 22.04 seconds |
| Started | May 30 03:56:54 PM PDT 24 |
| Finished | May 30 03:57:17 PM PDT 24 |
| Peak memory | 564756 kb |
| Host | smart-6296e7ec-33d8-4f9a-b281-9ce839d45d16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185962042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_al l_with_reset_error.4185962042 |
| Directory | /workspace/69.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.1446384770 |
| Short name | T1359 |
| Test name | |
| Test status | |
| Simulation time | 58213022 ps |
| CPU time | 9.15 seconds |
| Started | May 30 03:56:59 PM PDT 24 |
| Finished | May 30 03:57:09 PM PDT 24 |
| Peak memory | 564876 kb |
| Host | smart-7b850dc2-2727-405e-9366-134ac9c1cff3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446384770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_unmapped_addr.1446384770 |
| Directory | /workspace/69.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.2163165419 |
| Short name | T2170 |
| Test name | |
| Test status | |
| Simulation time | 14821326986 ps |
| CPU time | 1542.92 seconds |
| Started | May 30 03:48:56 PM PDT 24 |
| Finished | May 30 04:14:40 PM PDT 24 |
| Peak memory | 587632 kb |
| Host | smart-ccf3178e-b303-4617-b5ac-186801a84f35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163165419 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 7.chip_same_csr_outstanding.2163165419 |
| Directory | /workspace/7.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_tl_errors.3586905671 |
| Short name | T2861 |
| Test name | |
| Test status | |
| Simulation time | 3438349520 ps |
| CPU time | 141.1 seconds |
| Started | May 30 03:48:52 PM PDT 24 |
| Finished | May 30 03:51:15 PM PDT 24 |
| Peak memory | 594020 kb |
| Host | smart-16870e8a-29d3-4c77-ae28-5629c79b3858 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586905671 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_tl_errors.3586905671 |
| Directory | /workspace/7.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device.1743479841 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 828389870 ps |
| CPU time | 63.73 seconds |
| Started | May 30 03:48:57 PM PDT 24 |
| Finished | May 30 03:50:03 PM PDT 24 |
| Peak memory | 573112 kb |
| Host | smart-f97fd5e0-9c32-4cb0-a2d0-f9cde0ae93a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743479841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device. 1743479841 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.781603137 |
| Short name | T2562 |
| Test name | |
| Test status | |
| Simulation time | 22760464527 ps |
| CPU time | 404 seconds |
| Started | May 30 03:48:56 PM PDT 24 |
| Finished | May 30 03:55:42 PM PDT 24 |
| Peak memory | 573260 kb |
| Host | smart-67fd5941-39ab-461b-bdc6-24a23a439c01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781603137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_de vice_slow_rsp.781603137 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.3117424748 |
| Short name | T1673 |
| Test name | |
| Test status | |
| Simulation time | 208902294 ps |
| CPU time | 24.35 seconds |
| Started | May 30 03:48:58 PM PDT 24 |
| Finished | May 30 03:49:24 PM PDT 24 |
| Peak memory | 572588 kb |
| Host | smart-1ff3cd0d-c3ae-461d-8f9e-654e9d79ac85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117424748 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr .3117424748 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_random.2891753035 |
| Short name | T1686 |
| Test name | |
| Test status | |
| Simulation time | 2762512409 ps |
| CPU time | 98.81 seconds |
| Started | May 30 03:48:59 PM PDT 24 |
| Finished | May 30 03:50:39 PM PDT 24 |
| Peak memory | 574012 kb |
| Host | smart-ad0d36cc-7947-4472-bf5b-cf5d54b24d09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891753035 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.2891753035 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random.570666552 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 1341905372 ps |
| CPU time | 48.99 seconds |
| Started | May 30 03:48:58 PM PDT 24 |
| Finished | May 30 03:49:49 PM PDT 24 |
| Peak memory | 572808 kb |
| Host | smart-55015ccc-d8f8-4c18-aa80-1e129123b199 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570666552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random.570666552 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_large_delays.1234931344 |
| Short name | T1533 |
| Test name | |
| Test status | |
| Simulation time | 5342704272 ps |
| CPU time | 59.23 seconds |
| Started | May 30 03:48:55 PM PDT 24 |
| Finished | May 30 03:49:56 PM PDT 24 |
| Peak memory | 564992 kb |
| Host | smart-e985ebe7-9c5e-4905-a963-97406cb73fd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234931344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.1234931344 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.1676383778 |
| Short name | T2786 |
| Test name | |
| Test status | |
| Simulation time | 44091543316 ps |
| CPU time | 645.04 seconds |
| Started | May 30 03:48:52 PM PDT 24 |
| Finished | May 30 03:59:39 PM PDT 24 |
| Peak memory | 573168 kb |
| Host | smart-93c5fadd-3bc2-497f-b585-ab1d5c1a6d1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676383778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.1676383778 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_zero_delays.1350174112 |
| Short name | T2661 |
| Test name | |
| Test status | |
| Simulation time | 45723574 ps |
| CPU time | 6.13 seconds |
| Started | May 30 03:48:54 PM PDT 24 |
| Finished | May 30 03:49:01 PM PDT 24 |
| Peak memory | 564876 kb |
| Host | smart-b4fa5b57-3df6-40e1-b17d-16830024535a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350174112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_dela ys.1350174112 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_same_source.2330373152 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 1136872673 ps |
| CPU time | 34.61 seconds |
| Started | May 30 03:48:56 PM PDT 24 |
| Finished | May 30 03:49:33 PM PDT 24 |
| Peak memory | 573032 kb |
| Host | smart-5e835e1e-6667-48bd-a9ff-2303ab73b6b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330373152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.2330373152 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke.110152016 |
| Short name | T1961 |
| Test name | |
| Test status | |
| Simulation time | 187923017 ps |
| CPU time | 8.16 seconds |
| Started | May 30 03:48:51 PM PDT 24 |
| Finished | May 30 03:49:02 PM PDT 24 |
| Peak memory | 564840 kb |
| Host | smart-cf0b55de-61ee-4dad-9db8-150e009192e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110152016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.110152016 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_large_delays.2887788335 |
| Short name | T2005 |
| Test name | |
| Test status | |
| Simulation time | 8320488297 ps |
| CPU time | 93.17 seconds |
| Started | May 30 03:48:50 PM PDT 24 |
| Finished | May 30 03:50:25 PM PDT 24 |
| Peak memory | 564900 kb |
| Host | smart-e97f75f6-3f97-4757-83b3-dda80cb79770 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887788335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.2887788335 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.759695847 |
| Short name | T2217 |
| Test name | |
| Test status | |
| Simulation time | 3118528895 ps |
| CPU time | 51.23 seconds |
| Started | May 30 03:48:55 PM PDT 24 |
| Finished | May 30 03:49:48 PM PDT 24 |
| Peak memory | 564848 kb |
| Host | smart-db104012-9d3c-42e0-8f88-624b88e072f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759695847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.759695847 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_zero_delays.2428022504 |
| Short name | T2690 |
| Test name | |
| Test status | |
| Simulation time | 39027274 ps |
| CPU time | 5.97 seconds |
| Started | May 30 03:48:59 PM PDT 24 |
| Finished | May 30 03:49:07 PM PDT 24 |
| Peak memory | 564792 kb |
| Host | smart-cea2745d-5f4f-4e5c-8ecd-4b92c0088224 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428022504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays .2428022504 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all.1363401633 |
| Short name | T1688 |
| Test name | |
| Test status | |
| Simulation time | 1465122621 ps |
| CPU time | 124.24 seconds |
| Started | May 30 03:48:52 PM PDT 24 |
| Finished | May 30 03:50:58 PM PDT 24 |
| Peak memory | 573200 kb |
| Host | smart-f1330cb6-bb0e-49a1-8a19-c37a30499da8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363401633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.1363401633 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.1674007097 |
| Short name | T1941 |
| Test name | |
| Test status | |
| Simulation time | 1445052824 ps |
| CPU time | 125.37 seconds |
| Started | May 30 03:48:55 PM PDT 24 |
| Finished | May 30 03:51:02 PM PDT 24 |
| Peak memory | 573084 kb |
| Host | smart-2c28d98a-8fc0-4408-aa06-a57e6358a3f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674007097 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.1674007097 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.4053310343 |
| Short name | T2464 |
| Test name | |
| Test status | |
| Simulation time | 3647965500 ps |
| CPU time | 445.2 seconds |
| Started | May 30 03:48:50 PM PDT 24 |
| Finished | May 30 03:56:18 PM PDT 24 |
| Peak memory | 579304 kb |
| Host | smart-d71eb5ef-19a5-4bd8-92d6-9ff7fd0f5e07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053310343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_ with_rand_reset.4053310343 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.3342390711 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 299628479 ps |
| CPU time | 169.4 seconds |
| Started | May 30 03:48:56 PM PDT 24 |
| Finished | May 30 03:51:48 PM PDT 24 |
| Peak memory | 573096 kb |
| Host | smart-e6dd65b8-f805-4c52-9363-1b832d58d60d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342390711 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all _with_reset_error.3342390711 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_unmapped_addr.652333863 |
| Short name | T2433 |
| Test name | |
| Test status | |
| Simulation time | 452881129 ps |
| CPU time | 20.9 seconds |
| Started | May 30 03:48:56 PM PDT 24 |
| Finished | May 30 03:49:19 PM PDT 24 |
| Peak memory | 573016 kb |
| Host | smart-8dff7140-4293-4c86-9c5b-478b7a7e834d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652333863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.652333863 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.2061304293 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 10813003186 ps |
| CPU time | 180.02 seconds |
| Started | May 30 03:57:06 PM PDT 24 |
| Finished | May 30 04:00:07 PM PDT 24 |
| Peak memory | 565008 kb |
| Host | smart-3a2ec669-f1ef-424a-93c9-4ddf117db2af |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061304293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_ device_slow_rsp.2061304293 |
| Directory | /workspace/70.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.78856920 |
| Short name | T1801 |
| Test name | |
| Test status | |
| Simulation time | 1267736700 ps |
| CPU time | 55.36 seconds |
| Started | May 30 03:57:06 PM PDT 24 |
| Finished | May 30 03:58:03 PM PDT 24 |
| Peak memory | 572876 kb |
| Host | smart-36d94252-4a9e-4340-a46e-da7ba3e0258c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78856920 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_and_unmapped_addr.78856920 |
| Directory | /workspace/70.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_random.327201349 |
| Short name | T2473 |
| Test name | |
| Test status | |
| Simulation time | 1377984606 ps |
| CPU time | 45.66 seconds |
| Started | May 30 03:57:08 PM PDT 24 |
| Finished | May 30 03:57:55 PM PDT 24 |
| Peak memory | 572904 kb |
| Host | smart-7c3dec45-39cb-4725-9a83-b1a5a09f31a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327201349 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_random.327201349 |
| Directory | /workspace/70.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random.847693078 |
| Short name | T2478 |
| Test name | |
| Test status | |
| Simulation time | 343955109 ps |
| CPU time | 16.5 seconds |
| Started | May 30 03:57:05 PM PDT 24 |
| Finished | May 30 03:57:22 PM PDT 24 |
| Peak memory | 572936 kb |
| Host | smart-44b22910-6748-47b9-9f27-a1da238e625f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847693078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random.847693078 |
| Directory | /workspace/70.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_large_delays.3703535341 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 31395956473 ps |
| CPU time | 316.02 seconds |
| Started | May 30 03:57:06 PM PDT 24 |
| Finished | May 30 04:02:23 PM PDT 24 |
| Peak memory | 573220 kb |
| Host | smart-a9722359-cfe2-4746-aedc-e692cb0baf4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703535341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_large_delays.3703535341 |
| Directory | /workspace/70.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_slow_rsp.4281901890 |
| Short name | T1723 |
| Test name | |
| Test status | |
| Simulation time | 49519903470 ps |
| CPU time | 929.4 seconds |
| Started | May 30 03:57:08 PM PDT 24 |
| Finished | May 30 04:12:39 PM PDT 24 |
| Peak memory | 572804 kb |
| Host | smart-4a2bf119-3710-468a-b0c0-e746efb5432b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281901890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_slow_rsp.4281901890 |
| Directory | /workspace/70.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.2717874290 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 557007334 ps |
| CPU time | 40.73 seconds |
| Started | May 30 03:57:10 PM PDT 24 |
| Finished | May 30 03:57:51 PM PDT 24 |
| Peak memory | 573052 kb |
| Host | smart-812a1df8-1168-44c7-b745-0814233213fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717874290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_zero_del ays.2717874290 |
| Directory | /workspace/70.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_same_source.1522610468 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 2554088803 ps |
| CPU time | 77.58 seconds |
| Started | May 30 03:57:06 PM PDT 24 |
| Finished | May 30 03:58:24 PM PDT 24 |
| Peak memory | 573052 kb |
| Host | smart-a81b6b5a-47a9-405a-aa4e-edb0484af96e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522610468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_same_source.1522610468 |
| Directory | /workspace/70.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke.1402323236 |
| Short name | T2103 |
| Test name | |
| Test status | |
| Simulation time | 212999513 ps |
| CPU time | 9.3 seconds |
| Started | May 30 03:57:12 PM PDT 24 |
| Finished | May 30 03:57:22 PM PDT 24 |
| Peak memory | 564852 kb |
| Host | smart-60057b3e-a0f5-41c9-bd9f-7fe5035b52c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402323236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke.1402323236 |
| Directory | /workspace/70.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_large_delays.2857763225 |
| Short name | T1776 |
| Test name | |
| Test status | |
| Simulation time | 8505408914 ps |
| CPU time | 88.37 seconds |
| Started | May 30 03:57:08 PM PDT 24 |
| Finished | May 30 03:58:37 PM PDT 24 |
| Peak memory | 564960 kb |
| Host | smart-3e0de86c-6d89-47bd-9ee5-7cc57b997dd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857763225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_large_delays.2857763225 |
| Directory | /workspace/70.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.373473718 |
| Short name | T1851 |
| Test name | |
| Test status | |
| Simulation time | 5339018822 ps |
| CPU time | 89.05 seconds |
| Started | May 30 03:57:05 PM PDT 24 |
| Finished | May 30 03:58:35 PM PDT 24 |
| Peak memory | 563540 kb |
| Host | smart-8b1a3a9e-473f-4cdd-a6d3-b16c168f1cba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373473718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_slow_rsp.373473718 |
| Directory | /workspace/70.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_zero_delays.4235846734 |
| Short name | T1398 |
| Test name | |
| Test status | |
| Simulation time | 54287297 ps |
| CPU time | 6.77 seconds |
| Started | May 30 03:57:06 PM PDT 24 |
| Finished | May 30 03:57:13 PM PDT 24 |
| Peak memory | 564772 kb |
| Host | smart-327b9c94-2550-4ef3-b451-2d8656701d75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235846734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_zero_delay s.4235846734 |
| Directory | /workspace/70.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all.90358794 |
| Short name | T1552 |
| Test name | |
| Test status | |
| Simulation time | 13364066143 ps |
| CPU time | 500.37 seconds |
| Started | May 30 03:57:14 PM PDT 24 |
| Finished | May 30 04:05:36 PM PDT 24 |
| Peak memory | 573248 kb |
| Host | smart-3b977b5e-d145-45a4-847e-36cfb63ffada |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90358794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all.90358794 |
| Directory | /workspace/70.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.4287677637 |
| Short name | T1725 |
| Test name | |
| Test status | |
| Simulation time | 355267010 ps |
| CPU time | 25.06 seconds |
| Started | May 30 03:57:16 PM PDT 24 |
| Finished | May 30 03:57:42 PM PDT 24 |
| Peak memory | 572928 kb |
| Host | smart-3f47a73f-87cb-43f6-a222-03d1f51f4259 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287677637 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_error.4287677637 |
| Directory | /workspace/70.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.3447757688 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 254820181 ps |
| CPU time | 59.42 seconds |
| Started | May 30 03:57:24 PM PDT 24 |
| Finished | May 30 03:58:24 PM PDT 24 |
| Peak memory | 573096 kb |
| Host | smart-303c1b97-5f5a-4699-a914-ae58c450da70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447757688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all _with_rand_reset.3447757688 |
| Directory | /workspace/70.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.4228558366 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 1792925161 ps |
| CPU time | 275.14 seconds |
| Started | May 30 03:57:19 PM PDT 24 |
| Finished | May 30 04:01:55 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-dfc8453e-4900-4859-aeac-978af47387a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228558366 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_al l_with_reset_error.4228558366 |
| Directory | /workspace/70.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.3966522959 |
| Short name | T1676 |
| Test name | |
| Test status | |
| Simulation time | 227666372 ps |
| CPU time | 12.95 seconds |
| Started | May 30 03:57:06 PM PDT 24 |
| Finished | May 30 03:57:20 PM PDT 24 |
| Peak memory | 564848 kb |
| Host | smart-fc7adc70-771b-456f-9b33-504f22b959b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966522959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_unmapped_addr.3966522959 |
| Directory | /workspace/70.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device.2110186696 |
| Short name | T1615 |
| Test name | |
| Test status | |
| Simulation time | 2559276680 ps |
| CPU time | 100.3 seconds |
| Started | May 30 03:57:18 PM PDT 24 |
| Finished | May 30 03:58:59 PM PDT 24 |
| Peak memory | 573140 kb |
| Host | smart-12e43924-f830-4c37-86bf-4e29e30b248e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110186696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device .2110186696 |
| Directory | /workspace/71.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.1613629017 |
| Short name | T2699 |
| Test name | |
| Test status | |
| Simulation time | 81227222159 ps |
| CPU time | 1495.18 seconds |
| Started | May 30 03:57:16 PM PDT 24 |
| Finished | May 30 04:22:12 PM PDT 24 |
| Peak memory | 573212 kb |
| Host | smart-4eb10eed-a426-4176-b745-ae083f2d8a82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613629017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_ device_slow_rsp.1613629017 |
| Directory | /workspace/71.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.3515493659 |
| Short name | T1320 |
| Test name | |
| Test status | |
| Simulation time | 102348583 ps |
| CPU time | 12.04 seconds |
| Started | May 30 03:57:19 PM PDT 24 |
| Finished | May 30 03:57:31 PM PDT 24 |
| Peak memory | 572944 kb |
| Host | smart-113a2ea0-d592-4d47-8142-ee444b5f3254 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515493659 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_and_unmapped_add r.3515493659 |
| Directory | /workspace/71.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_random.2332728304 |
| Short name | T1678 |
| Test name | |
| Test status | |
| Simulation time | 337656586 ps |
| CPU time | 30.66 seconds |
| Started | May 30 03:57:15 PM PDT 24 |
| Finished | May 30 03:57:47 PM PDT 24 |
| Peak memory | 572940 kb |
| Host | smart-11f769d4-291f-4447-926a-d11a94a46935 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332728304 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_random.2332728304 |
| Directory | /workspace/71.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random.3337773770 |
| Short name | T2129 |
| Test name | |
| Test status | |
| Simulation time | 94977735 ps |
| CPU time | 10.93 seconds |
| Started | May 30 03:57:15 PM PDT 24 |
| Finished | May 30 03:57:27 PM PDT 24 |
| Peak memory | 573068 kb |
| Host | smart-9dd41694-799b-470c-b6b6-652d6ea9fb20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337773770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random.3337773770 |
| Directory | /workspace/71.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_large_delays.2164633295 |
| Short name | T1590 |
| Test name | |
| Test status | |
| Simulation time | 62553909392 ps |
| CPU time | 760.31 seconds |
| Started | May 30 03:57:19 PM PDT 24 |
| Finished | May 30 04:10:01 PM PDT 24 |
| Peak memory | 573204 kb |
| Host | smart-ab1ae07a-c8c6-44ca-978c-16ed241ded4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164633295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_large_delays.2164633295 |
| Directory | /workspace/71.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_slow_rsp.1639442485 |
| Short name | T1808 |
| Test name | |
| Test status | |
| Simulation time | 45957971306 ps |
| CPU time | 860.49 seconds |
| Started | May 30 03:57:15 PM PDT 24 |
| Finished | May 30 04:11:37 PM PDT 24 |
| Peak memory | 573220 kb |
| Host | smart-c3af625b-0e9f-4161-a71e-901bc429b777 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639442485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_slow_rsp.1639442485 |
| Directory | /workspace/71.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.3037724306 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 447730303 ps |
| CPU time | 39.82 seconds |
| Started | May 30 03:57:18 PM PDT 24 |
| Finished | May 30 03:57:58 PM PDT 24 |
| Peak memory | 572964 kb |
| Host | smart-665281bf-dc56-4329-a7c4-74dc182ee825 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037724306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_zero_del ays.3037724306 |
| Directory | /workspace/71.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_same_source.2794583567 |
| Short name | T1467 |
| Test name | |
| Test status | |
| Simulation time | 356567543 ps |
| CPU time | 13.09 seconds |
| Started | May 30 03:57:16 PM PDT 24 |
| Finished | May 30 03:57:30 PM PDT 24 |
| Peak memory | 572996 kb |
| Host | smart-96cb4c0f-b0e0-4129-849c-9d3ada95c94e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794583567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_same_source.2794583567 |
| Directory | /workspace/71.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke.257594961 |
| Short name | T2455 |
| Test name | |
| Test status | |
| Simulation time | 149655124 ps |
| CPU time | 7.76 seconds |
| Started | May 30 03:57:17 PM PDT 24 |
| Finished | May 30 03:57:26 PM PDT 24 |
| Peak memory | 564828 kb |
| Host | smart-98b241a5-7815-4fd1-bd59-1f95378dd9b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257594961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke.257594961 |
| Directory | /workspace/71.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_large_delays.2145372293 |
| Short name | T2102 |
| Test name | |
| Test status | |
| Simulation time | 8305600258 ps |
| CPU time | 92.73 seconds |
| Started | May 30 03:57:16 PM PDT 24 |
| Finished | May 30 03:58:50 PM PDT 24 |
| Peak memory | 564960 kb |
| Host | smart-ce377c76-7917-4257-81fe-aa440b16ea7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145372293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_large_delays.2145372293 |
| Directory | /workspace/71.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.2329134286 |
| Short name | T1349 |
| Test name | |
| Test status | |
| Simulation time | 5097763420 ps |
| CPU time | 90.46 seconds |
| Started | May 30 03:57:16 PM PDT 24 |
| Finished | May 30 03:58:47 PM PDT 24 |
| Peak memory | 563512 kb |
| Host | smart-11e9ef69-d8c5-4653-bf5d-33e9aa883564 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329134286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_slow_rsp.2329134286 |
| Directory | /workspace/71.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_zero_delays.1549052789 |
| Short name | T2260 |
| Test name | |
| Test status | |
| Simulation time | 43534112 ps |
| CPU time | 6.11 seconds |
| Started | May 30 03:57:16 PM PDT 24 |
| Finished | May 30 03:57:23 PM PDT 24 |
| Peak memory | 563408 kb |
| Host | smart-ff6213a7-528d-4e0a-810d-68175b67e202 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549052789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_zero_delay s.1549052789 |
| Directory | /workspace/71.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all.485550832 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 66884400 ps |
| CPU time | 7.2 seconds |
| Started | May 30 03:57:18 PM PDT 24 |
| Finished | May 30 03:57:26 PM PDT 24 |
| Peak memory | 564856 kb |
| Host | smart-78140dad-258a-4140-98f4-40ad657eab9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485550832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all.485550832 |
| Directory | /workspace/71.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.971079743 |
| Short name | T2665 |
| Test name | |
| Test status | |
| Simulation time | 4089978709 ps |
| CPU time | 376.08 seconds |
| Started | May 30 03:57:21 PM PDT 24 |
| Finished | May 30 04:03:38 PM PDT 24 |
| Peak memory | 573176 kb |
| Host | smart-6c43f762-37b2-48a0-b3b9-0cf3e1f12da6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971079743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_ with_rand_reset.971079743 |
| Directory | /workspace/71.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.2026868657 |
| Short name | T2364 |
| Test name | |
| Test status | |
| Simulation time | 3391630107 ps |
| CPU time | 380.32 seconds |
| Started | May 30 03:57:19 PM PDT 24 |
| Finished | May 30 04:03:40 PM PDT 24 |
| Peak memory | 580764 kb |
| Host | smart-5e212382-dafc-43b9-9ca0-06727a34bb15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026868657 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_al l_with_reset_error.2026868657 |
| Directory | /workspace/71.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_unmapped_addr.1370726825 |
| Short name | T2617 |
| Test name | |
| Test status | |
| Simulation time | 37398631 ps |
| CPU time | 7.17 seconds |
| Started | May 30 03:57:21 PM PDT 24 |
| Finished | May 30 03:57:29 PM PDT 24 |
| Peak memory | 564916 kb |
| Host | smart-e5fea959-5ed5-4c22-ae61-0e1edc626d5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370726825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_unmapped_addr.1370726825 |
| Directory | /workspace/71.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device.3319376095 |
| Short name | T2325 |
| Test name | |
| Test status | |
| Simulation time | 1617580550 ps |
| CPU time | 65.05 seconds |
| Started | May 30 03:57:30 PM PDT 24 |
| Finished | May 30 03:58:36 PM PDT 24 |
| Peak memory | 573056 kb |
| Host | smart-0a09ed8e-5c39-4579-8e81-97467ad9c478 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319376095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device .3319376095 |
| Directory | /workspace/72.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.3866827120 |
| Short name | T2065 |
| Test name | |
| Test status | |
| Simulation time | 21115930586 ps |
| CPU time | 361.44 seconds |
| Started | May 30 03:57:37 PM PDT 24 |
| Finished | May 30 04:03:39 PM PDT 24 |
| Peak memory | 573240 kb |
| Host | smart-f59f0e02-ff26-4d95-ae4c-e928e5fa9287 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866827120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_ device_slow_rsp.3866827120 |
| Directory | /workspace/72.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.2711741148 |
| Short name | T2051 |
| Test name | |
| Test status | |
| Simulation time | 27845923 ps |
| CPU time | 5.38 seconds |
| Started | May 30 03:57:30 PM PDT 24 |
| Finished | May 30 03:57:36 PM PDT 24 |
| Peak memory | 564716 kb |
| Host | smart-1860735f-5acc-4866-adc6-46219f57ea82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711741148 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_and_unmapped_add r.2711741148 |
| Directory | /workspace/72.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_random.3658006318 |
| Short name | T1450 |
| Test name | |
| Test status | |
| Simulation time | 143706194 ps |
| CPU time | 8.38 seconds |
| Started | May 30 03:57:27 PM PDT 24 |
| Finished | May 30 03:57:36 PM PDT 24 |
| Peak memory | 564472 kb |
| Host | smart-05119882-59af-4a47-83b1-9b635cafc902 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658006318 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_random.3658006318 |
| Directory | /workspace/72.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random.3941586926 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 560317822 ps |
| CPU time | 44.84 seconds |
| Started | May 30 03:57:29 PM PDT 24 |
| Finished | May 30 03:58:14 PM PDT 24 |
| Peak memory | 573060 kb |
| Host | smart-f9016321-6c8b-4d6c-88ba-5698dc7386c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941586926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random.3941586926 |
| Directory | /workspace/72.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_large_delays.119640445 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 77333603862 ps |
| CPU time | 840.84 seconds |
| Started | May 30 03:57:27 PM PDT 24 |
| Finished | May 30 04:11:28 PM PDT 24 |
| Peak memory | 573084 kb |
| Host | smart-96daaa9e-2c05-492a-8275-c6070ce8aca6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119640445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_large_delays.119640445 |
| Directory | /workspace/72.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_slow_rsp.2158887656 |
| Short name | T2452 |
| Test name | |
| Test status | |
| Simulation time | 4434899465 ps |
| CPU time | 73.53 seconds |
| Started | May 30 03:57:29 PM PDT 24 |
| Finished | May 30 03:58:43 PM PDT 24 |
| Peak memory | 564992 kb |
| Host | smart-735e0176-b0dc-487a-a7db-ba4f3cddad90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158887656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_slow_rsp.2158887656 |
| Directory | /workspace/72.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.1184395634 |
| Short name | T2150 |
| Test name | |
| Test status | |
| Simulation time | 357336830 ps |
| CPU time | 27.21 seconds |
| Started | May 30 03:57:28 PM PDT 24 |
| Finished | May 30 03:57:56 PM PDT 24 |
| Peak memory | 573024 kb |
| Host | smart-3a16479f-c5f1-4a97-9dd6-fa8a8d725c2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184395634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_zero_del ays.1184395634 |
| Directory | /workspace/72.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_same_source.3247095000 |
| Short name | T2336 |
| Test name | |
| Test status | |
| Simulation time | 2591551397 ps |
| CPU time | 86.93 seconds |
| Started | May 30 03:57:28 PM PDT 24 |
| Finished | May 30 03:58:55 PM PDT 24 |
| Peak memory | 573056 kb |
| Host | smart-0468d74b-ef2b-4a2d-a743-48f6555629b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247095000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_same_source.3247095000 |
| Directory | /workspace/72.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke.170068117 |
| Short name | T1958 |
| Test name | |
| Test status | |
| Simulation time | 162387761 ps |
| CPU time | 8.05 seconds |
| Started | May 30 03:57:18 PM PDT 24 |
| Finished | May 30 03:57:27 PM PDT 24 |
| Peak memory | 564836 kb |
| Host | smart-05ca421b-d395-4c45-aaaf-e0994dc6d271 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170068117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke.170068117 |
| Directory | /workspace/72.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.3762625298 |
| Short name | T2446 |
| Test name | |
| Test status | |
| Simulation time | 4583603271 ps |
| CPU time | 47.46 seconds |
| Started | May 30 03:57:30 PM PDT 24 |
| Finished | May 30 03:58:18 PM PDT 24 |
| Peak memory | 564904 kb |
| Host | smart-f84cf211-75b5-469f-acd8-3947eb8da750 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762625298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_large_delays.3762625298 |
| Directory | /workspace/72.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.86304652 |
| Short name | T2745 |
| Test name | |
| Test status | |
| Simulation time | 4337773087 ps |
| CPU time | 76.59 seconds |
| Started | May 30 03:57:29 PM PDT 24 |
| Finished | May 30 03:58:47 PM PDT 24 |
| Peak memory | 564936 kb |
| Host | smart-239a4e1c-6eb6-4381-861c-4b2efd501106 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86304652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_slow_rsp.86304652 |
| Directory | /workspace/72.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_zero_delays.3343571929 |
| Short name | T2529 |
| Test name | |
| Test status | |
| Simulation time | 46949184 ps |
| CPU time | 6.15 seconds |
| Started | May 30 03:57:20 PM PDT 24 |
| Finished | May 30 03:57:27 PM PDT 24 |
| Peak memory | 563304 kb |
| Host | smart-a3cee97f-d4ed-4269-b0d4-40d56b041b6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343571929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_zero_delay s.3343571929 |
| Directory | /workspace/72.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all.2460780102 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 1145333827 ps |
| CPU time | 79.92 seconds |
| Started | May 30 03:57:26 PM PDT 24 |
| Finished | May 30 03:58:47 PM PDT 24 |
| Peak memory | 573152 kb |
| Host | smart-bf378fcd-da43-4579-9ec9-ad16d8cccc1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460780102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all.2460780102 |
| Directory | /workspace/72.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_error.124069384 |
| Short name | T1852 |
| Test name | |
| Test status | |
| Simulation time | 4143152094 ps |
| CPU time | 131.65 seconds |
| Started | May 30 03:57:28 PM PDT 24 |
| Finished | May 30 03:59:41 PM PDT 24 |
| Peak memory | 573016 kb |
| Host | smart-fe9740c4-c13f-417b-8367-2f1d2add5c3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124069384 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_error.124069384 |
| Directory | /workspace/72.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.2585456498 |
| Short name | T2803 |
| Test name | |
| Test status | |
| Simulation time | 1225938721 ps |
| CPU time | 174.23 seconds |
| Started | May 30 03:57:29 PM PDT 24 |
| Finished | May 30 04:00:24 PM PDT 24 |
| Peak memory | 573140 kb |
| Host | smart-6f9dd328-6747-4b13-a0cc-4ca581312d58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585456498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all _with_rand_reset.2585456498 |
| Directory | /workspace/72.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.2838913072 |
| Short name | T2747 |
| Test name | |
| Test status | |
| Simulation time | 5377107803 ps |
| CPU time | 314.45 seconds |
| Started | May 30 03:57:34 PM PDT 24 |
| Finished | May 30 04:02:49 PM PDT 24 |
| Peak memory | 573212 kb |
| Host | smart-25cf3c37-272f-4c35-8819-47f47647cbfd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838913072 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_al l_with_reset_error.2838913072 |
| Directory | /workspace/72.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_unmapped_addr.2029947172 |
| Short name | T2061 |
| Test name | |
| Test status | |
| Simulation time | 1097541442 ps |
| CPU time | 44.25 seconds |
| Started | May 30 03:57:29 PM PDT 24 |
| Finished | May 30 03:58:14 PM PDT 24 |
| Peak memory | 573096 kb |
| Host | smart-0f147913-138b-4327-a8a2-54c3da478c11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029947172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_unmapped_addr.2029947172 |
| Directory | /workspace/72.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device.1757291020 |
| Short name | T1473 |
| Test name | |
| Test status | |
| Simulation time | 824059200 ps |
| CPU time | 64.48 seconds |
| Started | May 30 03:57:46 PM PDT 24 |
| Finished | May 30 03:58:51 PM PDT 24 |
| Peak memory | 573040 kb |
| Host | smart-0991cee7-ae51-485f-9047-c9ed41f633e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757291020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device .1757291020 |
| Directory | /workspace/73.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.4134921359 |
| Short name | T2531 |
| Test name | |
| Test status | |
| Simulation time | 47306832969 ps |
| CPU time | 896.46 seconds |
| Started | May 30 03:57:38 PM PDT 24 |
| Finished | May 30 04:12:35 PM PDT 24 |
| Peak memory | 573264 kb |
| Host | smart-c50fcfee-d674-443e-95e1-665631e3ad74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134921359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_ device_slow_rsp.4134921359 |
| Directory | /workspace/73.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.2521320896 |
| Short name | T2607 |
| Test name | |
| Test status | |
| Simulation time | 518436043 ps |
| CPU time | 24.08 seconds |
| Started | May 30 03:57:43 PM PDT 24 |
| Finished | May 30 03:58:09 PM PDT 24 |
| Peak memory | 572928 kb |
| Host | smart-aba2b991-759b-4110-aef4-31c4d42120e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521320896 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_and_unmapped_add r.2521320896 |
| Directory | /workspace/73.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_random.1672640827 |
| Short name | T1636 |
| Test name | |
| Test status | |
| Simulation time | 1824459592 ps |
| CPU time | 61.87 seconds |
| Started | May 30 03:57:40 PM PDT 24 |
| Finished | May 30 03:58:43 PM PDT 24 |
| Peak memory | 572948 kb |
| Host | smart-93176241-fbbd-4d90-a062-2b955777a421 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672640827 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_random.1672640827 |
| Directory | /workspace/73.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random.2945100422 |
| Short name | T1466 |
| Test name | |
| Test status | |
| Simulation time | 931390829 ps |
| CPU time | 37.54 seconds |
| Started | May 30 03:57:28 PM PDT 24 |
| Finished | May 30 03:58:06 PM PDT 24 |
| Peak memory | 572948 kb |
| Host | smart-172bc70f-7cd9-4a70-a18c-b460f4c49ed2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945100422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random.2945100422 |
| Directory | /workspace/73.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_large_delays.1654224241 |
| Short name | T1341 |
| Test name | |
| Test status | |
| Simulation time | 11155118934 ps |
| CPU time | 120.24 seconds |
| Started | May 30 03:57:38 PM PDT 24 |
| Finished | May 30 03:59:39 PM PDT 24 |
| Peak memory | 564900 kb |
| Host | smart-fab668a5-f991-40ff-8e30-373611eccb96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654224241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_large_delays.1654224241 |
| Directory | /workspace/73.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_slow_rsp.2567249472 |
| Short name | T2731 |
| Test name | |
| Test status | |
| Simulation time | 3858881319 ps |
| CPU time | 68.84 seconds |
| Started | May 30 03:57:38 PM PDT 24 |
| Finished | May 30 03:58:48 PM PDT 24 |
| Peak memory | 564864 kb |
| Host | smart-6e869142-15a6-4874-83c5-79080b7d0fb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567249472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_slow_rsp.2567249472 |
| Directory | /workspace/73.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_zero_delays.3875515206 |
| Short name | T2447 |
| Test name | |
| Test status | |
| Simulation time | 325891455 ps |
| CPU time | 28.45 seconds |
| Started | May 30 03:57:29 PM PDT 24 |
| Finished | May 30 03:57:58 PM PDT 24 |
| Peak memory | 572900 kb |
| Host | smart-538d09b4-ccc3-4689-9a4f-44a2ecce4647 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875515206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_zero_del ays.3875515206 |
| Directory | /workspace/73.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_same_source.2511715252 |
| Short name | T2581 |
| Test name | |
| Test status | |
| Simulation time | 2370637182 ps |
| CPU time | 72.41 seconds |
| Started | May 30 03:57:46 PM PDT 24 |
| Finished | May 30 03:58:59 PM PDT 24 |
| Peak memory | 573100 kb |
| Host | smart-fb31c5d6-d7cf-4632-8c41-964053bb5a5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511715252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_same_source.2511715252 |
| Directory | /workspace/73.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke.3129440659 |
| Short name | T2832 |
| Test name | |
| Test status | |
| Simulation time | 44295401 ps |
| CPU time | 6.26 seconds |
| Started | May 30 03:57:29 PM PDT 24 |
| Finished | May 30 03:57:36 PM PDT 24 |
| Peak memory | 564828 kb |
| Host | smart-9adddc03-2c4e-41df-a4d2-05a4cdf03272 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129440659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke.3129440659 |
| Directory | /workspace/73.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.2454931504 |
| Short name | T2242 |
| Test name | |
| Test status | |
| Simulation time | 9559555842 ps |
| CPU time | 101.2 seconds |
| Started | May 30 03:57:29 PM PDT 24 |
| Finished | May 30 03:59:11 PM PDT 24 |
| Peak memory | 564952 kb |
| Host | smart-d6aa3ce3-e155-4693-a03b-fce17f91e393 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454931504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_large_delays.2454931504 |
| Directory | /workspace/73.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.416977800 |
| Short name | T1396 |
| Test name | |
| Test status | |
| Simulation time | 4630687121 ps |
| CPU time | 79.6 seconds |
| Started | May 30 03:57:29 PM PDT 24 |
| Finished | May 30 03:58:49 PM PDT 24 |
| Peak memory | 563512 kb |
| Host | smart-76ae5c8d-40c1-4fd4-a68f-d169ff8a25da |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416977800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_slow_rsp.416977800 |
| Directory | /workspace/73.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_zero_delays.1467005710 |
| Short name | T2662 |
| Test name | |
| Test status | |
| Simulation time | 45622854 ps |
| CPU time | 6.42 seconds |
| Started | May 30 03:57:31 PM PDT 24 |
| Finished | May 30 03:57:38 PM PDT 24 |
| Peak memory | 564812 kb |
| Host | smart-9e4ab841-c11a-4151-b48c-ede144edc9b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467005710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_zero_delay s.1467005710 |
| Directory | /workspace/73.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all.862476113 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 1350993659 ps |
| CPU time | 132.38 seconds |
| Started | May 30 03:57:42 PM PDT 24 |
| Finished | May 30 03:59:55 PM PDT 24 |
| Peak memory | 573164 kb |
| Host | smart-56190a40-9b7d-4576-b032-14103322dcf1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862476113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all.862476113 |
| Directory | /workspace/73.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.317994226 |
| Short name | T1727 |
| Test name | |
| Test status | |
| Simulation time | 7682873933 ps |
| CPU time | 235.97 seconds |
| Started | May 30 03:57:43 PM PDT 24 |
| Finished | May 30 04:01:40 PM PDT 24 |
| Peak memory | 573164 kb |
| Host | smart-eaeab57b-9361-437b-938f-652cfeed32b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317994226 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_error.317994226 |
| Directory | /workspace/73.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.470484121 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 400776115 ps |
| CPU time | 114.55 seconds |
| Started | May 30 03:57:46 PM PDT 24 |
| Finished | May 30 03:59:41 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-1f2580e9-d84a-4c86-8138-86cd66df9e10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470484121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_ with_rand_reset.470484121 |
| Directory | /workspace/73.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_unmapped_addr.3484326479 |
| Short name | T2784 |
| Test name | |
| Test status | |
| Simulation time | 536178600 ps |
| CPU time | 24.35 seconds |
| Started | May 30 03:57:40 PM PDT 24 |
| Finished | May 30 03:58:06 PM PDT 24 |
| Peak memory | 573060 kb |
| Host | smart-5d7f8884-0aed-483b-9e8b-30f2fd16ee10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484326479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_unmapped_addr.3484326479 |
| Directory | /workspace/73.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device.1792341834 |
| Short name | T2027 |
| Test name | |
| Test status | |
| Simulation time | 737522305 ps |
| CPU time | 60.76 seconds |
| Started | May 30 03:57:39 PM PDT 24 |
| Finished | May 30 03:58:41 PM PDT 24 |
| Peak memory | 573068 kb |
| Host | smart-17221837-06e9-4b74-a746-69f01f0756d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792341834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device .1792341834 |
| Directory | /workspace/74.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.2187379587 |
| Short name | T2314 |
| Test name | |
| Test status | |
| Simulation time | 61994895544 ps |
| CPU time | 1237.44 seconds |
| Started | May 30 03:57:54 PM PDT 24 |
| Finished | May 30 04:18:32 PM PDT 24 |
| Peak memory | 573192 kb |
| Host | smart-4810befd-3e2c-48e4-abc2-5701b28bb0a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187379587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_ device_slow_rsp.2187379587 |
| Directory | /workspace/74.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.2027810566 |
| Short name | T1390 |
| Test name | |
| Test status | |
| Simulation time | 475655116 ps |
| CPU time | 20.1 seconds |
| Started | May 30 03:57:49 PM PDT 24 |
| Finished | May 30 03:58:10 PM PDT 24 |
| Peak memory | 573956 kb |
| Host | smart-f9b09dbc-6bc3-436b-ad7a-b539570f3f30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027810566 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_and_unmapped_add r.2027810566 |
| Directory | /workspace/74.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_random.4074258981 |
| Short name | T2653 |
| Test name | |
| Test status | |
| Simulation time | 1115754470 ps |
| CPU time | 37.44 seconds |
| Started | May 30 03:57:48 PM PDT 24 |
| Finished | May 30 03:58:26 PM PDT 24 |
| Peak memory | 572928 kb |
| Host | smart-13b54af2-9331-47b4-ab44-129f5763d050 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074258981 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_random.4074258981 |
| Directory | /workspace/74.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random.4007548293 |
| Short name | T2031 |
| Test name | |
| Test status | |
| Simulation time | 1370013316 ps |
| CPU time | 49.07 seconds |
| Started | May 30 03:57:41 PM PDT 24 |
| Finished | May 30 03:58:31 PM PDT 24 |
| Peak memory | 573072 kb |
| Host | smart-5a7d6d81-a4d3-4a43-8bc1-07d199846b77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007548293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random.4007548293 |
| Directory | /workspace/74.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_large_delays.852156636 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 115504103704 ps |
| CPU time | 1387.94 seconds |
| Started | May 30 03:57:39 PM PDT 24 |
| Finished | May 30 04:20:48 PM PDT 24 |
| Peak memory | 573132 kb |
| Host | smart-1372821c-04f6-4804-80bb-f0c2e03ccdc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852156636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_large_delays.852156636 |
| Directory | /workspace/74.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_slow_rsp.4272041787 |
| Short name | T1527 |
| Test name | |
| Test status | |
| Simulation time | 32125005778 ps |
| CPU time | 552.08 seconds |
| Started | May 30 03:57:39 PM PDT 24 |
| Finished | May 30 04:06:52 PM PDT 24 |
| Peak memory | 573128 kb |
| Host | smart-548f8929-bb95-452a-bd7f-8eb63867dab8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272041787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_slow_rsp.4272041787 |
| Directory | /workspace/74.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_zero_delays.1332178776 |
| Short name | T1797 |
| Test name | |
| Test status | |
| Simulation time | 343485040 ps |
| CPU time | 27.85 seconds |
| Started | May 30 03:57:38 PM PDT 24 |
| Finished | May 30 03:58:07 PM PDT 24 |
| Peak memory | 572956 kb |
| Host | smart-0bd16048-3b91-4a0a-baac-2f6b2f16791f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332178776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_zero_del ays.1332178776 |
| Directory | /workspace/74.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_same_source.1554178310 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 2666246419 ps |
| CPU time | 77.51 seconds |
| Started | May 30 03:57:48 PM PDT 24 |
| Finished | May 30 03:59:07 PM PDT 24 |
| Peak memory | 573136 kb |
| Host | smart-d4e74c17-e6b4-46af-a191-5b118720b7b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554178310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_same_source.1554178310 |
| Directory | /workspace/74.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke.1659721146 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 45337025 ps |
| CPU time | 6.18 seconds |
| Started | May 30 03:57:40 PM PDT 24 |
| Finished | May 30 03:57:47 PM PDT 24 |
| Peak memory | 564868 kb |
| Host | smart-1ce5cc18-3fa7-4137-ba6b-abcd004cb2ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659721146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke.1659721146 |
| Directory | /workspace/74.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_large_delays.2144547998 |
| Short name | T2420 |
| Test name | |
| Test status | |
| Simulation time | 7266022183 ps |
| CPU time | 75.34 seconds |
| Started | May 30 03:57:40 PM PDT 24 |
| Finished | May 30 03:58:57 PM PDT 24 |
| Peak memory | 564972 kb |
| Host | smart-d8dc4d51-fc8c-4e61-a826-0178680c301d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144547998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_large_delays.2144547998 |
| Directory | /workspace/74.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.3826202429 |
| Short name | T1777 |
| Test name | |
| Test status | |
| Simulation time | 5385022349 ps |
| CPU time | 97.78 seconds |
| Started | May 30 03:57:37 PM PDT 24 |
| Finished | May 30 03:59:16 PM PDT 24 |
| Peak memory | 564940 kb |
| Host | smart-83756d35-6ac0-4335-b494-b6b19ee3205f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826202429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_slow_rsp.3826202429 |
| Directory | /workspace/74.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_zero_delays.1503543699 |
| Short name | T2740 |
| Test name | |
| Test status | |
| Simulation time | 54138395 ps |
| CPU time | 7.24 seconds |
| Started | May 30 03:57:38 PM PDT 24 |
| Finished | May 30 03:57:47 PM PDT 24 |
| Peak memory | 563352 kb |
| Host | smart-dfc975a5-eb37-4f5e-97be-85403ed92f2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503543699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_zero_delay s.1503543699 |
| Directory | /workspace/74.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all.2892502055 |
| Short name | T2385 |
| Test name | |
| Test status | |
| Simulation time | 954088253 ps |
| CPU time | 88.37 seconds |
| Started | May 30 03:57:48 PM PDT 24 |
| Finished | May 30 03:59:18 PM PDT 24 |
| Peak memory | 573140 kb |
| Host | smart-0c6e066a-bd48-45cf-a4fc-32a94bc03251 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892502055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all.2892502055 |
| Directory | /workspace/74.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.4291733198 |
| Short name | T1795 |
| Test name | |
| Test status | |
| Simulation time | 1091242485 ps |
| CPU time | 86.66 seconds |
| Started | May 30 03:57:47 PM PDT 24 |
| Finished | May 30 03:59:15 PM PDT 24 |
| Peak memory | 573048 kb |
| Host | smart-e02d2821-7a25-4cad-8067-b3453f3da1ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291733198 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_error.4291733198 |
| Directory | /workspace/74.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.2743299619 |
| Short name | T1345 |
| Test name | |
| Test status | |
| Simulation time | 79103067 ps |
| CPU time | 69.04 seconds |
| Started | May 30 03:57:49 PM PDT 24 |
| Finished | May 30 03:58:59 PM PDT 24 |
| Peak memory | 575200 kb |
| Host | smart-3d132b6e-5df3-4197-82c8-2fa549de8d22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743299619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all _with_rand_reset.2743299619 |
| Directory | /workspace/74.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.2955562564 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 7541186360 ps |
| CPU time | 416.68 seconds |
| Started | May 30 03:57:48 PM PDT 24 |
| Finished | May 30 04:04:46 PM PDT 24 |
| Peak memory | 573172 kb |
| Host | smart-3d53032a-9276-4b74-9aae-3b829672142d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955562564 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_al l_with_reset_error.2955562564 |
| Directory | /workspace/74.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_unmapped_addr.1481700999 |
| Short name | T2680 |
| Test name | |
| Test status | |
| Simulation time | 81588233 ps |
| CPU time | 12.29 seconds |
| Started | May 30 03:57:49 PM PDT 24 |
| Finished | May 30 03:58:02 PM PDT 24 |
| Peak memory | 572980 kb |
| Host | smart-06d34a06-fa74-498b-a942-043f553ce9fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481700999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_unmapped_addr.1481700999 |
| Directory | /workspace/74.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device.753659178 |
| Short name | T1664 |
| Test name | |
| Test status | |
| Simulation time | 2079575754 ps |
| CPU time | 86.06 seconds |
| Started | May 30 03:58:03 PM PDT 24 |
| Finished | May 30 03:59:30 PM PDT 24 |
| Peak memory | 572944 kb |
| Host | smart-ce5a1904-e71f-4e79-8b2c-e5e4ecf32a96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753659178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device. 753659178 |
| Directory | /workspace/75.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.3911032047 |
| Short name | T2415 |
| Test name | |
| Test status | |
| Simulation time | 142236284946 ps |
| CPU time | 2585.25 seconds |
| Started | May 30 03:58:05 PM PDT 24 |
| Finished | May 30 04:41:11 PM PDT 24 |
| Peak memory | 573332 kb |
| Host | smart-87330066-a521-4fa4-8dc0-5babc730613f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911032047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_ device_slow_rsp.3911032047 |
| Directory | /workspace/75.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.3190279571 |
| Short name | T2338 |
| Test name | |
| Test status | |
| Simulation time | 22657364 ps |
| CPU time | 5.45 seconds |
| Started | May 30 03:58:02 PM PDT 24 |
| Finished | May 30 03:58:09 PM PDT 24 |
| Peak memory | 564488 kb |
| Host | smart-06234c5c-f3d9-40cf-bb8d-e3cec462b2b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190279571 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_and_unmapped_add r.3190279571 |
| Directory | /workspace/75.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_random.2564243399 |
| Short name | T1934 |
| Test name | |
| Test status | |
| Simulation time | 518404474 ps |
| CPU time | 40.22 seconds |
| Started | May 30 03:58:00 PM PDT 24 |
| Finished | May 30 03:58:42 PM PDT 24 |
| Peak memory | 572924 kb |
| Host | smart-16002b77-8f5a-4348-879c-ed2194fe7a9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564243399 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_random.2564243399 |
| Directory | /workspace/75.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random.951758413 |
| Short name | T2471 |
| Test name | |
| Test status | |
| Simulation time | 2645902895 ps |
| CPU time | 105.75 seconds |
| Started | May 30 03:57:49 PM PDT 24 |
| Finished | May 30 03:59:35 PM PDT 24 |
| Peak memory | 573116 kb |
| Host | smart-fe9c71d5-958e-4d59-a2f3-255c5e396876 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951758413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random.951758413 |
| Directory | /workspace/75.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.3425971261 |
| Short name | T1886 |
| Test name | |
| Test status | |
| Simulation time | 60418870799 ps |
| CPU time | 644.05 seconds |
| Started | May 30 03:58:01 PM PDT 24 |
| Finished | May 30 04:08:46 PM PDT 24 |
| Peak memory | 573132 kb |
| Host | smart-6b127b2f-aaf9-4f84-973e-8dabe547ef15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425971261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_large_delays.3425971261 |
| Directory | /workspace/75.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.980111304 |
| Short name | T2451 |
| Test name | |
| Test status | |
| Simulation time | 64714078547 ps |
| CPU time | 1181.81 seconds |
| Started | May 30 03:58:01 PM PDT 24 |
| Finished | May 30 04:17:45 PM PDT 24 |
| Peak memory | 573196 kb |
| Host | smart-afeb544f-1a1d-4321-9ad3-9bd3d1a5b502 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980111304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_slow_rsp.980111304 |
| Directory | /workspace/75.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_zero_delays.1592195188 |
| Short name | T2352 |
| Test name | |
| Test status | |
| Simulation time | 271995291 ps |
| CPU time | 26.47 seconds |
| Started | May 30 03:58:00 PM PDT 24 |
| Finished | May 30 03:58:27 PM PDT 24 |
| Peak memory | 573064 kb |
| Host | smart-abd93ea6-9b0c-41c6-942b-4ec2e3b0e7fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592195188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_zero_del ays.1592195188 |
| Directory | /workspace/75.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_same_source.3397100954 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 890191491 ps |
| CPU time | 26.18 seconds |
| Started | May 30 03:58:03 PM PDT 24 |
| Finished | May 30 03:58:30 PM PDT 24 |
| Peak memory | 572996 kb |
| Host | smart-08dd4c0e-2789-4a3d-a182-7ab661592052 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397100954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_same_source.3397100954 |
| Directory | /workspace/75.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke.2035907717 |
| Short name | T1315 |
| Test name | |
| Test status | |
| Simulation time | 39963680 ps |
| CPU time | 5.63 seconds |
| Started | May 30 03:57:54 PM PDT 24 |
| Finished | May 30 03:58:01 PM PDT 24 |
| Peak memory | 564828 kb |
| Host | smart-f8cc445e-e000-40e7-832b-f464bb78c513 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035907717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke.2035907717 |
| Directory | /workspace/75.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.724309382 |
| Short name | T2236 |
| Test name | |
| Test status | |
| Simulation time | 8660838167 ps |
| CPU time | 93.41 seconds |
| Started | May 30 03:57:48 PM PDT 24 |
| Finished | May 30 03:59:22 PM PDT 24 |
| Peak memory | 564936 kb |
| Host | smart-2bfd5e7f-a6fb-4450-8bc4-0f52d7adaf2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724309382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_large_delays.724309382 |
| Directory | /workspace/75.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.3335707792 |
| Short name | T1683 |
| Test name | |
| Test status | |
| Simulation time | 4156847366 ps |
| CPU time | 68.68 seconds |
| Started | May 30 03:57:51 PM PDT 24 |
| Finished | May 30 03:59:01 PM PDT 24 |
| Peak memory | 564860 kb |
| Host | smart-2aa72acb-256a-431d-befa-2a1dc0719ad7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335707792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_slow_rsp.3335707792 |
| Directory | /workspace/75.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_zero_delays.2411912366 |
| Short name | T2837 |
| Test name | |
| Test status | |
| Simulation time | 50564326 ps |
| CPU time | 6.51 seconds |
| Started | May 30 03:57:49 PM PDT 24 |
| Finished | May 30 03:57:57 PM PDT 24 |
| Peak memory | 564824 kb |
| Host | smart-96f65099-7dce-4ff4-a242-0dc59519f47d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411912366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_zero_delay s.2411912366 |
| Directory | /workspace/75.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all.1103083932 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 8575775202 ps |
| CPU time | 294.82 seconds |
| Started | May 30 03:58:00 PM PDT 24 |
| Finished | May 30 04:02:56 PM PDT 24 |
| Peak memory | 573264 kb |
| Host | smart-18073aa7-9814-4a7c-b52c-fbebf82922b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103083932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all.1103083932 |
| Directory | /workspace/75.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.2683876324 |
| Short name | T2728 |
| Test name | |
| Test status | |
| Simulation time | 3072765046 ps |
| CPU time | 123.73 seconds |
| Started | May 30 03:58:02 PM PDT 24 |
| Finished | May 30 04:00:07 PM PDT 24 |
| Peak memory | 573008 kb |
| Host | smart-894b951a-ebb7-43f1-942a-5a4d1daaad01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683876324 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_error.2683876324 |
| Directory | /workspace/75.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.1927862380 |
| Short name | T1379 |
| Test name | |
| Test status | |
| Simulation time | 230480516 ps |
| CPU time | 71.36 seconds |
| Started | May 30 03:58:02 PM PDT 24 |
| Finished | May 30 03:59:14 PM PDT 24 |
| Peak memory | 573084 kb |
| Host | smart-dcb809a1-f1dd-457e-bd9e-c7cece7e2e2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927862380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all _with_rand_reset.1927862380 |
| Directory | /workspace/75.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.1488670454 |
| Short name | T2396 |
| Test name | |
| Test status | |
| Simulation time | 2763386110 ps |
| CPU time | 396.24 seconds |
| Started | May 30 03:58:00 PM PDT 24 |
| Finished | May 30 04:04:37 PM PDT 24 |
| Peak memory | 573172 kb |
| Host | smart-a083a92f-d77d-4828-a337-d10f608c58f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488670454 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_al l_with_reset_error.1488670454 |
| Directory | /workspace/75.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.4139635537 |
| Short name | T1597 |
| Test name | |
| Test status | |
| Simulation time | 799385018 ps |
| CPU time | 35.49 seconds |
| Started | May 30 03:58:01 PM PDT 24 |
| Finished | May 30 03:58:37 PM PDT 24 |
| Peak memory | 573004 kb |
| Host | smart-c07e31d6-8962-4f1e-bdcb-1893ec823b98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139635537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_unmapped_addr.4139635537 |
| Directory | /workspace/75.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device.1039224529 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 441114742 ps |
| CPU time | 40.35 seconds |
| Started | May 30 03:58:04 PM PDT 24 |
| Finished | May 30 03:58:45 PM PDT 24 |
| Peak memory | 573080 kb |
| Host | smart-106c6d77-a3c9-4b67-a76d-9540ec21e9df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039224529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device .1039224529 |
| Directory | /workspace/76.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.790644393 |
| Short name | T2800 |
| Test name | |
| Test status | |
| Simulation time | 64238422978 ps |
| CPU time | 1239.08 seconds |
| Started | May 30 03:58:05 PM PDT 24 |
| Finished | May 30 04:18:45 PM PDT 24 |
| Peak memory | 573272 kb |
| Host | smart-cb3ac618-8039-45ae-83d8-3323aa04c2f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790644393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_d evice_slow_rsp.790644393 |
| Directory | /workspace/76.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.3830847718 |
| Short name | T1658 |
| Test name | |
| Test status | |
| Simulation time | 585812350 ps |
| CPU time | 21.39 seconds |
| Started | May 30 03:58:07 PM PDT 24 |
| Finished | May 30 03:58:29 PM PDT 24 |
| Peak memory | 572948 kb |
| Host | smart-18f51e0a-f34b-42de-b1c5-fc16744035ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830847718 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_and_unmapped_add r.3830847718 |
| Directory | /workspace/76.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_random.2516249182 |
| Short name | T1410 |
| Test name | |
| Test status | |
| Simulation time | 1826562243 ps |
| CPU time | 63.95 seconds |
| Started | May 30 03:58:04 PM PDT 24 |
| Finished | May 30 03:59:08 PM PDT 24 |
| Peak memory | 572928 kb |
| Host | smart-6b3d4d3d-67fd-42a4-8ea4-fd8b3aa9ccc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516249182 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_random.2516249182 |
| Directory | /workspace/76.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random.2342951644 |
| Short name | T2698 |
| Test name | |
| Test status | |
| Simulation time | 706286220 ps |
| CPU time | 24.78 seconds |
| Started | May 30 03:58:02 PM PDT 24 |
| Finished | May 30 03:58:27 PM PDT 24 |
| Peak memory | 572984 kb |
| Host | smart-ff9a05fa-01ae-4b6f-bc40-504974bcbd79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342951644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random.2342951644 |
| Directory | /workspace/76.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_large_delays.3596873565 |
| Short name | T1694 |
| Test name | |
| Test status | |
| Simulation time | 80979974984 ps |
| CPU time | 877.02 seconds |
| Started | May 30 03:58:04 PM PDT 24 |
| Finished | May 30 04:12:42 PM PDT 24 |
| Peak memory | 573180 kb |
| Host | smart-4b45407c-b673-4b0b-8526-5a7677e28480 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596873565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_large_delays.3596873565 |
| Directory | /workspace/76.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_slow_rsp.3038214187 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 64343564595 ps |
| CPU time | 1302.59 seconds |
| Started | May 30 03:58:03 PM PDT 24 |
| Finished | May 30 04:19:47 PM PDT 24 |
| Peak memory | 573216 kb |
| Host | smart-acda678a-2353-409f-a89e-b45c3dece8eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038214187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_slow_rsp.3038214187 |
| Directory | /workspace/76.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.2563273866 |
| Short name | T1550 |
| Test name | |
| Test status | |
| Simulation time | 408982451 ps |
| CPU time | 39.7 seconds |
| Started | May 30 03:58:04 PM PDT 24 |
| Finished | May 30 03:58:45 PM PDT 24 |
| Peak memory | 573020 kb |
| Host | smart-20ed31f3-51ad-46c6-bfa9-79315b6f8cda |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563273866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_zero_del ays.2563273866 |
| Directory | /workspace/76.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_same_source.3145380043 |
| Short name | T1759 |
| Test name | |
| Test status | |
| Simulation time | 1089229549 ps |
| CPU time | 29.9 seconds |
| Started | May 30 03:58:04 PM PDT 24 |
| Finished | May 30 03:58:35 PM PDT 24 |
| Peak memory | 573108 kb |
| Host | smart-6be7a21c-9c1a-4740-8afc-e4ca003e1f51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145380043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_same_source.3145380043 |
| Directory | /workspace/76.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke.2812768198 |
| Short name | T1666 |
| Test name | |
| Test status | |
| Simulation time | 178901123 ps |
| CPU time | 8.16 seconds |
| Started | May 30 03:58:04 PM PDT 24 |
| Finished | May 30 03:58:13 PM PDT 24 |
| Peak memory | 564816 kb |
| Host | smart-55b37b70-66fc-4805-856d-e02c81c22baa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812768198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke.2812768198 |
| Directory | /workspace/76.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_large_delays.2918218984 |
| Short name | T2106 |
| Test name | |
| Test status | |
| Simulation time | 7692524139 ps |
| CPU time | 80.69 seconds |
| Started | May 30 03:58:04 PM PDT 24 |
| Finished | May 30 03:59:26 PM PDT 24 |
| Peak memory | 564936 kb |
| Host | smart-db5d8f93-4884-44b4-abfb-1d18bf0a6f9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918218984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_large_delays.2918218984 |
| Directory | /workspace/76.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.247381330 |
| Short name | T2592 |
| Test name | |
| Test status | |
| Simulation time | 4816164326 ps |
| CPU time | 82.68 seconds |
| Started | May 30 03:58:04 PM PDT 24 |
| Finished | May 30 03:59:27 PM PDT 24 |
| Peak memory | 564976 kb |
| Host | smart-61efd244-159c-40e7-a7e4-0f58a24f2644 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247381330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_slow_rsp.247381330 |
| Directory | /workspace/76.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_zero_delays.2297911995 |
| Short name | T2738 |
| Test name | |
| Test status | |
| Simulation time | 52093467 ps |
| CPU time | 6.18 seconds |
| Started | May 30 03:58:04 PM PDT 24 |
| Finished | May 30 03:58:11 PM PDT 24 |
| Peak memory | 564788 kb |
| Host | smart-056b8f73-5c9e-4dd0-af52-a8cf8cf258a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297911995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_zero_delay s.2297911995 |
| Directory | /workspace/76.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all.1205270494 |
| Short name | T2588 |
| Test name | |
| Test status | |
| Simulation time | 7804767714 ps |
| CPU time | 338.96 seconds |
| Started | May 30 03:58:07 PM PDT 24 |
| Finished | May 30 04:03:47 PM PDT 24 |
| Peak memory | 573280 kb |
| Host | smart-2364db38-46fb-4677-b38f-8826e4e37c5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205270494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all.1205270494 |
| Directory | /workspace/76.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.3670691293 |
| Short name | T1596 |
| Test name | |
| Test status | |
| Simulation time | 4856873709 ps |
| CPU time | 177.53 seconds |
| Started | May 30 03:58:14 PM PDT 24 |
| Finished | May 30 04:01:13 PM PDT 24 |
| Peak memory | 573212 kb |
| Host | smart-b81441f7-cf03-4b74-aff4-1fc5c4999137 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670691293 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_error.3670691293 |
| Directory | /workspace/76.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.2867370201 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 860377346 ps |
| CPU time | 229.95 seconds |
| Started | May 30 03:58:17 PM PDT 24 |
| Finished | May 30 04:02:07 PM PDT 24 |
| Peak memory | 576444 kb |
| Host | smart-6829cdee-8ab1-4b52-a693-0a842731fe30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867370201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all _with_rand_reset.2867370201 |
| Directory | /workspace/76.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.1310254764 |
| Short name | T1973 |
| Test name | |
| Test status | |
| Simulation time | 816875240 ps |
| CPU time | 172.54 seconds |
| Started | May 30 03:58:13 PM PDT 24 |
| Finished | May 30 04:01:07 PM PDT 24 |
| Peak memory | 573076 kb |
| Host | smart-80f2c79f-6b89-4412-9c94-20eb394b2f8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310254764 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_al l_with_reset_error.1310254764 |
| Directory | /workspace/76.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_unmapped_addr.2892994829 |
| Short name | T2841 |
| Test name | |
| Test status | |
| Simulation time | 246237226 ps |
| CPU time | 13.8 seconds |
| Started | May 30 03:58:06 PM PDT 24 |
| Finished | May 30 03:58:21 PM PDT 24 |
| Peak memory | 573052 kb |
| Host | smart-a7989024-385e-45f0-b7ed-ab6ccd99d448 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892994829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_unmapped_addr.2892994829 |
| Directory | /workspace/76.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device.2904903323 |
| Short name | T2722 |
| Test name | |
| Test status | |
| Simulation time | 1256933160 ps |
| CPU time | 45.84 seconds |
| Started | May 30 03:58:15 PM PDT 24 |
| Finished | May 30 03:59:02 PM PDT 24 |
| Peak memory | 564772 kb |
| Host | smart-5a7287f0-1c0e-4b75-9b09-8af251cbb4b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904903323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device .2904903323 |
| Directory | /workspace/77.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.2959136252 |
| Short name | T2739 |
| Test name | |
| Test status | |
| Simulation time | 2966285639 ps |
| CPU time | 55.63 seconds |
| Started | May 30 03:58:16 PM PDT 24 |
| Finished | May 30 03:59:12 PM PDT 24 |
| Peak memory | 564960 kb |
| Host | smart-136f0e21-7cf0-4aed-9093-876ced339252 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959136252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_ device_slow_rsp.2959136252 |
| Directory | /workspace/77.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.3350299705 |
| Short name | T1854 |
| Test name | |
| Test status | |
| Simulation time | 295343029 ps |
| CPU time | 13.53 seconds |
| Started | May 30 03:58:27 PM PDT 24 |
| Finished | May 30 03:58:41 PM PDT 24 |
| Peak memory | 572852 kb |
| Host | smart-414d3b32-39da-408f-bb4b-4914a802b35e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350299705 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_and_unmapped_add r.3350299705 |
| Directory | /workspace/77.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_random.4038363447 |
| Short name | T1412 |
| Test name | |
| Test status | |
| Simulation time | 379043444 ps |
| CPU time | 30.63 seconds |
| Started | May 30 03:58:15 PM PDT 24 |
| Finished | May 30 03:58:47 PM PDT 24 |
| Peak memory | 572840 kb |
| Host | smart-778bcb77-ed01-4e0d-9ca9-a45a2b80b62e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038363447 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_random.4038363447 |
| Directory | /workspace/77.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random.1980510645 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 102842887 ps |
| CPU time | 7.59 seconds |
| Started | May 30 03:58:14 PM PDT 24 |
| Finished | May 30 03:58:22 PM PDT 24 |
| Peak memory | 563416 kb |
| Host | smart-a11b40ef-722d-452b-b6dd-955a8365e3e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980510645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random.1980510645 |
| Directory | /workspace/77.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_large_delays.4179032372 |
| Short name | T1931 |
| Test name | |
| Test status | |
| Simulation time | 72971265390 ps |
| CPU time | 788.59 seconds |
| Started | May 30 03:58:15 PM PDT 24 |
| Finished | May 30 04:11:25 PM PDT 24 |
| Peak memory | 573132 kb |
| Host | smart-1d20c8b0-bfb5-4aeb-bc7f-11d9af7d2870 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179032372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_large_delays.4179032372 |
| Directory | /workspace/77.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_slow_rsp.2153382924 |
| Short name | T2324 |
| Test name | |
| Test status | |
| Simulation time | 19101268610 ps |
| CPU time | 312.59 seconds |
| Started | May 30 03:58:14 PM PDT 24 |
| Finished | May 30 04:03:27 PM PDT 24 |
| Peak memory | 572848 kb |
| Host | smart-59217d59-7046-43e9-ae2f-7321fe6130d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153382924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_slow_rsp.2153382924 |
| Directory | /workspace/77.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.2515539440 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 69841798 ps |
| CPU time | 9.1 seconds |
| Started | May 30 03:58:16 PM PDT 24 |
| Finished | May 30 03:58:26 PM PDT 24 |
| Peak memory | 564828 kb |
| Host | smart-bc91353e-0d0a-4957-8c54-88469fe636c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515539440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_zero_del ays.2515539440 |
| Directory | /workspace/77.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_same_source.3173129439 |
| Short name | T2672 |
| Test name | |
| Test status | |
| Simulation time | 435501701 ps |
| CPU time | 33.81 seconds |
| Started | May 30 03:58:16 PM PDT 24 |
| Finished | May 30 03:58:51 PM PDT 24 |
| Peak memory | 572928 kb |
| Host | smart-858ec663-8346-41b3-9db3-71af450530da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173129439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_same_source.3173129439 |
| Directory | /workspace/77.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke.936885003 |
| Short name | T1381 |
| Test name | |
| Test status | |
| Simulation time | 219550594 ps |
| CPU time | 9.85 seconds |
| Started | May 30 03:58:15 PM PDT 24 |
| Finished | May 30 03:58:26 PM PDT 24 |
| Peak memory | 564820 kb |
| Host | smart-e89ed4c9-831d-4a0d-892e-b462c29db9fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936885003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke.936885003 |
| Directory | /workspace/77.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_large_delays.2488860380 |
| Short name | T2499 |
| Test name | |
| Test status | |
| Simulation time | 6906004678 ps |
| CPU time | 72.3 seconds |
| Started | May 30 03:58:15 PM PDT 24 |
| Finished | May 30 03:59:28 PM PDT 24 |
| Peak memory | 564964 kb |
| Host | smart-f07d0a90-8540-4c9a-8f5a-8b6f3f7bfb5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488860380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_large_delays.2488860380 |
| Directory | /workspace/77.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.20489230 |
| Short name | T2626 |
| Test name | |
| Test status | |
| Simulation time | 4052794990 ps |
| CPU time | 68.57 seconds |
| Started | May 30 03:58:15 PM PDT 24 |
| Finished | May 30 03:59:24 PM PDT 24 |
| Peak memory | 564864 kb |
| Host | smart-85e8a14c-61de-442b-9a95-4bdfb368d159 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20489230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_slow_rsp.20489230 |
| Directory | /workspace/77.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_zero_delays.1276678273 |
| Short name | T2306 |
| Test name | |
| Test status | |
| Simulation time | 50780066 ps |
| CPU time | 6.63 seconds |
| Started | May 30 03:58:14 PM PDT 24 |
| Finished | May 30 03:58:22 PM PDT 24 |
| Peak memory | 564772 kb |
| Host | smart-6a3da219-7c54-41d6-99cc-384866801a9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276678273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_zero_delay s.1276678273 |
| Directory | /workspace/77.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all.1036539573 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 9844783993 ps |
| CPU time | 365.47 seconds |
| Started | May 30 03:58:28 PM PDT 24 |
| Finished | May 30 04:04:35 PM PDT 24 |
| Peak memory | 573264 kb |
| Host | smart-de483133-1130-41ce-b662-b85743225a75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036539573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all.1036539573 |
| Directory | /workspace/77.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.1053791361 |
| Short name | T1780 |
| Test name | |
| Test status | |
| Simulation time | 12142153381 ps |
| CPU time | 464.9 seconds |
| Started | May 30 03:58:28 PM PDT 24 |
| Finished | May 30 04:06:14 PM PDT 24 |
| Peak memory | 573164 kb |
| Host | smart-b033a5e8-0e79-4ae4-ae83-2fb22a58e3bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053791361 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_error.1053791361 |
| Directory | /workspace/77.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.3636390825 |
| Short name | T1751 |
| Test name | |
| Test status | |
| Simulation time | 960160267 ps |
| CPU time | 337.84 seconds |
| Started | May 30 03:58:26 PM PDT 24 |
| Finished | May 30 04:04:05 PM PDT 24 |
| Peak memory | 573128 kb |
| Host | smart-80b88145-69e8-4ee0-a4ca-d12944bf4b68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636390825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all _with_rand_reset.3636390825 |
| Directory | /workspace/77.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.4119315185 |
| Short name | T2153 |
| Test name | |
| Test status | |
| Simulation time | 220040512 ps |
| CPU time | 69.14 seconds |
| Started | May 30 03:58:30 PM PDT 24 |
| Finished | May 30 03:59:40 PM PDT 24 |
| Peak memory | 575124 kb |
| Host | smart-2eaa7a79-907f-4895-9947-570bf58073f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119315185 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_al l_with_reset_error.4119315185 |
| Directory | /workspace/77.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.640069635 |
| Short name | T1736 |
| Test name | |
| Test status | |
| Simulation time | 120848170 ps |
| CPU time | 15.67 seconds |
| Started | May 30 03:58:18 PM PDT 24 |
| Finished | May 30 03:58:34 PM PDT 24 |
| Peak memory | 573096 kb |
| Host | smart-39c14dad-47b5-4000-85ed-b55aad44db30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640069635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_unmapped_addr.640069635 |
| Directory | /workspace/77.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device.2649797462 |
| Short name | T2221 |
| Test name | |
| Test status | |
| Simulation time | 2823576583 ps |
| CPU time | 105.34 seconds |
| Started | May 30 03:58:31 PM PDT 24 |
| Finished | May 30 04:00:18 PM PDT 24 |
| Peak memory | 573088 kb |
| Host | smart-3e5be470-b1af-408d-a8d7-13cdbd470f19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649797462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device .2649797462 |
| Directory | /workspace/78.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.3412377919 |
| Short name | T2006 |
| Test name | |
| Test status | |
| Simulation time | 78810831440 ps |
| CPU time | 1397.24 seconds |
| Started | May 30 03:58:28 PM PDT 24 |
| Finished | May 30 04:21:46 PM PDT 24 |
| Peak memory | 573200 kb |
| Host | smart-c2f6c89f-2aed-404c-88d8-17cd6c7f0e7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412377919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_ device_slow_rsp.3412377919 |
| Directory | /workspace/78.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.3925791035 |
| Short name | T2281 |
| Test name | |
| Test status | |
| Simulation time | 666522546 ps |
| CPU time | 28.07 seconds |
| Started | May 30 03:58:30 PM PDT 24 |
| Finished | May 30 03:58:59 PM PDT 24 |
| Peak memory | 572920 kb |
| Host | smart-9e1be60a-19cb-405e-a755-1183ca01a4e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925791035 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_and_unmapped_add r.3925791035 |
| Directory | /workspace/78.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_random.1805360336 |
| Short name | T2319 |
| Test name | |
| Test status | |
| Simulation time | 1353207194 ps |
| CPU time | 51.27 seconds |
| Started | May 30 03:58:27 PM PDT 24 |
| Finished | May 30 03:59:19 PM PDT 24 |
| Peak memory | 572816 kb |
| Host | smart-780392c8-83c4-4ed6-9af5-45aa84e96103 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805360336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_random.1805360336 |
| Directory | /workspace/78.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random.794545819 |
| Short name | T1524 |
| Test name | |
| Test status | |
| Simulation time | 1547397362 ps |
| CPU time | 61.7 seconds |
| Started | May 30 03:58:28 PM PDT 24 |
| Finished | May 30 03:59:31 PM PDT 24 |
| Peak memory | 573040 kb |
| Host | smart-abb4e590-2cad-4aac-a0ca-458dfe6df007 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794545819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random.794545819 |
| Directory | /workspace/78.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_large_delays.676888907 |
| Short name | T2294 |
| Test name | |
| Test status | |
| Simulation time | 98134591590 ps |
| CPU time | 1174.97 seconds |
| Started | May 30 03:58:28 PM PDT 24 |
| Finished | May 30 04:18:04 PM PDT 24 |
| Peak memory | 573092 kb |
| Host | smart-a81f3198-6a27-4c9d-823c-eb255e16531f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676888907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_large_delays.676888907 |
| Directory | /workspace/78.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_slow_rsp.344062507 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 32152308642 ps |
| CPU time | 598.87 seconds |
| Started | May 30 03:58:30 PM PDT 24 |
| Finished | May 30 04:08:30 PM PDT 24 |
| Peak memory | 573216 kb |
| Host | smart-6e00d9f1-3498-4d06-9ed0-fb8cef48195b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344062507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_slow_rsp.344062507 |
| Directory | /workspace/78.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.1557486304 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 523975297 ps |
| CPU time | 48.16 seconds |
| Started | May 30 03:58:27 PM PDT 24 |
| Finished | May 30 03:59:16 PM PDT 24 |
| Peak memory | 573028 kb |
| Host | smart-6630d518-5edb-488c-b8d3-211513a93651 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557486304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_zero_del ays.1557486304 |
| Directory | /workspace/78.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_same_source.694448376 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 2458167057 ps |
| CPU time | 74.13 seconds |
| Started | May 30 03:58:29 PM PDT 24 |
| Finished | May 30 03:59:44 PM PDT 24 |
| Peak memory | 573124 kb |
| Host | smart-5c5b6839-9187-4741-8537-da74b2d4666c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694448376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_same_source.694448376 |
| Directory | /workspace/78.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke.3711605703 |
| Short name | T2572 |
| Test name | |
| Test status | |
| Simulation time | 48213047 ps |
| CPU time | 6.23 seconds |
| Started | May 30 03:58:26 PM PDT 24 |
| Finished | May 30 03:58:33 PM PDT 24 |
| Peak memory | 564824 kb |
| Host | smart-8ea9f17b-2f22-49c3-bb7e-c720cf648098 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711605703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke.3711605703 |
| Directory | /workspace/78.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_large_delays.1875892276 |
| Short name | T2873 |
| Test name | |
| Test status | |
| Simulation time | 9594723378 ps |
| CPU time | 101.65 seconds |
| Started | May 30 03:58:31 PM PDT 24 |
| Finished | May 30 04:00:13 PM PDT 24 |
| Peak memory | 564972 kb |
| Host | smart-20812b6f-359d-44e7-a1a4-b60959e58b2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875892276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_large_delays.1875892276 |
| Directory | /workspace/78.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.1398685899 |
| Short name | T1881 |
| Test name | |
| Test status | |
| Simulation time | 4970576027 ps |
| CPU time | 89.57 seconds |
| Started | May 30 03:58:32 PM PDT 24 |
| Finished | May 30 04:00:03 PM PDT 24 |
| Peak memory | 563476 kb |
| Host | smart-6cc637d8-8caa-4f95-86a2-2c5769eefa99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398685899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_slow_rsp.1398685899 |
| Directory | /workspace/78.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_zero_delays.2286883120 |
| Short name | T1945 |
| Test name | |
| Test status | |
| Simulation time | 46172217 ps |
| CPU time | 6.14 seconds |
| Started | May 30 03:58:30 PM PDT 24 |
| Finished | May 30 03:58:38 PM PDT 24 |
| Peak memory | 564812 kb |
| Host | smart-c4ce6796-2942-4112-a6ce-93feacd5e8b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286883120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_zero_delay s.2286883120 |
| Directory | /workspace/78.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all.3640612430 |
| Short name | T1984 |
| Test name | |
| Test status | |
| Simulation time | 1040913645 ps |
| CPU time | 88.34 seconds |
| Started | May 30 03:58:30 PM PDT 24 |
| Finished | May 30 04:00:00 PM PDT 24 |
| Peak memory | 573096 kb |
| Host | smart-2264454d-f0de-4454-a9fc-44ce4db6a618 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640612430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all.3640612430 |
| Directory | /workspace/78.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.3851890385 |
| Short name | T2859 |
| Test name | |
| Test status | |
| Simulation time | 3103910011 ps |
| CPU time | 136.51 seconds |
| Started | May 30 03:58:27 PM PDT 24 |
| Finished | May 30 04:00:45 PM PDT 24 |
| Peak memory | 573016 kb |
| Host | smart-1ee000f5-abef-4d18-9524-2087c3447c5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851890385 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_error.3851890385 |
| Directory | /workspace/78.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.197820071 |
| Short name | T2403 |
| Test name | |
| Test status | |
| Simulation time | 50613796 ps |
| CPU time | 34.37 seconds |
| Started | May 30 03:58:30 PM PDT 24 |
| Finished | May 30 03:59:06 PM PDT 24 |
| Peak memory | 564956 kb |
| Host | smart-b6b1921b-32c5-4c2d-ba38-a134f3c8a76f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197820071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_ with_rand_reset.197820071 |
| Directory | /workspace/78.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.392782525 |
| Short name | T2522 |
| Test name | |
| Test status | |
| Simulation time | 73251207 ps |
| CPU time | 26.89 seconds |
| Started | May 30 03:58:28 PM PDT 24 |
| Finished | May 30 03:58:56 PM PDT 24 |
| Peak memory | 573088 kb |
| Host | smart-4fcf9b12-0a4b-42fa-a1c9-1425230cc337 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392782525 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all _with_reset_error.392782525 |
| Directory | /workspace/78.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_unmapped_addr.1860164062 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 1344644719 ps |
| CPU time | 57.84 seconds |
| Started | May 30 03:58:27 PM PDT 24 |
| Finished | May 30 03:59:26 PM PDT 24 |
| Peak memory | 573068 kb |
| Host | smart-c212fa90-5fd8-4dfb-8d76-04fdcb3a6928 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860164062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_unmapped_addr.1860164062 |
| Directory | /workspace/78.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device.918231170 |
| Short name | T1611 |
| Test name | |
| Test status | |
| Simulation time | 968445369 ps |
| CPU time | 42.46 seconds |
| Started | May 30 03:58:26 PM PDT 24 |
| Finished | May 30 03:59:09 PM PDT 24 |
| Peak memory | 572980 kb |
| Host | smart-61b433c2-9ce3-47a6-8a2f-abebadc7ce36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918231170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device. 918231170 |
| Directory | /workspace/79.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.2422214569 |
| Short name | T2176 |
| Test name | |
| Test status | |
| Simulation time | 111298366563 ps |
| CPU time | 2161.23 seconds |
| Started | May 30 03:58:28 PM PDT 24 |
| Finished | May 30 04:34:31 PM PDT 24 |
| Peak memory | 573352 kb |
| Host | smart-2a91c8b9-87c3-4a0c-8b3b-cada2574c96a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422214569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_ device_slow_rsp.2422214569 |
| Directory | /workspace/79.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.2225290041 |
| Short name | T2627 |
| Test name | |
| Test status | |
| Simulation time | 325383021 ps |
| CPU time | 13.31 seconds |
| Started | May 30 03:58:28 PM PDT 24 |
| Finished | May 30 03:58:43 PM PDT 24 |
| Peak memory | 573964 kb |
| Host | smart-0dc8a94c-7de1-4521-849f-745481d49313 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225290041 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_and_unmapped_add r.2225290041 |
| Directory | /workspace/79.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_random.988261261 |
| Short name | T1558 |
| Test name | |
| Test status | |
| Simulation time | 539100695 ps |
| CPU time | 41.98 seconds |
| Started | May 30 03:58:28 PM PDT 24 |
| Finished | May 30 03:59:11 PM PDT 24 |
| Peak memory | 572960 kb |
| Host | smart-ccda1a92-2829-49e2-82f0-d88d9be9548f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988261261 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_random.988261261 |
| Directory | /workspace/79.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random.636285517 |
| Short name | T2161 |
| Test name | |
| Test status | |
| Simulation time | 1476363693 ps |
| CPU time | 55.73 seconds |
| Started | May 30 03:58:28 PM PDT 24 |
| Finished | May 30 03:59:25 PM PDT 24 |
| Peak memory | 573072 kb |
| Host | smart-6529ab74-f1b3-4f41-bf94-07c787b99f31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636285517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random.636285517 |
| Directory | /workspace/79.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_large_delays.4187861682 |
| Short name | T2750 |
| Test name | |
| Test status | |
| Simulation time | 34299344456 ps |
| CPU time | 369.13 seconds |
| Started | May 30 03:58:26 PM PDT 24 |
| Finished | May 30 04:04:36 PM PDT 24 |
| Peak memory | 573204 kb |
| Host | smart-5cf051e1-a081-4cd6-bab4-bc9e6abca884 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187861682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_large_delays.4187861682 |
| Directory | /workspace/79.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_slow_rsp.1289283262 |
| Short name | T2301 |
| Test name | |
| Test status | |
| Simulation time | 68316426989 ps |
| CPU time | 1292.09 seconds |
| Started | May 30 03:58:27 PM PDT 24 |
| Finished | May 30 04:20:01 PM PDT 24 |
| Peak memory | 573192 kb |
| Host | smart-7ddcd8a0-631d-41be-9b47-5fdfc7c1037e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289283262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_slow_rsp.1289283262 |
| Directory | /workspace/79.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_zero_delays.343941711 |
| Short name | T2257 |
| Test name | |
| Test status | |
| Simulation time | 555205794 ps |
| CPU time | 52.38 seconds |
| Started | May 30 03:58:27 PM PDT 24 |
| Finished | May 30 03:59:21 PM PDT 24 |
| Peak memory | 573028 kb |
| Host | smart-fb9a8478-1e01-416a-85af-03e166bd0e31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343941711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_zero_dela ys.343941711 |
| Directory | /workspace/79.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_same_source.1339849539 |
| Short name | T1986 |
| Test name | |
| Test status | |
| Simulation time | 1394018911 ps |
| CPU time | 41.81 seconds |
| Started | May 30 03:58:31 PM PDT 24 |
| Finished | May 30 03:59:14 PM PDT 24 |
| Peak memory | 573068 kb |
| Host | smart-96de8f83-126c-4720-b73f-32a42864e523 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339849539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_same_source.1339849539 |
| Directory | /workspace/79.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke.2074361355 |
| Short name | T2210 |
| Test name | |
| Test status | |
| Simulation time | 47329746 ps |
| CPU time | 6.68 seconds |
| Started | May 30 03:58:27 PM PDT 24 |
| Finished | May 30 03:58:34 PM PDT 24 |
| Peak memory | 564844 kb |
| Host | smart-d5acd97d-27a4-4344-8214-435203a1106c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074361355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke.2074361355 |
| Directory | /workspace/79.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.2796702725 |
| Short name | T1924 |
| Test name | |
| Test status | |
| Simulation time | 8792341558 ps |
| CPU time | 95.48 seconds |
| Started | May 30 03:58:28 PM PDT 24 |
| Finished | May 30 04:00:05 PM PDT 24 |
| Peak memory | 564928 kb |
| Host | smart-e87ce96b-f7e4-45ba-9dec-e7dfb3bb9173 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796702725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_large_delays.2796702725 |
| Directory | /workspace/79.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.2823153408 |
| Short name | T2774 |
| Test name | |
| Test status | |
| Simulation time | 5724707986 ps |
| CPU time | 97.94 seconds |
| Started | May 30 03:58:31 PM PDT 24 |
| Finished | May 30 04:00:10 PM PDT 24 |
| Peak memory | 564952 kb |
| Host | smart-ca6e1bb1-e9b2-463b-8203-0faf06bfd7ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823153408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_slow_rsp.2823153408 |
| Directory | /workspace/79.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.2695076742 |
| Short name | T2559 |
| Test name | |
| Test status | |
| Simulation time | 57170234 ps |
| CPU time | 6.32 seconds |
| Started | May 30 03:58:31 PM PDT 24 |
| Finished | May 30 03:58:38 PM PDT 24 |
| Peak memory | 564816 kb |
| Host | smart-b8ecf4bb-e604-4e4a-905d-93cbb6b64ed6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695076742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_zero_delay s.2695076742 |
| Directory | /workspace/79.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all.2291807979 |
| Short name | T2870 |
| Test name | |
| Test status | |
| Simulation time | 1287766658 ps |
| CPU time | 44.37 seconds |
| Started | May 30 03:58:32 PM PDT 24 |
| Finished | May 30 03:59:17 PM PDT 24 |
| Peak memory | 573068 kb |
| Host | smart-7c634238-9799-4f73-b031-15b3ac60cb02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291807979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all.2291807979 |
| Directory | /workspace/79.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.3539288356 |
| Short name | T1788 |
| Test name | |
| Test status | |
| Simulation time | 10270204681 ps |
| CPU time | 350.69 seconds |
| Started | May 30 03:58:29 PM PDT 24 |
| Finished | May 30 04:04:21 PM PDT 24 |
| Peak memory | 573132 kb |
| Host | smart-0f820cfe-c3a6-4811-b53a-583921e1e783 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539288356 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_error.3539288356 |
| Directory | /workspace/79.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.2589670118 |
| Short name | T2817 |
| Test name | |
| Test status | |
| Simulation time | 871801285 ps |
| CPU time | 330.81 seconds |
| Started | May 30 03:58:29 PM PDT 24 |
| Finished | May 30 04:04:01 PM PDT 24 |
| Peak memory | 576996 kb |
| Host | smart-fc4e187e-c3d7-40b4-9d71-3ed8547f035b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589670118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all _with_rand_reset.2589670118 |
| Directory | /workspace/79.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.1391201878 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 649414360 ps |
| CPU time | 63.82 seconds |
| Started | May 30 03:58:40 PM PDT 24 |
| Finished | May 30 03:59:44 PM PDT 24 |
| Peak memory | 575136 kb |
| Host | smart-ea029927-ef2f-4c83-a003-bfa1577d9aa3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391201878 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_al l_with_reset_error.1391201878 |
| Directory | /workspace/79.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_unmapped_addr.3015663753 |
| Short name | T2610 |
| Test name | |
| Test status | |
| Simulation time | 928589729 ps |
| CPU time | 36.11 seconds |
| Started | May 30 03:58:28 PM PDT 24 |
| Finished | May 30 03:59:05 PM PDT 24 |
| Peak memory | 573068 kb |
| Host | smart-a5dfcdbe-65db-4208-85d6-81dd7de08355 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015663753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_unmapped_addr.3015663753 |
| Directory | /workspace/79.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_csr_rw.1105920949 |
| Short name | T2475 |
| Test name | |
| Test status | |
| Simulation time | 5538469116 ps |
| CPU time | 581.24 seconds |
| Started | May 30 03:48:51 PM PDT 24 |
| Finished | May 30 03:58:34 PM PDT 24 |
| Peak memory | 593072 kb |
| Host | smart-1953fd7e-d626-4a86-9ca5-c332ca621c3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105920949 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_csr_rw.1105920949 |
| Directory | /workspace/8.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.1713592159 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 29110886652 ps |
| CPU time | 3841.51 seconds |
| Started | May 30 03:48:55 PM PDT 24 |
| Finished | May 30 04:52:59 PM PDT 24 |
| Peak memory | 587816 kb |
| Host | smart-b83655ed-c108-48f4-a7df-d40d2bf942a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713592159 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 8.chip_same_csr_outstanding.1713592159 |
| Directory | /workspace/8.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_tl_errors.40328093 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 2876461167 ps |
| CPU time | 144.59 seconds |
| Started | May 30 03:48:49 PM PDT 24 |
| Finished | May 30 03:51:16 PM PDT 24 |
| Peak memory | 588540 kb |
| Host | smart-0d44578e-2160-468c-ab28-fc80099a21c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40328093 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_tl_errors.40328093 |
| Directory | /workspace/8.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device.548297643 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 544495167 ps |
| CPU time | 48.62 seconds |
| Started | May 30 03:48:50 PM PDT 24 |
| Finished | May 30 03:49:40 PM PDT 24 |
| Peak memory | 572988 kb |
| Host | smart-d9a1051b-1c94-45db-a6bb-bcd07ac84fe8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548297643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.548297643 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.1270846002 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 46484294638 ps |
| CPU time | 838.16 seconds |
| Started | May 30 03:48:55 PM PDT 24 |
| Finished | May 30 04:02:55 PM PDT 24 |
| Peak memory | 573172 kb |
| Host | smart-6df783f9-99ae-4e5a-b88d-346eebb24fe0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270846002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_d evice_slow_rsp.1270846002 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.3560248206 |
| Short name | T1667 |
| Test name | |
| Test status | |
| Simulation time | 192894869 ps |
| CPU time | 9.77 seconds |
| Started | May 30 03:48:50 PM PDT 24 |
| Finished | May 30 03:49:01 PM PDT 24 |
| Peak memory | 564756 kb |
| Host | smart-91e5a9b6-3e5f-4a5e-acbb-e7d4614e16f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560248206 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr .3560248206 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_random.734256104 |
| Short name | T2311 |
| Test name | |
| Test status | |
| Simulation time | 1527195363 ps |
| CPU time | 54.46 seconds |
| Started | May 30 03:48:52 PM PDT 24 |
| Finished | May 30 03:49:48 PM PDT 24 |
| Peak memory | 573956 kb |
| Host | smart-33663f33-f345-4da0-95c6-503855ec4d36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734256104 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.734256104 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random.3791043703 |
| Short name | T2723 |
| Test name | |
| Test status | |
| Simulation time | 514802898 ps |
| CPU time | 20.81 seconds |
| Started | May 30 03:49:02 PM PDT 24 |
| Finished | May 30 03:49:24 PM PDT 24 |
| Peak memory | 572960 kb |
| Host | smart-4bd08f82-82c3-4ccb-979b-d6cf60936368 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791043703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random.3791043703 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_large_delays.2397475077 |
| Short name | T2107 |
| Test name | |
| Test status | |
| Simulation time | 9773965413 ps |
| CPU time | 105.51 seconds |
| Started | May 30 03:48:52 PM PDT 24 |
| Finished | May 30 03:50:39 PM PDT 24 |
| Peak memory | 564956 kb |
| Host | smart-d09f118c-3535-4194-bdda-fa67fcb881e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397475077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.2397475077 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.3069573239 |
| Short name | T2288 |
| Test name | |
| Test status | |
| Simulation time | 33552440440 ps |
| CPU time | 552.61 seconds |
| Started | May 30 03:48:49 PM PDT 24 |
| Finished | May 30 03:58:04 PM PDT 24 |
| Peak memory | 573184 kb |
| Host | smart-395a0e0a-8972-4d32-aff6-e4e8bf07b60b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069573239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.3069573239 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.3774044639 |
| Short name | T1955 |
| Test name | |
| Test status | |
| Simulation time | 464971869 ps |
| CPU time | 41.03 seconds |
| Started | May 30 03:48:55 PM PDT 24 |
| Finished | May 30 03:49:38 PM PDT 24 |
| Peak memory | 573048 kb |
| Host | smart-14c4f090-0113-4b9b-bebb-c213b5ec9253 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774044639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_dela ys.3774044639 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_same_source.2499965828 |
| Short name | T1737 |
| Test name | |
| Test status | |
| Simulation time | 275966992 ps |
| CPU time | 20.23 seconds |
| Started | May 30 03:49:01 PM PDT 24 |
| Finished | May 30 03:49:23 PM PDT 24 |
| Peak memory | 573040 kb |
| Host | smart-de9f551f-7b0f-4814-acf9-a3a7c1971307 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499965828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.2499965828 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke.3115816619 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 215044158 ps |
| CPU time | 8.97 seconds |
| Started | May 30 03:48:55 PM PDT 24 |
| Finished | May 30 03:49:06 PM PDT 24 |
| Peak memory | 564836 kb |
| Host | smart-26cbaf53-9294-42cb-bb02-365d7b3fa317 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115816619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.3115816619 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_large_delays.581326550 |
| Short name | T2634 |
| Test name | |
| Test status | |
| Simulation time | 8656518249 ps |
| CPU time | 83.83 seconds |
| Started | May 30 03:48:57 PM PDT 24 |
| Finished | May 30 03:50:23 PM PDT 24 |
| Peak memory | 564928 kb |
| Host | smart-4dee45c9-6065-4740-bca9-a594df5a3492 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581326550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.581326550 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.1977212157 |
| Short name | T2710 |
| Test name | |
| Test status | |
| Simulation time | 4874117288 ps |
| CPU time | 76.84 seconds |
| Started | May 30 03:48:59 PM PDT 24 |
| Finished | May 30 03:50:18 PM PDT 24 |
| Peak memory | 564936 kb |
| Host | smart-72d6e0a1-ad98-4e30-bcfd-c4190cc890e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977212157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.1977212157 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_zero_delays.748171774 |
| Short name | T1342 |
| Test name | |
| Test status | |
| Simulation time | 45010644 ps |
| CPU time | 6.1 seconds |
| Started | May 30 03:48:49 PM PDT 24 |
| Finished | May 30 03:48:57 PM PDT 24 |
| Peak memory | 564764 kb |
| Host | smart-f5dd9aea-c5a6-428e-8e82-2fad3347774b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748171774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays. 748171774 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all.2473916295 |
| Short name | T2085 |
| Test name | |
| Test status | |
| Simulation time | 4381979083 ps |
| CPU time | 160.02 seconds |
| Started | May 30 03:48:58 PM PDT 24 |
| Finished | May 30 03:51:40 PM PDT 24 |
| Peak memory | 573304 kb |
| Host | smart-a688866f-7a1a-4f54-a992-b63a3329415b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473916295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.2473916295 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.4205150022 |
| Short name | T2220 |
| Test name | |
| Test status | |
| Simulation time | 364639948 ps |
| CPU time | 33.68 seconds |
| Started | May 30 03:48:52 PM PDT 24 |
| Finished | May 30 03:49:28 PM PDT 24 |
| Peak memory | 573052 kb |
| Host | smart-40ed2379-811a-4385-91f4-d48b9206dbb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205150022 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.4205150022 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.1120481297 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 155592907 ps |
| CPU time | 90.14 seconds |
| Started | May 30 03:48:59 PM PDT 24 |
| Finished | May 30 03:50:31 PM PDT 24 |
| Peak memory | 573044 kb |
| Host | smart-7a11c1b9-6a52-4b55-b4a3-e4367d3fb944 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120481297 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all _with_reset_error.1120481297 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.219136568 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 304197534 ps |
| CPU time | 32.18 seconds |
| Started | May 30 03:48:57 PM PDT 24 |
| Finished | May 30 03:49:30 PM PDT 24 |
| Peak memory | 573044 kb |
| Host | smart-354e8c73-fc5f-411e-8324-86604c0f3732 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219136568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.219136568 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device.2242488997 |
| Short name | T2510 |
| Test name | |
| Test status | |
| Simulation time | 1175843040 ps |
| CPU time | 55.4 seconds |
| Started | May 30 03:58:38 PM PDT 24 |
| Finished | May 30 03:59:35 PM PDT 24 |
| Peak memory | 573064 kb |
| Host | smart-fa0aa9eb-be0b-4425-8f65-4ccdbb37d948 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242488997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device .2242488997 |
| Directory | /workspace/80.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.3317408180 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 67321783900 ps |
| CPU time | 1261.27 seconds |
| Started | May 30 03:58:43 PM PDT 24 |
| Finished | May 30 04:19:45 PM PDT 24 |
| Peak memory | 573292 kb |
| Host | smart-3e2285cc-9880-4816-82ac-d7785412c159 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317408180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_ device_slow_rsp.3317408180 |
| Directory | /workspace/80.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.3055881694 |
| Short name | T1604 |
| Test name | |
| Test status | |
| Simulation time | 1078474052 ps |
| CPU time | 45.33 seconds |
| Started | May 30 03:58:43 PM PDT 24 |
| Finished | May 30 03:59:29 PM PDT 24 |
| Peak memory | 572956 kb |
| Host | smart-e03b3f00-33e3-4e4b-b7db-50f25e95ed7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055881694 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_and_unmapped_add r.3055881694 |
| Directory | /workspace/80.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_random.2865368818 |
| Short name | T2376 |
| Test name | |
| Test status | |
| Simulation time | 85557978 ps |
| CPU time | 10.6 seconds |
| Started | May 30 03:58:39 PM PDT 24 |
| Finished | May 30 03:58:51 PM PDT 24 |
| Peak memory | 572800 kb |
| Host | smart-ba9aaf87-dc67-431c-8523-d52be1904f6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865368818 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_random.2865368818 |
| Directory | /workspace/80.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random.3388065497 |
| Short name | T1939 |
| Test name | |
| Test status | |
| Simulation time | 2474286608 ps |
| CPU time | 87.58 seconds |
| Started | May 30 03:58:38 PM PDT 24 |
| Finished | May 30 04:00:07 PM PDT 24 |
| Peak memory | 573104 kb |
| Host | smart-6c227740-48fc-4ee3-8427-7793b5a6c150 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388065497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random.3388065497 |
| Directory | /workspace/80.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_large_delays.510722116 |
| Short name | T1672 |
| Test name | |
| Test status | |
| Simulation time | 104520733441 ps |
| CPU time | 1074.69 seconds |
| Started | May 30 03:58:39 PM PDT 24 |
| Finished | May 30 04:16:35 PM PDT 24 |
| Peak memory | 573160 kb |
| Host | smart-4bcc62cf-69ca-461d-93c3-20be66de07f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510722116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_large_delays.510722116 |
| Directory | /workspace/80.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_slow_rsp.3948359946 |
| Short name | T2760 |
| Test name | |
| Test status | |
| Simulation time | 54575482923 ps |
| CPU time | 1084.11 seconds |
| Started | May 30 03:58:38 PM PDT 24 |
| Finished | May 30 04:16:43 PM PDT 24 |
| Peak memory | 573188 kb |
| Host | smart-a6236a2a-dcc7-4332-a883-b08fc127f343 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948359946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_slow_rsp.3948359946 |
| Directory | /workspace/80.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_zero_delays.2405282207 |
| Short name | T2700 |
| Test name | |
| Test status | |
| Simulation time | 397457712 ps |
| CPU time | 34.8 seconds |
| Started | May 30 03:58:40 PM PDT 24 |
| Finished | May 30 03:59:16 PM PDT 24 |
| Peak memory | 573064 kb |
| Host | smart-ae92d2c9-e39b-4d19-8acf-7c5fd62652fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405282207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_zero_del ays.2405282207 |
| Directory | /workspace/80.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_same_source.4032519773 |
| Short name | T2248 |
| Test name | |
| Test status | |
| Simulation time | 2143045795 ps |
| CPU time | 68.13 seconds |
| Started | May 30 03:58:38 PM PDT 24 |
| Finished | May 30 03:59:48 PM PDT 24 |
| Peak memory | 573056 kb |
| Host | smart-25645d03-b095-4400-a0b2-d73b254e2e43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032519773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_same_source.4032519773 |
| Directory | /workspace/80.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke.3851234181 |
| Short name | T2482 |
| Test name | |
| Test status | |
| Simulation time | 46757295 ps |
| CPU time | 5.79 seconds |
| Started | May 30 03:58:43 PM PDT 24 |
| Finished | May 30 03:58:50 PM PDT 24 |
| Peak memory | 563360 kb |
| Host | smart-1aa6b0a5-038f-4785-927c-81e8121cbc0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851234181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke.3851234181 |
| Directory | /workspace/80.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.3194060839 |
| Short name | T2568 |
| Test name | |
| Test status | |
| Simulation time | 9977317627 ps |
| CPU time | 105.41 seconds |
| Started | May 30 03:58:38 PM PDT 24 |
| Finished | May 30 04:00:24 PM PDT 24 |
| Peak memory | 564944 kb |
| Host | smart-bbbe43c9-7289-4c99-8407-a777f6f73fc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194060839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_large_delays.3194060839 |
| Directory | /workspace/80.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.713574546 |
| Short name | T1772 |
| Test name | |
| Test status | |
| Simulation time | 2680835502 ps |
| CPU time | 40.86 seconds |
| Started | May 30 03:58:39 PM PDT 24 |
| Finished | May 30 03:59:21 PM PDT 24 |
| Peak memory | 564848 kb |
| Host | smart-7ebf149c-937f-4236-afa9-7f833b7f8afd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713574546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_slow_rsp.713574546 |
| Directory | /workspace/80.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.2949006610 |
| Short name | T2425 |
| Test name | |
| Test status | |
| Simulation time | 42924793 ps |
| CPU time | 5.52 seconds |
| Started | May 30 03:58:38 PM PDT 24 |
| Finished | May 30 03:58:44 PM PDT 24 |
| Peak memory | 564760 kb |
| Host | smart-4c36421b-dd0e-460b-9e0a-dbb80d9aed8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949006610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_zero_delay s.2949006610 |
| Directory | /workspace/80.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all.619208747 |
| Short name | T2377 |
| Test name | |
| Test status | |
| Simulation time | 1464892896 ps |
| CPU time | 129.64 seconds |
| Started | May 30 03:58:38 PM PDT 24 |
| Finished | May 30 04:00:49 PM PDT 24 |
| Peak memory | 573168 kb |
| Host | smart-ea48eaef-fced-441e-a2fb-94bb9f266ded |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619208747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all.619208747 |
| Directory | /workspace/80.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.2272209891 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 1184125063 ps |
| CPU time | 93.38 seconds |
| Started | May 30 03:58:39 PM PDT 24 |
| Finished | May 30 04:00:13 PM PDT 24 |
| Peak memory | 572920 kb |
| Host | smart-bafdad11-63b4-44b6-b678-f916e3bffb2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272209891 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_error.2272209891 |
| Directory | /workspace/80.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.1515108902 |
| Short name | T2787 |
| Test name | |
| Test status | |
| Simulation time | 1286314520 ps |
| CPU time | 128.6 seconds |
| Started | May 30 03:58:38 PM PDT 24 |
| Finished | May 30 04:00:48 PM PDT 24 |
| Peak memory | 573148 kb |
| Host | smart-45262f86-c57c-4b75-ac35-9f35b1722592 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515108902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all _with_rand_reset.1515108902 |
| Directory | /workspace/80.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.2714004858 |
| Short name | T2823 |
| Test name | |
| Test status | |
| Simulation time | 922690223 ps |
| CPU time | 215.07 seconds |
| Started | May 30 03:58:40 PM PDT 24 |
| Finished | May 30 04:02:16 PM PDT 24 |
| Peak memory | 573096 kb |
| Host | smart-957e8e72-0be2-4e2d-b006-861fd77aca70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714004858 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_al l_with_reset_error.2714004858 |
| Directory | /workspace/80.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_unmapped_addr.917950899 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 114032369 ps |
| CPU time | 14.85 seconds |
| Started | May 30 03:58:40 PM PDT 24 |
| Finished | May 30 03:58:56 PM PDT 24 |
| Peak memory | 573100 kb |
| Host | smart-2da8927b-ae27-4407-8957-df4d19d485bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917950899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_unmapped_addr.917950899 |
| Directory | /workspace/80.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device.2228201993 |
| Short name | T1626 |
| Test name | |
| Test status | |
| Simulation time | 1351014974 ps |
| CPU time | 48.42 seconds |
| Started | May 30 03:58:49 PM PDT 24 |
| Finished | May 30 03:59:38 PM PDT 24 |
| Peak memory | 573088 kb |
| Host | smart-62a3e288-49ea-4ed7-b5d9-97abc12320ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228201993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device .2228201993 |
| Directory | /workspace/81.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.1554368542 |
| Short name | T2302 |
| Test name | |
| Test status | |
| Simulation time | 122688179255 ps |
| CPU time | 2389.09 seconds |
| Started | May 30 03:58:48 PM PDT 24 |
| Finished | May 30 04:38:38 PM PDT 24 |
| Peak memory | 573396 kb |
| Host | smart-cab7d392-5455-4821-968e-62fe6eb81053 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554368542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_ device_slow_rsp.1554368542 |
| Directory | /workspace/81.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.1266313900 |
| Short name | T2836 |
| Test name | |
| Test status | |
| Simulation time | 258463764 ps |
| CPU time | 26.28 seconds |
| Started | May 30 03:58:51 PM PDT 24 |
| Finished | May 30 03:59:18 PM PDT 24 |
| Peak memory | 572928 kb |
| Host | smart-5babab97-eec8-4156-9008-bbb706d8bdf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266313900 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_and_unmapped_add r.1266313900 |
| Directory | /workspace/81.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_random.2323802964 |
| Short name | T1818 |
| Test name | |
| Test status | |
| Simulation time | 908176663 ps |
| CPU time | 33.4 seconds |
| Started | May 30 03:58:50 PM PDT 24 |
| Finished | May 30 03:59:24 PM PDT 24 |
| Peak memory | 572908 kb |
| Host | smart-01b69df3-e362-4727-8fbe-b101181b95de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323802964 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_random.2323802964 |
| Directory | /workspace/81.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random.2354884631 |
| Short name | T2474 |
| Test name | |
| Test status | |
| Simulation time | 102938206 ps |
| CPU time | 11.45 seconds |
| Started | May 30 03:58:50 PM PDT 24 |
| Finished | May 30 03:59:02 PM PDT 24 |
| Peak memory | 573072 kb |
| Host | smart-beba5bc0-b1f1-4944-9507-c20b1c7ffa29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354884631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random.2354884631 |
| Directory | /workspace/81.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_large_delays.566908120 |
| Short name | T2604 |
| Test name | |
| Test status | |
| Simulation time | 16795974276 ps |
| CPU time | 171.2 seconds |
| Started | May 30 03:58:47 PM PDT 24 |
| Finished | May 30 04:01:40 PM PDT 24 |
| Peak memory | 573108 kb |
| Host | smart-f08d3b14-2d34-452b-926e-8b4a4c527694 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566908120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_large_delays.566908120 |
| Directory | /workspace/81.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.2095034476 |
| Short name | T1671 |
| Test name | |
| Test status | |
| Simulation time | 34866686946 ps |
| CPU time | 633.6 seconds |
| Started | May 30 03:58:50 PM PDT 24 |
| Finished | May 30 04:09:24 PM PDT 24 |
| Peak memory | 573156 kb |
| Host | smart-883cea9b-8722-4b7e-932f-1bb54e24975e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095034476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_slow_rsp.2095034476 |
| Directory | /workspace/81.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_zero_delays.2295773765 |
| Short name | T2818 |
| Test name | |
| Test status | |
| Simulation time | 156629478 ps |
| CPU time | 14.38 seconds |
| Started | May 30 03:58:48 PM PDT 24 |
| Finished | May 30 03:59:03 PM PDT 24 |
| Peak memory | 572940 kb |
| Host | smart-17a2320d-8ac4-426e-b552-3a600680038a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295773765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_zero_del ays.2295773765 |
| Directory | /workspace/81.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_same_source.60399885 |
| Short name | T2060 |
| Test name | |
| Test status | |
| Simulation time | 1459230456 ps |
| CPU time | 45.28 seconds |
| Started | May 30 03:58:50 PM PDT 24 |
| Finished | May 30 03:59:36 PM PDT 24 |
| Peak memory | 573076 kb |
| Host | smart-f84ac39d-9f07-49a8-a6e6-a8a6bbd11734 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60399885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_same_source.60399885 |
| Directory | /workspace/81.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke.2892011848 |
| Short name | T2660 |
| Test name | |
| Test status | |
| Simulation time | 199529196 ps |
| CPU time | 9.09 seconds |
| Started | May 30 03:58:39 PM PDT 24 |
| Finished | May 30 03:58:49 PM PDT 24 |
| Peak memory | 564796 kb |
| Host | smart-d8fd6be5-36cb-4169-b213-243376ac460a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892011848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke.2892011848 |
| Directory | /workspace/81.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_large_delays.2659974287 |
| Short name | T2286 |
| Test name | |
| Test status | |
| Simulation time | 10373985889 ps |
| CPU time | 101.45 seconds |
| Started | May 30 03:58:39 PM PDT 24 |
| Finished | May 30 04:00:21 PM PDT 24 |
| Peak memory | 564972 kb |
| Host | smart-420e128d-e6de-4db3-9cf9-de67f8af1dea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659974287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_large_delays.2659974287 |
| Directory | /workspace/81.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.2171903486 |
| Short name | T2202 |
| Test name | |
| Test status | |
| Simulation time | 6232274011 ps |
| CPU time | 103.1 seconds |
| Started | May 30 03:58:47 PM PDT 24 |
| Finished | May 30 04:00:32 PM PDT 24 |
| Peak memory | 564896 kb |
| Host | smart-5d52a771-b837-42a8-82a9-e7e9fc01ac08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171903486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_slow_rsp.2171903486 |
| Directory | /workspace/81.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_zero_delays.4104485746 |
| Short name | T2369 |
| Test name | |
| Test status | |
| Simulation time | 49265602 ps |
| CPU time | 6.51 seconds |
| Started | May 30 03:58:38 PM PDT 24 |
| Finished | May 30 03:58:46 PM PDT 24 |
| Peak memory | 563372 kb |
| Host | smart-14935d5f-b8d7-4bb8-8704-e81626550d29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104485746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_zero_delay s.4104485746 |
| Directory | /workspace/81.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all.1770516717 |
| Short name | T2258 |
| Test name | |
| Test status | |
| Simulation time | 9081753131 ps |
| CPU time | 346.86 seconds |
| Started | May 30 03:58:47 PM PDT 24 |
| Finished | May 30 04:04:35 PM PDT 24 |
| Peak memory | 573268 kb |
| Host | smart-ca2181ed-5c82-481d-a1db-759efc458311 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770516717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all.1770516717 |
| Directory | /workspace/81.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.4130884230 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 9967487478 ps |
| CPU time | 373.31 seconds |
| Started | May 30 03:58:47 PM PDT 24 |
| Finished | May 30 04:05:02 PM PDT 24 |
| Peak memory | 575212 kb |
| Host | smart-3cd17bf3-807a-4340-b0f4-0eb83e9ea104 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130884230 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_error.4130884230 |
| Directory | /workspace/81.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.915174871 |
| Short name | T2279 |
| Test name | |
| Test status | |
| Simulation time | 6332522400 ps |
| CPU time | 728.19 seconds |
| Started | May 30 03:58:51 PM PDT 24 |
| Finished | May 30 04:11:00 PM PDT 24 |
| Peak memory | 573260 kb |
| Host | smart-7469cdfb-a886-4e0c-9b7f-b006b4d1a55c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915174871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_ with_rand_reset.915174871 |
| Directory | /workspace/81.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.2438403202 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 5793206393 ps |
| CPU time | 547.99 seconds |
| Started | May 30 03:58:48 PM PDT 24 |
| Finished | May 30 04:07:57 PM PDT 24 |
| Peak memory | 573152 kb |
| Host | smart-db1b8e08-3295-41c6-8db3-812d84ecf040 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438403202 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_al l_with_reset_error.2438403202 |
| Directory | /workspace/81.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_unmapped_addr.68056627 |
| Short name | T2410 |
| Test name | |
| Test status | |
| Simulation time | 269664029 ps |
| CPU time | 30 seconds |
| Started | May 30 03:58:49 PM PDT 24 |
| Finished | May 30 03:59:20 PM PDT 24 |
| Peak memory | 573100 kb |
| Host | smart-3c0450af-5e3c-4ddf-a7a6-a5e845494b88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68056627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_unmapped_addr.68056627 |
| Directory | /workspace/81.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device.1195210795 |
| Short name | T2549 |
| Test name | |
| Test status | |
| Simulation time | 3234090362 ps |
| CPU time | 136.74 seconds |
| Started | May 30 03:59:08 PM PDT 24 |
| Finished | May 30 04:01:25 PM PDT 24 |
| Peak memory | 573152 kb |
| Host | smart-e3ba33af-5de2-4064-abc2-95609ba35764 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195210795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device .1195210795 |
| Directory | /workspace/82.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.822959081 |
| Short name | T2659 |
| Test name | |
| Test status | |
| Simulation time | 74561008783 ps |
| CPU time | 1414.33 seconds |
| Started | May 30 03:58:58 PM PDT 24 |
| Finished | May 30 04:22:35 PM PDT 24 |
| Peak memory | 573240 kb |
| Host | smart-83a38fc9-3953-4512-b584-5bac626df34c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822959081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_d evice_slow_rsp.822959081 |
| Directory | /workspace/82.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.508781308 |
| Short name | T1514 |
| Test name | |
| Test status | |
| Simulation time | 1164678789 ps |
| CPU time | 48.19 seconds |
| Started | May 30 03:59:00 PM PDT 24 |
| Finished | May 30 03:59:49 PM PDT 24 |
| Peak memory | 572920 kb |
| Host | smart-52b5d95c-92ff-44f8-9f95-fa57d9b63352 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508781308 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_and_unmapped_addr .508781308 |
| Directory | /workspace/82.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_random.2474776234 |
| Short name | T1746 |
| Test name | |
| Test status | |
| Simulation time | 462873713 ps |
| CPU time | 37.44 seconds |
| Started | May 30 03:59:08 PM PDT 24 |
| Finished | May 30 03:59:46 PM PDT 24 |
| Peak memory | 572944 kb |
| Host | smart-fa797013-bc5c-4b1a-ab4a-64cd13435e4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474776234 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_random.2474776234 |
| Directory | /workspace/82.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random.1049788043 |
| Short name | T2278 |
| Test name | |
| Test status | |
| Simulation time | 2279590567 ps |
| CPU time | 93.05 seconds |
| Started | May 30 03:58:48 PM PDT 24 |
| Finished | May 30 04:00:22 PM PDT 24 |
| Peak memory | 573100 kb |
| Host | smart-6efb838c-5b45-4421-98f7-4d4dad56fc9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049788043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random.1049788043 |
| Directory | /workspace/82.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_large_delays.1309703106 |
| Short name | T1895 |
| Test name | |
| Test status | |
| Simulation time | 21595994716 ps |
| CPU time | 266.04 seconds |
| Started | May 30 03:58:59 PM PDT 24 |
| Finished | May 30 04:03:26 PM PDT 24 |
| Peak memory | 573208 kb |
| Host | smart-a78fcabf-de46-4c9a-87cc-184def57bd41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309703106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_large_delays.1309703106 |
| Directory | /workspace/82.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_slow_rsp.349461049 |
| Short name | T2334 |
| Test name | |
| Test status | |
| Simulation time | 10822808724 ps |
| CPU time | 180.8 seconds |
| Started | May 30 03:58:58 PM PDT 24 |
| Finished | May 30 04:02:00 PM PDT 24 |
| Peak memory | 573136 kb |
| Host | smart-47a1e1a6-6492-4df6-bad1-62f57063cbe8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349461049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_slow_rsp.349461049 |
| Directory | /workspace/82.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.3666616193 |
| Short name | T2754 |
| Test name | |
| Test status | |
| Simulation time | 148739763 ps |
| CPU time | 13.88 seconds |
| Started | May 30 03:58:59 PM PDT 24 |
| Finished | May 30 03:59:14 PM PDT 24 |
| Peak memory | 572584 kb |
| Host | smart-f8c406a4-fe6a-4fd5-9941-b594ad18d533 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666616193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_zero_del ays.3666616193 |
| Directory | /workspace/82.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_same_source.906807738 |
| Short name | T1721 |
| Test name | |
| Test status | |
| Simulation time | 268630241 ps |
| CPU time | 20.62 seconds |
| Started | May 30 03:58:59 PM PDT 24 |
| Finished | May 30 03:59:21 PM PDT 24 |
| Peak memory | 572908 kb |
| Host | smart-c95da49a-8ae4-4d72-a1a1-775d9ec36c51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906807738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_same_source.906807738 |
| Directory | /workspace/82.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke.130036821 |
| Short name | T1332 |
| Test name | |
| Test status | |
| Simulation time | 50997670 ps |
| CPU time | 6.47 seconds |
| Started | May 30 03:58:50 PM PDT 24 |
| Finished | May 30 03:58:58 PM PDT 24 |
| Peak memory | 563416 kb |
| Host | smart-eba26d69-6f43-412a-a666-1d2ef93299b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130036821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke.130036821 |
| Directory | /workspace/82.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_large_delays.4149512480 |
| Short name | T2411 |
| Test name | |
| Test status | |
| Simulation time | 9512519837 ps |
| CPU time | 97.98 seconds |
| Started | May 30 03:58:48 PM PDT 24 |
| Finished | May 30 04:00:27 PM PDT 24 |
| Peak memory | 564904 kb |
| Host | smart-e7fad7ce-c58b-448b-ac29-ab9b583ad68d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149512480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_large_delays.4149512480 |
| Directory | /workspace/82.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.2206984037 |
| Short name | T2758 |
| Test name | |
| Test status | |
| Simulation time | 4284447795 ps |
| CPU time | 72.32 seconds |
| Started | May 30 03:58:47 PM PDT 24 |
| Finished | May 30 04:00:01 PM PDT 24 |
| Peak memory | 564876 kb |
| Host | smart-7a7daa2b-a67b-44c0-8466-f1ca12d3233f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206984037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_slow_rsp.2206984037 |
| Directory | /workspace/82.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_zero_delays.1207513307 |
| Short name | T1761 |
| Test name | |
| Test status | |
| Simulation time | 50132643 ps |
| CPU time | 6.36 seconds |
| Started | May 30 03:58:51 PM PDT 24 |
| Finished | May 30 03:58:59 PM PDT 24 |
| Peak memory | 564776 kb |
| Host | smart-3756c9be-51ef-4d72-836b-ba50c5f71e27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207513307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_zero_delay s.1207513307 |
| Directory | /workspace/82.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all.1065593161 |
| Short name | T2233 |
| Test name | |
| Test status | |
| Simulation time | 18895375085 ps |
| CPU time | 770.45 seconds |
| Started | May 30 03:59:00 PM PDT 24 |
| Finished | May 30 04:11:52 PM PDT 24 |
| Peak memory | 573276 kb |
| Host | smart-f3ddbb7e-63f6-4b93-9aa9-6fe8cae03f37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065593161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all.1065593161 |
| Directory | /workspace/82.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.4206494645 |
| Short name | T1400 |
| Test name | |
| Test status | |
| Simulation time | 10091384841 ps |
| CPU time | 365.07 seconds |
| Started | May 30 03:58:59 PM PDT 24 |
| Finished | May 30 04:05:06 PM PDT 24 |
| Peak memory | 573204 kb |
| Host | smart-88aeb282-8e26-402a-95aa-7d8c74597be7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206494645 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_error.4206494645 |
| Directory | /workspace/82.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.1609956961 |
| Short name | T1785 |
| Test name | |
| Test status | |
| Simulation time | 6257121061 ps |
| CPU time | 516.38 seconds |
| Started | May 30 03:59:09 PM PDT 24 |
| Finished | May 30 04:07:46 PM PDT 24 |
| Peak memory | 576920 kb |
| Host | smart-9a780c7b-9e6c-43bd-a021-7b38786c2508 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609956961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all _with_rand_reset.1609956961 |
| Directory | /workspace/82.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.898673405 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 1033206162 ps |
| CPU time | 147.74 seconds |
| Started | May 30 03:58:59 PM PDT 24 |
| Finished | May 30 04:01:28 PM PDT 24 |
| Peak memory | 578980 kb |
| Host | smart-4dcb7e01-eac3-4a5b-99cd-ed6b844401f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898673405 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all _with_reset_error.898673405 |
| Directory | /workspace/82.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_unmapped_addr.2436422379 |
| Short name | T1644 |
| Test name | |
| Test status | |
| Simulation time | 83859459 ps |
| CPU time | 12.17 seconds |
| Started | May 30 03:59:08 PM PDT 24 |
| Finished | May 30 03:59:21 PM PDT 24 |
| Peak memory | 573104 kb |
| Host | smart-8ff97bbb-f936-4838-a3c0-0c63942e1289 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436422379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_unmapped_addr.2436422379 |
| Directory | /workspace/82.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device.2072009657 |
| Short name | T1544 |
| Test name | |
| Test status | |
| Simulation time | 2230735135 ps |
| CPU time | 88.61 seconds |
| Started | May 30 03:59:09 PM PDT 24 |
| Finished | May 30 04:00:38 PM PDT 24 |
| Peak memory | 573140 kb |
| Host | smart-35b5b634-59e7-46dc-9252-a127d156e91b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072009657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device .2072009657 |
| Directory | /workspace/83.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.4079907453 |
| Short name | T2534 |
| Test name | |
| Test status | |
| Simulation time | 123481438 ps |
| CPU time | 15.31 seconds |
| Started | May 30 03:59:11 PM PDT 24 |
| Finished | May 30 03:59:27 PM PDT 24 |
| Peak memory | 572932 kb |
| Host | smart-83743ff7-1d65-42e7-ab3b-0d32a24d85bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079907453 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_and_unmapped_add r.4079907453 |
| Directory | /workspace/83.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_random.3300825148 |
| Short name | T1429 |
| Test name | |
| Test status | |
| Simulation time | 1876817486 ps |
| CPU time | 61.68 seconds |
| Started | May 30 03:59:09 PM PDT 24 |
| Finished | May 30 04:00:12 PM PDT 24 |
| Peak memory | 572944 kb |
| Host | smart-eecdf651-4f39-4b2f-b234-c92f6370d174 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300825148 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_random.3300825148 |
| Directory | /workspace/83.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random.1231125930 |
| Short name | T2746 |
| Test name | |
| Test status | |
| Simulation time | 140259703 ps |
| CPU time | 8.08 seconds |
| Started | May 30 03:59:03 PM PDT 24 |
| Finished | May 30 03:59:12 PM PDT 24 |
| Peak memory | 563392 kb |
| Host | smart-08f1414c-6902-43d9-9cee-07bc8e75ca14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231125930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random.1231125930 |
| Directory | /workspace/83.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_large_delays.1041837263 |
| Short name | T2736 |
| Test name | |
| Test status | |
| Simulation time | 20870632236 ps |
| CPU time | 243.24 seconds |
| Started | May 30 03:59:17 PM PDT 24 |
| Finished | May 30 04:03:22 PM PDT 24 |
| Peak memory | 573216 kb |
| Host | smart-96c86de9-fd16-4baa-b56a-4b01eeea3bc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041837263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_large_delays.1041837263 |
| Directory | /workspace/83.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_slow_rsp.1391300648 |
| Short name | T2477 |
| Test name | |
| Test status | |
| Simulation time | 14607401506 ps |
| CPU time | 259.11 seconds |
| Started | May 30 03:59:10 PM PDT 24 |
| Finished | May 30 04:03:30 PM PDT 24 |
| Peak memory | 573180 kb |
| Host | smart-c900558b-4530-4fb6-acf4-edeffbad5747 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391300648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_slow_rsp.1391300648 |
| Directory | /workspace/83.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.2603591237 |
| Short name | T1543 |
| Test name | |
| Test status | |
| Simulation time | 209230660 ps |
| CPU time | 23.53 seconds |
| Started | May 30 03:59:10 PM PDT 24 |
| Finished | May 30 03:59:34 PM PDT 24 |
| Peak memory | 573032 kb |
| Host | smart-edd68f38-a58e-43c1-b3f7-42a7d859c972 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603591237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_zero_del ays.2603591237 |
| Directory | /workspace/83.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_same_source.536529499 |
| Short name | T2503 |
| Test name | |
| Test status | |
| Simulation time | 1561711699 ps |
| CPU time | 44.64 seconds |
| Started | May 30 03:59:11 PM PDT 24 |
| Finished | May 30 03:59:57 PM PDT 24 |
| Peak memory | 572964 kb |
| Host | smart-7a10b107-badc-4a8d-a065-7331fc0e849d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536529499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_same_source.536529499 |
| Directory | /workspace/83.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke.2717662721 |
| Short name | T2187 |
| Test name | |
| Test status | |
| Simulation time | 208860196 ps |
| CPU time | 9.43 seconds |
| Started | May 30 03:59:04 PM PDT 24 |
| Finished | May 30 03:59:14 PM PDT 24 |
| Peak memory | 564856 kb |
| Host | smart-760a3e12-5ff3-486e-9a86-2e65f2a03048 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717662721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke.2717662721 |
| Directory | /workspace/83.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.4242752509 |
| Short name | T1548 |
| Test name | |
| Test status | |
| Simulation time | 7411539815 ps |
| CPU time | 80.84 seconds |
| Started | May 30 03:59:00 PM PDT 24 |
| Finished | May 30 04:00:22 PM PDT 24 |
| Peak memory | 563476 kb |
| Host | smart-2ba68a16-5862-4b58-93ae-62f48f4433c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242752509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_large_delays.4242752509 |
| Directory | /workspace/83.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.1728847188 |
| Short name | T1885 |
| Test name | |
| Test status | |
| Simulation time | 3858493558 ps |
| CPU time | 62.06 seconds |
| Started | May 30 03:59:00 PM PDT 24 |
| Finished | May 30 04:00:03 PM PDT 24 |
| Peak memory | 564856 kb |
| Host | smart-4ff5f52b-9d90-4178-a1b2-b58809c4f465 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728847188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_slow_rsp.1728847188 |
| Directory | /workspace/83.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_zero_delays.1974874194 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 46010550 ps |
| CPU time | 6.49 seconds |
| Started | May 30 03:59:03 PM PDT 24 |
| Finished | May 30 03:59:11 PM PDT 24 |
| Peak memory | 564824 kb |
| Host | smart-e8ecc881-b243-4c0d-aaa6-7cbe29068974 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974874194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_zero_delay s.1974874194 |
| Directory | /workspace/83.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all.2573527972 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 3232404705 ps |
| CPU time | 123.23 seconds |
| Started | May 30 03:59:11 PM PDT 24 |
| Finished | May 30 04:01:16 PM PDT 24 |
| Peak memory | 573164 kb |
| Host | smart-cc951eff-f952-4af3-9096-7a39192a10c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573527972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all.2573527972 |
| Directory | /workspace/83.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_error.328843663 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 19252937132 ps |
| CPU time | 793.53 seconds |
| Started | May 30 03:59:10 PM PDT 24 |
| Finished | May 30 04:12:25 PM PDT 24 |
| Peak memory | 573172 kb |
| Host | smart-20730521-c919-4cfb-8f88-310e4b88bb10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328843663 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_error.328843663 |
| Directory | /workspace/83.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.955663156 |
| Short name | T2741 |
| Test name | |
| Test status | |
| Simulation time | 5154820595 ps |
| CPU time | 449.84 seconds |
| Started | May 30 03:59:09 PM PDT 24 |
| Finished | May 30 04:06:40 PM PDT 24 |
| Peak memory | 573268 kb |
| Host | smart-748ab527-e0c7-4cac-90e3-67a9fe2f7e7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955663156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_ with_rand_reset.955663156 |
| Directory | /workspace/83.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.2419694978 |
| Short name | T1726 |
| Test name | |
| Test status | |
| Simulation time | 386322013 ps |
| CPU time | 118.44 seconds |
| Started | May 30 03:59:09 PM PDT 24 |
| Finished | May 30 04:01:08 PM PDT 24 |
| Peak memory | 573084 kb |
| Host | smart-baf1122f-bade-4a27-8d97-5dfdc4b8e5cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419694978 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_al l_with_reset_error.2419694978 |
| Directory | /workspace/83.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_unmapped_addr.2941464297 |
| Short name | T1800 |
| Test name | |
| Test status | |
| Simulation time | 1315434522 ps |
| CPU time | 53.62 seconds |
| Started | May 30 03:59:10 PM PDT 24 |
| Finished | May 30 04:00:05 PM PDT 24 |
| Peak memory | 572984 kb |
| Host | smart-8fb388f8-d0d5-4882-9536-d02c244a450a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941464297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_unmapped_addr.2941464297 |
| Directory | /workspace/83.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device.1656182904 |
| Short name | T1745 |
| Test name | |
| Test status | |
| Simulation time | 3713888629 ps |
| CPU time | 161.26 seconds |
| Started | May 30 03:59:21 PM PDT 24 |
| Finished | May 30 04:02:03 PM PDT 24 |
| Peak memory | 573108 kb |
| Host | smart-1e18fb6d-5b17-488a-823e-7247a721abbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656182904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device .1656182904 |
| Directory | /workspace/84.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.2858167592 |
| Short name | T1691 |
| Test name | |
| Test status | |
| Simulation time | 10309609943 ps |
| CPU time | 176.5 seconds |
| Started | May 30 03:59:22 PM PDT 24 |
| Finished | May 30 04:02:20 PM PDT 24 |
| Peak memory | 565024 kb |
| Host | smart-25aa2fe9-6361-49b6-b6be-ea473ca01586 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858167592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_ device_slow_rsp.2858167592 |
| Directory | /workspace/84.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.1318686781 |
| Short name | T2295 |
| Test name | |
| Test status | |
| Simulation time | 249927283 ps |
| CPU time | 27.39 seconds |
| Started | May 30 03:59:22 PM PDT 24 |
| Finished | May 30 03:59:51 PM PDT 24 |
| Peak memory | 572904 kb |
| Host | smart-011507bc-50ff-4f29-94b1-becd4e8e365f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318686781 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_and_unmapped_add r.1318686781 |
| Directory | /workspace/84.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_random.910958817 |
| Short name | T1637 |
| Test name | |
| Test status | |
| Simulation time | 585350145 ps |
| CPU time | 53.44 seconds |
| Started | May 30 03:59:20 PM PDT 24 |
| Finished | May 30 04:00:14 PM PDT 24 |
| Peak memory | 573964 kb |
| Host | smart-e22da089-86f3-4375-8657-cdf641b2052b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910958817 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_random.910958817 |
| Directory | /workspace/84.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random.3519253341 |
| Short name | T1834 |
| Test name | |
| Test status | |
| Simulation time | 89011868 ps |
| CPU time | 7.28 seconds |
| Started | May 30 03:59:11 PM PDT 24 |
| Finished | May 30 03:59:20 PM PDT 24 |
| Peak memory | 564792 kb |
| Host | smart-f687ccf3-809b-4b63-9bef-51a02c150bc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519253341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random.3519253341 |
| Directory | /workspace/84.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_large_delays.3719897044 |
| Short name | T1591 |
| Test name | |
| Test status | |
| Simulation time | 75168406894 ps |
| CPU time | 911.54 seconds |
| Started | May 30 03:59:17 PM PDT 24 |
| Finished | May 30 04:14:30 PM PDT 24 |
| Peak memory | 573104 kb |
| Host | smart-061cf79b-b1f8-4e84-b9bc-39241c4c71e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719897044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_large_delays.3719897044 |
| Directory | /workspace/84.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_slow_rsp.2952641744 |
| Short name | T2333 |
| Test name | |
| Test status | |
| Simulation time | 62448743084 ps |
| CPU time | 1195.86 seconds |
| Started | May 30 03:59:12 PM PDT 24 |
| Finished | May 30 04:19:09 PM PDT 24 |
| Peak memory | 573148 kb |
| Host | smart-6723e8af-0e9c-4d3d-8a77-b9ed296184dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952641744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_slow_rsp.2952641744 |
| Directory | /workspace/84.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_zero_delays.3776027978 |
| Short name | T2857 |
| Test name | |
| Test status | |
| Simulation time | 334063803 ps |
| CPU time | 33.76 seconds |
| Started | May 30 03:59:09 PM PDT 24 |
| Finished | May 30 03:59:44 PM PDT 24 |
| Peak memory | 573020 kb |
| Host | smart-d20f7181-dcf6-4c23-b069-911af6432feb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776027978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_zero_del ays.3776027978 |
| Directory | /workspace/84.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_same_source.4026675003 |
| Short name | T1762 |
| Test name | |
| Test status | |
| Simulation time | 1638768077 ps |
| CPU time | 47.85 seconds |
| Started | May 30 03:59:24 PM PDT 24 |
| Finished | May 30 04:00:13 PM PDT 24 |
| Peak memory | 572948 kb |
| Host | smart-1b7f1310-416a-45b9-85a1-3a4125ba6ac2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026675003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_same_source.4026675003 |
| Directory | /workspace/84.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke.2883548947 |
| Short name | T2382 |
| Test name | |
| Test status | |
| Simulation time | 161629184 ps |
| CPU time | 7.39 seconds |
| Started | May 30 03:59:12 PM PDT 24 |
| Finished | May 30 03:59:20 PM PDT 24 |
| Peak memory | 563344 kb |
| Host | smart-63c81e83-1e51-4278-be35-43f6c66203ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883548947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke.2883548947 |
| Directory | /workspace/84.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.2010926728 |
| Short name | T2806 |
| Test name | |
| Test status | |
| Simulation time | 6701017302 ps |
| CPU time | 71.21 seconds |
| Started | May 30 03:59:18 PM PDT 24 |
| Finished | May 30 04:00:30 PM PDT 24 |
| Peak memory | 564952 kb |
| Host | smart-c6626756-2939-4101-86e5-3fb0c1ade0ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010926728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_large_delays.2010926728 |
| Directory | /workspace/84.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.4084096567 |
| Short name | T2809 |
| Test name | |
| Test status | |
| Simulation time | 6245256750 ps |
| CPU time | 106.48 seconds |
| Started | May 30 03:59:11 PM PDT 24 |
| Finished | May 30 04:00:59 PM PDT 24 |
| Peak memory | 564916 kb |
| Host | smart-8a5c5dbc-ecd7-4ca2-b704-453abe59371c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084096567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_slow_rsp.4084096567 |
| Directory | /workspace/84.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_zero_delays.55305047 |
| Short name | T2445 |
| Test name | |
| Test status | |
| Simulation time | 46227082 ps |
| CPU time | 6.14 seconds |
| Started | May 30 03:59:11 PM PDT 24 |
| Finished | May 30 03:59:19 PM PDT 24 |
| Peak memory | 564780 kb |
| Host | smart-cd6ec68c-23cf-4329-bfd4-00141284a69b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55305047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_zero_delays.55305047 |
| Directory | /workspace/84.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all.2329467603 |
| Short name | T1790 |
| Test name | |
| Test status | |
| Simulation time | 2587108421 ps |
| CPU time | 205 seconds |
| Started | May 30 03:59:25 PM PDT 24 |
| Finished | May 30 04:02:51 PM PDT 24 |
| Peak memory | 573148 kb |
| Host | smart-b751c4b7-8bc5-4d78-9cf4-6119a087fb7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329467603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all.2329467603 |
| Directory | /workspace/84.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.3856272560 |
| Short name | T2532 |
| Test name | |
| Test status | |
| Simulation time | 8598669621 ps |
| CPU time | 304.2 seconds |
| Started | May 30 03:59:21 PM PDT 24 |
| Finished | May 30 04:04:27 PM PDT 24 |
| Peak memory | 573144 kb |
| Host | smart-41de78a8-2cc2-490d-9a5a-a91004c1f7a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856272560 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_error.3856272560 |
| Directory | /workspace/84.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.3549391520 |
| Short name | T2755 |
| Test name | |
| Test status | |
| Simulation time | 3788961147 ps |
| CPU time | 243.82 seconds |
| Started | May 30 03:59:21 PM PDT 24 |
| Finished | May 30 04:03:26 PM PDT 24 |
| Peak memory | 573212 kb |
| Host | smart-01ccc0e2-c8c7-449b-819c-96463b379874 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549391520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all _with_rand_reset.3549391520 |
| Directory | /workspace/84.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_unmapped_addr.1130137428 |
| Short name | T1699 |
| Test name | |
| Test status | |
| Simulation time | 265513893 ps |
| CPU time | 15.37 seconds |
| Started | May 30 03:59:19 PM PDT 24 |
| Finished | May 30 03:59:36 PM PDT 24 |
| Peak memory | 573072 kb |
| Host | smart-ab4a1bfb-a425-4dac-876d-71d383d9c6c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130137428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_unmapped_addr.1130137428 |
| Directory | /workspace/84.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device.1043746467 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 339179904 ps |
| CPU time | 16 seconds |
| Started | May 30 03:59:40 PM PDT 24 |
| Finished | May 30 03:59:57 PM PDT 24 |
| Peak memory | 564708 kb |
| Host | smart-ff9cc7ce-c602-4ffd-9584-7a00859c0533 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043746467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device .1043746467 |
| Directory | /workspace/85.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.1969311574 |
| Short name | T2115 |
| Test name | |
| Test status | |
| Simulation time | 10991662736 ps |
| CPU time | 196.15 seconds |
| Started | May 30 03:59:31 PM PDT 24 |
| Finished | May 30 04:02:48 PM PDT 24 |
| Peak memory | 573260 kb |
| Host | smart-71a55ee1-eba7-41d0-8714-c62aafc71181 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969311574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_ device_slow_rsp.1969311574 |
| Directory | /workspace/85.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.1231465658 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 124235477 ps |
| CPU time | 7.9 seconds |
| Started | May 30 03:59:37 PM PDT 24 |
| Finished | May 30 03:59:45 PM PDT 24 |
| Peak memory | 564716 kb |
| Host | smart-4089425e-a0c0-4658-b823-334e2367c5c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231465658 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_and_unmapped_add r.1231465658 |
| Directory | /workspace/85.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_random.678535231 |
| Short name | T2594 |
| Test name | |
| Test status | |
| Simulation time | 712696700 ps |
| CPU time | 26.21 seconds |
| Started | May 30 03:59:32 PM PDT 24 |
| Finished | May 30 03:59:59 PM PDT 24 |
| Peak memory | 572880 kb |
| Host | smart-c1a9cb77-9a24-4d02-98a8-ce5a02f7ad2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678535231 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_random.678535231 |
| Directory | /workspace/85.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random.1930573092 |
| Short name | T1814 |
| Test name | |
| Test status | |
| Simulation time | 100071644 ps |
| CPU time | 7.09 seconds |
| Started | May 30 03:59:21 PM PDT 24 |
| Finished | May 30 03:59:29 PM PDT 24 |
| Peak memory | 564832 kb |
| Host | smart-9360c9ab-7a81-4f23-8128-5dc98b205105 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930573092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random.1930573092 |
| Directory | /workspace/85.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_large_delays.391763521 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 87242409047 ps |
| CPU time | 1036.27 seconds |
| Started | May 30 03:59:21 PM PDT 24 |
| Finished | May 30 04:16:38 PM PDT 24 |
| Peak memory | 573164 kb |
| Host | smart-a1a96094-a3f0-4d03-82a3-575f69edd839 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391763521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_large_delays.391763521 |
| Directory | /workspace/85.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_slow_rsp.1162294694 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 55656304465 ps |
| CPU time | 1003.3 seconds |
| Started | May 30 03:59:32 PM PDT 24 |
| Finished | May 30 04:16:16 PM PDT 24 |
| Peak memory | 573180 kb |
| Host | smart-19baed52-dfa7-4c7d-b55b-0718c69b093f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162294694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_slow_rsp.1162294694 |
| Directory | /workspace/85.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_zero_delays.127248586 |
| Short name | T2557 |
| Test name | |
| Test status | |
| Simulation time | 256289311 ps |
| CPU time | 23.48 seconds |
| Started | May 30 03:59:20 PM PDT 24 |
| Finished | May 30 03:59:45 PM PDT 24 |
| Peak memory | 572920 kb |
| Host | smart-24b286f8-1e32-44ef-9201-cc8cb4a51984 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127248586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_zero_dela ys.127248586 |
| Directory | /workspace/85.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_same_source.3517915942 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 292498081 ps |
| CPU time | 23.59 seconds |
| Started | May 30 03:59:41 PM PDT 24 |
| Finished | May 30 04:00:05 PM PDT 24 |
| Peak memory | 573012 kb |
| Host | smart-46ce5ba1-d27d-46ce-ad40-52b8becb38ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517915942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_same_source.3517915942 |
| Directory | /workspace/85.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke.1182785823 |
| Short name | T1920 |
| Test name | |
| Test status | |
| Simulation time | 166940946 ps |
| CPU time | 7.71 seconds |
| Started | May 30 03:59:20 PM PDT 24 |
| Finished | May 30 03:59:29 PM PDT 24 |
| Peak memory | 564824 kb |
| Host | smart-a0c37d5b-75ed-4e0d-922b-82ade99d76d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182785823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke.1182785823 |
| Directory | /workspace/85.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.1450780126 |
| Short name | T1594 |
| Test name | |
| Test status | |
| Simulation time | 8305533731 ps |
| CPU time | 92.43 seconds |
| Started | May 30 03:59:22 PM PDT 24 |
| Finished | May 30 04:00:56 PM PDT 24 |
| Peak memory | 564988 kb |
| Host | smart-86561c09-8a3f-4b70-a0a2-75caf7686f3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450780126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_large_delays.1450780126 |
| Directory | /workspace/85.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.1379232096 |
| Short name | T2372 |
| Test name | |
| Test status | |
| Simulation time | 4720340759 ps |
| CPU time | 77.31 seconds |
| Started | May 30 03:59:21 PM PDT 24 |
| Finished | May 30 04:00:39 PM PDT 24 |
| Peak memory | 564976 kb |
| Host | smart-aaefc549-a97a-4b8c-a3da-a5daf3c81e26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379232096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_slow_rsp.1379232096 |
| Directory | /workspace/85.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_zero_delays.3919581916 |
| Short name | T1367 |
| Test name | |
| Test status | |
| Simulation time | 54992788 ps |
| CPU time | 7.14 seconds |
| Started | May 30 03:59:21 PM PDT 24 |
| Finished | May 30 03:59:29 PM PDT 24 |
| Peak memory | 564788 kb |
| Host | smart-37a527f7-8bb6-4f08-be72-b1d985b415bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919581916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_zero_delay s.3919581916 |
| Directory | /workspace/85.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all.2697351844 |
| Short name | T2830 |
| Test name | |
| Test status | |
| Simulation time | 1202119389 ps |
| CPU time | 89.99 seconds |
| Started | May 30 03:59:32 PM PDT 24 |
| Finished | May 30 04:01:03 PM PDT 24 |
| Peak memory | 573080 kb |
| Host | smart-dca8efb6-b43c-4c24-9ca2-885d08d1f087 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697351844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all.2697351844 |
| Directory | /workspace/85.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.3240282978 |
| Short name | T1922 |
| Test name | |
| Test status | |
| Simulation time | 1678060507 ps |
| CPU time | 114.71 seconds |
| Started | May 30 03:59:34 PM PDT 24 |
| Finished | May 30 04:01:30 PM PDT 24 |
| Peak memory | 572920 kb |
| Host | smart-1cc065cc-6a95-4cb7-b806-394da5ba3505 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240282978 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_error.3240282978 |
| Directory | /workspace/85.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.1232484974 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 6536118387 ps |
| CPU time | 783.68 seconds |
| Started | May 30 03:59:32 PM PDT 24 |
| Finished | May 30 04:12:37 PM PDT 24 |
| Peak memory | 573304 kb |
| Host | smart-5ca41c92-79fb-4521-ac33-d952e9cdde28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232484974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all _with_rand_reset.1232484974 |
| Directory | /workspace/85.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.3748431980 |
| Short name | T1812 |
| Test name | |
| Test status | |
| Simulation time | 6479254942 ps |
| CPU time | 414.54 seconds |
| Started | May 30 03:59:34 PM PDT 24 |
| Finished | May 30 04:06:29 PM PDT 24 |
| Peak memory | 573224 kb |
| Host | smart-f6d193c0-53ea-40b5-8bff-be417e79bab7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748431980 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_al l_with_reset_error.3748431980 |
| Directory | /workspace/85.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_unmapped_addr.3694793087 |
| Short name | T2589 |
| Test name | |
| Test status | |
| Simulation time | 26157041 ps |
| CPU time | 5.95 seconds |
| Started | May 30 03:59:32 PM PDT 24 |
| Finished | May 30 03:59:39 PM PDT 24 |
| Peak memory | 564828 kb |
| Host | smart-a6bb64af-1014-4a39-a1cd-51f591ea2dcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694793087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_unmapped_addr.3694793087 |
| Directory | /workspace/85.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device.1715631711 |
| Short name | T2697 |
| Test name | |
| Test status | |
| Simulation time | 1813588007 ps |
| CPU time | 78.58 seconds |
| Started | May 30 03:59:33 PM PDT 24 |
| Finished | May 30 04:00:52 PM PDT 24 |
| Peak memory | 573032 kb |
| Host | smart-02083056-f23b-4f1c-9854-20b9d373a3f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715631711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device .1715631711 |
| Directory | /workspace/86.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.1969760310 |
| Short name | T1559 |
| Test name | |
| Test status | |
| Simulation time | 56343049105 ps |
| CPU time | 979.22 seconds |
| Started | May 30 03:59:40 PM PDT 24 |
| Finished | May 30 04:16:01 PM PDT 24 |
| Peak memory | 573184 kb |
| Host | smart-bdfff63e-a99b-4d9f-b1f9-26b976eaed7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969760310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_ device_slow_rsp.1969760310 |
| Directory | /workspace/86.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.1645389542 |
| Short name | T2025 |
| Test name | |
| Test status | |
| Simulation time | 409507889 ps |
| CPU time | 19.44 seconds |
| Started | May 30 03:59:48 PM PDT 24 |
| Finished | May 30 04:00:08 PM PDT 24 |
| Peak memory | 572900 kb |
| Host | smart-f3ec0dcb-f2d1-4dfe-8544-994ffbf5bea4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645389542 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_and_unmapped_add r.1645389542 |
| Directory | /workspace/86.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_random.4017473196 |
| Short name | T1649 |
| Test name | |
| Test status | |
| Simulation time | 776604493 ps |
| CPU time | 26.5 seconds |
| Started | May 30 03:59:42 PM PDT 24 |
| Finished | May 30 04:00:09 PM PDT 24 |
| Peak memory | 572976 kb |
| Host | smart-b397682e-7708-48bc-a55e-e4c0c081c478 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017473196 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_random.4017473196 |
| Directory | /workspace/86.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random.1770474289 |
| Short name | T1956 |
| Test name | |
| Test status | |
| Simulation time | 667847211 ps |
| CPU time | 26.42 seconds |
| Started | May 30 03:59:32 PM PDT 24 |
| Finished | May 30 04:00:00 PM PDT 24 |
| Peak memory | 573036 kb |
| Host | smart-6127b9a1-6b04-4453-a767-3f5d85375e05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770474289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random.1770474289 |
| Directory | /workspace/86.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_large_delays.4275904912 |
| Short name | T1913 |
| Test name | |
| Test status | |
| Simulation time | 76706697799 ps |
| CPU time | 989.17 seconds |
| Started | May 30 03:59:33 PM PDT 24 |
| Finished | May 30 04:16:03 PM PDT 24 |
| Peak memory | 573196 kb |
| Host | smart-94340d92-644d-46d5-8af7-6b755bef10bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275904912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_large_delays.4275904912 |
| Directory | /workspace/86.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_slow_rsp.3820890945 |
| Short name | T2595 |
| Test name | |
| Test status | |
| Simulation time | 36610058558 ps |
| CPU time | 701.28 seconds |
| Started | May 30 03:59:36 PM PDT 24 |
| Finished | May 30 04:11:18 PM PDT 24 |
| Peak memory | 573104 kb |
| Host | smart-df553136-1447-408d-bbd9-12102e857c9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820890945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_slow_rsp.3820890945 |
| Directory | /workspace/86.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.1773738495 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 440295473 ps |
| CPU time | 37.79 seconds |
| Started | May 30 03:59:32 PM PDT 24 |
| Finished | May 30 04:00:11 PM PDT 24 |
| Peak memory | 572984 kb |
| Host | smart-849886f3-fc1b-4a0c-b680-a0501ca04d92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773738495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_zero_del ays.1773738495 |
| Directory | /workspace/86.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_same_source.1283516158 |
| Short name | T2780 |
| Test name | |
| Test status | |
| Simulation time | 2461676383 ps |
| CPU time | 80.74 seconds |
| Started | May 30 03:59:34 PM PDT 24 |
| Finished | May 30 04:00:56 PM PDT 24 |
| Peak memory | 573028 kb |
| Host | smart-5ffdb559-602f-49c8-af08-d5d5dcf054d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283516158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_same_source.1283516158 |
| Directory | /workspace/86.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke.228634904 |
| Short name | T2331 |
| Test name | |
| Test status | |
| Simulation time | 138704925 ps |
| CPU time | 7.57 seconds |
| Started | May 30 03:59:32 PM PDT 24 |
| Finished | May 30 03:59:41 PM PDT 24 |
| Peak memory | 564808 kb |
| Host | smart-f5eac498-285e-4182-961b-dc5dac8b5f64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228634904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke.228634904 |
| Directory | /workspace/86.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_large_delays.1963125106 |
| Short name | T2237 |
| Test name | |
| Test status | |
| Simulation time | 7143901729 ps |
| CPU time | 82.99 seconds |
| Started | May 30 03:59:34 PM PDT 24 |
| Finished | May 30 04:00:58 PM PDT 24 |
| Peak memory | 563484 kb |
| Host | smart-b579d51f-7123-43f3-ac8c-ba0d9ec32094 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963125106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_large_delays.1963125106 |
| Directory | /workspace/86.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.1985271427 |
| Short name | T2497 |
| Test name | |
| Test status | |
| Simulation time | 4371436424 ps |
| CPU time | 72.52 seconds |
| Started | May 30 03:59:34 PM PDT 24 |
| Finished | May 30 04:00:47 PM PDT 24 |
| Peak memory | 564960 kb |
| Host | smart-41609d69-293d-429a-9ffd-abc72a5a161e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985271427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_slow_rsp.1985271427 |
| Directory | /workspace/86.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_zero_delays.599619030 |
| Short name | T1796 |
| Test name | |
| Test status | |
| Simulation time | 41435735 ps |
| CPU time | 6.21 seconds |
| Started | May 30 03:59:32 PM PDT 24 |
| Finished | May 30 03:59:39 PM PDT 24 |
| Peak memory | 563360 kb |
| Host | smart-371eadc7-6ac6-4716-ad92-f9694a4359e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599619030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_zero_delays .599619030 |
| Directory | /workspace/86.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all.138623273 |
| Short name | T2864 |
| Test name | |
| Test status | |
| Simulation time | 1666331589 ps |
| CPU time | 67.44 seconds |
| Started | May 30 03:59:49 PM PDT 24 |
| Finished | May 30 04:00:58 PM PDT 24 |
| Peak memory | 573132 kb |
| Host | smart-889d72e0-372b-47f2-85af-7a5c5dee8be6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138623273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all.138623273 |
| Directory | /workspace/86.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.444251848 |
| Short name | T2096 |
| Test name | |
| Test status | |
| Simulation time | 12250009322 ps |
| CPU time | 382.23 seconds |
| Started | May 30 03:59:44 PM PDT 24 |
| Finished | May 30 04:06:07 PM PDT 24 |
| Peak memory | 573184 kb |
| Host | smart-cf70c35e-45fc-42d1-9222-a8752e99bbb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444251848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_error.444251848 |
| Directory | /workspace/86.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.953833675 |
| Short name | T2183 |
| Test name | |
| Test status | |
| Simulation time | 5249131042 ps |
| CPU time | 509.32 seconds |
| Started | May 30 03:59:48 PM PDT 24 |
| Finished | May 30 04:08:18 PM PDT 24 |
| Peak memory | 573252 kb |
| Host | smart-e09cb4db-a709-4669-ad7b-b18e87838926 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953833675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_ with_rand_reset.953833675 |
| Directory | /workspace/86.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.1621643235 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 6806515838 ps |
| CPU time | 298.97 seconds |
| Started | May 30 03:59:46 PM PDT 24 |
| Finished | May 30 04:04:46 PM PDT 24 |
| Peak memory | 573236 kb |
| Host | smart-cbbb8082-205a-4257-a63b-68076b5497c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621643235 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_al l_with_reset_error.1621643235 |
| Directory | /workspace/86.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_unmapped_addr.998372868 |
| Short name | T1406 |
| Test name | |
| Test status | |
| Simulation time | 348216542 ps |
| CPU time | 16.52 seconds |
| Started | May 30 03:59:48 PM PDT 24 |
| Finished | May 30 04:00:06 PM PDT 24 |
| Peak memory | 573108 kb |
| Host | smart-1c70ced5-9ef8-4d6e-9a16-9266ed3fa39f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998372868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_unmapped_addr.998372868 |
| Directory | /workspace/86.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device.906651945 |
| Short name | T1453 |
| Test name | |
| Test status | |
| Simulation time | 933081304 ps |
| CPU time | 45.59 seconds |
| Started | May 30 03:59:44 PM PDT 24 |
| Finished | May 30 04:00:31 PM PDT 24 |
| Peak memory | 573056 kb |
| Host | smart-b7f63f96-47c7-47c2-be8a-600ba07e1acf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906651945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device. 906651945 |
| Directory | /workspace/87.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.1527151706 |
| Short name | T2820 |
| Test name | |
| Test status | |
| Simulation time | 136344540138 ps |
| CPU time | 2332.39 seconds |
| Started | May 30 03:59:48 PM PDT 24 |
| Finished | May 30 04:38:42 PM PDT 24 |
| Peak memory | 573208 kb |
| Host | smart-d0757b16-74a4-4b86-8bb9-f6e6d2d7298d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527151706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_ device_slow_rsp.1527151706 |
| Directory | /workspace/87.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.3225430070 |
| Short name | T1660 |
| Test name | |
| Test status | |
| Simulation time | 327984433 ps |
| CPU time | 15.03 seconds |
| Started | May 30 03:59:54 PM PDT 24 |
| Finished | May 30 04:00:10 PM PDT 24 |
| Peak memory | 572924 kb |
| Host | smart-d7aa375b-3995-4746-b1a3-9957e55e7e8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225430070 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_and_unmapped_add r.3225430070 |
| Directory | /workspace/87.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_random.541388941 |
| Short name | T1334 |
| Test name | |
| Test status | |
| Simulation time | 743677518 ps |
| CPU time | 28.98 seconds |
| Started | May 30 03:59:44 PM PDT 24 |
| Finished | May 30 04:00:15 PM PDT 24 |
| Peak memory | 572900 kb |
| Host | smart-e541c2fb-8467-41be-9af0-97c0177ba0c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541388941 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_random.541388941 |
| Directory | /workspace/87.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random.840228545 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 1349097972 ps |
| CPU time | 51.14 seconds |
| Started | May 30 03:59:48 PM PDT 24 |
| Finished | May 30 04:00:40 PM PDT 24 |
| Peak memory | 573084 kb |
| Host | smart-ee427cac-8c64-42f5-b67c-1a9c115e513b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840228545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random.840228545 |
| Directory | /workspace/87.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_large_delays.1960609876 |
| Short name | T2601 |
| Test name | |
| Test status | |
| Simulation time | 16537129502 ps |
| CPU time | 180.84 seconds |
| Started | May 30 03:59:43 PM PDT 24 |
| Finished | May 30 04:02:45 PM PDT 24 |
| Peak memory | 573160 kb |
| Host | smart-06892f7e-3f68-4cc8-909a-99c1ebc6d73e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960609876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_large_delays.1960609876 |
| Directory | /workspace/87.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_slow_rsp.2926401592 |
| Short name | T1499 |
| Test name | |
| Test status | |
| Simulation time | 60852992351 ps |
| CPU time | 1068.82 seconds |
| Started | May 30 03:59:48 PM PDT 24 |
| Finished | May 30 04:17:38 PM PDT 24 |
| Peak memory | 573244 kb |
| Host | smart-32e5edbd-c426-4683-a5af-f59d833cbc84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926401592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_slow_rsp.2926401592 |
| Directory | /workspace/87.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_zero_delays.3212285650 |
| Short name | T1710 |
| Test name | |
| Test status | |
| Simulation time | 262827867 ps |
| CPU time | 25.23 seconds |
| Started | May 30 03:59:48 PM PDT 24 |
| Finished | May 30 04:00:14 PM PDT 24 |
| Peak memory | 572780 kb |
| Host | smart-bb67614b-bf1d-4533-a0ca-6e0e1b803c14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212285650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_zero_del ays.3212285650 |
| Directory | /workspace/87.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_same_source.2809065714 |
| Short name | T1857 |
| Test name | |
| Test status | |
| Simulation time | 285853207 ps |
| CPU time | 22.23 seconds |
| Started | May 30 03:59:45 PM PDT 24 |
| Finished | May 30 04:00:08 PM PDT 24 |
| Peak memory | 573076 kb |
| Host | smart-e4db9c34-0b6d-4c39-8e02-8e708b2e87da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809065714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_same_source.2809065714 |
| Directory | /workspace/87.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke.1815629014 |
| Short name | T1488 |
| Test name | |
| Test status | |
| Simulation time | 45530553 ps |
| CPU time | 5.94 seconds |
| Started | May 30 03:59:45 PM PDT 24 |
| Finished | May 30 03:59:52 PM PDT 24 |
| Peak memory | 564848 kb |
| Host | smart-d49100b9-2144-4fb8-8105-0d0036981dbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815629014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke.1815629014 |
| Directory | /workspace/87.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_large_delays.4232123749 |
| Short name | T1441 |
| Test name | |
| Test status | |
| Simulation time | 9818773409 ps |
| CPU time | 103.8 seconds |
| Started | May 30 03:59:42 PM PDT 24 |
| Finished | May 30 04:01:27 PM PDT 24 |
| Peak memory | 564948 kb |
| Host | smart-9729c457-a62b-4ef0-b425-f6c2923f201a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232123749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_large_delays.4232123749 |
| Directory | /workspace/87.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.2172359063 |
| Short name | T1898 |
| Test name | |
| Test status | |
| Simulation time | 5192757340 ps |
| CPU time | 84.28 seconds |
| Started | May 30 03:59:44 PM PDT 24 |
| Finished | May 30 04:01:09 PM PDT 24 |
| Peak memory | 564932 kb |
| Host | smart-faf1df69-b062-4814-b61c-71e50f55ebf6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172359063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_slow_rsp.2172359063 |
| Directory | /workspace/87.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_zero_delays.2014942344 |
| Short name | T1712 |
| Test name | |
| Test status | |
| Simulation time | 41643654 ps |
| CPU time | 6.28 seconds |
| Started | May 30 03:59:46 PM PDT 24 |
| Finished | May 30 03:59:54 PM PDT 24 |
| Peak memory | 563320 kb |
| Host | smart-1a2c653e-1f37-4ad8-a95d-97c6e04846aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014942344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_zero_delay s.2014942344 |
| Directory | /workspace/87.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all.3813265241 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 11611754485 ps |
| CPU time | 497.96 seconds |
| Started | May 30 03:59:56 PM PDT 24 |
| Finished | May 30 04:08:15 PM PDT 24 |
| Peak memory | 573260 kb |
| Host | smart-34360e75-a286-4973-889b-fa8162350ff5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813265241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all.3813265241 |
| Directory | /workspace/87.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_error.1867745301 |
| Short name | T1988 |
| Test name | |
| Test status | |
| Simulation time | 535236706 ps |
| CPU time | 22.63 seconds |
| Started | May 30 03:59:59 PM PDT 24 |
| Finished | May 30 04:00:23 PM PDT 24 |
| Peak memory | 572972 kb |
| Host | smart-5cfc58b8-7845-4dc4-8e27-c82f70e0f23e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867745301 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_error.1867745301 |
| Directory | /workspace/87.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.2457237109 |
| Short name | T1655 |
| Test name | |
| Test status | |
| Simulation time | 387322306 ps |
| CPU time | 99.96 seconds |
| Started | May 30 03:59:54 PM PDT 24 |
| Finished | May 30 04:01:34 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-f15631ce-d861-4ddb-8b6b-4bbcff1e78ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457237109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all _with_rand_reset.2457237109 |
| Directory | /workspace/87.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.2879855963 |
| Short name | T2417 |
| Test name | |
| Test status | |
| Simulation time | 1324852054 ps |
| CPU time | 75.13 seconds |
| Started | May 30 03:59:59 PM PDT 24 |
| Finished | May 30 04:01:15 PM PDT 24 |
| Peak memory | 573092 kb |
| Host | smart-6d9c26c9-e7f4-4430-b280-e3ed409814ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879855963 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_al l_with_reset_error.2879855963 |
| Directory | /workspace/87.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_unmapped_addr.1225706085 |
| Short name | T2024 |
| Test name | |
| Test status | |
| Simulation time | 602336061 ps |
| CPU time | 26.4 seconds |
| Started | May 30 03:59:47 PM PDT 24 |
| Finished | May 30 04:00:14 PM PDT 24 |
| Peak memory | 573108 kb |
| Host | smart-9c895e81-bbac-4bf4-a7f5-777865d2e781 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225706085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_unmapped_addr.1225706085 |
| Directory | /workspace/87.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device.2008087526 |
| Short name | T1901 |
| Test name | |
| Test status | |
| Simulation time | 963722190 ps |
| CPU time | 78.27 seconds |
| Started | May 30 03:59:55 PM PDT 24 |
| Finished | May 30 04:01:14 PM PDT 24 |
| Peak memory | 573096 kb |
| Host | smart-21a28473-3f93-44a8-945c-41f5c1bf24f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008087526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device .2008087526 |
| Directory | /workspace/88.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.3573009952 |
| Short name | T1702 |
| Test name | |
| Test status | |
| Simulation time | 63759969493 ps |
| CPU time | 1220.54 seconds |
| Started | May 30 03:59:54 PM PDT 24 |
| Finished | May 30 04:20:17 PM PDT 24 |
| Peak memory | 573268 kb |
| Host | smart-d16d98e3-e564-4889-b666-04febe81a185 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573009952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_ device_slow_rsp.3573009952 |
| Directory | /workspace/88.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.4090422011 |
| Short name | T1933 |
| Test name | |
| Test status | |
| Simulation time | 773609406 ps |
| CPU time | 32.06 seconds |
| Started | May 30 03:59:54 PM PDT 24 |
| Finished | May 30 04:00:27 PM PDT 24 |
| Peak memory | 572916 kb |
| Host | smart-504115c5-593d-427e-a49e-987645f08264 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090422011 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_and_unmapped_add r.4090422011 |
| Directory | /workspace/88.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_random.3588758699 |
| Short name | T1385 |
| Test name | |
| Test status | |
| Simulation time | 504216802 ps |
| CPU time | 41.9 seconds |
| Started | May 30 03:59:56 PM PDT 24 |
| Finished | May 30 04:00:38 PM PDT 24 |
| Peak memory | 573928 kb |
| Host | smart-a2cf2067-75f4-4c29-a6ac-c7326c099754 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588758699 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_random.3588758699 |
| Directory | /workspace/88.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random.2500794393 |
| Short name | T1593 |
| Test name | |
| Test status | |
| Simulation time | 2153805333 ps |
| CPU time | 72.21 seconds |
| Started | May 30 03:59:57 PM PDT 24 |
| Finished | May 30 04:01:10 PM PDT 24 |
| Peak memory | 573008 kb |
| Host | smart-07474576-b3c6-466c-b0cd-8aa712dc4f90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500794393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random.2500794393 |
| Directory | /workspace/88.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_large_delays.1890837354 |
| Short name | T2209 |
| Test name | |
| Test status | |
| Simulation time | 5413917993 ps |
| CPU time | 59.03 seconds |
| Started | May 30 03:59:54 PM PDT 24 |
| Finished | May 30 04:00:54 PM PDT 24 |
| Peak memory | 563488 kb |
| Host | smart-ef715767-120a-4452-84ba-7b65b7efafdb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890837354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_large_delays.1890837354 |
| Directory | /workspace/88.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.897201379 |
| Short name | T1608 |
| Test name | |
| Test status | |
| Simulation time | 16285024433 ps |
| CPU time | 287.54 seconds |
| Started | May 30 03:59:55 PM PDT 24 |
| Finished | May 30 04:04:44 PM PDT 24 |
| Peak memory | 573160 kb |
| Host | smart-e986bfda-2028-4654-b226-f8f4355558fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897201379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_slow_rsp.897201379 |
| Directory | /workspace/88.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_zero_delays.4104419386 |
| Short name | T2547 |
| Test name | |
| Test status | |
| Simulation time | 423689015 ps |
| CPU time | 41.27 seconds |
| Started | May 30 03:59:57 PM PDT 24 |
| Finished | May 30 04:00:39 PM PDT 24 |
| Peak memory | 573056 kb |
| Host | smart-ab2bccde-2390-4494-9ec0-eea328846be9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104419386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_zero_del ays.4104419386 |
| Directory | /workspace/88.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_same_source.2874698305 |
| Short name | T1468 |
| Test name | |
| Test status | |
| Simulation time | 465075855 ps |
| CPU time | 14.73 seconds |
| Started | May 30 03:59:53 PM PDT 24 |
| Finished | May 30 04:00:08 PM PDT 24 |
| Peak memory | 572900 kb |
| Host | smart-12060275-5fa9-4066-a2e8-517017f71b4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874698305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_same_source.2874698305 |
| Directory | /workspace/88.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke.158899486 |
| Short name | T2826 |
| Test name | |
| Test status | |
| Simulation time | 52466250 ps |
| CPU time | 6.6 seconds |
| Started | May 30 03:59:53 PM PDT 24 |
| Finished | May 30 04:00:01 PM PDT 24 |
| Peak memory | 563364 kb |
| Host | smart-a8bc4ed1-591a-476d-afe2-afbf9cce9f14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158899486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke.158899486 |
| Directory | /workspace/88.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.1836865046 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 9511976834 ps |
| CPU time | 100.05 seconds |
| Started | May 30 03:59:57 PM PDT 24 |
| Finished | May 30 04:01:38 PM PDT 24 |
| Peak memory | 563536 kb |
| Host | smart-96cefee2-4d41-42fb-87cf-3c9ff0218fe9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836865046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_large_delays.1836865046 |
| Directory | /workspace/88.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.3289989486 |
| Short name | T1337 |
| Test name | |
| Test status | |
| Simulation time | 5674611730 ps |
| CPU time | 94.24 seconds |
| Started | May 30 03:59:54 PM PDT 24 |
| Finished | May 30 04:01:29 PM PDT 24 |
| Peak memory | 564936 kb |
| Host | smart-2a8c006b-4a91-44ac-a943-8e8cb587a060 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289989486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_slow_rsp.3289989486 |
| Directory | /workspace/88.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_zero_delays.4044816559 |
| Short name | T1926 |
| Test name | |
| Test status | |
| Simulation time | 57317118 ps |
| CPU time | 6.75 seconds |
| Started | May 30 03:59:55 PM PDT 24 |
| Finished | May 30 04:00:02 PM PDT 24 |
| Peak memory | 564800 kb |
| Host | smart-805b0a54-00c0-4ecd-94f8-1cb9e25b1850 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044816559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_zero_delay s.4044816559 |
| Directory | /workspace/88.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all.441293258 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 18762963741 ps |
| CPU time | 731.01 seconds |
| Started | May 30 03:59:54 PM PDT 24 |
| Finished | May 30 04:12:06 PM PDT 24 |
| Peak memory | 576400 kb |
| Host | smart-45f46e1e-a19c-45f0-8000-a8c0360b538a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441293258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all.441293258 |
| Directory | /workspace/88.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.2506893374 |
| Short name | T2315 |
| Test name | |
| Test status | |
| Simulation time | 12780502409 ps |
| CPU time | 474.75 seconds |
| Started | May 30 03:59:58 PM PDT 24 |
| Finished | May 30 04:07:54 PM PDT 24 |
| Peak memory | 573232 kb |
| Host | smart-8562077f-db53-4e43-a6db-9640ee325fc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506893374 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_error.2506893374 |
| Directory | /workspace/88.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.720437621 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 329012252 ps |
| CPU time | 164.26 seconds |
| Started | May 30 03:59:53 PM PDT 24 |
| Finished | May 30 04:02:38 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-7610d5ee-dacf-4a98-86f1-aa1ea76df60a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720437621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_ with_rand_reset.720437621 |
| Directory | /workspace/88.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.2419986531 |
| Short name | T2655 |
| Test name | |
| Test status | |
| Simulation time | 155218775 ps |
| CPU time | 29.02 seconds |
| Started | May 30 03:59:58 PM PDT 24 |
| Finished | May 30 04:00:28 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-129cf084-6514-4376-9c3e-6c23028253b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419986531 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_al l_with_reset_error.2419986531 |
| Directory | /workspace/88.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_unmapped_addr.1292568077 |
| Short name | T2646 |
| Test name | |
| Test status | |
| Simulation time | 793331687 ps |
| CPU time | 34.87 seconds |
| Started | May 30 03:59:54 PM PDT 24 |
| Finished | May 30 04:00:30 PM PDT 24 |
| Peak memory | 573056 kb |
| Host | smart-ce5c2aa4-01c4-419d-9328-fb1baabaddfd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292568077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_unmapped_addr.1292568077 |
| Directory | /workspace/88.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device.3296681524 |
| Short name | T2055 |
| Test name | |
| Test status | |
| Simulation time | 1536399259 ps |
| CPU time | 59.25 seconds |
| Started | May 30 03:59:54 PM PDT 24 |
| Finished | May 30 04:00:54 PM PDT 24 |
| Peak memory | 573024 kb |
| Host | smart-4ac0eace-1fba-4338-ba36-6f34a758ae3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296681524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device .3296681524 |
| Directory | /workspace/89.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.246192984 |
| Short name | T2427 |
| Test name | |
| Test status | |
| Simulation time | 13322483044 ps |
| CPU time | 247.23 seconds |
| Started | May 30 04:00:06 PM PDT 24 |
| Finished | May 30 04:04:14 PM PDT 24 |
| Peak memory | 572888 kb |
| Host | smart-ba956b22-da83-44d6-9eec-bb2c9c22b728 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246192984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_d evice_slow_rsp.246192984 |
| Directory | /workspace/89.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.543341964 |
| Short name | T1366 |
| Test name | |
| Test status | |
| Simulation time | 165862159 ps |
| CPU time | 22.12 seconds |
| Started | May 30 04:00:08 PM PDT 24 |
| Finished | May 30 04:00:31 PM PDT 24 |
| Peak memory | 573964 kb |
| Host | smart-e329e171-58ce-46de-a3fc-8fc584e50518 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543341964 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_and_unmapped_addr .543341964 |
| Directory | /workspace/89.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_random.2895041733 |
| Short name | T2858 |
| Test name | |
| Test status | |
| Simulation time | 78100845 ps |
| CPU time | 6.12 seconds |
| Started | May 30 04:00:08 PM PDT 24 |
| Finished | May 30 04:00:15 PM PDT 24 |
| Peak memory | 564724 kb |
| Host | smart-ec0d7143-77a6-456f-8b82-64a4636e0bc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895041733 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_random.2895041733 |
| Directory | /workspace/89.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random.1975918060 |
| Short name | T2612 |
| Test name | |
| Test status | |
| Simulation time | 1023769006 ps |
| CPU time | 33.77 seconds |
| Started | May 30 03:59:54 PM PDT 24 |
| Finished | May 30 04:00:29 PM PDT 24 |
| Peak memory | 572944 kb |
| Host | smart-d23cb72b-fa3b-48b3-abae-1eb53d5a4bd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975918060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random.1975918060 |
| Directory | /workspace/89.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_large_delays.3028903322 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 55435258702 ps |
| CPU time | 615.29 seconds |
| Started | May 30 04:00:00 PM PDT 24 |
| Finished | May 30 04:10:17 PM PDT 24 |
| Peak memory | 573184 kb |
| Host | smart-5ec93b00-9a91-4f28-a556-36ac70c0e54d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028903322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_large_delays.3028903322 |
| Directory | /workspace/89.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_slow_rsp.1980294489 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 31767067862 ps |
| CPU time | 530.92 seconds |
| Started | May 30 03:59:58 PM PDT 24 |
| Finished | May 30 04:08:50 PM PDT 24 |
| Peak memory | 573208 kb |
| Host | smart-71b75c4b-62a8-4846-80cd-f53d91a055b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980294489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_slow_rsp.1980294489 |
| Directory | /workspace/89.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_zero_delays.1859797210 |
| Short name | T2154 |
| Test name | |
| Test status | |
| Simulation time | 304937012 ps |
| CPU time | 28.71 seconds |
| Started | May 30 03:59:59 PM PDT 24 |
| Finished | May 30 04:00:29 PM PDT 24 |
| Peak memory | 572936 kb |
| Host | smart-3ba63f1e-4e2b-4c61-be3a-e4682469c73e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859797210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_zero_del ays.1859797210 |
| Directory | /workspace/89.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_same_source.1587201777 |
| Short name | T2799 |
| Test name | |
| Test status | |
| Simulation time | 918929622 ps |
| CPU time | 29.39 seconds |
| Started | May 30 04:00:05 PM PDT 24 |
| Finished | May 30 04:00:35 PM PDT 24 |
| Peak memory | 572960 kb |
| Host | smart-c7583a62-913b-4478-bc47-03a278995104 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587201777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_same_source.1587201777 |
| Directory | /workspace/89.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke.3078505447 |
| Short name | T2169 |
| Test name | |
| Test status | |
| Simulation time | 222611726 ps |
| CPU time | 9.31 seconds |
| Started | May 30 03:59:57 PM PDT 24 |
| Finished | May 30 04:00:07 PM PDT 24 |
| Peak memory | 563352 kb |
| Host | smart-1c1269c4-8452-45fa-8f94-e6df5346957f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078505447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke.3078505447 |
| Directory | /workspace/89.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_large_delays.1814996022 |
| Short name | T1714 |
| Test name | |
| Test status | |
| Simulation time | 8580110878 ps |
| CPU time | 94.09 seconds |
| Started | May 30 03:59:54 PM PDT 24 |
| Finished | May 30 04:01:29 PM PDT 24 |
| Peak memory | 564924 kb |
| Host | smart-aa9ce122-32e0-4114-8b9d-03baf4630266 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814996022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_large_delays.1814996022 |
| Directory | /workspace/89.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.2587315796 |
| Short name | T1570 |
| Test name | |
| Test status | |
| Simulation time | 6636447577 ps |
| CPU time | 111.7 seconds |
| Started | May 30 04:00:00 PM PDT 24 |
| Finished | May 30 04:01:53 PM PDT 24 |
| Peak memory | 563536 kb |
| Host | smart-01d75724-71e1-4637-a677-fa221cf12d4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587315796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_slow_rsp.2587315796 |
| Directory | /workspace/89.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.1341093607 |
| Short name | T2092 |
| Test name | |
| Test status | |
| Simulation time | 58708132 ps |
| CPU time | 7.48 seconds |
| Started | May 30 03:59:56 PM PDT 24 |
| Finished | May 30 04:00:04 PM PDT 24 |
| Peak memory | 564788 kb |
| Host | smart-d31d4f19-deb8-4425-99f0-bc392ce5448f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341093607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_zero_delay s.1341093607 |
| Directory | /workspace/89.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all.2021495887 |
| Short name | T2753 |
| Test name | |
| Test status | |
| Simulation time | 522321608 ps |
| CPU time | 47.66 seconds |
| Started | May 30 04:00:04 PM PDT 24 |
| Finished | May 30 04:00:53 PM PDT 24 |
| Peak memory | 573160 kb |
| Host | smart-f5115551-4946-4ff6-a606-4945d107cd62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021495887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all.2021495887 |
| Directory | /workspace/89.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.3053723181 |
| Short name | T1629 |
| Test name | |
| Test status | |
| Simulation time | 13131154202 ps |
| CPU time | 542.5 seconds |
| Started | May 30 04:00:06 PM PDT 24 |
| Finished | May 30 04:09:10 PM PDT 24 |
| Peak memory | 573236 kb |
| Host | smart-e99b4354-9c03-4e68-a525-0fcefd81afc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053723181 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_error.3053723181 |
| Directory | /workspace/89.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.1675209017 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 6843987520 ps |
| CPU time | 848.9 seconds |
| Started | May 30 04:00:03 PM PDT 24 |
| Finished | May 30 04:14:12 PM PDT 24 |
| Peak memory | 573240 kb |
| Host | smart-7d2374a4-d0f7-4421-80f7-1ee9ddf1573e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675209017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all _with_rand_reset.1675209017 |
| Directory | /workspace/89.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.238428006 |
| Short name | T2785 |
| Test name | |
| Test status | |
| Simulation time | 63934337 ps |
| CPU time | 31.4 seconds |
| Started | May 30 04:00:04 PM PDT 24 |
| Finished | May 30 04:00:36 PM PDT 24 |
| Peak memory | 573096 kb |
| Host | smart-09f6d3bd-7fc5-4faf-a94f-43107fb1b7cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238428006 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all _with_reset_error.238428006 |
| Directory | /workspace/89.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.3714284316 |
| Short name | T1716 |
| Test name | |
| Test status | |
| Simulation time | 68230871 ps |
| CPU time | 9.85 seconds |
| Started | May 30 04:00:05 PM PDT 24 |
| Finished | May 30 04:00:15 PM PDT 24 |
| Peak memory | 573004 kb |
| Host | smart-6c0474b6-bfb0-402d-8483-79404524a3cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714284316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_unmapped_addr.3714284316 |
| Directory | /workspace/89.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_csr_rw.3347617111 |
| Short name | T1909 |
| Test name | |
| Test status | |
| Simulation time | 6012747736 ps |
| CPU time | 488.49 seconds |
| Started | May 30 03:48:54 PM PDT 24 |
| Finished | May 30 03:57:04 PM PDT 24 |
| Peak memory | 592608 kb |
| Host | smart-b32fb574-3dca-4130-8c6d-1b0aedfaa61b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347617111 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_rw.3347617111 |
| Directory | /workspace/9.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.3029199750 |
| Short name | T1879 |
| Test name | |
| Test status | |
| Simulation time | 15780273782 ps |
| CPU time | 1588.59 seconds |
| Started | May 30 03:49:00 PM PDT 24 |
| Finished | May 30 04:15:31 PM PDT 24 |
| Peak memory | 587756 kb |
| Host | smart-02225bda-553f-4960-a166-bc534a735827 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029199750 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 9.chip_same_csr_outstanding.3029199750 |
| Directory | /workspace/9.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device.1129919646 |
| Short name | T1960 |
| Test name | |
| Test status | |
| Simulation time | 2372497459 ps |
| CPU time | 77.46 seconds |
| Started | May 30 03:49:00 PM PDT 24 |
| Finished | May 30 03:50:19 PM PDT 24 |
| Peak memory | 573132 kb |
| Host | smart-b61f1d81-470d-4579-926b-4d390fe48a79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129919646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device. 1129919646 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.3154639959 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 91915550849 ps |
| CPU time | 1439.52 seconds |
| Started | May 30 03:48:57 PM PDT 24 |
| Finished | May 30 04:12:59 PM PDT 24 |
| Peak memory | 573300 kb |
| Host | smart-34037f6b-7e03-4716-92aa-b3e05068bee3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154639959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_d evice_slow_rsp.3154639959 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.2707636074 |
| Short name | T1912 |
| Test name | |
| Test status | |
| Simulation time | 245320383 ps |
| CPU time | 23.95 seconds |
| Started | May 30 03:49:04 PM PDT 24 |
| Finished | May 30 03:49:29 PM PDT 24 |
| Peak memory | 572908 kb |
| Host | smart-a9903e51-8ba0-4eac-951f-e18028409c61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707636074 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr .2707636074 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_random.161864331 |
| Short name | T1612 |
| Test name | |
| Test status | |
| Simulation time | 606745475 ps |
| CPU time | 41.28 seconds |
| Started | May 30 03:49:19 PM PDT 24 |
| Finished | May 30 03:50:02 PM PDT 24 |
| Peak memory | 572852 kb |
| Host | smart-c6459fd9-9b15-401c-a8d7-f6f09c7bdd11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161864331 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.161864331 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random.4291075557 |
| Short name | T2141 |
| Test name | |
| Test status | |
| Simulation time | 1073605131 ps |
| CPU time | 43.71 seconds |
| Started | May 30 03:48:57 PM PDT 24 |
| Finished | May 30 03:49:43 PM PDT 24 |
| Peak memory | 573072 kb |
| Host | smart-039e62ac-1a37-4493-adf6-9d169a6d27b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291075557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random.4291075557 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_large_delays.370890122 |
| Short name | T2457 |
| Test name | |
| Test status | |
| Simulation time | 5441210452 ps |
| CPU time | 58.35 seconds |
| Started | May 30 03:49:03 PM PDT 24 |
| Finished | May 30 03:50:03 PM PDT 24 |
| Peak memory | 563552 kb |
| Host | smart-587e90a3-feb4-4551-acc6-ba69a19e4653 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370890122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.370890122 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_slow_rsp.2585906634 |
| Short name | T2542 |
| Test name | |
| Test status | |
| Simulation time | 32636716368 ps |
| CPU time | 552.95 seconds |
| Started | May 30 03:48:59 PM PDT 24 |
| Finished | May 30 03:58:14 PM PDT 24 |
| Peak memory | 573184 kb |
| Host | smart-6a646949-0ddb-4c8a-9548-c427477e01f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585906634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.2585906634 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_zero_delays.2940193900 |
| Short name | T2041 |
| Test name | |
| Test status | |
| Simulation time | 366129620 ps |
| CPU time | 34.61 seconds |
| Started | May 30 03:49:01 PM PDT 24 |
| Finished | May 30 03:49:37 PM PDT 24 |
| Peak memory | 573052 kb |
| Host | smart-b008e9b4-e483-4fec-a8e4-ed9512d70ca1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940193900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_dela ys.2940193900 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_same_source.1629357483 |
| Short name | T2645 |
| Test name | |
| Test status | |
| Simulation time | 373471640 ps |
| CPU time | 28.21 seconds |
| Started | May 30 03:49:00 PM PDT 24 |
| Finished | May 30 03:49:30 PM PDT 24 |
| Peak memory | 573080 kb |
| Host | smart-86bdd057-bd0f-4efe-9db2-c9c7fab7226c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629357483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.1629357483 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke.520843225 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 158545797 ps |
| CPU time | 7.76 seconds |
| Started | May 30 03:48:57 PM PDT 24 |
| Finished | May 30 03:49:07 PM PDT 24 |
| Peak memory | 564844 kb |
| Host | smart-ecd9fea1-65f2-4f57-9965-126ccf3de5d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520843225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.520843225 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_large_delays.2378388626 |
| Short name | T2696 |
| Test name | |
| Test status | |
| Simulation time | 8611568610 ps |
| CPU time | 89.9 seconds |
| Started | May 30 03:48:59 PM PDT 24 |
| Finished | May 30 03:50:31 PM PDT 24 |
| Peak memory | 564932 kb |
| Host | smart-cf0ec7e2-8c2f-4fdb-b080-d768e3a102f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378388626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.2378388626 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.2744590690 |
| Short name | T1328 |
| Test name | |
| Test status | |
| Simulation time | 4286636789 ps |
| CPU time | 71.74 seconds |
| Started | May 30 03:48:53 PM PDT 24 |
| Finished | May 30 03:50:06 PM PDT 24 |
| Peak memory | 564892 kb |
| Host | smart-bdaa37da-df5f-49ba-b7c2-9839c231d9de |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744590690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.2744590690 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_zero_delays.3070715049 |
| Short name | T1764 |
| Test name | |
| Test status | |
| Simulation time | 52827693 ps |
| CPU time | 6.82 seconds |
| Started | May 30 03:49:01 PM PDT 24 |
| Finished | May 30 03:49:10 PM PDT 24 |
| Peak memory | 564804 kb |
| Host | smart-ea0b1dff-f868-4b50-a19a-98ace27157e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070715049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays .3070715049 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all.1801691325 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 18477938540 ps |
| CPU time | 768.73 seconds |
| Started | May 30 03:49:17 PM PDT 24 |
| Finished | May 30 04:02:09 PM PDT 24 |
| Peak memory | 573280 kb |
| Host | smart-3ffb5066-bfda-4927-9bc9-53b0aa5482d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801691325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.1801691325 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_error.4073915903 |
| Short name | T2729 |
| Test name | |
| Test status | |
| Simulation time | 8478124060 ps |
| CPU time | 314.53 seconds |
| Started | May 30 03:48:55 PM PDT 24 |
| Finished | May 30 03:54:11 PM PDT 24 |
| Peak memory | 573132 kb |
| Host | smart-ac7b31bb-0ef2-4aa6-8816-4f41fe6b66ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073915903 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.4073915903 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.1620297722 |
| Short name | T2582 |
| Test name | |
| Test status | |
| Simulation time | 3698537207 ps |
| CPU time | 544.29 seconds |
| Started | May 30 03:49:03 PM PDT 24 |
| Finished | May 30 03:58:09 PM PDT 24 |
| Peak memory | 573212 kb |
| Host | smart-851f13ec-47dc-4e6a-bfc5-6fa0c1e8c3e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620297722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_ with_rand_reset.1620297722 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.3315234983 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 269004926 ps |
| CPU time | 149.37 seconds |
| Started | May 30 03:48:59 PM PDT 24 |
| Finished | May 30 03:51:30 PM PDT 24 |
| Peak memory | 576852 kb |
| Host | smart-84802e14-5e79-4c6b-99bf-cbea09f8bfde |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315234983 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all _with_reset_error.3315234983 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.1784348877 |
| Short name | T1882 |
| Test name | |
| Test status | |
| Simulation time | 1375990936 ps |
| CPU time | 59.9 seconds |
| Started | May 30 03:49:15 PM PDT 24 |
| Finished | May 30 03:50:17 PM PDT 24 |
| Peak memory | 573096 kb |
| Host | smart-02ad6a1a-8d72-42d0-a4c6-3db22bf79118 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784348877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.1784348877 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device.3195060136 |
| Short name | T1838 |
| Test name | |
| Test status | |
| Simulation time | 2678242170 ps |
| CPU time | 112.21 seconds |
| Started | May 30 04:00:06 PM PDT 24 |
| Finished | May 30 04:01:58 PM PDT 24 |
| Peak memory | 573120 kb |
| Host | smart-01ab8e2c-b3f4-4dd5-96b4-9e9c62b62da0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195060136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device .3195060136 |
| Directory | /workspace/90.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.122936030 |
| Short name | T2130 |
| Test name | |
| Test status | |
| Simulation time | 85189526375 ps |
| CPU time | 1559.29 seconds |
| Started | May 30 04:00:05 PM PDT 24 |
| Finished | May 30 04:26:05 PM PDT 24 |
| Peak memory | 573340 kb |
| Host | smart-31788a36-ee28-4114-a204-0c0235912639 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122936030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_d evice_slow_rsp.122936030 |
| Directory | /workspace/90.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.1500774771 |
| Short name | T2345 |
| Test name | |
| Test status | |
| Simulation time | 204531047 ps |
| CPU time | 24.03 seconds |
| Started | May 30 04:00:19 PM PDT 24 |
| Finished | May 30 04:00:44 PM PDT 24 |
| Peak memory | 572872 kb |
| Host | smart-7cf71e5c-6623-4f61-878c-b768815cfbfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500774771 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_and_unmapped_add r.1500774771 |
| Directory | /workspace/90.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_random.833916816 |
| Short name | T1323 |
| Test name | |
| Test status | |
| Simulation time | 2231806112 ps |
| CPU time | 83.33 seconds |
| Started | May 30 04:00:09 PM PDT 24 |
| Finished | May 30 04:01:33 PM PDT 24 |
| Peak memory | 574052 kb |
| Host | smart-522c5b94-9945-4f12-a0a8-baa24effb357 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833916816 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_random.833916816 |
| Directory | /workspace/90.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random.2008568755 |
| Short name | T1662 |
| Test name | |
| Test status | |
| Simulation time | 677292818 ps |
| CPU time | 27.2 seconds |
| Started | May 30 04:00:09 PM PDT 24 |
| Finished | May 30 04:00:37 PM PDT 24 |
| Peak memory | 573052 kb |
| Host | smart-d78639b2-b7ab-4342-9c39-af3c7a2cb791 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008568755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random.2008568755 |
| Directory | /workspace/90.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_large_delays.3323266847 |
| Short name | T1584 |
| Test name | |
| Test status | |
| Simulation time | 57311133485 ps |
| CPU time | 606.84 seconds |
| Started | May 30 04:00:06 PM PDT 24 |
| Finished | May 30 04:10:14 PM PDT 24 |
| Peak memory | 573148 kb |
| Host | smart-3fcb7435-91d0-47ab-83a0-9c443bb3deeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323266847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_large_delays.3323266847 |
| Directory | /workspace/90.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_slow_rsp.1949154344 |
| Short name | T2095 |
| Test name | |
| Test status | |
| Simulation time | 17925364538 ps |
| CPU time | 361.08 seconds |
| Started | May 30 04:00:05 PM PDT 24 |
| Finished | May 30 04:06:07 PM PDT 24 |
| Peak memory | 573160 kb |
| Host | smart-5977c592-2b07-49d8-b7e5-66ad69b76894 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949154344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_slow_rsp.1949154344 |
| Directory | /workspace/90.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.2189580307 |
| Short name | T1789 |
| Test name | |
| Test status | |
| Simulation time | 191784736 ps |
| CPU time | 17.16 seconds |
| Started | May 30 04:00:04 PM PDT 24 |
| Finished | May 30 04:00:22 PM PDT 24 |
| Peak memory | 572976 kb |
| Host | smart-19917c11-7439-4649-86d8-2fdaa1faa003 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189580307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_zero_del ays.2189580307 |
| Directory | /workspace/90.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_same_source.396541905 |
| Short name | T2142 |
| Test name | |
| Test status | |
| Simulation time | 2655988651 ps |
| CPU time | 77.51 seconds |
| Started | May 30 04:00:03 PM PDT 24 |
| Finished | May 30 04:01:21 PM PDT 24 |
| Peak memory | 573020 kb |
| Host | smart-710debd2-b2ab-4b52-bcff-b6923312005c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396541905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_same_source.396541905 |
| Directory | /workspace/90.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke.1837183770 |
| Short name | T1491 |
| Test name | |
| Test status | |
| Simulation time | 223760216 ps |
| CPU time | 9.29 seconds |
| Started | May 30 04:00:07 PM PDT 24 |
| Finished | May 30 04:00:17 PM PDT 24 |
| Peak memory | 563336 kb |
| Host | smart-38faa08c-70f7-40c3-9a75-dd6edc278a45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837183770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke.1837183770 |
| Directory | /workspace/90.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_large_delays.2394406619 |
| Short name | T1508 |
| Test name | |
| Test status | |
| Simulation time | 6646554760 ps |
| CPU time | 72.93 seconds |
| Started | May 30 04:00:04 PM PDT 24 |
| Finished | May 30 04:01:18 PM PDT 24 |
| Peak memory | 564964 kb |
| Host | smart-6adc61ea-f001-46e4-ba66-e8ae737a7c2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394406619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_large_delays.2394406619 |
| Directory | /workspace/90.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.553238371 |
| Short name | T1557 |
| Test name | |
| Test status | |
| Simulation time | 3879176206 ps |
| CPU time | 67.82 seconds |
| Started | May 30 04:00:07 PM PDT 24 |
| Finished | May 30 04:01:15 PM PDT 24 |
| Peak memory | 563448 kb |
| Host | smart-2ade5eee-cda4-42d3-8ec5-1d30bb5e4775 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553238371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_slow_rsp.553238371 |
| Directory | /workspace/90.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_zero_delays.4015339334 |
| Short name | T1378 |
| Test name | |
| Test status | |
| Simulation time | 39091230 ps |
| CPU time | 5.57 seconds |
| Started | May 30 04:00:08 PM PDT 24 |
| Finished | May 30 04:00:14 PM PDT 24 |
| Peak memory | 563372 kb |
| Host | smart-e700323f-5ae1-4547-9168-db3d8d00123f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015339334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_zero_delay s.4015339334 |
| Directory | /workspace/90.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all.685535226 |
| Short name | T1729 |
| Test name | |
| Test status | |
| Simulation time | 1915466801 ps |
| CPU time | 169.82 seconds |
| Started | May 30 04:00:21 PM PDT 24 |
| Finished | May 30 04:03:12 PM PDT 24 |
| Peak memory | 573120 kb |
| Host | smart-8bad2538-5842-4010-9561-f27c4315e639 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685535226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all.685535226 |
| Directory | /workspace/90.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.3872921956 |
| Short name | T1856 |
| Test name | |
| Test status | |
| Simulation time | 1373858851 ps |
| CPU time | 94.32 seconds |
| Started | May 30 04:00:22 PM PDT 24 |
| Finished | May 30 04:01:57 PM PDT 24 |
| Peak memory | 572960 kb |
| Host | smart-c236033d-9fb1-4ca3-9e10-211b320e6613 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872921956 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_error.3872921956 |
| Directory | /workspace/90.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.2370628965 |
| Short name | T2605 |
| Test name | |
| Test status | |
| Simulation time | 389519642 ps |
| CPU time | 151.82 seconds |
| Started | May 30 04:00:22 PM PDT 24 |
| Finished | May 30 04:02:55 PM PDT 24 |
| Peak memory | 573144 kb |
| Host | smart-39c47350-2638-4340-b370-8825e83b651d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370628965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all _with_rand_reset.2370628965 |
| Directory | /workspace/90.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.1878554697 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 1810230278 ps |
| CPU time | 354.33 seconds |
| Started | May 30 04:00:21 PM PDT 24 |
| Finished | May 30 04:06:16 PM PDT 24 |
| Peak memory | 573056 kb |
| Host | smart-937b3ace-3f66-4881-9df7-77a3ad56b785 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878554697 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_al l_with_reset_error.1878554697 |
| Directory | /workspace/90.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_unmapped_addr.547253423 |
| Short name | T2412 |
| Test name | |
| Test status | |
| Simulation time | 214114111 ps |
| CPU time | 25.96 seconds |
| Started | May 30 04:00:22 PM PDT 24 |
| Finished | May 30 04:00:49 PM PDT 24 |
| Peak memory | 572972 kb |
| Host | smart-5f1c8bb7-280e-47a3-b5c8-76d521cb04c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547253423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_unmapped_addr.547253423 |
| Directory | /workspace/90.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device.2660064765 |
| Short name | T1663 |
| Test name | |
| Test status | |
| Simulation time | 2726075231 ps |
| CPU time | 123.56 seconds |
| Started | May 30 04:00:22 PM PDT 24 |
| Finished | May 30 04:02:27 PM PDT 24 |
| Peak memory | 573172 kb |
| Host | smart-ec8faf13-8ae7-486e-9a0f-2bd0d3d4347f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660064765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device .2660064765 |
| Directory | /workspace/91.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.835622323 |
| Short name | T1382 |
| Test name | |
| Test status | |
| Simulation time | 21938536230 ps |
| CPU time | 379.24 seconds |
| Started | May 30 04:00:20 PM PDT 24 |
| Finished | May 30 04:06:41 PM PDT 24 |
| Peak memory | 573244 kb |
| Host | smart-465b802a-874b-4407-88c3-b2e9e814b040 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835622323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_d evice_slow_rsp.835622323 |
| Directory | /workspace/91.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.824514215 |
| Short name | T1757 |
| Test name | |
| Test status | |
| Simulation time | 228373060 ps |
| CPU time | 26.12 seconds |
| Started | May 30 04:00:21 PM PDT 24 |
| Finished | May 30 04:00:49 PM PDT 24 |
| Peak memory | 572880 kb |
| Host | smart-27a329d8-004b-4b49-a6fa-35c626db8762 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824514215 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_and_unmapped_addr .824514215 |
| Directory | /workspace/91.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_random.887945583 |
| Short name | T1837 |
| Test name | |
| Test status | |
| Simulation time | 402921201 ps |
| CPU time | 15.83 seconds |
| Started | May 30 04:00:19 PM PDT 24 |
| Finished | May 30 04:00:36 PM PDT 24 |
| Peak memory | 572808 kb |
| Host | smart-1fd00020-96d4-49fe-8902-a6ee39faa9b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887945583 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_random.887945583 |
| Directory | /workspace/91.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random.3278880748 |
| Short name | T2579 |
| Test name | |
| Test status | |
| Simulation time | 38623657 ps |
| CPU time | 6.5 seconds |
| Started | May 30 04:00:20 PM PDT 24 |
| Finished | May 30 04:00:28 PM PDT 24 |
| Peak memory | 563456 kb |
| Host | smart-6d299803-408c-412f-92aa-51158a879cfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278880748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random.3278880748 |
| Directory | /workspace/91.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.3537920592 |
| Short name | T2666 |
| Test name | |
| Test status | |
| Simulation time | 55685743608 ps |
| CPU time | 609.83 seconds |
| Started | May 30 04:00:20 PM PDT 24 |
| Finished | May 30 04:10:31 PM PDT 24 |
| Peak memory | 573152 kb |
| Host | smart-4c2bf580-98de-4c86-a93d-bd16ba11ce5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537920592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_large_delays.3537920592 |
| Directory | /workspace/91.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_slow_rsp.102735381 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 55543948778 ps |
| CPU time | 1056.89 seconds |
| Started | May 30 04:00:21 PM PDT 24 |
| Finished | May 30 04:17:59 PM PDT 24 |
| Peak memory | 573204 kb |
| Host | smart-74997f10-0d84-484b-9d1e-9b224288057d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102735381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_slow_rsp.102735381 |
| Directory | /workspace/91.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_zero_delays.1861273149 |
| Short name | T1563 |
| Test name | |
| Test status | |
| Simulation time | 382795208 ps |
| CPU time | 36.29 seconds |
| Started | May 30 04:00:21 PM PDT 24 |
| Finished | May 30 04:00:59 PM PDT 24 |
| Peak memory | 572968 kb |
| Host | smart-3dc99057-3849-46ad-b12c-51ad06df66ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861273149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_zero_del ays.1861273149 |
| Directory | /workspace/91.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_same_source.3150887178 |
| Short name | T2088 |
| Test name | |
| Test status | |
| Simulation time | 328784976 ps |
| CPU time | 27.89 seconds |
| Started | May 30 04:00:19 PM PDT 24 |
| Finished | May 30 04:00:48 PM PDT 24 |
| Peak memory | 573048 kb |
| Host | smart-e92cad36-8b38-4953-94a5-7f696c7ac18e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150887178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_same_source.3150887178 |
| Directory | /workspace/91.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke.3040991019 |
| Short name | T2273 |
| Test name | |
| Test status | |
| Simulation time | 132681087 ps |
| CPU time | 7.91 seconds |
| Started | May 30 04:00:20 PM PDT 24 |
| Finished | May 30 04:00:29 PM PDT 24 |
| Peak memory | 563408 kb |
| Host | smart-231bd016-4cb8-423e-980e-8664e38ce5f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040991019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke.3040991019 |
| Directory | /workspace/91.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_large_delays.3432868393 |
| Short name | T2310 |
| Test name | |
| Test status | |
| Simulation time | 7014482064 ps |
| CPU time | 74.48 seconds |
| Started | May 30 04:00:20 PM PDT 24 |
| Finished | May 30 04:01:35 PM PDT 24 |
| Peak memory | 564964 kb |
| Host | smart-cc2578b5-b9fa-446e-9fa5-274ef2b32c8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432868393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_large_delays.3432868393 |
| Directory | /workspace/91.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.3546672011 |
| Short name | T2484 |
| Test name | |
| Test status | |
| Simulation time | 4725711563 ps |
| CPU time | 88.38 seconds |
| Started | May 30 04:00:20 PM PDT 24 |
| Finished | May 30 04:01:49 PM PDT 24 |
| Peak memory | 564924 kb |
| Host | smart-b2482496-37a7-4cc2-895c-2e9977873fb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546672011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_slow_rsp.3546672011 |
| Directory | /workspace/91.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.1152791073 |
| Short name | T2335 |
| Test name | |
| Test status | |
| Simulation time | 41820228 ps |
| CPU time | 6.49 seconds |
| Started | May 30 04:00:19 PM PDT 24 |
| Finished | May 30 04:00:27 PM PDT 24 |
| Peak memory | 563300 kb |
| Host | smart-c94d1005-53d5-4527-9430-1e24d8597859 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152791073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_zero_delay s.1152791073 |
| Directory | /workspace/91.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all.1161371626 |
| Short name | T1767 |
| Test name | |
| Test status | |
| Simulation time | 6349189384 ps |
| CPU time | 259.36 seconds |
| Started | May 30 04:00:20 PM PDT 24 |
| Finished | May 30 04:04:41 PM PDT 24 |
| Peak memory | 573288 kb |
| Host | smart-e376cf3f-c775-49c6-ace2-ec0260a28d52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161371626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all.1161371626 |
| Directory | /workspace/91.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.1681028956 |
| Short name | T1581 |
| Test name | |
| Test status | |
| Simulation time | 1542393865 ps |
| CPU time | 104.7 seconds |
| Started | May 30 04:00:39 PM PDT 24 |
| Finished | May 30 04:02:24 PM PDT 24 |
| Peak memory | 575080 kb |
| Host | smart-4d1f1076-a98a-4411-a68c-cdb4f993cf6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681028956 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_error.1681028956 |
| Directory | /workspace/91.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.727407720 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 153050835 ps |
| CPU time | 64.46 seconds |
| Started | May 30 04:00:20 PM PDT 24 |
| Finished | May 30 04:01:26 PM PDT 24 |
| Peak memory | 573088 kb |
| Host | smart-fdaf73be-4d3d-425d-a246-2a7d9a5a0914 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727407720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_ with_rand_reset.727407720 |
| Directory | /workspace/91.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.1827157361 |
| Short name | T1698 |
| Test name | |
| Test status | |
| Simulation time | 2246179711 ps |
| CPU time | 240.73 seconds |
| Started | May 30 04:00:30 PM PDT 24 |
| Finished | May 30 04:04:32 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-ba358e75-f99e-4feb-a43d-c08252f236ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827157361 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_al l_with_reset_error.1827157361 |
| Directory | /workspace/91.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_unmapped_addr.2247425782 |
| Short name | T1449 |
| Test name | |
| Test status | |
| Simulation time | 323659044 ps |
| CPU time | 16.37 seconds |
| Started | May 30 04:00:20 PM PDT 24 |
| Finished | May 30 04:00:37 PM PDT 24 |
| Peak memory | 572980 kb |
| Host | smart-53786fcb-f480-430c-9e04-901d8d3e481d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247425782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_unmapped_addr.2247425782 |
| Directory | /workspace/91.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device.4211028568 |
| Short name | T1569 |
| Test name | |
| Test status | |
| Simulation time | 918737003 ps |
| CPU time | 71.94 seconds |
| Started | May 30 04:00:28 PM PDT 24 |
| Finished | May 30 04:01:40 PM PDT 24 |
| Peak memory | 573048 kb |
| Host | smart-0b8c1110-6db4-4095-a473-49585bdad432 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211028568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device .4211028568 |
| Directory | /workspace/92.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.3134970176 |
| Short name | T2373 |
| Test name | |
| Test status | |
| Simulation time | 64673111950 ps |
| CPU time | 1116.15 seconds |
| Started | May 30 04:00:35 PM PDT 24 |
| Finished | May 30 04:19:12 PM PDT 24 |
| Peak memory | 573212 kb |
| Host | smart-d3e27f47-e1bf-4293-8f5d-24bef1348b4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134970176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_ device_slow_rsp.3134970176 |
| Directory | /workspace/92.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.1541369127 |
| Short name | T2835 |
| Test name | |
| Test status | |
| Simulation time | 891547237 ps |
| CPU time | 36.47 seconds |
| Started | May 30 04:00:36 PM PDT 24 |
| Finished | May 30 04:01:13 PM PDT 24 |
| Peak memory | 572916 kb |
| Host | smart-827f3229-1d38-4751-9f1b-17458cd3ad27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541369127 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_and_unmapped_add r.1541369127 |
| Directory | /workspace/92.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_random.3445328236 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 2406301183 ps |
| CPU time | 81.92 seconds |
| Started | May 30 04:00:31 PM PDT 24 |
| Finished | May 30 04:01:54 PM PDT 24 |
| Peak memory | 572980 kb |
| Host | smart-7eed2555-31eb-4021-bfcd-1c8516419e54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445328236 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_random.3445328236 |
| Directory | /workspace/92.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random.4214965945 |
| Short name | T1517 |
| Test name | |
| Test status | |
| Simulation time | 132158477 ps |
| CPU time | 14.65 seconds |
| Started | May 30 04:00:37 PM PDT 24 |
| Finished | May 30 04:00:52 PM PDT 24 |
| Peak memory | 572976 kb |
| Host | smart-22d3bebd-6e38-4bd6-9a5c-1187f50dbf8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214965945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random.4214965945 |
| Directory | /workspace/92.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_large_delays.3793370618 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 34924422943 ps |
| CPU time | 408.39 seconds |
| Started | May 30 04:00:29 PM PDT 24 |
| Finished | May 30 04:07:19 PM PDT 24 |
| Peak memory | 573148 kb |
| Host | smart-ecd02966-10bd-4959-a5b0-f616c0f804ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793370618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_large_delays.3793370618 |
| Directory | /workspace/92.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_slow_rsp.1812253492 |
| Short name | T1566 |
| Test name | |
| Test status | |
| Simulation time | 2771278137 ps |
| CPU time | 45.32 seconds |
| Started | May 30 04:00:36 PM PDT 24 |
| Finished | May 30 04:01:22 PM PDT 24 |
| Peak memory | 563444 kb |
| Host | smart-563315c5-06e9-40cb-bbd3-718507bc8061 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812253492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_slow_rsp.1812253492 |
| Directory | /workspace/92.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.2166507014 |
| Short name | T1830 |
| Test name | |
| Test status | |
| Simulation time | 367966064 ps |
| CPU time | 31.48 seconds |
| Started | May 30 04:00:29 PM PDT 24 |
| Finished | May 30 04:01:02 PM PDT 24 |
| Peak memory | 573064 kb |
| Host | smart-c38e280b-7bb7-4a91-bc54-77ab208f5c41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166507014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_zero_del ays.2166507014 |
| Directory | /workspace/92.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_same_source.3560825215 |
| Short name | T2781 |
| Test name | |
| Test status | |
| Simulation time | 294886553 ps |
| CPU time | 21.68 seconds |
| Started | May 30 04:00:29 PM PDT 24 |
| Finished | May 30 04:00:52 PM PDT 24 |
| Peak memory | 573028 kb |
| Host | smart-eb07e442-435f-46a9-8e3e-5cef4c1f8dfe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560825215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_same_source.3560825215 |
| Directory | /workspace/92.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke.415263089 |
| Short name | T2127 |
| Test name | |
| Test status | |
| Simulation time | 263767586 ps |
| CPU time | 10.38 seconds |
| Started | May 30 04:00:36 PM PDT 24 |
| Finished | May 30 04:00:47 PM PDT 24 |
| Peak memory | 564840 kb |
| Host | smart-63ded489-98ed-44a3-a906-fb9ee6663c8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415263089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke.415263089 |
| Directory | /workspace/92.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_large_delays.438778578 |
| Short name | T2328 |
| Test name | |
| Test status | |
| Simulation time | 9609932440 ps |
| CPU time | 107.2 seconds |
| Started | May 30 04:00:29 PM PDT 24 |
| Finished | May 30 04:02:17 PM PDT 24 |
| Peak memory | 564952 kb |
| Host | smart-a5aa88ba-7299-4190-b8e0-f7936a44838f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438778578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_large_delays.438778578 |
| Directory | /workspace/92.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.1274113037 |
| Short name | T2080 |
| Test name | |
| Test status | |
| Simulation time | 3351557976 ps |
| CPU time | 58.98 seconds |
| Started | May 30 04:00:31 PM PDT 24 |
| Finished | May 30 04:01:31 PM PDT 24 |
| Peak memory | 564864 kb |
| Host | smart-4d47fa63-85da-4786-a053-59b2c74eb127 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274113037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_slow_rsp.1274113037 |
| Directory | /workspace/92.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.2897651918 |
| Short name | T1794 |
| Test name | |
| Test status | |
| Simulation time | 43071295 ps |
| CPU time | 6.22 seconds |
| Started | May 30 04:00:29 PM PDT 24 |
| Finished | May 30 04:00:36 PM PDT 24 |
| Peak memory | 564776 kb |
| Host | smart-eac4a27b-7e7d-4240-92a4-d7be277bfc64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897651918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_zero_delay s.2897651918 |
| Directory | /workspace/92.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all.2800175901 |
| Short name | T2620 |
| Test name | |
| Test status | |
| Simulation time | 777751804 ps |
| CPU time | 77.85 seconds |
| Started | May 30 04:00:29 PM PDT 24 |
| Finished | May 30 04:01:48 PM PDT 24 |
| Peak memory | 575212 kb |
| Host | smart-33dc711d-fc69-4c5a-a6e5-9fd4e32b067f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800175901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all.2800175901 |
| Directory | /workspace/92.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_error.3716676573 |
| Short name | T1713 |
| Test name | |
| Test status | |
| Simulation time | 2062946728 ps |
| CPU time | 194.8 seconds |
| Started | May 30 04:00:38 PM PDT 24 |
| Finished | May 30 04:03:54 PM PDT 24 |
| Peak memory | 573124 kb |
| Host | smart-f13106ef-4422-4e0e-b8a7-25661c98927c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716676573 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_error.3716676573 |
| Directory | /workspace/92.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.405212790 |
| Short name | T2463 |
| Test name | |
| Test status | |
| Simulation time | 2981115084 ps |
| CPU time | 512.61 seconds |
| Started | May 30 04:00:30 PM PDT 24 |
| Finished | May 30 04:09:04 PM PDT 24 |
| Peak memory | 573136 kb |
| Host | smart-fb077602-9acb-4f5b-8419-be2fcd803624 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405212790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_ with_rand_reset.405212790 |
| Directory | /workspace/92.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.3671166491 |
| Short name | T2214 |
| Test name | |
| Test status | |
| Simulation time | 298187417 ps |
| CPU time | 66.45 seconds |
| Started | May 30 04:00:30 PM PDT 24 |
| Finished | May 30 04:01:38 PM PDT 24 |
| Peak memory | 573092 kb |
| Host | smart-f5962661-3bba-4198-b7ec-8b516ebeb53a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671166491 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_al l_with_reset_error.3671166491 |
| Directory | /workspace/92.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_unmapped_addr.4043700965 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 153198560 ps |
| CPU time | 18.76 seconds |
| Started | May 30 04:00:38 PM PDT 24 |
| Finished | May 30 04:00:58 PM PDT 24 |
| Peak memory | 573144 kb |
| Host | smart-44f95572-7180-4a0c-bce2-c57f91d18a53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043700965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_unmapped_addr.4043700965 |
| Directory | /workspace/92.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device.52663851 |
| Short name | T1610 |
| Test name | |
| Test status | |
| Simulation time | 1366728582 ps |
| CPU time | 90.03 seconds |
| Started | May 30 04:00:33 PM PDT 24 |
| Finished | May 30 04:02:03 PM PDT 24 |
| Peak memory | 573088 kb |
| Host | smart-b6905349-06e5-41cf-badf-f622f55955c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52663851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device.52663851 |
| Directory | /workspace/93.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.2396372212 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 115331755856 ps |
| CPU time | 2159.48 seconds |
| Started | May 30 04:00:28 PM PDT 24 |
| Finished | May 30 04:36:29 PM PDT 24 |
| Peak memory | 573256 kb |
| Host | smart-33f86cf8-837b-425e-9fbc-d45ec32122e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396372212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_ device_slow_rsp.2396372212 |
| Directory | /workspace/93.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.773728533 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 1225214700 ps |
| CPU time | 48.38 seconds |
| Started | May 30 04:00:30 PM PDT 24 |
| Finished | May 30 04:01:20 PM PDT 24 |
| Peak memory | 572884 kb |
| Host | smart-b5bfd43b-9c66-40bd-94ee-dfd4a6a0f11f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773728533 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_and_unmapped_addr .773728533 |
| Directory | /workspace/93.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_random.2773782831 |
| Short name | T2277 |
| Test name | |
| Test status | |
| Simulation time | 1888960972 ps |
| CPU time | 53.07 seconds |
| Started | May 30 04:00:28 PM PDT 24 |
| Finished | May 30 04:01:23 PM PDT 24 |
| Peak memory | 572912 kb |
| Host | smart-cd52a13f-cad6-49b4-9aa3-2119b399ad74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773782831 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_random.2773782831 |
| Directory | /workspace/93.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random.431936242 |
| Short name | T1578 |
| Test name | |
| Test status | |
| Simulation time | 1866247644 ps |
| CPU time | 63.28 seconds |
| Started | May 30 04:00:34 PM PDT 24 |
| Finished | May 30 04:01:37 PM PDT 24 |
| Peak memory | 573052 kb |
| Host | smart-39a432dd-5e0d-42ac-bc18-3106436e8bc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431936242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random.431936242 |
| Directory | /workspace/93.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_large_delays.1534357875 |
| Short name | T2622 |
| Test name | |
| Test status | |
| Simulation time | 111119276445 ps |
| CPU time | 1356.12 seconds |
| Started | May 30 04:00:32 PM PDT 24 |
| Finished | May 30 04:23:09 PM PDT 24 |
| Peak memory | 573200 kb |
| Host | smart-7ce0707b-4791-4824-8630-b8810f6fdeae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534357875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_large_delays.1534357875 |
| Directory | /workspace/93.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.3890468571 |
| Short name | T1693 |
| Test name | |
| Test status | |
| Simulation time | 36187554637 ps |
| CPU time | 689.42 seconds |
| Started | May 30 04:00:34 PM PDT 24 |
| Finished | May 30 04:12:05 PM PDT 24 |
| Peak memory | 573112 kb |
| Host | smart-74bc7b35-efc8-450a-941d-d2cdbbc0fed2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890468571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_slow_rsp.3890468571 |
| Directory | /workspace/93.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_zero_delays.2811412758 |
| Short name | T1583 |
| Test name | |
| Test status | |
| Simulation time | 388810540 ps |
| CPU time | 38.46 seconds |
| Started | May 30 04:00:30 PM PDT 24 |
| Finished | May 30 04:01:09 PM PDT 24 |
| Peak memory | 573008 kb |
| Host | smart-3231943a-d4c4-4f35-a36e-5ee3ac72f491 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811412758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_zero_del ays.2811412758 |
| Directory | /workspace/93.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_same_source.1462377362 |
| Short name | T2408 |
| Test name | |
| Test status | |
| Simulation time | 2470878720 ps |
| CPU time | 78.44 seconds |
| Started | May 30 04:00:30 PM PDT 24 |
| Finished | May 30 04:01:50 PM PDT 24 |
| Peak memory | 573088 kb |
| Host | smart-a020181e-9705-497e-b22b-5a0912a3e25b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462377362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_same_source.1462377362 |
| Directory | /workspace/93.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke.3835116955 |
| Short name | T1731 |
| Test name | |
| Test status | |
| Simulation time | 44981786 ps |
| CPU time | 6.29 seconds |
| Started | May 30 04:00:34 PM PDT 24 |
| Finished | May 30 04:00:41 PM PDT 24 |
| Peak memory | 563352 kb |
| Host | smart-c2c49e6f-42d2-4365-8d25-3a873cac661f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835116955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke.3835116955 |
| Directory | /workspace/93.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_large_delays.210119207 |
| Short name | T1425 |
| Test name | |
| Test status | |
| Simulation time | 7387056639 ps |
| CPU time | 82.99 seconds |
| Started | May 30 04:00:32 PM PDT 24 |
| Finished | May 30 04:01:56 PM PDT 24 |
| Peak memory | 564912 kb |
| Host | smart-30d64fef-cdff-4f88-ab44-2c4da9afa63d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210119207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_large_delays.210119207 |
| Directory | /workspace/93.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.216456950 |
| Short name | T1692 |
| Test name | |
| Test status | |
| Simulation time | 4712258230 ps |
| CPU time | 83.13 seconds |
| Started | May 30 04:00:29 PM PDT 24 |
| Finished | May 30 04:01:53 PM PDT 24 |
| Peak memory | 564976 kb |
| Host | smart-78fff675-e336-47b0-a99e-521dc6cc0518 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216456950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_slow_rsp.216456950 |
| Directory | /workspace/93.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_zero_delays.342070727 |
| Short name | T1975 |
| Test name | |
| Test status | |
| Simulation time | 47003353 ps |
| CPU time | 6.51 seconds |
| Started | May 30 04:00:28 PM PDT 24 |
| Finished | May 30 04:00:36 PM PDT 24 |
| Peak memory | 564816 kb |
| Host | smart-d0632d98-7e4c-498d-8f91-20ae68dbd2e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342070727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_zero_delays .342070727 |
| Directory | /workspace/93.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all.1340587564 |
| Short name | T2271 |
| Test name | |
| Test status | |
| Simulation time | 1878748302 ps |
| CPU time | 154.15 seconds |
| Started | May 30 04:00:51 PM PDT 24 |
| Finished | May 30 04:03:26 PM PDT 24 |
| Peak memory | 575224 kb |
| Host | smart-474f29d4-e3f5-4b56-86bc-fb54b6dec352 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340587564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all.1340587564 |
| Directory | /workspace/93.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.507736743 |
| Short name | T1744 |
| Test name | |
| Test status | |
| Simulation time | 11890018907 ps |
| CPU time | 436.78 seconds |
| Started | May 30 04:00:44 PM PDT 24 |
| Finished | May 30 04:08:02 PM PDT 24 |
| Peak memory | 573236 kb |
| Host | smart-437c15f2-bf82-4b62-981f-8dd46f55c0d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507736743 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_error.507736743 |
| Directory | /workspace/93.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.1678260277 |
| Short name | T2208 |
| Test name | |
| Test status | |
| Simulation time | 6512982900 ps |
| CPU time | 721.71 seconds |
| Started | May 30 04:00:44 PM PDT 24 |
| Finished | May 30 04:12:46 PM PDT 24 |
| Peak memory | 576496 kb |
| Host | smart-533c264c-b9e7-4cc0-acf1-8813ac68baa3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678260277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all _with_rand_reset.1678260277 |
| Directory | /workspace/93.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.607292142 |
| Short name | T2793 |
| Test name | |
| Test status | |
| Simulation time | 313973093 ps |
| CPU time | 83.54 seconds |
| Started | May 30 04:00:39 PM PDT 24 |
| Finished | May 30 04:02:03 PM PDT 24 |
| Peak memory | 573064 kb |
| Host | smart-3e773d9a-3df2-4f63-9c75-c6e6ab9d9ad2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607292142 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all _with_reset_error.607292142 |
| Directory | /workspace/93.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_unmapped_addr.4099681254 |
| Short name | T1652 |
| Test name | |
| Test status | |
| Simulation time | 335299330 ps |
| CPU time | 15.5 seconds |
| Started | May 30 04:00:39 PM PDT 24 |
| Finished | May 30 04:00:56 PM PDT 24 |
| Peak memory | 573004 kb |
| Host | smart-a8620399-3670-49c1-913f-9889b268ff07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099681254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_unmapped_addr.4099681254 |
| Directory | /workspace/93.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device.3987452049 |
| Short name | T1866 |
| Test name | |
| Test status | |
| Simulation time | 349945539 ps |
| CPU time | 16.7 seconds |
| Started | May 30 04:00:52 PM PDT 24 |
| Finished | May 30 04:01:09 PM PDT 24 |
| Peak memory | 564868 kb |
| Host | smart-62cdb86a-c1c0-4b9b-99bc-675faa45f07a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987452049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device .3987452049 |
| Directory | /workspace/94.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.1705904404 |
| Short name | T1858 |
| Test name | |
| Test status | |
| Simulation time | 32291313310 ps |
| CPU time | 634.36 seconds |
| Started | May 30 04:00:42 PM PDT 24 |
| Finished | May 30 04:11:17 PM PDT 24 |
| Peak memory | 573232 kb |
| Host | smart-12ed688c-436c-4002-8b57-940b2ecedb3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705904404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_ device_slow_rsp.1705904404 |
| Directory | /workspace/94.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.1515429306 |
| Short name | T2709 |
| Test name | |
| Test status | |
| Simulation time | 65277222 ps |
| CPU time | 9.88 seconds |
| Started | May 30 04:00:41 PM PDT 24 |
| Finished | May 30 04:00:52 PM PDT 24 |
| Peak memory | 572860 kb |
| Host | smart-25d283e0-c1a0-4f27-94bc-a96941563739 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515429306 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_and_unmapped_add r.1515429306 |
| Directory | /workspace/94.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_random.288116692 |
| Short name | T2068 |
| Test name | |
| Test status | |
| Simulation time | 1980566890 ps |
| CPU time | 68.98 seconds |
| Started | May 30 04:00:40 PM PDT 24 |
| Finished | May 30 04:01:50 PM PDT 24 |
| Peak memory | 572932 kb |
| Host | smart-6559c0f5-1263-44a6-b75e-8f017d7db6fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288116692 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_random.288116692 |
| Directory | /workspace/94.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random.2522421786 |
| Short name | T2567 |
| Test name | |
| Test status | |
| Simulation time | 518770036 ps |
| CPU time | 42.53 seconds |
| Started | May 30 04:00:39 PM PDT 24 |
| Finished | May 30 04:01:23 PM PDT 24 |
| Peak memory | 573088 kb |
| Host | smart-ba090d36-2bd2-4e13-a24c-93c9db80eacd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522421786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random.2522421786 |
| Directory | /workspace/94.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_large_delays.1413066167 |
| Short name | T2087 |
| Test name | |
| Test status | |
| Simulation time | 66384452469 ps |
| CPU time | 890.28 seconds |
| Started | May 30 04:00:42 PM PDT 24 |
| Finished | May 30 04:15:34 PM PDT 24 |
| Peak memory | 573188 kb |
| Host | smart-3f0a28a5-aa72-493d-b663-8819f9ab2104 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413066167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_large_delays.1413066167 |
| Directory | /workspace/94.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_slow_rsp.3910278372 |
| Short name | T2375 |
| Test name | |
| Test status | |
| Simulation time | 10536130525 ps |
| CPU time | 178.69 seconds |
| Started | May 30 04:00:42 PM PDT 24 |
| Finished | May 30 04:03:42 PM PDT 24 |
| Peak memory | 573168 kb |
| Host | smart-67c2ad72-2eab-4d1a-8a29-1e2b086a9a86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910278372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_slow_rsp.3910278372 |
| Directory | /workspace/94.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_zero_delays.2271363176 |
| Short name | T1718 |
| Test name | |
| Test status | |
| Simulation time | 180064968 ps |
| CPU time | 18.54 seconds |
| Started | May 30 04:00:40 PM PDT 24 |
| Finished | May 30 04:00:59 PM PDT 24 |
| Peak memory | 573016 kb |
| Host | smart-2ca15a30-bc3e-444b-a22d-9d60a7d15655 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271363176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_zero_del ays.2271363176 |
| Directory | /workspace/94.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_same_source.1407589231 |
| Short name | T1592 |
| Test name | |
| Test status | |
| Simulation time | 407339049 ps |
| CPU time | 15.01 seconds |
| Started | May 30 04:00:51 PM PDT 24 |
| Finished | May 30 04:01:07 PM PDT 24 |
| Peak memory | 573052 kb |
| Host | smart-68c5fc8b-d6d1-4801-83e4-f51b350cb899 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407589231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_same_source.1407589231 |
| Directory | /workspace/94.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke.2959339544 |
| Short name | T1350 |
| Test name | |
| Test status | |
| Simulation time | 53417362 ps |
| CPU time | 6.34 seconds |
| Started | May 30 04:00:40 PM PDT 24 |
| Finished | May 30 04:00:47 PM PDT 24 |
| Peak memory | 563376 kb |
| Host | smart-1d49a35c-1770-449e-81c5-3351e126101a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959339544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke.2959339544 |
| Directory | /workspace/94.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_large_delays.2787541794 |
| Short name | T2037 |
| Test name | |
| Test status | |
| Simulation time | 8376064580 ps |
| CPU time | 86.28 seconds |
| Started | May 30 04:00:42 PM PDT 24 |
| Finished | May 30 04:02:09 PM PDT 24 |
| Peak memory | 564948 kb |
| Host | smart-ccd018a0-d476-45f7-932b-b11bb504566f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787541794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_large_delays.2787541794 |
| Directory | /workspace/94.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.670500636 |
| Short name | T2290 |
| Test name | |
| Test status | |
| Simulation time | 3680714984 ps |
| CPU time | 60.03 seconds |
| Started | May 30 04:00:51 PM PDT 24 |
| Finished | May 30 04:01:52 PM PDT 24 |
| Peak memory | 563452 kb |
| Host | smart-2d85f9a9-89e3-4eff-b756-4fe3e73e60f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670500636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_slow_rsp.670500636 |
| Directory | /workspace/94.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_zero_delays.3769182073 |
| Short name | T1824 |
| Test name | |
| Test status | |
| Simulation time | 49489285 ps |
| CPU time | 6.2 seconds |
| Started | May 30 04:00:40 PM PDT 24 |
| Finished | May 30 04:00:47 PM PDT 24 |
| Peak memory | 564808 kb |
| Host | smart-7da6fcec-ee49-4658-b74e-756b087ab6e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769182073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_zero_delay s.3769182073 |
| Directory | /workspace/94.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all.1227993754 |
| Short name | T2658 |
| Test name | |
| Test status | |
| Simulation time | 10488805116 ps |
| CPU time | 413.73 seconds |
| Started | May 30 04:00:39 PM PDT 24 |
| Finished | May 30 04:07:34 PM PDT 24 |
| Peak memory | 573208 kb |
| Host | smart-b46c72b0-786f-4b72-99a7-914cb4c152b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227993754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all.1227993754 |
| Directory | /workspace/94.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_error.1104918240 |
| Short name | T2159 |
| Test name | |
| Test status | |
| Simulation time | 11874381567 ps |
| CPU time | 448.96 seconds |
| Started | May 30 04:00:52 PM PDT 24 |
| Finished | May 30 04:08:22 PM PDT 24 |
| Peak memory | 573172 kb |
| Host | smart-219580d0-42e5-4f5f-8e73-eebadeb91b28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104918240 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_error.1104918240 |
| Directory | /workspace/94.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.128771205 |
| Short name | T2468 |
| Test name | |
| Test status | |
| Simulation time | 468706004 ps |
| CPU time | 76.22 seconds |
| Started | May 30 04:00:40 PM PDT 24 |
| Finished | May 30 04:01:57 PM PDT 24 |
| Peak memory | 573192 kb |
| Host | smart-a5cf6baf-7ca6-44b0-bafb-0706d9350ae5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128771205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_ with_rand_reset.128771205 |
| Directory | /workspace/94.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.3378197926 |
| Short name | T2196 |
| Test name | |
| Test status | |
| Simulation time | 415319208 ps |
| CPU time | 136.35 seconds |
| Started | May 30 04:00:56 PM PDT 24 |
| Finished | May 30 04:03:13 PM PDT 24 |
| Peak memory | 573032 kb |
| Host | smart-cc61a2db-063c-44f0-b247-caccdc50e6b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378197926 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_al l_with_reset_error.3378197926 |
| Directory | /workspace/94.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_unmapped_addr.2295292919 |
| Short name | T1519 |
| Test name | |
| Test status | |
| Simulation time | 1353275855 ps |
| CPU time | 54.63 seconds |
| Started | May 30 04:00:51 PM PDT 24 |
| Finished | May 30 04:01:47 PM PDT 24 |
| Peak memory | 573100 kb |
| Host | smart-b37dcc9e-b10e-4cc0-9b24-216b72d2882e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295292919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_unmapped_addr.2295292919 |
| Directory | /workspace/94.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device.1511798408 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 3466521808 ps |
| CPU time | 137.84 seconds |
| Started | May 30 04:00:52 PM PDT 24 |
| Finished | May 30 04:03:11 PM PDT 24 |
| Peak memory | 573108 kb |
| Host | smart-5cf538c7-cf3d-4131-bd74-f88ad65032f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511798408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device .1511798408 |
| Directory | /workspace/95.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.2850726903 |
| Short name | T2596 |
| Test name | |
| Test status | |
| Simulation time | 69561409794 ps |
| CPU time | 1318.16 seconds |
| Started | May 30 04:00:51 PM PDT 24 |
| Finished | May 30 04:22:50 PM PDT 24 |
| Peak memory | 573296 kb |
| Host | smart-563dd394-80a9-46fd-b796-3583df665dea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850726903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_ device_slow_rsp.2850726903 |
| Directory | /workspace/95.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.2825287941 |
| Short name | T2321 |
| Test name | |
| Test status | |
| Simulation time | 497244803 ps |
| CPU time | 20.46 seconds |
| Started | May 30 04:00:56 PM PDT 24 |
| Finished | May 30 04:01:18 PM PDT 24 |
| Peak memory | 573916 kb |
| Host | smart-b09fc293-1699-4db5-a857-7774d9f78c03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825287941 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_and_unmapped_add r.2825287941 |
| Directory | /workspace/95.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_random.3861785101 |
| Short name | T2779 |
| Test name | |
| Test status | |
| Simulation time | 1295456717 ps |
| CPU time | 41.82 seconds |
| Started | May 30 04:00:52 PM PDT 24 |
| Finished | May 30 04:01:35 PM PDT 24 |
| Peak memory | 572924 kb |
| Host | smart-398e2452-abf4-4b57-a743-448ef40801d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861785101 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_random.3861785101 |
| Directory | /workspace/95.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random.3289236975 |
| Short name | T1804 |
| Test name | |
| Test status | |
| Simulation time | 1125026958 ps |
| CPU time | 36.32 seconds |
| Started | May 30 04:01:00 PM PDT 24 |
| Finished | May 30 04:01:38 PM PDT 24 |
| Peak memory | 573060 kb |
| Host | smart-698702fa-1f51-41fa-851d-64258222c453 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289236975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random.3289236975 |
| Directory | /workspace/95.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_large_delays.4054237697 |
| Short name | T2682 |
| Test name | |
| Test status | |
| Simulation time | 50536534145 ps |
| CPU time | 562.09 seconds |
| Started | May 30 04:00:48 PM PDT 24 |
| Finished | May 30 04:10:12 PM PDT 24 |
| Peak memory | 573036 kb |
| Host | smart-05c3a652-91fc-459c-8520-5b8732bd1aec |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054237697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_large_delays.4054237697 |
| Directory | /workspace/95.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_slow_rsp.268723301 |
| Short name | T2263 |
| Test name | |
| Test status | |
| Simulation time | 53858157364 ps |
| CPU time | 1003.6 seconds |
| Started | May 30 04:01:02 PM PDT 24 |
| Finished | May 30 04:17:47 PM PDT 24 |
| Peak memory | 573172 kb |
| Host | smart-f19e55ea-0e22-4a2f-a46d-7736700a0e14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268723301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_slow_rsp.268723301 |
| Directory | /workspace/95.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_zero_delays.2911503171 |
| Short name | T1489 |
| Test name | |
| Test status | |
| Simulation time | 289155439 ps |
| CPU time | 24.17 seconds |
| Started | May 30 04:00:54 PM PDT 24 |
| Finished | May 30 04:01:19 PM PDT 24 |
| Peak memory | 573016 kb |
| Host | smart-a39c7536-5ea8-4f18-ab7c-75a8bf2d4237 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911503171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_zero_del ays.2911503171 |
| Directory | /workspace/95.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_same_source.3537107840 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 281132775 ps |
| CPU time | 22.75 seconds |
| Started | May 30 04:00:53 PM PDT 24 |
| Finished | May 30 04:01:16 PM PDT 24 |
| Peak memory | 573040 kb |
| Host | smart-b82bc685-7fcb-4c53-ab83-e00c48f1339e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537107840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_same_source.3537107840 |
| Directory | /workspace/95.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke.2894628260 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 47973043 ps |
| CPU time | 6.04 seconds |
| Started | May 30 04:01:02 PM PDT 24 |
| Finished | May 30 04:01:09 PM PDT 24 |
| Peak memory | 564808 kb |
| Host | smart-92108c5e-c10f-4101-b8ed-75869b544849 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894628260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke.2894628260 |
| Directory | /workspace/95.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_large_delays.2046320419 |
| Short name | T2538 |
| Test name | |
| Test status | |
| Simulation time | 9236309660 ps |
| CPU time | 97.73 seconds |
| Started | May 30 04:00:51 PM PDT 24 |
| Finished | May 30 04:02:30 PM PDT 24 |
| Peak memory | 564956 kb |
| Host | smart-e1a43cc7-5d08-4822-a988-8f609793b0fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046320419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_large_delays.2046320419 |
| Directory | /workspace/95.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.749630339 |
| Short name | T2108 |
| Test name | |
| Test status | |
| Simulation time | 5992272729 ps |
| CPU time | 103.57 seconds |
| Started | May 30 04:00:53 PM PDT 24 |
| Finished | May 30 04:02:37 PM PDT 24 |
| Peak memory | 563564 kb |
| Host | smart-7ff14624-853f-49b7-af84-7a0a27afe3a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749630339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_slow_rsp.749630339 |
| Directory | /workspace/95.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_zero_delays.1890569041 |
| Short name | T1365 |
| Test name | |
| Test status | |
| Simulation time | 46434232 ps |
| CPU time | 6.16 seconds |
| Started | May 30 04:00:54 PM PDT 24 |
| Finished | May 30 04:01:01 PM PDT 24 |
| Peak memory | 564788 kb |
| Host | smart-a0ba5673-085e-4642-a1bf-02be15894447 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890569041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_zero_delay s.1890569041 |
| Directory | /workspace/95.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all.1648970891 |
| Short name | T2657 |
| Test name | |
| Test status | |
| Simulation time | 3912904806 ps |
| CPU time | 147.69 seconds |
| Started | May 30 04:00:48 PM PDT 24 |
| Finished | May 30 04:03:17 PM PDT 24 |
| Peak memory | 573232 kb |
| Host | smart-d1429be5-eca2-448e-a869-ac578b93ab04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648970891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all.1648970891 |
| Directory | /workspace/95.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.2189882600 |
| Short name | T2184 |
| Test name | |
| Test status | |
| Simulation time | 8460868813 ps |
| CPU time | 333.76 seconds |
| Started | May 30 04:00:57 PM PDT 24 |
| Finished | May 30 04:06:33 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-bfb67af6-c2af-479a-a7bf-25f8f212a0c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189882600 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_error.2189882600 |
| Directory | /workspace/95.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.3106369988 |
| Short name | T2205 |
| Test name | |
| Test status | |
| Simulation time | 596092157 ps |
| CPU time | 179.79 seconds |
| Started | May 30 04:00:48 PM PDT 24 |
| Finished | May 30 04:03:50 PM PDT 24 |
| Peak memory | 573168 kb |
| Host | smart-5c65b889-2194-481b-a3b2-193d6953ccca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106369988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all _with_rand_reset.3106369988 |
| Directory | /workspace/95.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.1919171082 |
| Short name | T2287 |
| Test name | |
| Test status | |
| Simulation time | 1545581387 ps |
| CPU time | 218.93 seconds |
| Started | May 30 04:00:58 PM PDT 24 |
| Finished | May 30 04:04:39 PM PDT 24 |
| Peak memory | 573096 kb |
| Host | smart-ea0fa75c-368b-46c4-83c8-22dd8a74ebba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919171082 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_al l_with_reset_error.1919171082 |
| Directory | /workspace/95.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_unmapped_addr.843021426 |
| Short name | T1428 |
| Test name | |
| Test status | |
| Simulation time | 31574503 ps |
| CPU time | 6.48 seconds |
| Started | May 30 04:01:02 PM PDT 24 |
| Finished | May 30 04:01:10 PM PDT 24 |
| Peak memory | 564880 kb |
| Host | smart-cd8f367f-0d5d-4480-ad86-89fb521c2921 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843021426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_unmapped_addr.843021426 |
| Directory | /workspace/95.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device.1003851147 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 290910002 ps |
| CPU time | 17.08 seconds |
| Started | May 30 04:00:57 PM PDT 24 |
| Finished | May 30 04:01:15 PM PDT 24 |
| Peak memory | 564840 kb |
| Host | smart-c21ad26f-040b-44d7-9008-8c9a2581c10c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003851147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device .1003851147 |
| Directory | /workspace/96.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.2873694910 |
| Short name | T2245 |
| Test name | |
| Test status | |
| Simulation time | 105342719861 ps |
| CPU time | 2022.21 seconds |
| Started | May 30 04:00:56 PM PDT 24 |
| Finished | May 30 04:34:39 PM PDT 24 |
| Peak memory | 573284 kb |
| Host | smart-182f6971-fc19-4d56-b8a7-c9e4b9d36ce9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873694910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_ device_slow_rsp.2873694910 |
| Directory | /workspace/96.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.1833117895 |
| Short name | T1966 |
| Test name | |
| Test status | |
| Simulation time | 102006408 ps |
| CPU time | 12.56 seconds |
| Started | May 30 04:01:09 PM PDT 24 |
| Finished | May 30 04:01:22 PM PDT 24 |
| Peak memory | 572876 kb |
| Host | smart-088c4236-3507-4ee2-ad45-f55d24f2cc4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833117895 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_and_unmapped_add r.1833117895 |
| Directory | /workspace/96.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_random.3711276290 |
| Short name | T2008 |
| Test name | |
| Test status | |
| Simulation time | 1986769643 ps |
| CPU time | 73.03 seconds |
| Started | May 30 04:01:08 PM PDT 24 |
| Finished | May 30 04:02:22 PM PDT 24 |
| Peak memory | 572904 kb |
| Host | smart-603103ac-5bfe-420f-bd98-e4a6965791cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711276290 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_random.3711276290 |
| Directory | /workspace/96.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random.642642900 |
| Short name | T1976 |
| Test name | |
| Test status | |
| Simulation time | 212620421 ps |
| CPU time | 11.06 seconds |
| Started | May 30 04:01:01 PM PDT 24 |
| Finished | May 30 04:01:12 PM PDT 24 |
| Peak memory | 564460 kb |
| Host | smart-ed5a0a58-bb5d-4eff-a8a4-dcb8813b0799 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642642900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random.642642900 |
| Directory | /workspace/96.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_large_delays.806285330 |
| Short name | T2308 |
| Test name | |
| Test status | |
| Simulation time | 91908983932 ps |
| CPU time | 1096.51 seconds |
| Started | May 30 04:01:03 PM PDT 24 |
| Finished | May 30 04:19:20 PM PDT 24 |
| Peak memory | 573012 kb |
| Host | smart-6db9aef1-969a-4def-b73c-3dbbe4ef60a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806285330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_large_delays.806285330 |
| Directory | /workspace/96.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_slow_rsp.2523542761 |
| Short name | T1929 |
| Test name | |
| Test status | |
| Simulation time | 42893311035 ps |
| CPU time | 801.65 seconds |
| Started | May 30 04:00:57 PM PDT 24 |
| Finished | May 30 04:14:20 PM PDT 24 |
| Peak memory | 573192 kb |
| Host | smart-8775708f-2a1c-49fa-8723-1c82d5892781 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523542761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_slow_rsp.2523542761 |
| Directory | /workspace/96.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.3040919790 |
| Short name | T1408 |
| Test name | |
| Test status | |
| Simulation time | 221922507 ps |
| CPU time | 21.41 seconds |
| Started | May 30 04:00:59 PM PDT 24 |
| Finished | May 30 04:01:22 PM PDT 24 |
| Peak memory | 573044 kb |
| Host | smart-53d2b6dc-d08f-4eb3-8a33-858346a3dcd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040919790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_zero_del ays.3040919790 |
| Directory | /workspace/96.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_same_source.3087083188 |
| Short name | T2693 |
| Test name | |
| Test status | |
| Simulation time | 519464682 ps |
| CPU time | 33.53 seconds |
| Started | May 30 04:00:56 PM PDT 24 |
| Finished | May 30 04:01:31 PM PDT 24 |
| Peak memory | 573064 kb |
| Host | smart-b95d9520-790b-408e-b78b-888f1c8ce799 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087083188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_same_source.3087083188 |
| Directory | /workspace/96.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke.4032012154 |
| Short name | T1577 |
| Test name | |
| Test status | |
| Simulation time | 43026820 ps |
| CPU time | 6.3 seconds |
| Started | May 30 04:00:58 PM PDT 24 |
| Finished | May 30 04:01:05 PM PDT 24 |
| Peak memory | 564848 kb |
| Host | smart-3cf73a00-a910-4396-ade3-0f34c7b8c738 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032012154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke.4032012154 |
| Directory | /workspace/96.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.2322189153 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 8938537352 ps |
| CPU time | 93.81 seconds |
| Started | May 30 04:00:59 PM PDT 24 |
| Finished | May 30 04:02:34 PM PDT 24 |
| Peak memory | 564936 kb |
| Host | smart-1f107472-f8dd-4fd6-89aa-9852ffaa0358 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322189153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_large_delays.2322189153 |
| Directory | /workspace/96.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.585736597 |
| Short name | T2407 |
| Test name | |
| Test status | |
| Simulation time | 5722321282 ps |
| CPU time | 97.21 seconds |
| Started | May 30 04:00:56 PM PDT 24 |
| Finished | May 30 04:02:34 PM PDT 24 |
| Peak memory | 564912 kb |
| Host | smart-34117a3f-7151-483b-9d84-54b077e51cd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585736597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_slow_rsp.585736597 |
| Directory | /workspace/96.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.3034470963 |
| Short name | T1659 |
| Test name | |
| Test status | |
| Simulation time | 46035778 ps |
| CPU time | 6.32 seconds |
| Started | May 30 04:01:00 PM PDT 24 |
| Finished | May 30 04:01:08 PM PDT 24 |
| Peak memory | 564784 kb |
| Host | smart-7b7ed996-759a-4892-be19-1102a214357e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034470963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_zero_delay s.3034470963 |
| Directory | /workspace/96.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all.4275455706 |
| Short name | T2844 |
| Test name | |
| Test status | |
| Simulation time | 9154226295 ps |
| CPU time | 344.14 seconds |
| Started | May 30 04:01:05 PM PDT 24 |
| Finished | May 30 04:06:50 PM PDT 24 |
| Peak memory | 573196 kb |
| Host | smart-536ce8f9-6683-43b5-a1b5-7f2d42d4fc3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275455706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all.4275455706 |
| Directory | /workspace/96.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.1415475148 |
| Short name | T2853 |
| Test name | |
| Test status | |
| Simulation time | 1038960396 ps |
| CPU time | 81.65 seconds |
| Started | May 30 04:01:05 PM PDT 24 |
| Finished | May 30 04:02:28 PM PDT 24 |
| Peak memory | 572948 kb |
| Host | smart-4ea5763d-0e83-41a1-b3f0-e8da2c3be1a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415475148 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_error.1415475148 |
| Directory | /workspace/96.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.2475030002 |
| Short name | T1927 |
| Test name | |
| Test status | |
| Simulation time | 422037849 ps |
| CPU time | 168.75 seconds |
| Started | May 30 04:01:07 PM PDT 24 |
| Finished | May 30 04:03:56 PM PDT 24 |
| Peak memory | 573172 kb |
| Host | smart-bdea2915-695d-47d1-84ea-33d9d081454b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475030002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all _with_rand_reset.2475030002 |
| Directory | /workspace/96.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.3703776072 |
| Short name | T1935 |
| Test name | |
| Test status | |
| Simulation time | 489309791 ps |
| CPU time | 153.04 seconds |
| Started | May 30 04:01:07 PM PDT 24 |
| Finished | May 30 04:03:41 PM PDT 24 |
| Peak memory | 573008 kb |
| Host | smart-51f7941f-6276-490a-a23d-a7d6bcc77fc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703776072 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_al l_with_reset_error.3703776072 |
| Directory | /workspace/96.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_unmapped_addr.3782183633 |
| Short name | T1981 |
| Test name | |
| Test status | |
| Simulation time | 612037305 ps |
| CPU time | 25.92 seconds |
| Started | May 30 04:01:06 PM PDT 24 |
| Finished | May 30 04:01:33 PM PDT 24 |
| Peak memory | 573024 kb |
| Host | smart-4aab149e-65de-4fa5-9fff-32f0a4fd6b41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782183633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_unmapped_addr.3782183633 |
| Directory | /workspace/96.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device.4257905440 |
| Short name | T2714 |
| Test name | |
| Test status | |
| Simulation time | 1214014939 ps |
| CPU time | 49.46 seconds |
| Started | May 30 04:01:07 PM PDT 24 |
| Finished | May 30 04:01:57 PM PDT 24 |
| Peak memory | 573020 kb |
| Host | smart-1553f49e-2885-44fb-9bd8-331d0c1d68c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257905440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device .4257905440 |
| Directory | /workspace/97.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.458168332 |
| Short name | T1586 |
| Test name | |
| Test status | |
| Simulation time | 17851785981 ps |
| CPU time | 317.16 seconds |
| Started | May 30 04:01:08 PM PDT 24 |
| Finished | May 30 04:06:27 PM PDT 24 |
| Peak memory | 573140 kb |
| Host | smart-a9d4fc79-293d-4b3d-a7af-40e0a6e8049f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458168332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_d evice_slow_rsp.458168332 |
| Directory | /workspace/97.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.1281042619 |
| Short name | T1330 |
| Test name | |
| Test status | |
| Simulation time | 218720140 ps |
| CPU time | 23.82 seconds |
| Started | May 30 04:01:08 PM PDT 24 |
| Finished | May 30 04:01:33 PM PDT 24 |
| Peak memory | 572864 kb |
| Host | smart-5f073024-6627-4479-af0e-6c40b7cc5186 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281042619 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_and_unmapped_add r.1281042619 |
| Directory | /workspace/97.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_random.1923356425 |
| Short name | T2119 |
| Test name | |
| Test status | |
| Simulation time | 415841787 ps |
| CPU time | 36.17 seconds |
| Started | May 30 04:01:11 PM PDT 24 |
| Finished | May 30 04:01:48 PM PDT 24 |
| Peak memory | 573964 kb |
| Host | smart-3824c1ef-3c3d-4d7f-b618-192682b48ca1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923356425 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_random.1923356425 |
| Directory | /workspace/97.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random.2664665114 |
| Short name | T2518 |
| Test name | |
| Test status | |
| Simulation time | 527523511 ps |
| CPU time | 41.13 seconds |
| Started | May 30 04:01:08 PM PDT 24 |
| Finished | May 30 04:01:50 PM PDT 24 |
| Peak memory | 573056 kb |
| Host | smart-20308cbf-81ab-4b0b-8232-3e444e6b7375 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664665114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random.2664665114 |
| Directory | /workspace/97.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_large_delays.1089106930 |
| Short name | T2536 |
| Test name | |
| Test status | |
| Simulation time | 76944116677 ps |
| CPU time | 838.63 seconds |
| Started | May 30 04:01:11 PM PDT 24 |
| Finished | May 30 04:15:11 PM PDT 24 |
| Peak memory | 573128 kb |
| Host | smart-72877b8a-a604-4cef-ae76-059e8f551570 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089106930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_large_delays.1089106930 |
| Directory | /workspace/97.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_slow_rsp.1160165183 |
| Short name | T2197 |
| Test name | |
| Test status | |
| Simulation time | 62150635716 ps |
| CPU time | 1185.08 seconds |
| Started | May 30 04:01:08 PM PDT 24 |
| Finished | May 30 04:20:54 PM PDT 24 |
| Peak memory | 573152 kb |
| Host | smart-ebbc3eb4-c935-473f-ad8c-9bd0774ba1b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160165183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_slow_rsp.1160165183 |
| Directory | /workspace/97.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.3671949247 |
| Short name | T1426 |
| Test name | |
| Test status | |
| Simulation time | 70156625 ps |
| CPU time | 8.65 seconds |
| Started | May 30 04:01:10 PM PDT 24 |
| Finished | May 30 04:01:19 PM PDT 24 |
| Peak memory | 564832 kb |
| Host | smart-71ba66fc-d2ae-4b58-8cbc-b9940433f7f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671949247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_zero_del ays.3671949247 |
| Directory | /workspace/97.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_same_source.2305124608 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 116773389 ps |
| CPU time | 11.67 seconds |
| Started | May 30 04:01:08 PM PDT 24 |
| Finished | May 30 04:01:20 PM PDT 24 |
| Peak memory | 573036 kb |
| Host | smart-fed3eab6-64cb-40a3-9a2a-e6c50d0c1498 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305124608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_same_source.2305124608 |
| Directory | /workspace/97.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke.3165362991 |
| Short name | T1422 |
| Test name | |
| Test status | |
| Simulation time | 220056644 ps |
| CPU time | 10.01 seconds |
| Started | May 30 04:01:07 PM PDT 24 |
| Finished | May 30 04:01:18 PM PDT 24 |
| Peak memory | 564808 kb |
| Host | smart-54d7c814-f17b-4494-93b1-5d8a451b4d22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165362991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke.3165362991 |
| Directory | /workspace/97.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.1734519377 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 8208971552 ps |
| CPU time | 87.32 seconds |
| Started | May 30 04:01:07 PM PDT 24 |
| Finished | May 30 04:02:36 PM PDT 24 |
| Peak memory | 564924 kb |
| Host | smart-7d8ac3ce-eb8d-4f67-b88e-4058916f5d4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734519377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_large_delays.1734519377 |
| Directory | /workspace/97.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.1814521582 |
| Short name | T2766 |
| Test name | |
| Test status | |
| Simulation time | 5383786670 ps |
| CPU time | 93.41 seconds |
| Started | May 30 04:01:08 PM PDT 24 |
| Finished | May 30 04:02:43 PM PDT 24 |
| Peak memory | 563512 kb |
| Host | smart-08991c39-ecf0-45a7-a622-10321901e4bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814521582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_slow_rsp.1814521582 |
| Directory | /workspace/97.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_zero_delays.874233577 |
| Short name | T2398 |
| Test name | |
| Test status | |
| Simulation time | 53793743 ps |
| CPU time | 7.21 seconds |
| Started | May 30 04:01:07 PM PDT 24 |
| Finished | May 30 04:01:16 PM PDT 24 |
| Peak memory | 564800 kb |
| Host | smart-260115bb-d880-4463-b673-e71d0229879c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874233577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_zero_delays .874233577 |
| Directory | /workspace/97.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all.3641442444 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 1752423260 ps |
| CPU time | 147.36 seconds |
| Started | May 30 04:01:19 PM PDT 24 |
| Finished | May 30 04:03:47 PM PDT 24 |
| Peak memory | 573156 kb |
| Host | smart-fbce74b8-3876-4585-b681-8dd427d7f592 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641442444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all.3641442444 |
| Directory | /workspace/97.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.1848420149 |
| Short name | T1720 |
| Test name | |
| Test status | |
| Simulation time | 9174161691 ps |
| CPU time | 325.31 seconds |
| Started | May 30 04:01:16 PM PDT 24 |
| Finished | May 30 04:06:42 PM PDT 24 |
| Peak memory | 573228 kb |
| Host | smart-7677c09a-a639-49e1-b1f8-b61a98341067 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848420149 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_error.1848420149 |
| Directory | /workspace/97.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.1108049845 |
| Short name | T2821 |
| Test name | |
| Test status | |
| Simulation time | 7554697 ps |
| CPU time | 15.77 seconds |
| Started | May 30 04:01:16 PM PDT 24 |
| Finished | May 30 04:01:32 PM PDT 24 |
| Peak memory | 564808 kb |
| Host | smart-dc922fdf-2611-44ee-a9e0-8baf8bc3e377 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108049845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all _with_rand_reset.1108049845 |
| Directory | /workspace/97.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.573607174 |
| Short name | T1832 |
| Test name | |
| Test status | |
| Simulation time | 2888402560 ps |
| CPU time | 377.06 seconds |
| Started | May 30 04:01:21 PM PDT 24 |
| Finished | May 30 04:07:40 PM PDT 24 |
| Peak memory | 573108 kb |
| Host | smart-a74baca2-5a41-4124-9bce-3c84ccb5a1c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573607174 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all _with_reset_error.573607174 |
| Directory | /workspace/97.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_unmapped_addr.3634960255 |
| Short name | T2575 |
| Test name | |
| Test status | |
| Simulation time | 284676567 ps |
| CPU time | 14.74 seconds |
| Started | May 30 04:01:10 PM PDT 24 |
| Finished | May 30 04:01:26 PM PDT 24 |
| Peak memory | 573072 kb |
| Host | smart-910c1fad-9314-4f92-af17-6b765b1ab206 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634960255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_unmapped_addr.3634960255 |
| Directory | /workspace/97.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device.2784203433 |
| Short name | T1967 |
| Test name | |
| Test status | |
| Simulation time | 505889805 ps |
| CPU time | 45.28 seconds |
| Started | May 30 04:01:22 PM PDT 24 |
| Finished | May 30 04:02:08 PM PDT 24 |
| Peak memory | 573044 kb |
| Host | smart-378a6895-ea4e-4eec-99b4-8be42783cce8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784203433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device .2784203433 |
| Directory | /workspace/98.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.3625228586 |
| Short name | T2397 |
| Test name | |
| Test status | |
| Simulation time | 30761387158 ps |
| CPU time | 604.93 seconds |
| Started | May 30 04:01:23 PM PDT 24 |
| Finished | May 30 04:11:29 PM PDT 24 |
| Peak memory | 573296 kb |
| Host | smart-adb2621f-f293-4192-8be3-e82dd64bf74f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625228586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_ device_slow_rsp.3625228586 |
| Directory | /workspace/98.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.4096218181 |
| Short name | T2790 |
| Test name | |
| Test status | |
| Simulation time | 163155435 ps |
| CPU time | 17.04 seconds |
| Started | May 30 04:01:23 PM PDT 24 |
| Finished | May 30 04:01:41 PM PDT 24 |
| Peak memory | 572840 kb |
| Host | smart-66f6caee-5aaf-42bb-b5da-e0c9c11d8172 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096218181 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_and_unmapped_add r.4096218181 |
| Directory | /workspace/98.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_random.78403295 |
| Short name | T1870 |
| Test name | |
| Test status | |
| Simulation time | 460924833 ps |
| CPU time | 41.66 seconds |
| Started | May 30 04:01:16 PM PDT 24 |
| Finished | May 30 04:01:58 PM PDT 24 |
| Peak memory | 572956 kb |
| Host | smart-a52aad64-ab34-40c3-abd6-23c9534efb75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78403295 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_random.78403295 |
| Directory | /workspace/98.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random.1359680860 |
| Short name | T1991 |
| Test name | |
| Test status | |
| Simulation time | 960261280 ps |
| CPU time | 30.38 seconds |
| Started | May 30 04:01:16 PM PDT 24 |
| Finished | May 30 04:01:47 PM PDT 24 |
| Peak memory | 573036 kb |
| Host | smart-dac15853-5ddb-4501-a5d3-6324b270b802 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359680860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random.1359680860 |
| Directory | /workspace/98.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_slow_rsp.1741308376 |
| Short name | T1483 |
| Test name | |
| Test status | |
| Simulation time | 57603996585 ps |
| CPU time | 1041.01 seconds |
| Started | May 30 04:01:17 PM PDT 24 |
| Finished | May 30 04:18:39 PM PDT 24 |
| Peak memory | 573212 kb |
| Host | smart-663b5d49-c7a5-4046-927c-7071be51fa6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741308376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_slow_rsp.1741308376 |
| Directory | /workspace/98.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_zero_delays.4045350107 |
| Short name | T2598 |
| Test name | |
| Test status | |
| Simulation time | 173561390 ps |
| CPU time | 16.25 seconds |
| Started | May 30 04:01:23 PM PDT 24 |
| Finished | May 30 04:01:40 PM PDT 24 |
| Peak memory | 573012 kb |
| Host | smart-c0e41d31-b2ca-49cb-a7c1-5547113c26e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045350107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_zero_del ays.4045350107 |
| Directory | /workspace/98.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_same_source.2214093154 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 577635920 ps |
| CPU time | 40.75 seconds |
| Started | May 30 04:01:20 PM PDT 24 |
| Finished | May 30 04:02:02 PM PDT 24 |
| Peak memory | 572940 kb |
| Host | smart-0b636cb1-faae-4379-8c37-084025a42aec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214093154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_same_source.2214093154 |
| Directory | /workspace/98.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke.1880163026 |
| Short name | T1878 |
| Test name | |
| Test status | |
| Simulation time | 142579122 ps |
| CPU time | 7.28 seconds |
| Started | May 30 04:01:18 PM PDT 24 |
| Finished | May 30 04:01:27 PM PDT 24 |
| Peak memory | 564764 kb |
| Host | smart-57392364-1084-41ad-aae4-3ca9af4fe4f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880163026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke.1880163026 |
| Directory | /workspace/98.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_large_delays.4098982806 |
| Short name | T1645 |
| Test name | |
| Test status | |
| Simulation time | 9348899392 ps |
| CPU time | 94.1 seconds |
| Started | May 30 04:01:23 PM PDT 24 |
| Finished | May 30 04:02:58 PM PDT 24 |
| Peak memory | 564876 kb |
| Host | smart-8242864b-e557-4e33-bcf3-9e8868327684 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098982806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_large_delays.4098982806 |
| Directory | /workspace/98.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.3400875150 |
| Short name | T1650 |
| Test name | |
| Test status | |
| Simulation time | 2880216548 ps |
| CPU time | 51.07 seconds |
| Started | May 30 04:01:23 PM PDT 24 |
| Finished | May 30 04:02:15 PM PDT 24 |
| Peak memory | 564848 kb |
| Host | smart-56a7f529-41f1-4cef-9112-589a2b369545 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400875150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_slow_rsp.3400875150 |
| Directory | /workspace/98.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.3408159926 |
| Short name | T1580 |
| Test name | |
| Test status | |
| Simulation time | 51274078 ps |
| CPU time | 6.62 seconds |
| Started | May 30 04:01:16 PM PDT 24 |
| Finished | May 30 04:01:23 PM PDT 24 |
| Peak memory | 564768 kb |
| Host | smart-16f4cce7-3c07-4b11-a729-ff3d1151ec26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408159926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_zero_delay s.3408159926 |
| Directory | /workspace/98.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all.167192289 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 16387185322 ps |
| CPU time | 826.81 seconds |
| Started | May 30 04:01:19 PM PDT 24 |
| Finished | May 30 04:15:07 PM PDT 24 |
| Peak memory | 573224 kb |
| Host | smart-3d70cc20-c461-4e41-8663-7c9e0b042cbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167192289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all.167192289 |
| Directory | /workspace/98.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.3985426780 |
| Short name | T1972 |
| Test name | |
| Test status | |
| Simulation time | 10312777980 ps |
| CPU time | 406.62 seconds |
| Started | May 30 04:01:17 PM PDT 24 |
| Finished | May 30 04:08:04 PM PDT 24 |
| Peak memory | 573136 kb |
| Host | smart-1d5f12bd-3a39-45a9-bd9a-8b7e46d44aa9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985426780 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_error.3985426780 |
| Directory | /workspace/98.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.3764790083 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 10973256190 ps |
| CPU time | 510.7 seconds |
| Started | May 30 04:01:17 PM PDT 24 |
| Finished | May 30 04:09:49 PM PDT 24 |
| Peak memory | 573272 kb |
| Host | smart-edc5c764-3089-4948-9193-bc110ee08a57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764790083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all _with_rand_reset.3764790083 |
| Directory | /workspace/98.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.343476728 |
| Short name | T2860 |
| Test name | |
| Test status | |
| Simulation time | 11110073 ps |
| CPU time | 18.92 seconds |
| Started | May 30 04:01:24 PM PDT 24 |
| Finished | May 30 04:01:43 PM PDT 24 |
| Peak memory | 564784 kb |
| Host | smart-778d9603-ec09-46e7-8ef3-2dacf127c71c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343476728 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all _with_reset_error.343476728 |
| Directory | /workspace/98.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_unmapped_addr.2234670009 |
| Short name | T2342 |
| Test name | |
| Test status | |
| Simulation time | 1350080796 ps |
| CPU time | 54.35 seconds |
| Started | May 30 04:01:18 PM PDT 24 |
| Finished | May 30 04:02:14 PM PDT 24 |
| Peak memory | 573084 kb |
| Host | smart-712cf184-ed1b-49e7-991c-a8a929e37308 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234670009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_unmapped_addr.2234670009 |
| Directory | /workspace/98.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device.1210304921 |
| Short name | T2651 |
| Test name | |
| Test status | |
| Simulation time | 568495292 ps |
| CPU time | 27.9 seconds |
| Started | May 30 04:01:27 PM PDT 24 |
| Finished | May 30 04:01:56 PM PDT 24 |
| Peak memory | 572904 kb |
| Host | smart-338e0336-50db-47fc-94d2-fcf1c996de81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210304921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device .1210304921 |
| Directory | /workspace/99.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.2840496397 |
| Short name | T2469 |
| Test name | |
| Test status | |
| Simulation time | 43021373775 ps |
| CPU time | 838.05 seconds |
| Started | May 30 04:01:28 PM PDT 24 |
| Finished | May 30 04:15:27 PM PDT 24 |
| Peak memory | 573244 kb |
| Host | smart-84f12bbc-9be4-40f3-8215-8c13a75eddcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840496397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_ device_slow_rsp.2840496397 |
| Directory | /workspace/99.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.2774783476 |
| Short name | T2669 |
| Test name | |
| Test status | |
| Simulation time | 510109097 ps |
| CPU time | 20.57 seconds |
| Started | May 30 04:01:28 PM PDT 24 |
| Finished | May 30 04:01:49 PM PDT 24 |
| Peak memory | 572852 kb |
| Host | smart-95b41c5f-93a1-4dde-a0ba-45caba53e639 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774783476 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_and_unmapped_add r.2774783476 |
| Directory | /workspace/99.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_random.527766128 |
| Short name | T1479 |
| Test name | |
| Test status | |
| Simulation time | 199138669 ps |
| CPU time | 10.33 seconds |
| Started | May 30 04:01:28 PM PDT 24 |
| Finished | May 30 04:01:39 PM PDT 24 |
| Peak memory | 564720 kb |
| Host | smart-0a9b0262-6c4a-4659-94ce-e082988a6e33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527766128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_random.527766128 |
| Directory | /workspace/99.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random.636724177 |
| Short name | T1643 |
| Test name | |
| Test status | |
| Simulation time | 1140373811 ps |
| CPU time | 41.73 seconds |
| Started | May 30 04:01:18 PM PDT 24 |
| Finished | May 30 04:02:00 PM PDT 24 |
| Peak memory | 572968 kb |
| Host | smart-9fcf8812-7ca3-4cb2-9824-36d2daa91dcc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636724177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random.636724177 |
| Directory | /workspace/99.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_large_delays.3187650409 |
| Short name | T2486 |
| Test name | |
| Test status | |
| Simulation time | 79647323546 ps |
| CPU time | 905.28 seconds |
| Started | May 30 04:01:28 PM PDT 24 |
| Finished | May 30 04:16:35 PM PDT 24 |
| Peak memory | 573120 kb |
| Host | smart-2cf0dc34-9741-45f5-a05b-4da45c143979 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187650409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_large_delays.3187650409 |
| Directory | /workspace/99.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.3681699359 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 13000906556 ps |
| CPU time | 216.21 seconds |
| Started | May 30 04:01:26 PM PDT 24 |
| Finished | May 30 04:05:03 PM PDT 24 |
| Peak memory | 573036 kb |
| Host | smart-ee8c903d-c587-4fe0-ae2b-6c313e9464fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681699359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_slow_rsp.3681699359 |
| Directory | /workspace/99.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_zero_delays.2008375864 |
| Short name | T1697 |
| Test name | |
| Test status | |
| Simulation time | 478609631 ps |
| CPU time | 43.48 seconds |
| Started | May 30 04:01:25 PM PDT 24 |
| Finished | May 30 04:02:10 PM PDT 24 |
| Peak memory | 573056 kb |
| Host | smart-4e29f433-d0fc-47ff-8ab8-2c5435773ff9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008375864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_zero_del ays.2008375864 |
| Directory | /workspace/99.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_same_source.1902599836 |
| Short name | T2339 |
| Test name | |
| Test status | |
| Simulation time | 42862574 ps |
| CPU time | 5.96 seconds |
| Started | May 30 04:01:27 PM PDT 24 |
| Finished | May 30 04:01:34 PM PDT 24 |
| Peak memory | 563296 kb |
| Host | smart-b30c51c6-c3e7-464f-812f-6d56908a8e07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902599836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_same_source.1902599836 |
| Directory | /workspace/99.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke.3083957159 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 234917816 ps |
| CPU time | 10.02 seconds |
| Started | May 30 04:01:17 PM PDT 24 |
| Finished | May 30 04:01:28 PM PDT 24 |
| Peak memory | 564832 kb |
| Host | smart-37b5d3fa-6fe3-4a09-b36d-2f6dce2ba57d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083957159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke.3083957159 |
| Directory | /workspace/99.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.1064941763 |
| Short name | T2038 |
| Test name | |
| Test status | |
| Simulation time | 8057717412 ps |
| CPU time | 87.23 seconds |
| Started | May 30 04:01:16 PM PDT 24 |
| Finished | May 30 04:02:44 PM PDT 24 |
| Peak memory | 564980 kb |
| Host | smart-c73798eb-a436-4c86-96d3-6169782c1e02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064941763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_large_delays.1064941763 |
| Directory | /workspace/99.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.3289762487 |
| Short name | T2487 |
| Test name | |
| Test status | |
| Simulation time | 3765345952 ps |
| CPU time | 64.85 seconds |
| Started | May 30 04:01:16 PM PDT 24 |
| Finished | May 30 04:02:21 PM PDT 24 |
| Peak memory | 564836 kb |
| Host | smart-21af4db8-4966-4e78-b9f8-b0015c4478b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289762487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_slow_rsp.3289762487 |
| Directory | /workspace/99.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_zero_delays.1493761423 |
| Short name | T1622 |
| Test name | |
| Test status | |
| Simulation time | 56091334 ps |
| CPU time | 7.22 seconds |
| Started | May 30 04:01:21 PM PDT 24 |
| Finished | May 30 04:01:29 PM PDT 24 |
| Peak memory | 564792 kb |
| Host | smart-6e3e1817-5197-46f5-88f4-7f10caed6506 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493761423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_zero_delay s.1493761423 |
| Directory | /workspace/99.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all.530845566 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 4599175544 ps |
| CPU time | 142.21 seconds |
| Started | May 30 04:01:26 PM PDT 24 |
| Finished | May 30 04:03:49 PM PDT 24 |
| Peak memory | 573320 kb |
| Host | smart-f3cf693f-c273-400c-97bd-55353c71f2ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530845566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all.530845566 |
| Directory | /workspace/99.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.4130600371 |
| Short name | T2168 |
| Test name | |
| Test status | |
| Simulation time | 1251293099 ps |
| CPU time | 103.28 seconds |
| Started | May 30 04:01:26 PM PDT 24 |
| Finished | May 30 04:03:10 PM PDT 24 |
| Peak memory | 573060 kb |
| Host | smart-9e0aa196-0f67-483b-9648-ec70ea3551de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130600371 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_error.4130600371 |
| Directory | /workspace/99.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.1900919587 |
| Short name | T2829 |
| Test name | |
| Test status | |
| Simulation time | 2638164283 ps |
| CPU time | 461.8 seconds |
| Started | May 30 04:01:26 PM PDT 24 |
| Finished | May 30 04:09:09 PM PDT 24 |
| Peak memory | 573212 kb |
| Host | smart-f941980b-78a4-49c9-bbc9-7f7ac8ab2764 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900919587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all _with_rand_reset.1900919587 |
| Directory | /workspace/99.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.996832040 |
| Short name | T1996 |
| Test name | |
| Test status | |
| Simulation time | 846282016 ps |
| CPU time | 267.94 seconds |
| Started | May 30 04:01:26 PM PDT 24 |
| Finished | May 30 04:05:55 PM PDT 24 |
| Peak memory | 573156 kb |
| Host | smart-79b4a61c-9972-408a-b790-7b9ce3579db4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996832040 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all _with_reset_error.996832040 |
| Directory | /workspace/99.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_unmapped_addr.47048401 |
| Short name | T1756 |
| Test name | |
| Test status | |
| Simulation time | 227301586 ps |
| CPU time | 12.06 seconds |
| Started | May 30 04:01:27 PM PDT 24 |
| Finished | May 30 04:01:40 PM PDT 24 |
| Peak memory | 564892 kb |
| Host | smart-15c10a2f-b816-4c5e-9058-c081a3e4e143 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47048401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_unmapped_addr.47048401 |
| Directory | /workspace/99.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_mem_access.7279275 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 12876191356 ps |
| CPU time | 1310.36 seconds |
| Started | May 30 04:03:10 PM PDT 24 |
| Finished | May 30 04:25:02 PM PDT 24 |
| Peak memory | 606628 kb |
| Host | smart-15475ce2-2804-4cc2-993f-97509ccc378f |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7279275 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_mem _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.7279275 |
| Directory | /workspace/0.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1889888996 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 3223347900 ps |
| CPU time | 416.74 seconds |
| Started | May 30 04:11:58 PM PDT 24 |
| Finished | May 30 04:18:55 PM PDT 24 |
| Peak memory | 613104 kb |
| Host | smart-e60d6150-783a-4b6e-a091-e034dd8ee186 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1 889888996 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.1889888996 |
| Directory | /workspace/0.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sival_flash_info_access.179324559 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 3074337078 ps |
| CPU time | 306.64 seconds |
| Started | May 30 04:09:16 PM PDT 24 |
| Finished | May 30 04:14:23 PM PDT 24 |
| Peak memory | 603608 kb |
| Host | smart-94982eba-da3a-4a33-abeb-9fe545204a0c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=179324559 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.179324559 |
| Directory | /workspace/0.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2501426919 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 3143941988 ps |
| CPU time | 246.4 seconds |
| Started | May 30 04:10:16 PM PDT 24 |
| Finished | May 30 04:14:23 PM PDT 24 |
| Peak memory | 603832 kb |
| Host | smart-f0719cf5-ef5e-402d-8c1e-a135dd3a70a4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501 426919 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.2501426919 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3810469062 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 2487850449 ps |
| CPU time | 266.3 seconds |
| Started | May 30 04:13:25 PM PDT 24 |
| Finished | May 30 04:17:52 PM PDT 24 |
| Peak memory | 603704 kb |
| Host | smart-5933a486-3acc-4be9-a9d3-900f51f9389a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810469062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.3810469062 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_entropy.4037178701 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 2010717036 ps |
| CPU time | 222.77 seconds |
| Started | May 30 04:13:35 PM PDT 24 |
| Finished | May 30 04:17:19 PM PDT 24 |
| Peak memory | 603760 kb |
| Host | smart-2c8e5ee2-a3ea-4417-bf21-625334dd8529 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037178701 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_entropy.4037178701 |
| Directory | /workspace/0.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_idle.3479164835 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 3353901256 ps |
| CPU time | 306.72 seconds |
| Started | May 30 04:11:47 PM PDT 24 |
| Finished | May 30 04:16:54 PM PDT 24 |
| Peak memory | 603848 kb |
| Host | smart-b26dc133-f007-46cd-9582-fb336f6d80ad |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479164835 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.3479164835 |
| Directory | /workspace/0.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_masking_off.2095073197 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 3209864897 ps |
| CPU time | 402.24 seconds |
| Started | May 30 04:17:41 PM PDT 24 |
| Finished | May 30 04:24:25 PM PDT 24 |
| Peak memory | 603880 kb |
| Host | smart-209a7b96-127d-4be3-8f3e-5988cc64b814 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095073197 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_masking_off.2095073197 |
| Directory | /workspace/0.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_smoketest.815929566 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 2990666474 ps |
| CPU time | 309.57 seconds |
| Started | May 30 04:14:15 PM PDT 24 |
| Finished | May 30 04:19:26 PM PDT 24 |
| Peak memory | 603476 kb |
| Host | smart-b7b06db1-d4e5-443b-9a9a-90a0836c8838 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815929566 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_smoketest.815929566 |
| Directory | /workspace/0.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_entropy.3071593568 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 2907073441 ps |
| CPU time | 232.13 seconds |
| Started | May 30 04:10:21 PM PDT 24 |
| Finished | May 30 04:14:14 PM PDT 24 |
| Peak memory | 604448 kb |
| Host | smart-eb0820f1-b165-4dc1-9c29-189e14809729 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3071593568 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.3071593568 |
| Directory | /workspace/0.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_escalation.3197319736 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 4194114280 ps |
| CPU time | 466.46 seconds |
| Started | May 30 04:11:27 PM PDT 24 |
| Finished | May 30 04:19:14 PM PDT 24 |
| Peak memory | 612060 kb |
| Host | smart-6378ea3c-90e0-409f-8c99-fa8e6eeea9c3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=3197319736 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.3197319736 |
| Directory | /workspace/0.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.3990368817 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 6241466770 ps |
| CPU time | 1335.4 seconds |
| Started | May 30 04:11:52 PM PDT 24 |
| Finished | May 30 04:34:09 PM PDT 24 |
| Peak memory | 605008 kb |
| Host | smart-d7bb8d8c-1a30-409c-ab4c-538840f900ac |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3990368817 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.3990368817 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.3842626436 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 6897062464 ps |
| CPU time | 1434.26 seconds |
| Started | May 30 04:11:56 PM PDT 24 |
| Finished | May 30 04:35:51 PM PDT 24 |
| Peak memory | 604312 kb |
| Host | smart-edbc7683-a21f-4e93-ae46-0579fd7bdf0b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842626436 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_togg le.3842626436 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1261053507 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 9773685016 ps |
| CPU time | 1263.5 seconds |
| Started | May 30 04:18:56 PM PDT 24 |
| Finished | May 30 04:40:00 PM PDT 24 |
| Peak memory | 605564 kb |
| Host | smart-94697442-dd09-452d-a11a-cf65d42ad16e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261053507 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_sleep_mode_pings.1261053507 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.2387160755 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 4052357560 ps |
| CPU time | 423.16 seconds |
| Started | May 30 04:15:56 PM PDT 24 |
| Finished | May 30 04:23:00 PM PDT 24 |
| Peak memory | 603636 kb |
| Host | smart-a93d605b-d352-4190-ac0d-fe3ab6f16ac6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2387160755 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.2387160755 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.4119596021 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 254557385616 ps |
| CPU time | 11957.4 seconds |
| Started | May 30 04:11:41 PM PDT 24 |
| Finished | May 30 07:31:00 PM PDT 24 |
| Peak memory | 605484 kb |
| Host | smart-1725bca5-3e49-4468-ba0a-ef2ec8d3f56a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4119596021 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.4119596021 |
| Directory | /workspace/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.4280583367 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 6592783900 ps |
| CPU time | 477.5 seconds |
| Started | May 30 04:11:00 PM PDT 24 |
| Finished | May 30 04:18:58 PM PDT 24 |
| Peak memory | 604244 kb |
| Host | smart-207e3cc9-1c87-4b93-8221-e9c2a59e3c13 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4280583367 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.4280583367 |
| Directory | /workspace/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.2426735416 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 3342263640 ps |
| CPU time | 292.48 seconds |
| Started | May 30 04:14:40 PM PDT 24 |
| Finished | May 30 04:19:34 PM PDT 24 |
| Peak memory | 603528 kb |
| Host | smart-9cc0cab0-049c-4aab-9170-a543a802521a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426735416 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_aon_timer_smoketest.2426735416 |
| Directory | /workspace/0.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2645415415 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 8369689128 ps |
| CPU time | 843.44 seconds |
| Started | May 30 04:11:40 PM PDT 24 |
| Finished | May 30 04:25:44 PM PDT 24 |
| Peak memory | 604188 kb |
| Host | smart-e5cb965a-b717-4462-b584-9015c6324623 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2645415415 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.2645415415 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.91188732 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 5777351400 ps |
| CPU time | 528.87 seconds |
| Started | May 30 04:10:23 PM PDT 24 |
| Finished | May 30 04:19:12 PM PDT 24 |
| Peak memory | 604284 kb |
| Host | smart-a53dc333-92c0-4fc5-8565-983ebcb0825a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =91188732 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.91188732 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_ast_clk_outputs.2396916606 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 7954009832 ps |
| CPU time | 1136.29 seconds |
| Started | May 30 04:11:31 PM PDT 24 |
| Finished | May 30 04:30:30 PM PDT 24 |
| Peak memory | 610628 kb |
| Host | smart-c246e614-0db5-4a42-859d-5156b42aa75e |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396916606 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.2396916606 |
| Directory | /workspace/0.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.195070017 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 12872238465 ps |
| CPU time | 755.39 seconds |
| Started | May 30 04:13:41 PM PDT 24 |
| Finished | May 30 04:26:17 PM PDT 24 |
| Peak memory | 616316 kb |
| Host | smart-6aa254b5-ac4d-4f79-93d2-6a0a7bad1164 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=195070017 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.195070017 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.4288510829 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 4108449950 ps |
| CPU time | 733.84 seconds |
| Started | May 30 04:12:02 PM PDT 24 |
| Finished | May 30 04:24:17 PM PDT 24 |
| Peak memory | 607788 kb |
| Host | smart-00110188-6bef-4ac6-a49c-9f2d4bff7d51 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288510829 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.4288510829 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2998740358 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 3988461012 ps |
| CPU time | 571.02 seconds |
| Started | May 30 04:13:40 PM PDT 24 |
| Finished | May 30 04:23:12 PM PDT 24 |
| Peak memory | 607860 kb |
| Host | smart-04bce1b3-924d-4593-b712-d8c9fecb65c4 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998740358 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2998740358 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1022787116 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 4620558664 ps |
| CPU time | 705.48 seconds |
| Started | May 30 04:11:45 PM PDT 24 |
| Finished | May 30 04:23:31 PM PDT 24 |
| Peak memory | 607784 kb |
| Host | smart-9450480d-abf0-448c-a8ed-1a0bd17614c1 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022787116 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.1022787116 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.75411119 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 4266481412 ps |
| CPU time | 577.66 seconds |
| Started | May 30 04:20:44 PM PDT 24 |
| Finished | May 30 04:30:23 PM PDT 24 |
| Peak memory | 607816 kb |
| Host | smart-b0ad6f7c-b112-4910-85aa-724ffd4ae47d |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75411119 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clk mgr_external_clk_src_for_sw_slow_rma.75411119 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1526269382 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 4820110402 ps |
| CPU time | 754.82 seconds |
| Started | May 30 04:20:39 PM PDT 24 |
| Finished | May 30 04:33:14 PM PDT 24 |
| Peak memory | 607872 kb |
| Host | smart-de2bae96-675b-49e6-abe2-f0d030b39122 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526269382 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1526269382 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter.1416691839 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 2758833538 ps |
| CPU time | 211.46 seconds |
| Started | May 30 04:11:32 PM PDT 24 |
| Finished | May 30 04:15:05 PM PDT 24 |
| Peak memory | 603540 kb |
| Host | smart-10c4f454-f39b-4516-b38e-e4c53409a532 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416691839 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_clkmgr_jitter.1416691839 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.2109384358 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 3209415038 ps |
| CPU time | 392.08 seconds |
| Started | May 30 04:11:59 PM PDT 24 |
| Finished | May 30 04:18:32 PM PDT 24 |
| Peak memory | 603504 kb |
| Host | smart-70bf239e-ddbf-4b50-acc7-e367c55b84fd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109384358 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_frequency.2109384358 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.423535889 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 3258725978 ps |
| CPU time | 231.24 seconds |
| Started | May 30 04:11:07 PM PDT 24 |
| Finished | May 30 04:15:00 PM PDT 24 |
| Peak memory | 603476 kb |
| Host | smart-e209d9c4-b3db-4a16-b668-b3b31dd2ee07 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423535889 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.423535889 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.3814918999 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 4756451880 ps |
| CPU time | 411.55 seconds |
| Started | May 30 04:20:04 PM PDT 24 |
| Finished | May 30 04:26:57 PM PDT 24 |
| Peak memory | 603680 kb |
| Host | smart-65d8db28-5250-47f0-b145-f84a1f805be6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814918999 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.3814918999 |
| Directory | /workspace/0.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.820710042 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 5013853850 ps |
| CPU time | 456.38 seconds |
| Started | May 30 04:11:41 PM PDT 24 |
| Finished | May 30 04:19:18 PM PDT 24 |
| Peak memory | 603972 kb |
| Host | smart-2a7b97c1-2b86-449c-b227-f1fee09c1e66 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820710042 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.820710042 |
| Directory | /workspace/0.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.1026864257 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 5036912442 ps |
| CPU time | 544.6 seconds |
| Started | May 30 04:20:12 PM PDT 24 |
| Finished | May 30 04:29:18 PM PDT 24 |
| Peak memory | 603968 kb |
| Host | smart-ba0aebae-212b-45db-82ee-dc229106b5ac |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026864257 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.1026864257 |
| Directory | /workspace/0.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.1126409687 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 5428592936 ps |
| CPU time | 606.64 seconds |
| Started | May 30 04:11:52 PM PDT 24 |
| Finished | May 30 04:21:59 PM PDT 24 |
| Peak memory | 603944 kb |
| Host | smart-d63780d6-7f12-474b-84b9-726b2f15cedc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126409687 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_otbn_trans.1126409687 |
| Directory | /workspace/0.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.3666994537 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 10282635262 ps |
| CPU time | 1047.43 seconds |
| Started | May 30 04:11:09 PM PDT 24 |
| Finished | May 30 04:28:37 PM PDT 24 |
| Peak memory | 605328 kb |
| Host | smart-b11552fa-27bc-45ed-8e29-14c28e50b4c4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666994537 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.3666994537 |
| Directory | /workspace/0.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.3753135248 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 3428219814 ps |
| CPU time | 428.09 seconds |
| Started | May 30 04:10:38 PM PDT 24 |
| Finished | May 30 04:17:47 PM PDT 24 |
| Peak memory | 603172 kb |
| Host | smart-6d003800-29fc-4b7f-b188-4703a12f062f |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753135248 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.3753135248 |
| Directory | /workspace/0.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1292449898 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 4683869740 ps |
| CPU time | 554.54 seconds |
| Started | May 30 04:11:19 PM PDT 24 |
| Finished | May 30 04:20:35 PM PDT 24 |
| Peak memory | 603940 kb |
| Host | smart-0f25ceaf-8147-48e1-b185-7f9fe0bca46b |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292449898 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.1292449898 |
| Directory | /workspace/0.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.424191868 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 2584631298 ps |
| CPU time | 243.32 seconds |
| Started | May 30 04:14:25 PM PDT 24 |
| Finished | May 30 04:18:30 PM PDT 24 |
| Peak memory | 603140 kb |
| Host | smart-c0b507e5-5105-4d03-9ba5-abef6f0b9d5e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424191868 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_clkmgr_smoketest.424191868 |
| Directory | /workspace/0.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2167823714 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 38380297208 ps |
| CPU time | 8176.02 seconds |
| Started | May 30 04:12:05 PM PDT 24 |
| Finished | May 30 06:28:22 PM PDT 24 |
| Peak memory | 604116 kb |
| Host | smart-c16660a7-66ea-4efe-9b63-6e4833d08071 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167823714 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency.2167823714 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_kat_test.102772243 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 3100890478 ps |
| CPU time | 270.53 seconds |
| Started | May 30 04:10:20 PM PDT 24 |
| Finished | May 30 04:14:51 PM PDT 24 |
| Peak memory | 603824 kb |
| Host | smart-c8e10c98-62e1-4c1e-8205-5ee81eb84bb6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102772243 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.102772243 |
| Directory | /workspace/0.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.143802616 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 7545601130 ps |
| CPU time | 641.58 seconds |
| Started | May 30 04:14:43 PM PDT 24 |
| Finished | May 30 04:25:25 PM PDT 24 |
| Peak memory | 604920 kb |
| Host | smart-594f9b63-ec37-4454-b312-dfbc2dec7b45 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143802616 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_l c_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrn g_lc_hw_debug_en_test.143802616 |
| Directory | /workspace/0.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_smoketest.2389775329 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 2420077860 ps |
| CPU time | 234.16 seconds |
| Started | May 30 04:13:23 PM PDT 24 |
| Finished | May 30 04:17:18 PM PDT 24 |
| Peak memory | 603408 kb |
| Host | smart-f184877b-e9d9-4797-ab70-65d86bf94efa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389775329 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_csrng_smoketest.2389775329 |
| Directory | /workspace/0.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_data_integrity_escalation.850200715 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 4924461448 ps |
| CPU time | 754.55 seconds |
| Started | May 30 04:09:37 PM PDT 24 |
| Finished | May 30 04:22:13 PM PDT 24 |
| Peak memory | 604512 kb |
| Host | smart-51da542a-a64c-403f-a4f7-79f9f41df19c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=850200715 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.850200715 |
| Directory | /workspace/0.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_auto_mode.3222090495 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 4125501776 ps |
| CPU time | 1134.02 seconds |
| Started | May 30 04:11:44 PM PDT 24 |
| Finished | May 30 04:30:38 PM PDT 24 |
| Peak memory | 603480 kb |
| Host | smart-08ef260c-4134-4aad-92c1-9833cbf95b92 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222090495 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ auto_mode.3222090495 |
| Directory | /workspace/0.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.1936460846 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 5277504000 ps |
| CPU time | 970.68 seconds |
| Started | May 30 04:11:56 PM PDT 24 |
| Finished | May 30 04:28:07 PM PDT 24 |
| Peak memory | 604316 kb |
| Host | smart-a4702859-afae-4993-a852-81b8e657297f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1936460846 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.1936460846 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2237080196 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 6884422518 ps |
| CPU time | 977.84 seconds |
| Started | May 30 04:15:54 PM PDT 24 |
| Finished | May 30 04:32:13 PM PDT 24 |
| Peak memory | 604552 kb |
| Host | smart-54f2f9bc-90e7-4953-a8aa-5a7e398d776d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237080196 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.2237080196 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_kat.3598605290 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 3628735400 ps |
| CPU time | 657.91 seconds |
| Started | May 30 04:11:56 PM PDT 24 |
| Finished | May 30 04:22:55 PM PDT 24 |
| Peak memory | 610116 kb |
| Host | smart-89090f5f-f32e-42ba-9795-663cf8583a8c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_imag es=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598605290 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_edn_kat.3598605290 |
| Directory | /workspace/0.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_sw_mode.2105369996 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 10542291096 ps |
| CPU time | 2335.2 seconds |
| Started | May 30 04:18:47 PM PDT 24 |
| Finished | May 30 04:57:45 PM PDT 24 |
| Peak memory | 604088 kb |
| Host | smart-02a284d6-9a64-45d1-94be-4133ac6dc66a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105369996 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_sw_mode.2105369996 |
| Directory | /workspace/0.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.2116272382 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 2102786136 ps |
| CPU time | 237.73 seconds |
| Started | May 30 04:10:24 PM PDT 24 |
| Finished | May 30 04:14:23 PM PDT 24 |
| Peak memory | 603544 kb |
| Host | smart-c00d2673-1b95-4c2b-8cbe-928ea67bdd2e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21 16272382 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.2116272382 |
| Directory | /workspace/0.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.2566210844 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 2512584200 ps |
| CPU time | 217.88 seconds |
| Started | May 30 04:18:53 PM PDT 24 |
| Finished | May 30 04:22:32 PM PDT 24 |
| Peak memory | 603536 kb |
| Host | smart-519a6bd1-3abc-4998-8a0d-cd9037f6949a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566210844 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.2566210844 |
| Directory | /workspace/0.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.242889488 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 3733451032 ps |
| CPU time | 432.55 seconds |
| Started | May 30 04:14:04 PM PDT 24 |
| Finished | May 30 04:21:17 PM PDT 24 |
| Peak memory | 603112 kb |
| Host | smart-7fd80339-2810-40d3-86c7-a7c4a44571b7 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=242889488 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.242889488 |
| Directory | /workspace/0.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_concurrency.2772398852 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 2399803846 ps |
| CPU time | 243.83 seconds |
| Started | May 30 04:09:49 PM PDT 24 |
| Finished | May 30 04:13:54 PM PDT 24 |
| Peak memory | 603520 kb |
| Host | smart-6359317c-0702-4925-a9b0-195167fb6a41 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772398852 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_example_concurrency.2772398852 |
| Directory | /workspace/0.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_flash.1570019608 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 2683530680 ps |
| CPU time | 177.63 seconds |
| Started | May 30 04:09:37 PM PDT 24 |
| Finished | May 30 04:12:36 PM PDT 24 |
| Peak memory | 603772 kb |
| Host | smart-0d3e19f8-40db-446c-b749-a6c752500212 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570019608 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_flash.1570019608 |
| Directory | /workspace/0.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_manufacturer.624847938 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 2234658280 ps |
| CPU time | 285.73 seconds |
| Started | May 30 04:09:55 PM PDT 24 |
| Finished | May 30 04:14:41 PM PDT 24 |
| Peak memory | 604504 kb |
| Host | smart-b1a0d811-1d2f-41d3-b7ad-cb65cd82dc6e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624847938 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 0.chip_sw_example_manufacturer.624847938 |
| Directory | /workspace/0.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_rom.756824874 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 2098945824 ps |
| CPU time | 129.17 seconds |
| Started | May 30 04:09:05 PM PDT 24 |
| Finished | May 30 04:11:16 PM PDT 24 |
| Peak memory | 602940 kb |
| Host | smart-9bb6db23-0473-4b35-97c6-162667319503 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756824874 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_example_rom.756824874 |
| Directory | /workspace/0.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.1499673692 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 58830219256 ps |
| CPU time | 11545.5 seconds |
| Started | May 30 04:07:58 PM PDT 24 |
| Finished | May 30 07:20:26 PM PDT 24 |
| Peak memory | 618400 kb |
| Host | smart-64e0cf00-0305-4db7-9a6c-5cc8669a6f5b |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1499673692 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_exit_test_unlocked_bootstrap.1499673692 |
| Directory | /workspace/0.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_crash_alert.3114684071 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 6622184476 ps |
| CPU time | 685.22 seconds |
| Started | May 30 04:12:21 PM PDT 24 |
| Finished | May 30 04:23:48 PM PDT 24 |
| Peak memory | 605596 kb |
| Host | smart-b04f9b14-23b5-458e-a655-5e505f244af2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=3114684071 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.3114684071 |
| Directory | /workspace/0.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access.1965430101 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 5583807380 ps |
| CPU time | 1168.02 seconds |
| Started | May 30 04:10:09 PM PDT 24 |
| Finished | May 30 04:29:38 PM PDT 24 |
| Peak memory | 603528 kb |
| Host | smart-3db787f7-e87e-4d9c-85ac-961e7c8f9776 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965430101 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_flash_ctrl_access.1965430101 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.129422011 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 5795019662 ps |
| CPU time | 1009.55 seconds |
| Started | May 30 04:09:53 PM PDT 24 |
| Finished | May 30 04:26:44 PM PDT 24 |
| Peak memory | 603904 kb |
| Host | smart-62a69d69-7a6b-4694-bae7-84af4aa51e9f |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129422011 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en.129422011 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3160979262 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 7561319917 ps |
| CPU time | 1181.3 seconds |
| Started | May 30 04:12:31 PM PDT 24 |
| Finished | May 30 04:32:14 PM PDT 24 |
| Peak memory | 603900 kb |
| Host | smart-5d1fc970-d453-4191-b971-f6a2383e5a68 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160979262 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3160979262 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.1719755303 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 6414770735 ps |
| CPU time | 1077.75 seconds |
| Started | May 30 04:09:54 PM PDT 24 |
| Finished | May 30 04:27:54 PM PDT 24 |
| Peak memory | 603848 kb |
| Host | smart-7b60aa7c-5370-428b-9dc6-78153f1b9449 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719755303 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_flash_ctrl_clock_freqs.1719755303 |
| Directory | /workspace/0.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.1734961486 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4163199622 ps |
| CPU time | 489.05 seconds |
| Started | May 30 04:09:55 PM PDT 24 |
| Finished | May 30 04:18:05 PM PDT 24 |
| Peak memory | 603520 kb |
| Host | smart-3a13387c-1a93-4660-8cdc-9205e0824e64 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734961486 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_idle_low_power.1734961486 |
| Directory | /workspace/0.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.630095949 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 5317726778 ps |
| CPU time | 1112.96 seconds |
| Started | May 30 04:12:55 PM PDT 24 |
| Finished | May 30 04:31:28 PM PDT 24 |
| Peak memory | 603852 kb |
| Host | smart-eebb74ed-22aa-41ca-bf43-8bf0d9acfcc8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630095949 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_mem_protection.630095949 |
| Directory | /workspace/0.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.1025726024 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 4842721841 ps |
| CPU time | 695.68 seconds |
| Started | May 30 04:11:25 PM PDT 24 |
| Finished | May 30 04:23:01 PM PDT 24 |
| Peak memory | 603728 kb |
| Host | smart-28754ca5-05ab-47c6-8641-5acfb8d00bd6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1025726024 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.1025726024 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1998792840 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 5231794121 ps |
| CPU time | 735.81 seconds |
| Started | May 30 04:13:15 PM PDT 24 |
| Finished | May 30 04:25:32 PM PDT 24 |
| Peak memory | 603976 kb |
| Host | smart-20030c21-a5a9-4e65-bcfe-ee36b07afbc9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1998792840 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1998792840 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.751084595 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 3295490680 ps |
| CPU time | 408.57 seconds |
| Started | May 30 04:13:14 PM PDT 24 |
| Finished | May 30 04:20:04 PM PDT 24 |
| Peak memory | 603504 kb |
| Host | smart-13040544-a631-491f-8ef0-0879ec17e8fe |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7510845 95 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_write_clear.751084595 |
| Directory | /workspace/0.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init.2788743877 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 16760977952 ps |
| CPU time | 1952.22 seconds |
| Started | May 30 04:09:37 PM PDT 24 |
| Finished | May 30 04:42:11 PM PDT 24 |
| Peak memory | 608064 kb |
| Host | smart-65011000-cdcf-4103-a4bd-d4a6ab78d74c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788743877 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init.2788743877 |
| Directory | /workspace/0.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.2175573106 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 2800313646 ps |
| CPU time | 291.41 seconds |
| Started | May 30 04:17:54 PM PDT 24 |
| Finished | May 30 04:22:47 PM PDT 24 |
| Peak memory | 603540 kb |
| Host | smart-e8f06679-30d5-494b-a291-ba58afda53a8 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2175573106 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.2175573106 |
| Directory | /workspace/0.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio_smoketest.1641125799 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 3068809471 ps |
| CPU time | 314.32 seconds |
| Started | May 30 04:14:26 PM PDT 24 |
| Finished | May 30 04:19:41 PM PDT 24 |
| Peak memory | 604820 kb |
| Host | smart-982b1800-a527-4383-9551-fda1dc3c89da |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641125799 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_gpio_smoketest.1641125799 |
| Directory | /workspace/0.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc.438324947 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 3580167688 ps |
| CPU time | 365.81 seconds |
| Started | May 30 04:18:55 PM PDT 24 |
| Finished | May 30 04:25:02 PM PDT 24 |
| Peak memory | 603432 kb |
| Host | smart-e7bdc12f-6cff-4f20-b7c4-e3df76aa21ea |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438324947 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc.438324947 |
| Directory | /workspace/0.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.1703781824 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 3076219223 ps |
| CPU time | 247.44 seconds |
| Started | May 30 04:18:54 PM PDT 24 |
| Finished | May 30 04:23:02 PM PDT 24 |
| Peak memory | 603588 kb |
| Host | smart-3494610b-85ab-4f76-b388-e3aa97aa30d5 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703781824 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en.1703781824 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1009551870 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 3301688773 ps |
| CPU time | 307.87 seconds |
| Started | May 30 04:12:36 PM PDT 24 |
| Finished | May 30 04:17:45 PM PDT 24 |
| Peak memory | 603708 kb |
| Host | smart-c0b8a68a-8d71-412f-a265-27604dff299c |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009551870 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.1009551870 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_smoketest.3042521317 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 2635346720 ps |
| CPU time | 310.15 seconds |
| Started | May 30 04:14:27 PM PDT 24 |
| Finished | May 30 04:19:39 PM PDT 24 |
| Peak memory | 603476 kb |
| Host | smart-13ea0f16-2b07-4d64-9501-2199c4b86c2c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042521317 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_hmac_smoketest.3042521317 |
| Directory | /workspace/0.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.397260143 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 4895812360 ps |
| CPU time | 843.05 seconds |
| Started | May 30 04:10:08 PM PDT 24 |
| Finished | May 30 04:24:12 PM PDT 24 |
| Peak memory | 604048 kb |
| Host | smart-6f3a0aef-3b26-4345-956f-df6ab92dca96 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397260143 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx.397260143 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2103790861 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 6132352432 ps |
| CPU time | 1051.37 seconds |
| Started | May 30 04:09:41 PM PDT 24 |
| Finished | May 30 04:27:13 PM PDT 24 |
| Peak memory | 603796 kb |
| Host | smart-e1daacbb-aee4-4929-bc21-3c11c1343e68 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103790861 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.2103790861 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1283418351 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 5361018090 ps |
| CPU time | 875.33 seconds |
| Started | May 30 04:10:34 PM PDT 24 |
| Finished | May 30 04:25:11 PM PDT 24 |
| Peak memory | 604000 kb |
| Host | smart-9b1cb6cf-f3cb-4afc-aaac-7b79daa898f9 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283418351 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.1283418351 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_inject_scramble_seed.3956316870 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 65505072356 ps |
| CPU time | 11927.8 seconds |
| Started | May 30 04:10:46 PM PDT 24 |
| Finished | May 30 07:29:37 PM PDT 24 |
| Peak memory | 621536 kb |
| Host | smart-4c51e60a-f381-422f-8b42-d59e6683ade8 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3956316870 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.3956316870 |
| Directory | /workspace/0.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.3390207589 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 10776086544 ps |
| CPU time | 2152.74 seconds |
| Started | May 30 04:18:51 PM PDT 24 |
| Finished | May 30 04:54:46 PM PDT 24 |
| Peak memory | 611264 kb |
| Host | smart-b81f3eb3-a6ed-47cb-bb01-8091d8ca8388 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390 207589 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation.3390207589 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.1572384368 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 9267347307 ps |
| CPU time | 2077.78 seconds |
| Started | May 30 04:11:23 PM PDT 24 |
| Finished | May 30 04:46:02 PM PDT 24 |
| Peak memory | 611264 kb |
| Host | smart-beb9035a-ec4d-46c7-8496-c8f19f630b5e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1572384368 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en.1572384368 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.4013895997 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 8069129683 ps |
| CPU time | 1151.01 seconds |
| Started | May 30 04:11:44 PM PDT 24 |
| Finished | May 30 04:30:56 PM PDT 24 |
| Peak memory | 610956 kb |
| Host | smart-2bb88ece-9b98-47b4-98df-1799b27c29eb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4013895997 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.4013895997 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3495933251 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 8725023800 ps |
| CPU time | 2253.09 seconds |
| Started | May 30 04:13:09 PM PDT 24 |
| Finished | May 30 04:50:43 PM PDT 24 |
| Peak memory | 611236 kb |
| Host | smart-8504623e-67ac-4b2f-9998-206dfa65ee6a |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3495933251 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_prod.3495933251 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.589548053 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 13301244244 ps |
| CPU time | 2525.58 seconds |
| Started | May 30 04:15:51 PM PDT 24 |
| Finished | May 30 04:57:57 PM PDT 24 |
| Peak memory | 605472 kb |
| Host | smart-c0603f64-a8a8-4ede-b90e-d6a6991b3e28 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589548 053 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_aes.589548053 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.2081784329 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 8952793888 ps |
| CPU time | 1616.66 seconds |
| Started | May 30 04:18:46 PM PDT 24 |
| Finished | May 30 04:45:44 PM PDT 24 |
| Peak memory | 605576 kb |
| Host | smart-0db0b0f3-f8d4-49e8-96eb-dd83cf33c2d0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20817 84329 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.2081784329 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3397876711 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 10384564588 ps |
| CPU time | 3155.62 seconds |
| Started | May 30 04:13:39 PM PDT 24 |
| Finished | May 30 05:06:16 PM PDT 24 |
| Peak memory | 604360 kb |
| Host | smart-8818b35b-21fd-4576-9fcd-0c648932b560 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33978 76711 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.3397876711 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_app_rom.1660777648 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 2610714262 ps |
| CPU time | 195.44 seconds |
| Started | May 30 04:13:21 PM PDT 24 |
| Finished | May 30 04:16:38 PM PDT 24 |
| Peak memory | 603496 kb |
| Host | smart-0a148d7a-52b0-4c26-90e5-1ece3a244d29 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660777648 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_kmac_app_rom.1660777648 |
| Directory | /workspace/0.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_entropy.504715048 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 2503469798 ps |
| CPU time | 280.41 seconds |
| Started | May 30 04:10:12 PM PDT 24 |
| Finished | May 30 04:14:53 PM PDT 24 |
| Peak memory | 603468 kb |
| Host | smart-70ae7dda-81a6-4e9a-8ba9-5aadefce120a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504715048 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_kmac_entropy.504715048 |
| Directory | /workspace/0.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_idle.1590722307 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 3237699140 ps |
| CPU time | 311.62 seconds |
| Started | May 30 04:13:08 PM PDT 24 |
| Finished | May 30 04:18:21 PM PDT 24 |
| Peak memory | 603492 kb |
| Host | smart-bbc5e8b5-ce5b-42f6-92f9-d468324f72fc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590722307 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_idle.1590722307 |
| Directory | /workspace/0.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.4190840513 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 3456861728 ps |
| CPU time | 283.89 seconds |
| Started | May 30 04:11:44 PM PDT 24 |
| Finished | May 30 04:16:29 PM PDT 24 |
| Peak memory | 603364 kb |
| Host | smart-5ccb5274-ad56-4520-af67-daf3c0016253 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190840513 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_kmac_mode_cshake.4190840513 |
| Directory | /workspace/0.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.3117206895 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 2532949552 ps |
| CPU time | 301.44 seconds |
| Started | May 30 04:11:40 PM PDT 24 |
| Finished | May 30 04:16:42 PM PDT 24 |
| Peak memory | 603312 kb |
| Host | smart-e66967ef-0298-4132-9847-32aebe1503cc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117206895 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_kmac_mode_kmac.3117206895 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2086740242 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 2763412024 ps |
| CPU time | 288.5 seconds |
| Started | May 30 04:11:39 PM PDT 24 |
| Finished | May 30 04:16:28 PM PDT 24 |
| Peak memory | 603276 kb |
| Host | smart-c34cf391-1a45-49a5-aa97-fb6998f6054d |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086740242 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.2086740242 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1245151350 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 2690163773 ps |
| CPU time | 264.41 seconds |
| Started | May 30 04:10:56 PM PDT 24 |
| Finished | May 30 04:15:21 PM PDT 24 |
| Peak memory | 603500 kb |
| Host | smart-d8ffb5b8-f1fa-4779-a014-e276329410ad |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12451513 50 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1245151350 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_smoketest.2120460962 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 3234905920 ps |
| CPU time | 337.38 seconds |
| Started | May 30 04:14:54 PM PDT 24 |
| Finished | May 30 04:20:33 PM PDT 24 |
| Peak memory | 603512 kb |
| Host | smart-7dc86fb6-dd22-48ef-82c8-f59e491be03a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120460962 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_smoketest.2120460962 |
| Directory | /workspace/0.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.2833618432 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 3420995106 ps |
| CPU time | 241.93 seconds |
| Started | May 30 04:09:26 PM PDT 24 |
| Finished | May 30 04:13:29 PM PDT 24 |
| Peak memory | 603236 kb |
| Host | smart-d7b767c6-99ce-4aa8-872a-4b8baca34ccf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833618432 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_lc_ctrl_otp_hw_cfg0.2833618432 |
| Directory | /workspace/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.2249150071 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 3063796504 ps |
| CPU time | 120.22 seconds |
| Started | May 30 04:10:20 PM PDT 24 |
| Finished | May 30 04:12:21 PM PDT 24 |
| Peak memory | 615648 kb |
| Host | smart-461805c2-71c8-44e6-bf59-5abf5996e0b2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249150071 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.2249150071 |
| Directory | /workspace/0.chip_sw_lc_ctrl_raw_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1205274443 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 2608226049 ps |
| CPU time | 147.49 seconds |
| Started | May 30 04:12:04 PM PDT 24 |
| Finished | May 30 04:14:32 PM PDT 24 |
| Peak memory | 614852 kb |
| Host | smart-7bf116d6-ed1b-4a22-a563-234d8b8c11d1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205274443 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.1205274443 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rma_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.6699499 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 2543343615 ps |
| CPU time | 140.68 seconds |
| Started | May 30 04:10:07 PM PDT 24 |
| Finished | May 30 04:12:29 PM PDT 24 |
| Peak memory | 615680 kb |
| Host | smart-a32cf8a4-8f6a-4863-ae00-25dbba9ec06f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTestLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=6699499 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.6699499 |
| Directory | /workspace/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.379758170 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 6592419753 ps |
| CPU time | 545.11 seconds |
| Started | May 30 04:09:49 PM PDT 24 |
| Finished | May 30 04:18:55 PM PDT 24 |
| Peak memory | 615632 kb |
| Host | smart-27e1513d-417b-4b8a-bb50-ad7c54723b17 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379758170 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_transition.379758170 |
| Directory | /workspace/0.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.744880415 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 1736462856 ps |
| CPU time | 98.78 seconds |
| Started | May 30 04:11:42 PM PDT 24 |
| Finished | May 30 04:13:22 PM PDT 24 |
| Peak memory | 610516 kb |
| Host | smart-541b4b7f-da59-4db0-b658-74b7d0e7e6a5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=744880415 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.744880415 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4228633186 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 2461799162 ps |
| CPU time | 96.18 seconds |
| Started | May 30 04:09:34 PM PDT 24 |
| Finished | May 30 04:11:11 PM PDT 24 |
| Peak memory | 610552 kb |
| Host | smart-657da583-3cbe-482b-bfb2-a0cf0b3030ed |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228633186 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4228633186 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.20002605 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 47606282490 ps |
| CPU time | 5480.17 seconds |
| Started | May 30 04:09:46 PM PDT 24 |
| Finished | May 30 05:41:08 PM PDT 24 |
| Peak memory | 612380 kb |
| Host | smart-a957651b-593c-47ca-8457-3c1c98909b7d |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20002605 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_lc_walkthrough_dev.20002605 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2818363109 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 46977903400 ps |
| CPU time | 4817.31 seconds |
| Started | May 30 04:10:29 PM PDT 24 |
| Finished | May 30 05:30:48 PM PDT 24 |
| Peak memory | 612352 kb |
| Host | smart-ccb99566-6bae-4918-8c47-5a8f941e19b4 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818363109 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi p_sw_lc_walkthrough_prod.2818363109 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.2079639024 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 9622034463 ps |
| CPU time | 1003.82 seconds |
| Started | May 30 04:12:19 PM PDT 24 |
| Finished | May 30 04:29:04 PM PDT 24 |
| Peak memory | 613180 kb |
| Host | smart-2043d469-e386-48ad-a79a-91967de86b8d |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079639024 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.2079639024 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.3826477122 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 25734658975 ps |
| CPU time | 2056.03 seconds |
| Started | May 30 04:09:48 PM PDT 24 |
| Finished | May 30 04:44:05 PM PDT 24 |
| Peak memory | 610088 kb |
| Host | smart-70e66395-8af9-492a-b4e0-2366732646a8 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3826477122 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_testun locks.3826477122 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.3200521557 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 16640220664 ps |
| CPU time | 3083.14 seconds |
| Started | May 30 04:11:19 PM PDT 24 |
| Finished | May 30 05:02:43 PM PDT 24 |
| Peak memory | 604156 kb |
| Host | smart-bc6c02ee-08da-4d93-8a13-692b9f6d7317 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=3200521557 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.3200521557 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3588327235 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 18702967591 ps |
| CPU time | 3448.04 seconds |
| Started | May 30 04:11:43 PM PDT 24 |
| Finished | May 30 05:09:13 PM PDT 24 |
| Peak memory | 604332 kb |
| Host | smart-490181e5-e684-487d-91c9-f4b860fa1571 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3588327235 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3588327235 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.4216986363 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 24653234791 ps |
| CPU time | 4065.36 seconds |
| Started | May 30 04:12:28 PM PDT 24 |
| Finished | May 30 05:20:15 PM PDT 24 |
| Peak memory | 603800 kb |
| Host | smart-e388d991-7ae5-41da-8067-37548125a338 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216986363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.4216986363 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.3564652775 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 3462139146 ps |
| CPU time | 392 seconds |
| Started | May 30 04:11:50 PM PDT 24 |
| Finished | May 30 04:18:23 PM PDT 24 |
| Peak memory | 603560 kb |
| Host | smart-39b7bdd8-0fe8-46b8-ba2e-271501a73757 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564652775 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.3564652775 |
| Directory | /workspace/0.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_randomness.1769419836 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 5815173700 ps |
| CPU time | 873.27 seconds |
| Started | May 30 04:11:21 PM PDT 24 |
| Finished | May 30 04:25:55 PM PDT 24 |
| Peak memory | 604212 kb |
| Host | smart-0fe18f35-9759-47d9-bfb4-53884d021fc9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1769419836 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.1769419836 |
| Directory | /workspace/0.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_smoketest.2797112988 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 11405663466 ps |
| CPU time | 2366.43 seconds |
| Started | May 30 04:14:13 PM PDT 24 |
| Finished | May 30 04:53:41 PM PDT 24 |
| Peak memory | 603952 kb |
| Host | smart-27ab8d4c-bf77-4599-8be9-6bde909688cc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797112988 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_otbn_smoketest.2797112988 |
| Directory | /workspace/0.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.1125943767 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 3119454790 ps |
| CPU time | 360.77 seconds |
| Started | May 30 04:09:13 PM PDT 24 |
| Finished | May 30 04:15:15 PM PDT 24 |
| Peak memory | 603968 kb |
| Host | smart-46562467-6faf-4db9-9e72-337d22bd19ec |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125943767 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_ecc_error_vendor_test.1125943767 |
| Directory | /workspace/0.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.143071561 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 5666859782 ps |
| CPU time | 657.01 seconds |
| Started | May 30 04:09:55 PM PDT 24 |
| Finished | May 30 04:20:53 PM PDT 24 |
| Peak memory | 605660 kb |
| Host | smart-296413b4-0901-4388-9d43-515843f0ed80 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 143071561 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.143071561 |
| Directory | /workspace/0.chip_sw_otp_ctrl_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.2219632598 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 7289709970 ps |
| CPU time | 1347.98 seconds |
| Started | May 30 04:11:30 PM PDT 24 |
| Finished | May 30 04:33:59 PM PDT 24 |
| Peak memory | 604092 kb |
| Host | smart-f89d88ee-03ee-42b9-8aeb-f19fa69c002c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2219632598 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.2219632598 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.2917240071 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 8624616358 ps |
| CPU time | 1501.01 seconds |
| Started | May 30 04:12:15 PM PDT 24 |
| Finished | May 30 04:37:18 PM PDT 24 |
| Peak memory | 605092 kb |
| Host | smart-d1e182d6-ba20-41db-984b-d8d1949525e4 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2917240071 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.2917240071 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.3871280338 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 6680904712 ps |
| CPU time | 1203.46 seconds |
| Started | May 30 04:09:36 PM PDT 24 |
| Finished | May 30 04:29:40 PM PDT 24 |
| Peak memory | 605104 kb |
| Host | smart-ffe1b4a2-8972-415b-8637-4564842ef23d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3871280338 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.3871280338 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3977090349 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 4615790412 ps |
| CPU time | 704.6 seconds |
| Started | May 30 04:11:55 PM PDT 24 |
| Finished | May 30 04:23:41 PM PDT 24 |
| Peak memory | 603964 kb |
| Host | smart-fab007d0-f25c-4e60-bb28-cd48da238381 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3977090349 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3977090349 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.2613248799 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 2642268836 ps |
| CPU time | 284.36 seconds |
| Started | May 30 04:13:47 PM PDT 24 |
| Finished | May 30 04:18:32 PM PDT 24 |
| Peak memory | 603740 kb |
| Host | smart-65b459ea-a5ff-4199-af35-1cc5ee72c0ec |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613248799 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_otp_ctrl_smoketest.2613248799 |
| Directory | /workspace/0.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_plic_sw_irq.2781942609 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 2635163172 ps |
| CPU time | 288.89 seconds |
| Started | May 30 04:10:52 PM PDT 24 |
| Finished | May 30 04:15:42 PM PDT 24 |
| Peak memory | 603140 kb |
| Host | smart-e9cdfac7-cf6a-4094-9635-1a5b04a57cf9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781942609 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_plic_sw_irq.2781942609 |
| Directory | /workspace/0.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_idle_load.1740149031 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 4237218132 ps |
| CPU time | 417.47 seconds |
| Started | May 30 04:12:48 PM PDT 24 |
| Finished | May 30 04:19:47 PM PDT 24 |
| Peak memory | 604048 kb |
| Host | smart-4a10b749-81e9-4910-bedc-8a0c2024fbac |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740149031 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_idle_load.1740149031 |
| Directory | /workspace/0.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_sleep_load.666689183 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 9892632352 ps |
| CPU time | 576.26 seconds |
| Started | May 30 04:13:32 PM PDT 24 |
| Finished | May 30 04:23:10 PM PDT 24 |
| Peak memory | 605168 kb |
| Host | smart-ab04c378-88c3-42da-9d75-8920de292b6d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666689183 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_power_sleep_load.666689183 |
| Directory | /workspace/0.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.1519060788 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 10233033999 ps |
| CPU time | 1745.71 seconds |
| Started | May 30 04:11:34 PM PDT 24 |
| Finished | May 30 04:40:41 PM PDT 24 |
| Peak memory | 604876 kb |
| Host | smart-cdb6845a-1d02-4144-9a37-fa958ad1b558 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519 060788 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.1519060788 |
| Directory | /workspace/0.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.3707801090 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 22064374038 ps |
| CPU time | 1989.61 seconds |
| Started | May 30 04:11:21 PM PDT 24 |
| Finished | May 30 04:44:31 PM PDT 24 |
| Peak memory | 605272 kb |
| Host | smart-41b67bc3-0a05-4b4c-8c6b-c7913b3fce3d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370 7801090 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.3707801090 |
| Directory | /workspace/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1131909971 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 16384357847 ps |
| CPU time | 1651.86 seconds |
| Started | May 30 04:10:14 PM PDT 24 |
| Finished | May 30 04:37:47 PM PDT 24 |
| Peak memory | 605624 kb |
| Host | smart-6c92438b-2b74-44bb-b4e8-fc1078b9a48b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1131909971 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1131909971 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.892173346 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 19533093930 ps |
| CPU time | 1382.8 seconds |
| Started | May 30 04:13:07 PM PDT 24 |
| Finished | May 30 04:36:11 PM PDT 24 |
| Peak memory | 605504 kb |
| Host | smart-e1b7579e-a0cb-46ff-b0f8-e78d3eed9235 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 892173346 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.892173346 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.519727604 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 7566294600 ps |
| CPU time | 781.44 seconds |
| Started | May 30 04:11:12 PM PDT 24 |
| Finished | May 30 04:24:15 PM PDT 24 |
| Peak memory | 604268 kb |
| Host | smart-7f8812ff-89aa-410e-84ba-f2eb72e0ade0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519727604 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.519727604 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.676250702 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 4299392846 ps |
| CPU time | 315.34 seconds |
| Started | May 30 04:10:03 PM PDT 24 |
| Finished | May 30 04:15:19 PM PDT 24 |
| Peak memory | 610868 kb |
| Host | smart-47081dc5-f36c-4604-8f15-f57123233b05 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=676250702 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.676250702 |
| Directory | /workspace/0.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1551982045 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 10642286082 ps |
| CPU time | 1621.87 seconds |
| Started | May 30 04:11:21 PM PDT 24 |
| Finished | May 30 04:38:24 PM PDT 24 |
| Peak memory | 606024 kb |
| Host | smart-2b7a9433-dec6-49c8-bade-ecaaacb93b28 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551982045 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1551982045 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3018315867 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 6954970800 ps |
| CPU time | 384.52 seconds |
| Started | May 30 04:14:33 PM PDT 24 |
| Finished | May 30 04:20:59 PM PDT 24 |
| Peak memory | 604432 kb |
| Host | smart-4aae25b5-07df-4a0b-9902-15a792a78df8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018315867 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3018315867 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.3594220904 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 5307785100 ps |
| CPU time | 738 seconds |
| Started | May 30 04:18:55 PM PDT 24 |
| Finished | May 30 04:31:14 PM PDT 24 |
| Peak memory | 604252 kb |
| Host | smart-ea9c93c6-b35b-401d-a01a-8db56f315d87 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594220904 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_por_reset.3594220904 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3495760376 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 21789347796 ps |
| CPU time | 1721.31 seconds |
| Started | May 30 04:12:00 PM PDT 24 |
| Finished | May 30 04:40:42 PM PDT 24 |
| Peak memory | 605424 kb |
| Host | smart-dc294457-cf95-4d40-9e35-9ba0742764b1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3495760376 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3495760376 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2324052354 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 31689118164 ps |
| CPU time | 3176.29 seconds |
| Started | May 30 04:11:15 PM PDT 24 |
| Finished | May 30 05:04:13 PM PDT 24 |
| Peak memory | 605808 kb |
| Host | smart-5fb3c4f1-792f-4a34-847b-da99ab8959d4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324052354 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_s leep_power_glitch_reset.2324052354 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3249375268 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 3098771000 ps |
| CPU time | 305.5 seconds |
| Started | May 30 04:11:21 PM PDT 24 |
| Finished | May 30 04:16:27 PM PDT 24 |
| Peak memory | 603228 kb |
| Host | smart-be770d34-d3ab-4c77-a37c-9a13b56088ad |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249375268 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_disabled.3249375268 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.1151013261 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 6551286892 ps |
| CPU time | 541.93 seconds |
| Started | May 30 04:10:47 PM PDT 24 |
| Finished | May 30 04:19:50 PM PDT 24 |
| Peak memory | 611044 kb |
| Host | smart-17735911-49b7-4e3f-8c20-9505b528dc2c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1151013261 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_power_glitch_reset.1151013261 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2430548393 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 4938326612 ps |
| CPU time | 422.95 seconds |
| Started | May 30 04:11:35 PM PDT 24 |
| Finished | May 30 04:18:39 PM PDT 24 |
| Peak memory | 604144 kb |
| Host | smart-ad308b1f-c8fe-4307-92b8-810b63ddb444 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24305483 93 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2430548393 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.2172497556 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 5994026776 ps |
| CPU time | 527.93 seconds |
| Started | May 30 04:11:19 PM PDT 24 |
| Finished | May 30 04:20:08 PM PDT 24 |
| Peak memory | 605372 kb |
| Host | smart-e4604a6a-b41d-4503-8df5-dc8e0beaa5ff |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2172497556 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.2172497556 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.2804368366 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 4231731480 ps |
| CPU time | 323.58 seconds |
| Started | May 30 04:15:01 PM PDT 24 |
| Finished | May 30 04:20:26 PM PDT 24 |
| Peak memory | 603748 kb |
| Host | smart-329f4d92-86f7-4fb5-af8a-2ddeca7dad78 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804368366 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.2804368366 |
| Directory | /workspace/0.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.2715495636 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 5344109917 ps |
| CPU time | 1009.13 seconds |
| Started | May 30 04:12:27 PM PDT 24 |
| Finished | May 30 04:29:18 PM PDT 24 |
| Peak memory | 604344 kb |
| Host | smart-6319e9ef-22b7-477c-9448-c8e72aea10ce |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715495636 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.2715495636 |
| Directory | /workspace/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.2014586608 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 4295532028 ps |
| CPU time | 491.24 seconds |
| Started | May 30 04:10:01 PM PDT 24 |
| Finished | May 30 04:18:14 PM PDT 24 |
| Peak memory | 603760 kb |
| Host | smart-aa5e3551-2184-4c63-85cd-9d18e204244f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014586608 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.2014586608 |
| Directory | /workspace/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.1855295851 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 5135509000 ps |
| CPU time | 411.55 seconds |
| Started | May 30 04:14:32 PM PDT 24 |
| Finished | May 30 04:21:25 PM PDT 24 |
| Peak memory | 604008 kb |
| Host | smart-afe83c6d-c03a-4c8d-8d55-9c659bf224d7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855295851 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usbdev_smoketest.1855295851 |
| Directory | /workspace/0.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.1896715348 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 4064573956 ps |
| CPU time | 435.41 seconds |
| Started | May 30 04:11:17 PM PDT 24 |
| Finished | May 30 04:18:34 PM PDT 24 |
| Peak memory | 603748 kb |
| Host | smart-c5e84ce2-4231-4e2c-9c3f-922a270d6361 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189 6715348 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.1896715348 |
| Directory | /workspace/0.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.4123915547 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 8712388375 ps |
| CPU time | 485.9 seconds |
| Started | May 30 04:10:48 PM PDT 24 |
| Finished | May 30 04:18:55 PM PDT 24 |
| Peak memory | 604052 kb |
| Host | smart-d8155720-48b1-4a97-a40a-939127f1227c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123915547 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.4123915547 |
| Directory | /workspace/0.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.2553354970 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 6317910808 ps |
| CPU time | 588.8 seconds |
| Started | May 30 04:10:19 PM PDT 24 |
| Finished | May 30 04:20:09 PM PDT 24 |
| Peak memory | 604080 kb |
| Host | smart-6b905239-bf2a-464c-88c2-a615939264f3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553354970 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_rstmgr_cpu_info.2553354970 |
| Directory | /workspace/0.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.1067349886 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 5182074120 ps |
| CPU time | 612.68 seconds |
| Started | May 30 04:09:37 PM PDT 24 |
| Finished | May 30 04:19:52 PM PDT 24 |
| Peak memory | 636112 kb |
| Host | smart-9e8fa950-fe3c-4fc8-8be7-d2a07f02d116 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1067349886 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.1067349886 |
| Directory | /workspace/0.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.4040957269 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 3428831630 ps |
| CPU time | 252.52 seconds |
| Started | May 30 04:15:29 PM PDT 24 |
| Finished | May 30 04:19:43 PM PDT 24 |
| Peak memory | 603452 kb |
| Host | smart-212e96d1-0ea9-41d9-a8e0-bc8d0f0913ba |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040957269 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_rstmgr_smoketest.4040957269 |
| Directory | /workspace/0.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.2358096489 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 4618497380 ps |
| CPU time | 455.63 seconds |
| Started | May 30 04:10:39 PM PDT 24 |
| Finished | May 30 04:18:17 PM PDT 24 |
| Peak memory | 604060 kb |
| Host | smart-ebc8eb54-83a5-41e0-acee-56e5aecddc82 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358096489 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rstmgr_sw_req.2358096489 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.945977036 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 2334956268 ps |
| CPU time | 274.7 seconds |
| Started | May 30 04:11:05 PM PDT 24 |
| Finished | May 30 04:15:41 PM PDT 24 |
| Peak memory | 603752 kb |
| Host | smart-1bd32d82-31f7-46f6-9ebc-8d4411092c70 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945977036 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_sw_rst.945977036 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.3618661067 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 3205863822 ps |
| CPU time | 195.35 seconds |
| Started | May 30 04:11:06 PM PDT 24 |
| Finished | May 30 04:14:22 PM PDT 24 |
| Peak memory | 604980 kb |
| Host | smart-ff6758d9-2fe5-44e4-81b3-d2dfa08cee4f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618661067 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.3618661067 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2941455011 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 2184899736 ps |
| CPU time | 246.44 seconds |
| Started | May 30 04:10:43 PM PDT 24 |
| Finished | May 30 04:14:51 PM PDT 24 |
| Peak memory | 640088 kb |
| Host | smart-635c6c82-b17b-45e6-ba7b-e8682d8d9346 |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941455011 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_lockstep_glitch.2941455011 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.2526831692 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 5971619158 ps |
| CPU time | 1223.81 seconds |
| Started | May 30 04:13:22 PM PDT 24 |
| Finished | May 30 04:33:47 PM PDT 24 |
| Peak memory | 604040 kb |
| Host | smart-f477e351-546c-48ce-8db1-a19302d4e716 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2526831692 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.2526831692 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.3999052935 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 2465356040 ps |
| CPU time | 208.97 seconds |
| Started | May 30 04:16:35 PM PDT 24 |
| Finished | May 30 04:20:05 PM PDT 24 |
| Peak memory | 603736 kb |
| Host | smart-36d1b5be-135c-4dc8-a6d1-c351ef461976 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999052935 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rv_plic_smoketest.3999052935 |
| Directory | /workspace/0.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_irq.3812328853 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 3143004864 ps |
| CPU time | 335.84 seconds |
| Started | May 30 04:11:30 PM PDT 24 |
| Finished | May 30 04:17:07 PM PDT 24 |
| Peak memory | 603540 kb |
| Host | smart-fc00dc5d-cb99-4d37-96b6-82d3d86c050a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812328853 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_irq.3812328853 |
| Directory | /workspace/0.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.1036816237 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 2691343140 ps |
| CPU time | 281.13 seconds |
| Started | May 30 04:12:48 PM PDT 24 |
| Finished | May 30 04:17:31 PM PDT 24 |
| Peak memory | 603512 kb |
| Host | smart-6d399c44-21c6-43c3-b90f-cf770311f136 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036816237 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_smoketest.1036816237 |
| Directory | /workspace/0.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_systick_test.1978423639 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 38151908816 ps |
| CPU time | 6694.11 seconds |
| Started | May 30 04:09:14 PM PDT 24 |
| Finished | May 30 06:00:49 PM PDT 24 |
| Peak memory | 603872 kb |
| Host | smart-5d1c1c53-e451-4267-aa8a-b2ecd1a9cd73 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=rv_timer_systick_test:1:new_rules,test_rom:0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197842363 9 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_timer_systick_test.1978423639 |
| Directory | /workspace/0.chip_sw_rv_timer_systick_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.2517997602 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 2959725686 ps |
| CPU time | 249.59 seconds |
| Started | May 30 04:12:08 PM PDT 24 |
| Finished | May 30 04:16:19 PM PDT 24 |
| Peak memory | 604372 kb |
| Host | smart-bd9ab39d-f4ba-46a7-9c09-40d127f63eb7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517997 602 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.2517997602 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.3474152646 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 7297445792 ps |
| CPU time | 1398.88 seconds |
| Started | May 30 04:10:20 PM PDT 24 |
| Finished | May 30 04:33:40 PM PDT 24 |
| Peak memory | 604460 kb |
| Host | smart-ae1e6acd-eeb2-460f-949c-a92363e266ba |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474152646 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_sleep_pwm_pulses.3474152646 |
| Directory | /workspace/0.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.4111279109 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 5995748672 ps |
| CPU time | 524.65 seconds |
| Started | May 30 04:11:13 PM PDT 24 |
| Finished | May 30 04:19:59 PM PDT 24 |
| Peak memory | 605416 kb |
| Host | smart-7cd625db-3203-440d-9646-a5a0254037b0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111279109 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sl eep_sram_ret_contents_no_scramble.4111279109 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1955107171 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 7568958992 ps |
| CPU time | 524.76 seconds |
| Started | May 30 04:12:02 PM PDT 24 |
| Finished | May 30 04:20:47 PM PDT 24 |
| Peak memory | 605428 kb |
| Host | smart-06659982-a45a-40da-8053-d953bf4f0482 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955107171 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep _sram_ret_contents_scramble.1955107171 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through.789101508 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 7128513048 ps |
| CPU time | 836.85 seconds |
| Started | May 30 04:10:13 PM PDT 24 |
| Finished | May 30 04:24:12 PM PDT 24 |
| Peak memory | 623468 kb |
| Host | smart-a0815e7a-3304-4a7e-aba6-2eede1020e74 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789101508 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through.789101508 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_tpm.165866070 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 3336809863 ps |
| CPU time | 338.14 seconds |
| Started | May 30 04:12:07 PM PDT 24 |
| Finished | May 30 04:17:46 PM PDT 24 |
| Peak memory | 612152 kb |
| Host | smart-0f8dddd2-7cf4-4950-9857-be6918bd9653 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165866070 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_tpm.165866070 |
| Directory | /workspace/0.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1125206444 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 3467711562 ps |
| CPU time | 295.07 seconds |
| Started | May 30 04:09:56 PM PDT 24 |
| Finished | May 30 04:14:52 PM PDT 24 |
| Peak memory | 603744 kb |
| Host | smart-f6e724fc-ea93-41a8-9ad9-4a0ece6b60a8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125206444 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_spi_host_tx_rx.1125206444 |
| Directory | /workspace/0.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.3787123922 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 4903183772 ps |
| CPU time | 643.72 seconds |
| Started | May 30 04:11:19 PM PDT 24 |
| Finished | May 30 04:22:04 PM PDT 24 |
| Peak memory | 604500 kb |
| Host | smart-2ef6d7a6-12ac-4348-bd67-fdc7916ab41d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787123922 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _sram_ctrl_scrambled_access.3787123922 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.3069095457 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 4600621219 ps |
| CPU time | 563.32 seconds |
| Started | May 30 04:15:17 PM PDT 24 |
| Finished | May 30 04:24:41 PM PDT 24 |
| Peak memory | 604272 kb |
| Host | smart-701d65da-989a-49ae-8deb-6869f92e4d16 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069095457 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.chip_sw_sram_ctrl_scrambled_access_jitter_en.3069095457 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.2019227852 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 2830792728 ps |
| CPU time | 223.82 seconds |
| Started | May 30 04:16:13 PM PDT 24 |
| Finished | May 30 04:19:58 PM PDT 24 |
| Peak memory | 603216 kb |
| Host | smart-a3b4db8b-ec2f-4079-8ca6-9c517087c02a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019227852 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_sram_ctrl_smoketest.2019227852 |
| Directory | /workspace/0.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.1374942557 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 20155012511 ps |
| CPU time | 3395.79 seconds |
| Started | May 30 04:12:50 PM PDT 24 |
| Finished | May 30 05:09:28 PM PDT 24 |
| Peak memory | 604264 kb |
| Host | smart-a9b5165c-0377-4938-bb65-1fac650e1887 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374942557 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.1374942557 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.4234636122 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 4923910611 ps |
| CPU time | 777.19 seconds |
| Started | May 30 04:17:25 PM PDT 24 |
| Finished | May 30 04:30:26 PM PDT 24 |
| Peak memory | 608344 kb |
| Host | smart-d6930d43-bf45-453b-854e-ed1641326f4f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234636122 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_in_irq.4234636122 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.4270268845 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 2862525959 ps |
| CPU time | 273.94 seconds |
| Started | May 30 04:10:53 PM PDT 24 |
| Finished | May 30 04:15:29 PM PDT 24 |
| Peak memory | 607984 kb |
| Host | smart-3e35d471-6071-4730-be3f-381cb7beedb5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270268845 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_inputs.4270268845 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2340446331 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 22270848250 ps |
| CPU time | 2147.1 seconds |
| Started | May 30 04:11:40 PM PDT 24 |
| Finished | May 30 04:47:28 PM PDT 24 |
| Peak memory | 608372 kb |
| Host | smart-c6abd159-89ee-4629-b429-3b2fc936745c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23404463 31 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.2340446331 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.985323300 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 4597974832 ps |
| CPU time | 432.29 seconds |
| Started | May 30 04:13:15 PM PDT 24 |
| Finished | May 30 04:20:29 PM PDT 24 |
| Peak memory | 604060 kb |
| Host | smart-31f5cf0c-24ac-4580-8e64-7a1ebce5c9f1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985323300 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.985323300 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.468420727 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 7996159880 ps |
| CPU time | 1547.28 seconds |
| Started | May 30 04:10:13 PM PDT 24 |
| Finished | May 30 04:36:01 PM PDT 24 |
| Peak memory | 612400 kb |
| Host | smart-89e40b80-be3d-4f50-9a21-3d18805ea5ee |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=468420727 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.468420727 |
| Directory | /workspace/0.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_smoketest.293728514 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 2738418680 ps |
| CPU time | 269.31 seconds |
| Started | May 30 04:14:25 PM PDT 24 |
| Finished | May 30 04:18:55 PM PDT 24 |
| Peak memory | 603828 kb |
| Host | smart-4475aae8-860f-4355-9450-ff60a684bc07 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293728514 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_uart_smoketest.293728514 |
| Directory | /workspace/0.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx.1105146227 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 3671803514 ps |
| CPU time | 626.67 seconds |
| Started | May 30 04:09:49 PM PDT 24 |
| Finished | May 30 04:20:17 PM PDT 24 |
| Peak memory | 612212 kb |
| Host | smart-cf8f5974-f02f-45b2-ae26-57fc4bda7701 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105146227 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.1105146227 |
| Directory | /workspace/0.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3599793416 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 3931021434 ps |
| CPU time | 448.9 seconds |
| Started | May 30 04:09:44 PM PDT 24 |
| Finished | May 30 04:17:14 PM PDT 24 |
| Peak memory | 612052 kb |
| Host | smart-f78ca720-cc9d-4a6d-b2f2-a4de4ca4f4f8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599793416 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.3599793416 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.328805004 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 4696887200 ps |
| CPU time | 639.65 seconds |
| Started | May 30 04:09:30 PM PDT 24 |
| Finished | May 30 04:20:10 PM PDT 24 |
| Peak memory | 609928 kb |
| Host | smart-7c38ea84-ce6d-4932-93cb-810bc83af51f |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328805004 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.328805004 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.1939954046 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 4262629170 ps |
| CPU time | 710.36 seconds |
| Started | May 30 04:09:31 PM PDT 24 |
| Finished | May 30 04:21:23 PM PDT 24 |
| Peak memory | 612196 kb |
| Host | smart-66e4ede7-390c-44f8-94d9-e1f97e02161c |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939954046 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.1939954046 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.3388958865 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 2887202404 ps |
| CPU time | 366.21 seconds |
| Started | May 30 04:12:57 PM PDT 24 |
| Finished | May 30 04:19:06 PM PDT 24 |
| Peak memory | 603880 kb |
| Host | smart-813153e1-e91f-40f9-babb-55e40ff579a7 |
| User | root |
| Command | /workspace/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw_images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388958865 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.3388958865 |
| Directory | /workspace/0.chip_sw_usb_ast_clk_calib/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_dpi.2274974207 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 12357962166 ps |
| CPU time | 2929.05 seconds |
| Started | May 30 04:11:03 PM PDT 24 |
| Finished | May 30 04:59:54 PM PDT 24 |
| Peak memory | 604124 kb |
| Host | smart-7cd6181d-5806-427a-8eff-7b94b216332c |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2274974207 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.2274974207 |
| Directory | /workspace/0.chip_sw_usbdev_dpi/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pincfg.2812493479 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 31367845816 ps |
| CPU time | 6264.07 seconds |
| Started | May 30 04:09:23 PM PDT 24 |
| Finished | May 30 05:53:48 PM PDT 24 |
| Peak memory | 604152 kb |
| Host | smart-f829bdc2-c72c-45a8-bba4-5f1600deb258 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2812493479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.2812493479 |
| Directory | /workspace/0.chip_sw_usbdev_pincfg/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pullup.1361618295 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 3202456852 ps |
| CPU time | 360.88 seconds |
| Started | May 30 04:11:51 PM PDT 24 |
| Finished | May 30 04:17:53 PM PDT 24 |
| Peak memory | 603572 kb |
| Host | smart-2fe3925b-10b6-4f09-9581-43f4b02112d1 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361618295 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.1361618295 |
| Directory | /workspace/0.chip_sw_usbdev_pullup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_setuprx.1223416300 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 3973598500 ps |
| CPU time | 570.41 seconds |
| Started | May 30 04:10:12 PM PDT 24 |
| Finished | May 30 04:19:44 PM PDT 24 |
| Peak memory | 603536 kb |
| Host | smart-bc223de1-00f8-4895-9592-97024f202e24 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122341630 0 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.1223416300 |
| Directory | /workspace/0.chip_sw_usbdev_setuprx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_stream.693011615 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 18506526110 ps |
| CPU time | 4181.48 seconds |
| Started | May 30 04:09:29 PM PDT 24 |
| Finished | May 30 05:19:12 PM PDT 24 |
| Peak memory | 604056 kb |
| Host | smart-8117ec48-0a2f-472a-a4d7-8815721b68bb |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=693011615 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.693011615 |
| Directory | /workspace/0.chip_sw_usbdev_stream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_vbus.668360028 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 2515870690 ps |
| CPU time | 286.76 seconds |
| Started | May 30 04:09:14 PM PDT 24 |
| Finished | May 30 04:14:02 PM PDT 24 |
| Peak memory | 603604 kb |
| Host | smart-5db0bf7b-f554-4664-9e6a-7b1d0da0069e |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668360028 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.668360028 |
| Directory | /workspace/0.chip_sw_usbdev_vbus/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_dev.34468406 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 3255114139 ps |
| CPU time | 249.08 seconds |
| Started | May 30 04:19:49 PM PDT 24 |
| Finished | May 30 04:23:59 PM PDT 24 |
| Peak memory | 614852 kb |
| Host | smart-05d0b379-6b82-417a-a8a0-88326b70fc96 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=34468406 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_dev.34468406 |
| Directory | /workspace/0.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_prod.3246110751 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 2970817554 ps |
| CPU time | 133.87 seconds |
| Started | May 30 04:12:18 PM PDT 24 |
| Finished | May 30 04:14:33 PM PDT 24 |
| Peak memory | 614604 kb |
| Host | smart-68435bcf-7ca3-40a6-94e7-0011111a405e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246110751 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.3246110751 |
| Directory | /workspace/0.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_rma.2198609147 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 3728895890 ps |
| CPU time | 256.32 seconds |
| Started | May 30 04:11:38 PM PDT 24 |
| Finished | May 30 04:15:56 PM PDT 24 |
| Peak memory | 614384 kb |
| Host | smart-06e0af1b-3926-48f7-81d1-0639abc08100 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198609147 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_rma.2198609147 |
| Directory | /workspace/0.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_testunlock0.1107589275 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 6644572720 ps |
| CPU time | 667.02 seconds |
| Started | May 30 04:10:16 PM PDT 24 |
| Finished | May 30 04:21:24 PM PDT 24 |
| Peak memory | 615248 kb |
| Host | smart-75973494-66d8-4712-8ecc-cc0a73a48d3e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1107589275 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_testunlock0.1107589275 |
| Directory | /workspace/0.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_dev.2839715140 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 14115351409 ps |
| CPU time | 3910.15 seconds |
| Started | May 30 04:22:34 PM PDT 24 |
| Finished | May 30 05:27:45 PM PDT 24 |
| Peak memory | 605288 kb |
| Host | smart-cd623c81-fb46-48f6-aa48-b3ff482b0ec4 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839715140 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_dev.2839715140 |
| Directory | /workspace/0.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod.614747640 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 14188210305 ps |
| CPU time | 3118.16 seconds |
| Started | May 30 04:19:30 PM PDT 24 |
| Finished | May 30 05:11:30 PM PDT 24 |
| Peak memory | 605080 kb |
| Host | smart-665dfe05-4ee4-42a3-a05c-88415b521796 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614747640 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_prod.614747640 |
| Directory | /workspace/0.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.3775519512 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 13914393237 ps |
| CPU time | 3514.81 seconds |
| Started | May 30 04:17:13 PM PDT 24 |
| Finished | May 30 05:15:48 PM PDT 24 |
| Peak memory | 605264 kb |
| Host | smart-5982782a-133e-46bd-9245-00749b97ec95 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775519512 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.rom_e2e_asm_init_prod_end.3775519512 |
| Directory | /workspace/0.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_rma.1381976600 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 14195118583 ps |
| CPU time | 3101.07 seconds |
| Started | May 30 04:17:53 PM PDT 24 |
| Finished | May 30 05:09:35 PM PDT 24 |
| Peak memory | 603768 kb |
| Host | smart-be4aa749-1495-47b8-9f27-3fc3e4a59141 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381976600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_rma.1381976600 |
| Directory | /workspace/0.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.2187192334 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 10962174807 ps |
| CPU time | 3050.73 seconds |
| Started | May 30 04:20:09 PM PDT 24 |
| Finished | May 30 05:11:01 PM PDT 24 |
| Peak memory | 605344 kb |
| Host | smart-43378356-65ed-4a98-8003-357bda745d88 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187192334 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.rom_e2e_asm_init_test_unlocked0.2187192334 |
| Directory | /workspace/0.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3659688992 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 22323551614 ps |
| CPU time | 5227.37 seconds |
| Started | May 30 04:18:46 PM PDT 24 |
| Finished | May 30 05:45:55 PM PDT 24 |
| Peak memory | 603932 kb |
| Host | smart-ef97a572-f2f0-4ee7-aa85-ee15eec395ca |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3659688992 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3659688992 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.685678664 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 22239462360 ps |
| CPU time | 6041.79 seconds |
| Started | May 30 04:18:52 PM PDT 24 |
| Finished | May 30 05:59:36 PM PDT 24 |
| Peak memory | 603964 kb |
| Host | smart-54827562-a317-41b3-b36b-f19dcf4e1ac5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=685678664 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.685678664 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.4204902566 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 23202954240 ps |
| CPU time | 5199.57 seconds |
| Started | May 30 04:21:24 PM PDT 24 |
| Finished | May 30 05:48:05 PM PDT 24 |
| Peak memory | 605448 kb |
| Host | smart-febaea91-fe6c-4ad6-88a5-5af47f85dc9a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=4204902566 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.4204902566 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.4013526314 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 23347458648 ps |
| CPU time | 7101.92 seconds |
| Started | May 30 04:21:49 PM PDT 24 |
| Finished | May 30 06:20:13 PM PDT 24 |
| Peak memory | 604972 kb |
| Host | smart-41dd2ed0-a52c-4473-bc0e-7cd06b97028e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4013526314 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.4013526314 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1064702030 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 14233643000 ps |
| CPU time | 3380.04 seconds |
| Started | May 30 04:17:34 PM PDT 24 |
| Finished | May 30 05:13:55 PM PDT 24 |
| Peak memory | 605404 kb |
| Host | smart-82ad83b3-ba0d-4c6c-9242-172e37dc7c23 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1064702030 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1064702030 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3095062546 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 14068691556 ps |
| CPU time | 3764.94 seconds |
| Started | May 30 04:19:39 PM PDT 24 |
| Finished | May 30 05:22:26 PM PDT 24 |
| Peak memory | 605472 kb |
| Host | smart-5a788490-c413-4c1e-a5fb-829acf035f53 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3095062546 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3095062546 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3158982973 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 14639839350 ps |
| CPU time | 3901.04 seconds |
| Started | May 30 04:18:23 PM PDT 24 |
| Finished | May 30 05:23:26 PM PDT 24 |
| Peak memory | 605460 kb |
| Host | smart-8d1ccee8-87b1-4862-8ee2-1d53d7d45469 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3158982973 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3158982973 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1370553648 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 13765748240 ps |
| CPU time | 3504.69 seconds |
| Started | May 30 04:21:42 PM PDT 24 |
| Finished | May 30 05:20:09 PM PDT 24 |
| Peak memory | 603580 kb |
| Host | smart-df4540b5-76ed-4d66-ac9e-c7f1a1583a0a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1370553648 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1370553648 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.270153715 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 10831590128 ps |
| CPU time | 2703.49 seconds |
| Started | May 30 04:18:33 PM PDT 24 |
| Finished | May 30 05:03:38 PM PDT 24 |
| Peak memory | 605444 kb |
| Host | smart-71a6913d-670c-4cbd-92e2-01c95695f3ab |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270153715 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.270153715 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2121958283 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 13891125020 ps |
| CPU time | 3258.59 seconds |
| Started | May 30 04:21:35 PM PDT 24 |
| Finished | May 30 05:15:54 PM PDT 24 |
| Peak memory | 604976 kb |
| Host | smart-9bfed942-b02c-4e54-9c4d-65b3051848f1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121958283 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2121958283 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2843912497 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 14096620208 ps |
| CPU time | 3683.2 seconds |
| Started | May 30 04:18:30 PM PDT 24 |
| Finished | May 30 05:19:54 PM PDT 24 |
| Peak memory | 603884 kb |
| Host | smart-4cfe3ad4-faf1-415b-aed1-cc0c28707446 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843912497 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2843912497 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3275573640 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 14227526688 ps |
| CPU time | 3908.59 seconds |
| Started | May 30 04:19:13 PM PDT 24 |
| Finished | May 30 05:24:22 PM PDT 24 |
| Peak memory | 603924 kb |
| Host | smart-4a50bb70-5794-4fa3-9c22-15b297b01f34 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327557 3640 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3275573640 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.3022902981 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 14414020244 ps |
| CPU time | 3760.07 seconds |
| Started | May 30 04:17:33 PM PDT 24 |
| Finished | May 30 05:20:14 PM PDT 24 |
| Peak memory | 603888 kb |
| Host | smart-ab4564a9-27fe-491c-9c86-ffbd6dc1cafe |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022902981 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.3022902981 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.3662271371 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 11296578720 ps |
| CPU time | 3303.14 seconds |
| Started | May 30 04:21:21 PM PDT 24 |
| Finished | May 30 05:16:26 PM PDT 24 |
| Peak memory | 603524 kb |
| Host | smart-b19dc1bb-425b-45d5-907d-be500fb9f907 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3662271371 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.3662271371 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.3242409672 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 14187409386 ps |
| CPU time | 3606.02 seconds |
| Started | May 30 04:19:40 PM PDT 24 |
| Finished | May 30 05:19:47 PM PDT 24 |
| Peak memory | 603988 kb |
| Host | smart-2c57b2c6-11e4-4093-bb3b-d872d7bfee5b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242409672 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_in it_rom_ext_invalid_meas.3242409672 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.335740222 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 15675630780 ps |
| CPU time | 3691.25 seconds |
| Started | May 30 04:21:31 PM PDT 24 |
| Finished | May 30 05:23:03 PM PDT 24 |
| Peak memory | 603920 kb |
| Host | smart-81cd9d52-5942-4e74-b38a-da5fda700e98 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335740222 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_meas.335740222 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.2638826887 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 14469780084 ps |
| CPU time | 3520.97 seconds |
| Started | May 30 04:22:43 PM PDT 24 |
| Finished | May 30 05:21:25 PM PDT 24 |
| Peak memory | 603944 kb |
| Host | smart-43825c86-9452-4a22-a246-97810e02390d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638826887 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext _no_meas.2638826887 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.1986372447 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 14029625915 ps |
| CPU time | 3136.65 seconds |
| Started | May 30 04:19:15 PM PDT 24 |
| Finished | May 30 05:11:34 PM PDT 24 |
| Peak memory | 604160 kb |
| Host | smart-ac57685f-3dc2-4bce-8977-6b501e1594b7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986372447 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_ shutdown_exception_c.1986372447 |
| Directory | /workspace/0.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_output.2495243265 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 24513032568 ps |
| CPU time | 2828.38 seconds |
| Started | May 30 04:16:59 PM PDT 24 |
| Finished | May 30 05:04:09 PM PDT 24 |
| Peak memory | 605804 kb |
| Host | smart-da341a4f-4fc6-4749-bf99-3b12ae5b65b8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495243265 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_shutdown_output.2495243265 |
| Directory | /workspace/0.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.1686918926 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 21044642064 ps |
| CPU time | 5193.61 seconds |
| Started | May 30 04:19:48 PM PDT 24 |
| Finished | May 30 05:46:23 PM PDT 24 |
| Peak memory | 605424 kb |
| Host | smart-da891edb-a4ed-48b5-abf0-e1449235ff3b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev :4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1686918926 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_b ad_dev.1686918926 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.3672683921 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 22493121928 ps |
| CPU time | 5563.9 seconds |
| Started | May 30 04:20:39 PM PDT 24 |
| Finished | May 30 05:53:24 PM PDT 24 |
| Peak memory | 605272 kb |
| Host | smart-0c76b9e6-bd17-4ada-9859-7e941d350c99 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3672683921 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_ b_bad_prod.3672683921 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.2669366235 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 21832332976 ps |
| CPU time | 4865.52 seconds |
| Started | May 30 04:18:32 PM PDT 24 |
| Finished | May 30 05:39:38 PM PDT 24 |
| Peak memory | 605148 kb |
| Host | smart-da679d5b-354f-4890-b357-f7cf7514670b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=2669366235 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_ bad_b_bad_prod_end.2669366235 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.2477891953 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 21730191258 ps |
| CPU time | 5351.93 seconds |
| Started | May 30 04:18:45 PM PDT 24 |
| Finished | May 30 05:47:58 PM PDT 24 |
| Peak memory | 605200 kb |
| Host | smart-898b661e-bd26-4707-aeda-5b3df14dc18f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_r ma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2477891953 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b _bad_rma.2477891953 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.1980159737 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 16588021867 ps |
| CPU time | 4660.22 seconds |
| Started | May 30 04:19:59 PM PDT 24 |
| Finished | May 30 05:37:40 PM PDT 24 |
| Peak memory | 605288 kb |
| Host | smart-8d13acfd-c711-4609-a9f7-52649ab1117e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=600_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_t est_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=1980159737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b _bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_alw ays_a_bad_b_bad_test_unlocked0.1980159737 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.914641119 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 14039551884 ps |
| CPU time | 2983.12 seconds |
| Started | May 30 04:18:24 PM PDT 24 |
| Finished | May 30 05:08:08 PM PDT 24 |
| Peak memory | 603860 kb |
| Host | smart-c3a5ed42-665b-4e6a-b96a-1e710e0ff6ec |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914641119 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.914641119 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.620718910 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 13688513936 ps |
| CPU time | 3881.93 seconds |
| Started | May 30 04:20:24 PM PDT 24 |
| Finished | May 30 05:25:07 PM PDT 24 |
| Peak memory | 603720 kb |
| Host | smart-be6e70f9-4fc9-4fb8-ba74-bf4f743b4fda |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620718910 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.620718910 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1435683895 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 13443633732 ps |
| CPU time | 3779.39 seconds |
| Started | May 30 04:19:16 PM PDT 24 |
| Finished | May 30 05:22:17 PM PDT 24 |
| Peak memory | 603768 kb |
| Host | smart-4abeb72c-fa73-43da-969c-fae5b00a9a65 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435683895 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1435683895 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.2121200143 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 10365557869 ps |
| CPU time | 2736.09 seconds |
| Started | May 30 04:18:00 PM PDT 24 |
| Finished | May 30 05:03:37 PM PDT 24 |
| Peak memory | 604572 kb |
| Host | smart-61c858de-4538-4749-9c9b-1fe40d009eb4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0:new_rules,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121200143 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.2121200143 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.4269919156 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 13845322268 ps |
| CPU time | 3662.22 seconds |
| Started | May 30 04:18:19 PM PDT 24 |
| Finished | May 30 05:19:22 PM PDT 24 |
| Peak memory | 603892 kb |
| Host | smart-978f1db7-e92f-42b7-8a01-aeaf21ba1e05 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269919156 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.4269919156 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.574941143 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 13189969621 ps |
| CPU time | 3348.87 seconds |
| Started | May 30 04:19:10 PM PDT 24 |
| Finished | May 30 05:15:00 PM PDT 24 |
| Peak memory | 604216 kb |
| Host | smart-86760166-bf47-4659-9c53-3988d47da270 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574941143 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.574941143 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.830454555 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 13413498296 ps |
| CPU time | 4294.84 seconds |
| Started | May 30 04:19:17 PM PDT 24 |
| Finished | May 30 05:30:53 PM PDT 24 |
| Peak memory | 604184 kb |
| Host | smart-96dd5456-6860-4eec-9a23-d54e630bc801 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830454555 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.830454555 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.3981687968 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 13582622974 ps |
| CPU time | 4139.95 seconds |
| Started | May 30 04:17:58 PM PDT 24 |
| Finished | May 30 05:26:59 PM PDT 24 |
| Peak memory | 604288 kb |
| Host | smart-e3007339-57d0-45c5-a982-457f43f66033 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981687968 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.3981687968 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.4183315742 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 10842394333 ps |
| CPU time | 2821.23 seconds |
| Started | May 30 04:20:15 PM PDT 24 |
| Finished | May 30 05:07:17 PM PDT 24 |
| Peak memory | 604412 kb |
| Host | smart-14379f06-aa6d-48b5-86ef-6a5233d98859 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183315742 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.4183315742 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_smoke.170685463 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 15098218732 ps |
| CPU time | 4047.67 seconds |
| Started | May 30 04:18:17 PM PDT 24 |
| Finished | May 30 05:25:46 PM PDT 24 |
| Peak memory | 604064 kb |
| Host | smart-f62e5d44-f11b-4a2d-909d-6e3dedfe971b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=170685463 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.170685463 |
| Directory | /workspace/0.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/0.rom_keymgr_functest.3756553592 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 4405158356 ps |
| CPU time | 716.3 seconds |
| Started | May 30 04:16:39 PM PDT 24 |
| Finished | May 30 04:28:37 PM PDT 24 |
| Peak memory | 604064 kb |
| Host | smart-6303eff8-c88b-4e68-b1e5-c85cb0b29ced |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756553592 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_keymgr_functest.3756553592 |
| Directory | /workspace/0.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/0.rom_volatile_raw_unlock.2902732855 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 2599804369 ps |
| CPU time | 101.9 seconds |
| Started | May 30 04:15:56 PM PDT 24 |
| Finished | May 30 04:17:39 PM PDT 24 |
| Peak memory | 610468 kb |
| Host | smart-8f72d421-6c8a-453f-b482-ba567f8b18e4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902732855 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.2902732855 |
| Directory | /workspace/0.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_mem_access.4257359904 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 13649777530 ps |
| CPU time | 1656.22 seconds |
| Started | May 30 04:12:29 PM PDT 24 |
| Finished | May 30 04:40:08 PM PDT 24 |
| Peak memory | 604604 kb |
| Host | smart-a2dd62be-0843-4f55-af94-9fb9fd9760ec |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257359904 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.4 257359904 |
| Directory | /workspace/1.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.1815732881 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 3565861752 ps |
| CPU time | 361.51 seconds |
| Started | May 30 04:20:57 PM PDT 24 |
| Finished | May 30 04:27:00 PM PDT 24 |
| Peak memory | 613092 kb |
| Host | smart-9243f481-b152-419f-afea-ccee3cdeae02 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1 815732881 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.1815732881 |
| Directory | /workspace/1.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sival_flash_info_access.3811899023 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 3496937172 ps |
| CPU time | 307.84 seconds |
| Started | May 30 04:13:41 PM PDT 24 |
| Finished | May 30 04:18:50 PM PDT 24 |
| Peak memory | 603184 kb |
| Host | smart-36b7d605-2ae6-4f62-abc1-6ae7cebbe580 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3811899023 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.3811899023 |
| Directory | /workspace/1.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3927787384 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 19074667732 ps |
| CPU time | 591.58 seconds |
| Started | May 30 04:17:41 PM PDT 24 |
| Finished | May 30 04:27:34 PM PDT 24 |
| Peak memory | 611100 kb |
| Host | smart-1a45ddd9-d77c-49d9-9a72-3bb3fd80c3f2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3927787384 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3927787384 |
| Directory | /workspace/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc.859383538 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 2356328968 ps |
| CPU time | 320.58 seconds |
| Started | May 30 04:22:13 PM PDT 24 |
| Finished | May 30 04:27:36 PM PDT 24 |
| Peak memory | 603832 kb |
| Host | smart-37c6d079-728c-4105-b7e9-d939c05be344 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859383538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.859383538 |
| Directory | /workspace/1.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.1524841674 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 2790521100 ps |
| CPU time | 193.28 seconds |
| Started | May 30 04:16:52 PM PDT 24 |
| Finished | May 30 04:20:07 PM PDT 24 |
| Peak memory | 603424 kb |
| Host | smart-28ec4446-deb2-4ae3-af54-06ac89f84d0a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524 841674 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.1524841674 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2743963544 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 2587035109 ps |
| CPU time | 242.1 seconds |
| Started | May 30 04:22:06 PM PDT 24 |
| Finished | May 30 04:26:09 PM PDT 24 |
| Peak memory | 603684 kb |
| Host | smart-79d7e41a-41b3-4e87-8b4e-88a1019dc402 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743963544 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.2743963544 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_entropy.594824282 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 2917512796 ps |
| CPU time | 273.55 seconds |
| Started | May 30 04:18:41 PM PDT 24 |
| Finished | May 30 04:23:15 PM PDT 24 |
| Peak memory | 603624 kb |
| Host | smart-61f8a002-61aa-4ba3-9989-a4529d3c466b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594824282 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_entropy.594824282 |
| Directory | /workspace/1.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_idle.331075792 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 3678365272 ps |
| CPU time | 281.1 seconds |
| Started | May 30 04:17:45 PM PDT 24 |
| Finished | May 30 04:22:27 PM PDT 24 |
| Peak memory | 603812 kb |
| Host | smart-2fc06885-1603-416a-be11-c8bce219d62c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331075792 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.331075792 |
| Directory | /workspace/1.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_masking_off.1010941062 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 3196061353 ps |
| CPU time | 261.7 seconds |
| Started | May 30 04:16:37 PM PDT 24 |
| Finished | May 30 04:20:59 PM PDT 24 |
| Peak memory | 603980 kb |
| Host | smart-0e6cd11b-5446-497d-a709-3888a9a89d5f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010941062 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_masking_off.1010941062 |
| Directory | /workspace/1.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_smoketest.3864174415 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 2592862170 ps |
| CPU time | 307.42 seconds |
| Started | May 30 04:25:07 PM PDT 24 |
| Finished | May 30 04:30:17 PM PDT 24 |
| Peak memory | 603488 kb |
| Host | smart-1f419d6e-e205-40ca-ab23-135af2989262 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864174415 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_smoketest.3864174415 |
| Directory | /workspace/1.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_entropy.1704881403 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 3061487574 ps |
| CPU time | 352.73 seconds |
| Started | May 30 04:16:52 PM PDT 24 |
| Finished | May 30 04:22:46 PM PDT 24 |
| Peak memory | 604712 kb |
| Host | smart-bdb01943-9183-49ee-b13c-df899b5b019c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1704881403 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.1704881403 |
| Directory | /workspace/1.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_escalation.1031173030 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 4491512996 ps |
| CPU time | 496.04 seconds |
| Started | May 30 04:17:26 PM PDT 24 |
| Finished | May 30 04:25:43 PM PDT 24 |
| Peak memory | 611044 kb |
| Host | smart-a8f4d231-f1c6-4b5b-9c30-5a12e6da6751 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1031173030 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.1031173030 |
| Directory | /workspace/1.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.83404662 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 6694794956 ps |
| CPU time | 1652.63 seconds |
| Started | May 30 04:17:04 PM PDT 24 |
| Finished | May 30 04:44:38 PM PDT 24 |
| Peak memory | 604788 kb |
| Host | smart-da874882-064f-4cf7-9745-2c92a02f9021 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=83404662 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.83404662 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.2471650290 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 8628530650 ps |
| CPU time | 2034.43 seconds |
| Started | May 30 04:17:14 PM PDT 24 |
| Finished | May 30 04:51:09 PM PDT 24 |
| Peak memory | 604328 kb |
| Host | smart-a67d175d-e4fe-4d17-a9d6-9f52cdcec498 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471650290 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_togg le.2471650290 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.749044035 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 3857592520 ps |
| CPU time | 431.22 seconds |
| Started | May 30 04:19:10 PM PDT 24 |
| Finished | May 30 04:26:23 PM PDT 24 |
| Peak memory | 638148 kb |
| Host | smart-94a2cb76-a016-4c83-ade5-ee99719c408b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749044035 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _alert_handler_lpg_sleep_mode_alerts.749044035 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1385759417 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 9944069684 ps |
| CPU time | 1011.13 seconds |
| Started | May 30 04:17:20 PM PDT 24 |
| Finished | May 30 04:34:12 PM PDT 24 |
| Peak memory | 605640 kb |
| Host | smart-8f3ab5b2-ed43-41d4-a85b-b0cb39b64293 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385759417 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_sleep_mode_pings.1385759417 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.1602450188 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 3951770952 ps |
| CPU time | 499.53 seconds |
| Started | May 30 04:18:20 PM PDT 24 |
| Finished | May 30 04:26:40 PM PDT 24 |
| Peak memory | 603560 kb |
| Host | smart-1d6320a7-723f-4b20-83a7-1caf00c09ede |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1602450188 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.1602450188 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1825690998 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 254899740338 ps |
| CPU time | 11198 seconds |
| Started | May 30 04:16:50 PM PDT 24 |
| Finished | May 30 07:23:30 PM PDT 24 |
| Peak memory | 605520 kb |
| Host | smart-17ef9c4a-d916-4c77-bc5a-e91a369df721 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1825690998 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1825690998 |
| Directory | /workspace/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_test.2777495155 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 3155394610 ps |
| CPU time | 354.62 seconds |
| Started | May 30 04:16:29 PM PDT 24 |
| Finished | May 30 04:22:25 PM PDT 24 |
| Peak memory | 603568 kb |
| Host | smart-c98377ac-6d8d-429a-8ada-08557baeeae5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777495155 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.chip_sw_alert_test.2777495155 |
| Directory | /workspace/1.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_irq.889941612 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 4116175912 ps |
| CPU time | 379.49 seconds |
| Started | May 30 04:18:03 PM PDT 24 |
| Finished | May 30 04:24:24 PM PDT 24 |
| Peak memory | 603700 kb |
| Host | smart-e688d685-2a0c-4a0a-922f-eb8f587f4cb8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889941612 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.889941612 |
| Directory | /workspace/1.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3707504355 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 6430203376 ps |
| CPU time | 412.36 seconds |
| Started | May 30 04:18:13 PM PDT 24 |
| Finished | May 30 04:25:06 PM PDT 24 |
| Peak memory | 604004 kb |
| Host | smart-c096e988-bd0d-4709-a938-910fd9562c61 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3707504355 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3707504355 |
| Directory | /workspace/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.4257826455 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 2707735400 ps |
| CPU time | 328.7 seconds |
| Started | May 30 04:22:58 PM PDT 24 |
| Finished | May 30 04:28:27 PM PDT 24 |
| Peak memory | 603512 kb |
| Host | smart-56b4dd7b-9c44-4f24-b212-21e0709b8bf9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257826455 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_aon_timer_smoketest.4257826455 |
| Directory | /workspace/1.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.501383834 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 9374278804 ps |
| CPU time | 960.2 seconds |
| Started | May 30 04:17:19 PM PDT 24 |
| Finished | May 30 04:33:20 PM PDT 24 |
| Peak memory | 605232 kb |
| Host | smart-0d8e2ef6-cf5c-4eb4-a3cb-8f803e2e2ea5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 501383834 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.501383834 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.2831990311 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 5389827288 ps |
| CPU time | 566.17 seconds |
| Started | May 30 04:17:43 PM PDT 24 |
| Finished | May 30 04:27:10 PM PDT 24 |
| Peak memory | 604312 kb |
| Host | smart-19e84043-6426-44c5-9edc-e01e136392b5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2831990311 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.2831990311 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_outputs.4196160931 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 7855520482 ps |
| CPU time | 1147.28 seconds |
| Started | May 30 04:19:18 PM PDT 24 |
| Finished | May 30 04:38:27 PM PDT 24 |
| Peak memory | 610400 kb |
| Host | smart-e9e7c220-023a-4852-aaa2-c3b286807192 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196160931 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.4196160931 |
| Directory | /workspace/1.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2208834880 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 5050809702 ps |
| CPU time | 340.72 seconds |
| Started | May 30 04:19:03 PM PDT 24 |
| Finished | May 30 04:24:45 PM PDT 24 |
| Peak memory | 615212 kb |
| Host | smart-a7b20911-afc6-4fab-8e16-0fb7dda47840 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2208834880 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.2208834880 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.128265376 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 4181817964 ps |
| CPU time | 582.64 seconds |
| Started | May 30 04:20:12 PM PDT 24 |
| Finished | May 30 04:29:56 PM PDT 24 |
| Peak memory | 607180 kb |
| Host | smart-6cf14811-40ae-4cb8-b7c9-ae07d7a0e1d7 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128265376 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_cl kmgr_external_clk_src_for_sw_fast_dev.128265376 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.4102514091 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 3488541886 ps |
| CPU time | 753.07 seconds |
| Started | May 30 04:21:12 PM PDT 24 |
| Finished | May 30 04:33:46 PM PDT 24 |
| Peak memory | 607268 kb |
| Host | smart-0f1311c1-c8f8-4875-b34e-b0e7bfb1b0e8 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102514091 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.4102514091 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.185631454 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 3722131616 ps |
| CPU time | 572.66 seconds |
| Started | May 30 04:20:54 PM PDT 24 |
| Finished | May 30 04:30:28 PM PDT 24 |
| Peak memory | 607856 kb |
| Host | smart-3c5af341-409a-4145-b44e-9923286b6f5c |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185631454 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1. chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.185631454 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.779348433 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 4617231400 ps |
| CPU time | 722.04 seconds |
| Started | May 30 04:21:15 PM PDT 24 |
| Finished | May 30 04:33:18 PM PDT 24 |
| Peak memory | 607204 kb |
| Host | smart-72db8865-69af-4d1a-be41-d41970f01be5 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779348433 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_cl kmgr_external_clk_src_for_sw_slow_dev.779348433 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1743248984 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 3908645832 ps |
| CPU time | 668.43 seconds |
| Started | May 30 04:21:12 PM PDT 24 |
| Finished | May 30 04:32:22 PM PDT 24 |
| Peak memory | 607264 kb |
| Host | smart-2b986266-7c1c-44c0-9aa2-600535a567ba |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743248984 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.1743248984 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1164694074 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 4955993600 ps |
| CPU time | 899.71 seconds |
| Started | May 30 04:20:34 PM PDT 24 |
| Finished | May 30 04:35:35 PM PDT 24 |
| Peak memory | 607236 kb |
| Host | smart-a2ca126e-6878-4404-8e72-70a3b7311c97 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164694074 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1164694074 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter.4169518173 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 2366080344 ps |
| CPU time | 303.17 seconds |
| Started | May 30 04:20:05 PM PDT 24 |
| Finished | May 30 04:25:09 PM PDT 24 |
| Peak memory | 603548 kb |
| Host | smart-a4aa3243-2f1b-43f5-9e7c-83c15b3981ca |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169518173 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_clkmgr_jitter.4169518173 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.2337083770 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 3817294088 ps |
| CPU time | 482.63 seconds |
| Started | May 30 04:24:24 PM PDT 24 |
| Finished | May 30 04:32:27 PM PDT 24 |
| Peak memory | 603536 kb |
| Host | smart-c4b152a3-bb77-4f4e-84ca-e2641b67c6df |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337083770 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_frequency.2337083770 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.2465481485 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 2262435574 ps |
| CPU time | 179.64 seconds |
| Started | May 30 04:23:20 PM PDT 24 |
| Finished | May 30 04:26:21 PM PDT 24 |
| Peak memory | 603184 kb |
| Host | smart-7fce7f73-738a-4d4d-933e-7976038cc21d |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465481485 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.2465481485 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2666984235 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 3832420664 ps |
| CPU time | 473.97 seconds |
| Started | May 30 04:18:52 PM PDT 24 |
| Finished | May 30 04:26:47 PM PDT 24 |
| Peak memory | 604640 kb |
| Host | smart-78741af3-9734-4aac-8373-92b8bc11afa5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666984235 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.2666984235 |
| Directory | /workspace/1.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.977979805 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 5737426288 ps |
| CPU time | 514.23 seconds |
| Started | May 30 04:18:34 PM PDT 24 |
| Finished | May 30 04:27:09 PM PDT 24 |
| Peak memory | 603972 kb |
| Host | smart-8be4dafc-e9f2-4a38-806f-ac4600f10c68 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977979805 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_hmac_trans.977979805 |
| Directory | /workspace/1.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.955377451 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 4143184744 ps |
| CPU time | 498.6 seconds |
| Started | May 30 04:21:16 PM PDT 24 |
| Finished | May 30 04:29:36 PM PDT 24 |
| Peak memory | 603644 kb |
| Host | smart-9029031c-214e-4d4e-b131-340dda49c10d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955377451 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_kmac_trans.955377451 |
| Directory | /workspace/1.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.3381083125 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 3426776400 ps |
| CPU time | 435.84 seconds |
| Started | May 30 04:19:44 PM PDT 24 |
| Finished | May 30 04:27:00 PM PDT 24 |
| Peak memory | 603672 kb |
| Host | smart-9c6a17c9-bf63-4f74-b8d7-4e9928b00723 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381083125 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_otbn_trans.3381083125 |
| Directory | /workspace/1.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.1062292321 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 12468714060 ps |
| CPU time | 1410.38 seconds |
| Started | May 30 04:18:00 PM PDT 24 |
| Finished | May 30 04:41:31 PM PDT 24 |
| Peak memory | 605336 kb |
| Host | smart-cd5796ed-ac5d-40c1-b81d-f147241dc13f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062292321 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.1062292321 |
| Directory | /workspace/1.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.1340027978 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 3691397064 ps |
| CPU time | 412.15 seconds |
| Started | May 30 04:20:20 PM PDT 24 |
| Finished | May 30 04:27:13 PM PDT 24 |
| Peak memory | 603592 kb |
| Host | smart-01168094-4a41-4fb0-97ce-f6b117b4b3c0 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340027978 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.1340027978 |
| Directory | /workspace/1.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.3478769674 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 4607558204 ps |
| CPU time | 721.01 seconds |
| Started | May 30 04:19:41 PM PDT 24 |
| Finished | May 30 04:31:43 PM PDT 24 |
| Peak memory | 603904 kb |
| Host | smart-74b18cc9-2863-44c2-9a90-4d00484b8951 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478769674 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.3478769674 |
| Directory | /workspace/1.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.1124115105 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 2093699896 ps |
| CPU time | 253.57 seconds |
| Started | May 30 04:25:01 PM PDT 24 |
| Finished | May 30 04:29:16 PM PDT 24 |
| Peak memory | 603108 kb |
| Host | smart-f13d73a6-0070-4515-a6e9-520bd98a3bb5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124115105 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_clkmgr_smoketest.1124115105 |
| Directory | /workspace/1.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.2175941980 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 10984119240 ps |
| CPU time | 3555.54 seconds |
| Started | May 30 04:22:49 PM PDT 24 |
| Finished | May 30 05:22:06 PM PDT 24 |
| Peak memory | 604076 kb |
| Host | smart-1d7436dc-8207-4c45-9415-c49367c3fff6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175941980 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency.2175941980 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.584475966 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 4319377598 ps |
| CPU time | 475.47 seconds |
| Started | May 30 04:19:36 PM PDT 24 |
| Finished | May 30 04:27:33 PM PDT 24 |
| Peak memory | 604356 kb |
| Host | smart-5fde27dd-2b4b-4c0a-838b-ddf443abb545 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58447 5966 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.584475966 |
| Directory | /workspace/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_kat_test.3080997656 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 2636893182 ps |
| CPU time | 290.24 seconds |
| Started | May 30 04:18:31 PM PDT 24 |
| Finished | May 30 04:23:23 PM PDT 24 |
| Peak memory | 603844 kb |
| Host | smart-6b3554f8-fde7-4fda-bf41-dae4ad347180 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080997656 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_kat_test.3080997656 |
| Directory | /workspace/1.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1980227948 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 7184456284 ps |
| CPU time | 524.53 seconds |
| Started | May 30 04:19:03 PM PDT 24 |
| Finished | May 30 04:27:48 PM PDT 24 |
| Peak memory | 605656 kb |
| Host | smart-80ec3118-d884-45ef-a964-1225e8c93886 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980227948 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csr ng_lc_hw_debug_en_test.1980227948 |
| Directory | /workspace/1.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_smoketest.2916961338 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 2349152160 ps |
| CPU time | 206.87 seconds |
| Started | May 30 04:23:07 PM PDT 24 |
| Finished | May 30 04:26:35 PM PDT 24 |
| Peak memory | 603416 kb |
| Host | smart-3073baca-4504-4a15-a64e-ebe5c80145d1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916961338 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_csrng_smoketest.2916961338 |
| Directory | /workspace/1.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_data_integrity_escalation.2992562236 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 5872116308 ps |
| CPU time | 777.06 seconds |
| Started | May 30 04:13:03 PM PDT 24 |
| Finished | May 30 04:26:02 PM PDT 24 |
| Peak memory | 605476 kb |
| Host | smart-a9e89148-1c7c-4fe3-aaa3-747b25b2cbbd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2992562236 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.2992562236 |
| Directory | /workspace/1.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_auto_mode.1257077781 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 3281884384 ps |
| CPU time | 763.82 seconds |
| Started | May 30 04:18:46 PM PDT 24 |
| Finished | May 30 04:31:31 PM PDT 24 |
| Peak memory | 603944 kb |
| Host | smart-ef418cff-cb1f-4976-bf14-b5b82615e242 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257077781 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ auto_mode.1257077781 |
| Directory | /workspace/1.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_boot_mode.1683633139 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 3154865064 ps |
| CPU time | 468.93 seconds |
| Started | May 30 04:17:33 PM PDT 24 |
| Finished | May 30 04:25:22 PM PDT 24 |
| Peak memory | 604040 kb |
| Host | smart-aba0022f-4cb3-4e58-9023-29bd4ebb640c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683633139 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ boot_mode.1683633139 |
| Directory | /workspace/1.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3569676372 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 7068839766 ps |
| CPU time | 1259.13 seconds |
| Started | May 30 04:19:55 PM PDT 24 |
| Finished | May 30 04:40:55 PM PDT 24 |
| Peak memory | 604264 kb |
| Host | smart-2abcf3ab-8670-42be-aafb-3ea09213f9a8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569676372 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.3569676372 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_kat.3389361761 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 3501774382 ps |
| CPU time | 557.57 seconds |
| Started | May 30 04:17:38 PM PDT 24 |
| Finished | May 30 04:26:57 PM PDT 24 |
| Peak memory | 610156 kb |
| Host | smart-d67403ba-922d-4e88-8999-190fdb623ff9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_imag es=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389361761 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_edn_kat.3389361761 |
| Directory | /workspace/1.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_sw_mode.1264548039 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 6686377288 ps |
| CPU time | 1452.95 seconds |
| Started | May 30 04:18:41 PM PDT 24 |
| Finished | May 30 04:42:55 PM PDT 24 |
| Peak memory | 604020 kb |
| Host | smart-71b25e61-a6dc-4a80-b460-9c0725449eb7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264548039 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_sw_mode.1264548039 |
| Directory | /workspace/1.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.2974881583 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 2560699336 ps |
| CPU time | 245.86 seconds |
| Started | May 30 04:19:15 PM PDT 24 |
| Finished | May 30 04:23:21 PM PDT 24 |
| Peak memory | 603500 kb |
| Host | smart-db6ba8e2-75be-4523-b778-f5fc001331b4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29 74881583 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.2974881583 |
| Directory | /workspace/1.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_csrng.1031511850 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 6968719120 ps |
| CPU time | 1956.4 seconds |
| Started | May 30 04:18:58 PM PDT 24 |
| Finished | May 30 04:51:36 PM PDT 24 |
| Peak memory | 604200 kb |
| Host | smart-8e150258-228b-4beb-bdcc-c2fea98c8ef4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1031511850 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.1031511850 |
| Directory | /workspace/1.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.1977222118 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 2384424616 ps |
| CPU time | 199.89 seconds |
| Started | May 30 04:19:21 PM PDT 24 |
| Finished | May 30 04:22:42 PM PDT 24 |
| Peak memory | 603536 kb |
| Host | smart-385e3ae9-f266-439c-812a-7318d51d549a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977222118 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.1977222118 |
| Directory | /workspace/1.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.2816666914 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 3195139800 ps |
| CPU time | 652.64 seconds |
| Started | May 30 04:23:04 PM PDT 24 |
| Finished | May 30 04:33:58 PM PDT 24 |
| Peak memory | 603116 kb |
| Host | smart-e8bf2759-b5fc-4498-9886-aa48196a1a76 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2816666914 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.2816666914 |
| Directory | /workspace/1.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_concurrency.2030111281 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 2788423040 ps |
| CPU time | 248.15 seconds |
| Started | May 30 04:14:01 PM PDT 24 |
| Finished | May 30 04:18:11 PM PDT 24 |
| Peak memory | 603468 kb |
| Host | smart-006b9b44-e5ac-4bc1-9770-892bee1e793e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030111281 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_example_concurrency.2030111281 |
| Directory | /workspace/1.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_flash.1422285500 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 2591222320 ps |
| CPU time | 182.03 seconds |
| Started | May 30 04:16:02 PM PDT 24 |
| Finished | May 30 04:19:05 PM PDT 24 |
| Peak memory | 603372 kb |
| Host | smart-88b5a9d1-4d69-4c45-aaba-47183ee982ca |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422285500 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_flash.1422285500 |
| Directory | /workspace/1.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_manufacturer.435457066 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 3196911658 ps |
| CPU time | 328.74 seconds |
| Started | May 30 04:16:26 PM PDT 24 |
| Finished | May 30 04:21:56 PM PDT 24 |
| Peak memory | 603188 kb |
| Host | smart-8a1827df-5297-4d55-889c-82ede60c11d8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435457066 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 1.chip_sw_example_manufacturer.435457066 |
| Directory | /workspace/1.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_rom.4175626018 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 3159643336 ps |
| CPU time | 135.94 seconds |
| Started | May 30 04:13:19 PM PDT 24 |
| Finished | May 30 04:15:36 PM PDT 24 |
| Peak memory | 604136 kb |
| Host | smart-d9fc1b14-9bdb-44bc-8ec9-796546a751bc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175626018 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_rom.4175626018 |
| Directory | /workspace/1.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.2404778104 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 58848057304 ps |
| CPU time | 10958.6 seconds |
| Started | May 30 04:14:05 PM PDT 24 |
| Finished | May 30 07:16:46 PM PDT 24 |
| Peak memory | 619520 kb |
| Host | smart-9f854015-dbf9-481d-8316-8a8037fbd802 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=2404778104 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_exit_test_unlocked_bootstrap.2404778104 |
| Directory | /workspace/1.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_crash_alert.3714073232 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 5443029064 ps |
| CPU time | 569.73 seconds |
| Started | May 30 04:20:39 PM PDT 24 |
| Finished | May 30 04:30:10 PM PDT 24 |
| Peak memory | 605612 kb |
| Host | smart-6deac1b3-c6c9-4548-8879-bacb828d8cdc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=3714073232 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.3714073232 |
| Directory | /workspace/1.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access.2385659637 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 5276208110 ps |
| CPU time | 1110.79 seconds |
| Started | May 30 04:18:19 PM PDT 24 |
| Finished | May 30 04:36:50 PM PDT 24 |
| Peak memory | 603536 kb |
| Host | smart-1195a2ff-42d9-4d45-be08-2114831a48f7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385659637 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_flash_ctrl_access.2385659637 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1813139202 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 5219446411 ps |
| CPU time | 1119.87 seconds |
| Started | May 30 04:15:59 PM PDT 24 |
| Finished | May 30 04:34:40 PM PDT 24 |
| Peak memory | 603988 kb |
| Host | smart-e5e1f3f6-ba76-4299-af54-39aa209bced0 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813139202 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en.1813139202 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2875678744 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 7772908762 ps |
| CPU time | 1029.8 seconds |
| Started | May 30 04:22:48 PM PDT 24 |
| Finished | May 30 04:39:59 PM PDT 24 |
| Peak memory | 603876 kb |
| Host | smart-27eff002-1a1c-4a29-8b78-2a4439ebfd00 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875678744 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2875678744 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.878170983 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 5450572600 ps |
| CPU time | 951.99 seconds |
| Started | May 30 04:23:25 PM PDT 24 |
| Finished | May 30 04:39:18 PM PDT 24 |
| Peak memory | 603872 kb |
| Host | smart-1fd31f24-6dfe-4d8e-b8ec-98cf64d64e6d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878170983 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_flash_ctrl_clock_freqs.878170983 |
| Directory | /workspace/1.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.3570538491 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 3634886732 ps |
| CPU time | 463.97 seconds |
| Started | May 30 04:16:41 PM PDT 24 |
| Finished | May 30 04:24:26 PM PDT 24 |
| Peak memory | 603216 kb |
| Host | smart-430768e4-7de8-4627-8a72-1d8c8cc6b4f3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570538491 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_idle_low_power.3570538491 |
| Directory | /workspace/1.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.2043529421 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 5329085920 ps |
| CPU time | 1029.45 seconds |
| Started | May 30 04:21:14 PM PDT 24 |
| Finished | May 30 04:38:24 PM PDT 24 |
| Peak memory | 603896 kb |
| Host | smart-b4401592-976e-4c28-9247-db32169216ff |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043529421 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_mem_protection.2043529421 |
| Directory | /workspace/1.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.415396433 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 3960250240 ps |
| CPU time | 672 seconds |
| Started | May 30 04:16:15 PM PDT 24 |
| Finished | May 30 04:27:28 PM PDT 24 |
| Peak memory | 603792 kb |
| Host | smart-dff25d05-96a4-4aef-aff0-6e0450fb7c76 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415396433 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.415396433 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3187677795 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 4352837695 ps |
| CPU time | 723.45 seconds |
| Started | May 30 04:16:50 PM PDT 24 |
| Finished | May 30 04:28:55 PM PDT 24 |
| Peak memory | 603960 kb |
| Host | smart-3161abf3-c8f1-4022-9485-40b478a4a63b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3187677795 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.3187677795 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2038297436 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 5068925724 ps |
| CPU time | 745.64 seconds |
| Started | May 30 04:21:51 PM PDT 24 |
| Finished | May 30 04:34:17 PM PDT 24 |
| Peak memory | 604024 kb |
| Host | smart-01d03aca-6321-407f-8fcd-6615db3018d1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=2038297436 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2038297436 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.4037986699 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 2693898528 ps |
| CPU time | 353.93 seconds |
| Started | May 30 04:21:13 PM PDT 24 |
| Finished | May 30 04:27:09 PM PDT 24 |
| Peak memory | 603156 kb |
| Host | smart-8e52a80e-daa9-4f80-bdd2-f1134a2d183f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037986 699 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_write_clear.4037986699 |
| Directory | /workspace/1.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init.1366695575 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 19739000584 ps |
| CPU time | 2229.1 seconds |
| Started | May 30 04:15:32 PM PDT 24 |
| Finished | May 30 04:52:43 PM PDT 24 |
| Peak memory | 608756 kb |
| Host | smart-1f517fee-34fc-4282-99b8-073e0eff0717 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366695575 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init.1366695575 |
| Directory | /workspace/1.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.792466464 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 20177848027 ps |
| CPU time | 2124.28 seconds |
| Started | May 30 04:20:38 PM PDT 24 |
| Finished | May 30 04:56:04 PM PDT 24 |
| Peak memory | 609084 kb |
| Host | smart-d698fd13-d684-4acc-80e1-2c10ad79fce8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=792466464 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.792466464 |
| Directory | /workspace/1.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.504576008 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 2070120632 ps |
| CPU time | 176.44 seconds |
| Started | May 30 04:26:50 PM PDT 24 |
| Finished | May 30 04:29:47 PM PDT 24 |
| Peak memory | 603476 kb |
| Host | smart-45ce1d4f-af05-4b27-9244-a30e4c123dcf |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=504576008 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.504576008 |
| Directory | /workspace/1.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc.295755822 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 2608350248 ps |
| CPU time | 299.19 seconds |
| Started | May 30 04:19:53 PM PDT 24 |
| Finished | May 30 04:24:54 PM PDT 24 |
| Peak memory | 603460 kb |
| Host | smart-4d184726-9037-4721-bb14-ae2a5a41c884 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295755822 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc.295755822 |
| Directory | /workspace/1.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_idle.1765745054 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 2633020580 ps |
| CPU time | 327.44 seconds |
| Started | May 30 04:20:07 PM PDT 24 |
| Finished | May 30 04:25:35 PM PDT 24 |
| Peak memory | 603488 kb |
| Host | smart-0fceb4b7-5338-49b3-a4a3-1f37608a408d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765745054 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_hmac_enc_idle.1765745054 |
| Directory | /workspace/1.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.3933536175 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 2496830629 ps |
| CPU time | 302 seconds |
| Started | May 30 04:23:44 PM PDT 24 |
| Finished | May 30 04:28:47 PM PDT 24 |
| Peak memory | 603528 kb |
| Host | smart-5d459e9e-499c-4d9a-975b-11ff6a017f17 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933536175 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en.3933536175 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1374858192 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 2707103296 ps |
| CPU time | 314.13 seconds |
| Started | May 30 04:22:01 PM PDT 24 |
| Finished | May 30 04:27:16 PM PDT 24 |
| Peak memory | 604252 kb |
| Host | smart-6614a734-115c-440f-8638-68f3a66a75fb |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374858192 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.1374858192 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_smoketest.756958077 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 2696924136 ps |
| CPU time | 444.56 seconds |
| Started | May 30 04:23:33 PM PDT 24 |
| Finished | May 30 04:30:58 PM PDT 24 |
| Peak memory | 603412 kb |
| Host | smart-5ded581f-39b7-48c1-a052-acb2e37b9a40 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756958077 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_smoketest.756958077 |
| Directory | /workspace/1.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.888827912 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 4474509812 ps |
| CPU time | 555.09 seconds |
| Started | May 30 04:12:57 PM PDT 24 |
| Finished | May 30 04:22:14 PM PDT 24 |
| Peak memory | 604536 kb |
| Host | smart-1b62dffc-c8de-4fb3-95c1-fe022fc1f8f3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888827912 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.888827912 |
| Directory | /workspace/1.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.416468770 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 4570935264 ps |
| CPU time | 763.34 seconds |
| Started | May 30 04:16:10 PM PDT 24 |
| Finished | May 30 04:28:55 PM PDT 24 |
| Peak memory | 604048 kb |
| Host | smart-60acd58a-65f9-43fd-a501-95fe25fe7c69 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416468770 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx.416468770 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.645414080 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 4441318992 ps |
| CPU time | 664.21 seconds |
| Started | May 30 04:17:15 PM PDT 24 |
| Finished | May 30 04:28:20 PM PDT 24 |
| Peak memory | 603864 kb |
| Host | smart-0b6c69d5-e025-48a6-82b7-cfb93794d6fd |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645414080 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.645414080 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.872952989 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 4575453586 ps |
| CPU time | 846.59 seconds |
| Started | May 30 04:15:32 PM PDT 24 |
| Finished | May 30 04:29:40 PM PDT 24 |
| Peak memory | 604020 kb |
| Host | smart-7d0845c2-d0a6-4992-a194-fc641ad5979d |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872952989 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.872952989 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_inject_scramble_seed.1134663641 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 65396092240 ps |
| CPU time | 11881.1 seconds |
| Started | May 30 04:13:53 PM PDT 24 |
| Finished | May 30 07:31:57 PM PDT 24 |
| Peak memory | 622564 kb |
| Host | smart-7ad5500c-5ea2-44d1-a4e9-3ca51c0bdf87 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1134663641 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.1134663641 |
| Directory | /workspace/1.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.2936215734 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 11675922384 ps |
| CPU time | 2190.46 seconds |
| Started | May 30 04:20:03 PM PDT 24 |
| Finished | May 30 04:56:34 PM PDT 24 |
| Peak memory | 611180 kb |
| Host | smart-3180d611-fc33-4939-9a56-01d92956ed51 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936 215734 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation.2936215734 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.2666828206 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 6914330751 ps |
| CPU time | 1331.65 seconds |
| Started | May 30 04:17:50 PM PDT 24 |
| Finished | May 30 04:40:02 PM PDT 24 |
| Peak memory | 611264 kb |
| Host | smart-924a7ab8-db3f-4717-80c6-508d8737fbad |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2666828206 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en.2666828206 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2535526758 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 12456052001 ps |
| CPU time | 1687.6 seconds |
| Started | May 30 04:23:04 PM PDT 24 |
| Finished | May 30 04:51:12 PM PDT 24 |
| Peak memory | 611188 kb |
| Host | smart-19850186-e3c9-4546-9ea0-6fb865b8deca |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2535526758 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.2535526758 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.2114767743 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 8811357920 ps |
| CPU time | 1385.24 seconds |
| Started | May 30 04:18:31 PM PDT 24 |
| Finished | May 30 04:41:37 PM PDT 24 |
| Peak memory | 611196 kb |
| Host | smart-b2a481b9-c700-41cf-8632-d1ded16ce799 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2114767743 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.2114767743 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.2056135224 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 9603171240 ps |
| CPU time | 1906.74 seconds |
| Started | May 30 04:23:14 PM PDT 24 |
| Finished | May 30 04:55:01 PM PDT 24 |
| Peak memory | 604580 kb |
| Host | smart-c89aa3b7-24a3-4cc9-8939-407b6e6433d4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20561 35224 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.2056135224 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_app_rom.989292156 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 3068673864 ps |
| CPU time | 206.12 seconds |
| Started | May 30 04:18:18 PM PDT 24 |
| Finished | May 30 04:21:45 PM PDT 24 |
| Peak memory | 603320 kb |
| Host | smart-8108a2f9-5438-4a81-85a9-ef8f42365df8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989292156 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_kmac_app_rom.989292156 |
| Directory | /workspace/1.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_entropy.3257421083 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 3331752958 ps |
| CPU time | 272.71 seconds |
| Started | May 30 04:14:45 PM PDT 24 |
| Finished | May 30 04:19:19 PM PDT 24 |
| Peak memory | 603540 kb |
| Host | smart-a547918f-91c8-418b-9cc2-e596a292dfe0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257421083 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_entropy.3257421083 |
| Directory | /workspace/1.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_idle.1271928547 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 2788759672 ps |
| CPU time | 211.48 seconds |
| Started | May 30 04:20:43 PM PDT 24 |
| Finished | May 30 04:24:15 PM PDT 24 |
| Peak memory | 603476 kb |
| Host | smart-27ab30b5-59bd-4c9c-83ca-e0c3dd7a1e4f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271928547 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_idle.1271928547 |
| Directory | /workspace/1.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.880227720 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 2227871912 ps |
| CPU time | 171.3 seconds |
| Started | May 30 04:17:52 PM PDT 24 |
| Finished | May 30 04:20:44 PM PDT 24 |
| Peak memory | 603732 kb |
| Host | smart-514ecf87-8ede-4702-8542-3688250e6e93 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880227720 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_kmac_mode_cshake.880227720 |
| Directory | /workspace/1.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.1756664403 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 3280965484 ps |
| CPU time | 242.3 seconds |
| Started | May 30 04:19:59 PM PDT 24 |
| Finished | May 30 04:24:02 PM PDT 24 |
| Peak memory | 603392 kb |
| Host | smart-cda1ac78-4fcf-4e9a-afa6-2361c3453b30 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756664403 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_kmac_mode_kmac.1756664403 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.45899245 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 2475399965 ps |
| CPU time | 335.71 seconds |
| Started | May 30 04:18:33 PM PDT 24 |
| Finished | May 30 04:24:11 PM PDT 24 |
| Peak memory | 603532 kb |
| Host | smart-5854760b-8250-4de5-b800-bea9271e76b7 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45899245 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.45899245 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3605393053 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 3649693352 ps |
| CPU time | 328.86 seconds |
| Started | May 30 04:24:07 PM PDT 24 |
| Finished | May 30 04:29:37 PM PDT 24 |
| Peak memory | 603440 kb |
| Host | smart-7119691a-8f4d-43fc-9f5c-c6235b1aa0e0 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36053930 53 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3605393053 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_smoketest.4048785953 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 3203664652 ps |
| CPU time | 265.66 seconds |
| Started | May 30 04:24:11 PM PDT 24 |
| Finished | May 30 04:28:37 PM PDT 24 |
| Peak memory | 603504 kb |
| Host | smart-d42bfcd8-2d79-49e1-8aac-a797e8336702 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048785953 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_smoketest.4048785953 |
| Directory | /workspace/1.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.3889231818 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 2557677454 ps |
| CPU time | 264.7 seconds |
| Started | May 30 04:18:50 PM PDT 24 |
| Finished | May 30 04:23:17 PM PDT 24 |
| Peak memory | 603220 kb |
| Host | smart-0797d14c-1dd4-4414-af96-cdd15c2c212d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889231818 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg0.3889231818 |
| Directory | /workspace/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.2220788699 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 2810471250 ps |
| CPU time | 237.36 seconds |
| Started | May 30 04:15:16 PM PDT 24 |
| Finished | May 30 04:19:14 PM PDT 24 |
| Peak memory | 615500 kb |
| Host | smart-7932426c-1949-4334-9995-45689b586e0c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22207886 99 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_rand_to_scrap.2220788699 |
| Directory | /workspace/1.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.572945618 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 7549861293 ps |
| CPU time | 398.09 seconds |
| Started | May 30 04:14:22 PM PDT 24 |
| Finished | May 30 04:21:01 PM PDT 24 |
| Peak memory | 615680 kb |
| Host | smart-53b8b7cd-68bf-4137-be3f-abd0fb910872 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572945618 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_transition.572945618 |
| Directory | /workspace/1.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.431176235 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 1940297397 ps |
| CPU time | 122.62 seconds |
| Started | May 30 04:16:30 PM PDT 24 |
| Finished | May 30 04:18:33 PM PDT 24 |
| Peak memory | 611288 kb |
| Host | smart-7644877e-4019-4b3a-b54d-b03009351fa1 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=431176235 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.431176235 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2344005037 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1893309291 ps |
| CPU time | 110.65 seconds |
| Started | May 30 04:16:00 PM PDT 24 |
| Finished | May 30 04:17:52 PM PDT 24 |
| Peak memory | 610472 kb |
| Host | smart-71212a04-a73d-4ab6-85f8-48751d32a077 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344005037 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2344005037 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.2918143271 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 8432687908 ps |
| CPU time | 1066.78 seconds |
| Started | May 30 04:16:47 PM PDT 24 |
| Finished | May 30 04:34:35 PM PDT 24 |
| Peak memory | 611144 kb |
| Host | smart-2e5aa33c-610f-4283-a3f1-bc5ec0187628 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918143271 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.2918143271 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1752786514 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 47036218453 ps |
| CPU time | 5047.65 seconds |
| Started | May 30 04:19:39 PM PDT 24 |
| Finished | May 30 05:43:50 PM PDT 24 |
| Peak memory | 612336 kb |
| Host | smart-334c6f73-9ed0-45d1-a010-c393317c549d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752786514 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_rma.1752786514 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.3932847735 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 32472832520 ps |
| CPU time | 2155.65 seconds |
| Started | May 30 04:16:36 PM PDT 24 |
| Finished | May 30 04:52:32 PM PDT 24 |
| Peak memory | 611108 kb |
| Host | smart-3e998db5-5762-4d38-9f08-d7847f91ee11 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3932847735 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testun locks.3932847735 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.561250636 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 16602814246 ps |
| CPU time | 3233.46 seconds |
| Started | May 30 04:16:59 PM PDT 24 |
| Finished | May 30 05:10:53 PM PDT 24 |
| Peak memory | 603876 kb |
| Host | smart-6b6f43ec-ef2b-45ae-9907-337efcb3c3fd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=561250636 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.561250636 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.3939569002 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 19718442692 ps |
| CPU time | 3537.53 seconds |
| Started | May 30 04:17:50 PM PDT 24 |
| Finished | May 30 05:16:49 PM PDT 24 |
| Peak memory | 604356 kb |
| Host | smart-9a5c67fd-51d3-48d1-87cd-2e0258abf89e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3939569002 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.3939569002 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3626979168 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 24842932768 ps |
| CPU time | 3460.29 seconds |
| Started | May 30 04:21:41 PM PDT 24 |
| Finished | May 30 05:19:23 PM PDT 24 |
| Peak memory | 603860 kb |
| Host | smart-b09285f8-9d1e-49f1-b7ec-3c001a0b2dd3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626979168 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.3626979168 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.2910673387 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 3139512716 ps |
| CPU time | 566.02 seconds |
| Started | May 30 04:18:48 PM PDT 24 |
| Finished | May 30 04:28:16 PM PDT 24 |
| Peak memory | 603532 kb |
| Host | smart-2e0b6aaf-bbcf-4406-9e5a-310091c67f9b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910673387 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.2910673387 |
| Directory | /workspace/1.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_randomness.340979656 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 5122059664 ps |
| CPU time | 1007.5 seconds |
| Started | May 30 04:18:06 PM PDT 24 |
| Finished | May 30 04:34:54 PM PDT 24 |
| Peak memory | 604196 kb |
| Host | smart-584c9734-fdb2-443f-ad9a-b3789660d600 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=340979656 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.340979656 |
| Directory | /workspace/1.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_smoketest.219600424 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 10845419898 ps |
| CPU time | 2182.38 seconds |
| Started | May 30 04:24:02 PM PDT 24 |
| Finished | May 30 05:00:27 PM PDT 24 |
| Peak memory | 603840 kb |
| Host | smart-da17b94d-48a1-459d-b15f-298a3e2fa237 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219600424 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_smoketest.219600424 |
| Directory | /workspace/1.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.3797273107 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 3489440302 ps |
| CPU time | 277.87 seconds |
| Started | May 30 04:15:14 PM PDT 24 |
| Finished | May 30 04:19:53 PM PDT 24 |
| Peak memory | 603996 kb |
| Host | smart-a2602092-ddb9-4392-8466-3052737cee88 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797273107 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_ecc_error_vendor_test.3797273107 |
| Directory | /workspace/1.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3254133138 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 9347235200 ps |
| CPU time | 1588.93 seconds |
| Started | May 30 04:14:19 PM PDT 24 |
| Finished | May 30 04:40:49 PM PDT 24 |
| Peak memory | 605136 kb |
| Host | smart-c279ebd9-2c84-4f31-8372-ddcd003dee50 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3254133138 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.3254133138 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.1902166596 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 9493881988 ps |
| CPU time | 1533.2 seconds |
| Started | May 30 04:16:26 PM PDT 24 |
| Finished | May 30 04:42:01 PM PDT 24 |
| Peak memory | 603880 kb |
| Host | smart-1676dd16-4fb8-4db2-88d1-ee96bbda6be7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1902166596 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.1902166596 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.1438131510 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 6885004944 ps |
| CPU time | 1384.51 seconds |
| Started | May 30 04:15:13 PM PDT 24 |
| Finished | May 30 04:38:18 PM PDT 24 |
| Peak memory | 604804 kb |
| Host | smart-9adf22dd-e9ee-4468-8d93-09b7d54deb58 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1438131510 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.1438131510 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2460661159 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 4380546930 ps |
| CPU time | 676.08 seconds |
| Started | May 30 04:15:28 PM PDT 24 |
| Finished | May 30 04:26:45 PM PDT 24 |
| Peak memory | 603948 kb |
| Host | smart-3b00b01e-6d5a-4b03-acb7-0eb16d583162 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=2460661159 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2460661159 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.1655524572 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 3024900056 ps |
| CPU time | 337.25 seconds |
| Started | May 30 04:24:23 PM PDT 24 |
| Finished | May 30 04:30:01 PM PDT 24 |
| Peak memory | 603484 kb |
| Host | smart-7c2056d9-87a9-4bf3-9cd0-26f64ea55134 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655524572 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_otp_ctrl_smoketest.1655524572 |
| Directory | /workspace/1.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_idle_load.2581438760 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 4800010200 ps |
| CPU time | 791.18 seconds |
| Started | May 30 04:22:30 PM PDT 24 |
| Finished | May 30 04:35:42 PM PDT 24 |
| Peak memory | 604064 kb |
| Host | smart-f45501df-d28d-4488-8dbc-fe095e86af2b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581438760 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_idle_load.2581438760 |
| Directory | /workspace/1.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_sleep_load.3832144845 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 10646650104 ps |
| CPU time | 508.66 seconds |
| Started | May 30 04:21:44 PM PDT 24 |
| Finished | May 30 04:30:14 PM PDT 24 |
| Peak memory | 604148 kb |
| Host | smart-b719f456-937b-4b0e-83b2-6274b08496cf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832144845 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_power_sleep_load.3832144845 |
| Directory | /workspace/1.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.200587390 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 13210346833 ps |
| CPU time | 2197.24 seconds |
| Started | May 30 04:17:04 PM PDT 24 |
| Finished | May 30 04:53:43 PM PDT 24 |
| Peak memory | 605892 kb |
| Host | smart-905265a6-9b55-4c33-9021-43c4db299857 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005 87390 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.200587390 |
| Directory | /workspace/1.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.2680606246 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 22988379368 ps |
| CPU time | 1949.84 seconds |
| Started | May 30 04:24:15 PM PDT 24 |
| Finished | May 30 04:56:46 PM PDT 24 |
| Peak memory | 604304 kb |
| Host | smart-46fbf1c4-a773-463f-aa76-a8071e0507ff |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268 0606246 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.2680606246 |
| Directory | /workspace/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2445862661 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 16663158149 ps |
| CPU time | 1382.28 seconds |
| Started | May 30 04:15:28 PM PDT 24 |
| Finished | May 30 04:38:32 PM PDT 24 |
| Peak memory | 605976 kb |
| Host | smart-78e72dfa-0b77-4edc-9c36-0d8d6508f18f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2445862661 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2445862661 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.586738981 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 23380660952 ps |
| CPU time | 1499.64 seconds |
| Started | May 30 04:21:15 PM PDT 24 |
| Finished | May 30 04:46:15 PM PDT 24 |
| Peak memory | 605504 kb |
| Host | smart-f321939a-87e5-4d56-9848-ae84a3edbce2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 586738981 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.586738981 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.2442317847 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 8920682492 ps |
| CPU time | 593.72 seconds |
| Started | May 30 04:19:58 PM PDT 24 |
| Finished | May 30 04:29:52 PM PDT 24 |
| Peak memory | 604352 kb |
| Host | smart-58a1de5d-c597-4e54-9f3c-2cfc965ccf1b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442317847 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_por_reset.2442317847 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.179045493 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 6269996930 ps |
| CPU time | 475.2 seconds |
| Started | May 30 04:15:38 PM PDT 24 |
| Finished | May 30 04:23:35 PM PDT 24 |
| Peak memory | 610680 kb |
| Host | smart-adceff58-5806-441a-be41-bae8b2764b0b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=179045493 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.179045493 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.2254715171 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 8602594640 ps |
| CPU time | 488.45 seconds |
| Started | May 30 04:19:55 PM PDT 24 |
| Finished | May 30 04:28:05 PM PDT 24 |
| Peak memory | 604248 kb |
| Host | smart-f628d497-6c4c-4d77-b998-60c8b62eae1c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254715171 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_full_aon_reset.2254715171 |
| Directory | /workspace/1.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.4231805134 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 4487657788 ps |
| CPU time | 308.63 seconds |
| Started | May 30 04:16:52 PM PDT 24 |
| Finished | May 30 04:22:02 PM PDT 24 |
| Peak memory | 610896 kb |
| Host | smart-79892019-1ebd-4c39-9bb3-118f0aee0ab3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=4231805134 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.4231805134 |
| Directory | /workspace/1.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3530278586 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 12455882839 ps |
| CPU time | 1305.7 seconds |
| Started | May 30 04:18:04 PM PDT 24 |
| Finished | May 30 04:39:51 PM PDT 24 |
| Peak memory | 605720 kb |
| Host | smart-60cdf2ab-f1a2-4690-ba23-340803c41861 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530278586 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3530278586 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3005460381 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 6755012126 ps |
| CPU time | 407.62 seconds |
| Started | May 30 04:20:12 PM PDT 24 |
| Finished | May 30 04:27:01 PM PDT 24 |
| Peak memory | 604448 kb |
| Host | smart-7465b565-af83-4d72-a23c-344ad6306fad |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005460381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3005460381 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.1798072574 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 6714856341 ps |
| CPU time | 552.18 seconds |
| Started | May 30 04:16:00 PM PDT 24 |
| Finished | May 30 04:25:13 PM PDT 24 |
| Peak memory | 604308 kb |
| Host | smart-a6da662e-cb5f-482e-a498-0933b6f56efb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798072574 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.1798072574 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1829646723 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 23555184868 ps |
| CPU time | 2251.83 seconds |
| Started | May 30 04:16:51 PM PDT 24 |
| Finished | May 30 04:54:25 PM PDT 24 |
| Peak memory | 606288 kb |
| Host | smart-ea39d8c0-d2e8-4d7c-ad5f-35b96c76dddd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829646723 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_s leep_power_glitch_reset.1829646723 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1557167031 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 5627812144 ps |
| CPU time | 357.5 seconds |
| Started | May 30 04:19:50 PM PDT 24 |
| Finished | May 30 04:25:49 PM PDT 24 |
| Peak memory | 605828 kb |
| Host | smart-428ecb21-5c64-4976-b8f4-327bf595dc87 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1557167031 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.1557167031 |
| Directory | /workspace/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.846562858 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 3481451144 ps |
| CPU time | 262.87 seconds |
| Started | May 30 04:16:38 PM PDT 24 |
| Finished | May 30 04:21:02 PM PDT 24 |
| Peak memory | 603552 kb |
| Host | smart-3c3f6967-1913-4405-8db5-91b6c3717927 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846562858 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_disabled.846562858 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.1990374034 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 4997520144 ps |
| CPU time | 517.66 seconds |
| Started | May 30 04:18:37 PM PDT 24 |
| Finished | May 30 04:27:15 PM PDT 24 |
| Peak memory | 610748 kb |
| Host | smart-a252340c-b3ff-4f81-acfa-893fcb4c38de |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1990374034 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_power_glitch_reset.1990374034 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1264128867 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 5663004200 ps |
| CPU time | 400.24 seconds |
| Started | May 30 04:18:50 PM PDT 24 |
| Finished | May 30 04:25:31 PM PDT 24 |
| Peak memory | 604124 kb |
| Host | smart-94eb5a3f-42f1-4f82-831e-bd5a4b1f9f79 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12641288 67 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1264128867 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.3577554198 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 5472994858 ps |
| CPU time | 581.24 seconds |
| Started | May 30 04:19:57 PM PDT 24 |
| Finished | May 30 04:29:39 PM PDT 24 |
| Peak memory | 605420 kb |
| Host | smart-926546cd-164d-4d36-94c5-6ad6c5ad8ea9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3577554198 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.3577554198 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.2805890585 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 5878145272 ps |
| CPU time | 456.31 seconds |
| Started | May 30 04:23:08 PM PDT 24 |
| Finished | May 30 04:30:45 PM PDT 24 |
| Peak memory | 604024 kb |
| Host | smart-09d73f84-01b9-40df-9ea0-2cfa82ab9e20 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805890585 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.2805890585 |
| Directory | /workspace/1.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.1807811875 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 6482889104 ps |
| CPU time | 977.3 seconds |
| Started | May 30 04:20:01 PM PDT 24 |
| Finished | May 30 04:36:19 PM PDT 24 |
| Peak memory | 604108 kb |
| Host | smart-aefcfb60-a0a1-4870-b69f-4a4fcfd822fd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807811875 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.1807811875 |
| Directory | /workspace/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.4218655129 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 5534040510 ps |
| CPU time | 458.35 seconds |
| Started | May 30 04:14:57 PM PDT 24 |
| Finished | May 30 04:22:36 PM PDT 24 |
| Peak memory | 603936 kb |
| Host | smart-e2fddb79-1f54-4cdb-81e6-73180e9d7fb5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218655129 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.4218655129 |
| Directory | /workspace/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.4122392739 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 4816596348 ps |
| CPU time | 476.33 seconds |
| Started | May 30 04:25:01 PM PDT 24 |
| Finished | May 30 04:32:58 PM PDT 24 |
| Peak memory | 603716 kb |
| Host | smart-65c3fd86-ccec-4fe5-a4e4-5ce64a1e0813 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122392739 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usbdev_smoketest.4122392739 |
| Directory | /workspace/1.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1898059062 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 5245335220 ps |
| CPU time | 684.16 seconds |
| Started | May 30 04:18:01 PM PDT 24 |
| Finished | May 30 04:29:26 PM PDT 24 |
| Peak memory | 604016 kb |
| Host | smart-4898b202-5db9-433c-b329-fe3e0057015a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189 8059062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.1898059062 |
| Directory | /workspace/1.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.698086294 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 8901204461 ps |
| CPU time | 496.86 seconds |
| Started | May 30 04:17:54 PM PDT 24 |
| Finished | May 30 04:26:12 PM PDT 24 |
| Peak memory | 604060 kb |
| Host | smart-4611b34a-47b7-4cc0-8563-f3ee4a674302 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698086294 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.698086294 |
| Directory | /workspace/1.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.2984025712 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 12254694320 ps |
| CPU time | 1477.7 seconds |
| Started | May 30 04:20:00 PM PDT 24 |
| Finished | May 30 04:44:39 PM PDT 24 |
| Peak memory | 605728 kb |
| Host | smart-ea1d2cc2-82ab-4ba8-8eb9-582fdd90c46c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=2984025712 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.2984025712 |
| Directory | /workspace/1.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.589314854 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 6443512360 ps |
| CPU time | 646.42 seconds |
| Started | May 30 04:15:02 PM PDT 24 |
| Finished | May 30 04:25:49 PM PDT 24 |
| Peak memory | 603984 kb |
| Host | smart-c599dd8c-607b-496c-b393-c3a610059540 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589314854 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_rstmgr_cpu_info.589314854 |
| Directory | /workspace/1.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2350372363 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 4414147576 ps |
| CPU time | 646.06 seconds |
| Started | May 30 04:15:11 PM PDT 24 |
| Finished | May 30 04:25:58 PM PDT 24 |
| Peak memory | 636448 kb |
| Host | smart-54161255-a529-49f5-951a-bd0b99a4ac2f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2350372363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.2350372363 |
| Directory | /workspace/1.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.1680352329 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 2563164992 ps |
| CPU time | 178.12 seconds |
| Started | May 30 04:25:31 PM PDT 24 |
| Finished | May 30 04:28:30 PM PDT 24 |
| Peak memory | 603160 kb |
| Host | smart-84df57e5-7b75-48f6-b5bf-ca24fe0376d4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680352329 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_rstmgr_smoketest.1680352329 |
| Directory | /workspace/1.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.1676637448 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 3228121380 ps |
| CPU time | 384.32 seconds |
| Started | May 30 04:19:14 PM PDT 24 |
| Finished | May 30 04:25:40 PM PDT 24 |
| Peak memory | 603392 kb |
| Host | smart-fd562ebe-9605-45f3-b181-4a036db0b62f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676637448 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rstmgr_sw_req.1676637448 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.285299863 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 3222839600 ps |
| CPU time | 264.48 seconds |
| Started | May 30 04:19:49 PM PDT 24 |
| Finished | May 30 04:24:14 PM PDT 24 |
| Peak memory | 603468 kb |
| Host | smart-828efc30-0ad8-41dc-a72d-a37adbb42184 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285299863 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_sw_rst.285299863 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.298223377 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 2591082136 ps |
| CPU time | 236.22 seconds |
| Started | May 30 04:20:46 PM PDT 24 |
| Finished | May 30 04:24:43 PM PDT 24 |
| Peak memory | 603504 kb |
| Host | smart-c8a51c22-b216-4656-8198-d27ffa38ef30 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=298223377 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.298223377 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.1130864574 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 2820800191 ps |
| CPU time | 297.72 seconds |
| Started | May 30 04:21:22 PM PDT 24 |
| Finished | May 30 04:26:22 PM PDT 24 |
| Peak memory | 603772 kb |
| Host | smart-420c82e3-e8e1-42b9-b19e-cf641dc73d3a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130864574 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.1130864574 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2653042929 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 4485954628 ps |
| CPU time | 986.24 seconds |
| Started | May 30 04:17:46 PM PDT 24 |
| Finished | May 30 04:34:14 PM PDT 24 |
| Peak memory | 603556 kb |
| Host | smart-ae787315-2fb1-4bbf-9fd1-373798427681 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26530 42929 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.2653042929 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.3154550050 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 5572427992 ps |
| CPU time | 899.28 seconds |
| Started | May 30 04:17:17 PM PDT 24 |
| Finished | May 30 04:32:17 PM PDT 24 |
| Peak memory | 603728 kb |
| Host | smart-4467fb2f-1fdc-433d-b3dd-5b6643335a90 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3154550050 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.3154550050 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.1475132256 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 4377446586 ps |
| CPU time | 395.98 seconds |
| Started | May 30 04:19:47 PM PDT 24 |
| Finished | May 30 04:26:24 PM PDT 24 |
| Peak memory | 611028 kb |
| Host | smart-02fc5901-40e2-4382-a90c-071a97a8c475 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475132256 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.1475132256 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1200310724 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 4448653256 ps |
| CPU time | 674.84 seconds |
| Started | May 30 04:19:53 PM PDT 24 |
| Finished | May 30 04:31:09 PM PDT 24 |
| Peak memory | 613128 kb |
| Host | smart-e7966cfc-b5fa-4555-a8f6-6069112896a5 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120031 0724 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1200310724 |
| Directory | /workspace/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.2174340583 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 2254887094 ps |
| CPU time | 221.45 seconds |
| Started | May 30 04:23:45 PM PDT 24 |
| Finished | May 30 04:27:27 PM PDT 24 |
| Peak memory | 603516 kb |
| Host | smart-71110801-1e33-4429-a836-109b7ad34d32 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174340583 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rv_plic_smoketest.2174340583 |
| Directory | /workspace/1.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_irq.3337382334 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 2878957000 ps |
| CPU time | 293.76 seconds |
| Started | May 30 04:16:57 PM PDT 24 |
| Finished | May 30 04:21:52 PM PDT 24 |
| Peak memory | 603384 kb |
| Host | smart-2de9abb4-3900-4f3e-ab2f-eca36e7c4da7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337382334 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_irq.3337382334 |
| Directory | /workspace/1.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.133672008 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 2545412792 ps |
| CPU time | 217.72 seconds |
| Started | May 30 04:22:34 PM PDT 24 |
| Finished | May 30 04:26:12 PM PDT 24 |
| Peak memory | 603736 kb |
| Host | smart-5b1393c4-876b-492f-bbb7-8be68516f341 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133672008 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rv_timer_smoketest.133672008 |
| Directory | /workspace/1.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1879930461 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 2849989393 ps |
| CPU time | 207.28 seconds |
| Started | May 30 04:19:52 PM PDT 24 |
| Finished | May 30 04:23:21 PM PDT 24 |
| Peak memory | 603852 kb |
| Host | smart-0fc8655b-c5a5-4f62-8ecc-1e768a3cd42e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879930 461 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.1879930461 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_retention.2102088838 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 2572246968 ps |
| CPU time | 263.05 seconds |
| Started | May 30 04:14:22 PM PDT 24 |
| Finished | May 30 04:18:45 PM PDT 24 |
| Peak memory | 603516 kb |
| Host | smart-d718026c-d993-4e51-995b-65d29712ccf7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102088838 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_retention.2102088838 |
| Directory | /workspace/1.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.1468050149 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 9249057064 ps |
| CPU time | 1480.44 seconds |
| Started | May 30 04:15:02 PM PDT 24 |
| Finished | May 30 04:39:43 PM PDT 24 |
| Peak memory | 604416 kb |
| Host | smart-5665a53c-9965-4884-932e-89547902929c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468050149 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_sleep_pwm_pulses.1468050149 |
| Directory | /workspace/1.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.1410417460 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 8276949880 ps |
| CPU time | 830.1 seconds |
| Started | May 30 04:19:27 PM PDT 24 |
| Finished | May 30 04:33:18 PM PDT 24 |
| Peak memory | 605372 kb |
| Host | smart-3aacaba7-6715-4c35-b59a-420a4f47101d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410417460 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sl eep_sram_ret_contents_no_scramble.1410417460 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.1193452882 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 7554541894 ps |
| CPU time | 660.68 seconds |
| Started | May 30 04:18:08 PM PDT 24 |
| Finished | May 30 04:29:09 PM PDT 24 |
| Peak memory | 605320 kb |
| Host | smart-fa23b5e9-a41c-4660-a0fc-4506b1d72984 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193452882 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep _sram_ret_contents_scramble.1193452882 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through.1038082180 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 6385609070 ps |
| CPU time | 787.72 seconds |
| Started | May 30 04:15:51 PM PDT 24 |
| Finished | May 30 04:29:00 PM PDT 24 |
| Peak memory | 622968 kb |
| Host | smart-88b4c6c8-eb17-44e0-9a8c-7587ec2da318 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038082180 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through.1038082180 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.285696106 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 3907059251 ps |
| CPU time | 529.7 seconds |
| Started | May 30 04:15:34 PM PDT 24 |
| Finished | May 30 04:24:24 PM PDT 24 |
| Peak memory | 621480 kb |
| Host | smart-06678388-0786-4b96-8cd2-d2f442d2c988 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285696106 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.285696106 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_tpm.1725304865 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 2579712806 ps |
| CPU time | 320.42 seconds |
| Started | May 30 04:16:45 PM PDT 24 |
| Finished | May 30 04:22:07 PM PDT 24 |
| Peak memory | 611152 kb |
| Host | smart-efc71d1e-3da7-4c3b-9dd6-f5397e84a4c6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725304865 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_tpm.1725304865 |
| Directory | /workspace/1.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3563012842 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 9972392588 ps |
| CPU time | 960.62 seconds |
| Started | May 30 04:19:54 PM PDT 24 |
| Finished | May 30 04:35:56 PM PDT 24 |
| Peak memory | 604196 kb |
| Host | smart-22fa9750-0902-4a5a-b887-1a155ad497f9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563012842 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.3563012842 |
| Directory | /workspace/1.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.1880265970 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 5177537868 ps |
| CPU time | 825.24 seconds |
| Started | May 30 04:18:14 PM PDT 24 |
| Finished | May 30 04:32:00 PM PDT 24 |
| Peak memory | 604568 kb |
| Host | smart-e2e26db7-53d7-43dd-a520-24cbd5a6c475 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880265970 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _sram_ctrl_scrambled_access.1880265970 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2879990865 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 5368028900 ps |
| CPU time | 588.89 seconds |
| Started | May 30 04:20:25 PM PDT 24 |
| Finished | May 30 04:30:14 PM PDT 24 |
| Peak memory | 604160 kb |
| Host | smart-570fbe16-7fcd-4a33-bac3-392426dee48d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879990865 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2879990865 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3572881678 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 5597974388 ps |
| CPU time | 769.64 seconds |
| Started | May 30 04:21:58 PM PDT 24 |
| Finished | May 30 04:34:49 PM PDT 24 |
| Peak memory | 604184 kb |
| Host | smart-1d05d491-043f-4485-8685-f888c9b2db80 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572881678 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3572881678 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.1864773012 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 3016902536 ps |
| CPU time | 195.36 seconds |
| Started | May 30 04:23:50 PM PDT 24 |
| Finished | May 30 04:27:06 PM PDT 24 |
| Peak memory | 603244 kb |
| Host | smart-f4fad51f-35a1-4983-9e5a-0f823495e02f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864773012 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_sram_ctrl_smoketest.1864773012 |
| Directory | /workspace/1.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.2764435111 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 20337836976 ps |
| CPU time | 3025.48 seconds |
| Started | May 30 04:14:59 PM PDT 24 |
| Finished | May 30 05:05:25 PM PDT 24 |
| Peak memory | 604256 kb |
| Host | smart-f6fcc4d6-6163-4557-b33d-7a76e418f967 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764435111 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.2764435111 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1729542865 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 4373993938 ps |
| CPU time | 524.18 seconds |
| Started | May 30 04:16:23 PM PDT 24 |
| Finished | May 30 04:25:09 PM PDT 24 |
| Peak memory | 607996 kb |
| Host | smart-cd8cd96d-2afb-4d3d-bbd9-e91059c28d61 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729542865 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_in_irq.1729542865 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3391176183 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 3171353049 ps |
| CPU time | 316 seconds |
| Started | May 30 04:17:17 PM PDT 24 |
| Finished | May 30 04:22:34 PM PDT 24 |
| Peak memory | 607988 kb |
| Host | smart-bbd95e4d-3c06-4dcd-8079-a3907b789a8c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391176183 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_inputs.3391176183 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.1704234135 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 21687205624 ps |
| CPU time | 2207.06 seconds |
| Started | May 30 04:16:12 PM PDT 24 |
| Finished | May 30 04:53:00 PM PDT 24 |
| Peak memory | 608596 kb |
| Host | smart-9b0fb2da-e561-4ad9-906c-be7688a3dd78 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17042341 35 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.1704234135 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1938352406 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 5320546668 ps |
| CPU time | 667.96 seconds |
| Started | May 30 04:20:51 PM PDT 24 |
| Finished | May 30 04:32:00 PM PDT 24 |
| Peak memory | 604340 kb |
| Host | smart-d0c0a6d0-96c0-41cc-8301-f734e41877a0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938352406 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1938352406 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2088584806 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 4493562138 ps |
| CPU time | 621.3 seconds |
| Started | May 30 04:13:55 PM PDT 24 |
| Finished | May 30 04:24:17 PM PDT 24 |
| Peak memory | 611976 kb |
| Host | smart-ba0197b5-9534-4bd2-a4ac-4b683ed22324 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2088584806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.2088584806 |
| Directory | /workspace/1.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_smoketest.929500852 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 2717524368 ps |
| CPU time | 325.71 seconds |
| Started | May 30 04:23:53 PM PDT 24 |
| Finished | May 30 04:29:20 PM PDT 24 |
| Peak memory | 603620 kb |
| Host | smart-a092d36f-d307-4d2e-a145-8b32b1ed5225 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929500852 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_uart_smoketest.929500852 |
| Directory | /workspace/1.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx.148683031 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 4314860660 ps |
| CPU time | 549.93 seconds |
| Started | May 30 04:13:41 PM PDT 24 |
| Finished | May 30 04:22:52 PM PDT 24 |
| Peak memory | 609948 kb |
| Host | smart-3dad74ca-3b6a-4948-87c3-a9760cecfda8 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148683031 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.148683031 |
| Directory | /workspace/1.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1372196139 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 7682603859 ps |
| CPU time | 1665.24 seconds |
| Started | May 30 04:15:11 PM PDT 24 |
| Finished | May 30 04:42:57 PM PDT 24 |
| Peak memory | 613064 kb |
| Host | smart-5823aacf-6840-4cad-8e95-b8d72df7bbd0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372196139 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq.1372196139 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3446773655 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 13213039930 ps |
| CPU time | 1886.55 seconds |
| Started | May 30 04:15:39 PM PDT 24 |
| Finished | May 30 04:47:08 PM PDT 24 |
| Peak memory | 612072 kb |
| Host | smart-74e84cd2-c2ee-4074-86d4-74b67e870933 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446773655 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.3446773655 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.4045562802 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 78127030536 ps |
| CPU time | 13440.9 seconds |
| Started | May 30 04:14:18 PM PDT 24 |
| Finished | May 30 07:58:22 PM PDT 24 |
| Peak memory | 631708 kb |
| Host | smart-3f0bc0d7-b033-45b1-9300-07e1c340935f |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=80_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4045562802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.4045562802 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.3273090887 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 4244392600 ps |
| CPU time | 574.28 seconds |
| Started | May 30 04:17:06 PM PDT 24 |
| Finished | May 30 04:26:42 PM PDT 24 |
| Peak memory | 609928 kb |
| Host | smart-a268e998-83fc-4de2-b27d-5b0884b0f69e |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273090887 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.3273090887 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.1237421444 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 4625771930 ps |
| CPU time | 697.44 seconds |
| Started | May 30 04:16:32 PM PDT 24 |
| Finished | May 30 04:28:10 PM PDT 24 |
| Peak memory | 609928 kb |
| Host | smart-24d378db-cb54-4082-9b37-0bb68865ca0d |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237421444 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.1237421444 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.2570832916 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 4038518228 ps |
| CPU time | 690.73 seconds |
| Started | May 30 04:15:35 PM PDT 24 |
| Finished | May 30 04:27:07 PM PDT 24 |
| Peak memory | 612228 kb |
| Host | smart-a29c0a22-762e-4c26-b8d1-1ee541af5bcb |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570832916 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.2570832916 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_dev.890228169 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 2174606877 ps |
| CPU time | 170.7 seconds |
| Started | May 30 04:20:46 PM PDT 24 |
| Finished | May 30 04:23:38 PM PDT 24 |
| Peak memory | 614212 kb |
| Host | smart-77b471ff-a14e-4a33-a60d-84f4839c7874 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=890228169 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.890228169 |
| Directory | /workspace/1.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_prod.3005328158 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 10299673148 ps |
| CPU time | 1038.89 seconds |
| Started | May 30 04:21:00 PM PDT 24 |
| Finished | May 30 04:38:19 PM PDT 24 |
| Peak memory | 618872 kb |
| Host | smart-70c76e2c-766d-4b0f-92ea-e50f48105b21 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005328158 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.3005328158 |
| Directory | /workspace/1.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_dev.3781875479 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 15055537762 ps |
| CPU time | 3446.54 seconds |
| Started | May 30 04:28:43 PM PDT 24 |
| Finished | May 30 05:26:11 PM PDT 24 |
| Peak memory | 605092 kb |
| Host | smart-320d4c2c-8242-4c4f-b1d6-4f759159caed |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781875479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_dev.3781875479 |
| Directory | /workspace/1.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod.2642140459 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 14695305203 ps |
| CPU time | 3064.69 seconds |
| Started | May 30 04:29:39 PM PDT 24 |
| Finished | May 30 05:20:45 PM PDT 24 |
| Peak memory | 605104 kb |
| Host | smart-834a2643-5f64-4f04-9153-f94a765ecfca |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642140459 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_prod.2642140459 |
| Directory | /workspace/1.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.1254205230 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 14191905928 ps |
| CPU time | 3747.07 seconds |
| Started | May 30 04:26:45 PM PDT 24 |
| Finished | May 30 05:29:13 PM PDT 24 |
| Peak memory | 605104 kb |
| Host | smart-b5949268-631a-47bd-a604-b89a4122684e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254205230 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.rom_e2e_asm_init_prod_end.1254205230 |
| Directory | /workspace/1.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_rma.1215549427 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 14002961675 ps |
| CPU time | 3090.81 seconds |
| Started | May 30 04:28:43 PM PDT 24 |
| Finished | May 30 05:20:15 PM PDT 24 |
| Peak memory | 605364 kb |
| Host | smart-2f5254b5-36d9-4f48-bfcd-25847bc5da87 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215549427 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_rma.1215549427 |
| Directory | /workspace/1.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.3170624704 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 10970190231 ps |
| CPU time | 2724.69 seconds |
| Started | May 30 04:28:52 PM PDT 24 |
| Finished | May 30 05:14:18 PM PDT 24 |
| Peak memory | 605372 kb |
| Host | smart-3403b874-6189-437e-8290-1c1980f89620 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170624704 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.rom_e2e_asm_init_test_unlocked0.3170624704 |
| Directory | /workspace/1.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.3444570886 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 14689283292 ps |
| CPU time | 4471.3 seconds |
| Started | May 30 04:27:29 PM PDT 24 |
| Finished | May 30 05:42:02 PM PDT 24 |
| Peak memory | 605376 kb |
| Host | smart-4860289a-4f68-40b5-9aca-89b5bd516a7a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444570886 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_in it_rom_ext_invalid_meas.3444570886 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.3248252172 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 15501678136 ps |
| CPU time | 3326.69 seconds |
| Started | May 30 04:27:46 PM PDT 24 |
| Finished | May 30 05:23:15 PM PDT 24 |
| Peak memory | 605264 kb |
| Host | smart-a66ec7ce-d8d5-4000-a982-b88de52af6d9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248252172 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_meas.3248252172 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.698596649 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 14473002200 ps |
| CPU time | 3344.03 seconds |
| Started | May 30 04:26:16 PM PDT 24 |
| Finished | May 30 05:22:01 PM PDT 24 |
| Peak memory | 605212 kb |
| Host | smart-34db83db-2211-408c-bbdc-585e4a1bf25a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698596649 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_ no_meas.698596649 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.3985034571 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 14019595092 ps |
| CPU time | 3512.14 seconds |
| Started | May 30 04:26:39 PM PDT 24 |
| Finished | May 30 05:25:13 PM PDT 24 |
| Peak memory | 605048 kb |
| Host | smart-411c51e3-62b6-4869-9000-5cca864b0595 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985034571 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_ shutdown_exception_c.3985034571 |
| Directory | /workspace/1.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_output.873471981 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 22153015426 ps |
| CPU time | 3154.98 seconds |
| Started | May 30 04:29:09 PM PDT 24 |
| Finished | May 30 05:21:45 PM PDT 24 |
| Peak memory | 605424 kb |
| Host | smart-ebb20115-13a8-4381-a43c-1ebf0fb964a3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873471981 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_output.873471981 |
| Directory | /workspace/1.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_smoke.2565238744 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 14017377656 ps |
| CPU time | 3589.33 seconds |
| Started | May 30 04:27:18 PM PDT 24 |
| Finished | May 30 05:27:10 PM PDT 24 |
| Peak memory | 605284 kb |
| Host | smart-db4dcbc8-7cff-4067-94f1-b1c502a58421 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=2565238744 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.2565238744 |
| Directory | /workspace/1.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/1.rom_keymgr_functest.263567251 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 4781169346 ps |
| CPU time | 665.9 seconds |
| Started | May 30 04:22:54 PM PDT 24 |
| Finished | May 30 04:34:01 PM PDT 24 |
| Peak memory | 605136 kb |
| Host | smart-9499a676-40eb-4acc-8c6b-e946d32a777a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263567251 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.rom_keymgr_functest.263567251 |
| Directory | /workspace/1.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/1.rom_volatile_raw_unlock.721569678 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 2233618133 ps |
| CPU time | 108.17 seconds |
| Started | May 30 04:23:06 PM PDT 24 |
| Finished | May 30 04:24:55 PM PDT 24 |
| Peak memory | 610576 kb |
| Host | smart-8ab975a5-056c-4af8-bd4c-a71e33e4bfc7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721569678 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.721569678 |
| Directory | /workspace/1.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/10.chip_sw_all_escalation_resets.1539133506 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 5138887196 ps |
| CPU time | 747.58 seconds |
| Started | May 30 04:36:53 PM PDT 24 |
| Finished | May 30 04:49:21 PM PDT 24 |
| Peak memory | 639432 kb |
| Host | smart-f024d8e0-eb61-4812-ad28-f051c7486517 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1539133506 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.1539133506 |
| Directory | /workspace/10.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.3412727720 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 10503703968 ps |
| CPU time | 613.39 seconds |
| Started | May 30 04:36:31 PM PDT 24 |
| Finished | May 30 04:46:45 PM PDT 24 |
| Peak memory | 615608 kb |
| Host | smart-e67b1ef1-e850-4e50-be49-9818a61748b4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412727720 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 10.chip_sw_lc_ctrl_transition.3412727720 |
| Directory | /workspace/10.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.3567796324 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 12695310920 ps |
| CPU time | 2097.16 seconds |
| Started | May 30 04:35:13 PM PDT 24 |
| Finished | May 30 05:10:11 PM PDT 24 |
| Peak memory | 612488 kb |
| Host | smart-b6b846b2-249f-4064-a630-8ed942ee7217 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3567796324 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.3567796324 |
| Directory | /workspace/10.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.2918614545 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 11443444580 ps |
| CPU time | 992.59 seconds |
| Started | May 30 04:34:40 PM PDT 24 |
| Finished | May 30 04:51:14 PM PDT 24 |
| Peak memory | 616256 kb |
| Host | smart-afb78ed3-3738-4e55-8005-a8e66b7820ea |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918614545 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 11.chip_sw_lc_ctrl_transition.2918614545 |
| Directory | /workspace/11.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.872509181 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 7725756760 ps |
| CPU time | 1507.34 seconds |
| Started | May 30 04:36:42 PM PDT 24 |
| Finished | May 30 05:01:51 PM PDT 24 |
| Peak memory | 611876 kb |
| Host | smart-dc9465bc-36f4-41b8-aa8e-86c703b9e883 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=872509181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.872509181 |
| Directory | /workspace/11.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.4070680372 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 10056850715 ps |
| CPU time | 925.9 seconds |
| Started | May 30 04:33:48 PM PDT 24 |
| Finished | May 30 04:49:14 PM PDT 24 |
| Peak memory | 616296 kb |
| Host | smart-a42ecee0-690c-4256-adb6-6bdbec1012b4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070680372 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 12.chip_sw_lc_ctrl_transition.4070680372 |
| Directory | /workspace/12.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.206666945 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 8105865912 ps |
| CPU time | 1444.17 seconds |
| Started | May 30 04:34:31 PM PDT 24 |
| Finished | May 30 04:58:37 PM PDT 24 |
| Peak memory | 612416 kb |
| Host | smart-39ffada7-12eb-4197-83f1-ba054cad459a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=206666945 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.206666945 |
| Directory | /workspace/12.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.2401165119 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 5758915191 ps |
| CPU time | 421.23 seconds |
| Started | May 30 04:35:01 PM PDT 24 |
| Finished | May 30 04:42:04 PM PDT 24 |
| Peak memory | 615656 kb |
| Host | smart-ac19aadb-e547-4d79-b0e3-4665f01ed098 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401165119 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 13.chip_sw_lc_ctrl_transition.2401165119 |
| Directory | /workspace/13.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.1810756692 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 12956044740 ps |
| CPU time | 2459.28 seconds |
| Started | May 30 04:34:58 PM PDT 24 |
| Finished | May 30 05:15:59 PM PDT 24 |
| Peak memory | 612500 kb |
| Host | smart-3d59fa82-09fe-4faa-884e-490e59be7d5a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1810756692 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.1810756692 |
| Directory | /workspace/13.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/14.chip_sw_all_escalation_resets.353782616 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 4278785220 ps |
| CPU time | 538.17 seconds |
| Started | May 30 04:34:36 PM PDT 24 |
| Finished | May 30 04:43:35 PM PDT 24 |
| Peak memory | 611272 kb |
| Host | smart-b6566392-73b8-4ec2-b95e-a8bfc50a2dd3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 353782616 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.353782616 |
| Directory | /workspace/14.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.3756666876 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 10942020681 ps |
| CPU time | 612.25 seconds |
| Started | May 30 04:34:53 PM PDT 24 |
| Finished | May 30 04:45:06 PM PDT 24 |
| Peak memory | 616244 kb |
| Host | smart-11ad1318-0c4e-49df-8f6e-5539c5ea9587 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756666876 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 14.chip_sw_lc_ctrl_transition.3756666876 |
| Directory | /workspace/14.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.3419128925 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 4045569176 ps |
| CPU time | 516.51 seconds |
| Started | May 30 04:35:41 PM PDT 24 |
| Finished | May 30 04:44:19 PM PDT 24 |
| Peak memory | 612600 kb |
| Host | smart-9b143f73-a9ec-4dfc-9ea8-93e80550dc4d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3419128925 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.3419128925 |
| Directory | /workspace/14.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.3655694854 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 4017765256 ps |
| CPU time | 314.45 seconds |
| Started | May 30 04:35:22 PM PDT 24 |
| Finished | May 30 04:40:38 PM PDT 24 |
| Peak memory | 639568 kb |
| Host | smart-2df0f256-9419-4612-acef-caaa06ea6b4c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655694854 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3655694854 |
| Directory | /workspace/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.3717332486 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 8958317376 ps |
| CPU time | 1288.51 seconds |
| Started | May 30 04:37:13 PM PDT 24 |
| Finished | May 30 04:58:43 PM PDT 24 |
| Peak memory | 610960 kb |
| Host | smart-0907baa1-110c-4ac7-a769-957617a69cea |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3717332486 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.3717332486 |
| Directory | /workspace/15.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.2962457500 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 3361091160 ps |
| CPU time | 376.86 seconds |
| Started | May 30 04:35:28 PM PDT 24 |
| Finished | May 30 04:41:46 PM PDT 24 |
| Peak memory | 640120 kb |
| Host | smart-ae58314e-8f98-4ad1-8234-14c2edcbbc7c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962457500 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2962457500 |
| Directory | /workspace/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/16.chip_sw_all_escalation_resets.3900555731 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 4391637530 ps |
| CPU time | 618.7 seconds |
| Started | May 30 04:39:39 PM PDT 24 |
| Finished | May 30 04:49:59 PM PDT 24 |
| Peak memory | 611348 kb |
| Host | smart-d4185b7a-e126-492c-806e-140b263071e3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3900555731 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.3900555731 |
| Directory | /workspace/16.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.2861124225 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 7958605352 ps |
| CPU time | 1281.69 seconds |
| Started | May 30 04:35:28 PM PDT 24 |
| Finished | May 30 04:56:51 PM PDT 24 |
| Peak memory | 612508 kb |
| Host | smart-e54d7f26-1243-4954-9414-e8aa3e66c0f8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2861124225 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.2861124225 |
| Directory | /workspace/16.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.2712973557 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 4438287494 ps |
| CPU time | 437.1 seconds |
| Started | May 30 04:35:25 PM PDT 24 |
| Finished | May 30 04:42:43 PM PDT 24 |
| Peak memory | 612636 kb |
| Host | smart-546a1577-0658-480a-8fc3-696b80d2f8dc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2712973557 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.2712973557 |
| Directory | /workspace/17.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/18.chip_sw_all_escalation_resets.1827342811 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 5680008248 ps |
| CPU time | 525.41 seconds |
| Started | May 30 04:37:01 PM PDT 24 |
| Finished | May 30 04:45:47 PM PDT 24 |
| Peak memory | 611304 kb |
| Host | smart-034910ad-5540-40a1-ad58-ca6c5aed2ff1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1827342811 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.1827342811 |
| Directory | /workspace/18.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.2948834187 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 8087626056 ps |
| CPU time | 1443.82 seconds |
| Started | May 30 04:35:03 PM PDT 24 |
| Finished | May 30 04:59:08 PM PDT 24 |
| Peak memory | 612452 kb |
| Host | smart-de2175fb-950d-49fc-85f3-754580c74af1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2948834187 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.2948834187 |
| Directory | /workspace/18.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.3823273945 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 3823315232 ps |
| CPU time | 770.25 seconds |
| Started | May 30 04:35:34 PM PDT 24 |
| Finished | May 30 04:48:26 PM PDT 24 |
| Peak memory | 610956 kb |
| Host | smart-828a81d6-bde9-4881-83a4-54a1f4881d0c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3823273945 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.3823273945 |
| Directory | /workspace/19.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_mem_access.3076127191 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 13578523221 ps |
| CPU time | 1625.54 seconds |
| Started | May 30 04:22:03 PM PDT 24 |
| Finished | May 30 04:49:10 PM PDT 24 |
| Peak memory | 606684 kb |
| Host | smart-1f28699d-44e7-4ea9-aaf4-f43c516424f2 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076127191 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.3 076127191 |
| Directory | /workspace/2.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.2111395779 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 3915419800 ps |
| CPU time | 362.74 seconds |
| Started | May 30 04:30:09 PM PDT 24 |
| Finished | May 30 04:36:13 PM PDT 24 |
| Peak memory | 613068 kb |
| Host | smart-2f7c5e8a-3d0e-40d0-8868-39f165c5d2ed |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2 111395779 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.2111395779 |
| Directory | /workspace/2.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sival_flash_info_access.3244138062 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 2526804770 ps |
| CPU time | 250.8 seconds |
| Started | May 30 04:23:14 PM PDT 24 |
| Finished | May 30 04:27:26 PM PDT 24 |
| Peak memory | 603612 kb |
| Host | smart-02c93603-1d2f-4473-9f08-963ac3fcf988 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3244138062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.3244138062 |
| Directory | /workspace/2.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1308039826 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 19321005480 ps |
| CPU time | 524.1 seconds |
| Started | May 30 04:28:53 PM PDT 24 |
| Finished | May 30 04:37:38 PM PDT 24 |
| Peak memory | 611064 kb |
| Host | smart-366adea8-0d80-465f-bc40-b7683d85cbbb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1308039826 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1308039826 |
| Directory | /workspace/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc.2064286769 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 2753228094 ps |
| CPU time | 205.49 seconds |
| Started | May 30 04:26:54 PM PDT 24 |
| Finished | May 30 04:30:21 PM PDT 24 |
| Peak memory | 603676 kb |
| Host | smart-3f953f2a-19ad-4671-9bb5-cae2663e27ce |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064286769 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.2064286769 |
| Directory | /workspace/2.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.1863104315 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 2357462778 ps |
| CPU time | 301.27 seconds |
| Started | May 30 04:28:06 PM PDT 24 |
| Finished | May 30 04:33:10 PM PDT 24 |
| Peak memory | 603656 kb |
| Host | smart-0261e537-dfe1-4fd3-b532-92d2e1d78f63 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863 104315 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.1863104315 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.2047014235 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 3242647823 ps |
| CPU time | 283.37 seconds |
| Started | May 30 04:31:03 PM PDT 24 |
| Finished | May 30 04:35:47 PM PDT 24 |
| Peak memory | 603744 kb |
| Host | smart-af661bde-2179-4fe4-a673-39ed67abf5d4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047014235 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.2047014235 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_entropy.4224819099 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 3463824088 ps |
| CPU time | 246.83 seconds |
| Started | May 30 04:27:39 PM PDT 24 |
| Finished | May 30 04:31:47 PM PDT 24 |
| Peak memory | 603868 kb |
| Host | smart-e02721f0-3123-44b8-a4d0-f2f80d280acc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224819099 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_entropy.4224819099 |
| Directory | /workspace/2.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_idle.2642635736 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 3128640494 ps |
| CPU time | 234.77 seconds |
| Started | May 30 04:27:57 PM PDT 24 |
| Finished | May 30 04:31:53 PM PDT 24 |
| Peak memory | 603900 kb |
| Host | smart-3053cf21-741e-41b3-8e33-281f63cdf000 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642635736 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.2642635736 |
| Directory | /workspace/2.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_masking_off.3555634034 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 2682753431 ps |
| CPU time | 259.93 seconds |
| Started | May 30 04:30:00 PM PDT 24 |
| Finished | May 30 04:34:21 PM PDT 24 |
| Peak memory | 603888 kb |
| Host | smart-aef8c1fb-fb27-4d03-950f-602e3b74cd87 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555634034 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_masking_off.3555634034 |
| Directory | /workspace/2.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_smoketest.1297101762 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 2886228140 ps |
| CPU time | 254.43 seconds |
| Started | May 30 04:33:14 PM PDT 24 |
| Finished | May 30 04:37:29 PM PDT 24 |
| Peak memory | 603404 kb |
| Host | smart-b842a580-823a-40d6-9e85-3793890130f5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297101762 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_smoketest.1297101762 |
| Directory | /workspace/2.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_entropy.2127133192 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 3151630482 ps |
| CPU time | 357.15 seconds |
| Started | May 30 04:29:44 PM PDT 24 |
| Finished | May 30 04:35:43 PM PDT 24 |
| Peak memory | 604420 kb |
| Host | smart-2315b449-d0fa-4d2e-8a11-17cbfe31b274 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2127133192 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.2127133192 |
| Directory | /workspace/2.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_escalation.2218822636 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 5190278084 ps |
| CPU time | 641.95 seconds |
| Started | May 30 04:27:00 PM PDT 24 |
| Finished | May 30 04:37:43 PM PDT 24 |
| Peak memory | 611012 kb |
| Host | smart-70d4c4f4-8c0f-46c0-b14c-9f78b2bdc5bb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=2218822636 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.2218822636 |
| Directory | /workspace/2.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.1122106568 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 5623835786 ps |
| CPU time | 1037.11 seconds |
| Started | May 30 04:28:09 PM PDT 24 |
| Finished | May 30 04:45:27 PM PDT 24 |
| Peak memory | 604932 kb |
| Host | smart-c938a0f4-3b83-486d-839d-5d124ed0c882 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1122106568 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.1122106568 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.2575995584 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 7148833328 ps |
| CPU time | 1864.19 seconds |
| Started | May 30 04:30:07 PM PDT 24 |
| Finished | May 30 05:01:12 PM PDT 24 |
| Peak memory | 604268 kb |
| Host | smart-28c01b1b-69b0-4d54-a9bb-86b5cff0beb2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575995584 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_togg le.2575995584 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.2342217697 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 4637604120 ps |
| CPU time | 484.6 seconds |
| Started | May 30 04:28:20 PM PDT 24 |
| Finished | May 30 04:36:25 PM PDT 24 |
| Peak memory | 603748 kb |
| Host | smart-14da3d5b-fb99-4314-98cf-5fa4a4d87c4c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2342217697 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.2342217697 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3248173347 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 256060604840 ps |
| CPU time | 12050.9 seconds |
| Started | May 30 04:27:24 PM PDT 24 |
| Finished | May 30 07:48:18 PM PDT 24 |
| Peak memory | 605180 kb |
| Host | smart-3638e732-0aba-412b-a812-169e2be63dbb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3248173347 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3248173347 |
| Directory | /workspace/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_test.4180922753 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 3236285994 ps |
| CPU time | 399.24 seconds |
| Started | May 30 04:30:34 PM PDT 24 |
| Finished | May 30 04:37:14 PM PDT 24 |
| Peak memory | 603552 kb |
| Host | smart-92d41b64-074f-49c3-b762-6d22b9b9e702 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180922753 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_alert_test.4180922753 |
| Directory | /workspace/2.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_irq.2330691885 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 4371413224 ps |
| CPU time | 424.08 seconds |
| Started | May 30 04:26:04 PM PDT 24 |
| Finished | May 30 04:33:09 PM PDT 24 |
| Peak memory | 604072 kb |
| Host | smart-485a5d36-d6e5-40d6-acdb-075adf5a46ee |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330691885 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.2330691885 |
| Directory | /workspace/2.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.819829596 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 7615944920 ps |
| CPU time | 337.97 seconds |
| Started | May 30 04:27:11 PM PDT 24 |
| Finished | May 30 04:32:50 PM PDT 24 |
| Peak memory | 603980 kb |
| Host | smart-464fee99-4bd4-4e89-9b4d-fc4287416c9d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=819829596 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.819829596 |
| Directory | /workspace/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.1918951195 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 2928000710 ps |
| CPU time | 315.11 seconds |
| Started | May 30 04:31:49 PM PDT 24 |
| Finished | May 30 04:37:05 PM PDT 24 |
| Peak memory | 603524 kb |
| Host | smart-f172294f-3035-4927-b309-ba96344f7cea |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918951195 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_aon_timer_smoketest.1918951195 |
| Directory | /workspace/2.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.794138551 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 7354150802 ps |
| CPU time | 732.12 seconds |
| Started | May 30 04:26:50 PM PDT 24 |
| Finished | May 30 04:39:03 PM PDT 24 |
| Peak memory | 604180 kb |
| Host | smart-5bbb7ca1-a57c-4672-b211-5645d9728bfc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 794138551 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.794138551 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.3658367878 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 5783693900 ps |
| CPU time | 842.78 seconds |
| Started | May 30 04:30:37 PM PDT 24 |
| Finished | May 30 04:44:40 PM PDT 24 |
| Peak memory | 604248 kb |
| Host | smart-147c533d-5825-4a6e-a90d-28a006120d59 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3658367878 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.3658367878 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_outputs.3831253883 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 7122218608 ps |
| CPU time | 925.34 seconds |
| Started | May 30 04:33:06 PM PDT 24 |
| Finished | May 30 04:48:32 PM PDT 24 |
| Peak memory | 610300 kb |
| Host | smart-2efaa2c5-1d00-4509-b848-0455d4b5c4e8 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831253883 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.3831253883 |
| Directory | /workspace/2.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.1886267292 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 21679041336 ps |
| CPU time | 2712.05 seconds |
| Started | May 30 04:30:30 PM PDT 24 |
| Finished | May 30 05:15:43 PM PDT 24 |
| Peak memory | 605508 kb |
| Host | smart-ab9e6a65-f7cb-4ad9-b3a0-35e9eb5cf2c2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886267292 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_rst_inputs.1886267292 |
| Directory | /workspace/2.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.3170152037 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 11640188113 ps |
| CPU time | 1243.72 seconds |
| Started | May 30 04:28:41 PM PDT 24 |
| Finished | May 30 04:49:27 PM PDT 24 |
| Peak memory | 615212 kb |
| Host | smart-0f9ca306-c3ee-43a1-bf7c-7f5507fe85f9 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=3170152037 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.3170152037 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.704985247 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 4008170452 ps |
| CPU time | 811.79 seconds |
| Started | May 30 04:30:23 PM PDT 24 |
| Finished | May 30 04:43:57 PM PDT 24 |
| Peak memory | 607804 kb |
| Host | smart-3bc2caab-ceca-45d3-9ed4-2a0b0715d0d3 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704985247 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_cl kmgr_external_clk_src_for_sw_fast_dev.704985247 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2408562772 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 4179605912 ps |
| CPU time | 616.2 seconds |
| Started | May 30 04:29:54 PM PDT 24 |
| Finished | May 30 04:40:11 PM PDT 24 |
| Peak memory | 607264 kb |
| Host | smart-88d34dc2-f732-4f7c-8264-cfd4c82a3403 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408562772 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.2408562772 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1397490299 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 3491173508 ps |
| CPU time | 645.72 seconds |
| Started | May 30 04:29:08 PM PDT 24 |
| Finished | May 30 04:39:54 PM PDT 24 |
| Peak memory | 607816 kb |
| Host | smart-07ccdb5c-4863-48eb-8559-f4be36d24c9f |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397490299 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1397490299 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3893807116 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 4055031828 ps |
| CPU time | 678.6 seconds |
| Started | May 30 04:30:37 PM PDT 24 |
| Finished | May 30 04:41:56 PM PDT 24 |
| Peak memory | 607792 kb |
| Host | smart-681d6879-2865-4d40-87f0-56631b0a8d0b |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893807116 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.3893807116 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.924910164 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 4526986056 ps |
| CPU time | 760.88 seconds |
| Started | May 30 04:29:06 PM PDT 24 |
| Finished | May 30 04:41:49 PM PDT 24 |
| Peak memory | 607200 kb |
| Host | smart-8b2d9288-8f7f-4f82-99af-6a47f1fe945e |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924910164 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_cl kmgr_external_clk_src_for_sw_slow_rma.924910164 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2538462628 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 4623446392 ps |
| CPU time | 595.83 seconds |
| Started | May 30 04:28:00 PM PDT 24 |
| Finished | May 30 04:37:57 PM PDT 24 |
| Peak memory | 607216 kb |
| Host | smart-2c74ed23-b782-4cca-bf30-08a004c050af |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538462628 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2538462628 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter.1236461876 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 2627289504 ps |
| CPU time | 203.42 seconds |
| Started | May 30 04:29:08 PM PDT 24 |
| Finished | May 30 04:32:32 PM PDT 24 |
| Peak memory | 603348 kb |
| Host | smart-132e810c-2c7c-4b4d-91f7-b06a1ee59c59 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236461876 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_clkmgr_jitter.1236461876 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.3575210068 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 2985098062 ps |
| CPU time | 516.27 seconds |
| Started | May 30 04:28:49 PM PDT 24 |
| Finished | May 30 04:37:26 PM PDT 24 |
| Peak memory | 603220 kb |
| Host | smart-6643d7e8-db00-46f4-87e4-83297c346e81 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575210068 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_frequency.3575210068 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.2280024731 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 2612716493 ps |
| CPU time | 263.95 seconds |
| Started | May 30 04:31:42 PM PDT 24 |
| Finished | May 30 04:36:07 PM PDT 24 |
| Peak memory | 603560 kb |
| Host | smart-d2c816d6-715f-494a-8343-4b6c9f6a35eb |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280024731 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.2280024731 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.1342762700 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 5168127672 ps |
| CPU time | 630.78 seconds |
| Started | May 30 04:28:28 PM PDT 24 |
| Finished | May 30 04:39:00 PM PDT 24 |
| Peak memory | 604940 kb |
| Host | smart-9d6edcef-f44d-4796-abab-6c88694dde01 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342762700 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.1342762700 |
| Directory | /workspace/2.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.3176673966 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 3807101140 ps |
| CPU time | 349.82 seconds |
| Started | May 30 04:29:20 PM PDT 24 |
| Finished | May 30 04:35:10 PM PDT 24 |
| Peak memory | 603312 kb |
| Host | smart-565b7b16-5e2d-4650-b2a2-0dda307bacdb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176673966 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_hmac_trans.3176673966 |
| Directory | /workspace/2.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.47802873 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 5183981962 ps |
| CPU time | 610.96 seconds |
| Started | May 30 04:28:27 PM PDT 24 |
| Finished | May 30 04:38:40 PM PDT 24 |
| Peak memory | 603640 kb |
| Host | smart-c7b23396-3d0c-4ae5-9ce2-736d9918468b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47802873 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_clkmgr_off_kmac_trans.47802873 |
| Directory | /workspace/2.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3828952616 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 5271851668 ps |
| CPU time | 575.19 seconds |
| Started | May 30 04:30:36 PM PDT 24 |
| Finished | May 30 04:40:11 PM PDT 24 |
| Peak memory | 603972 kb |
| Host | smart-8a94f286-d7b1-4d4e-8c22-6f38b12de5d2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828952616 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_otbn_trans.3828952616 |
| Directory | /workspace/2.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.1866273800 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 11526014192 ps |
| CPU time | 1349 seconds |
| Started | May 30 04:33:00 PM PDT 24 |
| Finished | May 30 04:55:30 PM PDT 24 |
| Peak memory | 605316 kb |
| Host | smart-4035cb90-87b2-47df-8e5e-531b1115f514 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866273800 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.1866273800 |
| Directory | /workspace/2.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.2773221546 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 3144112564 ps |
| CPU time | 549.47 seconds |
| Started | May 30 04:33:21 PM PDT 24 |
| Finished | May 30 04:42:31 PM PDT 24 |
| Peak memory | 603576 kb |
| Host | smart-ebe0acff-f34b-43de-8c19-1b457cd85da7 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773221546 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.2773221546 |
| Directory | /workspace/2.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.942498953 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 4069628790 ps |
| CPU time | 689.06 seconds |
| Started | May 30 04:29:42 PM PDT 24 |
| Finished | May 30 04:41:13 PM PDT 24 |
| Peak memory | 603244 kb |
| Host | smart-9f52b5c9-1361-4d34-8e49-7471a5a42a0f |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942498953 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.942498953 |
| Directory | /workspace/2.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.570998576 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 2963573872 ps |
| CPU time | 320.27 seconds |
| Started | May 30 04:33:42 PM PDT 24 |
| Finished | May 30 04:39:03 PM PDT 24 |
| Peak memory | 603472 kb |
| Host | smart-6b125cc9-09b6-4b45-bf3c-2ce94e6d2b6f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570998576 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_clkmgr_smoketest.570998576 |
| Directory | /workspace/2.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.4273266107 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 9494917204 ps |
| CPU time | 2474.26 seconds |
| Started | May 30 04:27:03 PM PDT 24 |
| Finished | May 30 05:08:18 PM PDT 24 |
| Peak memory | 604120 kb |
| Host | smart-d3b554ef-bfa0-45a1-b9dc-6dfa65fbb21e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273266107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency.4273266107 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.1396758214 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 11098879991 ps |
| CPU time | 2017.06 seconds |
| Started | May 30 04:30:11 PM PDT 24 |
| Finished | May 30 05:03:48 PM PDT 24 |
| Peak memory | 604212 kb |
| Host | smart-8c0b70e2-41ba-4e46-8c33-05bc9d43a4b4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=180_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396758214 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _csrng_edn_concurrency_reduced_freq.1396758214 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.3405250282 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 3379665128 ps |
| CPU time | 477.23 seconds |
| Started | May 30 04:30:17 PM PDT 24 |
| Finished | May 30 04:38:15 PM PDT 24 |
| Peak memory | 603664 kb |
| Host | smart-f4926365-761b-40fc-8ce3-afb6a3fdae48 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34052 50282 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.3405250282 |
| Directory | /workspace/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_kat_test.4210227624 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 2255409444 ps |
| CPU time | 261.04 seconds |
| Started | May 30 04:27:17 PM PDT 24 |
| Finished | May 30 04:31:40 PM PDT 24 |
| Peak memory | 603828 kb |
| Host | smart-f3e783a6-28f4-4500-a953-cd481cff853f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210227624 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.4210227624 |
| Directory | /workspace/2.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.186857040 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 4903843300 ps |
| CPU time | 658.69 seconds |
| Started | May 30 04:27:08 PM PDT 24 |
| Finished | May 30 04:38:07 PM PDT 24 |
| Peak memory | 606156 kb |
| Host | smart-3d852a98-0ac3-40d3-8338-4e21435f3797 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186857040 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_l c_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrn g_lc_hw_debug_en_test.186857040 |
| Directory | /workspace/2.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_smoketest.2259634035 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 2678961032 ps |
| CPU time | 176.29 seconds |
| Started | May 30 04:32:54 PM PDT 24 |
| Finished | May 30 04:35:51 PM PDT 24 |
| Peak memory | 603112 kb |
| Host | smart-104844c6-df4d-4e4f-97a9-e29d6cd0baca |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259634035 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_csrng_smoketest.2259634035 |
| Directory | /workspace/2.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_data_integrity_escalation.3003976394 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 5446907416 ps |
| CPU time | 790.13 seconds |
| Started | May 30 04:24:11 PM PDT 24 |
| Finished | May 30 04:37:23 PM PDT 24 |
| Peak memory | 604520 kb |
| Host | smart-32d7a75a-a884-4aa0-a8b3-7661503c1e55 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3003976394 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.3003976394 |
| Directory | /workspace/2.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_auto_mode.2615290114 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 6334177930 ps |
| CPU time | 1366.38 seconds |
| Started | May 30 04:31:20 PM PDT 24 |
| Finished | May 30 04:54:07 PM PDT 24 |
| Peak memory | 604156 kb |
| Host | smart-70906d2c-a784-44dc-860b-b49b0eff8c46 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615290114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ auto_mode.2615290114 |
| Directory | /workspace/2.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_boot_mode.4081036979 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 3194261376 ps |
| CPU time | 592.25 seconds |
| Started | May 30 04:29:42 PM PDT 24 |
| Finished | May 30 04:39:35 PM PDT 24 |
| Peak memory | 604020 kb |
| Host | smart-d899fd2a-32bb-4ea8-ba06-96d7424c744e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081036979 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ boot_mode.4081036979 |
| Directory | /workspace/2.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.20449398 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 6778523060 ps |
| CPU time | 1381.33 seconds |
| Started | May 30 04:28:16 PM PDT 24 |
| Finished | May 30 04:51:18 PM PDT 24 |
| Peak memory | 604656 kb |
| Host | smart-ad3d82c6-8b2f-4c93-af69-a6e1c91726ec |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=20449398 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.20449398 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.1409664098 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 6825344378 ps |
| CPU time | 1174.88 seconds |
| Started | May 30 04:28:28 PM PDT 24 |
| Finished | May 30 04:48:04 PM PDT 24 |
| Peak memory | 604584 kb |
| Host | smart-b926c755-bc21-4c19-94c2-6c0208e7d296 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409664098 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.1409664098 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_kat.326740229 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 3062014520 ps |
| CPU time | 703.33 seconds |
| Started | May 30 04:30:12 PM PDT 24 |
| Finished | May 30 04:41:56 PM PDT 24 |
| Peak memory | 610156 kb |
| Host | smart-43beca4e-e3de-4ae4-97b9-e11a8e494042 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_imag es=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326740229 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_edn_kat.326740229 |
| Directory | /workspace/2.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_sw_mode.2417381637 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 5242719444 ps |
| CPU time | 965.92 seconds |
| Started | May 30 04:28:01 PM PDT 24 |
| Finished | May 30 04:44:07 PM PDT 24 |
| Peak memory | 604044 kb |
| Host | smart-ff5ab3a9-4665-4d62-b616-60d8786c3315 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417381637 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_sw_mode.2417381637 |
| Directory | /workspace/2.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.2146863687 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 2226946640 ps |
| CPU time | 218.03 seconds |
| Started | May 30 04:28:28 PM PDT 24 |
| Finished | May 30 04:32:07 PM PDT 24 |
| Peak memory | 603832 kb |
| Host | smart-cdf92106-d000-4393-ae0a-3e7b696be3f0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21 46863687 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.2146863687 |
| Directory | /workspace/2.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_csrng.1612321530 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 8297230726 ps |
| CPU time | 1494.13 seconds |
| Started | May 30 04:30:59 PM PDT 24 |
| Finished | May 30 04:55:55 PM PDT 24 |
| Peak memory | 603804 kb |
| Host | smart-af9138b2-8dcb-49fd-ba36-046f63addf50 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1612321530 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.1612321530 |
| Directory | /workspace/2.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.1343357841 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 3139408590 ps |
| CPU time | 243.29 seconds |
| Started | May 30 04:27:24 PM PDT 24 |
| Finished | May 30 04:31:29 PM PDT 24 |
| Peak memory | 603492 kb |
| Host | smart-db93127d-6c13-4f81-95f0-de916f443a0f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343357841 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.1343357841 |
| Directory | /workspace/2.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.797243526 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 3671577464 ps |
| CPU time | 698.45 seconds |
| Started | May 30 04:31:26 PM PDT 24 |
| Finished | May 30 04:43:05 PM PDT 24 |
| Peak memory | 603288 kb |
| Host | smart-32ba4e54-fab0-456a-a37f-bdb85a40251c |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=797243526 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.797243526 |
| Directory | /workspace/2.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_concurrency.2893245400 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 2955456388 ps |
| CPU time | 310.97 seconds |
| Started | May 30 04:25:00 PM PDT 24 |
| Finished | May 30 04:30:13 PM PDT 24 |
| Peak memory | 603484 kb |
| Host | smart-f887abba-6132-4642-ad7d-4cb1f490ec84 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893245400 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_example_concurrency.2893245400 |
| Directory | /workspace/2.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_flash.2317201501 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 3073309212 ps |
| CPU time | 245.38 seconds |
| Started | May 30 04:22:53 PM PDT 24 |
| Finished | May 30 04:26:59 PM PDT 24 |
| Peak memory | 603504 kb |
| Host | smart-a58d91a4-67ab-489b-a05d-1e4ada521e98 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317201501 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_flash.2317201501 |
| Directory | /workspace/2.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_manufacturer.3308631054 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 3089006632 ps |
| CPU time | 263.87 seconds |
| Started | May 30 04:25:13 PM PDT 24 |
| Finished | May 30 04:29:38 PM PDT 24 |
| Peak memory | 604524 kb |
| Host | smart-4638fc74-0cd0-4278-b578-21b1dc9d1cab |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308631054 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_manufacturer.3308631054 |
| Directory | /workspace/2.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_rom.2864410278 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 2083192480 ps |
| CPU time | 127.71 seconds |
| Started | May 30 04:22:27 PM PDT 24 |
| Finished | May 30 04:24:36 PM PDT 24 |
| Peak memory | 602984 kb |
| Host | smart-f8cd9f58-32b1-480b-8114-5ce089ad90a1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864410278 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_rom.2864410278 |
| Directory | /workspace/2.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_crash_alert.1732480749 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 5482968400 ps |
| CPU time | 640.58 seconds |
| Started | May 30 04:31:09 PM PDT 24 |
| Finished | May 30 04:41:50 PM PDT 24 |
| Peak memory | 605580 kb |
| Host | smart-9cb846f4-7027-45c4-8349-b1f56920ae38 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=1732480749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.1732480749 |
| Directory | /workspace/2.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access.4103879857 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 6048859172 ps |
| CPU time | 1184.93 seconds |
| Started | May 30 04:24:36 PM PDT 24 |
| Finished | May 30 04:44:22 PM PDT 24 |
| Peak memory | 603816 kb |
| Host | smart-1d248e63-90ce-4d8d-a04d-8e60e98e4d32 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103879857 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_flash_ctrl_access.4103879857 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.1047346695 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 6344266538 ps |
| CPU time | 783.7 seconds |
| Started | May 30 04:25:00 PM PDT 24 |
| Finished | May 30 04:38:04 PM PDT 24 |
| Peak memory | 603968 kb |
| Host | smart-0ff76f16-4c88-4db5-b9d9-8971fa87912a |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047346695 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en.1047346695 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2625545478 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 7146748113 ps |
| CPU time | 1275.46 seconds |
| Started | May 30 04:32:12 PM PDT 24 |
| Finished | May 30 04:53:28 PM PDT 24 |
| Peak memory | 603648 kb |
| Host | smart-206e4466-08c5-45fd-9996-e14c2cec3580 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625545478 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2625545478 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.1063646326 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 5772258125 ps |
| CPU time | 1128.6 seconds |
| Started | May 30 04:27:24 PM PDT 24 |
| Finished | May 30 04:46:14 PM PDT 24 |
| Peak memory | 603848 kb |
| Host | smart-2a9e7f87-bd24-4abf-b766-db009adde7ad |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063646326 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_flash_ctrl_clock_freqs.1063646326 |
| Directory | /workspace/2.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.3642278473 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 4304482880 ps |
| CPU time | 395.43 seconds |
| Started | May 30 04:26:49 PM PDT 24 |
| Finished | May 30 04:33:26 PM PDT 24 |
| Peak memory | 603584 kb |
| Host | smart-66d36b93-4d97-4d40-86d9-56408847a8d1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642278473 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_idle_low_power.3642278473 |
| Directory | /workspace/2.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.3886200672 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 5376232282 ps |
| CPU time | 1127.2 seconds |
| Started | May 30 04:30:54 PM PDT 24 |
| Finished | May 30 04:49:42 PM PDT 24 |
| Peak memory | 603652 kb |
| Host | smart-2b6e8a88-7983-42e8-b7bd-5a4d15b22664 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886200672 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_mem_protection.3886200672 |
| Directory | /workspace/2.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.30724015 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 4363099368 ps |
| CPU time | 662.37 seconds |
| Started | May 30 04:24:59 PM PDT 24 |
| Finished | May 30 04:36:03 PM PDT 24 |
| Peak memory | 604072 kb |
| Host | smart-940a9245-b114-4b5c-8fc7-cec082572d40 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30724015 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.30724015 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1701137191 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 4931528777 ps |
| CPU time | 619.87 seconds |
| Started | May 30 04:31:29 PM PDT 24 |
| Finished | May 30 04:41:50 PM PDT 24 |
| Peak memory | 603996 kb |
| Host | smart-75b489b0-eeb4-4770-b813-0437610c19ea |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1701137191 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1701137191 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.762286166 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 3786598536 ps |
| CPU time | 423.57 seconds |
| Started | May 30 04:31:07 PM PDT 24 |
| Finished | May 30 04:38:11 PM PDT 24 |
| Peak memory | 603264 kb |
| Host | smart-9e31a415-d4ea-4f36-8ad8-066cd0e35b47 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7622861 66 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_write_clear.762286166 |
| Directory | /workspace/2.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.478183680 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 24584763737 ps |
| CPU time | 1874.7 seconds |
| Started | May 30 04:31:29 PM PDT 24 |
| Finished | May 30 05:02:44 PM PDT 24 |
| Peak memory | 608068 kb |
| Host | smart-b36df801-e396-4f0e-83aa-7ff3989751b4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=478183680 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.478183680 |
| Directory | /workspace/2.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.4286773872 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 2711366438 ps |
| CPU time | 231.61 seconds |
| Started | May 30 04:36:21 PM PDT 24 |
| Finished | May 30 04:40:14 PM PDT 24 |
| Peak memory | 603160 kb |
| Host | smart-3170ccd9-1f56-404c-87b6-fbac57c47f63 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4286773872 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.4286773872 |
| Directory | /workspace/2.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio_smoketest.210604582 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 2121067218 ps |
| CPU time | 193.33 seconds |
| Started | May 30 04:31:15 PM PDT 24 |
| Finished | May 30 04:34:30 PM PDT 24 |
| Peak memory | 603372 kb |
| Host | smart-9f842630-d851-4e7c-ab88-b82a69b15071 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210604582 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_gpio_smoketest.210604582 |
| Directory | /workspace/2.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc.1710792261 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 2927716600 ps |
| CPU time | 346.59 seconds |
| Started | May 30 04:30:32 PM PDT 24 |
| Finished | May 30 04:36:19 PM PDT 24 |
| Peak memory | 603156 kb |
| Host | smart-a9812a89-0d14-4eef-a6f4-a3b6f9cf0676 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710792261 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc.1710792261 |
| Directory | /workspace/2.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_idle.1067487843 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 2665009440 ps |
| CPU time | 250.31 seconds |
| Started | May 30 04:27:42 PM PDT 24 |
| Finished | May 30 04:31:53 PM PDT 24 |
| Peak memory | 603508 kb |
| Host | smart-792dbf0c-9ce0-4e71-af80-fe3396a03308 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067487843 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_hmac_enc_idle.1067487843 |
| Directory | /workspace/2.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.1623066004 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 2618445044 ps |
| CPU time | 281.77 seconds |
| Started | May 30 04:29:16 PM PDT 24 |
| Finished | May 30 04:34:00 PM PDT 24 |
| Peak memory | 603520 kb |
| Host | smart-0c2a466a-d130-44a1-9ba6-47604517c197 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623066004 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en.1623066004 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.254699985 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 2895072901 ps |
| CPU time | 268.07 seconds |
| Started | May 30 04:31:19 PM PDT 24 |
| Finished | May 30 04:35:47 PM PDT 24 |
| Peak memory | 603616 kb |
| Host | smart-c0144fea-cb44-46b8-9b88-ae60ead6d66f |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254699985 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.254699985 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_smoketest.3235977903 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 3170371488 ps |
| CPU time | 266.63 seconds |
| Started | May 30 04:32:30 PM PDT 24 |
| Finished | May 30 04:36:57 PM PDT 24 |
| Peak memory | 603512 kb |
| Host | smart-d12f84fc-15e4-40d2-8a4c-636abd74b6cf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235977903 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_hmac_smoketest.3235977903 |
| Directory | /workspace/2.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.1682350302 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 4094071264 ps |
| CPU time | 670.26 seconds |
| Started | May 30 04:24:53 PM PDT 24 |
| Finished | May 30 04:36:05 PM PDT 24 |
| Peak memory | 604760 kb |
| Host | smart-3197c066-fd03-4eb4-a4ca-5024d14326cd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682350302 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.1682350302 |
| Directory | /workspace/2.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.1678081227 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 5467425002 ps |
| CPU time | 740.82 seconds |
| Started | May 30 04:24:05 PM PDT 24 |
| Finished | May 30 04:36:27 PM PDT 24 |
| Peak memory | 603872 kb |
| Host | smart-76e99c04-0b5d-448f-8755-9ae494996052 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678081227 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx.1678081227 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.2822128432 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 4684318120 ps |
| CPU time | 871.19 seconds |
| Started | May 30 04:26:19 PM PDT 24 |
| Finished | May 30 04:40:52 PM PDT 24 |
| Peak memory | 603996 kb |
| Host | smart-4611924a-210d-4a7a-84d4-cd29d9dc8fa1 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822128432 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.2822128432 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_inject_scramble_seed.2198674559 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 63400084483 ps |
| CPU time | 10878.7 seconds |
| Started | May 30 04:26:52 PM PDT 24 |
| Finished | May 30 07:28:13 PM PDT 24 |
| Peak memory | 621476 kb |
| Host | smart-d3a06e95-dc77-4d63-be4e-fe9e899e5da3 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2198674559 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.2198674559 |
| Directory | /workspace/2.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.226236861 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 9162526298 ps |
| CPU time | 1531.54 seconds |
| Started | May 30 04:28:30 PM PDT 24 |
| Finished | May 30 04:54:03 PM PDT 24 |
| Peak memory | 611180 kb |
| Host | smart-9b37b4a5-c0ac-4d38-9679-e9830ac5f822 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262 36861 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation.226236861 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.2949131160 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 8999594385 ps |
| CPU time | 1402.89 seconds |
| Started | May 30 04:27:42 PM PDT 24 |
| Finished | May 30 04:51:06 PM PDT 24 |
| Peak memory | 611216 kb |
| Host | smart-ab94b13a-e72d-43ad-89ea-25d47711dc43 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2949131160 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.2949131160 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1424662369 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 10551972263 ps |
| CPU time | 1248.11 seconds |
| Started | May 30 04:30:14 PM PDT 24 |
| Finished | May 30 04:51:03 PM PDT 24 |
| Peak memory | 611236 kb |
| Host | smart-64daa52e-b912-4ca1-b765-dd8a0b70d2b1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1424662369 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.1424662369 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.516671634 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 9816697134 ps |
| CPU time | 1982.93 seconds |
| Started | May 30 04:27:59 PM PDT 24 |
| Finished | May 30 05:01:03 PM PDT 24 |
| Peak memory | 611184 kb |
| Host | smart-ecccbb23-c09a-4b73-bcf3-ed629af6b52e |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=516671634 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.516671634 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.1839727078 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 8317149500 ps |
| CPU time | 1537.96 seconds |
| Started | May 30 04:29:29 PM PDT 24 |
| Finished | May 30 04:55:08 PM PDT 24 |
| Peak memory | 605760 kb |
| Host | smart-6cb2942e-08f4-4e79-b833-2fd73e1dda2b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183972 7078 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.1839727078 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.151203193 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 10839575000 ps |
| CPU time | 2587.45 seconds |
| Started | May 30 04:29:02 PM PDT 24 |
| Finished | May 30 05:12:10 PM PDT 24 |
| Peak memory | 604532 kb |
| Host | smart-435d573e-d8ff-4ce6-97ed-d20ca11499b0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15120 3193 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.151203193 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.2053098234 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 12759326050 ps |
| CPU time | 2909.79 seconds |
| Started | May 30 04:27:41 PM PDT 24 |
| Finished | May 30 05:16:12 PM PDT 24 |
| Peak memory | 604600 kb |
| Host | smart-901f1a11-fe22-4c83-b7c9-9ca15735c6cb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20530 98234 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.2053098234 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_app_rom.432958468 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 2590903000 ps |
| CPU time | 213.24 seconds |
| Started | May 30 04:29:24 PM PDT 24 |
| Finished | May 30 04:32:58 PM PDT 24 |
| Peak memory | 603464 kb |
| Host | smart-6d78b861-372b-4f04-abdc-8adedeb00498 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432958468 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_kmac_app_rom.432958468 |
| Directory | /workspace/2.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_idle.4184427142 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 2847091400 ps |
| CPU time | 208.02 seconds |
| Started | May 30 04:28:45 PM PDT 24 |
| Finished | May 30 04:32:13 PM PDT 24 |
| Peak memory | 603464 kb |
| Host | smart-747e4622-4ea7-415f-8614-c5c8c8deaad8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184427142 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_idle.4184427142 |
| Directory | /workspace/2.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.3746504762 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 2436243400 ps |
| CPU time | 194.55 seconds |
| Started | May 30 04:28:21 PM PDT 24 |
| Finished | May 30 04:31:36 PM PDT 24 |
| Peak memory | 603792 kb |
| Host | smart-c3f20cda-1ff5-45a3-a364-6672661869c4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746504762 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_sw_kmac_mode_cshake.3746504762 |
| Directory | /workspace/2.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.3300412606 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 2194450040 ps |
| CPU time | 219.7 seconds |
| Started | May 30 04:28:31 PM PDT 24 |
| Finished | May 30 04:32:12 PM PDT 24 |
| Peak memory | 603292 kb |
| Host | smart-c23ea4c8-3e9e-4b7d-9ba1-d2adb6aaf3ec |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300412606 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_kmac_mode_kmac.3300412606 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.1532572425 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 2912158804 ps |
| CPU time | 325.67 seconds |
| Started | May 30 04:28:31 PM PDT 24 |
| Finished | May 30 04:33:58 PM PDT 24 |
| Peak memory | 603180 kb |
| Host | smart-324a0a4a-d5e2-4cc9-80fa-7520cbc4df7f |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532572425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.1532572425 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1081098808 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 2347896618 ps |
| CPU time | 308.87 seconds |
| Started | May 30 04:32:15 PM PDT 24 |
| Finished | May 30 04:37:25 PM PDT 24 |
| Peak memory | 603500 kb |
| Host | smart-3473b292-a2cc-4536-8d62-7ec0e74fc90e |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10810988 08 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1081098808 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_smoketest.1737621256 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 2566560490 ps |
| CPU time | 246.15 seconds |
| Started | May 30 04:31:07 PM PDT 24 |
| Finished | May 30 04:35:14 PM PDT 24 |
| Peak memory | 603472 kb |
| Host | smart-6e4c90f4-4455-453b-a2a9-3ff24efe49cb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737621256 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_smoketest.1737621256 |
| Directory | /workspace/2.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.2991693555 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 2882535608 ps |
| CPU time | 348.04 seconds |
| Started | May 30 04:25:48 PM PDT 24 |
| Finished | May 30 04:31:37 PM PDT 24 |
| Peak memory | 603172 kb |
| Host | smart-fc12da52-f9c7-4a5c-a573-14c7ed690ad1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991693555 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_lc_ctrl_otp_hw_cfg0.2991693555 |
| Directory | /workspace/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3558266694 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 3320531539 ps |
| CPU time | 168.72 seconds |
| Started | May 30 04:28:36 PM PDT 24 |
| Finished | May 30 04:31:25 PM PDT 24 |
| Peak memory | 615240 kb |
| Host | smart-62d5649c-ea54-4989-8b27-58d38b8b239c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35582666 94 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_rand_to_scrap.3558266694 |
| Directory | /workspace/2.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.2864018166 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 7710586938 ps |
| CPU time | 615.05 seconds |
| Started | May 30 04:24:54 PM PDT 24 |
| Finished | May 30 04:35:10 PM PDT 24 |
| Peak memory | 615604 kb |
| Host | smart-fa2c7114-89c3-45f2-bbfd-631c1c69361a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864018166 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_transition.2864018166 |
| Directory | /workspace/2.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.2031877989 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 2305372937 ps |
| CPU time | 94.58 seconds |
| Started | May 30 04:25:25 PM PDT 24 |
| Finished | May 30 04:27:00 PM PDT 24 |
| Peak memory | 609488 kb |
| Host | smart-8082986c-ad7f-4910-8000-fa29994dfa7e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2031877989 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.2031877989 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3470117912 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 3079960801 ps |
| CPU time | 122.98 seconds |
| Started | May 30 04:27:46 PM PDT 24 |
| Finished | May 30 04:29:51 PM PDT 24 |
| Peak memory | 610584 kb |
| Host | smart-5b49617d-935e-40eb-8db5-032760e66591 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470117912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3470117912 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.3771449478 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 48337374250 ps |
| CPU time | 4849.24 seconds |
| Started | May 30 04:28:53 PM PDT 24 |
| Finished | May 30 05:49:43 PM PDT 24 |
| Peak memory | 611312 kb |
| Host | smart-2288a3f3-3f03-4ec2-b54d-e88e429820d8 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771449478 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_dev.3771449478 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.1563022558 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 8068553742 ps |
| CPU time | 1123.71 seconds |
| Started | May 30 04:24:51 PM PDT 24 |
| Finished | May 30 04:43:36 PM PDT 24 |
| Peak memory | 612124 kb |
| Host | smart-21e12ffb-5129-4ff8-b6c3-9ce084fee2b0 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563022558 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.1563022558 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.3320998154 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 48238852390 ps |
| CPU time | 4974.25 seconds |
| Started | May 30 04:27:48 PM PDT 24 |
| Finished | May 30 05:50:44 PM PDT 24 |
| Peak memory | 612348 kb |
| Host | smart-7e699b55-2005-4927-8267-68c26f445581 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320998154 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_rma.3320998154 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.2576543322 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 24685518160 ps |
| CPU time | 2271.1 seconds |
| Started | May 30 04:25:43 PM PDT 24 |
| Finished | May 30 05:03:36 PM PDT 24 |
| Peak memory | 610108 kb |
| Host | smart-14328444-960f-4130-92e6-96dcdebc35cb |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2576543322 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testun locks.2576543322 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.2403334892 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 16473302208 ps |
| CPU time | 3240.27 seconds |
| Started | May 30 04:26:50 PM PDT 24 |
| Finished | May 30 05:20:51 PM PDT 24 |
| Peak memory | 604200 kb |
| Host | smart-f57b182c-d1be-47ab-b52f-5877786da698 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=2403334892 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.2403334892 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.526998029 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 18669082852 ps |
| CPU time | 3486.97 seconds |
| Started | May 30 04:27:39 PM PDT 24 |
| Finished | May 30 05:25:47 PM PDT 24 |
| Peak memory | 604180 kb |
| Host | smart-35799938-0798-4c72-a602-a762c67d2092 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=526998029 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.526998029 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2799317603 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 24199715355 ps |
| CPU time | 3398.5 seconds |
| Started | May 30 04:31:25 PM PDT 24 |
| Finished | May 30 05:28:05 PM PDT 24 |
| Peak memory | 604148 kb |
| Host | smart-364b5691-7e82-4acc-ae2b-f86078c0bcaf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799317603 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.2799317603 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.682982298 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 3018644200 ps |
| CPU time | 426.5 seconds |
| Started | May 30 04:26:54 PM PDT 24 |
| Finished | May 30 04:34:02 PM PDT 24 |
| Peak memory | 603908 kb |
| Host | smart-9042eb0e-3eb8-4e94-a85d-c88982441dec |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682982298 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.682982298 |
| Directory | /workspace/2.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_randomness.1305659854 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 5901904520 ps |
| CPU time | 1132.16 seconds |
| Started | May 30 04:27:04 PM PDT 24 |
| Finished | May 30 04:45:58 PM PDT 24 |
| Peak memory | 604176 kb |
| Host | smart-095d6cfc-e26b-4e9a-bc0d-b7546999d1f3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1305659854 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.1305659854 |
| Directory | /workspace/2.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_smoketest.3168259080 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 5855684040 ps |
| CPU time | 1120.8 seconds |
| Started | May 30 04:31:58 PM PDT 24 |
| Finished | May 30 04:50:40 PM PDT 24 |
| Peak memory | 603960 kb |
| Host | smart-ebfb4bde-1274-42d3-b961-08f709898bd3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168259080 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_otbn_smoketest.3168259080 |
| Directory | /workspace/2.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.513056428 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 2917963407 ps |
| CPU time | 385.89 seconds |
| Started | May 30 04:26:44 PM PDT 24 |
| Finished | May 30 04:33:11 PM PDT 24 |
| Peak memory | 603320 kb |
| Host | smart-7e94fcf5-78cd-41cd-8ebe-404646f67bd4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513056428 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_ecc_error_vendor_test.513056428 |
| Directory | /workspace/2.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.2759679705 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 8957897552 ps |
| CPU time | 1226.43 seconds |
| Started | May 30 04:25:31 PM PDT 24 |
| Finished | May 30 04:45:59 PM PDT 24 |
| Peak memory | 603852 kb |
| Host | smart-1164e1c2-18c5-4f25-8820-2053514eb71e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2759679705 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.2759679705 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.1546025799 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 7212898602 ps |
| CPU time | 1422.37 seconds |
| Started | May 30 04:26:18 PM PDT 24 |
| Finished | May 30 04:50:02 PM PDT 24 |
| Peak memory | 604168 kb |
| Host | smart-fb2f0016-6e51-41d7-a173-c642b32eb8b9 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1546025799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.1546025799 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.3503416941 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 7743904950 ps |
| CPU time | 1419.71 seconds |
| Started | May 30 04:25:35 PM PDT 24 |
| Finished | May 30 04:49:15 PM PDT 24 |
| Peak memory | 604084 kb |
| Host | smart-b8519e98-7ad6-45b2-b7a4-265852282ab9 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3503416941 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.3503416941 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.390191201 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 4704065740 ps |
| CPU time | 671.62 seconds |
| Started | May 30 04:26:46 PM PDT 24 |
| Finished | May 30 04:37:58 PM PDT 24 |
| Peak memory | 603900 kb |
| Host | smart-f45e5d45-dd1d-4a9d-954a-558851085172 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=390191201 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.390191201 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.2924385388 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 3137469536 ps |
| CPU time | 337.27 seconds |
| Started | May 30 04:31:55 PM PDT 24 |
| Finished | May 30 04:37:32 PM PDT 24 |
| Peak memory | 603476 kb |
| Host | smart-f380d997-ba60-46ed-810d-cc1723533d9a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924385388 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_otp_ctrl_smoketest.2924385388 |
| Directory | /workspace/2.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pattgen_ios.2665131687 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 3027743180 ps |
| CPU time | 240.34 seconds |
| Started | May 30 04:24:47 PM PDT 24 |
| Finished | May 30 04:28:48 PM PDT 24 |
| Peak memory | 604228 kb |
| Host | smart-e4302520-fe2c-4611-b348-78d379b2cf83 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665131687 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.2665131687 |
| Directory | /workspace/2.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/2.chip_sw_plic_sw_irq.1641061068 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 3041169322 ps |
| CPU time | 252.73 seconds |
| Started | May 30 04:29:57 PM PDT 24 |
| Finished | May 30 04:34:11 PM PDT 24 |
| Peak memory | 603492 kb |
| Host | smart-6f80bb93-c8b5-49dd-b746-6e01cb17d607 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641061068 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_plic_sw_irq.1641061068 |
| Directory | /workspace/2.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_idle_load.2569258801 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 4508781240 ps |
| CPU time | 661.84 seconds |
| Started | May 30 04:32:16 PM PDT 24 |
| Finished | May 30 04:43:19 PM PDT 24 |
| Peak memory | 604084 kb |
| Host | smart-e669f19a-887f-4046-a87a-40b2e900b261 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569258801 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_idle_load.2569258801 |
| Directory | /workspace/2.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_sleep_load.2816570229 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 11106370000 ps |
| CPU time | 645.19 seconds |
| Started | May 30 04:30:41 PM PDT 24 |
| Finished | May 30 04:41:28 PM PDT 24 |
| Peak memory | 604380 kb |
| Host | smart-3270a26b-d4ca-4d9d-b465-d17b123155bb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816570229 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.2816570229 |
| Directory | /workspace/2.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.1548404301 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 9104138640 ps |
| CPU time | 1335.68 seconds |
| Started | May 30 04:26:26 PM PDT 24 |
| Finished | May 30 04:48:43 PM PDT 24 |
| Peak memory | 605568 kb |
| Host | smart-45fc1c65-5ba5-472d-9b7f-4829589811f3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548 404301 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.1548404301 |
| Directory | /workspace/2.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.3419901651 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 20969089452 ps |
| CPU time | 1817.26 seconds |
| Started | May 30 04:29:49 PM PDT 24 |
| Finished | May 30 05:00:07 PM PDT 24 |
| Peak memory | 604500 kb |
| Host | smart-e55d1290-ce62-455c-b970-f356f0d39ab1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341 9901651 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.3419901651 |
| Directory | /workspace/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.671472027 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 14440222445 ps |
| CPU time | 1497.6 seconds |
| Started | May 30 04:27:58 PM PDT 24 |
| Finished | May 30 04:52:57 PM PDT 24 |
| Peak memory | 605688 kb |
| Host | smart-3a32e28c-2cab-4b25-9c9c-5afea95963b1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=671472027 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.671472027 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.117176950 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 22095131794 ps |
| CPU time | 1532.35 seconds |
| Started | May 30 04:32:14 PM PDT 24 |
| Finished | May 30 04:57:48 PM PDT 24 |
| Peak memory | 605164 kb |
| Host | smart-ef33a92c-0933-45c1-8b0a-ab247b579d4d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 117176950 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.117176950 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.3047295954 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 6584087138 ps |
| CPU time | 728.32 seconds |
| Started | May 30 04:26:26 PM PDT 24 |
| Finished | May 30 04:38:35 PM PDT 24 |
| Peak memory | 604548 kb |
| Host | smart-f9e29152-306d-4b7c-946b-888663b84a34 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047295954 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_por_reset.3047295954 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.783049156 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 6405175880 ps |
| CPU time | 349.81 seconds |
| Started | May 30 04:29:44 PM PDT 24 |
| Finished | May 30 04:35:34 PM PDT 24 |
| Peak memory | 610004 kb |
| Host | smart-a3c5cbe9-0af5-4b70-b3dc-dbbeb1e162de |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=783049156 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.783049156 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.4191669100 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 7258379202 ps |
| CPU time | 535.65 seconds |
| Started | May 30 04:26:28 PM PDT 24 |
| Finished | May 30 04:35:25 PM PDT 24 |
| Peak memory | 604184 kb |
| Host | smart-5cf85f2f-f67f-46d2-b809-98a6f22055fe |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191669100 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_full_aon_reset.4191669100 |
| Directory | /workspace/2.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.4289705284 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 5223829400 ps |
| CPU time | 509.73 seconds |
| Started | May 30 04:26:02 PM PDT 24 |
| Finished | May 30 04:34:33 PM PDT 24 |
| Peak memory | 610620 kb |
| Host | smart-342b0eaa-0175-4d06-bf0b-3e8d9623021f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=4289705284 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.4289705284 |
| Directory | /workspace/2.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.314450874 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 9313232441 ps |
| CPU time | 1105.2 seconds |
| Started | May 30 04:26:32 PM PDT 24 |
| Finished | May 30 04:44:58 PM PDT 24 |
| Peak memory | 605684 kb |
| Host | smart-3268a28c-561c-4db7-977c-38edb34307ec |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314450874 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.314450874 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3998299287 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 7523280960 ps |
| CPU time | 451.86 seconds |
| Started | May 30 04:29:36 PM PDT 24 |
| Finished | May 30 04:37:09 PM PDT 24 |
| Peak memory | 604456 kb |
| Host | smart-0215442d-a69a-45fe-84cd-3297601b9181 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998299287 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3998299287 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.392542015 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 7768834317 ps |
| CPU time | 910.95 seconds |
| Started | May 30 04:26:48 PM PDT 24 |
| Finished | May 30 04:42:00 PM PDT 24 |
| Peak memory | 604076 kb |
| Host | smart-3080c435-76cf-4319-82ee-25ac194561f9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392542015 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.392542015 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.821355926 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 21795418802 ps |
| CPU time | 1961.52 seconds |
| Started | May 30 04:25:26 PM PDT 24 |
| Finished | May 30 04:58:10 PM PDT 24 |
| Peak memory | 605992 kb |
| Host | smart-f01b92e5-8513-4c83-886f-365b4206545c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=821355926 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.821355926 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1915453628 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 21525102426 ps |
| CPU time | 1558.19 seconds |
| Started | May 30 04:30:20 PM PDT 24 |
| Finished | May 30 04:56:18 PM PDT 24 |
| Peak memory | 605468 kb |
| Host | smart-87095621-4490-4597-a9f8-53695689c987 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1915453628 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1915453628 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.4272118714 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 30842373560 ps |
| CPU time | 3603.29 seconds |
| Started | May 30 04:25:49 PM PDT 24 |
| Finished | May 30 05:25:54 PM PDT 24 |
| Peak memory | 605704 kb |
| Host | smart-25635489-6b44-421c-be32-7f2229af9fb8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272118714 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_s leep_power_glitch_reset.4272118714 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2197445558 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 4567767720 ps |
| CPU time | 423.59 seconds |
| Started | May 30 04:33:06 PM PDT 24 |
| Finished | May 30 04:40:10 PM PDT 24 |
| Peak memory | 605788 kb |
| Host | smart-19435697-4b95-4d58-93b3-927d7fa31103 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2197445558 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.2197445558 |
| Directory | /workspace/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.3733301522 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 3001407020 ps |
| CPU time | 260.02 seconds |
| Started | May 30 04:30:23 PM PDT 24 |
| Finished | May 30 04:34:43 PM PDT 24 |
| Peak memory | 603140 kb |
| Host | smart-3cf401e4-1dd7-42ea-8704-2a3e6894ba91 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733301522 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_disabled.3733301522 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.1539832294 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 4980196216 ps |
| CPU time | 417.56 seconds |
| Started | May 30 04:26:52 PM PDT 24 |
| Finished | May 30 04:33:51 PM PDT 24 |
| Peak memory | 610748 kb |
| Host | smart-0e46e77e-0fb0-4bdb-a3dc-b2562fe7add5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1539832294 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_power_glitch_reset.1539832294 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3599319158 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 5933539560 ps |
| CPU time | 361.81 seconds |
| Started | May 30 04:30:08 PM PDT 24 |
| Finished | May 30 04:36:11 PM PDT 24 |
| Peak memory | 605092 kb |
| Host | smart-e574fc0f-c4a8-44e6-b56a-960cbe18edf5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3599319158 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.3599319158 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1278662697 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 5573219612 ps |
| CPU time | 522.91 seconds |
| Started | May 30 04:31:49 PM PDT 24 |
| Finished | May 30 04:40:33 PM PDT 24 |
| Peak memory | 603680 kb |
| Host | smart-2c127359-3ac2-4c5d-96be-1d6e687299c0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278662697 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.1278662697 |
| Directory | /workspace/2.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.3067493342 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 8975902176 ps |
| CPU time | 1399.84 seconds |
| Started | May 30 04:27:46 PM PDT 24 |
| Finished | May 30 04:51:09 PM PDT 24 |
| Peak memory | 604356 kb |
| Host | smart-7ce22689-f67b-480d-ba01-0a6ca1dc36a7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067493342 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.3067493342 |
| Directory | /workspace/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2973343274 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 5445746946 ps |
| CPU time | 565.82 seconds |
| Started | May 30 04:29:00 PM PDT 24 |
| Finished | May 30 04:38:27 PM PDT 24 |
| Peak memory | 603624 kb |
| Host | smart-f7faa44c-145d-475d-b0ae-8784c8320864 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973343274 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2973343274 |
| Directory | /workspace/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.3976098009 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 4748043516 ps |
| CPU time | 345.86 seconds |
| Started | May 30 04:32:26 PM PDT 24 |
| Finished | May 30 04:38:12 PM PDT 24 |
| Peak memory | 603640 kb |
| Host | smart-6ff03872-0a32-4b8d-bea6-42245d9c944f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976098009 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usbdev_smoketest.3976098009 |
| Directory | /workspace/2.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.4136327655 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 3869267892 ps |
| CPU time | 577.23 seconds |
| Started | May 30 04:25:20 PM PDT 24 |
| Finished | May 30 04:34:58 PM PDT 24 |
| Peak memory | 603876 kb |
| Host | smart-26472caa-7e29-4e5a-867e-9609834399ea |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413 6327655 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.4136327655 |
| Directory | /workspace/2.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.787228345 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 9045046335 ps |
| CPU time | 592.06 seconds |
| Started | May 30 04:28:12 PM PDT 24 |
| Finished | May 30 04:38:05 PM PDT 24 |
| Peak memory | 604108 kb |
| Host | smart-22c952dc-66a4-412c-886d-eb92498286c6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787228345 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.787228345 |
| Directory | /workspace/2.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1929560459 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 11852897144 ps |
| CPU time | 1815.06 seconds |
| Started | May 30 04:26:36 PM PDT 24 |
| Finished | May 30 04:56:52 PM PDT 24 |
| Peak memory | 605408 kb |
| Host | smart-37b153e3-03c0-424b-9a8b-3f6835817c69 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1929560459 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.1929560459 |
| Directory | /workspace/2.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.3698740085 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 6448757692 ps |
| CPU time | 750.29 seconds |
| Started | May 30 04:26:41 PM PDT 24 |
| Finished | May 30 04:39:13 PM PDT 24 |
| Peak memory | 604176 kb |
| Host | smart-496c8fed-b99c-499c-83c0-eb6f96d290b4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698740085 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_rstmgr_cpu_info.3698740085 |
| Directory | /workspace/2.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.490670995 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 5334047180 ps |
| CPU time | 673.46 seconds |
| Started | May 30 04:24:01 PM PDT 24 |
| Finished | May 30 04:35:15 PM PDT 24 |
| Peak memory | 636428 kb |
| Host | smart-cbcc7f92-f917-4f01-8065-715af0cf0540 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 490670995 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.490670995 |
| Directory | /workspace/2.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.1879839756 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 3149329370 ps |
| CPU time | 221.08 seconds |
| Started | May 30 04:31:37 PM PDT 24 |
| Finished | May 30 04:35:18 PM PDT 24 |
| Peak memory | 603460 kb |
| Host | smart-2686cd48-f12a-45f7-8f96-d81243224c9e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879839756 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_rstmgr_smoketest.1879839756 |
| Directory | /workspace/2.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.1435787428 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 3418392200 ps |
| CPU time | 514.98 seconds |
| Started | May 30 04:25:40 PM PDT 24 |
| Finished | May 30 04:34:16 PM PDT 24 |
| Peak memory | 603628 kb |
| Host | smart-3cacd21c-3871-488e-bec9-ac0522e74f96 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435787428 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rstmgr_sw_req.1435787428 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.2513459594 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 3084957400 ps |
| CPU time | 261.17 seconds |
| Started | May 30 04:26:35 PM PDT 24 |
| Finished | May 30 04:30:57 PM PDT 24 |
| Peak memory | 603208 kb |
| Host | smart-f55acf61-573c-4e24-a20c-734641f239e6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513459594 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_sw_rst.2513459594 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.1189297567 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 2286604744 ps |
| CPU time | 238.14 seconds |
| Started | May 30 04:31:20 PM PDT 24 |
| Finished | May 30 04:35:19 PM PDT 24 |
| Peak memory | 603916 kb |
| Host | smart-d792eb77-04cd-409f-bc5a-49a1b893fd97 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1189297567 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.1189297567 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.1999040857 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 2133390423 ps |
| CPU time | 204.48 seconds |
| Started | May 30 04:30:24 PM PDT 24 |
| Finished | May 30 04:33:50 PM PDT 24 |
| Peak memory | 603716 kb |
| Host | smart-940044b1-5cc2-44e0-a71f-ae8b9f2d3c1b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999040857 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.1999040857 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.1896655089 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 2950931166 ps |
| CPU time | 260.34 seconds |
| Started | May 30 04:30:13 PM PDT 24 |
| Finished | May 30 04:34:34 PM PDT 24 |
| Peak memory | 640632 kb |
| Host | smart-f8a0d0f4-d8ba-452f-8dcb-00b6db1a46da |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896655089 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_lockstep_glitch.1896655089 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3267838494 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 4278405384 ps |
| CPU time | 765.33 seconds |
| Started | May 30 04:30:33 PM PDT 24 |
| Finished | May 30 04:43:19 PM PDT 24 |
| Peak memory | 603224 kb |
| Host | smart-280e3de9-2b17-48e1-a75a-4cbf031f5f27 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32678 38494 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.3267838494 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.3553083395 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 4969072200 ps |
| CPU time | 849.1 seconds |
| Started | May 30 04:29:38 PM PDT 24 |
| Finished | May 30 04:43:48 PM PDT 24 |
| Peak memory | 604056 kb |
| Host | smart-3b4011d4-4d40-4531-8343-ab8be0cb1f49 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3553083395 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.3553083395 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.3438907290 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 5741711390 ps |
| CPU time | 640.84 seconds |
| Started | May 30 04:30:04 PM PDT 24 |
| Finished | May 30 04:40:46 PM PDT 24 |
| Peak memory | 613164 kb |
| Host | smart-34eed083-d48e-4d82-ae8d-cab3e6ef2bfc |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438907290 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.3438907290 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3879126611 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 3675466456 ps |
| CPU time | 495.89 seconds |
| Started | May 30 04:29:46 PM PDT 24 |
| Finished | May 30 04:38:03 PM PDT 24 |
| Peak memory | 613148 kb |
| Host | smart-f3036492-1ccc-488c-b43e-f15599535273 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387912 6611 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3879126611 |
| Directory | /workspace/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.4290853381 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 2715699870 ps |
| CPU time | 225.8 seconds |
| Started | May 30 04:32:00 PM PDT 24 |
| Finished | May 30 04:35:47 PM PDT 24 |
| Peak memory | 603508 kb |
| Host | smart-d7a46e09-8af3-4db1-b81d-c0815862abce |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290853381 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_rv_plic_smoketest.4290853381 |
| Directory | /workspace/2.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_irq.943419426 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 2738857440 ps |
| CPU time | 326.76 seconds |
| Started | May 30 04:27:00 PM PDT 24 |
| Finished | May 30 04:32:28 PM PDT 24 |
| Peak memory | 603528 kb |
| Host | smart-080d47d4-982e-4002-b2fa-e3c04fbc0a22 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943419426 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_rv_timer_irq.943419426 |
| Directory | /workspace/2.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3279540560 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 2391297752 ps |
| CPU time | 276.65 seconds |
| Started | May 30 04:33:15 PM PDT 24 |
| Finished | May 30 04:37:52 PM PDT 24 |
| Peak memory | 603468 kb |
| Host | smart-2f0f9d44-7700-4a7d-adc7-b00ad7c78fdf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279540560 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_smoketest.3279540560 |
| Directory | /workspace/2.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1546662315 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 6091671978 ps |
| CPU time | 668.11 seconds |
| Started | May 30 04:28:29 PM PDT 24 |
| Finished | May 30 04:39:38 PM PDT 24 |
| Peak memory | 604060 kb |
| Host | smart-4b5199b1-d086-4a50-8f54-8ea7d15c32f7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15466623 15 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.1546662315 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.2728655871 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 3179495257 ps |
| CPU time | 254.74 seconds |
| Started | May 30 04:29:29 PM PDT 24 |
| Finished | May 30 04:33:44 PM PDT 24 |
| Peak memory | 604132 kb |
| Host | smart-e93f3a1e-082d-4b71-912e-a70186b31bd9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728655 871 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.2728655871 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_retention.957607366 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4399709160 ps |
| CPU time | 433.2 seconds |
| Started | May 30 04:27:24 PM PDT 24 |
| Finished | May 30 04:34:40 PM PDT 24 |
| Peak memory | 603960 kb |
| Host | smart-82a3dedc-4b6b-4d9e-897c-9f3ba766c501 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957607366 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_retention.957607366 |
| Directory | /workspace/2.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.2155015212 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 8843926780 ps |
| CPU time | 1468.09 seconds |
| Started | May 30 04:23:53 PM PDT 24 |
| Finished | May 30 04:48:23 PM PDT 24 |
| Peak memory | 604056 kb |
| Host | smart-84ff99a5-d69e-46a9-a62f-d2d11f324dc6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155015212 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_sleep_pwm_pulses.2155015212 |
| Directory | /workspace/2.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3945156235 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 6810478500 ps |
| CPU time | 536.34 seconds |
| Started | May 30 04:30:10 PM PDT 24 |
| Finished | May 30 04:39:07 PM PDT 24 |
| Peak memory | 604992 kb |
| Host | smart-560ebde5-a550-4cbb-97f6-f18a029bd555 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945156235 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sl eep_sram_ret_contents_no_scramble.3945156235 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.1745119312 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 7636082970 ps |
| CPU time | 861.27 seconds |
| Started | May 30 04:28:00 PM PDT 24 |
| Finished | May 30 04:42:22 PM PDT 24 |
| Peak memory | 605536 kb |
| Host | smart-0d425906-38a9-4780-8088-14318be7e6e9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745119312 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep _sram_ret_contents_scramble.1745119312 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through.363487381 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 5602855925 ps |
| CPU time | 687.84 seconds |
| Started | May 30 04:26:32 PM PDT 24 |
| Finished | May 30 04:38:01 PM PDT 24 |
| Peak memory | 621508 kb |
| Host | smart-a0f2f66d-a354-4be3-aca8-df8c5067affb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363487381 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through.363487381 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.398721076 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 4668957298 ps |
| CPU time | 528.11 seconds |
| Started | May 30 04:25:05 PM PDT 24 |
| Finished | May 30 04:33:54 PM PDT 24 |
| Peak memory | 621484 kb |
| Host | smart-abb0d4fc-d52a-4a5c-a439-beb72b077d63 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398721076 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.398721076 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_tpm.1549500774 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 3716626732 ps |
| CPU time | 304.03 seconds |
| Started | May 30 04:25:13 PM PDT 24 |
| Finished | May 30 04:30:18 PM PDT 24 |
| Peak memory | 611172 kb |
| Host | smart-b13b46c6-4152-404d-abcb-778daabffbe7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549500774 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_tpm.1549500774 |
| Directory | /workspace/2.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.620620943 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 3557810308 ps |
| CPU time | 368.01 seconds |
| Started | May 30 04:26:56 PM PDT 24 |
| Finished | May 30 04:33:06 PM PDT 24 |
| Peak memory | 603648 kb |
| Host | smart-1410aefc-2d9d-4cb0-95ab-5bc7ab2a4887 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620620943 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_spi_host_tx_rx.620620943 |
| Directory | /workspace/2.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.3555571368 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 7523894799 ps |
| CPU time | 586.98 seconds |
| Started | May 30 04:28:50 PM PDT 24 |
| Finished | May 30 04:38:38 PM PDT 24 |
| Peak memory | 604288 kb |
| Host | smart-2034f21d-ea57-4e42-95a2-2e309e14594e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555571368 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.3555571368 |
| Directory | /workspace/2.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.318438396 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 5228788700 ps |
| CPU time | 594.58 seconds |
| Started | May 30 04:31:20 PM PDT 24 |
| Finished | May 30 04:41:15 PM PDT 24 |
| Peak memory | 605432 kb |
| Host | smart-dbe79c47-6df6-4081-9613-824e31f8d645 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318438396 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl _scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ sram_ctrl_scrambled_access.318438396 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3730247286 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 5009173640 ps |
| CPU time | 714.4 seconds |
| Started | May 30 04:28:03 PM PDT 24 |
| Finished | May 30 04:39:58 PM PDT 24 |
| Peak memory | 604260 kb |
| Host | smart-5a0048ae-3d65-41f9-a6c0-2e4d8b29cc70 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730247286 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3730247286 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2075738731 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 3886497514 ps |
| CPU time | 622.67 seconds |
| Started | May 30 04:32:43 PM PDT 24 |
| Finished | May 30 04:43:07 PM PDT 24 |
| Peak memory | 604340 kb |
| Host | smart-ed8cfa27-4eba-448e-a4be-ba68e9d0d56d |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075738731 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2075738731 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.2651574066 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 3081273490 ps |
| CPU time | 307.34 seconds |
| Started | May 30 04:33:47 PM PDT 24 |
| Finished | May 30 04:38:55 PM PDT 24 |
| Peak memory | 603204 kb |
| Host | smart-800801ad-87b5-482b-b5c7-5d52a7904a3b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651574066 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_sram_ctrl_smoketest.2651574066 |
| Directory | /workspace/2.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3529260177 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 20311932907 ps |
| CPU time | 2933.42 seconds |
| Started | May 30 04:27:04 PM PDT 24 |
| Finished | May 30 05:15:59 PM PDT 24 |
| Peak memory | 604284 kb |
| Host | smart-630ad42b-aff1-49cc-b6e4-c71fe704b148 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529260177 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.3529260177 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.1672475397 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 4697169347 ps |
| CPU time | 646.36 seconds |
| Started | May 30 04:25:46 PM PDT 24 |
| Finished | May 30 04:36:35 PM PDT 24 |
| Peak memory | 608276 kb |
| Host | smart-ccf84445-6b15-49d0-bdef-d0197f536714 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672475397 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_in_irq.1672475397 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.4095936429 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 2937313424 ps |
| CPU time | 303.56 seconds |
| Started | May 30 04:27:49 PM PDT 24 |
| Finished | May 30 04:32:55 PM PDT 24 |
| Peak memory | 608336 kb |
| Host | smart-81c7579c-191e-4fff-b5e7-ab0cc60d49af |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095936429 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_inputs.4095936429 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.687350101 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 5164372800 ps |
| CPU time | 454.5 seconds |
| Started | May 30 04:26:30 PM PDT 24 |
| Finished | May 30 04:34:06 PM PDT 24 |
| Peak memory | 604060 kb |
| Host | smart-900057db-2c50-4c7c-82c6-def3bc3f3e90 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687350101 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.687350101 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.1446504112 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 4252257288 ps |
| CPU time | 381.74 seconds |
| Started | May 30 04:23:46 PM PDT 24 |
| Finished | May 30 04:30:08 PM PDT 24 |
| Peak memory | 612540 kb |
| Host | smart-9b19a2c7-d1fe-4119-aa8c-185acc5833a4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1446504112 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.1446504112 |
| Directory | /workspace/2.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_smoketest.1032258335 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 3056176800 ps |
| CPU time | 334.3 seconds |
| Started | May 30 04:32:18 PM PDT 24 |
| Finished | May 30 04:37:54 PM PDT 24 |
| Peak memory | 603820 kb |
| Host | smart-b55e6999-960a-4779-9038-9ba83c3078f2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032258335 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_uart_smoketest.1032258335 |
| Directory | /workspace/2.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx.3030091905 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 4020906364 ps |
| CPU time | 546.82 seconds |
| Started | May 30 04:24:59 PM PDT 24 |
| Finished | May 30 04:34:07 PM PDT 24 |
| Peak memory | 612240 kb |
| Host | smart-c7c5e032-d6e1-4dda-b364-0718296b3748 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030091905 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.3030091905 |
| Directory | /workspace/2.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.2036209389 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 12864549433 ps |
| CPU time | 2448.93 seconds |
| Started | May 30 04:25:14 PM PDT 24 |
| Finished | May 30 05:06:04 PM PDT 24 |
| Peak memory | 612088 kb |
| Host | smart-7cc160c8-035b-45b8-b01a-3be505f05619 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036209389 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq.2036209389 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.8592364 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 4922081686 ps |
| CPU time | 511.48 seconds |
| Started | May 30 04:23:50 PM PDT 24 |
| Finished | May 30 04:32:23 PM PDT 24 |
| Peak memory | 612012 kb |
| Host | smart-45cbebfe-842e-408d-8967-06edf0bc071b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8592364 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baud rate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_al t_clk_freq_low_speed.8592364 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.2953840348 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 78274972920 ps |
| CPU time | 12949.2 seconds |
| Started | May 30 04:23:46 PM PDT 24 |
| Finished | May 30 07:59:38 PM PDT 24 |
| Peak memory | 634460 kb |
| Host | smart-9f5fa24f-621d-4822-b7d3-d77e1d113e07 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=80_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2953840348 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_bootstrap.2953840348 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.4128398116 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 4367651848 ps |
| CPU time | 492.21 seconds |
| Started | May 30 04:24:05 PM PDT 24 |
| Finished | May 30 04:32:18 PM PDT 24 |
| Peak memory | 612208 kb |
| Host | smart-c4433711-b244-47d7-88ea-864114aa187d |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128398116 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.4128398116 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3455045123 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 3906203346 ps |
| CPU time | 729.51 seconds |
| Started | May 30 04:26:42 PM PDT 24 |
| Finished | May 30 04:38:53 PM PDT 24 |
| Peak memory | 609892 kb |
| Host | smart-6b336ca3-0915-498e-a836-aa86a1771d56 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455045123 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.3455045123 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.2574633375 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 4856988500 ps |
| CPU time | 842.37 seconds |
| Started | May 30 04:24:17 PM PDT 24 |
| Finished | May 30 04:38:21 PM PDT 24 |
| Peak memory | 612452 kb |
| Host | smart-517c33c3-dcab-4a5d-bf70-18f0d28554ac |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574633375 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.2574633375 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_dev.2444263562 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 10907383003 ps |
| CPU time | 1275.02 seconds |
| Started | May 30 04:29:58 PM PDT 24 |
| Finished | May 30 04:51:15 PM PDT 24 |
| Peak memory | 618680 kb |
| Host | smart-a1517c3f-f376-4b92-86e9-1efa03bbb3e3 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2444263562 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.2444263562 |
| Directory | /workspace/2.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_prod.3014921237 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 9089378370 ps |
| CPU time | 880.71 seconds |
| Started | May 30 04:29:22 PM PDT 24 |
| Finished | May 30 04:44:03 PM PDT 24 |
| Peak memory | 622652 kb |
| Host | smart-7262c7b7-5f5f-46df-b7d4-7bb91f3aef21 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014921237 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.3014921237 |
| Directory | /workspace/2.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_rma.1060512843 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 6935650097 ps |
| CPU time | 697.25 seconds |
| Started | May 30 04:29:53 PM PDT 24 |
| Finished | May 30 04:41:32 PM PDT 24 |
| Peak memory | 622644 kb |
| Host | smart-69fd15bd-9abd-4db7-bba1-e7c8a1a3ed32 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060512843 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_rma.1060512843 |
| Directory | /workspace/2.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_testunlock0.3650857213 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 3328893360 ps |
| CPU time | 241.7 seconds |
| Started | May 30 04:29:12 PM PDT 24 |
| Finished | May 30 04:33:15 PM PDT 24 |
| Peak memory | 615324 kb |
| Host | smart-c1a1ce73-b55a-431f-acfd-cc41b71a91b0 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3650857213 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_testunlock0.3650857213 |
| Directory | /workspace/2.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_dev.2124686160 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 14545700612 ps |
| CPU time | 3024.49 seconds |
| Started | May 30 04:36:28 PM PDT 24 |
| Finished | May 30 05:26:53 PM PDT 24 |
| Peak memory | 605060 kb |
| Host | smart-ce5a0b78-82d3-4483-adf6-d242610d55a5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124686160 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_dev.2124686160 |
| Directory | /workspace/2.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod.2556289381 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 14042259097 ps |
| CPU time | 3332.6 seconds |
| Started | May 30 04:36:12 PM PDT 24 |
| Finished | May 30 05:31:46 PM PDT 24 |
| Peak memory | 605320 kb |
| Host | smart-664bf8af-8590-4dcc-a7e8-5ac07cead69b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556289381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_prod.2556289381 |
| Directory | /workspace/2.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.1841485496 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 14272430416 ps |
| CPU time | 2895.15 seconds |
| Started | May 30 04:35:34 PM PDT 24 |
| Finished | May 30 05:23:50 PM PDT 24 |
| Peak memory | 605004 kb |
| Host | smart-07a171be-25b9-4592-b8f7-301f084eed48 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841485496 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.rom_e2e_asm_init_prod_end.1841485496 |
| Directory | /workspace/2.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_rma.3238484735 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 14669166760 ps |
| CPU time | 3562.27 seconds |
| Started | May 30 04:36:29 PM PDT 24 |
| Finished | May 30 05:35:53 PM PDT 24 |
| Peak memory | 605084 kb |
| Host | smart-ea67917c-4068-401f-8b48-8c49b91d1067 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238484735 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_rma.3238484735 |
| Directory | /workspace/2.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2784240597 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 11559528059 ps |
| CPU time | 2531.55 seconds |
| Started | May 30 04:37:16 PM PDT 24 |
| Finished | May 30 05:19:28 PM PDT 24 |
| Peak memory | 604032 kb |
| Host | smart-ab80b781-5258-40f2-846d-f93d4a7f072f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784240597 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.rom_e2e_asm_init_test_unlocked0.2784240597 |
| Directory | /workspace/2.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.442169891 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 14531753800 ps |
| CPU time | 3135.47 seconds |
| Started | May 30 04:39:24 PM PDT 24 |
| Finished | May 30 05:31:41 PM PDT 24 |
| Peak memory | 605392 kb |
| Host | smart-31d7b85c-a3f5-4d22-a1d9-d28d8afcb515 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442169891 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_ini t_rom_ext_invalid_meas.442169891 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.3289868665 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 15187131840 ps |
| CPU time | 3845.5 seconds |
| Started | May 30 04:36:29 PM PDT 24 |
| Finished | May 30 05:40:35 PM PDT 24 |
| Peak memory | 603904 kb |
| Host | smart-d7ee25da-16dc-4c27-b4c3-f623f3e4deb8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289868665 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_meas.3289868665 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.2892365017 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 14728091572 ps |
| CPU time | 3171.31 seconds |
| Started | May 30 04:37:29 PM PDT 24 |
| Finished | May 30 05:30:22 PM PDT 24 |
| Peak memory | 605344 kb |
| Host | smart-77461b79-aca5-4ab3-a86d-a9a7e01d1cef |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892365017 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext _no_meas.2892365017 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.2209171806 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 13673107624 ps |
| CPU time | 2747.56 seconds |
| Started | May 30 04:37:51 PM PDT 24 |
| Finished | May 30 05:23:39 PM PDT 24 |
| Peak memory | 604028 kb |
| Host | smart-5ab04c77-a860-4288-b0b1-a010a42e81d9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209171806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_ shutdown_exception_c.2209171806 |
| Directory | /workspace/2.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_output.2549357352 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 28874992850 ps |
| CPU time | 3372.76 seconds |
| Started | May 30 04:36:56 PM PDT 24 |
| Finished | May 30 05:33:10 PM PDT 24 |
| Peak memory | 606388 kb |
| Host | smart-146ab6ce-c170-4a42-962c-9a0396b0337e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549357352 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_output.2549357352 |
| Directory | /workspace/2.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_smoke.1658375147 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 14220427000 ps |
| CPU time | 3279.67 seconds |
| Started | May 30 04:33:43 PM PDT 24 |
| Finished | May 30 05:28:24 PM PDT 24 |
| Peak memory | 605292 kb |
| Host | smart-d6729e1e-f0f9-46ae-a961-4164e5ece741 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=1658375147 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.1658375147 |
| Directory | /workspace/2.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/2.rom_keymgr_functest.108151452 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 4986779260 ps |
| CPU time | 548.82 seconds |
| Started | May 30 04:31:37 PM PDT 24 |
| Finished | May 30 04:40:46 PM PDT 24 |
| Peak memory | 603876 kb |
| Host | smart-8c886cc3-9fb8-4dc4-ba9e-fb63e1cb00bc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108151452 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.rom_keymgr_functest.108151452 |
| Directory | /workspace/2.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/2.rom_volatile_raw_unlock.4788334 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 2337909753 ps |
| CPU time | 105.78 seconds |
| Started | May 30 04:30:24 PM PDT 24 |
| Finished | May 30 04:32:11 PM PDT 24 |
| Peak memory | 611548 kb |
| Host | smart-c6122f4f-5bf5-455f-aad4-37078e95f3ae |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4788334 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.4788334 |
| Directory | /workspace/2.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/21.chip_sw_all_escalation_resets.4179997097 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 5738184888 ps |
| CPU time | 667.38 seconds |
| Started | May 30 04:36:20 PM PDT 24 |
| Finished | May 30 04:47:28 PM PDT 24 |
| Peak memory | 611280 kb |
| Host | smart-ee96445a-b54f-4772-bf34-c7509658c36b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4179997097 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.4179997097 |
| Directory | /workspace/21.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/22.chip_sw_all_escalation_resets.2836937569 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 5504882880 ps |
| CPU time | 599.33 seconds |
| Started | May 30 04:36:56 PM PDT 24 |
| Finished | May 30 04:46:56 PM PDT 24 |
| Peak memory | 639240 kb |
| Host | smart-10f2e7ae-b3cd-4dd4-82fd-7e4e6d833304 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2836937569 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.2836937569 |
| Directory | /workspace/22.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3344055635 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 3406289536 ps |
| CPU time | 410.15 seconds |
| Started | May 30 04:35:31 PM PDT 24 |
| Finished | May 30 04:42:22 PM PDT 24 |
| Peak memory | 639464 kb |
| Host | smart-018870a0-fd9d-47ee-a910-9ba7db24f187 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344055635 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3344055635 |
| Directory | /workspace/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/28.chip_sw_all_escalation_resets.999545294 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 4970713644 ps |
| CPU time | 537.81 seconds |
| Started | May 30 04:35:32 PM PDT 24 |
| Finished | May 30 04:44:31 PM PDT 24 |
| Peak memory | 639404 kb |
| Host | smart-a9bf487a-56fb-4298-b3b2-c1c705a40bc3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 999545294 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.999545294 |
| Directory | /workspace/28.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/29.chip_sw_all_escalation_resets.2766632648 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 5174508344 ps |
| CPU time | 798.39 seconds |
| Started | May 30 04:35:13 PM PDT 24 |
| Finished | May 30 04:48:32 PM PDT 24 |
| Peak memory | 639564 kb |
| Host | smart-32888ad3-e5e6-4b9a-adec-e21455e47f27 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2766632648 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_all_escalation_resets.2766632648 |
| Directory | /workspace/29.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.4139947388 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 3299965568 ps |
| CPU time | 409.89 seconds |
| Started | May 30 04:33:31 PM PDT 24 |
| Finished | May 30 04:40:22 PM PDT 24 |
| Peak memory | 639696 kb |
| Host | smart-d871e28b-fa5b-41be-a5e1-9aa3653f7cdd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139947388 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_s w_alert_handler_lpg_sleep_mode_alerts.4139947388 |
| Directory | /workspace/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3556318837 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 7886698158 ps |
| CPU time | 577.97 seconds |
| Started | May 30 04:33:42 PM PDT 24 |
| Finished | May 30 04:43:20 PM PDT 24 |
| Peak memory | 604224 kb |
| Host | smart-cee29d03-6f92-484a-a8dc-63a6193ef1c5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3556318837 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3556318837 |
| Directory | /workspace/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.2235312379 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 16649489230 ps |
| CPU time | 3481.33 seconds |
| Started | May 30 04:32:38 PM PDT 24 |
| Finished | May 30 05:30:40 PM PDT 24 |
| Peak memory | 604120 kb |
| Host | smart-fcb57299-aaf0-41dd-8a4c-266b8e00dd4e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235312379 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 3.chip_sw_csrng_edn_concurrency.2235312379 |
| Directory | /workspace/3.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/3.chip_sw_data_integrity_escalation.3136260535 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 6322239110 ps |
| CPU time | 718.43 seconds |
| Started | May 30 04:35:48 PM PDT 24 |
| Finished | May 30 04:47:47 PM PDT 24 |
| Peak memory | 605252 kb |
| Host | smart-b67dbfe6-3efd-4059-8de0-d3a43ddf0e4a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3136260535 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.3136260535 |
| Directory | /workspace/3.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.246806446 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 9972875040 ps |
| CPU time | 1050.62 seconds |
| Started | May 30 04:34:21 PM PDT 24 |
| Finished | May 30 04:51:53 PM PDT 24 |
| Peak memory | 616288 kb |
| Host | smart-7a03b257-b79d-4fcb-9fe4-df73305b42b2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246806446 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 3.chip_sw_lc_ctrl_transition.246806446 |
| Directory | /workspace/3.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.1769863329 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 8091622634 ps |
| CPU time | 1373.85 seconds |
| Started | May 30 04:33:47 PM PDT 24 |
| Finished | May 30 04:56:41 PM PDT 24 |
| Peak memory | 612440 kb |
| Host | smart-44cca844-3ee6-4fae-b25f-726aa1b15ada |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1769863329 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.1769863329 |
| Directory | /workspace/3.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.2551403210 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 8609223537 ps |
| CPU time | 1703.41 seconds |
| Started | May 30 04:33:34 PM PDT 24 |
| Finished | May 30 05:01:59 PM PDT 24 |
| Peak memory | 613080 kb |
| Host | smart-01d843ac-8a02-45a8-8b64-ba42463d94b3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551403210 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq.2551403210 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4291170542 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 4129453528 ps |
| CPU time | 423.3 seconds |
| Started | May 30 04:34:30 PM PDT 24 |
| Finished | May 30 04:41:35 PM PDT 24 |
| Peak memory | 612048 kb |
| Host | smart-e4a82c03-dc7d-4c80-ada3-f6d6d3bd11bf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291170542 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.4291170542 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.767410619 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 4566737816 ps |
| CPU time | 607.2 seconds |
| Started | May 30 04:36:02 PM PDT 24 |
| Finished | May 30 04:46:10 PM PDT 24 |
| Peak memory | 612520 kb |
| Host | smart-22e1f056-230f-4a46-b04f-a1c31977a47f |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767410619 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.767410619 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.4200245383 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 3870931090 ps |
| CPU time | 579.06 seconds |
| Started | May 30 04:31:53 PM PDT 24 |
| Finished | May 30 04:41:33 PM PDT 24 |
| Peak memory | 612168 kb |
| Host | smart-09dd34c1-cd03-462b-84fe-a72799df2b03 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200245383 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.4200245383 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.539887550 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 4245011218 ps |
| CPU time | 645.95 seconds |
| Started | May 30 04:32:49 PM PDT 24 |
| Finished | May 30 04:43:36 PM PDT 24 |
| Peak memory | 612236 kb |
| Host | smart-63889baa-ddf9-4d36-aeb8-53f285f809f4 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539887550 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.539887550 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_dev.579915484 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 10629253049 ps |
| CPU time | 941.7 seconds |
| Started | May 30 04:34:03 PM PDT 24 |
| Finished | May 30 04:49:48 PM PDT 24 |
| Peak memory | 618924 kb |
| Host | smart-3dfc5321-90b3-46f3-8d9d-363274fbfb51 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=579915484 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.579915484 |
| Directory | /workspace/3.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_prod.3978497717 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 2602720501 ps |
| CPU time | 123.43 seconds |
| Started | May 30 04:32:49 PM PDT 24 |
| Finished | May 30 04:34:53 PM PDT 24 |
| Peak memory | 614812 kb |
| Host | smart-a9c69079-8e4e-4ff5-b4f2-6a61d024515c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978497717 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.3978497717 |
| Directory | /workspace/3.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_rma.1868032434 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 4899980191 ps |
| CPU time | 524.72 seconds |
| Started | May 30 04:31:54 PM PDT 24 |
| Finished | May 30 04:40:39 PM PDT 24 |
| Peak memory | 615040 kb |
| Host | smart-852a12cf-f519-4fce-80b6-9f1ee29e617d |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868032434 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_rma.1868032434 |
| Directory | /workspace/3.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_testunlock0.4081206287 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 5649145861 ps |
| CPU time | 521.36 seconds |
| Started | May 30 04:32:12 PM PDT 24 |
| Finished | May 30 04:40:54 PM PDT 24 |
| Peak memory | 615264 kb |
| Host | smart-349097ac-c38e-4bb5-aad6-21f447995089 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4081206287 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_testunlock0.4081206287 |
| Directory | /workspace/3.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/30.chip_sw_all_escalation_resets.2740082366 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 4386354304 ps |
| CPU time | 646.91 seconds |
| Started | May 30 04:36:15 PM PDT 24 |
| Finished | May 30 04:47:03 PM PDT 24 |
| Peak memory | 639980 kb |
| Host | smart-b373ba77-f7ab-413b-9eb0-ecd4a07f56e0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2740082366 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.2740082366 |
| Directory | /workspace/30.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/31.chip_sw_all_escalation_resets.4073281017 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 5760967250 ps |
| CPU time | 660.32 seconds |
| Started | May 30 04:36:33 PM PDT 24 |
| Finished | May 30 04:47:34 PM PDT 24 |
| Peak memory | 640028 kb |
| Host | smart-4f517872-c45c-40ee-8f81-67f801b29917 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4073281017 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_all_escalation_resets.4073281017 |
| Directory | /workspace/31.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/33.chip_sw_all_escalation_resets.449966064 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 5074982880 ps |
| CPU time | 655.84 seconds |
| Started | May 30 04:38:03 PM PDT 24 |
| Finished | May 30 04:49:02 PM PDT 24 |
| Peak memory | 639476 kb |
| Host | smart-9fa2f396-9590-4ac4-9a19-6f0dbba8c56c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 449966064 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.449966064 |
| Directory | /workspace/33.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3926125560 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 3711682616 ps |
| CPU time | 413.34 seconds |
| Started | May 30 04:37:11 PM PDT 24 |
| Finished | May 30 04:44:05 PM PDT 24 |
| Peak memory | 639508 kb |
| Host | smart-79e8f9bd-88c5-4b22-91eb-df92a5d96afa |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926125560 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3926125560 |
| Directory | /workspace/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/34.chip_sw_all_escalation_resets.1146478672 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 6004276488 ps |
| CPU time | 700.23 seconds |
| Started | May 30 04:36:22 PM PDT 24 |
| Finished | May 30 04:48:04 PM PDT 24 |
| Peak memory | 639580 kb |
| Host | smart-91b5e365-239c-4c5f-aabf-107e1985cf6e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1146478672 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.1146478672 |
| Directory | /workspace/34.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3234231071 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 3648618992 ps |
| CPU time | 375.02 seconds |
| Started | May 30 04:38:27 PM PDT 24 |
| Finished | May 30 04:44:43 PM PDT 24 |
| Peak memory | 639484 kb |
| Host | smart-a6132481-59de-4f67-a12d-f9b4908b2612 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234231071 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3234231071 |
| Directory | /workspace/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/35.chip_sw_all_escalation_resets.1526007763 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 6052770216 ps |
| CPU time | 622.86 seconds |
| Started | May 30 04:36:26 PM PDT 24 |
| Finished | May 30 04:46:50 PM PDT 24 |
| Peak memory | 639304 kb |
| Host | smart-f2cac941-fc62-4e00-854d-30a4ab7a5510 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1526007763 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.1526007763 |
| Directory | /workspace/35.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1608934383 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 4147862520 ps |
| CPU time | 310.74 seconds |
| Started | May 30 04:38:18 PM PDT 24 |
| Finished | May 30 04:43:29 PM PDT 24 |
| Peak memory | 639616 kb |
| Host | smart-f4336c1e-f1be-4c98-a0a2-e83ab5ef00cc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608934383 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1608934383 |
| Directory | /workspace/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/37.chip_sw_all_escalation_resets.4264299679 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 5202818404 ps |
| CPU time | 626.6 seconds |
| Started | May 30 04:36:43 PM PDT 24 |
| Finished | May 30 04:47:11 PM PDT 24 |
| Peak memory | 639324 kb |
| Host | smart-73a547b2-cd87-4f17-9cb7-29c6cd00a175 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4264299679 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.4264299679 |
| Directory | /workspace/37.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1498269827 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 3038348120 ps |
| CPU time | 345.44 seconds |
| Started | May 30 04:36:48 PM PDT 24 |
| Finished | May 30 04:42:34 PM PDT 24 |
| Peak memory | 639452 kb |
| Host | smart-4f1b77af-302f-48c4-b45b-6715d944c7ad |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498269827 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1498269827 |
| Directory | /workspace/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/4.chip_sw_all_escalation_resets.3359062827 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 4703807166 ps |
| CPU time | 643.79 seconds |
| Started | May 30 04:34:00 PM PDT 24 |
| Finished | May 30 04:44:47 PM PDT 24 |
| Peak memory | 639756 kb |
| Host | smart-3e4382dd-df42-4ed2-8e12-12f795e49da4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3359062827 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.3359062827 |
| Directory | /workspace/4.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2911847588 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 6397988560 ps |
| CPU time | 411.47 seconds |
| Started | May 30 04:33:53 PM PDT 24 |
| Finished | May 30 04:40:46 PM PDT 24 |
| Peak memory | 604440 kb |
| Host | smart-ef27de54-ed96-4878-b6c7-ecebc1014fc5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2911847588 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2911847588 |
| Directory | /workspace/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.3249376089 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 27237030788 ps |
| CPU time | 5732.23 seconds |
| Started | May 30 04:35:25 PM PDT 24 |
| Finished | May 30 06:10:59 PM PDT 24 |
| Peak memory | 604144 kb |
| Host | smart-6292d84a-6e12-4fe6-aa49-fe00560608a3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249376089 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 4.chip_sw_csrng_edn_concurrency.3249376089 |
| Directory | /workspace/4.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.2920019496 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 13596381521 ps |
| CPU time | 1151.97 seconds |
| Started | May 30 04:33:09 PM PDT 24 |
| Finished | May 30 04:52:22 PM PDT 24 |
| Peak memory | 615672 kb |
| Host | smart-566bc3c8-d482-45f7-8a2f-23d19fc6d9f3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920019496 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 4.chip_sw_lc_ctrl_transition.2920019496 |
| Directory | /workspace/4.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2121146525 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 8621605736 ps |
| CPU time | 1443.65 seconds |
| Started | May 30 04:33:12 PM PDT 24 |
| Finished | May 30 04:57:17 PM PDT 24 |
| Peak memory | 612496 kb |
| Host | smart-f42efc69-7e1b-4d4b-9169-1afe39dba0c3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2121146525 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.2121146525 |
| Directory | /workspace/4.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx.2619241032 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 4112436840 ps |
| CPU time | 663.97 seconds |
| Started | May 30 04:33:45 PM PDT 24 |
| Finished | May 30 04:44:50 PM PDT 24 |
| Peak memory | 612192 kb |
| Host | smart-20e6c7aa-b2c9-43b2-b858-ed6c7501b77b |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619241032 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.2619241032 |
| Directory | /workspace/4.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.4169118404 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 8020041574 ps |
| CPU time | 1456.44 seconds |
| Started | May 30 04:34:25 PM PDT 24 |
| Finished | May 30 04:58:43 PM PDT 24 |
| Peak memory | 612012 kb |
| Host | smart-dfb5777e-6f15-4c22-8713-159b9790b633 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169118404 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq.4169118404 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.1809542918 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 4401798168 ps |
| CPU time | 646.37 seconds |
| Started | May 30 04:32:38 PM PDT 24 |
| Finished | May 30 04:43:26 PM PDT 24 |
| Peak memory | 612244 kb |
| Host | smart-bf83bda5-a903-44a7-8ee5-d8c92e1fa7f2 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809542918 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.1809542918 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.3652636565 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 4426706292 ps |
| CPU time | 572.28 seconds |
| Started | May 30 04:32:53 PM PDT 24 |
| Finished | May 30 04:42:26 PM PDT 24 |
| Peak memory | 612512 kb |
| Host | smart-d699eea1-292a-4849-b470-7214b4796595 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652636565 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.3652636565 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.623198561 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 4253324712 ps |
| CPU time | 613.96 seconds |
| Started | May 30 04:33:08 PM PDT 24 |
| Finished | May 30 04:43:22 PM PDT 24 |
| Peak memory | 609956 kb |
| Host | smart-501bcce7-28e8-4fbb-8b98-cf538c660f6b |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623198561 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.623198561 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_dev.628414523 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 3151357501 ps |
| CPU time | 201.52 seconds |
| Started | May 30 04:31:32 PM PDT 24 |
| Finished | May 30 04:34:54 PM PDT 24 |
| Peak memory | 614808 kb |
| Host | smart-3e780e69-d621-4460-a7e0-ace1c23a3b07 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=628414523 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.628414523 |
| Directory | /workspace/4.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_prod.65359714 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 6542692373 ps |
| CPU time | 707.33 seconds |
| Started | May 30 04:31:55 PM PDT 24 |
| Finished | May 30 04:43:43 PM PDT 24 |
| Peak memory | 615272 kb |
| Host | smart-58f8981a-83a2-48d2-9724-7e000e389c46 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65359714 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.65359714 |
| Directory | /workspace/4.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_rma.2646686232 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 9695809102 ps |
| CPU time | 842.43 seconds |
| Started | May 30 04:31:52 PM PDT 24 |
| Finished | May 30 04:45:55 PM PDT 24 |
| Peak memory | 615212 kb |
| Host | smart-210abda6-709b-4a35-bfe4-7f163df758dc |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646686232 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_rma.2646686232 |
| Directory | /workspace/4.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_testunlock0.1336580219 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 2582082769 ps |
| CPU time | 143.87 seconds |
| Started | May 30 04:31:52 PM PDT 24 |
| Finished | May 30 04:34:17 PM PDT 24 |
| Peak memory | 614996 kb |
| Host | smart-5ff8e7cc-b663-441c-aa42-0c4cf67182ad |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1336580219 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_testunlock0.1336580219 |
| Directory | /workspace/4.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/40.chip_sw_all_escalation_resets.670476672 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 5735930712 ps |
| CPU time | 742.36 seconds |
| Started | May 30 04:38:01 PM PDT 24 |
| Finished | May 30 04:50:25 PM PDT 24 |
| Peak memory | 611288 kb |
| Host | smart-0a3fdc2e-80c9-4b14-aac1-d7b41c99c991 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 670476672 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.670476672 |
| Directory | /workspace/40.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3912521819 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 3658972500 ps |
| CPU time | 387.84 seconds |
| Started | May 30 04:38:19 PM PDT 24 |
| Finished | May 30 04:44:48 PM PDT 24 |
| Peak memory | 639548 kb |
| Host | smart-91d7e38f-596b-4a34-ba21-c0c1068c1dae |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912521819 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3912521819 |
| Directory | /workspace/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.533558219 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 3698415276 ps |
| CPU time | 384.11 seconds |
| Started | May 30 04:37:14 PM PDT 24 |
| Finished | May 30 04:43:39 PM PDT 24 |
| Peak memory | 639816 kb |
| Host | smart-9a53bd13-d389-4023-9fc6-9a2443370a95 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533558219 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_s w_alert_handler_lpg_sleep_mode_alerts.533558219 |
| Directory | /workspace/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.852337591 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 3268103624 ps |
| CPU time | 391.91 seconds |
| Started | May 30 04:38:00 PM PDT 24 |
| Finished | May 30 04:44:34 PM PDT 24 |
| Peak memory | 638268 kb |
| Host | smart-2f51febd-1eab-4ff4-b035-cc9b61f6147b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852337591 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_s w_alert_handler_lpg_sleep_mode_alerts.852337591 |
| Directory | /workspace/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/43.chip_sw_all_escalation_resets.3353671319 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 5051036024 ps |
| CPU time | 551.68 seconds |
| Started | May 30 04:37:33 PM PDT 24 |
| Finished | May 30 04:46:46 PM PDT 24 |
| Peak memory | 639784 kb |
| Host | smart-98065f9c-76c3-4efe-9e4c-3783d0f4c292 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3353671319 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.3353671319 |
| Directory | /workspace/43.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/44.chip_sw_all_escalation_resets.667622741 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 5750282040 ps |
| CPU time | 659.75 seconds |
| Started | May 30 04:39:10 PM PDT 24 |
| Finished | May 30 04:50:10 PM PDT 24 |
| Peak memory | 639664 kb |
| Host | smart-675c7ee9-cb18-4dd0-96b6-3700f972374a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 667622741 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.667622741 |
| Directory | /workspace/44.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/45.chip_sw_all_escalation_resets.4013848968 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 6112739800 ps |
| CPU time | 580.54 seconds |
| Started | May 30 04:37:35 PM PDT 24 |
| Finished | May 30 04:47:16 PM PDT 24 |
| Peak memory | 639372 kb |
| Host | smart-55aeb5d8-1579-41a2-81e1-3b4f61801223 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4013848968 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.4013848968 |
| Directory | /workspace/45.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2599982848 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 3476661360 ps |
| CPU time | 360.23 seconds |
| Started | May 30 04:41:06 PM PDT 24 |
| Finished | May 30 04:47:06 PM PDT 24 |
| Peak memory | 639696 kb |
| Host | smart-eaa0a7a3-8b42-4ebf-9f71-b5a09cca47f9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599982848 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2599982848 |
| Directory | /workspace/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2003134786 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 3524421696 ps |
| CPU time | 310.62 seconds |
| Started | May 30 04:40:46 PM PDT 24 |
| Finished | May 30 04:45:58 PM PDT 24 |
| Peak memory | 638180 kb |
| Host | smart-6ebaf1c4-3cd2-4088-8b85-a82258fda7cb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003134786 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2003134786 |
| Directory | /workspace/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/47.chip_sw_all_escalation_resets.2171527125 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 4899021120 ps |
| CPU time | 645.66 seconds |
| Started | May 30 04:40:48 PM PDT 24 |
| Finished | May 30 04:51:34 PM PDT 24 |
| Peak memory | 639468 kb |
| Host | smart-bf85015c-d865-4c54-a538-ffde16704697 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2171527125 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.2171527125 |
| Directory | /workspace/47.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/48.chip_sw_all_escalation_resets.2405595339 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 5438834400 ps |
| CPU time | 524.71 seconds |
| Started | May 30 04:42:09 PM PDT 24 |
| Finished | May 30 04:50:54 PM PDT 24 |
| Peak memory | 639536 kb |
| Host | smart-09cf3c20-28a2-4165-a2e1-26fea5a9a571 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2405595339 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.2405595339 |
| Directory | /workspace/48.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.118168097 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 3311948930 ps |
| CPU time | 338.79 seconds |
| Started | May 30 04:40:36 PM PDT 24 |
| Finished | May 30 04:46:16 PM PDT 24 |
| Peak memory | 639504 kb |
| Host | smart-617fef87-2a60-4e6a-bb11-b5a0976eb3e2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118168097 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_s w_alert_handler_lpg_sleep_mode_alerts.118168097 |
| Directory | /workspace/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/49.chip_sw_all_escalation_resets.4123931658 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 5455045008 ps |
| CPU time | 520.12 seconds |
| Started | May 30 04:41:09 PM PDT 24 |
| Finished | May 30 04:49:50 PM PDT 24 |
| Peak memory | 611360 kb |
| Host | smart-c78559e1-da6a-4eda-b822-43aa0a6141bc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4123931658 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.4123931658 |
| Directory | /workspace/49.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2394171825 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 4343410580 ps |
| CPU time | 423.75 seconds |
| Started | May 30 04:35:00 PM PDT 24 |
| Finished | May 30 04:42:05 PM PDT 24 |
| Peak memory | 639988 kb |
| Host | smart-a85df483-3489-4d0e-b612-d617e60e4756 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394171825 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_s w_alert_handler_lpg_sleep_mode_alerts.2394171825 |
| Directory | /workspace/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.1694046912 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 14565677438 ps |
| CPU time | 3450.4 seconds |
| Started | May 30 04:35:14 PM PDT 24 |
| Finished | May 30 05:32:46 PM PDT 24 |
| Peak memory | 604076 kb |
| Host | smart-f6e34be4-e3d6-4437-939e-62bebb317b15 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694046912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 5.chip_sw_csrng_edn_concurrency.1694046912 |
| Directory | /workspace/5.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/5.chip_sw_data_integrity_escalation.965057168 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 6150579410 ps |
| CPU time | 877.55 seconds |
| Started | May 30 04:32:58 PM PDT 24 |
| Finished | May 30 04:47:36 PM PDT 24 |
| Peak memory | 604504 kb |
| Host | smart-509d6d16-4f99-4c18-9f13-e2cc38e6eb42 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=965057168 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.965057168 |
| Directory | /workspace/5.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.522218117 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 11514884040 ps |
| CPU time | 930.43 seconds |
| Started | May 30 04:35:06 PM PDT 24 |
| Finished | May 30 04:50:38 PM PDT 24 |
| Peak memory | 615676 kb |
| Host | smart-55e77718-4c2e-4ac6-86c8-954e8bc954b2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522218117 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 5.chip_sw_lc_ctrl_transition.522218117 |
| Directory | /workspace/5.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.2033805935 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 12878015912 ps |
| CPU time | 2635.49 seconds |
| Started | May 30 04:34:31 PM PDT 24 |
| Finished | May 30 05:18:29 PM PDT 24 |
| Peak memory | 612456 kb |
| Host | smart-e9818c46-4d72-49c4-9f31-259d59530711 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2033805935 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.2033805935 |
| Directory | /workspace/5.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1573056527 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 4210097192 ps |
| CPU time | 398.74 seconds |
| Started | May 30 04:42:11 PM PDT 24 |
| Finished | May 30 04:48:50 PM PDT 24 |
| Peak memory | 639532 kb |
| Host | smart-5167bf5d-0263-4287-af65-429d1285b765 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573056527 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1573056527 |
| Directory | /workspace/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/50.chip_sw_all_escalation_resets.3701781586 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 5104138170 ps |
| CPU time | 525.4 seconds |
| Started | May 30 04:40:59 PM PDT 24 |
| Finished | May 30 04:49:45 PM PDT 24 |
| Peak memory | 639332 kb |
| Host | smart-69779f0c-e406-4d36-bb9d-007afea8dc32 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3701781586 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.3701781586 |
| Directory | /workspace/50.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/51.chip_sw_all_escalation_resets.1335607681 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 4813404724 ps |
| CPU time | 497.49 seconds |
| Started | May 30 04:41:16 PM PDT 24 |
| Finished | May 30 04:49:34 PM PDT 24 |
| Peak memory | 639332 kb |
| Host | smart-ccd7e47d-11f8-412a-85ed-c37b0461f351 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1335607681 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.1335607681 |
| Directory | /workspace/51.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.289435210 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 3631612706 ps |
| CPU time | 400.45 seconds |
| Started | May 30 04:41:20 PM PDT 24 |
| Finished | May 30 04:48:01 PM PDT 24 |
| Peak memory | 639512 kb |
| Host | smart-c511e940-d20e-4d6c-8e49-d9be01d94180 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289435210 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_s w_alert_handler_lpg_sleep_mode_alerts.289435210 |
| Directory | /workspace/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/53.chip_sw_all_escalation_resets.2713127627 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 3806136600 ps |
| CPU time | 439.04 seconds |
| Started | May 30 04:40:40 PM PDT 24 |
| Finished | May 30 04:48:00 PM PDT 24 |
| Peak memory | 638096 kb |
| Host | smart-e072919f-c66c-4ed1-8598-7364838c16c8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2713127627 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.2713127627 |
| Directory | /workspace/53.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1969176013 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 3325301734 ps |
| CPU time | 397.18 seconds |
| Started | May 30 04:40:10 PM PDT 24 |
| Finished | May 30 04:46:48 PM PDT 24 |
| Peak memory | 638240 kb |
| Host | smart-316144b6-8757-4ded-92c8-dfef5d25faa7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969176013 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1969176013 |
| Directory | /workspace/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/54.chip_sw_all_escalation_resets.4162523593 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 6441443650 ps |
| CPU time | 640.7 seconds |
| Started | May 30 04:42:37 PM PDT 24 |
| Finished | May 30 04:53:21 PM PDT 24 |
| Peak memory | 639764 kb |
| Host | smart-32118f02-4fb2-4b05-8337-8a2a84f1647e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4162523593 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.4162523593 |
| Directory | /workspace/54.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3763306812 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 3162268264 ps |
| CPU time | 353.1 seconds |
| Started | May 30 04:42:41 PM PDT 24 |
| Finished | May 30 04:48:40 PM PDT 24 |
| Peak memory | 613456 kb |
| Host | smart-56807c51-b496-4a39-9b68-884c07beecbf |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763306812 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3763306812 |
| Directory | /workspace/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.2472153445 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 3842480414 ps |
| CPU time | 397.48 seconds |
| Started | May 30 04:40:15 PM PDT 24 |
| Finished | May 30 04:46:53 PM PDT 24 |
| Peak memory | 639452 kb |
| Host | smart-0e0e0950-e3a3-4671-8578-b43e57188368 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472153445 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2472153445 |
| Directory | /workspace/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/57.chip_sw_all_escalation_resets.1554648331 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 5773879962 ps |
| CPU time | 668.89 seconds |
| Started | May 30 04:40:28 PM PDT 24 |
| Finished | May 30 04:51:37 PM PDT 24 |
| Peak memory | 605380 kb |
| Host | smart-6d68deff-94d8-442f-8831-9477f39d192c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1554648331 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.1554648331 |
| Directory | /workspace/57.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2879292842 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 3717348180 ps |
| CPU time | 387.74 seconds |
| Started | May 30 04:40:07 PM PDT 24 |
| Finished | May 30 04:46:35 PM PDT 24 |
| Peak memory | 639592 kb |
| Host | smart-e220aa59-7675-45d6-9c34-0091e7ea19ff |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879292842 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2879292842 |
| Directory | /workspace/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1935232806 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 3974264180 ps |
| CPU time | 378.99 seconds |
| Started | May 30 04:41:03 PM PDT 24 |
| Finished | May 30 04:47:23 PM PDT 24 |
| Peak memory | 639464 kb |
| Host | smart-22934ed9-5a65-43ce-8b56-cb2b9a90d4d6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935232806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1935232806 |
| Directory | /workspace/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.627715166 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 3444079420 ps |
| CPU time | 432.68 seconds |
| Started | May 30 04:33:55 PM PDT 24 |
| Finished | May 30 04:41:10 PM PDT 24 |
| Peak memory | 640052 kb |
| Host | smart-a4f5a4ac-6760-4d8d-bea5-a4845b5b7442 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627715166 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw _alert_handler_lpg_sleep_mode_alerts.627715166 |
| Directory | /workspace/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/6.chip_sw_all_escalation_resets.1905446006 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 4937459428 ps |
| CPU time | 646.21 seconds |
| Started | May 30 04:33:34 PM PDT 24 |
| Finished | May 30 04:44:22 PM PDT 24 |
| Peak memory | 639392 kb |
| Host | smart-7988cfb0-669a-4d41-80d1-59ac84ff2f22 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1905446006 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.1905446006 |
| Directory | /workspace/6.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.260161271 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 10939387038 ps |
| CPU time | 2182.61 seconds |
| Started | May 30 04:34:51 PM PDT 24 |
| Finished | May 30 05:11:15 PM PDT 24 |
| Peak memory | 604096 kb |
| Host | smart-6bc026aa-a506-41aa-bdb5-9e1e72dfb8ba |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260161271 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_csrng_edn_concurrency.260161271 |
| Directory | /workspace/6.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.1943915753 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 11734492610 ps |
| CPU time | 1184.94 seconds |
| Started | May 30 04:34:05 PM PDT 24 |
| Finished | May 30 04:53:53 PM PDT 24 |
| Peak memory | 615644 kb |
| Host | smart-2a8fd26d-faa6-41f5-8045-88d2565585ef |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943915753 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 6.chip_sw_lc_ctrl_transition.1943915753 |
| Directory | /workspace/6.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2343072930 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 4449705948 ps |
| CPU time | 688.59 seconds |
| Started | May 30 04:34:38 PM PDT 24 |
| Finished | May 30 04:46:08 PM PDT 24 |
| Peak memory | 611996 kb |
| Host | smart-2c6b36d4-ea81-4d53-9549-4abe986a5825 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2343072930 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.2343072930 |
| Directory | /workspace/6.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1688793627 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 4078290368 ps |
| CPU time | 300.63 seconds |
| Started | May 30 04:41:20 PM PDT 24 |
| Finished | May 30 04:46:21 PM PDT 24 |
| Peak memory | 639620 kb |
| Host | smart-93274c55-55fb-4415-82e8-f256288fad61 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688793627 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1688793627 |
| Directory | /workspace/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/60.chip_sw_all_escalation_resets.1908387921 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 6056486130 ps |
| CPU time | 480.14 seconds |
| Started | May 30 04:41:48 PM PDT 24 |
| Finished | May 30 04:49:49 PM PDT 24 |
| Peak memory | 639840 kb |
| Host | smart-655a1e8a-fde7-4016-b0aa-9298aa569616 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1908387921 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.1908387921 |
| Directory | /workspace/60.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.4077856300 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 3404934470 ps |
| CPU time | 379.84 seconds |
| Started | May 30 04:40:54 PM PDT 24 |
| Finished | May 30 04:47:15 PM PDT 24 |
| Peak memory | 639504 kb |
| Host | smart-16705dcc-c949-4a73-bf34-98a9a3c26f12 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077856300 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4077856300 |
| Directory | /workspace/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2344909956 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 4156175760 ps |
| CPU time | 374.39 seconds |
| Started | May 30 04:41:49 PM PDT 24 |
| Finished | May 30 04:48:04 PM PDT 24 |
| Peak memory | 639560 kb |
| Host | smart-6012e3f3-790e-4fcb-909d-6f246ae43ca4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344909956 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2344909956 |
| Directory | /workspace/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.78759527 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 3563121792 ps |
| CPU time | 424.85 seconds |
| Started | May 30 04:42:47 PM PDT 24 |
| Finished | May 30 04:49:59 PM PDT 24 |
| Peak memory | 639520 kb |
| Host | smart-bd4ea311-4a34-4e75-80ff-706f65ca3d72 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78759527 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw _alert_handler_lpg_sleep_mode_alerts.78759527 |
| Directory | /workspace/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/64.chip_sw_all_escalation_resets.2757032842 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 4995387232 ps |
| CPU time | 555.54 seconds |
| Started | May 30 04:42:21 PM PDT 24 |
| Finished | May 30 04:51:37 PM PDT 24 |
| Peak memory | 639552 kb |
| Host | smart-5ec5c1ea-21c0-43fd-8a68-be944d567997 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2757032842 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.2757032842 |
| Directory | /workspace/64.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1278270783 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 4197789060 ps |
| CPU time | 383.85 seconds |
| Started | May 30 04:41:48 PM PDT 24 |
| Finished | May 30 04:48:12 PM PDT 24 |
| Peak memory | 639504 kb |
| Host | smart-a5567f3b-355e-4a28-a885-9daef65f8fda |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278270783 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1278270783 |
| Directory | /workspace/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/65.chip_sw_all_escalation_resets.2778484999 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 4652474236 ps |
| CPU time | 660.84 seconds |
| Started | May 30 04:42:33 PM PDT 24 |
| Finished | May 30 04:53:34 PM PDT 24 |
| Peak memory | 639756 kb |
| Host | smart-e4437598-8985-49be-86d3-6b03b23816be |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2778484999 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.2778484999 |
| Directory | /workspace/65.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/66.chip_sw_all_escalation_resets.4191121714 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 5280533516 ps |
| CPU time | 642.3 seconds |
| Started | May 30 04:42:10 PM PDT 24 |
| Finished | May 30 04:52:53 PM PDT 24 |
| Peak memory | 640724 kb |
| Host | smart-62869d8f-1e71-4431-9a30-48b46aa41254 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4191121714 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.4191121714 |
| Directory | /workspace/66.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.133507767 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 3473610940 ps |
| CPU time | 381.97 seconds |
| Started | May 30 04:42:35 PM PDT 24 |
| Finished | May 30 04:48:57 PM PDT 24 |
| Peak memory | 638436 kb |
| Host | smart-ffcd17d6-052f-45d9-837d-e3e097896234 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133507767 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_s w_alert_handler_lpg_sleep_mode_alerts.133507767 |
| Directory | /workspace/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1531397496 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 3690044828 ps |
| CPU time | 391.3 seconds |
| Started | May 30 04:41:38 PM PDT 24 |
| Finished | May 30 04:48:10 PM PDT 24 |
| Peak memory | 611320 kb |
| Host | smart-f8c7552a-ffff-4714-b2fb-29ca5611af58 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531397496 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1531397496 |
| Directory | /workspace/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/69.chip_sw_all_escalation_resets.4195840523 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 4228491484 ps |
| CPU time | 537.71 seconds |
| Started | May 30 04:41:09 PM PDT 24 |
| Finished | May 30 04:50:07 PM PDT 24 |
| Peak memory | 639252 kb |
| Host | smart-10505d4e-c438-4338-a53c-70c8d15c093b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4195840523 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.4195840523 |
| Directory | /workspace/69.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1115583381 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 3385716206 ps |
| CPU time | 474.08 seconds |
| Started | May 30 04:33:22 PM PDT 24 |
| Finished | May 30 04:41:17 PM PDT 24 |
| Peak memory | 639448 kb |
| Host | smart-78c7bffc-9d5b-45c4-b62c-800b0acf07ab |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115583381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_s w_alert_handler_lpg_sleep_mode_alerts.1115583381 |
| Directory | /workspace/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.3791805169 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 16397304532 ps |
| CPU time | 3164.35 seconds |
| Started | May 30 04:34:03 PM PDT 24 |
| Finished | May 30 05:26:50 PM PDT 24 |
| Peak memory | 603788 kb |
| Host | smart-cc9703dc-a6c1-4eac-9849-2dbe2f20178f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791805169 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 7.chip_sw_csrng_edn_concurrency.3791805169 |
| Directory | /workspace/7.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.309576589 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 5208796369 ps |
| CPU time | 433.52 seconds |
| Started | May 30 04:33:29 PM PDT 24 |
| Finished | May 30 04:40:43 PM PDT 24 |
| Peak memory | 615652 kb |
| Host | smart-75524aaf-9a3f-47ac-94c7-efba6383c2f7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309576589 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 7.chip_sw_lc_ctrl_transition.309576589 |
| Directory | /workspace/7.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3727802378 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 4373084344 ps |
| CPU time | 707.75 seconds |
| Started | May 30 04:32:58 PM PDT 24 |
| Finished | May 30 04:44:47 PM PDT 24 |
| Peak memory | 612444 kb |
| Host | smart-1e8e4307-d385-43ef-8f31-d6dede8ba80a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3727802378 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.3727802378 |
| Directory | /workspace/7.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3386945158 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 3484000190 ps |
| CPU time | 283.11 seconds |
| Started | May 30 04:41:30 PM PDT 24 |
| Finished | May 30 04:46:14 PM PDT 24 |
| Peak memory | 639576 kb |
| Host | smart-9245bedc-4c3b-4544-ba4b-87e41978bfc4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386945158 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3386945158 |
| Directory | /workspace/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/70.chip_sw_all_escalation_resets.802552954 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 5217112620 ps |
| CPU time | 604.43 seconds |
| Started | May 30 04:42:47 PM PDT 24 |
| Finished | May 30 04:52:59 PM PDT 24 |
| Peak memory | 611376 kb |
| Host | smart-7a21dc91-dffd-4715-9e26-79d4167a0623 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 802552954 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.802552954 |
| Directory | /workspace/70.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1436865057 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 4084810092 ps |
| CPU time | 338.31 seconds |
| Started | May 30 04:43:55 PM PDT 24 |
| Finished | May 30 04:49:34 PM PDT 24 |
| Peak memory | 639636 kb |
| Host | smart-42534824-9b7b-4e88-a547-8d3d481f534c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436865057 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1436865057 |
| Directory | /workspace/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2503077085 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 4065594448 ps |
| CPU time | 309.33 seconds |
| Started | May 30 04:41:33 PM PDT 24 |
| Finished | May 30 04:46:44 PM PDT 24 |
| Peak memory | 640028 kb |
| Host | smart-e924e64f-c61b-411e-94c3-5a92403df132 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503077085 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2503077085 |
| Directory | /workspace/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/73.chip_sw_all_escalation_resets.168091671 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 5804368392 ps |
| CPU time | 590.68 seconds |
| Started | May 30 04:44:21 PM PDT 24 |
| Finished | May 30 04:54:12 PM PDT 24 |
| Peak memory | 640608 kb |
| Host | smart-3dfd252c-bdf1-40b4-964d-fac607b44b4d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 168091671 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.168091671 |
| Directory | /workspace/73.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/74.chip_sw_all_escalation_resets.447260656 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 5922714846 ps |
| CPU time | 566.89 seconds |
| Started | May 30 04:41:51 PM PDT 24 |
| Finished | May 30 04:51:19 PM PDT 24 |
| Peak memory | 611304 kb |
| Host | smart-79355bcd-6a17-40c3-bb2a-245c7ab03db6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 447260656 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.447260656 |
| Directory | /workspace/74.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2894019064 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 3175612210 ps |
| CPU time | 323.82 seconds |
| Started | May 30 04:41:47 PM PDT 24 |
| Finished | May 30 04:47:12 PM PDT 24 |
| Peak memory | 639500 kb |
| Host | smart-8631b33d-c088-468e-ae43-ae0afccd2e88 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894019064 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2894019064 |
| Directory | /workspace/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/75.chip_sw_all_escalation_resets.1620831390 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 5553778688 ps |
| CPU time | 588.83 seconds |
| Started | May 30 04:41:57 PM PDT 24 |
| Finished | May 30 04:51:46 PM PDT 24 |
| Peak memory | 639392 kb |
| Host | smart-afdc38f1-32c7-4f9c-a18b-e3139af4373c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1620831390 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.1620831390 |
| Directory | /workspace/75.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2596638519 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 3906384760 ps |
| CPU time | 341.89 seconds |
| Started | May 30 04:41:46 PM PDT 24 |
| Finished | May 30 04:47:28 PM PDT 24 |
| Peak memory | 638544 kb |
| Host | smart-c76aeab0-6d37-452e-905c-c8fb23174a34 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596638519 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2596638519 |
| Directory | /workspace/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/76.chip_sw_all_escalation_resets.1795222279 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 4571948936 ps |
| CPU time | 617.59 seconds |
| Started | May 30 04:41:43 PM PDT 24 |
| Finished | May 30 04:52:01 PM PDT 24 |
| Peak memory | 639540 kb |
| Host | smart-93c324ec-a995-4e37-827d-ed8f43373368 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1795222279 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.1795222279 |
| Directory | /workspace/76.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/77.chip_sw_all_escalation_resets.2546669080 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 4931823588 ps |
| CPU time | 583.07 seconds |
| Started | May 30 04:41:46 PM PDT 24 |
| Finished | May 30 04:51:30 PM PDT 24 |
| Peak memory | 639332 kb |
| Host | smart-979a7415-3979-4331-aab8-21da87ca9689 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2546669080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.2546669080 |
| Directory | /workspace/77.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3879369151 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 3814401040 ps |
| CPU time | 396.98 seconds |
| Started | May 30 04:42:10 PM PDT 24 |
| Finished | May 30 04:48:48 PM PDT 24 |
| Peak memory | 639620 kb |
| Host | smart-784448b1-c491-465c-a286-e3375bf2b4ec |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879369151 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3879369151 |
| Directory | /workspace/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/78.chip_sw_all_escalation_resets.1236962791 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 5492133104 ps |
| CPU time | 599.79 seconds |
| Started | May 30 04:41:36 PM PDT 24 |
| Finished | May 30 04:51:36 PM PDT 24 |
| Peak memory | 639408 kb |
| Host | smart-388fa22e-3cbb-433d-9567-3bcc93b4df1e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1236962791 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.1236962791 |
| Directory | /workspace/78.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/79.chip_sw_all_escalation_resets.1477875588 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 4715084500 ps |
| CPU time | 544.2 seconds |
| Started | May 30 04:42:43 PM PDT 24 |
| Finished | May 30 04:51:55 PM PDT 24 |
| Peak memory | 639728 kb |
| Host | smart-70c6cd05-574a-4049-a908-ee5f5b1a2f23 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1477875588 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_all_escalation_resets.1477875588 |
| Directory | /workspace/79.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1294596023 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 3978428168 ps |
| CPU time | 442.42 seconds |
| Started | May 30 04:33:58 PM PDT 24 |
| Finished | May 30 04:41:23 PM PDT 24 |
| Peak memory | 638544 kb |
| Host | smart-06a2be83-fdc0-4d1e-ad0f-4e04b2f3bc47 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294596023 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_s w_alert_handler_lpg_sleep_mode_alerts.1294596023 |
| Directory | /workspace/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/8.chip_sw_all_escalation_resets.16694476 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 4917842762 ps |
| CPU time | 761.61 seconds |
| Started | May 30 04:33:56 PM PDT 24 |
| Finished | May 30 04:46:40 PM PDT 24 |
| Peak memory | 639572 kb |
| Host | smart-a2493256-5648-46ae-95df-3a9ebe198e75 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 16694476 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.16694476 |
| Directory | /workspace/8.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.2973766170 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 16357947588 ps |
| CPU time | 3933.4 seconds |
| Started | May 30 04:34:09 PM PDT 24 |
| Finished | May 30 05:39:45 PM PDT 24 |
| Peak memory | 604096 kb |
| Host | smart-add49cb5-e51a-4308-b40b-69bdfec656ca |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973766170 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 8.chip_sw_csrng_edn_concurrency.2973766170 |
| Directory | /workspace/8.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.2745489876 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 11364158532 ps |
| CPU time | 800.25 seconds |
| Started | May 30 04:34:00 PM PDT 24 |
| Finished | May 30 04:47:24 PM PDT 24 |
| Peak memory | 615680 kb |
| Host | smart-d1cdee7d-fb19-41bb-9b9b-6b0f5856664e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745489876 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 8.chip_sw_lc_ctrl_transition.2745489876 |
| Directory | /workspace/8.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2802631271 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 4983766732 ps |
| CPU time | 683.92 seconds |
| Started | May 30 04:34:36 PM PDT 24 |
| Finished | May 30 04:46:02 PM PDT 24 |
| Peak memory | 612484 kb |
| Host | smart-40ac595d-06ba-4678-8eff-f38e4a55eb7b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2802631271 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.2802631271 |
| Directory | /workspace/8.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.207289854 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 3664776040 ps |
| CPU time | 355.54 seconds |
| Started | May 30 04:42:04 PM PDT 24 |
| Finished | May 30 04:48:01 PM PDT 24 |
| Peak memory | 638476 kb |
| Host | smart-7b9c5919-8dc0-4dd5-8b72-1a58dcbbdb01 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207289854 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_s w_alert_handler_lpg_sleep_mode_alerts.207289854 |
| Directory | /workspace/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/80.chip_sw_all_escalation_resets.2833934548 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 5667152510 ps |
| CPU time | 520.28 seconds |
| Started | May 30 04:41:41 PM PDT 24 |
| Finished | May 30 04:50:22 PM PDT 24 |
| Peak memory | 611360 kb |
| Host | smart-fe563df9-ea6d-4b42-8258-f79931568422 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2833934548 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.2833934548 |
| Directory | /workspace/80.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/81.chip_sw_all_escalation_resets.3100691800 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 5378060344 ps |
| CPU time | 527.41 seconds |
| Started | May 30 04:44:19 PM PDT 24 |
| Finished | May 30 04:53:07 PM PDT 24 |
| Peak memory | 611380 kb |
| Host | smart-3d4d73df-542d-40bd-b253-9fbba9ab5a48 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3100691800 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.3100691800 |
| Directory | /workspace/81.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2830497868 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 3414355016 ps |
| CPU time | 316.97 seconds |
| Started | May 30 04:43:24 PM PDT 24 |
| Finished | May 30 04:48:42 PM PDT 24 |
| Peak memory | 639592 kb |
| Host | smart-1ab67c95-544d-456c-bbd7-71a050ac898d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830497868 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2830497868 |
| Directory | /workspace/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/82.chip_sw_all_escalation_resets.3344022435 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 4434630024 ps |
| CPU time | 491.74 seconds |
| Started | May 30 04:41:58 PM PDT 24 |
| Finished | May 30 04:50:11 PM PDT 24 |
| Peak memory | 639708 kb |
| Host | smart-98b8ec1f-f966-4a5e-9a74-41cc597140ff |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3344022435 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.3344022435 |
| Directory | /workspace/82.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1136748820 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 4119074580 ps |
| CPU time | 350.35 seconds |
| Started | May 30 04:43:34 PM PDT 24 |
| Finished | May 30 04:49:25 PM PDT 24 |
| Peak memory | 639820 kb |
| Host | smart-cdbeafdf-c1da-42f5-a7c6-1dc8af2694d6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136748820 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1136748820 |
| Directory | /workspace/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/83.chip_sw_all_escalation_resets.1692923504 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 5012342754 ps |
| CPU time | 557.33 seconds |
| Started | May 30 04:42:04 PM PDT 24 |
| Finished | May 30 04:51:22 PM PDT 24 |
| Peak memory | 611272 kb |
| Host | smart-1823c086-5747-42db-adf1-421807de88d0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1692923504 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.1692923504 |
| Directory | /workspace/83.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2151569594 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 3883693358 ps |
| CPU time | 383.45 seconds |
| Started | May 30 04:42:03 PM PDT 24 |
| Finished | May 30 04:48:27 PM PDT 24 |
| Peak memory | 639560 kb |
| Host | smart-e64473e9-b9eb-4fc9-8750-246126bdb7cb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151569594 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2151569594 |
| Directory | /workspace/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/84.chip_sw_all_escalation_resets.3372663187 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 5386016204 ps |
| CPU time | 511.36 seconds |
| Started | May 30 04:43:34 PM PDT 24 |
| Finished | May 30 04:52:06 PM PDT 24 |
| Peak memory | 639376 kb |
| Host | smart-dc67217c-760b-437c-bdf6-8534caaf4eeb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3372663187 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.3372663187 |
| Directory | /workspace/84.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1651611181 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 3688024424 ps |
| CPU time | 408.5 seconds |
| Started | May 30 04:42:16 PM PDT 24 |
| Finished | May 30 04:49:05 PM PDT 24 |
| Peak memory | 639572 kb |
| Host | smart-31496c77-6125-4d66-aca9-2d0d8eb654be |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651611181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1651611181 |
| Directory | /workspace/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/85.chip_sw_all_escalation_resets.3306210295 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 5381841828 ps |
| CPU time | 690.97 seconds |
| Started | May 30 04:47:15 PM PDT 24 |
| Finished | May 30 04:58:47 PM PDT 24 |
| Peak memory | 612280 kb |
| Host | smart-bfc98f6b-ce9e-4449-924d-22806a1c7bd1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3306210295 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.3306210295 |
| Directory | /workspace/85.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/86.chip_sw_all_escalation_resets.2437260928 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 6021195890 ps |
| CPU time | 714.83 seconds |
| Started | May 30 04:46:10 PM PDT 24 |
| Finished | May 30 04:58:06 PM PDT 24 |
| Peak memory | 639660 kb |
| Host | smart-da26e67a-755a-4eb6-a3c5-ca3137a9041b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2437260928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.2437260928 |
| Directory | /workspace/86.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.260389457 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 3884473570 ps |
| CPU time | 381.46 seconds |
| Started | May 30 04:46:29 PM PDT 24 |
| Finished | May 30 04:52:51 PM PDT 24 |
| Peak memory | 639728 kb |
| Host | smart-fc136e79-320d-4a5f-9001-4adf759cd4ce |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260389457 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_s w_alert_handler_lpg_sleep_mode_alerts.260389457 |
| Directory | /workspace/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/87.chip_sw_all_escalation_resets.646349275 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 5060643992 ps |
| CPU time | 663.43 seconds |
| Started | May 30 04:43:28 PM PDT 24 |
| Finished | May 30 04:54:32 PM PDT 24 |
| Peak memory | 639732 kb |
| Host | smart-75a9caaf-bfff-4e90-bcb3-8d08787d7433 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 646349275 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.646349275 |
| Directory | /workspace/87.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1446192071 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 3889137344 ps |
| CPU time | 358.96 seconds |
| Started | May 30 04:42:12 PM PDT 24 |
| Finished | May 30 04:48:12 PM PDT 24 |
| Peak memory | 639776 kb |
| Host | smart-dfb7182a-9841-44fd-83c3-b396f63a879f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446192071 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1446192071 |
| Directory | /workspace/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/88.chip_sw_all_escalation_resets.3983015006 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 5488412680 ps |
| CPU time | 554.46 seconds |
| Started | May 30 04:42:01 PM PDT 24 |
| Finished | May 30 04:51:17 PM PDT 24 |
| Peak memory | 639356 kb |
| Host | smart-fd4efd2c-14fc-4ce3-96d2-83c7bf791d7f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3983015006 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.3983015006 |
| Directory | /workspace/88.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.4144013496 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 3701840264 ps |
| CPU time | 502.69 seconds |
| Started | May 30 04:42:54 PM PDT 24 |
| Finished | May 30 04:51:19 PM PDT 24 |
| Peak memory | 639544 kb |
| Host | smart-449e5dd0-a5aa-4935-878e-7b6e70bbf3ac |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144013496 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4144013496 |
| Directory | /workspace/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/89.chip_sw_all_escalation_resets.920041640 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 4111598048 ps |
| CPU time | 623.53 seconds |
| Started | May 30 04:42:58 PM PDT 24 |
| Finished | May 30 04:53:23 PM PDT 24 |
| Peak memory | 639340 kb |
| Host | smart-9bc611b0-190a-453d-b313-5cc26c36a345 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 920041640 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.920041640 |
| Directory | /workspace/89.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1804971740 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 4101823560 ps |
| CPU time | 415.6 seconds |
| Started | May 30 04:34:38 PM PDT 24 |
| Finished | May 30 04:41:35 PM PDT 24 |
| Peak memory | 638036 kb |
| Host | smart-3ff6c059-7ae4-409b-9f65-a05da3c21834 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804971740 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_s w_alert_handler_lpg_sleep_mode_alerts.1804971740 |
| Directory | /workspace/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.3620986090 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 22150138990 ps |
| CPU time | 4719.03 seconds |
| Started | May 30 04:36:52 PM PDT 24 |
| Finished | May 30 05:55:32 PM PDT 24 |
| Peak memory | 603828 kb |
| Host | smart-50615a19-208b-476e-9ef7-ca645ce7f032 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620986090 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 9.chip_sw_csrng_edn_concurrency.3620986090 |
| Directory | /workspace/9.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.4180409132 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 5864136219 ps |
| CPU time | 467.93 seconds |
| Started | May 30 04:33:42 PM PDT 24 |
| Finished | May 30 04:41:31 PM PDT 24 |
| Peak memory | 615680 kb |
| Host | smart-23a776e5-e2aa-4f94-9fcf-ee6dd4735589 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180409132 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 9.chip_sw_lc_ctrl_transition.4180409132 |
| Directory | /workspace/9.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.811354858 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 8496691200 ps |
| CPU time | 1443.82 seconds |
| Started | May 30 04:34:01 PM PDT 24 |
| Finished | May 30 04:58:08 PM PDT 24 |
| Peak memory | 612436 kb |
| Host | smart-a98f23ed-55cd-4d7e-9657-5d9d33c41032 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=811354858 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.811354858 |
| Directory | /workspace/9.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/90.chip_sw_all_escalation_resets.1120847974 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 6081311100 ps |
| CPU time | 601.34 seconds |
| Started | May 30 04:46:55 PM PDT 24 |
| Finished | May 30 04:56:58 PM PDT 24 |
| Peak memory | 639388 kb |
| Host | smart-d0add9de-1c57-40f7-990a-f69839fb497b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1120847974 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.1120847974 |
| Directory | /workspace/90.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/91.chip_sw_all_escalation_resets.3347656023 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 4227835508 ps |
| CPU time | 455.66 seconds |
| Started | May 30 04:42:46 PM PDT 24 |
| Finished | May 30 04:50:29 PM PDT 24 |
| Peak memory | 611260 kb |
| Host | smart-41137d1f-35f2-4b86-aa80-f3ca043e7424 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3347656023 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.3347656023 |
| Directory | /workspace/91.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/92.chip_sw_all_escalation_resets.2071937415 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 5599389800 ps |
| CPU time | 717.08 seconds |
| Started | May 30 04:46:48 PM PDT 24 |
| Finished | May 30 04:58:46 PM PDT 24 |
| Peak memory | 640568 kb |
| Host | smart-5e2d2970-efdb-433f-b7e2-f327b5da946d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2071937415 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.2071937415 |
| Directory | /workspace/92.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/93.chip_sw_all_escalation_resets.3410661463 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 5080876600 ps |
| CPU time | 562.72 seconds |
| Started | May 30 04:42:45 PM PDT 24 |
| Finished | May 30 04:52:16 PM PDT 24 |
| Peak memory | 639584 kb |
| Host | smart-a716b41f-1c63-45a0-8d9c-1a6369f2e822 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3410661463 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.3410661463 |
| Directory | /workspace/93.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/94.chip_sw_all_escalation_resets.3932240959 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 5519688768 ps |
| CPU time | 500.66 seconds |
| Started | May 30 04:42:43 PM PDT 24 |
| Finished | May 30 04:51:11 PM PDT 24 |
| Peak memory | 639544 kb |
| Host | smart-e1426403-320f-4603-bc9d-44280fe97cfd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3932240959 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.3932240959 |
| Directory | /workspace/94.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/95.chip_sw_all_escalation_resets.998342975 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 4766531590 ps |
| CPU time | 645.55 seconds |
| Started | May 30 04:46:31 PM PDT 24 |
| Finished | May 30 04:57:18 PM PDT 24 |
| Peak memory | 605372 kb |
| Host | smart-11db1d65-19e4-4269-9cc2-fd4a2bca6dbe |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 998342975 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.998342975 |
| Directory | /workspace/95.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/96.chip_sw_all_escalation_resets.651336699 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 5145458060 ps |
| CPU time | 562.73 seconds |
| Started | May 30 04:43:04 PM PDT 24 |
| Finished | May 30 04:52:28 PM PDT 24 |
| Peak memory | 640784 kb |
| Host | smart-a2308e7f-05fa-4d8b-b3cb-0d73de768a53 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 651336699 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.651336699 |
| Directory | /workspace/96.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/97.chip_sw_all_escalation_resets.3168478625 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 4635541754 ps |
| CPU time | 555.13 seconds |
| Started | May 30 04:44:19 PM PDT 24 |
| Finished | May 30 04:53:35 PM PDT 24 |
| Peak memory | 611324 kb |
| Host | smart-ce1cd5aa-ca04-420d-a76d-4f5a5431374c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3168478625 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.3168478625 |
| Directory | /workspace/97.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/98.chip_sw_all_escalation_resets.3988578182 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 5485099558 ps |
| CPU time | 512.56 seconds |
| Started | May 30 04:41:24 PM PDT 24 |
| Finished | May 30 04:49:58 PM PDT 24 |
| Peak memory | 638508 kb |
| Host | smart-4339bd3c-73d3-47a6-a110-494f0b627099 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3988578182 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.3988578182 |
| Directory | /workspace/98.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/99.chip_sw_all_escalation_resets.2508292432 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 5957554570 ps |
| CPU time | 482.89 seconds |
| Started | May 30 04:41:41 PM PDT 24 |
| Finished | May 30 04:49:44 PM PDT 24 |
| Peak memory | 639560 kb |
| Host | smart-f1d740a8-12ec-467e-85f0-b91293ef7d46 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2508292432 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.2508292432 |
| Directory | /workspace/99.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2819108315 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 4804286284 ps |
| CPU time | 279.14 seconds |
| Started | May 30 04:01:32 PM PDT 24 |
| Finished | May 30 04:06:12 PM PDT 24 |
| Peak memory | 639672 kb |
| Host | smart-68b11d16-44be-4e64-9593-3881c0439236 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819108315 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 1.chip_padctrl_attributes.2819108315 |
| Directory | /workspace/1.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1341210892 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 4466690102 ps |
| CPU time | 254.59 seconds |
| Started | May 30 04:01:37 PM PDT 24 |
| Finished | May 30 04:05:53 PM PDT 24 |
| Peak memory | 639676 kb |
| Host | smart-cd56a82f-31fe-4b9d-95df-5ff3f86b4ef1 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341210892 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 2.chip_padctrl_attributes.1341210892 |
| Directory | /workspace/2.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3431310560 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 5395356800 ps |
| CPU time | 323.16 seconds |
| Started | May 30 04:01:38 PM PDT 24 |
| Finished | May 30 04:07:03 PM PDT 24 |
| Peak memory | 639744 kb |
| Host | smart-6f8e0715-5893-4f75-b3d0-dfcd625ac191 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431310560 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 3.chip_padctrl_attributes.3431310560 |
| Directory | /workspace/3.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3465449281 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 4331547445 ps |
| CPU time | 235.31 seconds |
| Started | May 30 04:01:36 PM PDT 24 |
| Finished | May 30 04:05:33 PM PDT 24 |
| Peak memory | 639712 kb |
| Host | smart-0de3db61-8108-4ec2-ab34-e2723634c17a |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465449281 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 4.chip_padctrl_attributes.3465449281 |
| Directory | /workspace/4.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.3573255103 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 4134021570 ps |
| CPU time | 248.45 seconds |
| Started | May 30 04:01:39 PM PDT 24 |
| Finished | May 30 04:05:48 PM PDT 24 |
| Peak memory | 639756 kb |
| Host | smart-1e991b71-db85-4524-abaf-a6e76149ad23 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573255103 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 6.chip_padctrl_attributes.3573255103 |
| Directory | /workspace/6.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3671563782 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 4505717098 ps |
| CPU time | 312.06 seconds |
| Started | May 30 04:01:35 PM PDT 24 |
| Finished | May 30 04:06:48 PM PDT 24 |
| Peak memory | 639752 kb |
| Host | smart-aa96ce94-402b-4b0d-8b5b-76d5cc2f40f6 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671563782 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 7.chip_padctrl_attributes.3671563782 |
| Directory | /workspace/7.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.704438347 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 4561731918 ps |
| CPU time | 299.1 seconds |
| Started | May 30 04:01:40 PM PDT 24 |
| Finished | May 30 04:06:40 PM PDT 24 |
| Peak memory | 639748 kb |
| Host | smart-09111140-f8ac-402f-b954-e30e6081bd33 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704438347 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 8.chip_padctrl_attributes.704438347 |
| Directory | /workspace/8.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3542712953 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 5071828776 ps |
| CPU time | 253.48 seconds |
| Started | May 30 04:01:36 PM PDT 24 |
| Finished | May 30 04:05:50 PM PDT 24 |
| Peak memory | 647896 kb |
| Host | smart-404d50b1-55e8-425d-96f6-18319e158c8b |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542712953 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 9.chip_padctrl_attributes.3542712953 |
| Directory | /workspace/9.chip_padctrl_attributes/latest |
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