Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.13 95.57 94.38 95.52 95.30 96.47 99.58


Total test records in report: 2874
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html | tests60.html
T1150 /workspace/coverage/default/2.chip_sw_csrng_kat_test.4210227624 May 30 04:27:17 PM PDT 24 May 30 04:31:40 PM PDT 24 2255409444 ps
T71 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.2812493479 May 30 04:09:23 PM PDT 24 May 30 05:53:48 PM PDT 24 31367845816 ps
T748 /workspace/coverage/default/59.chip_sw_all_escalation_resets.2712189700 May 30 04:39:51 PM PDT 24 May 30 04:48:12 PM PDT 24 5753139272 ps
T1151 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.2358096489 May 30 04:10:39 PM PDT 24 May 30 04:18:17 PM PDT 24 4618497380 ps
T339 /workspace/coverage/default/1.chip_sw_entropy_src_csrng.1031511850 May 30 04:18:58 PM PDT 24 May 30 04:51:36 PM PDT 24 6968719120 ps
T1152 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3828952616 May 30 04:30:36 PM PDT 24 May 30 04:40:11 PM PDT 24 5271851668 ps
T1153 /workspace/coverage/default/0.rom_e2e_asm_init_rma.1381976600 May 30 04:17:53 PM PDT 24 May 30 05:09:35 PM PDT 24 14195118583 ps
T1154 /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.3170624704 May 30 04:28:52 PM PDT 24 May 30 05:14:18 PM PDT 24 10970190231 ps
T747 /workspace/coverage/default/86.chip_sw_all_escalation_resets.2437260928 May 30 04:46:10 PM PDT 24 May 30 04:58:06 PM PDT 24 6021195890 ps
T1155 /workspace/coverage/default/2.chip_sw_aon_timer_irq.2330691885 May 30 04:26:04 PM PDT 24 May 30 04:33:09 PM PDT 24 4371413224 ps
T1156 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.2712973557 May 30 04:35:25 PM PDT 24 May 30 04:42:43 PM PDT 24 4438287494 ps
T719 /workspace/coverage/default/31.chip_sw_all_escalation_resets.4073281017 May 30 04:36:33 PM PDT 24 May 30 04:47:34 PM PDT 24 5760967250 ps
T1157 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.2471650290 May 30 04:17:14 PM PDT 24 May 30 04:51:09 PM PDT 24 8628530650 ps
T1158 /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.1125943767 May 30 04:09:13 PM PDT 24 May 30 04:15:15 PM PDT 24 3119454790 ps
T1159 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.704985247 May 30 04:30:23 PM PDT 24 May 30 04:43:57 PM PDT 24 4008170452 ps
T1160 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.2175941980 May 30 04:22:49 PM PDT 24 May 30 05:22:06 PM PDT 24 10984119240 ps
T726 /workspace/coverage/default/99.chip_sw_all_escalation_resets.2508292432 May 30 04:41:41 PM PDT 24 May 30 04:49:44 PM PDT 24 5957554570 ps
T1161 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1424662369 May 30 04:30:14 PM PDT 24 May 30 04:51:03 PM PDT 24 10551972263 ps
T1162 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2645415415 May 30 04:11:40 PM PDT 24 May 30 04:25:44 PM PDT 24 8369689128 ps
T447 /workspace/coverage/default/0.chip_sw_edn_boot_mode.1943316000 May 30 04:11:40 PM PDT 24 May 30 04:20:35 PM PDT 24 3438616520 ps
T369 /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2197445558 May 30 04:33:06 PM PDT 24 May 30 04:40:10 PM PDT 24 4567767720 ps
T518 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2653042929 May 30 04:17:46 PM PDT 24 May 30 04:34:14 PM PDT 24 4485954628 ps
T200 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.4234636122 May 30 04:17:25 PM PDT 24 May 30 04:30:26 PM PDT 24 4923910611 ps
T83 /workspace/coverage/default/2.chip_sw_alert_handler_entropy.2127133192 May 30 04:29:44 PM PDT 24 May 30 04:35:43 PM PDT 24 3151630482 ps
T1163 /workspace/coverage/default/18.chip_sw_all_escalation_resets.1827342811 May 30 04:37:01 PM PDT 24 May 30 04:45:47 PM PDT 24 5680008248 ps
T340 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.1612321530 May 30 04:30:59 PM PDT 24 May 30 04:55:55 PM PDT 24 8297230726 ps
T1164 /workspace/coverage/default/0.rom_e2e_shutdown_output.2495243265 May 30 04:16:59 PM PDT 24 May 30 05:04:09 PM PDT 24 24513032568 ps
T1165 /workspace/coverage/default/2.chip_sival_flash_info_access.3244138062 May 30 04:23:14 PM PDT 24 May 30 04:27:26 PM PDT 24 2526804770 ps
T1166 /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1969176013 May 30 04:40:10 PM PDT 24 May 30 04:46:48 PM PDT 24 3325301734 ps
T417 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3018315867 May 30 04:14:33 PM PDT 24 May 30 04:20:59 PM PDT 24 6954970800 ps
T707 /workspace/coverage/default/17.chip_sw_all_escalation_resets.67267926 May 30 04:34:28 PM PDT 24 May 30 04:47:18 PM PDT 24 5079714292 ps
T761 /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2003134786 May 30 04:40:46 PM PDT 24 May 30 04:45:58 PM PDT 24 3524421696 ps
T1167 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.2974881583 May 30 04:19:15 PM PDT 24 May 30 04:23:21 PM PDT 24 2560699336 ps
T1168 /workspace/coverage/default/2.chip_tap_straps_dev.2444263562 May 30 04:29:58 PM PDT 24 May 30 04:51:15 PM PDT 24 10907383003 ps
T1169 /workspace/coverage/default/2.chip_sw_example_flash.2317201501 May 30 04:22:53 PM PDT 24 May 30 04:26:59 PM PDT 24 3073309212 ps
T1170 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1898059062 May 30 04:18:01 PM PDT 24 May 30 04:29:26 PM PDT 24 5245335220 ps
T39 /workspace/coverage/default/0.chip_sw_gpio.1325020322 May 30 04:09:00 PM PDT 24 May 30 04:15:29 PM PDT 24 3520682097 ps
T1171 /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.872509181 May 30 04:36:42 PM PDT 24 May 30 05:01:51 PM PDT 24 7725756760 ps
T1172 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.3826477122 May 30 04:09:48 PM PDT 24 May 30 04:44:05 PM PDT 24 25734658975 ps
T1173 /workspace/coverage/default/0.chip_sw_usbdev_vbus.668360028 May 30 04:09:14 PM PDT 24 May 30 04:14:02 PM PDT 24 2515870690 ps
T1174 /workspace/coverage/default/50.chip_sw_all_escalation_resets.3701781586 May 30 04:40:59 PM PDT 24 May 30 04:49:45 PM PDT 24 5104138170 ps
T314 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2394171825 May 30 04:35:00 PM PDT 24 May 30 04:42:05 PM PDT 24 4343410580 ps
T1175 /workspace/coverage/default/1.rom_e2e_asm_init_rma.1215549427 May 30 04:28:43 PM PDT 24 May 30 05:20:15 PM PDT 24 14002961675 ps
T1176 /workspace/coverage/default/2.chip_sw_kmac_idle.4184427142 May 30 04:28:45 PM PDT 24 May 30 04:32:13 PM PDT 24 2847091400 ps
T744 /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.4144013496 May 30 04:42:54 PM PDT 24 May 30 04:51:19 PM PDT 24 3701840264 ps
T1177 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.442169891 May 30 04:39:24 PM PDT 24 May 30 05:31:41 PM PDT 24 14531753800 ps
T1178 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.645414080 May 30 04:17:15 PM PDT 24 May 30 04:28:20 PM PDT 24 4441318992 ps
T1179 /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.572945618 May 30 04:14:22 PM PDT 24 May 30 04:21:01 PM PDT 24 7549861293 ps
T1180 /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.3823273945 May 30 04:35:34 PM PDT 24 May 30 04:48:26 PM PDT 24 3823315232 ps
T1181 /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.3775519512 May 30 04:17:13 PM PDT 24 May 30 05:15:48 PM PDT 24 13914393237 ps
T1182 /workspace/coverage/default/1.chip_sw_hmac_enc.295755822 May 30 04:19:53 PM PDT 24 May 30 04:24:54 PM PDT 24 2608350248 ps
T418 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3998299287 May 30 04:29:36 PM PDT 24 May 30 04:37:09 PM PDT 24 7523280960 ps
T1183 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.1866273800 May 30 04:33:00 PM PDT 24 May 30 04:55:30 PM PDT 24 11526014192 ps
T1184 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2802631271 May 30 04:34:36 PM PDT 24 May 30 04:46:02 PM PDT 24 4983766732 ps
T1185 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.744880415 May 30 04:11:42 PM PDT 24 May 30 04:13:22 PM PDT 24 1736462856 ps
T704 /workspace/coverage/default/42.chip_sw_all_escalation_resets.203297577 May 30 04:37:05 PM PDT 24 May 30 04:45:49 PM PDT 24 5698277780 ps
T731 /workspace/coverage/default/7.chip_sw_all_escalation_resets.1123700720 May 30 04:33:21 PM PDT 24 May 30 04:41:14 PM PDT 24 4885415762 ps
T1186 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.75411119 May 30 04:20:44 PM PDT 24 May 30 04:30:23 PM PDT 24 4266481412 ps
T701 /workspace/coverage/default/15.chip_sw_all_escalation_resets.3708572067 May 30 04:34:58 PM PDT 24 May 30 04:46:46 PM PDT 24 5993239760 ps
T1187 /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.3985034571 May 30 04:26:39 PM PDT 24 May 30 05:25:13 PM PDT 24 14019595092 ps
T1188 /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.3249376089 May 30 04:35:25 PM PDT 24 May 30 06:10:59 PM PDT 24 27237030788 ps
T1189 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.2570832916 May 30 04:15:35 PM PDT 24 May 30 04:27:07 PM PDT 24 4038518228 ps
T345 /workspace/coverage/default/2.chip_plic_all_irqs_20.2157398787 May 30 04:28:53 PM PDT 24 May 30 04:42:40 PM PDT 24 4471762944 ps
T755 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.225525544 May 30 04:36:13 PM PDT 24 May 30 04:41:50 PM PDT 24 4249830392 ps
T1190 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.4102514091 May 30 04:21:12 PM PDT 24 May 30 04:33:46 PM PDT 24 3488541886 ps
T1191 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1064702030 May 30 04:17:34 PM PDT 24 May 30 05:13:55 PM PDT 24 14233643000 ps
T1192 /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.2401165119 May 30 04:35:01 PM PDT 24 May 30 04:42:04 PM PDT 24 5758915191 ps
T1193 /workspace/coverage/default/2.rom_e2e_shutdown_output.2549357352 May 30 04:36:56 PM PDT 24 May 30 05:33:10 PM PDT 24 28874992850 ps
T1194 /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2350372363 May 30 04:15:11 PM PDT 24 May 30 04:25:58 PM PDT 24 4414147576 ps
T275 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.850200715 May 30 04:09:37 PM PDT 24 May 30 04:22:13 PM PDT 24 4924461448 ps
T763 /workspace/coverage/default/11.chip_sw_all_escalation_resets.1738300418 May 30 04:34:15 PM PDT 24 May 30 04:42:49 PM PDT 24 4706211582 ps
T1195 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2121146525 May 30 04:33:12 PM PDT 24 May 30 04:57:17 PM PDT 24 8621605736 ps
T234 /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.1839727078 May 30 04:29:29 PM PDT 24 May 30 04:55:08 PM PDT 24 8317149500 ps
T1196 /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.4290853381 May 30 04:32:00 PM PDT 24 May 30 04:35:47 PM PDT 24 2715699870 ps
T296 /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.1999040857 May 30 04:30:24 PM PDT 24 May 30 04:33:50 PM PDT 24 2133390423 ps
T1197 /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.1943915753 May 30 04:34:05 PM PDT 24 May 30 04:53:53 PM PDT 24 11734492610 ps
T1198 /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.424191868 May 30 04:14:25 PM PDT 24 May 30 04:18:30 PM PDT 24 2584631298 ps
T1199 /workspace/coverage/default/2.chip_sw_otbn_smoketest.3168259080 May 30 04:31:58 PM PDT 24 May 30 04:50:40 PM PDT 24 5855684040 ps
T1200 /workspace/coverage/default/0.chip_sw_flash_crash_alert.3114684071 May 30 04:12:21 PM PDT 24 May 30 04:23:48 PM PDT 24 6622184476 ps
T45 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.620620943 May 30 04:26:56 PM PDT 24 May 30 04:33:06 PM PDT 24 3557810308 ps
T1201 /workspace/coverage/default/2.chip_sw_hmac_enc.1710792261 May 30 04:30:32 PM PDT 24 May 30 04:36:19 PM PDT 24 2927716600 ps
T419 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.586738981 May 30 04:21:15 PM PDT 24 May 30 04:46:15 PM PDT 24 23380660952 ps
T1202 /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.4037986699 May 30 04:21:13 PM PDT 24 May 30 04:27:09 PM PDT 24 2693898528 ps
T1203 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.2936215734 May 30 04:20:03 PM PDT 24 May 30 04:56:34 PM PDT 24 11675922384 ps
T1204 /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.4119596021 May 30 04:11:41 PM PDT 24 May 30 07:31:00 PM PDT 24 254557385616 ps
T1205 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1526269382 May 30 04:20:39 PM PDT 24 May 30 04:33:14 PM PDT 24 4820110402 ps
T1206 /workspace/coverage/default/2.rom_volatile_raw_unlock.4788334 May 30 04:30:24 PM PDT 24 May 30 04:32:11 PM PDT 24 2337909753 ps
T1207 /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.4286773872 May 30 04:36:21 PM PDT 24 May 30 04:40:14 PM PDT 24 2711366438 ps
T1208 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.767410619 May 30 04:36:02 PM PDT 24 May 30 04:46:10 PM PDT 24 4566737816 ps
T1209 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2237080196 May 30 04:15:54 PM PDT 24 May 30 04:32:13 PM PDT 24 6884422518 ps
T1210 /workspace/coverage/default/44.chip_sw_all_escalation_resets.667622741 May 30 04:39:10 PM PDT 24 May 30 04:50:10 PM PDT 24 5750282040 ps
T1211 /workspace/coverage/default/1.chip_tap_straps_prod.3005328158 May 30 04:21:00 PM PDT 24 May 30 04:38:19 PM PDT 24 10299673148 ps
T1212 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.3594220904 May 30 04:18:55 PM PDT 24 May 30 04:31:14 PM PDT 24 5307785100 ps
T1213 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.2715495636 May 30 04:12:27 PM PDT 24 May 30 04:29:18 PM PDT 24 5344109917 ps
T1214 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.4204902566 May 30 04:21:24 PM PDT 24 May 30 05:48:05 PM PDT 24 23202954240 ps
T1215 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.314450874 May 30 04:26:32 PM PDT 24 May 30 04:44:58 PM PDT 24 9313232441 ps
T1216 /workspace/coverage/default/0.chip_sw_edn_kat.3598605290 May 30 04:11:56 PM PDT 24 May 30 04:22:55 PM PDT 24 3628735400 ps
T266 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1385759417 May 30 04:17:20 PM PDT 24 May 30 04:34:12 PM PDT 24 9944069684 ps
T1217 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.1122106568 May 30 04:28:09 PM PDT 24 May 30 04:45:27 PM PDT 24 5623835786 ps
T341 /workspace/coverage/default/0.chip_sw_entropy_src_csrng.1113895113 May 30 04:19:24 PM PDT 24 May 30 04:40:28 PM PDT 24 5603290680 ps
T11 /workspace/coverage/default/2.chip_jtag_csr_rw.1396873104 May 30 04:21:54 PM PDT 24 May 30 05:03:36 PM PDT 24 20248339494 ps
T1218 /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3556318837 May 30 04:33:42 PM PDT 24 May 30 04:43:20 PM PDT 24 7886698158 ps
T1219 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.3117206895 May 30 04:11:40 PM PDT 24 May 30 04:16:42 PM PDT 24 2532949552 ps
T1220 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.328805004 May 30 04:09:30 PM PDT 24 May 30 04:20:10 PM PDT 24 4696887200 ps
T1221 /workspace/coverage/default/1.chip_sw_aes_idle.331075792 May 30 04:17:45 PM PDT 24 May 30 04:22:27 PM PDT 24 3678365272 ps
T1222 /workspace/coverage/default/0.chip_sw_otbn_smoketest.2797112988 May 30 04:14:13 PM PDT 24 May 30 04:53:41 PM PDT 24 11405663466 ps
T1223 /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.1680352329 May 30 04:25:31 PM PDT 24 May 30 04:28:30 PM PDT 24 2563164992 ps
T1224 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.1879839756 May 30 04:31:37 PM PDT 24 May 30 04:35:18 PM PDT 24 3149329370 ps
T1225 /workspace/coverage/default/75.chip_sw_all_escalation_resets.1620831390 May 30 04:41:57 PM PDT 24 May 30 04:51:46 PM PDT 24 5553778688 ps
T1226 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.942498953 May 30 04:29:42 PM PDT 24 May 30 04:41:13 PM PDT 24 4069628790 ps
T382 /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2941455011 May 30 04:10:43 PM PDT 24 May 30 04:14:51 PM PDT 24 2184899736 ps
T1227 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.2575995584 May 30 04:30:07 PM PDT 24 May 30 05:01:12 PM PDT 24 7148833328 ps
T276 /workspace/coverage/default/1.chip_sw_data_integrity_escalation.2992562236 May 30 04:13:03 PM PDT 24 May 30 04:26:02 PM PDT 24 5872116308 ps
T1228 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2799317603 May 30 04:31:25 PM PDT 24 May 30 05:28:05 PM PDT 24 24199715355 ps
T1229 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.3672683921 May 30 04:20:39 PM PDT 24 May 30 05:53:24 PM PDT 24 22493121928 ps
T1230 /workspace/coverage/default/0.chip_sw_rv_timer_systick_test.1978423639 May 30 04:09:14 PM PDT 24 May 30 06:00:49 PM PDT 24 38151908816 ps
T1231 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1261053507 May 30 04:18:56 PM PDT 24 May 30 04:40:00 PM PDT 24 9773685016 ps
T1232 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.3003976394 May 30 04:24:11 PM PDT 24 May 30 04:37:23 PM PDT 24 5446907416 ps
T1233 /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.2861124225 May 30 04:35:28 PM PDT 24 May 30 04:56:51 PM PDT 24 7958605352 ps
T675 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.3733301522 May 30 04:30:23 PM PDT 24 May 30 04:34:43 PM PDT 24 3001407020 ps
T1234 /workspace/coverage/default/1.chip_sw_kmac_app_rom.989292156 May 30 04:18:18 PM PDT 24 May 30 04:21:45 PM PDT 24 3068673864 ps
T1235 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.4190840513 May 30 04:11:44 PM PDT 24 May 30 04:16:29 PM PDT 24 3456861728 ps
T195 /workspace/coverage/default/0.chip_jtag_mem_access.7279275 May 30 04:03:10 PM PDT 24 May 30 04:25:02 PM PDT 24 12876191356 ps
T1236 /workspace/coverage/default/2.chip_sw_rv_timer_irq.943419426 May 30 04:27:00 PM PDT 24 May 30 04:32:28 PM PDT 24 2738857440 ps
T730 /workspace/coverage/default/10.chip_sw_all_escalation_resets.1539133506 May 30 04:36:53 PM PDT 24 May 30 04:49:21 PM PDT 24 5138887196 ps
T1237 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1980227948 May 30 04:19:03 PM PDT 24 May 30 04:27:48 PM PDT 24 7184456284 ps
T1238 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3279540560 May 30 04:33:15 PM PDT 24 May 30 04:37:52 PM PDT 24 2391297752 ps
T1239 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.91188732 May 30 04:10:23 PM PDT 24 May 30 04:19:12 PM PDT 24 5777351400 ps
T1240 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.1686918926 May 30 04:19:48 PM PDT 24 May 30 05:46:23 PM PDT 24 21044642064 ps
T1241 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.1855295851 May 30 04:14:32 PM PDT 24 May 30 04:21:25 PM PDT 24 5135509000 ps
T297 /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.1130864574 May 30 04:21:22 PM PDT 24 May 30 04:26:22 PM PDT 24 2820800191 ps
T1242 /workspace/coverage/default/1.chip_sw_kmac_smoketest.4048785953 May 30 04:24:11 PM PDT 24 May 30 04:28:37 PM PDT 24 3203664652 ps
T709 /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2679644549 May 30 04:41:57 PM PDT 24 May 30 04:47:49 PM PDT 24 4034546480 ps
T1243 /workspace/coverage/default/1.chip_sw_clkmgr_jitter.4169518173 May 30 04:20:05 PM PDT 24 May 30 04:25:09 PM PDT 24 2366080344 ps
T1244 /workspace/coverage/default/14.chip_sw_all_escalation_resets.353782616 May 30 04:34:36 PM PDT 24 May 30 04:43:35 PM PDT 24 4278785220 ps
T1245 /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.2804368366 May 30 04:15:01 PM PDT 24 May 30 04:20:26 PM PDT 24 4231731480 ps
T1246 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.903235604 May 30 04:11:46 PM PDT 24 May 30 04:51:58 PM PDT 24 26095178491 ps
T1247 /workspace/coverage/default/0.chip_sw_uart_tx_rx.1105146227 May 30 04:09:49 PM PDT 24 May 30 04:20:17 PM PDT 24 3671803514 ps
T1248 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.2666828206 May 30 04:17:50 PM PDT 24 May 30 04:40:02 PM PDT 24 6914330751 ps
T1249 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.2442317847 May 30 04:19:58 PM PDT 24 May 30 04:29:52 PM PDT 24 8920682492 ps
T1250 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1573056527 May 30 04:42:11 PM PDT 24 May 30 04:48:50 PM PDT 24 4210097192 ps
T751 /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1436865057 May 30 04:43:55 PM PDT 24 May 30 04:49:34 PM PDT 24 4084810092 ps
T1251 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.1756664403 May 30 04:19:59 PM PDT 24 May 30 04:24:02 PM PDT 24 3280965484 ps
T1252 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3599793416 May 30 04:09:44 PM PDT 24 May 30 04:17:14 PM PDT 24 3931021434 ps
T1253 /workspace/coverage/default/0.chip_sw_example_manufacturer.624847938 May 30 04:09:55 PM PDT 24 May 30 04:14:41 PM PDT 24 2234658280 ps
T52 /workspace/coverage/default/2.chip_sw_spi_device_tpm.1549500774 May 30 04:25:13 PM PDT 24 May 30 04:30:18 PM PDT 24 3716626732 ps
T1254 /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.151203193 May 30 04:29:02 PM PDT 24 May 30 05:12:10 PM PDT 24 10839575000 ps
T1255 /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.490670995 May 30 04:24:01 PM PDT 24 May 30 04:35:15 PM PDT 24 5334047180 ps
T305 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.3555571368 May 30 04:28:50 PM PDT 24 May 30 04:38:38 PM PDT 24 7523894799 ps
T1256 /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.3553083395 May 30 04:29:38 PM PDT 24 May 30 04:43:48 PM PDT 24 4969072200 ps
T1257 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.1539832294 May 30 04:26:52 PM PDT 24 May 30 04:33:51 PM PDT 24 4980196216 ps
T1258 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.4272118714 May 30 04:25:49 PM PDT 24 May 30 05:25:54 PM PDT 24 30842373560 ps
T684 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1915453628 May 30 04:30:20 PM PDT 24 May 30 04:56:18 PM PDT 24 21525102426 ps
T46 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1125206444 May 30 04:09:56 PM PDT 24 May 30 04:14:52 PM PDT 24 3467711562 ps
T1259 /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.47802873 May 30 04:28:27 PM PDT 24 May 30 04:38:40 PM PDT 24 5183981962 ps
T1260 /workspace/coverage/default/1.chip_sw_aes_masking_off.1010941062 May 30 04:16:37 PM PDT 24 May 30 04:20:59 PM PDT 24 3196061353 ps
T1261 /workspace/coverage/default/2.chip_sw_aes_smoketest.1297101762 May 30 04:33:14 PM PDT 24 May 30 04:37:29 PM PDT 24 2886228140 ps
T90 /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2233444011 May 30 04:36:11 PM PDT 24 May 30 04:43:31 PM PDT 24 2985725550 ps
T1262 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.392542015 May 30 04:26:48 PM PDT 24 May 30 04:42:00 PM PDT 24 7768834317 ps
T736 /workspace/coverage/default/9.chip_sw_all_escalation_resets.2578445731 May 30 04:34:10 PM PDT 24 May 30 04:42:04 PM PDT 24 5421456870 ps
T687 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.845922309 May 30 04:36:15 PM PDT 24 May 30 04:43:09 PM PDT 24 4242543848 ps
T420 /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.1815732881 May 30 04:20:57 PM PDT 24 May 30 04:27:00 PM PDT 24 3565861752 ps
T315 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.4139947388 May 30 04:33:31 PM PDT 24 May 30 04:40:22 PM PDT 24 3299965568 ps
T676 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.846562858 May 30 04:16:38 PM PDT 24 May 30 04:21:02 PM PDT 24 3481451144 ps
T183 /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.584475966 May 30 04:19:36 PM PDT 24 May 30 04:27:33 PM PDT 24 4319377598 ps
T1263 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4291170542 May 30 04:34:30 PM PDT 24 May 30 04:41:35 PM PDT 24 4129453528 ps
T269 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.589314854 May 30 04:15:02 PM PDT 24 May 30 04:25:49 PM PDT 24 6443512360 ps
T1264 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.3864348934 May 30 04:11:29 PM PDT 24 May 30 04:22:56 PM PDT 24 4675937746 ps
T1265 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.1342762700 May 30 04:28:28 PM PDT 24 May 30 04:39:00 PM PDT 24 5168127672 ps
T1266 /workspace/coverage/default/0.chip_sw_edn_auto_mode.3222090495 May 30 04:11:44 PM PDT 24 May 30 04:30:38 PM PDT 24 4125501776 ps
T1267 /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1879930461 May 30 04:19:52 PM PDT 24 May 30 04:23:21 PM PDT 24 2849989393 ps
T1268 /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.1864773012 May 30 04:23:50 PM PDT 24 May 30 04:27:06 PM PDT 24 3016902536 ps
T770 /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2861627889 May 30 04:35:15 PM PDT 24 May 30 04:42:18 PM PDT 24 4372894520 ps
T1269 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.1809542918 May 30 04:32:38 PM PDT 24 May 30 04:43:26 PM PDT 24 4401798168 ps
T758 /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1804971740 May 30 04:34:38 PM PDT 24 May 30 04:41:35 PM PDT 24 4101823560 ps
T201 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.4270268845 May 30 04:10:53 PM PDT 24 May 30 04:15:29 PM PDT 24 2862525959 ps
T1270 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.3390207589 May 30 04:18:51 PM PDT 24 May 30 04:54:46 PM PDT 24 10776086544 ps
T766 /workspace/coverage/default/32.chip_sw_all_escalation_resets.3293553552 May 30 04:37:01 PM PDT 24 May 30 04:50:03 PM PDT 24 4471879530 ps
T714 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1446192071 May 30 04:42:12 PM PDT 24 May 30 04:48:12 PM PDT 24 3889137344 ps
T1271 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.3658367878 May 30 04:30:37 PM PDT 24 May 30 04:44:40 PM PDT 24 5783693900 ps
T1272 /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3558266694 May 30 04:28:36 PM PDT 24 May 30 04:31:25 PM PDT 24 3320531539 ps
T60 /workspace/coverage/default/2.chip_sw_alert_test.4180922753 May 30 04:30:34 PM PDT 24 May 30 04:37:14 PM PDT 24 3236285994 ps
T1273 /workspace/coverage/default/0.chip_sw_kmac_smoketest.2120460962 May 30 04:14:54 PM PDT 24 May 30 04:20:33 PM PDT 24 3234905920 ps
T331 /workspace/coverage/default/2.chip_plic_all_irqs_0.1189013651 May 30 04:30:17 PM PDT 24 May 30 04:43:46 PM PDT 24 5593372194 ps
T1274 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1372196139 May 30 04:15:11 PM PDT 24 May 30 04:42:57 PM PDT 24 7682603859 ps
T1275 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.3575210068 May 30 04:28:49 PM PDT 24 May 30 04:37:26 PM PDT 24 2985098062 ps
T1276 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.779348433 May 30 04:21:15 PM PDT 24 May 30 04:33:18 PM PDT 24 4617231400 ps
T448 /workspace/coverage/default/2.chip_sw_edn_boot_mode.4081036979 May 30 04:29:42 PM PDT 24 May 30 04:39:35 PM PDT 24 3194261376 ps
T1277 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.787228345 May 30 04:28:12 PM PDT 24 May 30 04:38:05 PM PDT 24 9045046335 ps
T1278 /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.2209171806 May 30 04:37:51 PM PDT 24 May 30 05:23:39 PM PDT 24 13673107624 ps
T1279 /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.2566210844 May 30 04:18:53 PM PDT 24 May 30 04:22:32 PM PDT 24 2512584200 ps
T757 /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.933496150 May 30 04:37:50 PM PDT 24 May 30 04:44:09 PM PDT 24 3645609340 ps
T1280 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.3071593568 May 30 04:10:21 PM PDT 24 May 30 04:14:14 PM PDT 24 2907073441 ps
T1281 /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.2056135224 May 30 04:23:14 PM PDT 24 May 30 04:55:01 PM PDT 24 9603171240 ps
T1282 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.1602450188 May 30 04:18:20 PM PDT 24 May 30 04:26:40 PM PDT 24 3951770952 ps
T1283 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.3069095457 May 30 04:15:17 PM PDT 24 May 30 04:24:41 PM PDT 24 4600621219 ps
T1284 /workspace/coverage/default/1.chip_sw_aes_entropy.594824282 May 30 04:18:41 PM PDT 24 May 30 04:23:15 PM PDT 24 2917512796 ps
T202 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.1704234135 May 30 04:16:12 PM PDT 24 May 30 04:53:00 PM PDT 24 21687205624 ps
T186 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.1038082180 May 30 04:15:51 PM PDT 24 May 30 04:29:00 PM PDT 24 6385609070 ps
T1285 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.179045493 May 30 04:15:38 PM PDT 24 May 30 04:23:35 PM PDT 24 6269996930 ps
T1286 /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.977979805 May 30 04:18:34 PM PDT 24 May 30 04:27:09 PM PDT 24 5737426288 ps
T1287 /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.143802616 May 30 04:14:43 PM PDT 24 May 30 04:25:25 PM PDT 24 7545601130 ps
T1288 /workspace/coverage/default/1.chip_sw_example_rom.4175626018 May 30 04:13:19 PM PDT 24 May 30 04:15:36 PM PDT 24 3159643336 ps
T1289 /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1308039826 May 30 04:28:53 PM PDT 24 May 30 04:37:38 PM PDT 24 19321005480 ps
T1290 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.1026864257 May 30 04:20:12 PM PDT 24 May 30 04:29:18 PM PDT 24 5036912442 ps
T1291 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.2254715171 May 30 04:19:55 PM PDT 24 May 30 04:28:05 PM PDT 24 8602594640 ps
T1292 /workspace/coverage/default/1.chip_sw_kmac_entropy.3257421083 May 30 04:14:45 PM PDT 24 May 30 04:19:19 PM PDT 24 3331752958 ps
T725 /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.78759527 May 30 04:42:47 PM PDT 24 May 30 04:49:59 PM PDT 24 3563121792 ps
T1293 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3386945158 May 30 04:41:30 PM PDT 24 May 30 04:46:14 PM PDT 24 3484000190 ps
T1294 /workspace/coverage/default/2.chip_sw_kmac_app_rom.432958468 May 30 04:29:24 PM PDT 24 May 30 04:32:58 PM PDT 24 2590903000 ps
T1295 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2911847588 May 30 04:33:53 PM PDT 24 May 30 04:40:46 PM PDT 24 6397988560 ps
T180 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.4042606821 May 30 04:09:48 PM PDT 24 May 30 05:26:49 PM PDT 24 44610161049 ps
T421 /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.2111395779 May 30 04:30:09 PM PDT 24 May 30 04:36:13 PM PDT 24 3915419800 ps
T1296 /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.6699499 May 30 04:10:07 PM PDT 24 May 30 04:12:29 PM PDT 24 2543343615 ps
T1297 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1370553648 May 30 04:21:42 PM PDT 24 May 30 05:20:09 PM PDT 24 13765748240 ps
T1298 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.4103879857 May 30 04:24:36 PM PDT 24 May 30 04:44:22 PM PDT 24 6048859172 ps
T1299 /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.1435787428 May 30 04:25:40 PM PDT 24 May 30 04:34:16 PM PDT 24 3418392200 ps
T64 /workspace/coverage/default/0.chip_tap_straps_rma.2198609147 May 30 04:11:38 PM PDT 24 May 30 04:15:56 PM PDT 24 3728895890 ps
T1300 /workspace/coverage/default/93.chip_sw_all_escalation_resets.3410661463 May 30 04:42:45 PM PDT 24 May 30 04:52:16 PM PDT 24 5080876600 ps
T1301 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.1236461876 May 30 04:29:08 PM PDT 24 May 30 04:32:32 PM PDT 24 2627289504 ps
T1302 /workspace/coverage/default/0.rom_keymgr_functest.3756553592 May 30 04:16:39 PM PDT 24 May 30 04:28:37 PM PDT 24 4405158356 ps
T254 /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.1730543678 May 30 04:35:34 PM PDT 24 May 30 04:42:05 PM PDT 24 3870742948 ps
T1303 /workspace/coverage/default/0.chip_sw_aes_idle.3479164835 May 30 04:11:47 PM PDT 24 May 30 04:16:54 PM PDT 24 3353901256 ps
T1304 /workspace/coverage/default/0.chip_sw_uart_smoketest.293728514 May 30 04:14:25 PM PDT 24 May 30 04:18:55 PM PDT 24 2738418680 ps
T73 /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.1227764513 May 30 03:50:44 PM PDT 24 May 30 03:56:27 PM PDT 24 9267554777 ps
T74 /workspace/coverage/cover_reg_top/23.xbar_smoke.585927891 May 30 03:50:21 PM PDT 24 May 30 03:50:28 PM PDT 24 43058285 ps
T75 /workspace/coverage/cover_reg_top/59.xbar_random.1126642664 May 30 03:55:28 PM PDT 24 May 30 03:56:22 PM PDT 24 1474549408 ps
T144 /workspace/coverage/cover_reg_top/9.xbar_smoke.520843225 May 30 03:48:57 PM PDT 24 May 30 03:49:07 PM PDT 24 158545797 ps
T79 /workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.410335266 May 30 03:50:50 PM PDT 24 May 30 04:06:07 PM PDT 24 50689143887 ps
T454 /workspace/coverage/cover_reg_top/29.xbar_stress_all.1203909980 May 30 03:51:21 PM PDT 24 May 30 03:55:55 PM PDT 24 6058136084 ps
T136 /workspace/coverage/cover_reg_top/3.chip_csr_rw.1474063326 May 30 03:48:49 PM PDT 24 May 30 03:58:21 PM PDT 24 5874587214 ps
T255 /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.3587098334 May 30 03:57:18 PM PDT 24 May 30 03:59:05 PM PDT 24 1411213643 ps
T527 /workspace/coverage/cover_reg_top/35.xbar_smoke.217142320 May 30 03:52:02 PM PDT 24 May 30 03:52:10 PM PDT 24 39463802 ps
T529 /workspace/coverage/cover_reg_top/98.xbar_random_large_delays.3123096337 May 30 04:01:16 PM PDT 24 May 30 04:09:08 PM PDT 24 45787869195 ps
T528 /workspace/coverage/cover_reg_top/24.xbar_smoke.1096616499 May 30 03:50:32 PM PDT 24 May 30 03:50:39 PM PDT 24 45319645 ps
T536 /workspace/coverage/cover_reg_top/37.xbar_smoke.3564058221 May 30 03:52:14 PM PDT 24 May 30 03:52:25 PM PDT 24 199023029 ps
T534 /workspace/coverage/cover_reg_top/83.xbar_stress_all.2573527972 May 30 03:59:11 PM PDT 24 May 30 04:01:16 PM PDT 24 3232404705 ps
T473 /workspace/coverage/cover_reg_top/61.xbar_random_slow_rsp.3103585192 May 30 03:55:43 PM PDT 24 May 30 04:09:13 PM PDT 24 45160406961 ps
T539 /workspace/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.376562861 May 30 03:50:40 PM PDT 24 May 30 03:52:12 PM PDT 24 5410128549 ps
T449 /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.3328794463 May 30 03:51:34 PM PDT 24 May 30 03:53:03 PM PDT 24 199508340 ps
T538 /workspace/coverage/cover_reg_top/64.xbar_smoke_large_delays.3450201984 May 30 03:56:16 PM PDT 24 May 30 03:57:48 PM PDT 24 8438551997 ps
T533 /workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.1579881295 May 30 03:55:11 PM PDT 24 May 30 03:55:48 PM PDT 24 855837725 ps
T524 /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.2847755616 May 30 03:51:55 PM PDT 24 May 30 03:53:14 PM PDT 24 2076951247 ps
T525 /workspace/coverage/cover_reg_top/28.xbar_stress_all.4170866071 May 30 03:51:08 PM PDT 24 May 30 03:52:53 PM PDT 24 2923727149 ps
T537 /workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.3163691769 May 30 03:49:04 PM PDT 24 May 30 03:49:10 PM PDT 24 35767762 ps
T532 /workspace/coverage/cover_reg_top/29.xbar_unmapped_addr.179269313 May 30 03:51:21 PM PDT 24 May 30 03:51:45 PM PDT 24 474399809 ps
T641 /workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.1054463203 May 30 03:49:24 PM PDT 24 May 30 03:49:30 PM PDT 24 37695147 ps
T521 /workspace/coverage/cover_reg_top/70.xbar_access_same_device.3821589695 May 30 03:57:06 PM PDT 24 May 30 03:59:05 PM PDT 24 2767275884 ps
T522 /workspace/coverage/cover_reg_top/11.xbar_stress_all.2489762348 May 30 03:49:17 PM PDT 24 May 30 03:50:31 PM PDT 24 750583875 ps
T469 /workspace/coverage/cover_reg_top/11.xbar_random_large_delays.1520224933 May 30 03:49:07 PM PDT 24 May 30 04:04:00 PM PDT 24 77381385123 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%