| T732 |
/workspace/coverage/default/82.chip_sw_all_escalation_resets.3344022435 |
|
|
May 30 04:41:58 PM PDT 24 |
May 30 04:50:11 PM PDT 24 |
4434630024 ps |
| T22 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1235196643 |
|
|
May 30 04:09:20 PM PDT 24 |
May 30 04:14:13 PM PDT 24 |
3017049569 ps |
| T211 |
/workspace/coverage/default/2.chip_sw_gpio_smoketest.210604582 |
|
|
May 30 04:31:15 PM PDT 24 |
May 30 04:34:30 PM PDT 24 |
2121067218 ps |
| T1006 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.2513459594 |
|
|
May 30 04:26:35 PM PDT 24 |
May 30 04:30:57 PM PDT 24 |
3084957400 ps |
| T1007 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1955107171 |
|
|
May 30 04:12:02 PM PDT 24 |
May 30 04:20:47 PM PDT 24 |
7568958992 ps |
| T443 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3569676372 |
|
|
May 30 04:19:55 PM PDT 24 |
May 30 04:40:55 PM PDT 24 |
7068839766 ps |
| T1008 |
/workspace/coverage/default/2.rom_e2e_asm_init_dev.2124686160 |
|
|
May 30 04:36:28 PM PDT 24 |
May 30 05:26:53 PM PDT 24 |
14545700612 ps |
| T119 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3773361687 |
|
|
May 30 04:29:29 PM PDT 24 |
May 30 04:35:59 PM PDT 24 |
5011162604 ps |
| T655 |
/workspace/coverage/default/0.rom_volatile_raw_unlock.2902732855 |
|
|
May 30 04:15:56 PM PDT 24 |
May 30 04:17:39 PM PDT 24 |
2599804369 ps |
| T1009 |
/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.2187192334 |
|
|
May 30 04:20:09 PM PDT 24 |
May 30 05:11:01 PM PDT 24 |
10962174807 ps |
| T1010 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.45899245 |
|
|
May 30 04:18:33 PM PDT 24 |
May 30 04:24:11 PM PDT 24 |
2475399965 ps |
| T1011 |
/workspace/coverage/default/2.chip_sw_aes_entropy.4224819099 |
|
|
May 30 04:27:39 PM PDT 24 |
May 30 04:31:47 PM PDT 24 |
3463824088 ps |
| T125 |
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.533121725 |
|
|
May 30 04:31:53 PM PDT 24 |
May 30 04:41:39 PM PDT 24 |
3928669000 ps |
| T384 |
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2344909956 |
|
|
May 30 04:41:49 PM PDT 24 |
May 30 04:48:04 PM PDT 24 |
4156175760 ps |
| T1012 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.1676637448 |
|
|
May 30 04:19:14 PM PDT 24 |
May 30 04:25:40 PM PDT 24 |
3228121380 ps |
| T1013 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2625545478 |
|
|
May 30 04:32:12 PM PDT 24 |
May 30 04:53:28 PM PDT 24 |
7146748113 ps |
| T120 |
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2168140122 |
|
|
May 30 04:32:38 PM PDT 24 |
May 30 04:43:14 PM PDT 24 |
7405300560 ps |
| T350 |
/workspace/coverage/default/16.chip_sw_all_escalation_resets.3900555731 |
|
|
May 30 04:39:39 PM PDT 24 |
May 30 04:49:59 PM PDT 24 |
4391637530 ps |
| T1014 |
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.2745489876 |
|
|
May 30 04:34:00 PM PDT 24 |
May 30 04:47:24 PM PDT 24 |
11364158532 ps |
| T743 |
/workspace/coverage/default/38.chip_sw_all_escalation_resets.1062478392 |
|
|
May 30 04:37:25 PM PDT 24 |
May 30 04:48:19 PM PDT 24 |
4435606574 ps |
| T1015 |
/workspace/coverage/default/1.chip_sw_csrng_smoketest.2916961338 |
|
|
May 30 04:23:07 PM PDT 24 |
May 30 04:26:35 PM PDT 24 |
2349152160 ps |
| T1016 |
/workspace/coverage/default/2.chip_sw_otbn_randomness.1305659854 |
|
|
May 30 04:27:04 PM PDT 24 |
May 30 04:45:58 PM PDT 24 |
5901904520 ps |
| T1017 |
/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.4136327655 |
|
|
May 30 04:25:20 PM PDT 24 |
May 30 04:34:58 PM PDT 24 |
3869267892 ps |
| T357 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1679729334 |
|
|
May 30 04:10:54 PM PDT 24 |
May 30 04:20:18 PM PDT 24 |
18715057400 ps |
| T1018 |
/workspace/coverage/default/1.rom_e2e_shutdown_output.873471981 |
|
|
May 30 04:29:09 PM PDT 24 |
May 30 05:21:45 PM PDT 24 |
22153015426 ps |
| T1019 |
/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.3478769674 |
|
|
May 30 04:19:41 PM PDT 24 |
May 30 04:31:43 PM PDT 24 |
4607558204 ps |
| T1020 |
/workspace/coverage/default/3.chip_tap_straps_dev.579915484 |
|
|
May 30 04:34:03 PM PDT 24 |
May 30 04:49:48 PM PDT 24 |
10629253049 ps |
| T87 |
/workspace/coverage/default/96.chip_sw_all_escalation_resets.651336699 |
|
|
May 30 04:43:04 PM PDT 24 |
May 30 04:52:28 PM PDT 24 |
5145458060 ps |
| T1021 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.513056428 |
|
|
May 30 04:26:44 PM PDT 24 |
May 30 04:33:11 PM PDT 24 |
2917963407 ps |
| T772 |
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3414957386 |
|
|
May 30 04:46:58 PM PDT 24 |
May 30 04:53:19 PM PDT 24 |
3355794096 ps |
| T721 |
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.885317949 |
|
|
May 30 04:37:40 PM PDT 24 |
May 30 04:45:05 PM PDT 24 |
3795840790 ps |
| T426 |
/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.698086294 |
|
|
May 30 04:17:54 PM PDT 24 |
May 30 04:26:12 PM PDT 24 |
8901204461 ps |
| T1022 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.2864018166 |
|
|
May 30 04:24:54 PM PDT 24 |
May 30 04:35:10 PM PDT 24 |
7710586938 ps |
| T1023 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod.2556289381 |
|
|
May 30 04:36:12 PM PDT 24 |
May 30 05:31:46 PM PDT 24 |
14042259097 ps |
| T1024 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.285299863 |
|
|
May 30 04:19:49 PM PDT 24 |
May 30 04:24:14 PM PDT 24 |
3222839600 ps |
| T1025 |
/workspace/coverage/default/0.chip_sw_example_concurrency.2772398852 |
|
|
May 30 04:09:49 PM PDT 24 |
May 30 04:13:54 PM PDT 24 |
2399803846 ps |
| T729 |
/workspace/coverage/default/33.chip_sw_all_escalation_resets.449966064 |
|
|
May 30 04:38:03 PM PDT 24 |
May 30 04:49:02 PM PDT 24 |
5074982880 ps |
| T197 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3391176183 |
|
|
May 30 04:17:17 PM PDT 24 |
May 30 04:22:34 PM PDT 24 |
3171353049 ps |
| T1026 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.1546025799 |
|
|
May 30 04:26:18 PM PDT 24 |
May 30 04:50:02 PM PDT 24 |
7212898602 ps |
| T362 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.1623066004 |
|
|
May 30 04:29:16 PM PDT 24 |
May 30 04:34:00 PM PDT 24 |
2618445044 ps |
| T1027 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.924910164 |
|
|
May 30 04:29:06 PM PDT 24 |
May 30 04:41:49 PM PDT 24 |
4526986056 ps |
| T1028 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.3200521557 |
|
|
May 30 04:11:19 PM PDT 24 |
May 30 05:02:43 PM PDT 24 |
16640220664 ps |
| T16 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.892173346 |
|
|
May 30 04:13:07 PM PDT 24 |
May 30 04:36:11 PM PDT 24 |
19533093930 ps |
| T1029 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.2172497556 |
|
|
May 30 04:11:19 PM PDT 24 |
May 30 04:20:08 PM PDT 24 |
5994026776 ps |
| T1030 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.560931242 |
|
|
May 30 04:11:14 PM PDT 24 |
May 30 04:23:08 PM PDT 24 |
3861920332 ps |
| T705 |
/workspace/coverage/default/46.chip_sw_all_escalation_resets.3148332149 |
|
|
May 30 04:38:57 PM PDT 24 |
May 30 04:53:26 PM PDT 24 |
5794963552 ps |
| T1031 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.671472027 |
|
|
May 30 04:27:58 PM PDT 24 |
May 30 04:52:57 PM PDT 24 |
14440222445 ps |
| T773 |
/workspace/coverage/default/92.chip_sw_all_escalation_resets.2071937415 |
|
|
May 30 04:46:48 PM PDT 24 |
May 30 04:58:46 PM PDT 24 |
5599389800 ps |
| T734 |
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.118168097 |
|
|
May 30 04:40:36 PM PDT 24 |
May 30 04:46:16 PM PDT 24 |
3311948930 ps |
| T1032 |
/workspace/coverage/default/0.chip_sw_otbn_randomness.1769419836 |
|
|
May 30 04:11:21 PM PDT 24 |
May 30 04:25:55 PM PDT 24 |
5815173700 ps |
| T1033 |
/workspace/coverage/default/60.chip_sw_all_escalation_resets.1908387921 |
|
|
May 30 04:41:48 PM PDT 24 |
May 30 04:49:49 PM PDT 24 |
6056486130 ps |
| T233 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.589548053 |
|
|
May 30 04:15:51 PM PDT 24 |
May 30 04:57:57 PM PDT 24 |
13301244244 ps |
| T771 |
/workspace/coverage/default/22.chip_sw_all_escalation_resets.2836937569 |
|
|
May 30 04:36:56 PM PDT 24 |
May 30 04:46:56 PM PDT 24 |
5504882880 ps |
| T344 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.872952989 |
|
|
May 30 04:15:32 PM PDT 24 |
May 30 04:29:40 PM PDT 24 |
4575453586 ps |
| T735 |
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3001137267 |
|
|
May 30 04:37:52 PM PDT 24 |
May 30 04:44:39 PM PDT 24 |
3956382444 ps |
| T337 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.3742718800 |
|
|
May 30 04:27:40 PM PDT 24 |
May 30 04:41:41 PM PDT 24 |
5322637696 ps |
| T205 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.3842626436 |
|
|
May 30 04:11:56 PM PDT 24 |
May 30 04:35:51 PM PDT 24 |
6897062464 ps |
| T253 |
/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.4203698072 |
|
|
May 30 04:37:31 PM PDT 24 |
May 30 04:45:37 PM PDT 24 |
3591330394 ps |
| T287 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.3932847735 |
|
|
May 30 04:16:36 PM PDT 24 |
May 30 04:52:32 PM PDT 24 |
32472832520 ps |
| T288 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1245151350 |
|
|
May 30 04:10:56 PM PDT 24 |
May 30 04:15:21 PM PDT 24 |
2690163773 ps |
| T36 |
/workspace/coverage/default/0.chip_sw_usbdev_stream.693011615 |
|
|
May 30 04:09:29 PM PDT 24 |
May 30 05:19:12 PM PDT 24 |
18506526110 ps |
| T289 |
/workspace/coverage/default/0.chip_sival_flash_info_access.179324559 |
|
|
May 30 04:09:16 PM PDT 24 |
May 30 04:14:23 PM PDT 24 |
3074337078 ps |
| T290 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.2892365017 |
|
|
May 30 04:37:29 PM PDT 24 |
May 30 05:30:22 PM PDT 24 |
14728091572 ps |
| T291 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.3655694854 |
|
|
May 30 04:35:22 PM PDT 24 |
May 30 04:40:38 PM PDT 24 |
4017765256 ps |
| T292 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.4111279109 |
|
|
May 30 04:11:13 PM PDT 24 |
May 30 04:19:59 PM PDT 24 |
5995748672 ps |
| T293 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.2551403210 |
|
|
May 30 04:33:34 PM PDT 24 |
May 30 05:01:59 PM PDT 24 |
8609223537 ps |
| T294 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.955377451 |
|
|
May 30 04:21:16 PM PDT 24 |
May 30 04:29:36 PM PDT 24 |
4143184744 ps |
| T1034 |
/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.4070680372 |
|
|
May 30 04:33:48 PM PDT 24 |
May 30 04:49:14 PM PDT 24 |
10056850715 ps |
| T122 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1264128867 |
|
|
May 30 04:18:50 PM PDT 24 |
May 30 04:25:31 PM PDT 24 |
5663004200 ps |
| T259 |
/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1200310724 |
|
|
May 30 04:19:53 PM PDT 24 |
May 30 04:31:09 PM PDT 24 |
4448653256 ps |
| T1035 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx.2619241032 |
|
|
May 30 04:33:45 PM PDT 24 |
May 30 04:44:50 PM PDT 24 |
4112436840 ps |
| T1036 |
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1688793627 |
|
|
May 30 04:41:20 PM PDT 24 |
May 30 04:46:21 PM PDT 24 |
4078290368 ps |
| T1037 |
/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.1519060788 |
|
|
May 30 04:11:34 PM PDT 24 |
May 30 04:40:41 PM PDT 24 |
10233033999 ps |
| T427 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.1660777648 |
|
|
May 30 04:13:21 PM PDT 24 |
May 30 04:16:38 PM PDT 24 |
2610714262 ps |
| T38 |
/workspace/coverage/default/1.chip_sw_gpio.2627285285 |
|
|
May 30 04:14:53 PM PDT 24 |
May 30 04:22:47 PM PDT 24 |
3369106206 ps |
| T1038 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2408562772 |
|
|
May 30 04:29:54 PM PDT 24 |
May 30 04:40:11 PM PDT 24 |
4179605912 ps |
| T756 |
/workspace/coverage/default/37.chip_sw_all_escalation_resets.4264299679 |
|
|
May 30 04:36:43 PM PDT 24 |
May 30 04:47:11 PM PDT 24 |
5202818404 ps |
| T1039 |
/workspace/coverage/default/1.chip_sw_power_idle_load.2581438760 |
|
|
May 30 04:22:30 PM PDT 24 |
May 30 04:35:42 PM PDT 24 |
4800010200 ps |
| T1040 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.1936460846 |
|
|
May 30 04:11:56 PM PDT 24 |
May 30 04:28:07 PM PDT 24 |
5277504000 ps |
| T1041 |
/workspace/coverage/default/0.chip_sw_aes_entropy.4037178701 |
|
|
May 30 04:13:35 PM PDT 24 |
May 30 04:17:19 PM PDT 24 |
2010717036 ps |
| T765 |
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1498269827 |
|
|
May 30 04:36:48 PM PDT 24 |
May 30 04:42:34 PM PDT 24 |
3038348120 ps |
| T1042 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.2918143271 |
|
|
May 30 04:16:47 PM PDT 24 |
May 30 04:34:35 PM PDT 24 |
8432687908 ps |
| T128 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2430548393 |
|
|
May 30 04:11:35 PM PDT 24 |
May 30 04:18:39 PM PDT 24 |
4938326612 ps |
| T1043 |
/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1292449898 |
|
|
May 30 04:11:19 PM PDT 24 |
May 30 04:20:35 PM PDT 24 |
4683869740 ps |
| T1044 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2973343274 |
|
|
May 30 04:29:00 PM PDT 24 |
May 30 04:38:27 PM PDT 24 |
5445746946 ps |
| T1045 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.4216986363 |
|
|
May 30 04:12:28 PM PDT 24 |
May 30 05:20:15 PM PDT 24 |
24653234791 ps |
| T702 |
/workspace/coverage/default/76.chip_sw_all_escalation_resets.1795222279 |
|
|
May 30 04:41:43 PM PDT 24 |
May 30 04:52:01 PM PDT 24 |
4571948936 ps |
| T1046 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.2574633375 |
|
|
May 30 04:24:17 PM PDT 24 |
May 30 04:38:21 PM PDT 24 |
4856988500 ps |
| T139 |
/workspace/coverage/default/0.chip_sw_usbdev_dpi.2274974207 |
|
|
May 30 04:11:03 PM PDT 24 |
May 30 04:59:54 PM PDT 24 |
12357962166 ps |
| T1047 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.1841485496 |
|
|
May 30 04:35:34 PM PDT 24 |
May 30 05:23:50 PM PDT 24 |
14272430416 ps |
| T206 |
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3763306812 |
|
|
May 30 04:42:41 PM PDT 24 |
May 30 04:48:40 PM PDT 24 |
3162268264 ps |
| T283 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.1745119312 |
|
|
May 30 04:28:00 PM PDT 24 |
May 30 04:42:22 PM PDT 24 |
7636082970 ps |
| T1048 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.1563022558 |
|
|
May 30 04:24:51 PM PDT 24 |
May 30 04:43:36 PM PDT 24 |
8068553742 ps |
| T1049 |
/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.1986372447 |
|
|
May 30 04:19:15 PM PDT 24 |
May 30 05:11:34 PM PDT 24 |
14029625915 ps |
| T716 |
/workspace/coverage/default/12.chip_sw_all_escalation_resets.1425516703 |
|
|
May 30 04:35:09 PM PDT 24 |
May 30 04:46:01 PM PDT 24 |
4487885008 ps |
| T88 |
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2503077085 |
|
|
May 30 04:41:33 PM PDT 24 |
May 30 04:46:44 PM PDT 24 |
4065594448 ps |
| T752 |
/workspace/coverage/default/68.chip_sw_all_escalation_resets.3802482552 |
|
|
May 30 04:41:57 PM PDT 24 |
May 30 04:51:13 PM PDT 24 |
5425284232 ps |
| T1050 |
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3234231071 |
|
|
May 30 04:38:27 PM PDT 24 |
May 30 04:44:43 PM PDT 24 |
3648618992 ps |
| T1051 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1551982045 |
|
|
May 30 04:11:21 PM PDT 24 |
May 30 04:38:24 PM PDT 24 |
10642286082 ps |
| T1052 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.226236861 |
|
|
May 30 04:28:30 PM PDT 24 |
May 30 04:54:03 PM PDT 24 |
9162526298 ps |
| T1053 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3588327235 |
|
|
May 30 04:11:43 PM PDT 24 |
May 30 05:09:13 PM PDT 24 |
18702967591 ps |
| T1054 |
/workspace/coverage/default/65.chip_sw_all_escalation_resets.2778484999 |
|
|
May 30 04:42:33 PM PDT 24 |
May 30 04:53:34 PM PDT 24 |
4652474236 ps |
| T1055 |
/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.2773221546 |
|
|
May 30 04:33:21 PM PDT 24 |
May 30 04:42:31 PM PDT 24 |
3144112564 ps |
| T1056 |
/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.2816666914 |
|
|
May 30 04:23:04 PM PDT 24 |
May 30 04:33:58 PM PDT 24 |
3195139800 ps |
| T1057 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.914641119 |
|
|
May 30 04:18:24 PM PDT 24 |
May 30 05:08:08 PM PDT 24 |
14039551884 ps |
| T769 |
/workspace/coverage/default/8.chip_sw_all_escalation_resets.16694476 |
|
|
May 30 04:33:56 PM PDT 24 |
May 30 04:46:40 PM PDT 24 |
4917842762 ps |
| T1058 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.2043529421 |
|
|
May 30 04:21:14 PM PDT 24 |
May 30 04:38:24 PM PDT 24 |
5329085920 ps |
| T1059 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.4122392739 |
|
|
May 30 04:25:01 PM PDT 24 |
May 30 04:32:58 PM PDT 24 |
4816596348 ps |
| T1060 |
/workspace/coverage/default/1.chip_sw_example_flash.1422285500 |
|
|
May 30 04:16:02 PM PDT 24 |
May 30 04:19:05 PM PDT 24 |
2591222320 ps |
| T656 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.2220788699 |
|
|
May 30 04:15:16 PM PDT 24 |
May 30 04:19:14 PM PDT 24 |
2810471250 ps |
| T268 |
/workspace/coverage/default/62.chip_sw_all_escalation_resets.187491013 |
|
|
May 30 04:41:27 PM PDT 24 |
May 30 04:49:49 PM PDT 24 |
5027260570 ps |
| T1061 |
/workspace/coverage/default/2.chip_sw_aes_idle.2642635736 |
|
|
May 30 04:27:57 PM PDT 24 |
May 30 04:31:53 PM PDT 24 |
3128640494 ps |
| T1062 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.1193452882 |
|
|
May 30 04:18:08 PM PDT 24 |
May 30 04:29:09 PM PDT 24 |
7554541894 ps |
| T321 |
/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.2984025712 |
|
|
May 30 04:20:00 PM PDT 24 |
May 30 04:44:39 PM PDT 24 |
12254694320 ps |
| T370 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.854004978 |
|
|
May 30 04:37:32 PM PDT 24 |
May 30 04:44:02 PM PDT 24 |
3771431432 ps |
| T371 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2894019064 |
|
|
May 30 04:41:47 PM PDT 24 |
May 30 04:47:12 PM PDT 24 |
3175612210 ps |
| T1063 |
/workspace/coverage/default/2.chip_sw_aes_enc.2064286769 |
|
|
May 30 04:26:54 PM PDT 24 |
May 30 04:30:21 PM PDT 24 |
2753228094 ps |
| T746 |
/workspace/coverage/default/98.chip_sw_all_escalation_resets.3988578182 |
|
|
May 30 04:41:24 PM PDT 24 |
May 30 04:49:58 PM PDT 24 |
5485099558 ps |
| T1064 |
/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.1067349886 |
|
|
May 30 04:09:37 PM PDT 24 |
May 30 04:19:52 PM PDT 24 |
5182074120 ps |
| T82 |
/workspace/coverage/default/1.chip_sw_alert_handler_entropy.1704881403 |
|
|
May 30 04:16:52 PM PDT 24 |
May 30 04:22:46 PM PDT 24 |
3061487574 ps |
| T1065 |
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2830497868 |
|
|
May 30 04:43:24 PM PDT 24 |
May 30 04:48:42 PM PDT 24 |
3414355016 ps |
| T1066 |
/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.2680606246 |
|
|
May 30 04:24:15 PM PDT 24 |
May 30 04:56:46 PM PDT 24 |
22988379368 ps |
| T1067 |
/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.797243526 |
|
|
May 30 04:31:26 PM PDT 24 |
May 30 04:43:05 PM PDT 24 |
3671577464 ps |
| T70 |
/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1143664125 |
|
|
May 30 04:10:20 PM PDT 24 |
May 30 04:17:28 PM PDT 24 |
4046147428 ps |
| T284 |
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.3136260535 |
|
|
May 30 04:35:48 PM PDT 24 |
May 30 04:47:47 PM PDT 24 |
6322239110 ps |
| T762 |
/workspace/coverage/default/29.chip_sw_all_escalation_resets.2766632648 |
|
|
May 30 04:35:13 PM PDT 24 |
May 30 04:48:32 PM PDT 24 |
5174508344 ps |
| T750 |
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1651611181 |
|
|
May 30 04:42:16 PM PDT 24 |
May 30 04:49:05 PM PDT 24 |
3688024424 ps |
| T1068 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.2949131160 |
|
|
May 30 04:27:42 PM PDT 24 |
May 30 04:51:06 PM PDT 24 |
8999594385 ps |
| T1069 |
/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2088584806 |
|
|
May 30 04:13:55 PM PDT 24 |
May 30 04:24:17 PM PDT 24 |
4493562138 ps |
| T689 |
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.2472153445 |
|
|
May 30 04:40:15 PM PDT 24 |
May 30 04:46:53 PM PDT 24 |
3842480414 ps |
| T1070 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.1438131510 |
|
|
May 30 04:15:13 PM PDT 24 |
May 30 04:38:18 PM PDT 24 |
6885004944 ps |
| T710 |
/workspace/coverage/default/66.chip_sw_all_escalation_resets.4191121714 |
|
|
May 30 04:42:10 PM PDT 24 |
May 30 04:52:53 PM PDT 24 |
5280533516 ps |
| T260 |
/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3879126611 |
|
|
May 30 04:29:46 PM PDT 24 |
May 30 04:38:03 PM PDT 24 |
3675466456 ps |
| T720 |
/workspace/coverage/default/90.chip_sw_all_escalation_resets.1120847974 |
|
|
May 30 04:46:55 PM PDT 24 |
May 30 04:56:58 PM PDT 24 |
6081311100 ps |
| T198 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.1672475397 |
|
|
May 30 04:25:46 PM PDT 24 |
May 30 04:36:35 PM PDT 24 |
4697169347 ps |
| T1071 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.1025726024 |
|
|
May 30 04:11:25 PM PDT 24 |
May 30 04:23:01 PM PDT 24 |
4842721841 ps |
| T1072 |
/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.246806446 |
|
|
May 30 04:34:21 PM PDT 24 |
May 30 04:51:53 PM PDT 24 |
9972875040 ps |
| T1073 |
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.2920019496 |
|
|
May 30 04:33:09 PM PDT 24 |
May 30 04:52:22 PM PDT 24 |
13596381521 ps |
| T1074 |
/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.3567796324 |
|
|
May 30 04:35:13 PM PDT 24 |
May 30 05:10:11 PM PDT 24 |
12695310920 ps |
| T697 |
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.4280558396 |
|
|
May 30 04:41:54 PM PDT 24 |
May 30 04:48:10 PM PDT 24 |
3034183706 ps |
| T1075 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1081098808 |
|
|
May 30 04:32:15 PM PDT 24 |
May 30 04:37:25 PM PDT 24 |
2347896618 ps |
| T1076 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3810469062 |
|
|
May 30 04:13:25 PM PDT 24 |
May 30 04:17:52 PM PDT 24 |
2487850449 ps |
| T1077 |
/workspace/coverage/default/2.chip_sw_edn_sw_mode.2417381637 |
|
|
May 30 04:28:01 PM PDT 24 |
May 30 04:44:07 PM PDT 24 |
5242719444 ps |
| T97 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.117176950 |
|
|
May 30 04:32:14 PM PDT 24 |
May 30 04:57:48 PM PDT 24 |
22095131794 ps |
| T1078 |
/workspace/coverage/default/2.chip_sw_edn_auto_mode.2615290114 |
|
|
May 30 04:31:20 PM PDT 24 |
May 30 04:54:07 PM PDT 24 |
6334177930 ps |
| T1079 |
/workspace/coverage/default/1.chip_sw_hmac_enc_idle.1765745054 |
|
|
May 30 04:20:07 PM PDT 24 |
May 30 04:25:35 PM PDT 24 |
2633020580 ps |
| T1080 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.1524841674 |
|
|
May 30 04:16:52 PM PDT 24 |
May 30 04:20:07 PM PDT 24 |
2790521100 ps |
| T304 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.2471499035 |
|
|
May 30 04:10:56 PM PDT 24 |
May 30 04:23:45 PM PDT 24 |
7186919400 ps |
| T1081 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1397490299 |
|
|
May 30 04:29:08 PM PDT 24 |
May 30 04:39:54 PM PDT 24 |
3491173508 ps |
| T1082 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.1678081227 |
|
|
May 30 04:24:05 PM PDT 24 |
May 30 04:36:27 PM PDT 24 |
5467425002 ps |
| T1083 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.698596649 |
|
|
May 30 04:26:16 PM PDT 24 |
May 30 05:22:01 PM PDT 24 |
14473002200 ps |
| T1084 |
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.260161271 |
|
|
May 30 04:34:51 PM PDT 24 |
May 30 05:11:15 PM PDT 24 |
10939387038 ps |
| T1085 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.2014586608 |
|
|
May 30 04:10:01 PM PDT 24 |
May 30 04:18:14 PM PDT 24 |
4295532028 ps |
| T1086 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.876084629 |
|
|
May 30 04:08:59 PM PDT 24 |
May 30 04:54:47 PM PDT 24 |
13167032573 ps |
| T711 |
/workspace/coverage/default/48.chip_sw_all_escalation_resets.2405595339 |
|
|
May 30 04:42:09 PM PDT 24 |
May 30 04:50:54 PM PDT 24 |
5438834400 ps |
| T1087 |
/workspace/coverage/default/2.chip_tap_straps_testunlock0.3650857213 |
|
|
May 30 04:29:12 PM PDT 24 |
May 30 04:33:15 PM PDT 24 |
3328893360 ps |
| T1088 |
/workspace/coverage/default/0.rom_e2e_smoke.170685463 |
|
|
May 30 04:18:17 PM PDT 24 |
May 30 05:25:46 PM PDT 24 |
15098218732 ps |
| T1089 |
/workspace/coverage/default/1.chip_sw_aes_smoketest.3864174415 |
|
|
May 30 04:25:07 PM PDT 24 |
May 30 04:30:17 PM PDT 24 |
2592862170 ps |
| T1090 |
/workspace/coverage/default/49.chip_sw_all_escalation_resets.4123931658 |
|
|
May 30 04:41:09 PM PDT 24 |
May 30 04:49:50 PM PDT 24 |
5455045008 ps |
| T1091 |
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.533558219 |
|
|
May 30 04:37:14 PM PDT 24 |
May 30 04:43:39 PM PDT 24 |
3698415276 ps |
| T89 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.2962457500 |
|
|
May 30 04:35:28 PM PDT 24 |
May 30 04:41:46 PM PDT 24 |
3361091160 ps |
| T1092 |
/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.2948834187 |
|
|
May 30 04:35:03 PM PDT 24 |
May 30 04:59:08 PM PDT 24 |
8087626056 ps |
| T376 |
/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.186857040 |
|
|
May 30 04:27:08 PM PDT 24 |
May 30 04:38:07 PM PDT 24 |
4903843300 ps |
| T737 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.1682055088 |
|
|
May 30 04:37:21 PM PDT 24 |
May 30 04:46:59 PM PDT 24 |
5207137400 ps |
| T1093 |
/workspace/coverage/default/0.chip_sw_gpio_smoketest.1641125799 |
|
|
May 30 04:14:26 PM PDT 24 |
May 30 04:19:41 PM PDT 24 |
3068809471 ps |
| T1094 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.620718910 |
|
|
May 30 04:20:24 PM PDT 24 |
May 30 05:25:07 PM PDT 24 |
13688513936 ps |
| T713 |
/workspace/coverage/default/41.chip_sw_all_escalation_resets.2997976241 |
|
|
May 30 04:36:37 PM PDT 24 |
May 30 04:46:50 PM PDT 24 |
5189724504 ps |
| T1095 |
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.207289854 |
|
|
May 30 04:42:04 PM PDT 24 |
May 30 04:48:01 PM PDT 24 |
3664776040 ps |
| T1096 |
/workspace/coverage/default/4.chip_tap_straps_dev.628414523 |
|
|
May 30 04:31:32 PM PDT 24 |
May 30 04:34:54 PM PDT 24 |
3151357501 ps |
| T368 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1557167031 |
|
|
May 30 04:19:50 PM PDT 24 |
May 30 04:25:49 PM PDT 24 |
5627812144 ps |
| T23 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.476013744 |
|
|
May 30 04:14:53 PM PDT 24 |
May 30 04:19:09 PM PDT 24 |
2921104175 ps |
| T1097 |
/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.1446504112 |
|
|
May 30 04:23:46 PM PDT 24 |
May 30 04:30:08 PM PDT 24 |
4252257288 ps |
| T247 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.3771449478 |
|
|
May 30 04:28:53 PM PDT 24 |
May 30 05:49:43 PM PDT 24 |
48337374250 ps |
| T1098 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.1062292321 |
|
|
May 30 04:18:00 PM PDT 24 |
May 30 04:41:31 PM PDT 24 |
12468714060 ps |
| T102 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.1396758214 |
|
|
May 30 04:30:11 PM PDT 24 |
May 30 05:03:48 PM PDT 24 |
11098879991 ps |
| T742 |
/workspace/coverage/default/6.chip_sw_all_escalation_resets.1905446006 |
|
|
May 30 04:33:34 PM PDT 24 |
May 30 04:44:22 PM PDT 24 |
4937459428 ps |
| T1099 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.390191201 |
|
|
May 30 04:26:46 PM PDT 24 |
May 30 04:37:58 PM PDT 24 |
4704065740 ps |
| T723 |
/workspace/coverage/default/53.chip_sw_all_escalation_resets.2713127627 |
|
|
May 30 04:40:40 PM PDT 24 |
May 30 04:48:00 PM PDT 24 |
3806136600 ps |
| T285 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3572881678 |
|
|
May 30 04:21:58 PM PDT 24 |
May 30 04:34:49 PM PDT 24 |
5597974388 ps |
| T1100 |
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.3620986090 |
|
|
May 30 04:36:52 PM PDT 24 |
May 30 05:55:32 PM PDT 24 |
22150138990 ps |
| T1101 |
/workspace/coverage/default/0.chip_sw_hmac_enc.438324947 |
|
|
May 30 04:18:55 PM PDT 24 |
May 30 04:25:02 PM PDT 24 |
3580167688 ps |
| T1102 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2121958283 |
|
|
May 30 04:21:35 PM PDT 24 |
May 30 05:15:54 PM PDT 24 |
13891125020 ps |
| T147 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.1454027995 |
|
|
May 30 04:30:01 PM PDT 24 |
May 30 04:42:40 PM PDT 24 |
4659884932 ps |
| T1103 |
/workspace/coverage/default/28.chip_sw_all_escalation_resets.999545294 |
|
|
May 30 04:35:32 PM PDT 24 |
May 30 04:44:31 PM PDT 24 |
4970713644 ps |
| T1104 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.2081784329 |
|
|
May 30 04:18:46 PM PDT 24 |
May 30 04:45:44 PM PDT 24 |
8952793888 ps |
| T149 |
/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3248173347 |
|
|
May 30 04:27:24 PM PDT 24 |
May 30 07:48:18 PM PDT 24 |
256060604840 ps |
| T199 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.4095936429 |
|
|
May 30 04:27:49 PM PDT 24 |
May 30 04:32:55 PM PDT 24 |
2937313424 ps |
| T650 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.1475132256 |
|
|
May 30 04:19:47 PM PDT 24 |
May 30 04:26:24 PM PDT 24 |
4377446586 ps |
| T1105 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1022787116 |
|
|
May 30 04:11:45 PM PDT 24 |
May 30 04:23:31 PM PDT 24 |
4620558664 ps |
| T261 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.28184308 |
|
|
May 30 04:11:44 PM PDT 24 |
May 30 04:22:11 PM PDT 24 |
4192457270 ps |
| T1106 |
/workspace/coverage/default/2.chip_sw_kmac_smoketest.1737621256 |
|
|
May 30 04:31:07 PM PDT 24 |
May 30 04:35:14 PM PDT 24 |
2566560490 ps |
| T706 |
/workspace/coverage/default/88.chip_sw_all_escalation_resets.3983015006 |
|
|
May 30 04:42:01 PM PDT 24 |
May 30 04:51:17 PM PDT 24 |
5488412680 ps |
| T1107 |
/workspace/coverage/default/0.chip_tap_straps_prod.3246110751 |
|
|
May 30 04:12:18 PM PDT 24 |
May 30 04:14:33 PM PDT 24 |
2970817554 ps |
| T1108 |
/workspace/coverage/default/0.chip_sw_example_rom.756824874 |
|
|
May 30 04:09:05 PM PDT 24 |
May 30 04:11:16 PM PDT 24 |
2098945824 ps |
| T49 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1938352406 |
|
|
May 30 04:20:51 PM PDT 24 |
May 30 04:32:00 PM PDT 24 |
5320546668 ps |
| T1109 |
/workspace/coverage/default/87.chip_sw_all_escalation_resets.646349275 |
|
|
May 30 04:43:28 PM PDT 24 |
May 30 04:54:32 PM PDT 24 |
5060643992 ps |
| T1110 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.423535889 |
|
|
May 30 04:11:07 PM PDT 24 |
May 30 04:15:00 PM PDT 24 |
3258725978 ps |
| T1111 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.3981687968 |
|
|
May 30 04:17:58 PM PDT 24 |
May 30 05:26:59 PM PDT 24 |
13582622974 ps |
| T1112 |
/workspace/coverage/default/84.chip_sw_all_escalation_resets.3372663187 |
|
|
May 30 04:43:34 PM PDT 24 |
May 30 04:52:06 PM PDT 24 |
5386016204 ps |
| T313 |
/workspace/coverage/default/1.chip_sw_all_escalation_resets.11441257 |
|
|
May 30 04:15:57 PM PDT 24 |
May 30 04:27:37 PM PDT 24 |
5163401384 ps |
| T1113 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access.1965430101 |
|
|
May 30 04:10:09 PM PDT 24 |
May 30 04:29:38 PM PDT 24 |
5583807380 ps |
| T1114 |
/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.3419901651 |
|
|
May 30 04:29:49 PM PDT 24 |
May 30 05:00:07 PM PDT 24 |
20969089452 ps |
| T221 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3529260177 |
|
|
May 30 04:27:04 PM PDT 24 |
May 30 05:15:59 PM PDT 24 |
20311932907 ps |
| T1115 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2879990865 |
|
|
May 30 04:20:25 PM PDT 24 |
May 30 04:30:14 PM PDT 24 |
5368028900 ps |
| T1116 |
/workspace/coverage/default/1.rom_keymgr_functest.263567251 |
|
|
May 30 04:22:54 PM PDT 24 |
May 30 04:34:01 PM PDT 24 |
4781169346 ps |
| T1117 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3187677795 |
|
|
May 30 04:16:50 PM PDT 24 |
May 30 04:28:55 PM PDT 24 |
4352837695 ps |
| T1118 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.2517997602 |
|
|
May 30 04:12:08 PM PDT 24 |
May 30 04:16:19 PM PDT 24 |
2959725686 ps |
| T1119 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.783049156 |
|
|
May 30 04:29:44 PM PDT 24 |
May 30 04:35:34 PM PDT 24 |
6405175880 ps |
| T257 |
/workspace/coverage/default/2.chip_sw_plic_sw_irq.1641061068 |
|
|
May 30 04:29:57 PM PDT 24 |
May 30 04:34:11 PM PDT 24 |
3041169322 ps |
| T1120 |
/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.3999052935 |
|
|
May 30 04:16:35 PM PDT 24 |
May 30 04:20:05 PM PDT 24 |
2465356040 ps |
| T1121 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.1254205230 |
|
|
May 30 04:26:45 PM PDT 24 |
May 30 05:29:13 PM PDT 24 |
14191905928 ps |
| T517 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3267838494 |
|
|
May 30 04:30:33 PM PDT 24 |
May 30 04:43:19 PM PDT 24 |
4278405384 ps |
| T1122 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3160979262 |
|
|
May 30 04:12:31 PM PDT 24 |
May 30 04:32:14 PM PDT 24 |
7561319917 ps |
| T1123 |
/workspace/coverage/default/0.chip_sw_rv_timer_irq.3812328853 |
|
|
May 30 04:11:30 PM PDT 24 |
May 30 04:17:07 PM PDT 24 |
3143004864 ps |
| T1124 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.751084595 |
|
|
May 30 04:13:14 PM PDT 24 |
May 30 04:20:04 PM PDT 24 |
3295490680 ps |
| T1125 |
/workspace/coverage/default/80.chip_sw_all_escalation_resets.2833934548 |
|
|
May 30 04:41:41 PM PDT 24 |
May 30 04:50:22 PM PDT 24 |
5667152510 ps |
| T1126 |
/workspace/coverage/default/2.chip_tap_straps_prod.3014921237 |
|
|
May 30 04:29:22 PM PDT 24 |
May 30 04:44:03 PM PDT 24 |
9089378370 ps |
| T1127 |
/workspace/coverage/default/1.chip_sw_hmac_smoketest.756958077 |
|
|
May 30 04:23:33 PM PDT 24 |
May 30 04:30:58 PM PDT 24 |
2696924136 ps |
| T1128 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3530278586 |
|
|
May 30 04:18:04 PM PDT 24 |
May 30 04:39:51 PM PDT 24 |
12455882839 ps |
| T394 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3005460381 |
|
|
May 30 04:20:12 PM PDT 24 |
May 30 04:27:01 PM PDT 24 |
6755012126 ps |
| T1129 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.2991693555 |
|
|
May 30 04:25:48 PM PDT 24 |
May 30 04:31:37 PM PDT 24 |
2882535608 ps |
| T143 |
/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.2404778104 |
|
|
May 30 04:14:05 PM PDT 24 |
May 30 07:16:46 PM PDT 24 |
58848057304 ps |
| T130 |
/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.1886267292 |
|
|
May 30 04:30:30 PM PDT 24 |
May 30 05:15:43 PM PDT 24 |
21679041336 ps |
| T693 |
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2203725029 |
|
|
May 30 04:42:27 PM PDT 24 |
May 30 04:47:38 PM PDT 24 |
3353738760 ps |
| T1130 |
/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1278662697 |
|
|
May 30 04:31:49 PM PDT 24 |
May 30 04:40:33 PM PDT 24 |
5573219612 ps |
| T1131 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2208834880 |
|
|
May 30 04:19:03 PM PDT 24 |
May 30 04:24:45 PM PDT 24 |
5050809702 ps |
| T1132 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.3662271371 |
|
|
May 30 04:21:21 PM PDT 24 |
May 30 05:16:26 PM PDT 24 |
11296578720 ps |
| T1133 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3470117912 |
|
|
May 30 04:27:46 PM PDT 24 |
May 30 04:29:51 PM PDT 24 |
3079960801 ps |
| T760 |
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.4002578072 |
|
|
May 30 04:36:24 PM PDT 24 |
May 30 04:44:22 PM PDT 24 |
3240326820 ps |
| T386 |
/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.1806482241 |
|
|
May 30 04:08:53 PM PDT 24 |
May 30 04:17:28 PM PDT 24 |
4211551912 ps |
| T1134 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.1990374034 |
|
|
May 30 04:18:37 PM PDT 24 |
May 30 04:27:15 PM PDT 24 |
4997520144 ps |
| T1135 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.128265376 |
|
|
May 30 04:20:12 PM PDT 24 |
May 30 04:29:56 PM PDT 24 |
4181817964 ps |
| T1136 |
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3926125560 |
|
|
May 30 04:37:11 PM PDT 24 |
May 30 04:44:05 PM PDT 24 |
3711682616 ps |
| T1137 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.2638826887 |
|
|
May 30 04:22:43 PM PDT 24 |
May 30 05:21:25 PM PDT 24 |
14469780084 ps |
| T1138 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.20449398 |
|
|
May 30 04:28:16 PM PDT 24 |
May 30 04:51:18 PM PDT 24 |
6778523060 ps |
| T1139 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.820710042 |
|
|
May 30 04:11:41 PM PDT 24 |
May 30 04:19:18 PM PDT 24 |
5013853850 ps |
| T733 |
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1074976079 |
|
|
May 30 04:40:13 PM PDT 24 |
May 30 04:46:25 PM PDT 24 |
3519383542 ps |
| T1140 |
/workspace/coverage/default/1.chip_sw_kmac_idle.1271928547 |
|
|
May 30 04:20:43 PM PDT 24 |
May 30 04:24:15 PM PDT 24 |
2788759672 ps |
| T703 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.107543059 |
|
|
May 30 04:37:25 PM PDT 24 |
May 30 04:44:36 PM PDT 24 |
3780952824 ps |
| T1141 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.3787123922 |
|
|
May 30 04:11:19 PM PDT 24 |
May 30 04:22:04 PM PDT 24 |
4903183772 ps |
| T1142 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1829646723 |
|
|
May 30 04:16:51 PM PDT 24 |
May 30 04:54:25 PM PDT 24 |
23555184868 ps |
| T185 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through.363487381 |
|
|
May 30 04:26:32 PM PDT 24 |
May 30 04:38:01 PM PDT 24 |
5602855925 ps |
| T1143 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.1703781824 |
|
|
May 30 04:18:54 PM PDT 24 |
May 30 04:23:02 PM PDT 24 |
3076219223 ps |
| T1144 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.2387160755 |
|
|
May 30 04:15:56 PM PDT 24 |
May 30 04:23:00 PM PDT 24 |
4052357560 ps |
| T1145 |
/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.242889488 |
|
|
May 30 04:14:04 PM PDT 24 |
May 30 04:21:17 PM PDT 24 |
3733451032 ps |
| T1146 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.2079639024 |
|
|
May 30 04:12:19 PM PDT 24 |
May 30 04:29:04 PM PDT 24 |
9622034463 ps |
| T1147 |
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.522218117 |
|
|
May 30 04:35:06 PM PDT 24 |
May 30 04:50:38 PM PDT 24 |
11514884040 ps |
| T1148 |
/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.1769863329 |
|
|
May 30 04:33:47 PM PDT 24 |
May 30 04:56:41 PM PDT 24 |
8091622634 ps |
| T1149 |
/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.2910673387 |
|
|
May 30 04:18:48 PM PDT 24 |
May 30 04:28:16 PM PDT 24 |
3139512716 ps |
| T236 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3397876711 |
|
|
May 30 04:13:39 PM PDT 24 |
May 30 05:06:16 PM PDT 24 |
10384564588 ps |