CHIP Simulation Results

Wednesday June 05 2024 22:14:46 UTC

GitHub Revision: `b29ffbb03c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 104714960319679935410420483500971829136303708457300037460974663680452494898918

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	5.096m	2.678ms	3	3	100.00
		chip_sw_example_rom	2.374m	2.991ms	3	3	100.00
		chip_sw_example_manufacturer	4.068m	2.529ms	3	3	100.00
		chip_sw_example_concurrency	4.950m	2.897ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset	7.057m	7.963ms	5	5	100.00
V1	csr_rw	chip_csr_rw	11.505m	6.121ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	1.121h	34.624ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	2.790h	56.902ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	2.124m	3.279ms	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	2.790h	56.902ms	5	5	100.00
		chip_csr_rw	11.505m	6.121ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	11.360s	237.096us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	8.049m	4.251ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	8.049m	4.251ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	8.049m	4.251ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	12.856m	4.635ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	12.856m	4.635ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	13.300m	4.636ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	12.876m	4.898ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	11.571m	4.244ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	44.682m	12.900ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	34.047m	8.560ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	18.092m	8.711ms	5	5	100.00
V1		TOTAL			200	220	90.91
V2	chip_pin_mux	chip_padctrl_attributes	5.492m	5.648ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	5.492m	5.648ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	5.798m	3.400ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	6.038m	5.617ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	5.360m	4.697ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	24.651m	13.765ms	5	5	100.00
		chip_tap_straps_testunlock0	18.939m	9.849ms	5	5	100.00
		chip_tap_straps_rma	9.404m	6.111ms	5	5	100.00
		chip_tap_straps_prod	32.352m	14.589ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	6.180m	3.247ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	23.703m	8.482ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	14.385m	5.177ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	14.385m	5.177ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	18.586m	8.515ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	34.948m	17.252ms	1	3	33.33
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	11.657m	4.246ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	16.927m	5.870ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.106h	18.726ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.704m	3.412ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	21.473m	6.755ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.217m	3.460ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	38.700m	13.055ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.983m	3.527ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.250m	4.716ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.960m	2.869ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	4.412m	2.715ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	16.166m	7.333ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	8.456m	5.581ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	4.506m	2.507ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	8.456m	5.581ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	3.811m	2.372ms	3	3	100.00
		chip_sw_aes_smoketest	5.541m	2.778ms	3	3	100.00
		chip_sw_aon_timer_smoketest	4.653m	3.407ms	3	3	100.00
		chip_sw_clkmgr_smoketest	3.994m	3.073ms	3	3	100.00
		chip_sw_csrng_smoketest	4.782m	2.257ms	3	3	100.00
		chip_sw_entropy_src_smoketest	12.523m	3.993ms	3	3	100.00
		chip_sw_gpio_smoketest	6.617m	3.921ms	3	3	100.00
		chip_sw_hmac_smoketest	8.039m	3.169ms	3	3	100.00
		chip_sw_kmac_smoketest	6.781m	3.194ms	3	3	100.00
		chip_sw_otbn_smoketest	38.508m	11.352ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	9.225m	7.145ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	9.562m	6.450ms	3	3	100.00
		chip_sw_rv_plic_smoketest	4.418m	2.411ms	3	3	100.00
		chip_sw_rv_timer_smoketest	5.862m	3.430ms	3	3	100.00
		chip_sw_rstmgr_smoketest	3.742m	2.570ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	5.112m	2.534ms	3	3	100.00
		chip_sw_uart_smoketest	4.952m	3.077ms	3	3	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	4.549m	2.472ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	12.618m	4.484ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.590h	76.632ms	2	3	66.67
V2	chip_sw_secure_boot	rom_e2e_smoke	1.010h	14.641ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	5.027h	203.974ms	0	3	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	12.929m	4.390ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	11.765m	10.702ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	3.073h	58.804ms	3	3	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.365h	62.849ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	9.303m	5.795ms	30	30	100.00
V2	tl_d_illegal_access	chip_tl_errors	9.303m	5.795ms	30	30	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	2.790h	56.902ms	5	5	100.00
		chip_same_csr_outstanding	1.280h	31.434ms	20	20	100.00
		chip_csr_hw_reset	7.057m	7.963ms	5	5	100.00
		chip_csr_rw	11.505m	6.121ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	2.790h	56.902ms	5	5	100.00
		chip_same_csr_outstanding	1.280h	31.434ms	20	20	100.00
		chip_csr_hw_reset	7.057m	7.963ms	5	5	100.00
		chip_csr_rw	11.505m	6.121ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.641m	2.399ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.340s	51.660us	100	100	100.00
		xbar_smoke_large_delays	2.010m	10.610ms	100	100	100.00
		xbar_smoke_slow_rsp	2.135m	7.258ms	100	100	100.00
		xbar_random_zero_delays	1.016m	597.050us	100	100	100.00
		xbar_random_large_delays	22.267m	114.617ms	100	100	100.00
		xbar_random_slow_rsp	22.228m	69.613ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.087m	1.378ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.002m	1.392ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.480m	2.242ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.002m	1.392ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.644m	3.919ms	100	100	100.00
		xbar_access_same_device_slow_rsp	51.238m	167.078ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.454m	2.645ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	14.181m	16.400ms	100	100	100.00
		xbar_stress_all_with_error	12.393m	18.326ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	20.704m	11.447ms	100	100	100.00
		xbar_stress_all_with_reset_error	15.073m	17.909ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	1.010h	14.641ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	49.694m	25.429ms	3	3	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	1.017h	14.187ms	3	3	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	49.899m	10.875ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	57.827m	14.064ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	58.187m	14.561ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	59.679m	13.834ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	57.874m	14.766ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	45.670m	10.794ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	1.048h	14.699ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	1.209h	14.170ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	1.139h	14.612ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	56.203m	14.112ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	1.276h	18.024ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	1.560h	23.326ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	1.446h	23.047ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	1.446h	23.004ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	1.665h	22.401ms	1	1	100.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	1.377h	17.539ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	1.638h	22.553ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	1.851h	22.026ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	1.484h	22.055ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	1.407h	21.642ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	46.462m	10.474ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	53.992m	13.518ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	1.131h	14.096ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	54.044m	13.862ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	1.028h	13.153ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	46.944m	10.755ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	54.140m	14.670ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	1.058h	12.972ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	55.572m	14.103ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	56.419m	13.779ms	1	1	100.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	50.147m	11.546ms	3	3	100.00
		rom_e2e_asm_init_dev	1.083h	15.038ms	3	3	100.00
		rom_e2e_asm_init_prod	1.124h	14.534ms	3	3	100.00
		rom_e2e_asm_init_prod_end	57.681m	14.673ms	3	3	100.00
		rom_e2e_asm_init_rma	1.012h	14.908ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	1.158h	15.664ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	1.058h	14.782ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	1.149h	14.286ms	3	3	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	1.160h	20.016ms	0	3	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	3.913m	2.403ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.704m	3.412ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	5.697m	2.898ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	5.542m	3.303ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	45.557m	13.826ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.361m	19.550ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.361m	19.550ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	7.951m	3.780ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	9.225m	7.145ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	7.951m	3.780ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	16.741m	9.323ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	16.741m	9.323ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	10.807m	7.647ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	11.753m	4.879ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	17.916m	6.024ms	3	3	100.00
		chip_sw_aes_idle	5.542m	3.303ms	3	3	100.00
		chip_sw_hmac_enc_idle	5.283m	3.471ms	3	3	100.00
		chip_sw_kmac_idle	5.394m	3.174ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	8.152m	4.469ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	9.779m	4.467ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	10.008m	5.361ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	8.833m	4.398ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	29.760m	11.286ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.147m	3.676ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.923m	4.418ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.172m	4.232ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.559m	5.564ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	13.323m	4.658ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.148m	5.044ms	3	3	100.00
		chip_sw_ast_clk_outputs	18.586m	8.515ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	14.522m	10.931ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.172m	4.232ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.559m	5.564ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	11.657m	4.246ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	16.927m	5.870ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.106h	18.726ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.704m	3.412ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	21.473m	6.755ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.217m	3.460ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	38.700m	13.055ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.983m	3.527ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.250m	4.716ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.960m	2.869ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.083m	3.042ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	14.048m	4.750ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	18.811m	7.450ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.108h	25.090ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	4.462m	3.856ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	4.282m	3.467ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	35.274m	12.547ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	6.212m	3.193ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	10.285m	5.448ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	37.601m	22.577ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	1.190h	21.997ms	2	3	66.67
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	18.586m	8.515ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	10.080m	4.535ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	8.124m	3.605ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	15.530m	6.022ms	100	100	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	31.804m	7.810ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	29.648m	7.257ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	10.831m	4.905ms	3	3	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	13.732m	5.495ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	5.590m	2.744ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	22.768m	8.858ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	34.484m	23.890ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	5.110m	2.545ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	40.850s	10.360us	0	3	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	12.962m	5.339ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	34.484m	23.890ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	34.484m	23.890ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	1.231h	20.515ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	1.231h	20.515ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	9.754m	6.336ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.361m	19.550ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	2.481h	45.098ms	10	10	100.00
		chip_sw_entropy_src_ast_rng_req	4.486m	3.207ms	3	3	100.00
		chip_sw_edn_entropy_reqs	23.857m	7.591ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	4.486m	3.207ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	29.648m	7.257ms	3	3	100.00
V2	chip_sw_entropy_src_fuse_en_fw_read	chip_sw_entropy_src_fuse_en_fw_read_test			0	0	--
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	4.356m	2.824ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	37.662m	21.120ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	16.314m	5.757ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	16.927m	5.870ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	13.024m	3.549ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	11.657m	4.246ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.400h	43.321ms	3	3	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	37.662m	21.120ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	6.958m	3.806ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	37.470m	10.203ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.427m	2.775ms	0	3	0.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.400h	43.321ms	3	3	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.427m	2.775ms	0	3	0.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.427m	2.775ms	0	3	0.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.427m	2.775ms	0	3	0.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.427m	2.775ms	0	3	0.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	15.530m	6.022ms	100	100	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	8.503m	13.607ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	21.089m	5.390ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	12.127m	5.379ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	12.127m	5.379ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.952m	3.248ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.217m	3.460ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.283m	3.471ms	3	3	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	8.007m	3.066ms	3	3	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	28.517m	6.543ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	16.378m	5.094ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	17.297m	5.580ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	15.491m	5.036ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	10.040m	4.215ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	37.470m	10.203ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	38.700m	13.055ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	29.992m	8.446ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	45.557m	13.826ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.096h	17.421ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	5.576m	3.330ms	3	3	100.00
		chip_sw_kmac_mode_kmac	6.097m	3.371ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.983m	3.527ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	37.470m	10.203ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	21.040m	10.767ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	5.498m	2.982ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.120m	2.779ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	5.394m	3.174ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	11.035m	4.845ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	24.651m	13.765ms	5	5	100.00
		chip_tap_straps_rma	9.404m	6.111ms	5	5	100.00
		chip_tap_straps_prod	32.352m	14.589ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	6.281m	3.089ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	21.040m	10.767ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	21.040m	10.767ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	21.040m	10.767ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	38.053m	11.529ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.427m	2.775ms	0	3	0.00
		chip_sw_flash_rma_unlocked	1.400h	43.321ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.957m	4.332ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	22.268m	8.538ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	24.094m	9.138ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	26.593m	9.049ms	3	3	100.00
		chip_sw_lc_ctrl_transition	21.040m	10.767ms	15	15	100.00
		chip_sw_keymgr_key_derivation	37.470m	10.203ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	9.925m	9.962ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	16.973m	8.941ms	3	3	100.00
		chip_prim_tl_access	8.503m	13.607ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	14.522m	10.931ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.147m	3.676ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.923m	4.418ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.172m	4.232ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.559m	5.564ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	13.323m	4.658ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.148m	5.044ms	3	3	100.00
		chip_tap_straps_dev	24.651m	13.765ms	5	5	100.00
		chip_tap_straps_rma	9.404m	6.111ms	5	5	100.00
		chip_tap_straps_prod	32.352m	14.589ms	5	5	100.00
		chip_rv_dm_lc_disabled	9.006m	11.290ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.335m	2.980ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.626m	2.330ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.256m	3.103ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.291m	2.676ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	41.124m	28.434ms	3	3	100.00
		chip_rv_dm_lc_disabled	9.006m	11.290ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.570h	47.642ms	3	3	100.00
		chip_sw_lc_walkthrough_prod	1.527h	46.102ms	3	3	100.00
		chip_sw_lc_walkthrough_prodend	17.257m	8.880ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	1.486h	48.827ms	3	3	100.00
		chip_sw_lc_walkthrough_testunlocks	41.124m	28.434ms	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	2.026m	2.612ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.926m	1.990ms	3	3	100.00
		rom_volatile_raw_unlock	2.023m	3.058ms	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	21.040m	10.767ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	37.662m	21.120ms	3	3	100.00
		chip_sw_otbn_mem_scramble	8.595m	4.127ms	3	3	100.00
		chip_sw_keymgr_key_derivation	37.470m	10.203ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	10.529m	5.630ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.665m	2.903ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	37.662m	21.120ms	3	3	100.00
		chip_sw_otbn_mem_scramble	8.595m	4.127ms	3	3	100.00
		chip_sw_keymgr_key_derivation	37.470m	10.203ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	10.529m	5.630ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.665m	2.903ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	21.040m	10.767ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	17.384m	14.429ms	0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	6.281m	3.089ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.957m	4.332ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	22.268m	8.538ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	24.094m	9.138ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	26.593m	9.049ms	3	3	100.00
		chip_sw_lc_ctrl_transition	21.040m	10.767ms	15	15	100.00
		chip_prim_tl_access	8.503m	13.607ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	8.503m	13.607ms	3	3	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	1.424h	25.837ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	7.748m	6.749ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	33.783m	24.157ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	7.006m	7.425ms	2	3	66.67
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	12.850m	10.652ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	12.080m	7.686ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	29.058m	22.240ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	26.137m	16.452ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	16.741m	9.323ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	26.180m	12.835ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	10.791m	5.165ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	7.748m	6.749ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	7.824m	4.657ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	1.203h	39.268ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	10.407m	7.613ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	9.694m	5.775ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	42.755m	24.592ms	2	3	66.67
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	22.768m	8.858ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	29.843m	10.048ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	44.850m	26.859ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	4.961m	2.604ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	15.530m	6.022ms	100	100	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	9.925m	9.962ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	9.925m	9.962ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	29.843m	10.048ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	42.755m	24.592ms	2	3	66.67
		chip_sw_pwrmgr_wdog_reset	10.791m	5.165ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	9.225m	7.145ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	8.887m	4.993ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	12.937m	5.679ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	7.829m	4.286ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	39.246m	12.235ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	5.696m	2.695ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	15.530m	6.022ms	100	100	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	30.931m	7.082ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	21.280m	6.192ms	3	3	100.00
		chip_plic_all_irqs_10	11.849m	4.347ms	3	3	100.00
		chip_plic_all_irqs_20	13.793m	4.355ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	6.057m	2.642ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	4.692m	3.059ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	1.010h	14.641ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	16.062m	8.628ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	11.740m	4.916ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	7.103m	4.053ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	4.951m	2.977ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	10.529m	5.630ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.250m	4.716ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	12.613m	7.250ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	14.697m	7.804ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	16.973m	8.941ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	15.530m	6.022ms	100	100	100.00
		chip_sw_data_integrity_escalation	14.385m	5.177ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	3.530m	2.691ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	5.074m	3.040ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	7.835m	3.476ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	10.092m	3.547ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	31.326m	7.873ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.994h	30.995ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	47.296m	11.711ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	5.538m	3.433ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	11.035m	4.845ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	15.530m	6.022ms	100	100	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	5.514m	3.139ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	39.246m	12.235ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	8.485m	4.331ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	8.746m	3.332ms	88	90	97.78
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	25.535m	11.692ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	31.804m	7.810ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	30.931m	7.082ms	3	3	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	24.975m	8.069ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.084h	255.948ms	3	3	100.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	24.710m	12.890ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	27.712m	14.141ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	8.887m	4.993ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	10.002m	4.533ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	9.881m	3.674ms	0	3	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	9.404m	6.111ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	9.006m	11.290ms	3	3	100.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			2618	2644	99.02
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	8.363m	3.099ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark			0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	19.551m	5.724ms	0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	2.230m	2.288ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.947m	2.411ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.503m	1.754ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	52.060m	41.965ms	0	1	0.00
		rom_e2e_jtag_inject_dev	1.071h	53.876ms	0	1	0.00
		rom_e2e_jtag_inject_rma	1.209h	52.894ms	0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash			0	0	--
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.421m	3.509ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	10.304m	3.112ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	16.592m	4.896ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	33.311m	10.348ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	12.692m	3.611ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	23.388m	5.169ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	//sw/device/tests:i2c_host_override_test			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	3.876m	2.875ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	11.706m	5.416ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	9.436m	6.080ms	3	3	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	10.854m	5.487ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	29.843m	10.048ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	15.530m	6.022ms	100	100	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	//sw/device/tests:spi_passthru_test			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	//sw/device/tests:spi_passthru_test			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	12.856m	4.635ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.231h	19.331ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	2.230m	2.288ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.947m	2.411ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.503m	1.754ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.532m	5.237ms	3	3	100.00
V3		TOTAL			32	45	71.11
	Unmapped tests	chip_sival_flash_info_access	5.344m	3.107ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	14.019m	5.601ms	3	3	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	4.491m	3.076ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	1.160h	17.295ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	19.665m	5.011ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	16.297m	4.953ms	3	3	100.00
		chip_sw_pwrmgr_lowpower_cancel	7.412m	3.756ms	2	3	66.67
		chip_sw_pwrmgr_sleep_wake_5_bug	10.294m	7.433ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	6.149m	3.373ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	4.988m	2.882ms	3	3	100.00
		chip_sw_flash_ctrl_write_clear	5.989m	3.553ms	3	3	100.00
		TOTAL			2885	2945	97.96

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	11	11	10	90.91
V1	18	18	17	94.44
V2	285	270	258	90.53
V2S	1	1	1	100.00
V3	90	21	12	13.33

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.95	95.45	93.92	95.53	--	94.77	96.47	99.59

Failure Buckets

UVM_ERROR @ * us: (cip_base_vseq.sv:828) [chip_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test chip_csr_mem_rw_with_rand_reset has 20 failures.
  - 0.chip_csr_mem_rw_with_rand_reset.89695793053606546236560732705013261305887169877915049193878963590884935132149
    Line 387, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2453.207973 us: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2453.207973 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_csr_mem_rw_with_rand_reset.2637377182372629794487437346060671211860393716872098459914814436362457380772
    Line 362, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2310.493858 us: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2310.493858 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 10 failures:
- Test chip_sw_uart_tx_rx_bootstrap has 1 failures.
  - 0.chip_sw_uart_tx_rx_bootstrap.60644250126036334340541642699859434257632657550787959270959186007361807637717
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_bootstrap/latest/run.log
```
  Job ID: smart:bbfc60aa-cd8d-4887-999e-0e2d14fdbf94
```
- Test chip_sw_rv_timer_systick_test has 3 failures.
  - 0.chip_sw_rv_timer_systick_test.55909259430232031699484848272159362835864620865221003249226920850213876458750
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:51c5263c-c08e-4009-8967-f765d75ecdbe
```
  - 1.chip_sw_rv_timer_systick_test.21682966455494307751638556761953211257188906428360319835282300939176474158370
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:101be0ec-93ad-4052-bd62-f6505d748e8f
```
  - ... and 1 more failures.
- Test chip_sw_coremark has 1 failures.
  - 0.chip_sw_coremark.17563468446103644001644064634650028589412655095290195825738162865851968206866
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
```
  Job ID: smart:4ce17758-0b93-4965-990b-a52fc83269b8
```
- Test chip_sw_ast_clk_rst_inputs has 2 failures.
  - 0.chip_sw_ast_clk_rst_inputs.66766160650074754056922083793910271161850792708645792492841615732565042357139
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:c0d7b27d-21a1-4c46-b772-fbee0a299a41
```
  - 1.chip_sw_ast_clk_rst_inputs.98924682287501013829772388316084877543918129697445385580927248886308836903439
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:7bdc07e9-8022-4f3c-ab31-7dc31eab1031
```
- Test chip_sw_csrng_edn_concurrency_reduced_freq has 1 failures.
  - 1.chip_sw_csrng_edn_concurrency_reduced_freq.18337897718331976545737179004709278870663564473119068784881975757938974990093
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest/run.log
```
  Job ID: smart:ca2d08f0-58be-4f35-8b1d-4d7b784862d5
```
- ... and 2 more tests.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c:101)] DIF-fail: dif_keymgr_advance_state(keymgr, params) returns * has 3 failures:
- Test chip_sw_flash_ctrl_lc_rw_en has 3 failures.
  - 0.chip_sw_flash_ctrl_lc_rw_en.50626557850407583167470460880587458624648078201545778317489191384972499347624
    Line 745, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_lc_rw_en/latest/run.log
```
  UVM_ERROR @ 2512.953344 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c:101)] DIF-fail: dif_keymgr_advance_state(keymgr, params) returns 3
  UVM_INFO @ 2512.953344 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_flash_ctrl_lc_rw_en.53754790814640654252580845832058001741382426020288251263996266475769629331551
    Line 736, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_lc_rw_en/latest/run.log
```
  UVM_ERROR @ 2305.834690 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c:101)] DIF-fail: dif_keymgr_advance_state(keymgr, params) returns 3
  UVM_INFO @ 2305.834690 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat" has 3 failures:
- Test chip_sw_sysrst_ctrl_outputs has 3 failures.
  - 0.chip_sw_sysrst_ctrl_outputs.71406349288618752377145133939386618865911772393084377768758424559172151436388
    Line 754, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_sysrst_ctrl_outputs.32638628486344129397057118029568872661666223264682463301612802269171683277581
    Line 845, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:
- Test chip_sw_lc_ctrl_program_error has 3 failures.
  - 0.chip_sw_lc_ctrl_program_error.19351898495329487614061948928036576490903679701244581704253097376681380868514
    Line 772, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 14428.613486 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 14428.613486 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.chip_sw_lc_ctrl_program_error.31881397535077175614411581857172138384279981333571174189326720440692388271559
    Line 759, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 14633.376616 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 14633.376616 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep. has 3 failures:
- Test chip_sw_rv_dm_access_after_wakeup has 3 failures.
  - 0.chip_sw_rv_dm_access_after_wakeup.77787982882959533724642802343103680401343926437350432772420472162649361881555
    Line 802, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 4575.453826 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 4575.453826 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_rv_dm_access_after_wakeup.42045925832267773038863112318651299469133308811198817911363044455600557074244
    Line 780, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3673.546356 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3673.546356 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.43802466660599240006342475793446735235675530235175156846410924344297022235076
    Line 763, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 2287.670000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2287.670000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.78162544519596866107841068953498965339979688814601935191702794786818210950900
    Line 765, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 2410.626500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2410.626500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.26758363256910246517265222203045947451931023636142773917595054117211308131107
    Line 755, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 1754.291500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 1754.291500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 3 failures:
- Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_inject_test_unlocked0.93819054427949058635027415347460517681471361639670721859050208012156697464209
    Line 797, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 41964.679405 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 41964.679405 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_dev has 1 failures.
  - 0.rom_e2e_jtag_inject_dev.81491012933331515144522669904845204347173074776596476675414403920986019892246
    Line 775, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log
```
  UVM_FATAL @ 53875.508950 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 53875.508950 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_rma has 1 failures.
  - 0.rom_e2e_jtag_inject_rma.100547800531766007682839646249349171821904587041950130845184241594416511820374
    Line 878, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log
```
  UVM_FATAL @ 52894.201445 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 52894.201445 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 3 failures:
- Test rom_e2e_static_critical has 3 failures.
  - 0.rom_e2e_static_critical.2652990429271149047930839562853687698887346094111057907563702653749735591379
    Line 767, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_static_critical/latest/run.log
```
  UVM_ERROR @ 20017.732432 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 20000000 ns
  
  UVM_INFO @ 20017.732432 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.rom_e2e_static_critical.39275117894016589584545424600213338640324099738433909400160826879408833685400
    Line 826, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_static_critical/latest/run.log
```
  UVM_ERROR @ 20025.702344 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 20000000 ns
  
  UVM_INFO @ 20025.702344 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:178) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 2 failures:
- Test chip_sw_power_virus has 2 failures.
  - 0.chip_sw_power_virus.12049132597538213636509618839884330855479514817262897505962897747558139989082
    Line 992, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 5724.363566 us: (chip_sw_power_virus_vseq.sv:178) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 5724.363566 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.chip_sw_power_virus.64276909885018498643605250433736563954170689245264277078442036253097295521317
    Line 1018, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 5274.831462 us: (chip_sw_power_virus_vseq.sv:178) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 5274.831462 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 2 failures:

Test rom_raw_unlock has 2 failures.

0.rom_raw_unlock.38509428620320202120816823432823134000030724591023785278657956394742134275477
Line 808, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest/run.log

  UVM_ERROR @ 203973.804012 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns
  
  UVM_INFO @ 203973.804012 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.rom_raw_unlock.97769907710147360931644434360952679779627092279957227236724853677827521722225
Line 781, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_raw_unlock/latest/run.log

  UVM_ERROR @ 206504.701137 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns
  
  UVM_INFO @ 206504.701137 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 2 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 2 failures.
  - 40.chip_sw_alert_handler_lpg_sleep_mode_alerts.88550531858556176366119360723130976769364768341059414342403709918202103682803
    Line 792, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 4042.581400 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003720 MTVAL=40600800
  UVM_INFO @ 4042.581400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 72.chip_sw_alert_handler_lpg_sleep_mode_alerts.114570777687067075045203541610640095819541194017065126045451324124771078625635
    Line 774, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3332.494056 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003720 MTVAL=40600800
  UVM_INFO @ 3332.494056 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(pend_req[h2d.a_source].pend == *)' has 1 failures:
- Test chip_sw_pwrmgr_random_sleep_all_reset_reqs has 1 failures.
  - 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.84574505103549429379152507490642620210151898318878499063623392711509426342855
    Line 825, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log
```
      Offending '(pend_req[h2d.a_source].pend == 0)'
  UVM_ERROR @ 17913.374508 us: (tlul_assert.sv:268) [ASSERT FAILED] pendingReqPerSrc_M
  UVM_INFO @ 17913.374508 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits * and * set in filter status, got status * has 1 failures:
- Test chip_sw_pwrmgr_normal_sleep_all_wake_ups has 1 failures.
  - 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.81625497029957463625873694566907823742995165531439118082919950911735000951987
    Line 774, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log
```
  UVM_ERROR @ 6467.955750 us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits 5 and 8 set in filter status, got status 0x100
  UVM_INFO @ 6467.955750 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:84)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status() has 1 failures:
- Test chip_sw_pwrmgr_lowpower_cancel has 1 failures.
  - 2.chip_sw_pwrmgr_lowpower_cancel.11014309661515553194056708369676112440400996171499986560244393900492722712941
    Line 830, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_lowpower_cancel/latest/run.log
```
  UVM_ERROR @ 3007.320008 us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:84)] CHECK-fail: Timed out after 100 usec (10000 CPU cycles) waiting for !get_wakeup_status()
  UVM_INFO @ 3007.320008 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```