CHIP Simulation Results

Sunday June 02 2024 19:02:53 UTC

GitHub Revision: `01a208901a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 50418669159766293903157726892781832882154091083197082086235277423705989875584

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	4.889m	2.728ms	3	3	100.00
		chip_sw_example_rom	2.142m	2.232ms	3	3	100.00
		chip_sw_example_manufacturer	5.624m	2.708ms	3	3	100.00
		chip_sw_example_concurrency	4.844m	3.430ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset	8.206m	7.026ms	5	5	100.00
V1	csr_rw	chip_csr_rw	11.787m	6.534ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	1.831h	64.779ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	2.940h	73.782ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	2.230m	2.243ms	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	2.940h	73.782ms	5	5	100.00
		chip_csr_rw	11.787m	6.534ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	11.500s	247.377us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	7.924m	3.574ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	7.924m	3.574ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	7.924m	3.574ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	13.139m	4.014ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	13.139m	4.014ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	11.788m	3.767ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	12.726m	4.841ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	13.143m	4.072ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	52.414m	13.171ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	47.917m	13.321ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	33.700m	13.825ms	5	5	100.00
V1		TOTAL			200	220	90.91
V2	chip_pin_mux	chip_padctrl_attributes	6.186m	4.774ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	6.186m	4.774ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	5.416m	3.042ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	10.226m	5.986ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	4.934m	3.327ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	18.698m	9.035ms	5	5	100.00
		chip_tap_straps_testunlock0	16.244m	8.588ms	5	5	100.00
		chip_tap_straps_rma	14.732m	7.504ms	5	5	100.00
		chip_tap_straps_prod	31.172m	16.523ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	4.965m	2.912ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	23.602m	7.499ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	14.089m	5.491ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	14.089m	5.491ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	18.310m	7.611ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	44.522m	17.520ms	3	3	100.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	12.791m	4.751ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	22.349m	5.604ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.129h	18.490ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.397m	2.491ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	25.907m	7.781ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.700m	3.216ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	38.608m	12.206ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.950m	2.890ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	16.336m	5.783ms	3	3	100.00
		chip_sw_clkmgr_jitter	5.950m	3.062ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	7.256m	3.440ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	12.246m	7.545ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	6.964m	4.622ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	4.745m	3.047ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	6.964m	4.622ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	4.302m	2.674ms	3	3	100.00
		chip_sw_aes_smoketest	5.811m	2.989ms	3	3	100.00
		chip_sw_aon_timer_smoketest	6.126m	2.960ms	3	3	100.00
		chip_sw_clkmgr_smoketest	4.626m	2.451ms	3	3	100.00
		chip_sw_csrng_smoketest	4.446m	2.804ms	3	3	100.00
		chip_sw_entropy_src_smoketest	10.620m	3.289ms	3	3	100.00
		chip_sw_gpio_smoketest	5.809m	2.709ms	3	3	100.00
		chip_sw_hmac_smoketest	6.169m	2.997ms	3	3	100.00
		chip_sw_kmac_smoketest	6.003m	2.619ms	3	3	100.00
		chip_sw_otbn_smoketest	44.536m	10.777ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	7.488m	5.030ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	8.967m	6.021ms	3	3	100.00
		chip_sw_rv_plic_smoketest	3.981m	2.352ms	3	3	100.00
		chip_sw_rv_timer_smoketest	4.624m	2.623ms	3	3	100.00
		chip_sw_rstmgr_smoketest	4.618m	3.282ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	4.576m	2.052ms	3	3	100.00
		chip_sw_uart_smoketest	4.334m	3.091ms	3	3	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	5.023m	3.533ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	12.825m	4.672ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.736h	78.098ms	1	3	33.33
V2	chip_sw_secure_boot	rom_e2e_smoke	59.917m	13.891ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	4.620h	205.027ms	0	3	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	11.881m	4.055ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	9.506m	10.763ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	3.214h	57.648ms	3	3	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.289h	64.424ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	6.948m	4.523ms	30	30	100.00
V2	tl_d_illegal_access	chip_tl_errors	6.948m	4.523ms	30	30	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	2.940h	73.782ms	5	5	100.00
		chip_same_csr_outstanding	1.217h	31.308ms	20	20	100.00
		chip_csr_hw_reset	8.206m	7.026ms	5	5	100.00
		chip_csr_rw	11.787m	6.534ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	2.940h	73.782ms	5	5	100.00
		chip_same_csr_outstanding	1.217h	31.308ms	20	20	100.00
		chip_csr_hw_reset	8.206m	7.026ms	5	5	100.00
		chip_csr_rw	11.787m	6.534ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.973m	2.691ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.040s	54.439us	100	100	100.00
		xbar_smoke_large_delays	2.212m	10.024ms	100	100	100.00
		xbar_smoke_slow_rsp	2.289m	7.186ms	100	100	100.00
		xbar_random_zero_delays	1.030m	621.921us	100	100	100.00
		xbar_random_large_delays	21.143m	108.287ms	100	100	100.00
		xbar_random_slow_rsp	21.159m	68.010ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.304m	1.480ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.122m	1.170ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.613m	2.582ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.122m	1.170ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.676m	3.193ms	100	100	100.00
		xbar_access_same_device_slow_rsp	48.187m	165.957ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.621m	2.687ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	10.513m	14.800ms	100	100	100.00
		xbar_stress_all_with_error	16.686m	27.158ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	20.597m	12.049ms	100	100	100.00
		xbar_stress_all_with_reset_error	15.015m	7.481ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	59.917m	13.891ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	53.051m	22.393ms	3	3	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	1.099h	14.450ms	3	3	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	56.773m	11.456ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	1.346h	13.974ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	1.137h	14.241ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	1.028h	14.059ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	1.021h	14.495ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	49.827m	10.868ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	1.098h	14.618ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	1.200h	14.229ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	1.048h	14.114ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	1.150h	13.748ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	1.341h	17.155ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	1.766h	22.204ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	1.714h	22.704ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	1.814h	21.923ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	1.649h	22.733ms	1	1	100.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	1.398h	17.450ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	1.801h	22.063ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	1.463h	21.705ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	1.558h	21.605ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	1.531h	22.046ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	45.749m	11.027ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	58.670m	12.939ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	57.515m	13.297ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	1.108h	13.221ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	58.805m	13.114ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	51.966m	11.229ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	1.225h	13.524ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	59.474m	13.338ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	55.547m	13.635ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	54.063m	13.623ms	1	1	100.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	54.615m	11.028ms	3	3	100.00
		rom_e2e_asm_init_dev	1.112h	14.625ms	3	3	100.00
		rom_e2e_asm_init_prod	1.196h	14.458ms	3	3	100.00
		rom_e2e_asm_init_prod_end	1.095h	13.921ms	3	3	100.00
		rom_e2e_asm_init_rma	1.216h	14.272ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	1.157h	15.518ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	1.055h	14.681ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	1.189h	13.700ms	3	3	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	1.099h	20.016ms	0	3	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.692m	2.492ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.397m	2.491ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.959m	3.487ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	5.506m	2.687ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	30.747m	9.522ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	12.657m	19.078ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	12.657m	19.078ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	7.679m	3.908ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	7.488m	5.030ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	7.679m	3.908ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	17.959m	10.083ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	17.959m	10.083ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	10.404m	8.329ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	12.121m	4.693ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	16.275m	5.976ms	3	3	100.00
		chip_sw_aes_idle	5.506m	2.687ms	3	3	100.00
		chip_sw_hmac_enc_idle	6.046m	2.653ms	3	3	100.00
		chip_sw_kmac_idle	4.371m	2.345ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	11.848m	4.872ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	9.619m	5.695ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	8.425m	4.236ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	8.857m	5.922ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	31.535m	12.295ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.891m	4.237ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.041m	5.325ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.944m	3.736ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.927m	4.620ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.927m	4.552ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.580m	4.345ms	3	3	100.00
		chip_sw_ast_clk_outputs	18.310m	7.611ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	19.974m	13.673ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.944m	3.736ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.927m	4.620ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	12.791m	4.751ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	22.349m	5.604ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.129h	18.490ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.397m	2.491ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	25.907m	7.781ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.700m	3.216ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	38.608m	12.206ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.950m	2.890ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	16.336m	5.783ms	3	3	100.00
		chip_sw_clkmgr_jitter	5.950m	3.062ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.100m	3.112ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	13.381m	4.669ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	18.866m	6.630ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.148h	24.717ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	4.720m	3.435ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	4.978m	2.647ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	33.386m	11.091ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	5.255m	2.521ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	10.064m	5.647ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	39.129m	27.311ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	1.266h	22.752ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	18.310m	7.611ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	11.526m	4.668ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	7.947m	3.703ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	16.003m	5.865ms	98	100	98.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	29.048m	7.768ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	31.594m	7.489ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	7.379m	3.831ms	3	3	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	10.895m	5.877ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	5.075m	2.413ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	17.454m	8.368ms	2	3	66.67
		chip_sw_sysrst_ctrl_reset	32.502m	24.131ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	6.277m	2.587ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	44.000s	10.240us	0	3	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	11.579m	4.715ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	32.502m	24.131ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	32.502m	24.131ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	1.098h	20.721ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	1.098h	20.721ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	10.464m	4.928ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	12.657m	19.078ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	2.012h	35.955ms	10	10	100.00
		chip_sw_entropy_src_ast_rng_req	5.241m	2.751ms	3	3	100.00
		chip_sw_edn_entropy_reqs	22.807m	6.283ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	5.241m	2.751ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	31.594m	7.489ms	3	3	100.00
V2	chip_sw_entropy_src_fuse_en_fw_read	chip_sw_entropy_src_fuse_en_fw_read_test			0	0	--
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	4.995m	2.602ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	39.335m	23.837ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	19.229m	5.257ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	22.349m	5.604ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	12.549m	4.581ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	12.791m	4.751ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.573h	43.243ms	3	3	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	39.335m	23.837ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	6.817m	2.944ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	47.894m	12.581ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.418m	2.939ms	0	3	0.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.573h	43.243ms	3	3	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.418m	2.939ms	0	3	0.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.418m	2.939ms	0	3	0.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	5.418m	2.939ms	0	3	0.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.418m	2.939ms	0	3	0.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	16.003m	5.865ms	98	100	98.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	5.416m	9.183ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	17.498m	5.307ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	13.400m	5.163ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	13.400m	5.163ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.582m	2.676ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.700m	3.216ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	6.046m	2.653ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	15.121m	4.703ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	13.234m	5.042ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	19.686m	5.463ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	10.224m	3.867ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	47.894m	12.581ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	38.608m	12.206ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	47.289m	12.356ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	30.747m	9.522ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.201h	13.962ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	5.984m	3.110ms	3	3	100.00
		chip_sw_kmac_mode_kmac	5.353m	3.214ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.950m	2.890ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	47.894m	12.581ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	19.593m	10.317ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	4.356m	2.672ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	4.549m	2.477ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.371m	2.345ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	8.304m	4.748ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	18.698m	9.035ms	5	5	100.00
		chip_tap_straps_rma	14.732m	7.504ms	5	5	100.00
		chip_tap_straps_prod	31.172m	16.523ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.139m	2.651ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	19.593m	10.317ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	19.593m	10.317ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	19.593m	10.317ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	50.895m	12.208ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	5.418m	2.939ms	0	3	0.00
		chip_sw_flash_rma_unlocked	1.573h	43.243ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.752m	4.823ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	22.654m	8.793ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	23.011m	7.273ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	24.623m	9.391ms	3	3	100.00
		chip_sw_lc_ctrl_transition	19.593m	10.317ms	15	15	100.00
		chip_sw_keymgr_key_derivation	47.894m	12.581ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	10.215m	9.316ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	17.716m	9.995ms	3	3	100.00
		chip_prim_tl_access	5.416m	9.183ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	19.974m	13.673ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.891m	4.237ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.041m	5.325ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.944m	3.736ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.927m	4.620ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.927m	4.552ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.580m	4.345ms	3	3	100.00
		chip_tap_straps_dev	18.698m	9.035ms	5	5	100.00
		chip_tap_straps_rma	14.732m	7.504ms	5	5	100.00
		chip_tap_straps_prod	31.172m	16.523ms	5	5	100.00
		chip_rv_dm_lc_disabled	6.695m	10.352ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.080m	3.309ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.131m	3.694ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.627m	2.761ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.560m	2.946ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	43.757m	28.674ms	3	3	100.00
		chip_rv_dm_lc_disabled	6.695m	10.352ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.573h	50.809ms	3	3	100.00
		chip_sw_lc_walkthrough_prod	1.450h	49.553ms	3	3	100.00
		chip_sw_lc_walkthrough_prodend	17.489m	11.796ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	1.702h	48.318ms	3	3	100.00
		chip_sw_lc_walkthrough_testunlocks	43.757m	28.674ms	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	2.122m	3.101ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	2.056m	2.872ms	3	3	100.00
		rom_volatile_raw_unlock	1.783m	2.565ms	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	19.593m	10.317ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	39.335m	23.837ms	3	3	100.00
		chip_sw_otbn_mem_scramble	8.459m	3.409ms	3	3	100.00
		chip_sw_keymgr_key_derivation	47.894m	12.581ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	12.936m	4.185ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.604m	2.545ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	39.335m	23.837ms	3	3	100.00
		chip_sw_otbn_mem_scramble	8.459m	3.409ms	3	3	100.00
		chip_sw_keymgr_key_derivation	47.894m	12.581ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	12.936m	4.185ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.604m	2.545ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	19.593m	10.317ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	14.756m	14.490ms	0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.139m	2.651ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.752m	4.823ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	22.654m	8.793ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	23.011m	7.273ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	24.623m	9.391ms	3	3	100.00
		chip_sw_lc_ctrl_transition	19.593m	10.317ms	15	15	100.00
		chip_prim_tl_access	5.416m	9.183ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	5.416m	9.183ms	3	3	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	1.432h	27.547ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	8.208m	7.754ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	32.683m	21.060ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	7.178m	7.618ms	2	3	66.67
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	11.287m	8.885ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	10.800m	7.331ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	31.458m	18.893ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	36.786m	17.625ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	17.959m	10.083ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	34.769m	11.698ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	12.217m	4.765ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	8.208m	7.754ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	8.562m	3.873ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	58.015m	36.904ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	10.130m	7.487ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	9.465m	5.279ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	44.968m	23.051ms	3	3	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	17.454m	8.368ms	2	3	66.67
		chip_sw_pwrmgr_all_reset_reqs	34.825m	11.887ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	48.206m	22.408ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	5.623m	3.356ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	16.003m	5.865ms	98	100	98.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	10.215m	9.316ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	10.215m	9.316ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	34.825m	11.887ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	44.968m	23.051ms	3	3	100.00
		chip_sw_pwrmgr_wdog_reset	12.217m	4.765ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	7.488m	5.030ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	7.321m	4.947ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	10.614m	6.510ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	10.858m	4.541ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	37.024m	14.390ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.518m	2.688ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	16.003m	5.865ms	98	100	98.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	29.491m	8.383ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	23.535m	5.819ms	3	3	100.00
		chip_plic_all_irqs_10	10.572m	4.350ms	3	3	100.00
		chip_plic_all_irqs_20	15.812m	4.556ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.583m	2.698ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	4.346m	2.979ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	59.917m	13.891ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	13.037m	6.251ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	11.429m	5.326ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	6.361m	3.126ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	6.425m	2.762ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	12.936m	4.185ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	16.336m	5.783ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	14.723m	7.714ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	10.975m	7.622ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	17.716m	9.995ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	16.003m	5.865ms	98	100	98.00
		chip_sw_data_integrity_escalation	14.089m	5.491ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	4.183m	2.321ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	7.191m	3.362ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	9.133m	4.254ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	10.247m	3.350ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	28.378m	7.906ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.841h	31.683ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	44.400m	11.858ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	5.263m	3.724ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	8.304m	4.748ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	16.003m	5.865ms	98	100	98.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	5.553m	3.815ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	37.024m	14.390ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	10.441m	5.356ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	10.727m	4.213ms	89	90	98.89
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	24.336m	11.149ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	29.048m	7.768ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	29.491m	8.383ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.536h	255.409ms	3	3	100.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	28.270m	12.398ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	26.751m	13.276ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	7.321m	4.947ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	10.802m	4.619ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	11.561m	3.892ms	0	3	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	14.732m	7.504ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	6.695m	10.352ms	3	3	100.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			2610	2635	99.05
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.272m	3.390ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark			0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	14.697m	5.249ms	0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	1.772m	1.934ms	0	1	0.00
		rom_e2e_jtag_debug_dev	2.227m	2.585ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.413m	1.931ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	1.068h	53.115ms	0	1	0.00
		rom_e2e_jtag_inject_dev	1.098h	41.740ms	0	1	0.00
		rom_e2e_jtag_inject_rma	1.001h	54.161ms	0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash			0	0	--
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	9.302m	3.229ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	9.973m	3.040ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	24.327m	4.475ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	36.201m	9.679ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	10.622m	3.539ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	24.058m	5.612ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	//sw/device/tests:i2c_host_override_test			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	5.874m	2.827ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	10.283m	5.203ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	8.284m	5.639ms	3	3	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	8.595m	3.965ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	34.825m	11.887ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	16.003m	5.865ms	98	100	98.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	//sw/device/tests:spi_passthru_test			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	//sw/device/tests:spi_passthru_test			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	13.139m	4.014ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.287h	18.837ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	1.772m	1.934ms	0	1	0.00
		rom_e2e_jtag_debug_dev	2.227m	2.585ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.413m	1.931ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.528m	5.887ms	3	3	100.00
V3		TOTAL			32	45	71.11
	Unmapped tests	chip_sival_flash_info_access	6.383m	3.638ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	12.655m	4.550ms	3	3	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	5.197m	3.529ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	1.167h	16.228ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	19.856m	5.489ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	15.506m	5.151ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	8.923m	4.450ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	5.045m	2.990ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	3.890m	2.796ms	3	3	100.00
		chip_sw_flash_ctrl_write_clear	5.663m	2.625ms	3	3	100.00
		TOTAL			2875	2933	98.02

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	10	10	10	100.00
V1	18	18	17	94.44
V2	282	267	256	90.78
V2S	1	1	1	100.00
V3	90	21	12	13.33

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.84	95.42	93.64	95.49	--	94.45	96.47	99.58

Failure Buckets

UVM_ERROR @ * us: (cip_base_vseq.sv:828) [chip_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test chip_csr_mem_rw_with_rand_reset has 20 failures.
  - 0.chip_csr_mem_rw_with_rand_reset.104525831335857531012693261069298256774345632884946432226054452067727763335641
    Line 362, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1764.916368 us: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1764.916368 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_csr_mem_rw_with_rand_reset.11845871408763106856621040546483850639763227892142701064795804912302459203018
    Line 364, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2042.529740 us: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2042.529740 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 10 failures:
- Test chip_sw_rv_timer_systick_test has 3 failures.
  - 0.chip_sw_rv_timer_systick_test.8431677061430752103068202267022322711835517017726031773329802690819349280737
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:5f92be0b-157d-4986-98de-afb81be018b8
```
  - 1.chip_sw_rv_timer_systick_test.2395901165056989146014099019148064509654671484679076517664074327260632613918
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:889e40c2-832d-4a9f-a5f4-75ace8d0f0e6
```
  - ... and 1 more failures.
- Test chip_sw_coremark has 1 failures.
  - 0.chip_sw_coremark.41467116549908502362799656584881443437558562109425460662027521185542371654301
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
```
  Job ID: smart:c1650943-21a5-4793-8341-9f03ec848aa4
```
- Test chip_sw_power_virus has 2 failures.
  - 0.chip_sw_power_virus.72142346177259268343798103156327301501145841418230093906473166345934620136700
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:66923016-1b9e-4c4b-adda-05fef3510aff
```
  - 2.chip_sw_power_virus.96459656710138434114478720183566937653666288175034060034234072930408512902468
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:87c18962-5d98-468a-b265-7da875a937fb
```
- Test rom_raw_unlock has 1 failures.
  - 0.rom_raw_unlock.80759754028361640420995787337689711911371727388798312536267076814473354714894
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest/run.log
```
  Job ID: smart:1960abb9-d488-4f74-a3a7-9611e110a382
```
- Test chip_sw_uart_tx_rx_bootstrap has 2 failures.
  - 1.chip_sw_uart_tx_rx_bootstrap.73698570603322443373248866028659411321425585642272195908707368609580613436389
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_bootstrap/latest/run.log
```
  Job ID: smart:93d469bc-e88b-4f62-99c4-b8ae469714ea
```
  - 2.chip_sw_uart_tx_rx_bootstrap.71423368159208542804350754815509920173245624370962264100211978647992328349822
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_bootstrap/latest/run.log
```
  Job ID: smart:81de5298-973e-4084-bc07-ba858d150b85
```
- ... and 1 more tests.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c:101)] DIF-fail: dif_keymgr_advance_state(keymgr, params) returns * has 3 failures:
- Test chip_sw_flash_ctrl_lc_rw_en has 3 failures.
  - 0.chip_sw_flash_ctrl_lc_rw_en.72257107149441052320217271291483962397989452851885936340950362581903073723342
    Line 858, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_lc_rw_en/latest/run.log
```
  UVM_ERROR @ 2815.300104 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c:101)] DIF-fail: dif_keymgr_advance_state(keymgr, params) returns 3
  UVM_INFO @ 2815.300104 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_flash_ctrl_lc_rw_en.90753844804207654334877294396361322194074337394244292063256087281939862696737
    Line 843, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_lc_rw_en/latest/run.log
```
  UVM_ERROR @ 2939.347856 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c:101)] DIF-fail: dif_keymgr_advance_state(keymgr, params) returns 3
  UVM_INFO @ 2939.347856 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat" has 3 failures:
- Test chip_sw_sysrst_ctrl_outputs has 3 failures.
  - 0.chip_sw_sysrst_ctrl_outputs.107414978898610822876246985678202319668683717773725533200374662859366944916141
    Line 841, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_sysrst_ctrl_outputs.36877958675684122002739073835025321942450095241048681019465238176440816429708
    Line 811, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:
- Test chip_sw_lc_ctrl_program_error has 3 failures.
  - 0.chip_sw_lc_ctrl_program_error.108688731147936048850012695922049792450660237406071570727488719643447440226182
    Line 826, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 15029.639920 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 15029.639920 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.chip_sw_lc_ctrl_program_error.53459300800864092126962809271452444890999867577022444037048551552872459184523
    Line 788, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 15138.069032 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 15138.069032 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep. has 3 failures:
- Test chip_sw_rv_dm_access_after_wakeup has 3 failures.
  - 0.chip_sw_rv_dm_access_after_wakeup.3450425920283934260468866595756315562514341382888016958284599107735402165582
    Line 945, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3823.948107 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3823.948107 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_rv_dm_access_after_wakeup.8078496864942938758263009321272392785683785583222583037465241704767961903282
    Line 810, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 4005.423842 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 4005.423842 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.32068424982759150397904578164204857074369354005237481413009937072912721858155
    Line 776, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 1934.306500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 1934.306500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.106062900058443101343940341402769903137057181697246857523709169203389315308071
    Line 793, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 2585.308500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2585.308500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.6723818927423823296834747949391790112198713048595799394699004601064740186143
    Line 742, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 1931.220500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 1931.220500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 3 failures:
- Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_inject_test_unlocked0.48891650146129658796681756693702631069810713622589974329213484104688751651480
    Line 817, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 53114.990498 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 53114.990498 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_dev has 1 failures.
  - 0.rom_e2e_jtag_inject_dev.74066073596956886959972557313558962186353442909029371069926454733362548697843
    Line 795, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log
```
  UVM_FATAL @ 41739.945476 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 41739.945476 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_rma has 1 failures.
  - 0.rom_e2e_jtag_inject_rma.18357515292519493295206543482438611995721893989365043558380279246871275550546
    Line 867, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log
```
  UVM_FATAL @ 54160.861986 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 54160.861986 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 3 failures:
- Test rom_e2e_static_critical has 3 failures.
  - 0.rom_e2e_static_critical.101140227536196488384346696552362890838476132032510638260382334160784575455715
    Line 823, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_static_critical/latest/run.log
```
  UVM_ERROR @ 20022.399091 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 20000000 ns
  
  UVM_INFO @ 20022.399091 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.rom_e2e_static_critical.95909578424172569640024947299665921749173158230743624338761790201116277393692
    Line 870, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_static_critical/latest/run.log
```
  UVM_ERROR @ 20014.720411 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 20000000 ns
  
  UVM_INFO @ 20014.720411 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 2 failures:

Test rom_raw_unlock has 2 failures.

1.rom_raw_unlock.25375208375283631160052455686835532925564518917177844566321401168316333692077
Line 850, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_raw_unlock/latest/run.log

  UVM_ERROR @ 206958.108412 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns
  
  UVM_INFO @ 206958.108412 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.rom_raw_unlock.76226423316184460726810321565847700560733161803865810481219325409493244549161
Line 776, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.rom_raw_unlock/latest/run.log

  UVM_ERROR @ 205027.488966 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns
  
  UVM_INFO @ 205027.488966 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 2 failures:
- Test chip_sw_all_escalation_resets has 2 failures.
  - 45.chip_sw_all_escalation_resets.64652298804846666980992599096051023376989219680792047755093987989093757161687
    Line 758, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/45.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2436.729032 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 2436.729032 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 82.chip_sw_all_escalation_resets.92268398659714169718457977432845274802163207967593069269131768114297096940146
    Line 762, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/82.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2913.806776 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 2913.806776 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:178) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 1.chip_sw_power_virus.15617121203474111741451035469230890736073066194162600039414727505815083095235
    Line 979, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 5248.530466 us: (chip_sw_power_virus_vseq.sv:178) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 5248.530466 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits * and * set in filter status, got status * has 1 failures:
- Test chip_sw_pwrmgr_normal_sleep_all_wake_ups has 1 failures.
  - 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.93160295088949449373407425276086322226406924182559306695007234477373560296771
    Line 808, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log
```
  UVM_ERROR @ 6378.064608 us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits 5 and 8 set in filter status, got status 0x100
  UVM_INFO @ 6378.064608 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 44.chip_sw_alert_handler_lpg_sleep_mode_alerts.94659431126559660671749379327722833430296938962667103155251690387151700927900
    Line 785, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3394.490448 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003720 MTVAL=40600800
  UVM_INFO @ 3394.490448 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```