CHIP Simulation Results

Thursday May 30 2024 19:02:59 UTC

GitHub Revision: `8cb25a6867`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 26638040090898561482658723926798947801831709189350919955228328310045202344042

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	4.090m	3.073ms	3	3	100.00
		chip_sw_example_rom	2.266m	3.160ms	3	3	100.00
		chip_sw_example_manufacturer	5.479m	3.197ms	3	3	100.00
		chip_sw_example_concurrency	5.183m	2.955ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset	4.030m	4.710ms	5	5	100.00
V1	csr_rw	chip_csr_rw	11.571m	6.111ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	27.097m	11.823ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	2.745h	62.981ms	4	5	80.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	1.994m	2.679ms	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	2.745h	62.981ms	4	5	80.00
		chip_csr_rw	11.571m	6.111ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	11.000s	237.552us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	9.725m	4.525ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	9.725m	4.525ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	9.725m	4.525ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	11.066m	4.112ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	11.066m	4.112ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	11.434m	4.676ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	12.159m	3.906ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	14.040m	4.857ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	43.925m	12.878ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	45.770m	13.167ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	31.442m	13.213ms	5	5	100.00
V1		TOTAL			199	220	90.45
V2	chip_pin_mux	chip_padctrl_attributes	5.386m	5.395ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	5.386m	5.395ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	4.952m	2.463ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	7.684m	4.883ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	7.220m	4.400ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	21.250m	10.907ms	5	5	100.00
		chip_tap_straps_testunlock0	15.419m	9.435ms	5	5	100.00
		chip_tap_straps_rma	14.040m	9.696ms	5	5	100.00
		chip_tap_straps_prod	17.315m	10.300ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	5.364m	3.052ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	24.674m	9.249ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	14.626m	6.151ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	14.626m	6.151ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	19.121m	7.856ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	45.201m	21.679ms	2	3	66.67
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	12.058m	4.353ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	18.664m	5.219ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	58.959m	19.718ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.021m	2.357ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	20.986m	7.069ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.033m	2.497ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	34.630m	9.267ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.595m	2.475ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.907m	5.009ms	3	3	100.00
		chip_sw_clkmgr_jitter	5.053m	2.366ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	6.103m	2.887ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	13.747m	4.955ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	7.049m	4.938ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	4.246m	3.179ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	7.049m	4.938ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	4.857m	2.800ms	3	3	100.00
		chip_sw_aes_smoketest	5.159m	2.991ms	3	3	100.00
		chip_sw_aon_timer_smoketest	5.478m	2.708ms	3	3	100.00
		chip_sw_clkmgr_smoketest	5.338m	2.964ms	3	3	100.00
		chip_sw_csrng_smoketest	3.903m	2.420ms	3	3	100.00
		chip_sw_entropy_src_smoketest	11.641m	3.672ms	3	3	100.00
		chip_sw_gpio_smoketest	5.925m	3.410ms	3	3	100.00
		chip_sw_hmac_smoketest	7.409m	2.697ms	3	3	100.00
		chip_sw_kmac_smoketest	5.623m	3.235ms	3	3	100.00
		chip_sw_otbn_smoketest	39.441m	11.406ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	8.715m	5.573ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	7.939m	4.817ms	3	3	100.00
		chip_sw_rv_plic_smoketest	3.763m	2.716ms	3	3	100.00
		chip_sw_rv_timer_smoketest	4.686m	2.691ms	3	3	100.00
		chip_sw_rstmgr_smoketest	4.209m	3.429ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	5.122m	3.081ms	3	3	100.00
		chip_sw_uart_smoketest	5.572m	3.056ms	3	3	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	5.621m	3.137ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	11.938m	4.405ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.734h	78.127ms	3	3	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	1.124h	15.098ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	4.874h	204.624ms	0	3	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	13.186m	4.800ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	10.753m	11.106ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	3.207h	58.830ms	3	3	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.313h	65.505ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	7.145m	4.560ms	30	30	100.00
V2	tl_d_illegal_access	chip_tl_errors	7.145m	4.560ms	30	30	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	2.745h	62.981ms	4	5	80.00
		chip_same_csr_outstanding	1.493h	31.803ms	20	20	100.00
		chip_csr_hw_reset	4.030m	4.710ms	5	5	100.00
		chip_csr_rw	11.571m	6.111ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	2.745h	62.981ms	4	5	80.00
		chip_same_csr_outstanding	1.493h	31.803ms	20	20	100.00
		chip_csr_hw_reset	4.030m	4.710ms	5	5	100.00
		chip_csr_rw	11.571m	6.111ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.762m	2.646ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.480s	58.708us	100	100	100.00
		xbar_smoke_large_delays	2.042m	10.435ms	100	100	100.00
		xbar_smoke_slow_rsp	1.892m	6.424ms	100	100	100.00
		xbar_random_zero_delays	53.860s	570.168us	100	100	100.00
		xbar_random_large_delays	23.132m	115.504ms	100	100	100.00
		xbar_random_slow_rsp	22.605m	68.192ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.005m	1.471ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.038m	1.481ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.647m	2.763ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.038m	1.481ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.688m	3.714ms	100	100	100.00
		xbar_access_same_device_slow_rsp	48.188m	166.814ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.480m	2.738ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	13.780m	16.387ms	100	100	100.00
		xbar_stress_all_with_error	14.616m	20.368ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	16.465m	20.218ms	100	100	100.00
		xbar_stress_all_with_reset_error	15.822m	20.568ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	1.124h	15.098ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	56.213m	28.875ms	3	3	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	58.536m	14.020ms	3	3	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	55.052m	11.297ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	54.310m	13.891ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	1.023h	14.097ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	1.086h	14.228ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	1.044h	14.414ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	45.058m	10.832ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	56.334m	14.234ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	1.046h	14.069ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	1.084h	14.640ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	58.412m	13.766ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	1.597h	17.656ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	1.452h	22.324ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	1.678h	22.239ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	1.444h	23.203ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	1.973h	23.347ms	1	1	100.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	1.295h	16.588ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	1.443h	21.045ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	1.546h	22.493ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	1.352h	21.832ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	1.487h	21.730ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	45.602m	10.366ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	49.719m	14.040ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	1.078h	13.689ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	1.050h	13.444ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	54.034m	13.695ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	47.020m	10.842ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	1.017h	13.845ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	55.814m	13.190ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	1.193h	13.413ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	1.150h	13.583ms	1	1	100.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	50.846m	10.962ms	3	3	100.00
		rom_e2e_asm_init_dev	1.086h	14.115ms	3	3	100.00
		rom_e2e_asm_init_prod	55.543m	14.042ms	3	3	100.00
		rom_e2e_asm_init_prod_end	1.041h	14.192ms	3	3	100.00
		rom_e2e_asm_init_rma	59.371m	14.669ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	1.068h	15.187ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	58.683m	14.470ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	1.242h	14.689ms	3	3	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	1.342h	20.025ms	0	3	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	5.662m	3.833ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.021m	2.357ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.559m	2.918ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	5.112m	3.354ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	42.093m	13.301ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	9.860m	19.075ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	9.860m	19.075ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	7.068m	4.371ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	8.715m	5.573ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	7.068m	4.371ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	16.003m	9.374ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	16.003m	9.374ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	9.633m	7.887ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	14.046m	5.784ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	18.869m	5.902ms	3	3	100.00
		chip_sw_aes_idle	5.112m	3.354ms	3	3	100.00
		chip_sw_hmac_enc_idle	6.376m	3.126ms	3	3	100.00
		chip_sw_kmac_idle	5.194m	3.238ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	10.513m	5.168ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	8.571m	5.737ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	10.183m	5.184ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	10.111m	5.429ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	23.506m	12.469ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	10.762m	3.491ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.995m	4.956ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.530m	4.008ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.034m	4.617ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.551m	3.489ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.681m	4.527ms	3	3	100.00
		chip_sw_ast_clk_outputs	19.121m	7.856ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	20.729m	11.640ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.530m	4.008ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.034m	4.617ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	12.058m	4.353ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	18.664m	5.219ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	58.959m	19.718ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.021m	2.357ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	20.986m	7.069ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.033m	2.497ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	34.630m	9.267ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.595m	2.475ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.907m	5.009ms	3	3	100.00
		chip_sw_clkmgr_jitter	5.053m	2.366ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.399m	2.613ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	12.427m	5.069ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	21.258m	7.147ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.129h	24.653ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	4.723m	3.243ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	5.236m	2.707ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	28.127m	12.456ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	5.481m	3.650ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	12.827m	5.598ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	40.169m	26.095ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	1.226h	30.080ms	2	3	66.67
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	19.121m	7.856ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.017m	4.608ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	9.158m	3.144ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	14.468m	5.795ms	97	100	97.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	27.544m	6.695ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	32.607m	6.969ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	7.954m	3.380ms	3	3	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	10.978m	4.904ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.837m	2.637ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	23.331m	8.976ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	36.784m	21.687ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	5.267m	3.171ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	43.740s	10.400us	0	3	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	12.953m	4.924ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	36.784m	21.687ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	36.784m	21.687ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	56.596m	20.155ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	56.596m	20.155ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	11.133m	5.321ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	9.860m	19.075ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	2.271h	38.380ms	10	10	100.00
		chip_sw_entropy_src_ast_rng_req	4.098m	2.561ms	3	3	100.00
		chip_sw_edn_entropy_reqs	23.022m	6.779ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	4.098m	2.561ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	32.607m	6.969ms	3	3	100.00
V2	chip_sw_entropy_src_fuse_en_fw_read	chip_sw_entropy_src_fuse_en_fw_read_test			0	0	--
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	4.055m	3.139ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	37.152m	19.739ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	19.749m	6.049ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	18.664m	5.219ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	11.200m	3.960ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	12.058m	4.353ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.490h	43.772ms	3	3	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	37.152m	19.739ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	8.151m	4.163ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	36.508m	11.676ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.791m	2.597ms	0	3	0.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.490h	43.772ms	3	3	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.791m	2.597ms	0	3	0.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.791m	2.597ms	0	3	0.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.791m	2.597ms	0	3	0.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.791m	2.597ms	0	3	0.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	14.468m	5.795ms	97	100	97.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	8.601m	15.501ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	18.810m	5.772ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	11.420m	6.622ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	11.420m	6.622ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	6.097m	3.580ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.033m	2.497ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	6.376m	3.126ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	14.051m	4.896ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	17.523m	6.132ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	14.589m	5.361ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	11.171m	4.094ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	36.508m	11.676ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	34.630m	9.267ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	43.124m	10.840ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	42.093m	13.301ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	52.594m	10.385ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.731m	3.457ms	3	3	100.00
		chip_sw_kmac_mode_kmac	5.024m	2.533ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.595m	2.475ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	36.508m	11.676ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	19.749m	11.734ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	3.554m	2.591ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.934m	2.951ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	5.194m	3.238ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	10.699m	5.190ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	21.250m	10.907ms	5	5	100.00
		chip_tap_straps_rma	14.040m	9.696ms	5	5	100.00
		chip_tap_straps_prod	17.315m	10.300ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.801m	2.883ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	19.749m	11.734ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	19.749m	11.734ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	19.749m	11.734ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	37.552m	8.725ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.791m	2.597ms	0	3	0.00
		chip_sw_flash_rma_unlocked	1.490h	43.772ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.743m	4.616ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	26.482m	9.347ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	25.553m	9.494ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	23.662m	7.744ms	3	3	100.00
		chip_sw_lc_ctrl_transition	19.749m	11.734ms	15	15	100.00
		chip_sw_keymgr_key_derivation	36.508m	11.676ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	9.868m	9.045ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	16.010m	9.972ms	3	3	100.00
		chip_prim_tl_access	8.601m	15.501ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	20.729m	11.640ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	10.762m	3.491ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.995m	4.956ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.530m	4.008ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.034m	4.617ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.551m	3.489ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.681m	4.527ms	3	3	100.00
		chip_tap_straps_dev	21.250m	10.907ms	5	5	100.00
		chip_tap_straps_rma	14.040m	9.696ms	5	5	100.00
		chip_tap_straps_prod	17.315m	10.300ms	5	5	100.00
		chip_rv_dm_lc_disabled	6.151m	11.839ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.458m	2.608ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.004m	3.064ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.345m	2.543ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.956m	2.810ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	37.852m	24.686ms	3	3	100.00
		chip_rv_dm_lc_disabled	6.151m	11.839ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.522h	47.606ms	3	3	100.00
		chip_sw_lc_walkthrough_prod	1.461h	48.165ms	3	3	100.00
		chip_sw_lc_walkthrough_prodend	18.729m	8.069ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	1.447h	45.289ms	3	3	100.00
		chip_sw_lc_walkthrough_testunlocks	37.852m	24.686ms	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	2.044m	1.940ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	2.050m	3.080ms	3	3	100.00
		rom_volatile_raw_unlock	1.803m	2.234ms	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	19.749m	11.734ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	37.152m	19.739ms	3	3	100.00
		chip_sw_otbn_mem_scramble	9.434m	3.140ms	3	3	100.00
		chip_sw_keymgr_key_derivation	36.508m	11.676ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	13.754m	5.178ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.962m	2.821ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	37.152m	19.739ms	3	3	100.00
		chip_sw_otbn_mem_scramble	9.434m	3.140ms	3	3	100.00
		chip_sw_keymgr_key_derivation	36.508m	11.676ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	13.754m	5.178ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.962m	2.821ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	19.749m	11.734ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	13.482m	14.766ms	0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.801m	2.883ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.743m	4.616ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	26.482m	9.347ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	25.553m	9.494ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	23.662m	7.744ms	3	3	100.00
		chip_sw_lc_ctrl_transition	19.749m	11.734ms	15	15	100.00
		chip_prim_tl_access	8.601m	15.501ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	8.601m	15.501ms	3	3	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	8.928m	7.258ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	28.688m	21.789ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	7.531m	7.523ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	13.024m	7.566ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	15.183m	7.769ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	25.539m	22.095ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	27.531m	16.384ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	16.003m	9.374ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	27.031m	10.642ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	11.403m	5.245ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	8.928m	7.258ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	8.495m	5.224ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	1.001h	30.842ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	9.492m	6.599ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	9.032m	6.551ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	37.699m	24.297ms	2	3	66.67
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	23.331m	8.976ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	36.621m	13.210ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	33.160m	22.064ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	5.092m	3.099ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	14.468m	5.795ms	97	100	97.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	9.868m	9.045ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	9.868m	9.045ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	36.621m	13.210ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	37.699m	24.297ms	2	3	66.67
		chip_sw_pwrmgr_wdog_reset	11.403m	5.245ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	8.715m	5.573ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	6.946m	3.223ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	12.505m	6.449ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	8.583m	3.418ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	30.251m	11.853ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.578m	2.335ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	14.468m	5.795ms	97	100	97.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	33.907m	8.629ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	20.316m	5.850ms	3	3	100.00
		chip_plic_all_irqs_10	12.626m	4.660ms	3	3	100.00
		chip_plic_all_irqs_20	14.044m	4.716ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.815m	2.635ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.597m	3.143ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	1.124h	15.098ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	13.947m	7.129ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	8.828m	3.907ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	5.636m	3.337ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	6.133m	3.558ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	13.754m	5.178ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.907m	5.009ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	13.835m	8.277ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	14.354m	7.636ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	16.010m	9.972ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	14.468m	5.795ms	97	100	97.00
		chip_sw_data_integrity_escalation	14.626m	6.151ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	4.779m	2.516ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	6.015m	3.202ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	7.120m	4.046ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	9.507m	3.974ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	32.087m	8.008ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.740h	31.368ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	48.818m	12.358ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	6.654m	3.236ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	10.699m	5.190ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	14.468m	5.795ms	97	100	97.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	5.952m	3.152ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	30.251m	11.853ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	8.325m	3.952ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	8.962m	3.398ms	89	90	98.89
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	22.047m	11.388ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	27.544m	6.695ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	33.907m	8.629ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.347h	256.061ms	3	3	100.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	45.150m	20.549ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	27.604m	13.650ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	6.946m	3.223ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.247m	4.449ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	9.218m	3.487ms	0	3	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	14.040m	9.696ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	6.151m	11.839ms	3	3	100.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			2609	2634	99.05
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	6.704m	3.210ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark			0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	16.549m	5.242ms	0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	1.655m	2.713ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.741m	1.786ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.483m	2.244ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	55.617m	41.389ms	0	1	0.00
		rom_e2e_jtag_inject_dev	55.126m	52.475ms	0	1	0.00
		rom_e2e_jtag_inject_rma	47.022m	42.287ms	0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash			0	0	--
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.604m	2.985ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	9.871m	3.194ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	22.773m	6.334ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	38.920m	10.542ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	11.722m	3.062ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	18.787m	5.376ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	//sw/device/tests:i2c_host_override_test			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	2.211m	2.463ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	10.950m	5.667ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	9.640m	6.172ms	3	3	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	9.430m	5.446ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	36.621m	13.210ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	14.468m	5.795ms	97	100	97.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.859h	38.152ms	1	3	33.33
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.859h	38.152ms	1	3	33.33
V3	chip_sw_spi_device_pass_through_flash_model	//sw/device/tests:spi_passthru_test			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	//sw/device/tests:spi_passthru_test			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	11.066m	4.112ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.162h	18.507ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	1.655m	2.713ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.741m	1.786ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.483m	2.244ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.681m	5.742ms	3	3	100.00
V3		TOTAL			33	45	73.33
	Unmapped tests	chip_sival_flash_info_access	5.131m	3.497ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	11.224m	5.334ms	3	3	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	6.431m	2.918ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	54.005m	16.473ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	20.397m	5.972ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	16.437m	4.486ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	9.687m	5.473ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	4.559m	2.073ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	4.339m	2.951ms	3	3	100.00
		chip_sw_flash_ctrl_write_clear	7.059m	3.787ms	3	3	100.00
		TOTAL			2874	2932	98.02

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	10	10	10	100.00
V1	18	18	16	88.89
V2	281	266	255	90.75
V2S	1	1	1	100.00
V3	90	21	12	13.33

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.13	95.57	94.38	95.52	--	95.30	96.47	99.58

Failure Buckets

UVM_ERROR @ * us: (cip_base_vseq.sv:829) [chip_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test chip_csr_mem_rw_with_rand_reset has 20 failures.
  - 0.chip_csr_mem_rw_with_rand_reset.30091581506527951977786124426231372631616267441239308113378451972614107427553
    Line 398, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2360.314098 us: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2360.314098 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_csr_mem_rw_with_rand_reset.9866818101168834680838031690528573940173955665417211308084211724698199136918
    Line 375, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2678.689228 us: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2678.689228 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 6 failures:
- Test chip_sw_coremark has 1 failures.
  - 0.chip_sw_coremark.102191448845346796814605470296843939413698373583996783109149577370018370654970
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
```
  Job ID: smart:9d8b4f52-7ba7-4fe3-80a2-b9203f114ee2
```
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.80570285421780798645427092611493155490829322183612221338842118238481887986609
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:736ed90b-733c-4ec8-a067-47cb90df6c03
```
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.4747282085396273936218985748270002486646922623246731776597967945441908420610
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:76ff1f72-c81b-4422-9999-e7d4341c3d94
```
- Test chip_sw_rv_timer_systick_test has 2 failures.
  - 1.chip_sw_rv_timer_systick_test.115036522196237369729905616440814038511803212002679194543362408445054411403544
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:7c515c39-a1cf-4aa2-aab7-e5c0e101d5e3
```
  - 2.chip_sw_rv_timer_systick_test.79117432577318149164494819288884314470080310715999215054585188070403307651408
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:fffd51f4-b1e6-403e-a063-8a89ccc24bf5
```
- Test chip_sw_csrng_edn_concurrency_reduced_freq has 1 failures.
  - 1.chip_sw_csrng_edn_concurrency_reduced_freq.103799692851174980743496492754615756868767210509451377012673146852989408544803
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest/run.log
```
  Job ID: smart:7795f232-8513-41a8-a063-7e5c7eb6706a
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c:101)] DIF-fail: dif_keymgr_advance_state(keymgr, params) returns * has 3 failures:
- Test chip_sw_flash_ctrl_lc_rw_en has 3 failures.
  - 0.chip_sw_flash_ctrl_lc_rw_en.42723255400262492521052077284572376415109001893873240088206214002167352611898
    Line 777, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_lc_rw_en/latest/run.log
```
  UVM_ERROR @ 2519.382168 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c:101)] DIF-fail: dif_keymgr_advance_state(keymgr, params) returns 3
  UVM_INFO @ 2519.382168 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_flash_ctrl_lc_rw_en.34025510317654548831401692697447386552411568445199250153660301395735552159865
    Line 783, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_lc_rw_en/latest/run.log
```
  UVM_ERROR @ 2597.276810 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c:101)] DIF-fail: dif_keymgr_advance_state(keymgr, params) returns 3
  UVM_INFO @ 2597.276810 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat" has 3 failures:
- Test chip_sw_sysrst_ctrl_outputs has 3 failures.
  - 0.chip_sw_sysrst_ctrl_outputs.95077390859822203779910714955375288125962477789942508098359833165583680236532
    Line 744, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.400001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_sysrst_ctrl_outputs.77876330943940916635311840257311255115629693581945961472441635142034057232675
    Line 758, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.280001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:
- Test chip_sw_lc_ctrl_program_error has 3 failures.
  - 0.chip_sw_lc_ctrl_program_error.42588098678005900748078366458831089974709768135578210431326105749571293533241
    Line 789, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 14766.306406 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 14766.306406 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.chip_sw_lc_ctrl_program_error.26707299269151150341613202947589560806882683285682578795119560969063704761304
    Line 764, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 15049.501632 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 15049.501632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep. has 3 failures:
- Test chip_sw_rv_dm_access_after_wakeup has 3 failures.
  - 0.chip_sw_rv_dm_access_after_wakeup.98286285677384409489050107652979465151676722147289029037736344029732771430173
    Line 776, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 4462.119832 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 4462.119832 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_rv_dm_access_after_wakeup.75514737423995856261941599656695929536941863585392983091154285738597802358812
    Line 759, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3487.326572 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3487.326572 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.59944152187800787254567349833722716486574708333924673805173480480097696503537
    Line 725, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 2712.571000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2712.571000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.70313566077865047372223325726291846073026052095751242605487146423180841913004
    Line 798, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 1786.342500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 1786.342500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.96575764633342580005651109081443333398987750709494584292485449433379854498141
    Line 725, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 2244.116500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2244.116500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 3 failures:
- Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_inject_test_unlocked0.70869159819507839872804842361753792723157504133022193159608372867979374826137
    Line 780, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 41389.407446 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 41389.407446 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_dev has 1 failures.
  - 0.rom_e2e_jtag_inject_dev.83608388653168412729314923969482041002874166210233756023952336941300554503299
    Line 787, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log
```
  UVM_FATAL @ 52474.723835 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 52474.723835 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_rma has 1 failures.
  - 0.rom_e2e_jtag_inject_rma.61650860360144081348029734290115691518535701262783434867948139015540962966608
    Line 776, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log
```
  UVM_FATAL @ 42287.416271 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 42287.416271 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 3 failures:
- Test rom_e2e_static_critical has 3 failures.
  - 0.rom_e2e_static_critical.63428866164885333862273397432701912754818759116326002756089058443489288337733
    Line 806, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_static_critical/latest/run.log
```
  UVM_ERROR @ 20025.194220 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 20000000 ns
  
  UVM_INFO @ 20025.194220 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.rom_e2e_static_critical.92100982766729373680692962861739608933965097728305506887411632568580106528098
    Line 764, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_static_critical/latest/run.log
```
  UVM_ERROR @ 20025.475519 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 20000000 ns
  
  UVM_INFO @ 20025.475519 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 3 failures:

Test rom_raw_unlock has 3 failures.

0.rom_raw_unlock.47090633500951846333170937004840983025825969651636710045399393888876004003494
Line 839, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest/run.log

  UVM_ERROR @ 205564.283337 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns
  
  UVM_INFO @ 205564.283337 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.rom_raw_unlock.67152932954525076184989124383305457991302820975729790555125551554412669596074
Line 782, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_raw_unlock/latest/run.log

  UVM_ERROR @ 205502.863887 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns
  
  UVM_INFO @ 205502.863887 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 3 failures:
- Test chip_sw_all_escalation_resets has 3 failures.
  - 52.chip_sw_all_escalation_resets.66973920307058766297283641616618923910066174633225566506891547715461252558320
    Line 779, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/52.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3585.333552 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 3585.333552 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 58.chip_sw_all_escalation_resets.25945686765365858158969488067371589845189258706266421403722840586446732215226
    Line 787, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/58.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3872.201768 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 3872.201768 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:178) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 2 failures:
- Test chip_sw_power_virus has 2 failures.
  - 1.chip_sw_power_virus.69898882570991518838503901045541598584019328467783424129051622686392402792707
    Line 1000, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 5241.500252 us: (chip_sw_power_virus_vseq.sv:178) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 5241.500252 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.chip_sw_power_virus.112809237666502848399223542217229476077773662099621009850691378853887084222000
    Line 1042, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 4368.944355 us: (chip_sw_power_virus_vseq.sv:178) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 4368.944355 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(pend_req[h2d.a_source].pend == *)' has 1 failures:
- Test chip_sw_pwrmgr_random_sleep_all_reset_reqs has 1 failures.
  - 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.102789022892107162043605744007728359067208086347566643780276644352823550086833
    Line 828, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log
```
      Offending '(pend_req[h2d.a_source].pend == 0)'
  UVM_ERROR @ 17905.791224 us: (tlul_assert.sv:268) [ASSERT FAILED] pendingReqPerSrc_M
  UVM_INFO @ 17905.791224 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job chip_earlgrey_asic-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test chip_csr_aliasing has 1 failures.
  - 1.chip_csr_aliasing.32895091493402534586550063837385524135234682181776828847379135697852743329965
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_aliasing/latest/run.log
```
  Job ID: smart:e60d21c6-bc29-443f-9ce7-49f9fdb8a9a8
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 40.chip_sw_alert_handler_lpg_sleep_mode_alerts.81675429430218718052541701397383047665866105787849151904445263499749326452384
    Line 805, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3720.080830 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003720 MTVAL=40600800
  UVM_INFO @ 3720.080830 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```