CHIP Simulation Results

Tuesday May 28 2024 19:30:06 UTC

GitHub Revision: `0e5093d709`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 51604449886868634540233838791789448907774502353938218657919214072353062987195

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	5.562m	3.489ms	3	3	100.00
		chip_sw_example_rom	2.008m	2.447ms	3	3	100.00
		chip_sw_example_manufacturer	3.742m	2.356ms	3	3	100.00
		chip_sw_example_concurrency	3.554m	1.934ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset			0	5	0.00
V1	csr_rw	chip_csr_rw			0	20	0.00
V1	csr_bit_bash	chip_csr_bit_bash			0	5	0.00
V1	csr_aliasing	chip_csr_aliasing			0	5	0.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset			0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing			0	5	0.00
		chip_csr_rw			0	20	0.00
V1	xbar_smoke	xbar_smoke			0	100	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	9.493m	3.922ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	9.493m	3.922ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	9.493m	3.922ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	12.556m	4.231ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	12.556m	4.231ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	11.202m	4.070ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	13.809m	5.128ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	13.068m	4.455ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	38.947m	13.299ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	41.787m	12.776ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	24.064m	8.284ms	5	5	100.00
V1		TOTAL			65	220	29.55
V2	chip_pin_mux	chip_padctrl_attributes	5.701m	5.869ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	5.701m	5.869ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	6.867m	2.746ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	5.966m	5.075ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	4.651m	3.495ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	30.905m	18.183ms	5	5	100.00
		chip_tap_straps_testunlock0	10.947m	6.165ms	5	5	100.00
		chip_tap_straps_rma	6.800m	5.024ms	5	5	100.00
		chip_tap_straps_prod	32.417m	16.976ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	4.723m	2.744ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	24.416m	9.206ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	13.138m	5.373ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	13.138m	5.373ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	17.464m	7.316ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs			0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	13.113m	4.201ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	17.876m	6.159ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.171h	18.491ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.025m	3.832ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	19.842m	6.863ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.627m	2.737ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	38.077m	11.741ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.761m	3.163ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.519m	4.957ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.513m	2.734ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	5.204m	2.637ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	19.795m	9.378ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	7.981m	4.591ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	5.593m	3.203ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	7.981m	4.591ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	3.688m	3.375ms	3	3	100.00
		chip_sw_aes_smoketest	5.315m	2.862ms	3	3	100.00
		chip_sw_aon_timer_smoketest	6.345m	3.141ms	3	3	100.00
		chip_sw_clkmgr_smoketest	4.793m	3.183ms	3	3	100.00
		chip_sw_csrng_smoketest	3.900m	3.019ms	3	3	100.00
		chip_sw_entropy_src_smoketest	10.225m	4.056ms	3	3	100.00
		chip_sw_gpio_smoketest	5.247m	2.877ms	3	3	100.00
		chip_sw_hmac_smoketest	6.278m	3.092ms	3	3	100.00
		chip_sw_kmac_smoketest	6.975m	3.412ms	3	3	100.00
		chip_sw_otbn_smoketest	38.525m	10.215ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	6.243m	2.997ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	5.998m	5.512ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	10.262m	5.911ms	3	3	100.00
		chip_sw_rv_plic_smoketest	5.380m	2.463ms	3	3	100.00
		chip_sw_rv_timer_smoketest	4.458m	3.421ms	3	3	100.00
		chip_sw_rstmgr_smoketest	5.235m	3.037ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	3.819m	2.932ms	3	3	100.00
		chip_sw_uart_smoketest	6.535m	2.677ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	11.034m	4.558ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.839h	77.319ms	2	3	66.67
V2	chip_sw_secure_boot	rom_e2e_smoke	1.120h	13.744ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	3.687m	4.333ms	0	3	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	14.681m	3.951ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	8.464m	10.006ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	4.407m	4.012ms	0	3	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.255h	64.615ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors			0	30	0.00
V2	tl_d_illegal_access	chip_tl_errors			0	30	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing			0	5	0.00
		chip_same_csr_outstanding			0	20	0.00
		chip_csr_hw_reset			0	5	0.00
		chip_csr_rw			0	20	0.00
V2	tl_d_partial_access	chip_csr_aliasing			0	5	0.00
		chip_same_csr_outstanding			0	20	0.00
		chip_csr_hw_reset			0	5	0.00
		chip_csr_rw			0	20	0.00
V2	xbar_base_random_sequence	xbar_random			0	100	0.00
V2	xbar_random_delay	xbar_smoke_zero_delays			0	100	0.00
		xbar_smoke_large_delays			0	100	0.00
		xbar_smoke_slow_rsp			0	100	0.00
		xbar_random_zero_delays			0	100	0.00
		xbar_random_large_delays			0	100	0.00
		xbar_random_slow_rsp			0	100	0.00
V2	xbar_unmapped_address	xbar_unmapped_addr			0	100	0.00
		xbar_error_and_unmapped_addr			0	100	0.00
V2	xbar_error_cases	xbar_error_random			0	100	0.00
		xbar_error_and_unmapped_addr			0	100	0.00
V2	xbar_all_access_same_device	xbar_access_same_device			0	100	0.00
		xbar_access_same_device_slow_rsp			0	100	0.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source			0	100	0.00
V2	xbar_stress_all	xbar_stress_all			0	100	0.00
		xbar_stress_all_with_error			0	100	0.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset			0	100	0.00
		xbar_stress_all_with_reset_error			0	100	0.00
V2	rom_e2e_smoke	rom_e2e_smoke	1.120h	13.744ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	58.776m	28.486ms	3	3	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	1.030h	14.263ms	3	3	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	49.562m	10.646ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	57.090m	14.690ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	1.197h	14.570ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	1.032h	14.028ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	1.088h	14.607ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	46.823m	10.280ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	58.972m	14.261ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	1.173h	14.280ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	1.206h	15.030ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	59.555m	14.603ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	1.381h	17.464ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	1.567h	22.529ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	1.676h	21.833ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	1.664h	22.523ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	1.564h	22.138ms	1	1	100.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	1.236h	17.768ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	1.537h	21.690ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	1.465h	22.254ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	1.841h	21.550ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	1.505h	22.537ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	45.377m	10.543ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	1.107h	13.495ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	52.403m	13.696ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	1.177h	13.291ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	1.203h	13.641ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	48.988m	10.317ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	1.097h	13.924ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	1.031h	13.889ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	56.004m	14.094ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	1.095h	13.938ms	1	1	100.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	50.703m	11.557ms	3	3	100.00
		rom_e2e_asm_init_dev	1.121h	14.113ms	3	3	100.00
		rom_e2e_asm_init_prod	1.180h	15.281ms	3	3	100.00
		rom_e2e_asm_init_prod_end	1.107h	14.101ms	3	3	100.00
		rom_e2e_asm_init_rma	59.633m	13.645ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	1.207h	14.831ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	1.027h	14.756ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	1.115h	14.450ms	3	3	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	1.108h	20.015ms	0	3	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	5.281m	2.307ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.025m	3.832ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.151m	2.565ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.691m	2.908ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	44.474m	12.956ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	12.167m	18.845ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	12.167m	18.845ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	6.927m	4.045ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	5.998m	5.512ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	6.927m	4.045ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	19.408m	9.958ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	19.408m	9.958ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	8.271m	7.175ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	10.763m	4.576ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	16.504m	5.399ms	3	3	100.00
		chip_sw_aes_idle	4.691m	2.908ms	3	3	100.00
		chip_sw_hmac_enc_idle	4.008m	2.755ms	3	3	100.00
		chip_sw_kmac_idle	5.015m	2.666ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	11.764m	5.608ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	9.445m	5.744ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	8.283m	3.974ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	11.597m	4.692ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	30.110m	13.186ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.354m	4.132ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.285m	4.870ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.355m	3.628ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.464m	4.294ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.979m	4.276ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.153m	4.651ms	3	3	100.00
		chip_sw_ast_clk_outputs	17.464m	7.316ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	3.245m	3.465ms	0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.355m	3.628ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.464m	4.294ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	13.113m	4.201ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	17.876m	6.159ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.171h	18.491ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.025m	3.832ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	19.842m	6.863ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.627m	2.737ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	38.077m	11.741ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.761m	3.163ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.519m	4.957ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.513m	2.734ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.277m	2.824ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	12.311m	5.022ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	23.059m	7.943ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.034h	24.127ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	5.048m	2.934ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	4.349m	3.673ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	24.999m	7.408ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	5.505m	3.238ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	10.541m	5.127ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	33.553m	27.269ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	1.003h	16.334ms	2	3	66.67
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	17.464m	7.316ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	14.056m	4.910ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	8.156m	2.992ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	15.453m	6.043ms	99	100	99.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	30.313m	7.680ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	30.485m	8.287ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	11.588m	4.619ms	3	3	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	10.925m	6.046ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.255m	2.978ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	18.845m	8.321ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	28.904m	22.332ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	7.225m	3.094ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	43.700s	10.400us	0	3	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	12.455m	5.150ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	28.904m	22.332ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	28.904m	22.332ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	1.055h	20.888ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	1.055h	20.888ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	10.615m	5.747ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	12.167m	18.845ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	2.076h	26.698ms	10	10	100.00
		chip_sw_entropy_src_ast_rng_req	3.522m	2.018ms	3	3	100.00
		chip_sw_edn_entropy_reqs	25.074m	6.825ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	3.522m	2.018ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	30.485m	8.287ms	3	3	100.00
V2	chip_sw_entropy_src_fuse_en_fw_read	chip_sw_entropy_src_fuse_en_fw_read_test			0	0	--
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	4.480m	2.523ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	38.457m	23.685ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	19.179m	6.211ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	17.876m	6.159ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	12.895m	3.999ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	13.113m	4.201ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	7.504m	5.046ms	0	3	0.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	38.457m	23.685ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	6.532m	2.955ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	40.111m	10.145ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.257m	2.818ms	0	3	0.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	7.504m	5.046ms	0	3	0.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.257m	2.818ms	0	3	0.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.257m	2.818ms	0	3	0.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	5.257m	2.818ms	0	3	0.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.257m	2.818ms	0	3	0.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	15.453m	6.043ms	99	100	99.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access			0	3	0.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	20.495m	6.106ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	10.673m	5.757ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	10.673m	5.757ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.922m	2.812ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.627m	2.737ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.008m	2.755ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	13.486m	5.248ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	17.770m	4.947ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	15.036m	5.103ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	11.312m	4.017ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	40.111m	10.145ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	38.077m	11.741ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	32.742m	8.794ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	44.474m	12.956ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.148h	17.526ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	5.989m	3.026ms	3	3	100.00
		chip_sw_kmac_mode_kmac	5.987m	3.319ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.761m	3.163ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	40.111m	10.145ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	3.544m	4.422ms	0	15	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	5.243m	2.790ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	4.373m	2.508ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	5.015m	2.666ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	10.866m	5.424ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	30.905m	18.183ms	5	5	100.00
		chip_tap_straps_rma	6.800m	5.024ms	5	5	100.00
		chip_tap_straps_prod	32.417m	16.976ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.269m	2.768ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	3.544m	4.422ms	0	15	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	3.544m	4.422ms	0	15	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	3.544m	4.422ms	0	15	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	48.022m	12.695ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	5.257m	2.818ms	0	3	0.00
		chip_sw_flash_rma_unlocked	7.504m	5.046ms	0	3	0.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.167m	3.562ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	23.531m	6.562ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	28.162m	8.197ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	25.512m	9.028ms	3	3	100.00
		chip_sw_lc_ctrl_transition	3.544m	4.422ms	0	15	0.00
		chip_sw_keymgr_key_derivation	40.111m	10.145ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	11.418m	8.532ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	17.561m	9.592ms	3	3	100.00
		chip_prim_tl_access			0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_lc	3.245m	3.465ms	0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.354m	4.132ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.285m	4.870ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.355m	3.628ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.464m	4.294ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.979m	4.276ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.153m	4.651ms	3	3	100.00
		chip_tap_straps_dev	30.905m	18.183ms	5	5	100.00
		chip_tap_straps_rma	6.800m	5.024ms	5	5	100.00
		chip_tap_straps_prod	32.417m	16.976ms	5	5	100.00
		chip_rv_dm_lc_disabled			0	3	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.189m	3.233ms	0	1	0.00
		chip_sw_lc_ctrl_raw_to_scrap	3.237m	4.785ms	0	1	0.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.014m	3.413ms	0	1	0.00
		chip_sw_lc_ctrl_rand_to_scrap	3.336m	4.390ms	0	3	0.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	3.391m	4.538ms	0	3	0.00
		chip_rv_dm_lc_disabled			0	3	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	3.087m	4.668ms	0	3	0.00
		chip_sw_lc_walkthrough_prod	2.844m	3.400ms	0	3	0.00
		chip_sw_lc_walkthrough_prodend	3.553m	3.931ms	0	3	0.00
		chip_sw_lc_walkthrough_rma	3.342m	4.589ms	0	3	0.00
		chip_sw_lc_walkthrough_testunlocks	3.391m	4.538ms	0	3	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	3.935m	4.462ms	0	3	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	3.008m	4.458ms	0	3	0.00
		rom_volatile_raw_unlock	4.238m	3.937ms	0	3	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	3.544m	4.422ms	0	15	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	38.457m	23.685ms	3	3	100.00
		chip_sw_otbn_mem_scramble	8.784m	3.639ms	3	3	100.00
		chip_sw_keymgr_key_derivation	40.111m	10.145ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	12.212m	4.387ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.144m	2.779ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	38.457m	23.685ms	3	3	100.00
		chip_sw_otbn_mem_scramble	8.784m	3.639ms	3	3	100.00
		chip_sw_keymgr_key_derivation	40.111m	10.145ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	12.212m	4.387ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.144m	2.779ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	3.544m	4.422ms	0	15	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	15.245m	14.429ms	0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.269m	2.768ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.167m	3.562ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	23.531m	6.562ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	28.162m	8.197ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	25.512m	9.028ms	3	3	100.00
		chip_sw_lc_ctrl_transition	3.544m	4.422ms	0	15	0.00
		chip_prim_tl_access			0	3	0.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access			0	3	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	9.105m	8.920ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	33.162m	23.480ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	7.487m	7.671ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	17.374m	10.037ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	11.566m	7.762ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	34.752m	20.667ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	30.793m	17.143ms	2	3	66.67
		chip_sw_aon_timer_wdog_bite_reset	19.408m	9.958ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	26.396m	10.600ms	2	3	66.67
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	14.567m	5.503ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	9.105m	8.920ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	9.523m	4.253ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	58.721m	37.516ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	8.385m	6.771ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	8.869m	5.615ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	52.065m	29.097ms	3	3	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	18.845m	8.321ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	29.371m	12.726ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	55.370m	25.807ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	4.856m	2.696ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	15.453m	6.043ms	99	100	99.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	11.418m	8.532ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	11.418m	8.532ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	29.371m	12.726ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	52.065m	29.097ms	3	3	100.00
		chip_sw_pwrmgr_wdog_reset	14.567m	5.503ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	5.998m	5.512ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	8.892m	4.100ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	10.736m	5.770ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	7.349m	4.609ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	31.465m	9.540ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	5.426m	2.975ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	15.453m	6.043ms	99	100	99.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	37.524m	8.529ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	20.485m	6.038ms	3	3	100.00
		chip_plic_all_irqs_10	9.696m	4.019ms	3	3	100.00
		chip_plic_all_irqs_20	14.572m	4.206ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	5.355m	2.186ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.149m	3.155ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	1.120h	13.744ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	14.157m	6.892ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	8.609m	4.028ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	7.322m	3.715ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	4.999m	3.485ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	12.212m	4.387ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.519m	4.957ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	11.131m	5.738ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	15.145m	7.508ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	17.561m	9.592ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	15.453m	6.043ms	99	100	99.00
		chip_sw_data_integrity_escalation	13.138m	5.373ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	3.455m	2.779ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	5.019m	3.379ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	7.780m	3.679ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	7.830m	3.440ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	30.511m	8.042ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.874h	32.196ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	48.343m	12.136ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	5.343m	2.626ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	10.866m	5.424ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	15.453m	6.043ms	99	100	99.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	7.613m	3.766ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	31.465m	9.540ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	11.129m	5.547ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	8.825m	3.754ms	88	90	97.78
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	25.130m	11.484ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	30.313m	7.680ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	37.524m	8.529ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.767h	255.069ms	3	3	100.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	23.629m	11.906ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	29.867m	13.405ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	8.892m	4.100ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	9.356m	4.593ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	9.256m	3.810ms	0	3	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	6.800m	5.024ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled			0	3	0.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			796	2634	30.22
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.965m	3.341ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark			0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	16.096m	5.462ms	0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	2.120m	2.747ms	0	1	0.00
		rom_e2e_jtag_debug_dev	2.176m	2.676ms	0	1	0.00
		rom_e2e_jtag_debug_rma	2.147m	2.495ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	1.125h	58.526ms	0	1	0.00
		rom_e2e_jtag_inject_dev	1.208h	60.000ms	0	1	0.00
		rom_e2e_jtag_inject_rma	1.846h	56.973ms	0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash			0	0	--
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	7.184m	3.032ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	11.514m	2.979ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	30.771m	6.933ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	35.404m	8.614ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	11.119m	3.884ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	18.875m	5.858ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	//sw/device/tests:i2c_host_override_test			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	6.657m	3.605ms	0	3	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	9.488m	5.630ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	8.555m	4.785ms	3	3	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	8.198m	4.567ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	29.371m	12.726ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	15.453m	6.043ms	99	100	99.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	//sw/device/tests:spi_passthru_test			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	//sw/device/tests:spi_passthru_test			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	12.556m	4.231ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.451h	18.916ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	2.120m	2.747ms	0	1	0.00
		rom_e2e_jtag_debug_dev	2.176m	2.676ms	0	1	0.00
		rom_e2e_jtag_debug_rma	2.147m	2.495ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.887m	5.025ms	3	3	100.00
V3		TOTAL			29	45	64.44
	Unmapped tests	chip_sival_flash_info_access	5.892m	2.970ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	16.332m	5.665ms	3	3	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	4.700m	3.109ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	1.169h	17.328ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	15.190m	5.710ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	14.048m	4.659ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	9.654m	5.474ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	5.809m	3.381ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	5.506m	3.310ms	3	3	100.00
		chip_sw_flash_ctrl_write_clear	5.510m	3.121ms	3	3	100.00
		TOTAL			923	2932	31.48

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	10	10	10	100.00
V1	18	18	12	66.67
V2	281	266	216	76.87
V2S	1	1	1	100.00
V3	90	21	11	12.22

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
87.73	89.80	79.12	85.50	--	91.49	96.47	83.99

Failure Buckets

launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = The service is currently unavailable. has 956 failures:
- Test chip_csr_bit_bash has 3 failures.
  - 0.chip_csr_bit_bash.91647572913271946412586053948596020755058201910791449159313056161187013170962
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
  - 2.chip_csr_bit_bash.99657425986059043484429059502241014623075939800512598583841704475462440108266
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_csr_bit_bash/latest/run.log
  - ... and 1 more failures.
- Test chip_same_csr_outstanding has 3 failures.
  - 0.chip_same_csr_outstanding.55053484830763011267103115974864565861369319631215304887017793911862320331492
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
  - 2.chip_same_csr_outstanding.39543559452188546811901585552127585599748656025243200575535118200844760112998
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_same_csr_outstanding/latest/run.log
  - ... and 1 more failures.
- Test chip_prim_tl_access has 2 failures.
  - 0.chip_prim_tl_access.71583715986723045650784736906765969586028349143443894353469150555024150674243
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_prim_tl_access/latest/run.log
  - 2.chip_prim_tl_access.55399770337424494786379118864184668704476759315170346743462478581585864802761
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_prim_tl_access/latest/run.log
- Test xbar_smoke has 8 failures.
  - 0.xbar_smoke.33706112078708662726399544228303240475696222031856224253829854632490799978066
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke/latest/run.log
  - 2.xbar_smoke.110752567198449191814679398964628033484411352556639217639592979488945501576380
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke/latest/run.log
  - ... and 6 more failures.
- Test xbar_smoke_large_delays has 8 failures.
  - 0.xbar_smoke_large_delays.46603630611194027791244887496466165576020314253714498289677772816001366557588
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_large_delays/latest/run.log
  - 2.xbar_smoke_large_delays.44100011077454457658156915420652698698677013995234869082944451893033654199528
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_large_delays/latest/run.log
  - ... and 6 more failures.
- ... and 22 more tests.
Job killed most likely because its dependent job failed. has 955 failures:
- Test chip_csr_aliasing has 3 failures.
  - 0.chip_csr_aliasing.82771696786554870034536296799023219107825215192230102143402248328792298360448
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
  - 2.chip_csr_aliasing.10817030396135373858667789252074606915650033253396623871368875802661796895924
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_csr_aliasing/latest/run.log
  - ... and 1 more failures.
- Test chip_tl_errors has 8 failures.
  - 0.chip_tl_errors.54044395145866015275638117626849880048784228652797122071731925609590193191896
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log
  - 2.chip_tl_errors.34870469816813377592494666518356206807436856635406442035454832789927552073760
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_tl_errors/latest/run.log
  - ... and 6 more failures.
- Test chip_rv_dm_lc_disabled has 2 failures.
  - 0.chip_rv_dm_lc_disabled.61763700771787066979669191379053208272260461169542602012542791202351251178961
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
  - 2.chip_rv_dm_lc_disabled.12369656059215376828633606226724816816742523208767174375972390140403316697916
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_rv_dm_lc_disabled/latest/run.log
- Test xbar_smoke_zero_delays has 8 failures.
  - 0.xbar_smoke_zero_delays.12987945382954062415636819719458784278372203222805616283581618148789393331137
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_zero_delays/latest/run.log
  - 2.xbar_smoke_zero_delays.39995614555977850391638554977406447486492084804069843099857727715398474563146
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_zero_delays/latest/run.log
  - ... and 6 more failures.
- Test xbar_smoke_slow_rsp has 8 failures.
  - 0.xbar_smoke_slow_rsp.6728013110310786742078547527710480726873177287771992358647017883330230815844
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_slow_rsp/latest/run.log
  - 2.xbar_smoke_slow_rsp.81383446524200064435865410207398661496605446023292213854666640095762602730642
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_slow_rsp/latest/run.log
  - ... and 6 more failures.
- ... and 22 more tests.

UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_lc_ctrl_transition_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 18 failures:

Test chip_sw_lc_ctrl_transition has 15 failures.

0.chip_sw_lc_ctrl_transition.4692452338677370679966153346817806582225230783495889583601234599122626012342
Line 734, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_transition/latest/run.log

  UVM_FATAL @ 4299.654271 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_transition_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4299.654271 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_ctrl_transition.102754960833903143092940989581470249000147001540990445689075764786096074409662
Line 887, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_transition/latest/run.log

  UVM_FATAL @ 4421.682329 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_transition_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4421.682329 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 13 more failures.

Test chip_sw_clkmgr_external_clk_src_for_lc has 3 failures.

0.chip_sw_clkmgr_external_clk_src_for_lc.26568654396759301206287132923907794132145102396692367921621554170621141622385
Line 742, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_lc/latest/run.log

  UVM_FATAL @ 3413.796257 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_transition_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3413.796257 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_clkmgr_external_clk_src_for_lc.23508260043973726061178782855468450953364424601782191434796723806657983605191
Line 741, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_lc/latest/run.log

  UVM_FATAL @ 3765.833896 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_transition_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3765.833896 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_lc_walkthrough_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 12 failures:

Test chip_sw_lc_walkthrough_dev has 3 failures.

0.chip_sw_lc_walkthrough_dev.11776307174785770571729786407048958128132319386513027040879337569807066368514
Line 734, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_dev/latest/run.log

  UVM_FATAL @ 3117.912451 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3117.912451 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_walkthrough_dev.94652431021968625773450429095012710179736589137643082573616368800994492591708
Line 759, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_dev/latest/run.log

  UVM_FATAL @ 2848.012031 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 2848.012031 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_lc_walkthrough_prod has 3 failures.

0.chip_sw_lc_walkthrough_prod.13667067643723990825271930317446532880498821318332173179554786690400331531200
Line 789, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prod/latest/run.log

  UVM_FATAL @ 3609.989868 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3609.989868 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_walkthrough_prod.77778702703938149860068164298055469879486984858812588005823881313078020177706
Line 730, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_prod/latest/run.log

  UVM_FATAL @ 3520.818686 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3520.818686 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_lc_walkthrough_prodend has 3 failures.

0.chip_sw_lc_walkthrough_prodend.45255053038423706653589288547745759053906792722007378444341512603607999099242
Line 766, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prodend/latest/run.log

  UVM_FATAL @ 3930.564961 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3930.564961 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_walkthrough_prodend.114197247582736133528476173448192252544153947675067664012661022906397523012970
Line 764, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_prodend/latest/run.log

  UVM_FATAL @ 3583.010513 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3583.010513 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_lc_walkthrough_rma has 3 failures.

0.chip_sw_lc_walkthrough_rma.74383183527958747713792278275578919598832956606635281462859290079950997610240
Line 712, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_rma/latest/run.log

  UVM_FATAL @ 4312.407893 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4312.407893 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_walkthrough_rma.30820565128374673074223441127501890756507192934931220831229753361641838751644
Line 737, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_rma/latest/run.log

  UVM_FATAL @ 3396.792368 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3396.792368 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 9 failures:

Test chip_sw_lc_ctrl_volatile_raw_unlock has 3 failures.

0.chip_sw_lc_ctrl_volatile_raw_unlock.32453718595208437320541638891342940437070415274205292616211852283298954330046
Line 752, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest/run.log

  UVM_FATAL @ 4462.379462 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4462.379462 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_ctrl_volatile_raw_unlock.42550132160786193174775100980004493743360291876964912049746407384574564117085
Line 735, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest/run.log

  UVM_FATAL @ 3859.833582 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3859.833582 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz has 3 failures.

0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.115465722388983466542806822491438075062629632974029345297742053830383361767979
Line 739, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest/run.log

  UVM_FATAL @ 4458.415459 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4458.415459 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.114475383172141824449105075996184188798487748416915030470525201413572031941763
Line 768, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest/run.log

  UVM_FATAL @ 2993.793396 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 2993.793396 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test rom_volatile_raw_unlock has 3 failures.

0.rom_volatile_raw_unlock.107191524146603128148946779912267417218499946346070246270983937776298233166481
Line 746, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_volatile_raw_unlock/latest/run.log

  UVM_FATAL @ 4435.551725 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4435.551725 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.rom_volatile_raw_unlock.19007331534666755285238252039041267611542263485552901028204930722656222411362
Line 761, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_volatile_raw_unlock/latest/run.log

  UVM_FATAL @ 3602.077657 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3602.077657 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 9 failures:
- Test chip_sw_rv_timer_systick_test has 3 failures.
  - 0.chip_sw_rv_timer_systick_test.60762439679403665749675799708216511050250606902682836382729965332436332618507
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:2d89ffa2-b724-481b-9f94-7d6b04ed5853
```
  - 1.chip_sw_rv_timer_systick_test.37956353666083736942009616779695960331674842388170589904185387240281883260314
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:9adab23a-3305-4708-8e8f-0e81fd548c47
```
  - ... and 1 more failures.
- Test chip_sw_coremark has 1 failures.
  - 0.chip_sw_coremark.35282305633449127310195631180458804874736383517448220081265686093054751447037
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
```
  Job ID: smart:95b8d1e5-309f-4bf9-81f4-f4733f699fbc
```
- Test chip_sw_csrng_edn_concurrency_reduced_freq has 1 failures.
  - 0.chip_sw_csrng_edn_concurrency_reduced_freq.45975925838783635963733505677192890064040321110669226542727216786214268516216
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest/run.log
```
  Job ID: smart:08fae75f-9fec-471b-9f6c-4f91116daa61
```
- Test chip_sw_ast_clk_rst_inputs has 3 failures.
  - 0.chip_sw_ast_clk_rst_inputs.57705306453390147887771125900486337069367942626514991265997056599597425192227
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:99e01881-7e8b-488d-b5b6-9dfb59fced48
```
  - 1.chip_sw_ast_clk_rst_inputs.115435957592023064666333626824566497739590404408345087219410194838798442820687
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:e1dc6ba5-08a4-4ad2-a00a-d3cedaa7446d
```
  - ... and 1 more failures.
- Test chip_sw_uart_tx_rx_bootstrap has 1 failures.
  - 1.chip_sw_uart_tx_rx_bootstrap.95160361878697962346336335457610925659665046967328963906212196409713533342499
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_bootstrap/latest/run.log
```
  Job ID: smart:4e7a2be0-8f50-468a-834d-edad90a30b65
```

UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 6 failures:

Test chip_sw_lc_ctrl_rma_to_scrap has 1 failures.

0.chip_sw_lc_ctrl_rma_to_scrap.31069532746044748139846726668813203849694127801079314157711269972233532068585
Line 738, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_rma_to_scrap/latest/run.log

  UVM_FATAL @ 3232.833579 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3232.833579 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_lc_ctrl_raw_to_scrap has 1 failures.

0.chip_sw_lc_ctrl_raw_to_scrap.75844119580811129979412618622183542361756507508952282693208970773140558096716
Line 734, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_raw_to_scrap/latest/run.log

  UVM_FATAL @ 4784.588834 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4784.588834 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_lc_ctrl_test_locked0_to_scrap has 1 failures.

0.chip_sw_lc_ctrl_test_locked0_to_scrap.97785818005115716213103091101431883047087518197955834429883622714906151736050
Line 746, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest/run.log

  UVM_FATAL @ 3412.932763 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3412.932763 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_lc_ctrl_rand_to_scrap has 3 failures.

0.chip_sw_lc_ctrl_rand_to_scrap.93831798785407141357215602489606664427777644914863616974802219144579989423155
Line 739, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_rand_to_scrap/latest/run.log

  UVM_FATAL @ 3549.833236 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3549.833236 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_ctrl_rand_to_scrap.6205320203167201911761584569291565281126495754577213199753559968045330556747
Line 756, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_rand_to_scrap/latest/run.log

  UVM_FATAL @ 4068.386076 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4068.386076 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_exit_test_unlocked_bootstrap_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 3 failures:
- Test chip_sw_exit_test_unlocked_bootstrap has 3 failures.
  - 0.chip_sw_exit_test_unlocked_bootstrap.61802125356616540154426628220535761523066563184741901675982755419933919845317
    Line 762, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_exit_test_unlocked_bootstrap/latest/run.log
```
  UVM_FATAL @ 3838.095539 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_exit_test_unlocked_bootstrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3838.095539 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_exit_test_unlocked_bootstrap.59932522311443912068435831007552082843880887905947376074390876899695136672928
    Line 726, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_exit_test_unlocked_bootstrap/latest/run.log
```
  UVM_FATAL @ 3964.658437 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_exit_test_unlocked_bootstrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3964.658437 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c:101)] DIF-fail: dif_keymgr_advance_state(keymgr, params) returns * has 3 failures:
- Test chip_sw_flash_ctrl_lc_rw_en has 3 failures.
  - 0.chip_sw_flash_ctrl_lc_rw_en.71120081091700573686748675716734961358114552723503574803202802742051793833299
    Line 791, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_lc_rw_en/latest/run.log
```
  UVM_ERROR @ 2768.352864 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c:101)] DIF-fail: dif_keymgr_advance_state(keymgr, params) returns 3
  UVM_INFO @ 2768.352864 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_flash_ctrl_lc_rw_en.15531124333955935525205190260579563849353150580839436092131944618487373304671
    Line 748, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_lc_rw_en/latest/run.log
```
  UVM_ERROR @ 2817.812900 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c:101)] DIF-fail: dif_keymgr_advance_state(keymgr, params) returns 3
  UVM_INFO @ 2817.812900 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_flash_rma_unlocked_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 3 failures:
- Test chip_sw_flash_rma_unlocked has 3 failures.
  - 0.chip_sw_flash_rma_unlocked.113900349929516244362121548733729595944998158750959078691548471911738985802087
    Line 709, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_rma_unlocked/latest/run.log
```
  UVM_FATAL @ 4208.499078 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_flash_rma_unlocked_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4208.499078 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_flash_rma_unlocked.72923138355759649984811098798805820964977357712042400762421240893088073093805
    Line 702, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_rma_unlocked/latest/run.log
```
  UVM_FATAL @ 5045.604773 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_flash_rma_unlocked_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 5045.604773 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_otp_ctrl_vendor_test_csr_access_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 3 failures:
- Test chip_sw_otp_ctrl_vendor_test_csr_access has 3 failures.
  - 0.chip_sw_otp_ctrl_vendor_test_csr_access.15076467754600734280592331305189614996444400951882307548262391820299432651198
    Line 783, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest/run.log
```
  UVM_FATAL @ 3440.814304 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_otp_ctrl_vendor_test_csr_access_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3440.814304 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_otp_ctrl_vendor_test_csr_access.98355469821717946203003914174542191410605931389690405756288241243570507087248
    Line 747, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest/run.log
```
  UVM_FATAL @ 3861.856681 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_otp_ctrl_vendor_test_csr_access_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3861.856681 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_lc_walkthrough_testunlocks_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 3 failures:
- Test chip_sw_lc_walkthrough_testunlocks has 3 failures.
  - 0.chip_sw_lc_walkthrough_testunlocks.38378631371569752835996924187980497754997062324701202981027199031014094178615
    Line 722, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_testunlocks/latest/run.log
```
  UVM_FATAL @ 3140.936740 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_testunlocks_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3140.936740 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_lc_walkthrough_testunlocks.95436268425250733308436862003390840136629709681204597900554416134133704186910
    Line 746, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_testunlocks/latest/run.log
```
  UVM_FATAL @ 4896.691562 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_testunlocks_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4896.691562 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat" has 3 failures:
- Test chip_sw_sysrst_ctrl_outputs has 3 failures.
  - 0.chip_sw_sysrst_ctrl_outputs.36669131172737236724180038574195728142631370279314043110493646535761459050418
    Line 953, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.400001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_sysrst_ctrl_outputs.78274498918616194683509884216428400470489452377585404844561388088045231878076
    Line 763, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.180001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:
- Test chip_sw_lc_ctrl_program_error has 3 failures.
  - 0.chip_sw_lc_ctrl_program_error.74293371884701341574772551901858707825720161310917279988051843642994542274351
    Line 795, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 14533.417588 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 14533.417588 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.chip_sw_lc_ctrl_program_error.13311975557921821343302523431274783483151017864724263617634967713318683332184
    Line 759, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 14811.178748 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 14811.178748 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep. has 3 failures:
- Test chip_sw_rv_dm_access_after_wakeup has 3 failures.
  - 0.chip_sw_rv_dm_access_after_wakeup.21975970930382177631332844463810573431604821707873902546319099234099260675366
    Line 741, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3643.463846 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3643.463846 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_rv_dm_access_after_wakeup.14579702714683703365150000317408336900534999037862950209097555148211365520427
    Line 775, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3809.512345 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3809.512345 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:178) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 3 failures:
- Test chip_sw_power_virus has 3 failures.
  - 0.chip_sw_power_virus.51567941366446451332041389565656213849055122719642241611072897318194382963178
    Line 1229, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 5456.826687 us: (chip_sw_power_virus_vseq.sv:178) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 5456.826687 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_power_virus.111889651721325237288806660992589953187072230882094376514154927412918070814205
    Line 1034, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 5462.294582 us: (chip_sw_power_virus_vseq.sv:178) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 5462.294582 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.108206062920946612962392758987590021527182318446804470938134201610849771706792
    Line 744, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 2746.745500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2746.745500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.71464439601165559734749098807138328333569836299675506436084730526094293103799
    Line 737, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 2676.005500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2676.005500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.59698174817781683192649617824055566945666492655914734717618095685575142239614
    Line 725, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 2494.760000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2494.760000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 3 failures:
- Test rom_e2e_static_critical has 3 failures.
  - 0.rom_e2e_static_critical.15502023886696748274698979185975492689330905458087079260344831406124562369029
    Line 802, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_static_critical/latest/run.log
```
  UVM_ERROR @ 20014.910516 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 20000000 ns
  
  UVM_INFO @ 20014.910516 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.rom_e2e_static_critical.99705702700285314852248826041121808792718084607485870768678349374382509750695
    Line 769, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_static_critical/latest/run.log
```
  UVM_ERROR @ 20025.421441 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 20000000 ns
  
  UVM_INFO @ 20025.421441 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.

UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_lc_raw_unlock_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 3 failures:

Test rom_raw_unlock has 3 failures.

0.rom_raw_unlock.48244500395947186069545963209561911880128620729464608147607391782607113401845
Line 778, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest/run.log

  UVM_FATAL @ 4510.381342 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4510.381342 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.rom_raw_unlock.80801215684457801221571775517042934291284927438583698892328611038345883193975
Line 748, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_raw_unlock/latest/run.log

  UVM_FATAL @ 4781.655100 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4781.655100 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Offending '(pend_req[h2d.a_source].pend == *)' has 2 failures:
- Test chip_sw_pwrmgr_deep_sleep_all_reset_reqs has 1 failures.
  - 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.60715591420686535913178762674577056968224227950162585607141993067329433224815
    Line 932, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest/run.log
```
      Offending '(pend_req[h2d.a_source].pend == 0)'
  UVM_ERROR @ 10292.772808 us: (tlul_assert.sv:268) [ASSERT FAILED] pendingReqPerSrc_M
  UVM_INFO @ 10292.772808 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_pwrmgr_normal_sleep_all_reset_reqs has 1 failures.
  - 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.54045357149912557272574951274359146093771408810522830354311815243344066904843
    Line 772, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest/run.log
```
      Offending '(pend_req[h2d.a_source].pend == 0)'
  UVM_ERROR @ 8367.560600 us: (tlul_assert.sv:268) [ASSERT FAILED] pendingReqPerSrc_M
  UVM_INFO @ 8367.560600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 2 failures:
- Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_inject_test_unlocked0.31846557470611817408074825790906122128569727052557919915729340524831486360944
    Line 769, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 58525.682920 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 58525.682920 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_rma has 1 failures.
  - 0.rom_e2e_jtag_inject_rma.74154582357126579038782982942787340087306501294485804655475529020578232992816
    Line 772, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log
```
  UVM_FATAL @ 56973.403311 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 56973.403311 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 2 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 2 failures.
  - 17.chip_sw_alert_handler_lpg_sleep_mode_alerts.50827335237839794354372205997098138795922619329503683457110649695587905052749
    Line 755, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 4117.523900 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003720 MTVAL=40600800
  UVM_INFO @ 4117.523900 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 50.chip_sw_alert_handler_lpg_sleep_mode_alerts.99815292502249403490318467097490165159009212383218895626361867516861263550023
    Line 774, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3320.580176 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003720 MTVAL=40600800
  UVM_INFO @ 3320.580176 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * us hit, indicating a probable testbench issue has 1 failures:
- Test rom_e2e_jtag_inject_dev has 1 failures.
  - 0.rom_e2e_jtag_inject_dev.34316104120110488052584090270983623317521886353988685223162713661980750590134
    Line 779, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log
```
  UVM_FATAL @ 60000.000000 us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 60000.000000 us hit, indicating a probable testbench issue
  UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 1 failures:
- Test chip_sw_all_escalation_resets has 1 failures.
  - 99.chip_sw_all_escalation_resets.36588851471798244316009229308125577573787125344147691916708891697195363715665
    Line 763, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/99.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2180.998880 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 2180.998880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```