32d52b8d41| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | chip_sw_example_tests | chip_sw_example_flash | 5.772m | 2.865ms | 3 | 3 | 100.00 |
| chip_sw_example_rom | 2.231m | 2.272ms | 3 | 3 | 100.00 | ||
| chip_sw_example_manufacturer | 3.936m | 2.641ms | 3 | 3 | 100.00 | ||
| chip_sw_example_concurrency | 5.344m | 2.792ms | 3 | 3 | 100.00 | ||
| V1 | csr_hw_reset | chip_csr_hw_reset | 4.820m | 5.798ms | 5 | 5 | 100.00 |
| V1 | csr_rw | chip_csr_rw | 11.738m | 5.854ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | chip_csr_bit_bash | 1.452h | 47.647ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | chip_csr_aliasing | 2.042h | 39.763ms | 4 | 5 | 80.00 |
| V1 | csr_mem_rw_with_rand_reset | chip_csr_mem_rw_with_rand_reset | 2.213m | 2.610ms | 0 | 20 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 2.042h | 39.763ms | 4 | 5 | 80.00 |
| chip_csr_rw | 11.738m | 5.854ms | 20 | 20 | 100.00 | ||
| V1 | xbar_smoke | xbar_smoke | 10.770s | 242.358us | 100 | 100 | 100.00 |
| V1 | chip_sw_gpio_out | chip_sw_gpio | 10.082m | 4.124ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_in | chip_sw_gpio | 10.082m | 4.124ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_irq | chip_sw_gpio | 10.082m | 4.124ms | 3 | 3 | 100.00 |
| V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 14.957m | 4.549ms | 5 | 5 | 100.00 |
| V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 14.957m | 4.549ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_idx1 | 12.291m | 4.628ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx2 | 13.935m | 4.746ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx3 | 12.319m | 4.213ms | 5 | 5 | 100.00 | ||
| V1 | chip_sw_uart_baud_rate | chip_sw_uart_rand_baudrate | 45.561m | 13.048ms | 20 | 20 | 100.00 |
| V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 28.327m | 7.975ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 31.793m | 13.809ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 199 | 220 | 90.45 | |||
| V2 | chip_pin_mux | chip_padctrl_attributes | 5.729m | 5.602ms | 10 | 10 | 100.00 |
| V2 | chip_padctrl_attributes | chip_padctrl_attributes | 5.729m | 5.602ms | 10 | 10 | 100.00 |
| V2 | chip_sw_sleep_pin_mio_dio_val | chip_sw_sleep_pin_mio_dio_val | 6.764m | 2.525ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 7.770m | 6.028ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 6.411m | 4.822ms | 3 | 3 | 100.00 |
| V2 | chip_sw_tap_strap_sampling | chip_tap_straps_dev | 3.182m | 3.045ms | 5 | 5 | 100.00 |
| chip_tap_straps_testunlock0 | 13.683m | 8.264ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 8.542m | 5.690ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 23.807m | 12.561ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_pattgen_ios | chip_sw_pattgen_ios | 5.440m | 3.137ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pwm_pulses | chip_sw_sleep_pwm_pulses | 25.407m | 9.625ms | 3 | 3 | 100.00 |
| V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 14.959m | 6.215ms | 6 | 6 | 100.00 |
| V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 14.959m | 6.215ms | 6 | 6 | 100.00 |
| V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 19.187m | 6.920ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_clk_rst_inputs | chip_sw_ast_clk_rst_inputs | 29.732m | 16.439ms | 1 | 3 | 33.33 |
| V2 | chip_sw_ast_sys_clk_jitter | chip_sw_flash_ctrl_ops_jitter_en | 13.619m | 4.171ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.966m | 5.516ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.331h | 18.032ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 4.110m | 3.050ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 22.793m | 6.501ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 4.989m | 2.905ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 46.178m | 12.085ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 6.013m | 3.011ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 13.381m | 5.783ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 4.159m | 2.324ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_ast_usb_clk_calib | chip_sw_usb_ast_clk_calib | 6.090m | 3.686ms | 1 | 1 | 100.00 |
| V2 | chip_sw_sensor_ctrl_ast_alerts | chip_sw_sensor_ctrl_alert | 15.294m | 8.542ms | 5 | 5 | 100.00 |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 8.950m | 4.964ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sensor_ctrl_ast_status | chip_sw_sensor_ctrl_status | 5.282m | 3.469ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 8.950m | 4.964ms | 3 | 3 | 100.00 |
| V2 | chip_sw_smoketest | chip_sw_flash_scrambling_smoketest | 4.697m | 3.040ms | 3 | 3 | 100.00 |
| chip_sw_aes_smoketest | 4.875m | 2.862ms | 3 | 3 | 100.00 | ||
| chip_sw_aon_timer_smoketest | 5.001m | 2.604ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_smoketest | 5.103m | 2.527ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_smoketest | 5.580m | 2.783ms | 3 | 3 | 100.00 | ||
| chip_sw_entropy_src_smoketest | 8.546m | 4.369ms | 3 | 3 | 100.00 | ||
| chip_sw_gpio_smoketest | 5.581m | 3.217ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_smoketest | 7.165m | 3.749ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_smoketest | 5.629m | 3.420ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_smoketest | 27.622m | 7.775ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 10.042m | 5.868ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_usbdev_smoketest | 9.130m | 5.622ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_plic_smoketest | 4.074m | 2.386ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_timer_smoketest | 6.410m | 2.973ms | 3 | 3 | 100.00 | ||
| chip_sw_rstmgr_smoketest | 4.575m | 3.068ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_smoketest | 4.900m | 2.981ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest | 6.076m | 3.039ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_smoketest | chip_sw_otp_ctrl_smoketest | 6.273m | 3.614ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_functests | rom_keymgr_functest | 11.197m | 3.955ms | 3 | 3 | 100.00 |
| V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 0 | 3 | 0.00 | ||
| V2 | chip_sw_secure_boot | rom_e2e_smoke | 1.132h | 14.862ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_raw_unlock | rom_raw_unlock | 3.957h | 206.354ms | 0 | 3 | 0.00 |
| V2 | chip_sw_power_idle_load | chip_sw_power_idle_load | 12.541m | 4.084ms | 2 | 3 | 66.67 |
| V2 | chip_sw_power_sleep_load | chip_sw_power_sleep_load | 14.558m | 10.739ms | 3 | 3 | 100.00 |
| V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 3.365h | 59.402ms | 3 | 3 | 100.00 |
| V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 3.263h | 63.029ms | 3 | 3 | 100.00 |
| V2 | tl_d_oob_addr_access | chip_tl_errors | 8.652m | 5.357ms | 30 | 30 | 100.00 |
| V2 | tl_d_illegal_access | chip_tl_errors | 8.652m | 5.357ms | 30 | 30 | 100.00 |
| V2 | tl_d_outstanding_access | chip_csr_aliasing | 2.042h | 39.763ms | 4 | 5 | 80.00 |
| chip_same_csr_outstanding | 1.321h | 28.584ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 4.820m | 5.798ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 11.738m | 5.854ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | chip_csr_aliasing | 2.042h | 39.763ms | 4 | 5 | 80.00 |
| chip_same_csr_outstanding | 1.321h | 28.584ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 4.820m | 5.798ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 11.738m | 5.854ms | 20 | 20 | 100.00 | ||
| V2 | xbar_base_random_sequence | xbar_random | 1.582m | 2.259ms | 100 | 100 | 100.00 |
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 7.710s | 56.377us | 100 | 100 | 100.00 |
| xbar_smoke_large_delays | 2.086m | 11.026ms | 100 | 100 | 100.00 | ||
| xbar_smoke_slow_rsp | 2.079m | 6.793ms | 100 | 100 | 100.00 | ||
| xbar_random_zero_delays | 57.510s | 591.276us | 100 | 100 | 100.00 | ||
| xbar_random_large_delays | 24.287m | 116.642ms | 100 | 100 | 100.00 | ||
| xbar_random_slow_rsp | 21.681m | 68.227ms | 100 | 100 | 100.00 | ||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 1.047m | 1.405ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 1.028m | 1.460ms | 100 | 100 | 100.00 | ||
| V2 | xbar_error_cases | xbar_error_random | 1.684m | 2.530ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 1.028m | 1.460ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 2.500m | 3.373ms | 100 | 100 | 100.00 |
| xbar_access_same_device_slow_rsp | 57.166m | 185.090ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 1.516m | 2.667ms | 100 | 100 | 100.00 |
| V2 | xbar_stress_all | xbar_stress_all | 16.192m | 19.936ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_error | 10.146m | 15.802ms | 100 | 100 | 100.00 | ||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 18.397m | 25.698ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_reset_error | 13.836m | 7.839ms | 100 | 100 | 100.00 | ||
| V2 | rom_e2e_smoke | rom_e2e_smoke | 1.132h | 14.862ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 1.035h | 24.702ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 58.409m | 14.122ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 50.442m | 10.554ms | 1 | 1 | 100.00 |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 1.021h | 14.430ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 1.038h | 14.556ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 1.034h | 14.332ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 57.680m | 14.491ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 46.927m | 10.553ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 1.131h | 14.475ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 59.534m | 14.513ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 1.005h | 15.076ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 59.166m | 14.318ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 1.328h | 17.457ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 1.856h | 22.899ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 1.443h | 22.375ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 1.525h | 22.806ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 1.460h | 22.906ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 1.481h | 17.662ms | 1 | 1 | 100.00 |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 1.395h | 21.786ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 1.532h | 21.858ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 1.431h | 22.681ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 1.541h | 21.720ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 53.027m | 10.461ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 52.427m | 13.850ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 54.805m | 14.071ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 56.721m | 14.399ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 1.137h | 13.608ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 43.691m | 10.597ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 1.156h | 13.689ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 1.035h | 14.307ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 52.048m | 13.794ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 1.032h | 12.945ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 56.137m | 11.260ms | 3 | 3 | 100.00 |
| rom_e2e_asm_init_dev | 1.200h | 14.211ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod | 1.106h | 14.320ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod_end | 1.084h | 13.926ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_rma | 58.166m | 14.803ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 1.048h | 15.913ms | 3 | 3 | 100.00 |
| rom_e2e_keymgr_init_rom_ext_no_meas | 1.088h | 14.488ms | 3 | 3 | 100.00 | ||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 1.256h | 14.442ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_static_critical | rom_e2e_static_critical | 1.171h | 20.015ms | 0 | 3 | 0.00 |
| V2 | chip_sw_aes_enc | chip_sw_aes_enc | 4.950m | 3.128ms | 3 | 3 | 100.00 |
| chip_sw_aes_enc_jitter_en | 4.110m | 3.050ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_aes_multi_block | chip_sw_aes_multi_block | 0 | 0 | -- | ||
| V2 | chip_sw_aes_interrupt_encryption | chip_sw_aes_interrupt_encryption | 0 | 0 | -- | ||
| V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 6.009m | 3.217ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_prng_reseed | chip_sw_aes_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_force_prng_reseed | chip_sw_aes_force_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_idle | chip_sw_aes_idle | 4.350m | 2.618ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_sideload | chip_sw_keymgr_sideload_aes | 38.362m | 11.547ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_debug_cable_irq | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 10.655m | 19.986ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 10.655m | 19.986ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 8.567m | 4.148ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wakeup | chip_sw_pwrmgr_smoketest | 10.042m | 5.868ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 8.567m | 4.148ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 14.542m | 8.517ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 14.542m | 8.517ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 9.295m | 7.341ms | 5 | 5 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 12.820m | 5.136ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_idle_trans | chip_sw_otbn_randomness | 17.910m | 5.324ms | 3 | 3 | 100.00 |
| chip_sw_aes_idle | 4.350m | 2.618ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_idle | 5.160m | 2.508ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_idle | 5.402m | 3.482ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 8.128m | 4.532ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_off_hmac_trans | 8.907m | 4.118ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_kmac_trans | 7.068m | 4.016ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_otbn_trans | 9.926m | 5.224ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_peri | chip_sw_clkmgr_off_peri | 26.986m | 9.881ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_div | chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 12.448m | 4.652ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 13.967m | 4.989ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 12.453m | 4.050ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 11.786m | 4.192ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 12.792m | 3.834ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 11.037m | 4.775ms | 3 | 3 | 100.00 | ||
| chip_sw_ast_clk_outputs | 19.187m | 6.920ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_external_clk_src_for_lc | chip_sw_clkmgr_external_clk_src_for_lc | 11.651m | 11.109ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_external_clk_src_for_sw | chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 12.453m | 4.050ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 11.786m | 4.192ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_jitter | chip_sw_flash_ctrl_ops_jitter_en | 13.619m | 4.171ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.966m | 5.516ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.331h | 18.032ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 4.110m | 3.050ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 22.793m | 6.501ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 4.989m | 2.905ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 46.178m | 12.085ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 6.013m | 3.011ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 13.381m | 5.783ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 4.159m | 2.324ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 4.832m | 3.478ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 14.201m | 5.192ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 17.776m | 6.751ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 1.235h | 25.141ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 5.381m | 3.543ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 5.290m | 2.925ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 37.714m | 11.117ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 6.729m | 3.058ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 11.203m | 5.041ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_init_reduced_freq | 41.738m | 19.737ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 1.981h | 48.598ms | 2 | 3 | 66.67 | ||
| V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 19.187m | 6.920ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 11.931m | 4.479ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 8.972m | 3.122ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 15.587m | 6.374ms | 98 | 100 | 98.00 |
| V2 | chip_sw_clkmgr_alert_handler_clock_enables | chip_sw_alert_handler_lpg_clkoff | 27.462m | 6.578ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 24.462m | 7.712ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 6.973m | 5.466ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_lc_hw_debug_en | chip_sw_csrng_lc_hw_debug_en_test | 13.712m | 6.168ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 5.479m | 3.743ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 26.409m | 8.396ms | 3 | 3 | 100.00 |
| chip_sw_sysrst_ctrl_reset | 34.347m | 24.301ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sysrst_ctrl_inputs | chip_sw_sysrst_ctrl_inputs | 5.506m | 2.865ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_outputs | chip_sw_sysrst_ctrl_outputs | 43.940s | 10.160us | 0 | 3 | 0.00 |
| V2 | chip_sw_sysrst_ctrl_in_irq | chip_sw_sysrst_ctrl_in_irq | 10.931m | 4.741ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_wakeup | chip_sw_sysrst_ctrl_reset | 34.347m | 24.301ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_reset | chip_sw_sysrst_ctrl_reset | 34.347m | 24.301ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ec_rst_l | chip_sw_sysrst_ctrl_ec_rst_l | 56.814m | 20.311ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_flash_wp_l | chip_sw_sysrst_ctrl_ec_rst_l | 56.814m | 20.311ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ulp_z3_wakeup | chip_sw_sysrst_ctrl_ulp_z3_wakeup | 11.883m | 5.946ms | 3 | 3 | 100.00 |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 10.655m | 19.986ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 1.346h | 23.391ms | 10 | 10 | 100.00 |
| chip_sw_entropy_src_ast_rng_req | 4.085m | 2.473ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs | 22.059m | 7.385ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_entropy_src_ast_rng_req | chip_sw_entropy_src_ast_rng_req | 4.085m | 2.473ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 24.462m | 7.712ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fuse_en_fw_read | chip_sw_entropy_src_fuse_en_fw_read_test | 0 | 0 | -- | ||
| V2 | chip_sw_entropy_src_known_answer_tests | chip_sw_entropy_src_kat_test | 4.793m | 3.446ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fw_observe_many_contiguous | chip_sw_entropy_src_fw_observe_many_contiguous | 0 | 0 | -- | ||
| V2 | chip_sw_entropy_src_fw_extract_and_insert | chip_sw_entropy_src_fw_extract_and_insert | 0 | 0 | -- | ||
| V2 | chip_sw_flash_init | chip_sw_flash_init | 36.358m | 23.083ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_host_access | chip_sw_flash_ctrl_access | 18.417m | 5.435ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.966m | 5.516ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_ctrl_ops | chip_sw_flash_ctrl_ops | 14.579m | 4.256ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en | 13.619m | 4.171ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_rma_unlocked | chip_sw_flash_rma_unlocked | 1.773h | 44.235ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_scramble | chip_sw_flash_init | 36.358m | 23.083ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_idle_low_power | chip_sw_flash_ctrl_idle_low_power | 6.088m | 3.376ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_keymgr_seeds | chip_sw_keymgr_key_derivation | 35.801m | 10.133ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_creator_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 4.631m | 2.508ms | 0 | 3 | 0.00 |
| V2 | chip_sw_flash_creator_seed_wipe_on_rma | chip_sw_flash_rma_unlocked | 1.773h | 44.235ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_owner_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 4.631m | 2.508ms | 0 | 3 | 0.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 4.631m | 2.508ms | 0 | 3 | 0.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_wr_en | chip_sw_flash_ctrl_lc_rw_en | 4.631m | 2.508ms | 0 | 3 | 0.00 |
| V2 | chip_sw_flash_lc_seed_hw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 4.631m | 2.508ms | 0 | 3 | 0.00 |
| V2 | chip_sw_flash_lc_escalate_en | chip_sw_all_escalation_resets | 15.587m | 6.374ms | 98 | 100 | 98.00 |
| V2 | chip_sw_flash_prim_tl_access | chip_prim_tl_access | 6.252m | 8.949ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_clock_freqs | chip_sw_flash_ctrl_clock_freqs | 23.553m | 5.282ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_escalation_reset | chip_sw_flash_crash_alert | 12.873m | 6.503ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_write_clear | chip_sw_flash_crash_alert | 12.873m | 6.503ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 4.526m | 2.882ms | 3 | 3 | 100.00 |
| chip_sw_hmac_enc_jitter_en | 4.989m | 2.905ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 5.160m | 2.508ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_all_configurations | chip_sw_hmac_oneshot | 6.196m | 2.622ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_multistream_mode | chip_sw_hmac_multistream | 25.099m | 7.426ms | 3 | 3 | 100.00 |
| V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 15.716m | 5.577ms | 3 | 3 | 100.00 |
| chip_sw_i2c_host_tx_rx_idx1 | 15.583m | 5.395ms | 3 | 3 | 100.00 | ||
| chip_sw_i2c_host_tx_rx_idx2 | 15.620m | 5.098ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 11.174m | 3.598ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_key_derivation | chip_sw_keymgr_key_derivation | 35.801m | 10.133ms | 3 | 3 | 100.00 |
| chip_sw_keymgr_key_derivation_jitter_en | 46.178m | 12.085ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_keymgr_sideload_kmac | chip_sw_keymgr_sideload_kmac | 35.454m | 8.956ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_aes | chip_sw_keymgr_sideload_aes | 38.362m | 11.547ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_otbn | chip_sw_keymgr_sideload_otbn | 1.377h | 17.272ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 5.446m | 2.613ms | 3 | 3 | 100.00 |
| chip_sw_kmac_mode_kmac | 5.577m | 2.562ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 6.013m | 3.011ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_key_derivation | 35.801m | 10.133ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 21.957m | 10.512ms | 15 | 15 | 100.00 |
| V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 5.098m | 2.763ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 5.500m | 3.230ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 5.402m | 3.482ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 10.089m | 4.948ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_jtag_access | chip_tap_straps_dev | 3.182m | 3.045ms | 5 | 5 | 100.00 |
| chip_tap_straps_rma | 8.542m | 5.690ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 23.807m | 12.561ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_otp_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 4.904m | 3.068ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 21.957m | 10.512ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 21.957m | 10.512ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 21.957m | 10.512ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_key_derivation_prod | 34.395m | 11.912ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_broadcast | chip_sw_flash_ctrl_lc_rw_en | 4.631m | 2.508ms | 0 | 3 | 0.00 |
| chip_sw_flash_rma_unlocked | 1.773h | 44.235ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 12.408m | 4.222ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_dev | 24.037m | 7.351ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 23.034m | 9.578ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 27.528m | 7.417ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 21.957m | 10.512ms | 15 | 15 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 35.801m | 10.133ms | 3 | 3 | 100.00 | ||
| chip_sw_rom_ctrl_integrity_check | 10.669m | 9.577ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_execution_main | 13.976m | 7.091ms | 3 | 3 | 100.00 | ||
| chip_prim_tl_access | 6.252m | 8.949ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_lc | 11.651m | 11.109ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 12.448m | 4.652ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 13.967m | 4.989ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 12.453m | 4.050ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 11.786m | 4.192ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 12.792m | 3.834ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 11.037m | 4.775ms | 3 | 3 | 100.00 | ||
| chip_tap_straps_dev | 3.182m | 3.045ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 8.542m | 5.690ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 23.807m | 12.561ms | 5 | 5 | 100.00 | ||
| chip_rv_dm_lc_disabled | 12.076m | 14.507ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 2.922m | 3.274ms | 1 | 1 | 100.00 |
| chip_sw_lc_ctrl_raw_to_scrap | 2.174m | 2.514ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 2.501m | 3.569ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_rand_to_scrap | 4.262m | 3.313ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_test_locked | chip_sw_lc_walkthrough_testunlocks | 45.948m | 33.841ms | 3 | 3 | 100.00 |
| chip_rv_dm_lc_disabled | 12.076m | 14.507ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 1.559h | 47.952ms | 3 | 3 | 100.00 |
| chip_sw_lc_walkthrough_prod | 1.710h | 46.591ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_prodend | 17.819m | 11.027ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_rma | 1.548h | 48.959ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_testunlocks | 45.948m | 33.841ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 2.025m | 2.346ms | 3 | 3 | 100.00 |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 2.103m | 2.365ms | 3 | 3 | 100.00 | ||
| rom_volatile_raw_unlock | 1.901m | 2.664ms | 3 | 3 | 100.00 | ||
| V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 21.957m | 10.512ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_keys | chip_sw_flash_init | 36.358m | 23.083ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 8.775m | 3.213ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 35.801m | 10.133ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 12.060m | 5.056ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 4.322m | 3.204ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_entropy | chip_sw_flash_init | 36.358m | 23.083ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 8.775m | 3.213ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 35.801m | 10.133ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 12.060m | 5.056ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 4.322m | 3.204ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 21.957m | 10.512ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 13.703m | 14.826ms | 0 | 3 | 0.00 |
| V2 | chip_sw_otp_ctrl_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 4.904m | 3.068ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_lc_signals | chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 12.408m | 4.222ms | 3 | 3 | 100.00 |
| chip_sw_otp_ctrl_lc_signals_dev | 24.037m | 7.351ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 23.034m | 9.578ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 27.528m | 7.417ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 21.957m | 10.512ms | 15 | 15 | 100.00 | ||
| chip_prim_tl_access | 6.252m | 8.949ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 6.252m | 8.949ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_dai_lock | chip_sw_otp_ctrl_dai_lock | 1.464h | 27.328ms | 1 | 1 | 100.00 |
| V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 7.527m | 8.137ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_wake_ups | chip_sw_pwrmgr_random_sleep_all_wake_ups | 33.291m | 24.364ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_all_wake_ups | chip_sw_pwrmgr_normal_sleep_all_wake_ups | 6.198m | 7.111ms | 1 | 3 | 33.33 |
| V2 | chip_sw_pwrmgr_deep_sleep_por_reset | chip_sw_pwrmgr_deep_sleep_por_reset | 12.042m | 7.701ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_por_reset | chip_sw_pwrmgr_normal_sleep_por_reset | 11.958m | 6.954ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_wake_ups | chip_sw_pwrmgr_deep_sleep_all_wake_ups | 36.188m | 26.969ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 30.748m | 16.454ms | 3 | 3 | 100.00 |
| chip_sw_aon_timer_wdog_bite_reset | 14.542m | 8.517ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 24.394m | 13.437ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 10.655m | 5.154ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 7.527m | 8.137ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 10.635m | 5.091ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 53.532m | 31.270ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 8.313m | 5.510ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 8.678m | 4.610ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_reset_reqs | chip_sw_pwrmgr_random_sleep_all_reset_reqs | 49.222m | 23.399ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 26.409m | 8.396ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_all_reset_reqs | 28.347m | 12.509ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_b2b_sleep_reset_req | chip_sw_pwrmgr_b2b_sleep_reset_req | 44.567m | 26.660ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 5.896m | 3.164ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 15.587m | 6.374ms | 98 | 100 | 98.00 |
| V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 10.669m | 9.577ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 10.669m | 9.577ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_non_sys_reset_info | chip_sw_pwrmgr_all_reset_reqs | 28.347m | 12.509ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 49.222m | 23.399ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_wdog_reset | 10.655m | 5.154ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 10.042m | 5.868ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 8.091m | 5.102ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 12.632m | 7.492ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 7.657m | 3.444ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 33.102m | 13.967ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 4.852m | 3.423ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 15.587m | 6.374ms | 98 | 100 | 98.00 |
| V2 | chip_sw_rstmgr_alert_handler_reset_enables | chip_sw_alert_handler_lpg_reset_toggle | 30.211m | 7.744ms | 3 | 3 | 100.00 |
| V2 | chip_sw_plic_all_irqs | chip_plic_all_irqs_0 | 21.128m | 5.823ms | 3 | 3 | 100.00 |
| chip_plic_all_irqs_10 | 10.442m | 4.109ms | 3 | 3 | 100.00 | ||
| chip_plic_all_irqs_20 | 13.919m | 4.929ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 4.926m | 2.504ms | 3 | 3 | 100.00 |
| V2 | chip_sw_timer | chip_sw_rv_timer_irq | 5.567m | 3.510ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_flash_mode | rom_e2e_smoke | 1.132h | 14.862ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 17.993m | 8.623ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 10.918m | 4.731ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 7.116m | 3.679ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 4.835m | 3.036ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 12.060m | 5.056ms | 3 | 3 | 100.00 |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 13.381m | 5.783ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sleep_sram_ret_contents | chip_sw_sleep_sram_ret_contents_no_scramble | 15.612m | 7.834ms | 3 | 3 | 100.00 |
| chip_sw_sleep_sram_ret_contents_scramble | 15.414m | 8.597ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 13.976m | 7.091ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 15.587m | 6.374ms | 98 | 100 | 98.00 |
| chip_sw_data_integrity_escalation | 14.959m | 6.215ms | 6 | 6 | 100.00 | ||
| V2 | chip_sw_usbdev_mem | chip_sw_usbdev_mem | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_vbus | chip_sw_usbdev_vbus | 3.131m | 2.727ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pullup | chip_sw_usbdev_pullup | 5.037m | 2.891ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_aon_pullup | chip_sw_usbdev_aon_pullup | 6.715m | 3.265ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_sof | chip_sw_usbdev_sof | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_setup_rx | chip_sw_usbdev_setuprx | 9.107m | 4.094ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_config_host | chip_sw_usbdev_config_host | 32.301m | 8.037ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pincfg | chip_sw_usbdev_pincfg | 1.968h | 32.113ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_tx_rx | chip_sw_usbdev_dpi | 53.093m | 11.813ms | 1 | 1 | 100.00 |
| V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 6.111m | 3.692ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 10.089m | 4.948ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalation_nmi_reset | chip_sw_alert_handler_escalation_nmi_reset | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_escalation_methods | chip_sw_alert_handler_escalation_methods | 0 | 0 | -- | ||
| V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 15.587m | 6.374ms | 98 | 100 | 98.00 |
| V2 | chip_sw_alert_handler_irqs | chip_plic_all_irqs | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 7.627m | 3.127ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 33.102m | 13.967ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 8.344m | 4.858ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 9.200m | 4.280ms | 88 | 90 | 97.78 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 27.847m | 13.705ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 27.462m | 6.578ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 30.211m | 7.744ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_ok | chip_sw_alert_handler_ping_ok | 26.551m | 8.327ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 3.678h | 254.065ms | 1 | 3 | 33.33 |
| V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 46.786m | 23.023ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_mem_access | chip_jtag_mem_access | 28.513m | 13.561ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 8.091m | 5.102ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 11.534m | 4.881ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 9.996m | 3.985ms | 0 | 3 | 0.00 |
| V2 | chip_sw_rv_dm_jtag_tap_sel | chip_tap_straps_rma | 8.542m | 5.690ms | 5 | 5 | 100.00 |
| V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 12.076m | 14.507ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_jtag | chip_rv_dm_jtag | 0 | 0 | -- | ||
| V2 | chip_rv_dm_dtm | chip_rv_dm_dtm | 0 | 0 | -- | ||
| V2 | chip_rv_dm_control_status | chip_rv_dm_control_status | 0 | 0 | -- | ||
| V2 | TOTAL | 2611 | 2644 | 98.75 | |||
| V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 4.979m | 2.858ms | 3 | 3 | 100.00 |
| V2S | TOTAL | 3 | 3 | 100.00 | |||
| V3 | chip_sw_usb_suspend | chip_sw_usb_suspend | 0 | 0 | -- | ||
| V3 | chip_usb_wake_debug | chip_usb_wake_debug | 0 | 0 | -- | ||
| V3 | chip_sw_coremark | chip_sw_coremark | 0 | 1 | 0.00 | ||
| V3 | chip_sw_power_max_load | chip_sw_power_virus | 17.897m | 5.678ms | 0 | 3 | 0.00 |
| V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 47.476m | 14.217ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 45.544m | 13.275ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 40.824m | 13.838ms | 1 | 1 | 100.00 | ||
| V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 1.208h | 49.298ms | 0 | 1 | 0.00 |
| rom_e2e_jtag_inject_dev | 55.702m | 52.658ms | 0 | 1 | 0.00 | ||
| rom_e2e_jtag_inject_rma | 1.100h | 41.707ms | 0 | 1 | 0.00 | ||
| V3 | rom_bootstrap_rma | rom_bootstrap_rma | 0 | 0 | -- | ||
| V3 | rom_e2e_weak_straps | rom_e2e_weak_straps | 0 | 0 | -- | ||
| V3 | rom_e2e_self_hash | rom_e2e_self_hash | 0 | 0 | -- | ||
| V3 | manuf_cp_unlock_raw | manuf_cp_unlock_raw | 0 | 0 | -- | ||
| V3 | manuf_scrap | manuf_scrap | 0 | 0 | -- | ||
| V3 | manuf_cp_yield_test | manuf_cp_yield_test | 0 | 0 | -- | ||
| V3 | manuf_cp_ast_test_execution | manuf_cp_ast_test_execution | 0 | 0 | -- | ||
| V3 | manuf_cp_device_info_flash_wr | manuf_cp_device_info_flash_wr | 0 | 0 | -- | ||
| V3 | manuf_cp_test_lock | manuf_cp_test_lock | 0 | 0 | -- | ||
| V3 | manuf_ft_exit_token | manuf_ft_exit_token | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization_preop | manuf_ft_sku_individualization_preop | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization | manuf_ft_sku_individualization | 0 | 0 | -- | ||
| V3 | manuf_ft_provision_rma_token_and_personalization | manuf_ft_provision_rma_token_and_personalization | 0 | 0 | -- | ||
| V3 | manuf_ft_load_transport_image | manuf_ft_load_transport_image | 0 | 0 | -- | ||
| V3 | manuf_ft_load_certificates | manuf_ft_load_certificates | 0 | 0 | -- | ||
| V3 | manuf_ft_eom | manuf_ft_eom | 0 | 0 | -- | ||
| V3 | manuf_rma_entry | manuf_rma_entry | 0 | 0 | -- | ||
| V3 | manuf_sram_program_crc_functest | manuf_sram_program_crc_functest | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_normal | chip_sw_adc_ctrl_normal | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_oneshot | chip_sw_adc_ctrl_oneshot | 0 | 0 | -- | ||
| V3 | chip_sw_clkmgr_jitter_cycle_measurements | chip_sw_clkmgr_jitter_frequency | 8.875m | 3.759ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_boot_mode | chip_sw_edn_boot_mode | 11.866m | 2.922ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_auto_mode | chip_sw_edn_auto_mode | 23.969m | 5.876ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_sw_mode | chip_sw_edn_sw_mode | 44.294m | 10.186ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_kat | chip_sw_edn_kat | 13.167m | 3.137ms | 3 | 3 | 100.00 |
| V3 | chip_sw_entropy_src_bypass_mode_health_tests | chip_sw_entropy_src_bypass_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_fips_mode_health_tests | chip_sw_entropy_src_fips_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_validation | chip_sw_entropy_src_validation | 0 | 0 | -- | ||
| V3 | chip_sw_flash_memory_protection | chip_sw_flash_ctrl_mem_protection | 21.326m | 4.979ms | 3 | 3 | 100.00 |
| V3 | chip_sw_hmac_sha2_stress | chip_sw_hmac_sha2_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_stress | chip_sw_hmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_endianness | chip_sw_hmac_endianness | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_secure_wipe | chip_sw_hmac_secure_wipe | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_error_conditions | chip_sw_hmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_speed | chip_sw_i2c_speed | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_override | //sw/device/tests:i2c_host_override_test | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_clockstretching | chip_sw_i2c_clockstretching | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_nack | chip_sw_i2c_nack | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_repeatedstart | chip_sw_i2c_repeatedstart | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_sideload_kmac_error | chip_sw_keymgr_sideload_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_attestation | chip_sw_keymgr_derive_attestation | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_sealing | chip_sw_keymgr_derive_sealing | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_sha3_stress | chip_sw_kmac_sha3_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_shake_stress | chip_sw_kmac_shake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_cshake_stress | chip_sw_kmac_cshake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_stress | chip_sw_kmac_kmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_key_sideload | chip_sw_kmac_kmac_key_sideload | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_endianess | chip_sw_kmac_endianess | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_entropy_stress | chip_sw_kmac_entropy_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_error_conditions | chip_sw_kmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_kmac_error | chip_sw_lc_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_debug_access | chip_sw_lc_ctrl_debug_access | 0 | 0 | -- | ||
| V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 4.837m | 2.877ms | 3 | 3 | 100.00 |
| V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 7.267m | 4.810ms | 1 | 1 | 100.00 |
| V3 | otp_ctrl_calibration | otp_ctrl_calibration | 0 | 0 | -- | ||
| V3 | otp_ctrl_partition_access_locked | otp_ctrl_partition_access_locked | 0 | 0 | -- | ||
| V3 | otp_ctrl_check_timeout | otp_ctrl_check_timeout | 0 | 0 | -- | ||
| V3 | chip_sw_sensor_ctrl_deep_sleep_wake_up | chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up | 7.704m | 6.100ms | 3 | 3 | 100.00 |
| V3 | chip_sw_pwrmgr_usb_clk_disabled_when_active | chip_sw_pwrmgr_usb_clk_disabled_when_active | 10.290m | 4.302ms | 3 | 3 | 100.00 |
| V3 | chip_sw_all_resets | chip_sw_pwrmgr_all_reset_reqs | 28.347m | 12.509ms | 3 | 3 | 100.00 |
| V3 | chip_sw_rom_ctrl_kmac_error | chip_sw_rom_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_rom_ctrl_digests | chip_sw_rom_ctrl_digests | 0 | 0 | -- | ||
| V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 15.587m | 6.374ms | 98 | 100 | 98.00 |
| V3 | tick_configuration | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | counter_wrap | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | chip_sw_spi_device_pass_through_flash_model | //sw/device/tests:spi_passthru_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_device_output_when_disabled_or_sleeping | chip_sw_spi_device_output_when_disabled_or_sleeping | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_pass_through | //sw/device/tests:spi_passthru_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_configuration | chip_sw_spi_host_configuration | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_events | chip_sw_spi_host_events | 0 | 0 | -- | ||
| V3 | chip_sw_sram_memset | chip_sw_sram_memset | 0 | 0 | -- | ||
| V3 | chip_sw_sram_subword_access | chip_sw_sram_subword_access | 0 | 0 | -- | ||
| V3 | chip_sw_uart_parity | chip_sw_uart_parity | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_loopback | chip_sw_uart_line_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_system_loopback | chip_sw_uart_system_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_break | chip_sw_uart_line_break | 0 | 0 | -- | ||
| V3 | chip_sw_uart_watermarks | chip_sw_uart_tx_rx | 14.957m | 4.549ms | 5 | 5 | 100.00 |
| V3 | chip_sw_usbdev_stream | chip_sw_usbdev_stream | 1.275h | 18.692ms | 1 | 1 | 100.00 |
| V3 | chip_sw_usbdev_iso | chip_sw_usbdev_iso | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_mixed | chip_sw_usbdev_mixed | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_suspend_resume | chip_sw_usbdev_suspend_resume | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_reset | chip_sw_usbdev_aon_wake_reset | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_disconnect | chip_sw_usbdev_aon_wake_disconnect | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_toggle_restore | chip_sw_usbdev_toggle_restore | 0 | 0 | -- | ||
| V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 47.476m | 14.217ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 45.544m | 13.275ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 40.824m | 13.838ms | 1 | 1 | 100.00 | ||
| V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 14.005m | 5.631ms | 3 | 3 | 100.00 |
| V3 | TOTAL | 35 | 45 | 77.78 | |||
| Unmapped tests | chip_sival_flash_info_access | 5.324m | 3.074ms | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_rst_cnsty_escalation | 9.582m | 5.322ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_ecc_error_vendor_test | 5.238m | 3.227ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq | 57.950m | 16.977ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_rnd | 19.893m | 5.736ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_nmi_irq | 17.305m | 5.406ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_lowpower_cancel | 8.218m | 4.137ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_sleep_wake_5_bug | 11.918m | 6.484ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_address_translation | 6.255m | 2.810ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_lockstep_glitch | 4.193m | 2.547ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_ctrl_write_clear | 7.194m | 3.004ms | 3 | 3 | 100.00 | ||
| TOTAL | 2881 | 2945 | 97.83 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 11 | 11 | 11 | 100.00 |
| V1 | 18 | 18 | 16 | 88.89 |
| V2 | 285 | 270 | 256 | 89.82 |
| V2S | 1 | 1 | 1 | 100.00 |
| V3 | 90 | 21 | 15 | 16.67 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.06 | 95.60 | 94.23 | 95.49 | -- | 95.03 | 96.47 | 99.51 |
UVM_ERROR @ * us: (cip_base_vseq.sv:828) [chip_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
0.chip_csr_mem_rw_with_rand_reset.69521752597327624826042398140080757062111794247291104013326652293902512535614
Line 382, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 2259.800376 us: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2259.800376 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_csr_mem_rw_with_rand_reset.10263831007024834704676030431097897341498223883877430210893080179086655531141
Line 377, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 2379.677282 us: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2379.677282 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 13 failures:
Test chip_sw_uart_tx_rx_bootstrap has 3 failures.
0.chip_sw_uart_tx_rx_bootstrap.44470457608560558771037731424535256198285519573008639207887229451821500143503
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_bootstrap/latest/run.log
Job ID: smart:fa9c3566-fdc4-4709-8eba-7823ae64d4ca
1.chip_sw_uart_tx_rx_bootstrap.41734684217729792670229481105047397200703892177188127879851905353788262785535
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_bootstrap/latest/run.log
Job ID: smart:6f26a680-456c-4c81-b19e-be72afc25ec1
... and 1 more failures.
Test chip_sw_rv_timer_systick_test has 3 failures.
0.chip_sw_rv_timer_systick_test.113398156791332541665329125359200575174425900735229416320231385158890216029113
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
Job ID: smart:7fcf50aa-16b5-4bc5-8ccd-b197ad09743d
1.chip_sw_rv_timer_systick_test.17415440155527261160260796722878675212536664568789490325692910284249914897511
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
Job ID: smart:7df32ca6-2535-497a-8dbc-fbff942cdd13
... and 1 more failures.
Test chip_sw_alert_handler_reverse_ping_in_deep_sleep has 2 failures.
0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.79416323502268642718900105940213804552297948806918333959810697810742340728602
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log
Job ID: smart:441ebed3-ff3b-429e-8459-e92f03d31d02
1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.61204216095445175554655095507777012094666021836982270807887168028562528486672
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log
Job ID: smart:a5c72e88-2ac8-4510-ae11-ea2e332dc3b5
Test chip_sw_coremark has 1 failures.
0.chip_sw_coremark.110355008970973230807760929941293072628890313778712718329161110787847840331267
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
Job ID: smart:ae118da0-16db-438c-9244-9d35cb93dd39
Test chip_sw_csrng_edn_concurrency_reduced_freq has 1 failures.
0.chip_sw_csrng_edn_concurrency_reduced_freq.104981262102310140997188743556134247481412359475250921999094097241017946335126
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest/run.log
Job ID: smart:9de3e2de-d1a8-4847-842f-693a734164f2
... and 2 more tests.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c:101)] DIF-fail: dif_keymgr_advance_state(keymgr, params) returns * has 3 failures:
0.chip_sw_flash_ctrl_lc_rw_en.52841729988226231655297615375419523164117914155503369067722760263599001089924
Line 790, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_lc_rw_en/latest/run.log
UVM_ERROR @ 2363.969812 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c:101)] DIF-fail: dif_keymgr_advance_state(keymgr, params) returns 3
UVM_INFO @ 2363.969812 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_flash_ctrl_lc_rw_en.83693852538568100634036283313251437585648591813691846840781542813724661816303
Line 776, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_lc_rw_en/latest/run.log
UVM_ERROR @ 2508.196808 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c:101)] DIF-fail: dif_keymgr_advance_state(keymgr, params) returns 3
UVM_INFO @ 2508.196808 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat" has 3 failures:
0.chip_sw_sysrst_ctrl_outputs.91690973841786415431811350685465774005132677934399430818278329857172413307094
Line 831, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest/run.log
UVM_FATAL @ 10.140001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_sysrst_ctrl_outputs.68548248417304320296053834801109736714716732850007351245515347835629149192160
Line 792, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest/run.log
UVM_FATAL @ 10.160001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:
0.chip_sw_lc_ctrl_program_error.47734929860771258302296431821117804338393368236746672372072313333477145594046
Line 794, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log
UVM_ERROR @ 14825.990140 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
UVM_INFO @ 14825.990140 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_lc_ctrl_program_error.12612860959507026960959777413919328439407875321915244723284606139276606414605
Line 788, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log
UVM_ERROR @ 14428.579252 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
UVM_INFO @ 14428.579252 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep. has 3 failures:
0.chip_sw_rv_dm_access_after_wakeup.9125140701059067267933672051000293432325914024025457578504418577862642318754
Line 812, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log
UVM_FATAL @ 3887.506750 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
UVM_INFO @ 3887.506750 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_rv_dm_access_after_wakeup.6046920192376043030608130037896715460817760568320197983322698187999074518732
Line 769, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log
UVM_FATAL @ 3984.872949 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
UVM_INFO @ 3984.872949 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 3 failures:
Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.
0.rom_e2e_jtag_inject_test_unlocked0.25531251639300166771552762473633014816121649069210030405236109227452398776547
Line 926, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log
UVM_FATAL @ 49298.283725 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
UVM_INFO @ 49298.283725 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_e2e_jtag_inject_dev has 1 failures.
0.rom_e2e_jtag_inject_dev.86236636308014816404899101185888213072338730262704437973364108822661619632601
Line 781, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log
UVM_FATAL @ 52657.836650 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
UVM_INFO @ 52657.836650 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_e2e_jtag_inject_rma has 1 failures.
0.rom_e2e_jtag_inject_rma.87651571066010685081788161699854590736353020575170092200745826025259082246859
Line 794, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log
UVM_FATAL @ 41707.253754 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
UVM_INFO @ 41707.253754 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 3 failures:
0.rom_e2e_static_critical.76540247777778279639551301219318343102710692763202062269370460521122144315994
Line 908, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_static_critical/latest/run.log
UVM_ERROR @ 20021.906158 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 20000000 ns
UVM_INFO @ 20021.906158 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_e2e_static_critical.4245634073186235127448104381676737649223684053415970996695805284335232619268
Line 751, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_static_critical/latest/run.log
UVM_ERROR @ 20015.372379 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 20000000 ns
UVM_INFO @ 20015.372379 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 3 failures:
0.rom_raw_unlock.79842177189343828322473122247927701619095905522143634972973581944716362641635
Line 799, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest/run.log
UVM_ERROR @ 205526.445186 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns
UVM_INFO @ 205526.445186 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_raw_unlock.21902337725387207236640500737199177812531512130125245324639788180923951742184
Line 824, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_raw_unlock/latest/run.log
UVM_ERROR @ 206354.089153 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns
UVM_INFO @ 206354.089153 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits * and * set in filter status, got status * has 2 failures:
0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.38991927639601603512349544104574888783151338914791854852211114898500518114873
Line 879, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log
UVM_ERROR @ 6401.932028 us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits 5 and 8 set in filter status, got status 0x100
UVM_INFO @ 6401.932028 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.112560375407539542516801945976212320087666590218658201573247906318526949642724
Line 790, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log
UVM_ERROR @ 6247.508274 us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits 5 and 8 set in filter status, got status 0x100
UVM_INFO @ 6247.508274 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:178) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 2 failures:
0.chip_sw_power_virus.109011922531935673311470051745799593925626560165782997609100984628412607302103
Line 1018, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
UVM_ERROR @ 5611.295166 us: (chip_sw_power_virus_vseq.sv:178) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
UVM_INFO @ 5611.295166 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_power_virus.77018149137911400476891864424171188895686283626376398813084373039477346481780
Line 972, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
UVM_ERROR @ 5678.193891 us: (chip_sw_power_virus_vseq.sv:178) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
UVM_INFO @ 5678.193891 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 2 failures:
11.chip_sw_all_escalation_resets.33656051833557992510711763193211035357951930656706247938563441539162303523851
Line 777, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/11.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 2874.860200 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 2874.860200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
94.chip_sw_all_escalation_resets.29842758035202980181897898885214785372720016580956932492894176817583173819230
Line 779, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/94.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 3599.178340 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 3599.178340 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 2 failures:
17.chip_sw_alert_handler_lpg_sleep_mode_alerts.75248555666385021548713796457237732023047563718567990904592117472961505424144
Line 842, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
UVM_ERROR @ 4254.276002 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003720 MTVAL=40600800
UVM_INFO @ 4254.276002 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
49.chip_sw_alert_handler_lpg_sleep_mode_alerts.39016711721555481873868592528440831981462928630001642066445493844740074821075
Line 798, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
UVM_ERROR @ 4052.937184 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003720 MTVAL=40600800
UVM_INFO @ 4052.937184 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:554) [chip_sw_power_idle_load_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert rstmgr_aon_fatal_fault fired unexpectedly! has 1 failures:
2.chip_sw_power_idle_load.40326753829872626062541896155188040217937571527926133285726558347536373990204
Line 795, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_idle_load/latest/run.log
UVM_ERROR @ 4083.715549 us: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert rstmgr_aon_fatal_fault fired unexpectedly!
UVM_INFO @ 4083.715549 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job chip_earlgrey_asic-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
4.chip_csr_aliasing.94351159910422451127914431870775182020371421994125766285519479483015984013128
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/4.chip_csr_aliasing/latest/run.log
Job ID: smart:1c36709f-43b5-47f5-bcef-618556009a8d