CHIP Simulation Results

Wednesday June 26 2024 23:02:36 UTC

GitHub Revision: `be1c4a4f52`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 44766564427213563291105655232733134394512207819884794315335669279596867428010

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	4.033m	2.753ms	3	3	100.00
		chip_sw_example_rom	2.220m	2.383ms	3	3	100.00
		chip_sw_example_manufacturer	4.542m	2.736ms	3	3	100.00
		chip_sw_example_concurrency	4.470m	2.594ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset	7.625m	7.602ms	5	5	100.00
V1	csr_rw	chip_csr_rw	13.860m	6.542ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	1.505h	42.771ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	2.774h	71.063ms	3	5	60.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	2.167m	2.781ms	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	2.774h	71.063ms	3	5	60.00
		chip_csr_rw	13.860m	6.542ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	11.580s	267.655us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	9.175m	4.163ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	9.175m	4.163ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	9.175m	4.163ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	12.709m	3.816ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	12.709m	3.816ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	12.101m	4.638ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	12.551m	4.480ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	13.313m	3.884ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	41.449m	13.547ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	47.449m	13.217ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	28.866m	13.765ms	5	5	100.00
V1		TOTAL			198	220	90.00
V2	chip_pin_mux	chip_padctrl_attributes	5.341m	5.505ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	5.341m	5.505ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	7.071m	3.533ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	6.573m	3.000ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	5.654m	3.538ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	30.003m	20.306ms	4	5	80.00
		chip_tap_straps_testunlock0	29.396m	16.009ms	3	5	60.00
		chip_tap_straps_rma	22.882m	12.871ms	4	5	80.00
		chip_tap_straps_prod	26.947m	18.210ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	5.325m	2.663ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	27.785m	9.153ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	16.191m	6.418ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	16.191m	6.418ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	17.892m	7.070ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	36.598m	17.107ms	1	3	33.33
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	13.505m	3.915ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	23.037m	6.050ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.127h	18.874ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.951m	3.180ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	20.850m	6.413ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.454m	3.232ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	35.294m	12.102ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.047m	3.633ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.745m	5.352ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.500m	3.183ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	6.066m	2.836ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	18.430m	8.873ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	8.369m	5.765ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	5.522m	3.582ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	8.369m	5.765ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	3.252m	3.150ms	3	3	100.00
		chip_sw_aes_smoketest	4.768m	2.816ms	3	3	100.00
		chip_sw_aon_timer_smoketest	5.758m	2.677ms	3	3	100.00
		chip_sw_clkmgr_smoketest	4.356m	2.657ms	3	3	100.00
		chip_sw_csrng_smoketest	4.353m	2.678ms	3	3	100.00
		chip_sw_entropy_src_smoketest	8.241m	3.265ms	3	3	100.00
		chip_sw_gpio_smoketest	5.293m	2.802ms	3	3	100.00
		chip_sw_hmac_smoketest	6.059m	3.460ms	3	3	100.00
		chip_sw_kmac_smoketest	5.157m	3.196ms	3	3	100.00
		chip_sw_otbn_smoketest	20.884m	5.929ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	9.902m	6.966ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	9.524m	5.530ms	3	3	100.00
		chip_sw_rv_plic_smoketest	6.117m	2.891ms	3	3	100.00
		chip_sw_rv_timer_smoketest	5.162m	2.912ms	3	3	100.00
		chip_sw_rstmgr_smoketest	5.259m	3.064ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	4.632m	3.029ms	3	3	100.00
		chip_sw_uart_smoketest	5.414m	3.298ms	3	3	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	6.220m	2.922ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	11.698m	5.712ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	4.137h	78.943ms	3	3	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	1.124h	14.465ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	3.929h	205.152ms	0	3	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	13.454m	4.728ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	9.368m	10.393ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	2.977h	58.141ms	3	3	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.236h	65.428ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	8.585m	4.699ms	30	30	100.00
V2	tl_d_illegal_access	chip_tl_errors	8.585m	4.699ms	30	30	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	2.774h	71.063ms	3	5	60.00
		chip_same_csr_outstanding	1.238h	32.137ms	18	20	90.00
		chip_csr_hw_reset	7.625m	7.602ms	5	5	100.00
		chip_csr_rw	13.860m	6.542ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	2.774h	71.063ms	3	5	60.00
		chip_same_csr_outstanding	1.238h	32.137ms	18	20	90.00
		chip_csr_hw_reset	7.625m	7.602ms	5	5	100.00
		chip_csr_rw	13.860m	6.542ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.891m	2.437ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.460s	55.037us	100	100	100.00
		xbar_smoke_large_delays	2.092m	10.764ms	100	100	100.00
		xbar_smoke_slow_rsp	2.071m	6.667ms	100	100	100.00
		xbar_random_zero_delays	56.380s	566.882us	100	100	100.00
		xbar_random_large_delays	23.870m	117.541ms	100	100	100.00
		xbar_random_slow_rsp	21.822m	65.400ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.103m	1.369ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.101m	1.564ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.448m	2.467ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.101m	1.564ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.772m	3.858ms	100	100	100.00
		xbar_access_same_device_slow_rsp	59.199m	180.662ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.399m	2.692ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	12.727m	19.040ms	100	100	100.00
		xbar_stress_all_with_error	13.470m	23.099ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	19.693m	32.043ms	100	100	100.00
		xbar_stress_all_with_reset_error	18.505m	24.144ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	1.124h	14.465ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	15.409m	9.384ms	0	3	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	1.011h	14.997ms	0	3	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	51.127m	11.333ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	1.159h	16.054ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	1.062h	16.089ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	59.926m	15.412ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	1.146h	14.944ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	1.006h	11.248ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	1.071h	16.076ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	1.166h	15.879ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	1.147h	15.843ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	1.331h	14.786ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	1.355h	18.123ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	1.921h	24.567ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	1.995h	24.130ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	1.603h	24.041ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	1.505h	23.228ms	1	1	100.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	1.188h	17.452ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	1.649h	23.064ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	1.565h	23.076ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	1.684h	23.003ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	2.003h	21.915ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	46.403m	10.828ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	57.627m	14.112ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	50.003m	13.975ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	1.064h	14.338ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	1.034h	13.650ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	55.591m	10.506ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	57.621m	13.854ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	56.393m	14.551ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	56.393m	13.732ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	1.189h	13.582ms	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	57.626m	11.780ms	3	3	100.00
		rom_e2e_asm_init_dev	1.059h	16.257ms	3	3	100.00
		rom_e2e_asm_init_prod	1.127h	16.035ms	3	3	100.00
		rom_e2e_asm_init_prod_end	1.394h	15.458ms	3	3	100.00
		rom_e2e_asm_init_rma	1.115h	15.007ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	1.027h	15.744ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	1.190h	15.166ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	59.337m	15.097ms	3	3	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	1.270h	17.449ms	3	3	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	5.760m	3.040ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.951m	3.180ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.878m	3.034ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	5.144m	2.956ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	46.773m	11.539ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	9.783m	19.096ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	9.783m	19.096ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	8.519m	3.424ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	9.902m	6.966ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	8.519m	3.424ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	14.393m	8.182ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	14.393m	8.182ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	10.641m	7.477ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	10.578m	5.656ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	19.977m	5.863ms	3	3	100.00
		chip_sw_aes_idle	5.144m	2.956ms	3	3	100.00
		chip_sw_hmac_enc_idle	6.203m	3.575ms	3	3	100.00
		chip_sw_kmac_idle	4.671m	2.633ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	10.366m	4.647ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	12.257m	5.686ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	9.910m	5.346ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	10.237m	5.228ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	29.462m	10.765ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.963m	4.135ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.708m	4.781ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.611m	4.108ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.011m	5.154ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	13.173m	3.997ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.792m	5.250ms	3	3	100.00
		chip_sw_ast_clk_outputs	17.892m	7.070ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	17.565m	10.217ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.611m	4.108ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.011m	5.154ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	13.505m	3.915ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	23.037m	6.050ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.127h	18.874ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.951m	3.180ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	20.850m	6.413ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.454m	3.232ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	35.294m	12.102ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.047m	3.633ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.745m	5.352ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.500m	3.183ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.356m	3.072ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	12.597m	4.686ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	19.041m	7.151ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.300h	24.787ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	5.669m	3.207ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	5.883m	2.889ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	26.943m	8.605ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	5.656m	2.875ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	9.473m	4.913ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	37.020m	20.652ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	1.662h	37.885ms	2	3	66.67
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	17.892m	7.070ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	10.281m	4.589ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	9.995m	3.321ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	13.191m	5.783ms	99	100	99.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	33.896m	8.284ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	30.072m	7.546ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	9.636m	3.936ms	3	3	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	13.471m	7.005ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.258m	3.087ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	18.941m	7.415ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	34.934m	23.157ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	4.843m	2.982ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	6.719m	3.337ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	11.913m	5.128ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	34.934m	23.157ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	34.934m	23.157ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	1.003h	20.475ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	1.003h	20.475ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	8.600m	5.778ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	9.783m	19.096ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	2.409h	41.195ms	10	10	100.00
		chip_sw_entropy_src_ast_rng_req	3.374m	2.692ms	3	3	100.00
		chip_sw_edn_entropy_reqs	22.945m	5.381ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	3.374m	2.692ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	30.072m	7.546ms	3	3	100.00
V2	chip_sw_entropy_src_fuse_en_fw_read	chip_sw_entropy_src_fuse_en_fw_read_test			0	0	--
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	3.322m	2.293ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	38.804m	21.497ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	20.417m	5.021ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	23.037m	6.050ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	11.181m	4.057ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	13.505m	3.915ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.467h	43.249ms	3	3	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	38.804m	21.497ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	6.624m	3.731ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	40.104m	11.681ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	9.439m	5.669ms	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.467h	43.249ms	3	3	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	9.439m	5.669ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	9.439m	5.669ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	9.439m	5.669ms	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	9.439m	5.669ms	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	13.191m	5.783ms	99	100	99.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	7.571m	12.269ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	19.098m	6.343ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	13.232m	6.223ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	13.232m	6.223ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.643m	2.907ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.454m	3.232ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	6.203m	3.575ms	3	3	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	7.189m	4.051ms	3	3	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	35.732m	7.904ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	15.275m	4.860ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	16.977m	4.662ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	20.765m	5.627ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	12.300m	3.740ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	40.104m	11.681ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	35.294m	12.102ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	29.863m	10.933ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	46.773m	11.539ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.074h	12.459ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.871m	3.253ms	3	3	100.00
		chip_sw_kmac_mode_kmac	5.335m	2.677ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.047m	3.633ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	40.104m	11.681ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	19.991m	11.418ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	5.230m	2.534ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	4.842m	2.788ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.671m	2.633ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	10.638m	6.076ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	30.003m	20.306ms	4	5	80.00
		chip_tap_straps_rma	22.882m	12.871ms	4	5	80.00
		chip_tap_straps_prod	26.947m	18.210ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	4.439m	2.626ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	19.991m	11.418ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	19.991m	11.418ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	19.991m	11.418ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	39.275m	12.614ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	9.439m	5.669ms	3	3	100.00
		chip_sw_flash_rma_unlocked	1.467h	43.249ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	9.942m	4.082ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	21.332m	8.802ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	28.832m	7.364ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	22.720m	8.051ms	3	3	100.00
		chip_sw_lc_ctrl_transition	19.991m	11.418ms	15	15	100.00
		chip_sw_keymgr_key_derivation	40.104m	11.681ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	11.180m	8.366ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	14.075m	9.691ms	3	3	100.00
		chip_prim_tl_access	7.571m	12.269ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	17.565m	10.217ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.963m	4.135ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.708m	4.781ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.611m	4.108ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.011m	5.154ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	13.173m	3.997ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.792m	5.250ms	3	3	100.00
		chip_tap_straps_dev	30.003m	20.306ms	4	5	80.00
		chip_tap_straps_rma	22.882m	12.871ms	4	5	80.00
		chip_tap_straps_prod	26.947m	18.210ms	5	5	100.00
		chip_rv_dm_lc_disabled	11.366m	19.575ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.748m	3.305ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.804m	3.155ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.672m	2.466ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.441m	2.847ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	39.678m	26.328ms	3	3	100.00
		chip_rv_dm_lc_disabled	11.366m	19.575ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.613h	46.726ms	3	3	100.00
		chip_sw_lc_walkthrough_prod	1.768h	50.438ms	3	3	100.00
		chip_sw_lc_walkthrough_prodend	16.534m	9.319ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	1.588h	45.972ms	3	3	100.00
		chip_sw_lc_walkthrough_testunlocks	39.678m	26.328ms	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	2.216m	2.432ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.810m	1.893ms	3	3	100.00
		rom_volatile_raw_unlock	2.048m	2.853ms	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	19.991m	11.418ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	38.804m	21.497ms	3	3	100.00
		chip_sw_otbn_mem_scramble	9.120m	4.280ms	3	3	100.00
		chip_sw_keymgr_key_derivation	40.104m	11.681ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	13.282m	5.201ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.612m	2.890ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	38.804m	21.497ms	3	3	100.00
		chip_sw_otbn_mem_scramble	9.120m	4.280ms	3	3	100.00
		chip_sw_keymgr_key_derivation	40.104m	11.681ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	13.282m	5.201ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.612m	2.890ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	19.991m	11.418ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	10.586m	4.604ms	3	3	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	4.439m	2.626ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	9.942m	4.082ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	21.332m	8.802ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	28.832m	7.364ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	22.720m	8.051ms	3	3	100.00
		chip_sw_lc_ctrl_transition	19.991m	11.418ms	15	15	100.00
		chip_prim_tl_access	7.571m	12.269ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	7.571m	12.269ms	3	3	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	1.562h	26.961ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	8.431m	9.219ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	32.727m	23.365ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	7.897m	8.105ms	2	3	66.67
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	14.224m	8.980ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	12.351m	7.680ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	31.515m	24.211ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	27.278m	18.017ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	14.393m	8.182ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	26.688m	14.480ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	10.893m	4.816ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	8.431m	9.219ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	10.140m	5.488ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	59.382m	31.927ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	10.787m	7.339ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	7.827m	5.249ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	55.855m	26.052ms	2	3	66.67
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	18.941m	7.415ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	32.193m	10.014ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	47.121m	18.462ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	4.347m	3.071ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	13.191m	5.783ms	99	100	99.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	11.180m	8.366ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	11.180m	8.366ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	32.193m	10.014ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	55.855m	26.052ms	2	3	66.67
		chip_sw_pwrmgr_wdog_reset	10.893m	4.816ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	9.902m	6.966ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	7.753m	3.947ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	11.915m	6.529ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	9.140m	4.618ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	34.682m	12.723ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	6.539m	3.691ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	13.191m	5.783ms	99	100	99.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	30.691m	8.810ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	21.990m	6.232ms	3	3	100.00
		chip_plic_all_irqs_10	10.769m	4.320ms	3	3	100.00
		chip_plic_all_irqs_20	15.479m	4.888ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.982m	2.463ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.375m	3.462ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	1.124h	14.465ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	15.117m	8.083ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	12.199m	5.020ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	7.987m	3.254ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	4.888m	2.880ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	13.282m	5.201ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.745m	5.352ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	11.519m	9.060ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	15.530m	7.818ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	14.075m	9.691ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	13.191m	5.783ms	99	100	99.00
		chip_sw_data_integrity_escalation	16.191m	6.418ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	4.561m	3.422ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	5.505m	2.822ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	8.754m	3.839ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	11.778m	4.775ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	33.204m	7.700ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	2.205h	31.153ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	51.793m	12.545ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	6.783m	3.593ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	10.638m	6.076ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	13.191m	5.783ms	99	100	99.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	6.659m	3.539ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	34.682m	12.723ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	10.086m	5.388ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	9.965m	3.800ms	87	90	96.67
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	28.312m	13.812ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	33.896m	8.284ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	30.691m	8.810ms	3	3	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	24.284m	8.318ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.643h	254.643ms	3	3	100.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	22.872m	10.883ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	29.630m	13.587ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	7.753m	3.947ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	10.115m	5.420ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	10.293m	3.278ms	0	3	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	22.882m	12.871ms	4	5	80.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	11.366m	19.575ms	3	3	100.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			2602	2644	98.41
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.864m	3.473ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark			0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus			0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	19.897m	7.151ms	0	1	0.00
		rom_e2e_jtag_debug_dev	21.451m	8.121ms	0	1	0.00
		rom_e2e_jtag_debug_rma	20.698m	7.633ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	43.220m	31.939ms	1	1	100.00
		rom_e2e_jtag_inject_dev	52.959m	26.987ms	1	1	100.00
		rom_e2e_jtag_inject_rma	51.108m	23.855ms	1	1	100.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash			0	0	--
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.496m	3.842ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	10.710m	2.970ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	39.785m	8.579ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	27.701m	5.987ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	11.178m	3.829ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	21.052m	5.080ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	//sw/device/tests:i2c_host_override_test			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.910m	2.353ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	11.685m	5.524ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	11.282m	6.921ms	3	3	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	9.390m	4.685ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	32.193m	10.014ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	13.191m	5.783ms	99	100	99.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	//sw/device/tests:spi_passthru_test			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	//sw/device/tests:spi_passthru_test			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	12.709m	3.816ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.233h	19.432ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	19.897m	7.151ms	0	1	0.00
		rom_e2e_jtag_debug_dev	21.451m	8.121ms	0	1	0.00
		rom_e2e_jtag_debug_rma	20.698m	7.633ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	11.016m	4.908ms	3	3	100.00
V3		TOTAL			35	45	77.78
	Unmapped tests	chip_sival_flash_info_access	6.190m	3.087ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	14.063m	5.404ms	3	3	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	5.227m	2.667ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	1.257h	16.946ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	20.604m	5.910ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	15.891m	5.143ms	3	3	100.00
		chip_sw_pwrmgr_lowpower_cancel	8.480m	4.775ms	2	3	66.67
		chip_sw_pwrmgr_sleep_wake_5_bug	8.458m	6.420ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	6.395m	2.890ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	3.706m	3.167ms	3	3	100.00
		chip_sw_flash_ctrl_write_clear	7.018m	3.460ms	3	3	100.00
		TOTAL			2870	2945	97.45

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	11	11	10	90.91
V1	18	18	16	88.89
V2	285	270	241	84.56
V2S	1	1	1	100.00
V3	90	21	15	16.67

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.01	95.46	93.71	95.36	--	94.43	97.53	99.57

Failure Buckets

UVM_ERROR @ * us: (cip_base_vseq.sv:828) [chip_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test chip_csr_mem_rw_with_rand_reset has 20 failures.
  - 0.chip_csr_mem_rw_with_rand_reset.31489906762237943554957528667727132262613862961871451772327313492418891906711
    Line 370, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1858.166820 us: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1858.166820 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_csr_mem_rw_with_rand_reset.42786740461712070424023077742229221284492962191365176508636213669727453044217
    Line 386, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2781.100700 us: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2781.100700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:35) [chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:*-*-* has 15 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.53168383151784603375217695618631872798839305069264978280845731960629103242241
    Line 1060, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_ERROR @ 17452.118833 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  BFV:" == "BFV:07535603
  LCV:02108421
  "
  UVM_INFO @ 17452.118833 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.72604425937935507714806140653793865559238327782133167612893836470078365148230
    Line 1146, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_ERROR @ 23064.107621 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  BFV:" == "BFV:07535603
  LCV:21084210
  "
  UVM_INFO @ 23064.107621 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_prod.93484794165906937446750635497502299635642797956587286270879420321366709301899
    Line 1078, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest/run.log
```
  UVM_ERROR @ 23076.285015 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  BFV:" == "BFV:07535603
  LCV:2318c631
  "
  UVM_INFO @ 23076.285015 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.33413788612538164647122876139853252072224307375750804164214127234298741342334
    Line 1153, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest/run.log
```
  UVM_ERROR @ 23002.546815 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  BFV:" == "BFV:07535603
  LCV:25294a52
  "
  UVM_INFO @ 23002.546815 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_rma.57738538278335725950628265229727468365588537569701562633791029087109164856275
    Line 1105, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest/run.log
```
  UVM_ERROR @ 21915.164277 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  BFV:" == "BFV:07535603
  LCV:2739ce73
  "
  UVM_INFO @ 21915.164277 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- ... and 10 more tests.
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 11 failures:
- Test chip_sw_rv_timer_systick_test has 3 failures.
  - 0.chip_sw_rv_timer_systick_test.98465548393315679306261012755830611695575603920454346964070700960108722198416
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:f43be55b-a929-4314-9878-583ec964f1d6
```
  - 1.chip_sw_rv_timer_systick_test.3942797233183722491614030723252909206691334287165632292981332828946524483734
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:b047a203-01b3-4155-b887-3aa3dec0a818
```
  - ... and 1 more failures.
- Test chip_sw_coremark has 1 failures.
  - 0.chip_sw_coremark.7434118712262112264728916987609062343305268953105376107132277338756742768783
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
```
  Job ID: smart:f76672d1-7b0a-4654-94ac-e637ef922c74
```
- Test chip_sw_csrng_edn_concurrency_reduced_freq has 1 failures.
  - 0.chip_sw_csrng_edn_concurrency_reduced_freq.1879371803352290594922532274644470339327922916338043239333173296608375188327
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest/run.log
```
  Job ID: smart:70ff375a-1fe3-4a38-a2c2-5169465692a9
```
- Test chip_sw_ast_clk_rst_inputs has 2 failures.
  - 0.chip_sw_ast_clk_rst_inputs.111722686358889816234631877714593753884421560777720361844400622775505520937224
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:4f4e77e5-e1b3-4f67-941a-251898e59e94
```
  - 2.chip_sw_ast_clk_rst_inputs.24935066203954191721384857078014518181645367913219894751354811262437991984928
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:166f5202-abb7-4106-8c1e-e18a207979d0
```
- Test chip_sw_power_virus has 3 failures.
  - 0.chip_sw_power_virus.55808412392129993234505072042976735338938380526396669170495262031450826169838
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:756970d6-7bd4-43a3-ae31-94dc313cf350
```
  - 1.chip_sw_power_virus.104588919054318315788795054596321948295265713003706591595093277461669653942350
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:06f719e5-10cf-4a20-a179-9e13744a31a7
```
  - ... and 1 more failures.
- ... and 1 more tests.
UVM_FATAL @ * us: (jtag_driver.sv:124) [driver] wait timeout occurred! has 4 failures:
- Test chip_tap_straps_testunlock0 has 2 failures.
  - 0.chip_tap_straps_testunlock0.68641435262944844680831621320664806785819984246881522733729176878049104337597
    Line 5978, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_tap_straps_testunlock0/latest/run.log
```
  UVM_FATAL @ 16009.401160 us: (jtag_driver.sv:124) [uvm_test_top.env.m_jtag_riscv_agent.m_jtag_agent.driver] wait timeout occurred!
  UVM_INFO @ 16009.401160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.chip_tap_straps_testunlock0.51067916404880684421704198057406317577788558699165372393649702477191520651395
    Line 5930, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_tap_straps_testunlock0/latest/run.log
```
  UVM_FATAL @ 12883.332055 us: (jtag_driver.sv:124) [uvm_test_top.env.m_jtag_riscv_agent.m_jtag_agent.driver] wait timeout occurred!
  UVM_INFO @ 12883.332055 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_tap_straps_dev has 1 failures.
  - 2.chip_tap_straps_dev.55326963207241866610912415588182670553090961635584599040032080637298218247453
    Line 6054, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_tap_straps_dev/latest/run.log
```
  UVM_FATAL @ 20306.284530 us: (jtag_driver.sv:124) [uvm_test_top.env.m_jtag_riscv_agent.m_jtag_agent.driver] wait timeout occurred!
  UVM_INFO @ 20306.284530 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_tap_straps_rma has 1 failures.
  - 2.chip_tap_straps_rma.101912634744142189121103345262573704886954025356124721901504175762811232634927
    Line 5947, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_tap_straps_rma/latest/run.log
```
  UVM_FATAL @ 12870.856539 us: (jtag_driver.sv:124) [uvm_test_top.env.m_jtag_riscv_agent.m_jtag_agent.driver] wait timeout occurred!
  UVM_INFO @ 12870.856539 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep. has 3 failures:
- Test chip_sw_rv_dm_access_after_wakeup has 3 failures.
  - 0.chip_sw_rv_dm_access_after_wakeup.90394588001642880602507039636948519967307073052683864361908620051747048328752
    Line 783, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3876.437621 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3876.437621 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_rv_dm_access_after_wakeup.6980693761572357529934423765074030055874253070601780559317726538465529213123
    Line 756, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3991.316594 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3991.316594 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:35) [chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:*-*-* has 3 failures:
- Test rom_e2e_shutdown_exception_c has 3 failures.
  - 0.rom_e2e_shutdown_exception_c.74399252519718054974646175927663133628235664144943340111386543490090118910587
    Line 1012, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_exception_c/latest/run.log
```
  UVM_ERROR @ 14501.627817 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:4001-0002-01
  BFV:" == "BFV:01495202
  LCV:2739ce73
  "
  UVM_INFO @ 14501.627817 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
  - 1.rom_e2e_shutdown_exception_c.87631346635107435263379872272260249896183301711524728553863238884306376280880
    Line 964, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_exception_c/latest/run.log
```
  UVM_ERROR @ 14840.779779 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:4001-0002-01
  BFV:" == "BFV:01495202
  LCV:2739ce73
  "
  UVM_INFO @ 14840.779779 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:35) [chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:*-*-* has 3 failures:
- Test rom_e2e_shutdown_output has 3 failures.
  - 0.rom_e2e_shutdown_output.61794266508417903583456709598860711748837166738481771441476212043818665322111
    Line 1044, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log
```
  UVM_ERROR @ 9383.584989 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:4001-0002-01
  BFV:" == "BFV:0142500d
  LCV:02108421
  "
  UVM_INFO @ 9383.584989 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
  - 1.rom_e2e_shutdown_output.21417864274770382842064715574355951821858212611272839357682285726486784205541
    Line 962, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_output/latest/run.log
```
  UVM_ERROR @ 7293.855233 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:4001-0002-01
  BFV:" == "BFV:0142500d
  LCV:02108421
  "
  UVM_INFO @ 7293.855233 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat" has 3 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.88090637609622223222190445512085984131211947309159974557851675847063652688935
    Line 811, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 7151.345500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat"
  UVM_INFO @ 7151.345500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.49571275217332091979660843085530033498979985403123235779008597029162402109941
    Line 823, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 8121.366500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat"
  UVM_INFO @ 8121.366500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.114792956031497067795521908758640045600861422403871542399982171034718722600537
    Line 817, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 7633.272500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat"
  UVM_INFO @ 7633.272500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 3 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 3 failures.
  - 21.chip_sw_alert_handler_lpg_sleep_mode_alerts.14865554621998145110166958388073892743107463507842478768454556081396257626794
    Line 805, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3642.294996 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003720 MTVAL=40600800
  UVM_INFO @ 3642.294996 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.chip_sw_alert_handler_lpg_sleep_mode_alerts.24059442471683455559216961177800271578459108996220571698767498754533748093713
    Line 848, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3175.511040 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003720 MTVAL=40600800
  UVM_INFO @ 3175.511040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 2 failures:

Test rom_raw_unlock has 2 failures.

1.rom_raw_unlock.65787818183663473121244545390525045477553796921633175877237798879835531527920
Line 761, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_raw_unlock/latest/run.log

  UVM_ERROR @ 205152.120229 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns
  
  UVM_INFO @ 205152.120229 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.rom_raw_unlock.61479150407490855238745321192775343453732254531908804507004735534479752553670
Line 793, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.rom_raw_unlock/latest/run.log

  UVM_ERROR @ 205204.644810 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns
  
  UVM_INFO @ 205204.644810 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job chip_earlgrey_asic-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test chip_csr_aliasing has 2 failures.
  - 2.chip_csr_aliasing.9867290500084778703424899654721608618279439895205758152917091742277236963813
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_csr_aliasing/latest/run.log
```
  Job ID: smart:257fb36f-06e4-4059-a031-a61229bee3d8
```
  - 3.chip_csr_aliasing.51524794932991504015126521784928359610583038191645409016876374558430962031510
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/3.chip_csr_aliasing/latest/run.log
```
  Job ID: smart:94cfdcc6-55f5-4d33-8776-eeda2e8abdd4
```
UVM_ERROR @ * us: (cip_base_vseq.sv:250) [chip_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 2 failures:
- Test chip_same_csr_outstanding has 2 failures.
  - 6.chip_same_csr_outstanding.41338217162150910394367121558393237949961810998898030240298918019103129074868
    Line 3214, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/6.chip_same_csr_outstanding/latest/run.log
```
  UVM_ERROR @ 17450.082926 us: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed masked_data == exp_data (8 [0x8] vs 0 [0x0]) addr 0x40080078 read out mismatch
  UVM_INFO @ 17450.082926 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.chip_same_csr_outstanding.11595694086053417923293428225650019029559522048562489206234060383316783304451
    Line 4003, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/19.chip_same_csr_outstanding/latest/run.log
```
  UVM_ERROR @ 24083.055892 us: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed masked_data == exp_data (8 [0x8] vs 0 [0x0]) addr 0x40080078 read out mismatch
  UVM_INFO @ 24083.055892 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:84)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status() has 1 failures:
- Test chip_sw_pwrmgr_lowpower_cancel has 1 failures.
  - 1.chip_sw_pwrmgr_lowpower_cancel.17849827327841732844698384817852500677568328715146154758067518102917578778504
    Line 772, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_lowpower_cancel/latest/run.log
```
  UVM_ERROR @ 4367.947900 us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:84)] CHECK-fail: Timed out after 100 usec (10000 CPU cycles) waiting for !get_wakeup_status()
  UVM_INFO @ 4367.947900 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(pend_req[h2d.a_source].pend == *)' has 1 failures:
- Test chip_sw_pwrmgr_random_sleep_all_reset_reqs has 1 failures.
  - 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.103727763475935577242646529202152658422378311516120600806358428767028772400262
    Line 851, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log
```
      Offending '(pend_req[h2d.a_source].pend == 0)'
  UVM_ERROR @ 17777.530106 us: (tlul_assert.sv:268) [ASSERT FAILED] pendingReqPerSrc_M
  UVM_INFO @ 17777.530106 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits * and * set in filter status, got status * has 1 failures:
- Test chip_sw_pwrmgr_normal_sleep_all_wake_ups has 1 failures.
  - 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.42250682577568890046785609453486175492669153958893372194050175575177651918580
    Line 867, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log
```
  UVM_ERROR @ 6707.641028 us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits 5 and 8 set in filter status, got status 0x100
  UVM_INFO @ 6707.641028 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 1 failures:
- Test chip_sw_all_escalation_resets has 1 failures.
  - 87.chip_sw_all_escalation_resets.20718886191525087186969180936621465986466343472627359664671727561768613203351
    Line 766, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/87.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3446.442174 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 3446.442174 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```