CHIP Simulation Results

Thursday June 27 2024 23:02:31 UTC

GitHub Revision: `8db2a18db1`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 100513533386727882033709335126269317053614297947080434367729937568368619502352

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	5.073m	2.517ms	3	3	100.00
		chip_sw_example_rom	2.349m	2.850ms	3	3	100.00
		chip_sw_example_manufacturer	5.021m	3.569ms	3	3	100.00
		chip_sw_example_concurrency	5.680m	3.056ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset	7.394m	6.055ms	5	5	100.00
V1	csr_rw	chip_csr_rw	11.647m	6.262ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	2.758h	96.734ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	2.793h	64.585ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	2.260m	2.623ms	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	2.793h	64.585ms	5	5	100.00
		chip_csr_rw	11.647m	6.262ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	11.450s	267.990us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	9.086m	3.651ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	9.086m	3.651ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	9.086m	3.651ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	13.123m	4.755ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	13.123m	4.755ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	13.409m	4.185ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	13.157m	4.164ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	13.546m	4.157ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	43.593m	13.183ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	47.252m	13.577ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	34.177m	13.233ms	5	5	100.00
V1		TOTAL			200	220	90.91
V2	chip_pin_mux	chip_padctrl_attributes	6.423m	5.804ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	6.423m	5.804ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	6.532m	2.769ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	9.369m	7.154ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	6.820m	4.117ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	25.617m	13.884ms	5	5	100.00
		chip_tap_straps_testunlock0	24.791m	12.809ms	3	5	60.00
		chip_tap_straps_rma	25.570m	17.113ms	4	5	80.00
		chip_tap_straps_prod	31.367m	17.674ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	5.061m	2.573ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	24.210m	8.341ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	14.750m	5.618ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	14.750m	5.618ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	19.732m	7.918ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	41.554m	19.313ms	1	3	33.33
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	12.384m	4.021ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	18.692m	5.865ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.101h	18.119ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.413m	2.758ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	24.206m	7.507ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.987m	3.133ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	28.963m	8.939ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.650m	3.181ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.867m	4.984ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.537m	3.121ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	5.546m	3.104ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	18.489m	7.586ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	9.221m	5.260ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	3.794m	2.908ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	9.221m	5.260ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	5.653m	2.800ms	3	3	100.00
		chip_sw_aes_smoketest	4.205m	3.327ms	3	3	100.00
		chip_sw_aon_timer_smoketest	6.351m	3.029ms	3	3	100.00
		chip_sw_clkmgr_smoketest	4.329m	2.646ms	3	3	100.00
		chip_sw_csrng_smoketest	5.543m	2.478ms	3	3	100.00
		chip_sw_entropy_src_smoketest	9.554m	3.695ms	3	3	100.00
		chip_sw_gpio_smoketest	4.925m	3.262ms	3	3	100.00
		chip_sw_hmac_smoketest	6.542m	2.971ms	3	3	100.00
		chip_sw_kmac_smoketest	7.732m	3.378ms	3	3	100.00
		chip_sw_otbn_smoketest	36.741m	11.147ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	8.941m	6.575ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	6.406m	6.120ms	3	3	100.00
		chip_sw_rv_plic_smoketest	4.675m	3.391ms	3	3	100.00
		chip_sw_rv_timer_smoketest	4.287m	2.849ms	3	3	100.00
		chip_sw_rstmgr_smoketest	4.769m	3.310ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	4.040m	2.891ms	3	3	100.00
		chip_sw_uart_smoketest	5.790m	3.292ms	3	3	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	5.004m	3.185ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	11.065m	5.475ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	4.732h	77.557ms	3	3	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	1.226h	14.748ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	5.569h	204.114ms	0	3	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	13.749m	3.650ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	8.100m	4.177ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	3.081h	59.200ms	3	3	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.619h	64.495ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	8.435m	4.782ms	30	30	100.00
V2	tl_d_illegal_access	chip_tl_errors	8.435m	4.782ms	30	30	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	2.793h	64.585ms	5	5	100.00
		chip_same_csr_outstanding	1.302h	29.447ms	20	20	100.00
		chip_csr_hw_reset	7.394m	6.055ms	5	5	100.00
		chip_csr_rw	11.647m	6.262ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	2.793h	64.585ms	5	5	100.00
		chip_same_csr_outstanding	1.302h	29.447ms	20	20	100.00
		chip_csr_hw_reset	7.394m	6.055ms	5	5	100.00
		chip_csr_rw	11.647m	6.262ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.682m	2.528ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.510s	56.839us	100	100	100.00
		xbar_smoke_large_delays	1.864m	10.498ms	100	100	100.00
		xbar_smoke_slow_rsp	1.972m	6.992ms	100	100	100.00
		xbar_random_zero_delays	53.700s	581.529us	100	100	100.00
		xbar_random_large_delays	20.438m	114.033ms	100	100	100.00
		xbar_random_slow_rsp	22.278m	75.347ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.157m	1.554ms	100	100	100.00
		xbar_error_and_unmapped_addr	53.340s	1.259ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.723m	2.659ms	100	100	100.00
		xbar_error_and_unmapped_addr	53.340s	1.259ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.827m	4.039ms	100	100	100.00
		xbar_access_same_device_slow_rsp	53.586m	167.375ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.397m	2.759ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	11.231m	17.524ms	100	100	100.00
		xbar_stress_all_with_error	10.848m	18.550ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	17.217m	22.914ms	100	100	100.00
		xbar_stress_all_with_reset_error	15.522m	8.916ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	1.226h	14.748ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	13.703m	6.604ms	0	3	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	1.049h	14.557ms	0	3	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	57.226m	11.225ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	1.051h	15.283ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	1.216h	15.515ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	1.342h	15.860ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	1.177h	15.152ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	46.172m	11.042ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	1.147h	15.419ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	1.226h	14.988ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	57.336m	15.437ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	1.104h	15.048ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	1.306h	17.918ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	1.772h	24.182ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	1.641h	24.435ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	1.697h	23.968ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	1.814h	23.492ms	1	1	100.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	1.301h	17.832ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	1.564h	22.731ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	1.580h	22.504ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	1.865h	22.815ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	1.377h	21.947ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	50.355m	10.517ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	1.143h	13.796ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	1.307h	14.695ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	1.262h	14.555ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	57.850m	13.584ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	54.373m	10.325ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	1.028h	13.989ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	1.076h	13.910ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	52.666m	13.660ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	51.667m	13.453ms	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	53.759m	10.818ms	3	3	100.00
		rom_e2e_asm_init_dev	1.211h	14.926ms	3	3	100.00
		rom_e2e_asm_init_prod	1.121h	15.193ms	3	3	100.00
		rom_e2e_asm_init_prod_end	1.201h	15.496ms	3	3	100.00
		rom_e2e_asm_init_rma	1.088h	14.133ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	1.115h	15.504ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	1.164h	15.866ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	1.132h	14.311ms	3	3	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	1.493h	16.790ms	3	3	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	5.700m	3.417ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.413m	2.758ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.387m	2.682ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.067m	2.161ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	41.357m	10.149ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.840m	18.940ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.840m	18.940ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	7.048m	4.735ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	8.941m	6.575ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	7.048m	4.735ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	15.642m	8.805ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	15.642m	8.805ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	11.493m	8.223ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	12.174m	5.567ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	18.387m	6.044ms	3	3	100.00
		chip_sw_aes_idle	4.067m	2.161ms	3	3	100.00
		chip_sw_hmac_enc_idle	5.899m	2.804ms	3	3	100.00
		chip_sw_kmac_idle	4.842m	2.860ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	9.140m	5.527ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	8.928m	4.307ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	10.801m	5.916ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	10.019m	5.472ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	25.905m	12.454ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.276m	4.199ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.830m	4.449ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.369m	3.512ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.143m	5.119ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.548m	3.956ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.358m	5.190ms	3	3	100.00
		chip_sw_ast_clk_outputs	19.732m	7.918ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	14.419m	12.256ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.369m	3.512ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.143m	5.119ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	12.384m	4.021ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	18.692m	5.865ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.101h	18.119ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.413m	2.758ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	24.206m	7.507ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.987m	3.133ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	28.963m	8.939ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.650m	3.181ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.867m	4.984ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.537m	3.121ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.207m	2.984ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	14.253m	5.185ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	19.580m	7.535ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.066h	24.658ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	4.737m	3.135ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	5.071m	3.515ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	37.335m	13.680ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	6.475m	3.983ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	11.853m	5.407ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	44.613m	24.033ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	47.390m	16.178ms	1	3	33.33
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	19.732m	7.918ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	10.560m	3.975ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	8.271m	3.509ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	15.134m	5.067ms	99	100	99.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	28.969m	7.281ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	26.523m	6.710ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	8.015m	4.250ms	3	3	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	14.041m	7.782ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	5.801m	2.643ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	22.340m	8.635ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	37.106m	22.079ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	6.121m	3.289ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	7.020m	3.929ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	11.026m	4.781ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	37.106m	22.079ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	37.106m	22.079ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	54.162m	20.401ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	54.162m	20.401ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	9.657m	6.857ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.840m	18.940ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	2.120h	24.396ms	10	10	100.00
		chip_sw_entropy_src_ast_rng_req	4.791m	3.168ms	3	3	100.00
		chip_sw_edn_entropy_reqs	18.717m	6.097ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	4.791m	3.168ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	26.523m	6.710ms	3	3	100.00
V2	chip_sw_entropy_src_fuse_en_fw_read	chip_sw_entropy_src_fuse_en_fw_read_test			0	0	--
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	5.540m	2.657ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	36.270m	18.403ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	21.421m	6.269ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	18.692m	5.865ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	11.818m	3.702ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	12.384m	4.021ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.449h	43.830ms	3	3	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	36.270m	18.403ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	6.890m	2.936ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	44.838m	12.011ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	7.372m	4.049ms	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.449h	43.830ms	3	3	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	7.372m	4.049ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	7.372m	4.049ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	7.372m	4.049ms	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	7.372m	4.049ms	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	15.134m	5.067ms	99	100	99.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	6.707m	8.711ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	22.601m	6.151ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	12.138m	4.588ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	12.138m	4.588ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.739m	2.906ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.987m	3.133ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.899m	2.804ms	3	3	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	6.229m	2.511ms	3	3	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	36.363m	7.525ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	17.454m	4.942ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	16.031m	5.789ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	18.389m	5.212ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	11.303m	3.850ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	44.838m	12.011ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	28.963m	8.939ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	42.579m	12.831ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	41.357m	10.149ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.062h	14.724ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.782m	2.527ms	3	3	100.00
		chip_sw_kmac_mode_kmac	6.386m	3.387ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.650m	3.181ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	44.838m	12.011ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	19.473m	12.236ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	5.194m	3.065ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	4.651m	2.626ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.842m	2.860ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	8.816m	5.671ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	25.617m	13.884ms	5	5	100.00
		chip_tap_straps_rma	25.570m	17.113ms	4	5	80.00
		chip_tap_straps_prod	31.367m	17.674ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	6.643m	3.089ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	19.473m	12.236ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	19.473m	12.236ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	19.473m	12.236ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	43.569m	13.461ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	7.372m	4.049ms	3	3	100.00
		chip_sw_flash_rma_unlocked	1.449h	43.830ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.512m	4.618ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	25.291m	9.527ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	25.544m	8.470ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	24.929m	8.947ms	3	3	100.00
		chip_sw_lc_ctrl_transition	19.473m	12.236ms	15	15	100.00
		chip_sw_keymgr_key_derivation	44.838m	12.011ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	11.908m	9.211ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	16.995m	9.905ms	3	3	100.00
		chip_prim_tl_access	6.707m	8.711ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	14.419m	12.256ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.276m	4.199ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.830m	4.449ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.369m	3.512ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.143m	5.119ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.548m	3.956ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.358m	5.190ms	3	3	100.00
		chip_tap_straps_dev	25.617m	13.884ms	5	5	100.00
		chip_tap_straps_rma	25.570m	17.113ms	4	5	80.00
		chip_tap_straps_prod	31.367m	17.674ms	5	5	100.00
		chip_rv_dm_lc_disabled	11.941m	18.226ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.323m	2.779ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.282m	3.265ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.932m	3.792ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.614m	3.235ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	40.298m	31.995ms	3	3	100.00
		chip_rv_dm_lc_disabled	11.941m	18.226ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.735h	49.187ms	3	3	100.00
		chip_sw_lc_walkthrough_prod	1.593h	48.676ms	3	3	100.00
		chip_sw_lc_walkthrough_prodend	21.264m	10.487ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	1.664h	49.405ms	3	3	100.00
		chip_sw_lc_walkthrough_testunlocks	40.298m	31.995ms	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.869m	2.546ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	2.274m	2.987ms	3	3	100.00
		rom_volatile_raw_unlock	2.019m	2.399ms	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	19.473m	12.236ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	36.270m	18.403ms	3	3	100.00
		chip_sw_otbn_mem_scramble	10.357m	4.086ms	3	3	100.00
		chip_sw_keymgr_key_derivation	44.838m	12.011ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	13.088m	4.607ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.822m	3.265ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	36.270m	18.403ms	3	3	100.00
		chip_sw_otbn_mem_scramble	10.357m	4.086ms	3	3	100.00
		chip_sw_keymgr_key_derivation	44.838m	12.011ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	13.088m	4.607ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.822m	3.265ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	19.473m	12.236ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	11.354m	5.693ms	3	3	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	6.643m	3.089ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.512m	4.618ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	25.291m	9.527ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	25.544m	8.470ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	24.929m	8.947ms	3	3	100.00
		chip_sw_lc_ctrl_transition	19.473m	12.236ms	15	15	100.00
		chip_prim_tl_access	6.707m	8.711ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	6.707m	8.711ms	3	3	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	1.570h	27.419ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	9.314m	7.277ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	31.691m	22.826ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	9.214m	7.664ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	11.775m	9.661ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	14.276m	6.054ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	32.005m	24.438ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	29.665m	17.307ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	15.642m	8.805ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	25.096m	9.975ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	14.077m	6.204ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	9.314m	7.277ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	7.776m	4.300ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	1.122h	40.538ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	8.735m	6.262ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	6.477m	4.097ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	44.581m	22.255ms	3	3	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	22.340m	8.635ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	33.039m	12.426ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	41.641m	31.262ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	4.708m	3.087ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	15.134m	5.067ms	99	100	99.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	11.908m	9.211ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	11.908m	9.211ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	33.039m	12.426ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	44.581m	22.255ms	3	3	100.00
		chip_sw_pwrmgr_wdog_reset	14.077m	6.204ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	8.941m	6.575ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	7.004m	4.582ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	14.860m	7.359ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	8.309m	5.712ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	33.941m	12.060ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	5.174m	2.774ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	15.134m	5.067ms	99	100	99.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	35.450m	8.633ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	23.892m	5.889ms	3	3	100.00
		chip_plic_all_irqs_10	10.927m	4.379ms	3	3	100.00
		chip_plic_all_irqs_20	13.315m	4.899ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	5.049m	2.885ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	3.815m	3.304ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	1.226h	14.748ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	13.544m	7.435ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	8.801m	4.382ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	6.856m	3.424ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	5.898m	3.193ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	13.088m	4.607ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.867m	4.984ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	12.849m	8.215ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	14.774m	7.418ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	16.995m	9.905ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	15.134m	5.067ms	99	100	99.00
		chip_sw_data_integrity_escalation	14.750m	5.618ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	4.463m	2.543ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	6.287m	3.303ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	9.850m	3.118ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	10.188m	3.393ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	24.169m	7.855ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.873h	31.725ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	49.997m	11.865ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	6.079m	3.456ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	8.816m	5.671ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	15.134m	5.067ms	99	100	99.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	7.352m	3.166ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	33.941m	12.060ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	9.832m	5.313ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	9.729m	3.138ms	88	90	97.78
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	25.396m	11.812ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	28.969m	7.281ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	35.450m	8.633ms	3	3	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	30.218m	7.760ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.570h	255.477ms	3	3	100.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	28.780m	14.589ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	24.193m	13.408ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	7.004m	4.582ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	10.899m	5.363ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	12.475m	3.881ms	0	3	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	25.570m	17.113ms	4	5	80.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	11.941m	18.226ms	3	3	100.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			2607	2644	98.60
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.607m	3.342ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark			0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus			0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	18.875m	6.488ms	0	1	0.00
		rom_e2e_jtag_debug_dev	20.282m	8.730ms	0	1	0.00
		rom_e2e_jtag_debug_rma	21.630m	7.928ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	38.166m	32.812ms	1	1	100.00
		rom_e2e_jtag_inject_dev	42.770m	24.798ms	1	1	100.00
		rom_e2e_jtag_inject_rma	42.748m	31.944ms	1	1	100.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash			0	0	--
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.092m	3.657ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	10.137m	2.847ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	33.159m	6.260ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	39.684m	9.251ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	11.917m	3.247ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	21.733m	5.434ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	//sw/device/tests:i2c_host_override_test			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	4.412m	3.294ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	12.177m	6.052ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	9.478m	6.875ms	3	3	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	8.962m	5.265ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	33.039m	12.426ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	15.134m	5.067ms	99	100	99.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	//sw/device/tests:spi_passthru_test			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	//sw/device/tests:spi_passthru_test			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	13.123m	4.755ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.270h	18.281ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	18.875m	6.488ms	0	1	0.00
		rom_e2e_jtag_debug_dev	20.282m	8.730ms	0	1	0.00
		rom_e2e_jtag_debug_rma	21.630m	7.928ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	13.641m	6.016ms	3	3	100.00
V3		TOTAL			35	45	77.78
	Unmapped tests	chip_sival_flash_info_access	6.843m	3.280ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	12.772m	5.147ms	3	3	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	5.070m	2.847ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	58.899m	17.712ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	17.329m	5.283ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	16.129m	4.910ms	3	3	100.00
		chip_sw_pwrmgr_lowpower_cancel	9.146m	3.398ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	11.081m	7.185ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	5.986m	2.613ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	4.840m	2.527ms	2	3	66.67
		chip_sw_flash_ctrl_write_clear	6.789m	3.711ms	3	3	100.00
		TOTAL			2877	2945	97.69

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	11	11	10	90.91
V1	18	18	17	94.44
V2	285	270	245	85.96
V2S	1	1	1	100.00
V3	90	21	15	16.67

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.14	95.59	93.98	95.45	--	94.77	97.53	99.53

Failure Buckets

UVM_ERROR @ * us: (cip_base_vseq.sv:828) [chip_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test chip_csr_mem_rw_with_rand_reset has 20 failures.
  - 0.chip_csr_mem_rw_with_rand_reset.104281603536138520933211493215958006948305723320906729844179816603120247494040
    Line 364, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2649.043763 us: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2649.043763 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_csr_mem_rw_with_rand_reset.42785047631109739709134137549794928438306235628750053973778840951997136514918
    Line 401, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2508.059351 us: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2508.059351 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:35) [chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:*-*-* has 15 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.21014958396348005906245652828303164357991553662658058164512466219557301379525
    Line 1012, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_ERROR @ 17831.524257 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  BFV:" == "BFV:07535603
  LCV:02108421
  "
  UVM_INFO @ 17831.524257 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.49656526373922798453282038222071239042861285707768496254571002760923211958607
    Line 1016, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_ERROR @ 22730.999127 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  BFV:" == "BFV:07535603
  LCV:21084210
  "
  UVM_INFO @ 22730.999127 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_prod.102435899086741287302378904768578157089927150950915086611907864596619387503198
    Line 1010, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest/run.log
```
  UVM_ERROR @ 22504.471017 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  BFV:" == "BFV:07535603
  LCV:2318c631
  "
  UVM_INFO @ 22504.471017 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.78961527607076392827234627015182704488103039977491532699792971382260564653718
    Line 1110, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest/run.log
```
  UVM_ERROR @ 22815.247415 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  BFV:" == "BFV:07535603
  LCV:25294a52
  "
  UVM_INFO @ 22815.247415 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_rma.103053575984887107212405719801055778008379101488625329744253445760459981754154
    Line 1034, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest/run.log
```
  UVM_ERROR @ 21947.104369 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  BFV:" == "BFV:07535603
  LCV:2739ce73
  "
  UVM_INFO @ 21947.104369 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- ... and 10 more tests.
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 11 failures:
- Test chip_sw_rv_timer_systick_test has 3 failures.
  - 0.chip_sw_rv_timer_systick_test.6279823703569850858219776391963628618149551895756246756710871033277844883084
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:da2892a7-66fd-4eb1-9caa-8c7c5fd0be0b
```
  - 1.chip_sw_rv_timer_systick_test.57831926431703283534722225792331266068471870287371877734945325805763063724067
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:bee373f1-03fa-4356-8ef4-1d60b9d7e9ef
```
  - ... and 1 more failures.
- Test chip_sw_coremark has 1 failures.
  - 0.chip_sw_coremark.52769760800450414475043013058697000678686445491647665006799134786033591290918
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
```
  Job ID: smart:634579f7-f0e9-4b27-9007-cd5dd7f1b3ab
```
- Test chip_sw_csrng_edn_concurrency_reduced_freq has 2 failures.
  - 0.chip_sw_csrng_edn_concurrency_reduced_freq.62459209617791354718177858070878474012866075656180126694547561427297057761029
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest/run.log
```
  Job ID: smart:cb4cdfea-f90a-481b-bb39-23eb9e90d95d
```
  - 2.chip_sw_csrng_edn_concurrency_reduced_freq.48037619323018900590321263004191893035016381354448656299226928835810951920004
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest/run.log
```
  Job ID: smart:819402cb-5f79-4e15-91f2-7c1221de2110
```
- Test chip_sw_ast_clk_rst_inputs has 2 failures.
  - 0.chip_sw_ast_clk_rst_inputs.15445751317681562624841566219905398794197125011741358288949511135559797817365
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:07945f5c-6633-4ac0-841f-dec9912582b3
```
  - 2.chip_sw_ast_clk_rst_inputs.69776212189703167044424862572997805206973010651249401888032039299233293475162
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:bfb5c519-e180-4b8f-b4d5-a5ecbbe84b17
```
- Test chip_sw_power_virus has 3 failures.
  - 0.chip_sw_power_virus.101165144471847918938213813652825233926253085302626723634943851314523909988864
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:633315db-0fd6-4ce7-b344-6ed41643b776
```
  - 1.chip_sw_power_virus.87509684040286879872081892799061544834187197278376201809154353267123291185168
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:1573e974-5d0d-443d-852d-9e45a29c66eb
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep. has 3 failures:
- Test chip_sw_rv_dm_access_after_wakeup has 3 failures.
  - 0.chip_sw_rv_dm_access_after_wakeup.77009134797603164645679954458707406137693459135884884931041668390243813921681
    Line 773, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3881.209346 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3881.209346 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_rv_dm_access_after_wakeup.78103034455970743181043942660542689052400073041189897496076049555562224454746
    Line 835, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3781.791165 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3781.791165 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:35) [chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:*-*-* has 3 failures:
- Test rom_e2e_shutdown_exception_c has 3 failures.
  - 0.rom_e2e_shutdown_exception_c.3918289342289033491026868809870843054514936374593927347332378796381925188718
    Line 1019, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_exception_c/latest/run.log
```
  UVM_ERROR @ 14557.113441 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:4001-0002-01
  BFV:" == "BFV:01495202
  LCV:2739ce73
  "
  UVM_INFO @ 14557.113441 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
  - 1.rom_e2e_shutdown_exception_c.34491304179094546237885908475459366580792712184144068366767804336176692527276
    Line 981, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_exception_c/latest/run.log
```
  UVM_ERROR @ 14949.481617 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:4001-0002-01
  BFV:" == "BFV:01495202
  LCV:2739ce73
  "
  UVM_INFO @ 14949.481617 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:35) [chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:*-*-* has 3 failures:
- Test rom_e2e_shutdown_output has 3 failures.
  - 0.rom_e2e_shutdown_output.20936761879070951648875062839151847900672545468204448784308558310173578771605
    Line 1014, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log
```
  UVM_ERROR @ 7162.762623 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:4001-0002-01
  BFV:" == "BFV:0142500d
  LCV:02108421
  "
  UVM_INFO @ 7162.762623 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
  - 1.rom_e2e_shutdown_output.11558546741040823193698561506608571188441995828794241624705428154688051375102
    Line 947, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_output/latest/run.log
```
  UVM_ERROR @ 6603.574356 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:4001-0002-01
  BFV:" == "BFV:0142500d
  LCV:02108421
  "
  UVM_INFO @ 6603.574356 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat" has 3 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.54741286886736986236621725597268892518902105566326355674612938804436518996286
    Line 810, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 6488.287500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat"
  UVM_INFO @ 6488.287500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.56207268418663799100598484874232597754168697295960004360580433111480373349050
    Line 826, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 8730.346500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat"
  UVM_INFO @ 8730.346500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.48252337896574971771978941824083278662460376883297224959099185655312397939890
    Line 797, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 7927.598500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat"
  UVM_INFO @ 7927.598500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 3 failures:

Test rom_raw_unlock has 3 failures.

0.rom_raw_unlock.71815940194117839170288410814590578589289661176736115995311045450418681505356
Line 787, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest/run.log

  UVM_ERROR @ 207213.877443 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns
  
  UVM_INFO @ 207213.877443 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.rom_raw_unlock.10792757835843845615793531905489184973361033087764624137857265438888571831539
Line 813, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_raw_unlock/latest/run.log

  UVM_ERROR @ 204113.760140 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns
  
  UVM_INFO @ 204113.760140 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL @ * us: (jtag_driver.sv:124) [driver] wait timeout occurred! has 3 failures:
- Test chip_tap_straps_testunlock0 has 2 failures.
  - 2.chip_tap_straps_testunlock0.92768751218079758876392458555694978184280000212486578059664076783367115706793
    Line 5944, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_tap_straps_testunlock0/latest/run.log
```
  UVM_FATAL @ 12808.862918 us: (jtag_driver.sv:124) [uvm_test_top.env.m_jtag_riscv_agent.m_jtag_agent.driver] wait timeout occurred!
  UVM_INFO @ 12808.862918 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.chip_tap_straps_testunlock0.4618384157207283812331435506662258734055522214400114830219230663402729065883
    Line 6185, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/4.chip_tap_straps_testunlock0/latest/run.log
```
  UVM_FATAL @ 15237.282950 us: (jtag_driver.sv:124) [uvm_test_top.env.m_jtag_riscv_agent.m_jtag_agent.driver] wait timeout occurred!
  UVM_INFO @ 15237.282950 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_tap_straps_rma has 1 failures.
  - 2.chip_tap_straps_rma.1721447767713860112905117165001154843414455032282065710456641692293697564364
    Line 5985, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_tap_straps_rma/latest/run.log
```
  UVM_FATAL @ 17112.782752 us: (jtag_driver.sv:124) [uvm_test_top.env.m_jtag_riscv_agent.m_jtag_agent.driver] wait timeout occurred!
  UVM_INFO @ 17112.782752 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 2 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 2 failures.
  - 73.chip_sw_alert_handler_lpg_sleep_mode_alerts.16378414849754285032913897328372588518911263177969811225977415595968566380989
    Line 791, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3368.698070 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003720 MTVAL=40600800
  UVM_INFO @ 3368.698070 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 83.chip_sw_alert_handler_lpg_sleep_mode_alerts.47292082673762587211479336629099984420854394847355902047484315281322652298736
    Line 768, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3783.527964 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003720 MTVAL=40600800
  UVM_INFO @ 3783.527964 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:695) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 2.chip_sw_rv_core_ibex_lockstep_glitch.12220089929036440099665990038311553763612304161056349767040517932235520017985
    Line 849, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2526.512564 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:695) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2526.512564 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 1 failures:
- Test chip_sw_all_escalation_resets has 1 failures.
  - 56.chip_sw_all_escalation_resets.35593194682249306391413906514241945430061598048649080677017714353840443816121
    Line 767, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/56.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2637.960232 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 2637.960232 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```