Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_core_ibex
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.48 94.12 89.29 85.81 100.00 68.18

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_core_ibex 87.69 94.12 89.29 86.88 100.00 68.18



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.69 94.12 89.29 86.88 100.00 68.18


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.99 94.18 75.50 89.86 93.28 92.14


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.50 90.68 86.81 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
fifo_d 100.00 100.00 100.00 100.00 100.00
fifo_i 93.75 75.00 100.00 100.00 100.00
gen_alert_senders[0].u_alert_sender 100.00 100.00
gen_alert_senders[1].u_alert_sender 75.00 75.00
gen_alert_senders[2].u_alert_sender 100.00 100.00
gen_alert_senders[3].u_alert_sender 75.00 75.00
tl_adapter_host_d_ibex 91.79 95.35 81.82 90.00 100.00
tl_adapter_host_i_ibex 87.90 90.48 72.22 88.89 100.00
u_alert_nmi_sync 100.00 100.00 100.00
u_core 95.91 95.91
u_core_sleeping_buf 100.00 100.00
u_dbus_trans 96.36 100.00 92.59 100.00 92.86
u_edn_if 89.08 100.00 86.44 94.87 75.00
u_ibus_trans 96.36 100.00 92.59 100.00 92.86
u_intr_timer_sync 100.00 100.00 100.00
u_lc_sync 100.00 100.00 100.00 100.00
u_prim_buf_irq 100.00 100.00
u_prim_esc_receiver 100.00 100.00
u_prim_lc_sender 100.00 100.00 100.00
u_prim_sync_reqack_data 91.67 100.00 66.67 100.00 100.00
u_pwrmgr_sync 100.00 100.00 100.00 100.00
u_reg_cfg 88.94 92.30 72.28 91.18 100.00
u_sim_win_rsp 89.32 77.27 80.00 100.00 100.00
u_tlul_req_buf 100.00 100.00
u_tlul_rsp_buf 100.00 100.00
u_wdog_nmi_sync 100.00 100.00 100.00

Line Coverage for Module : rv_core_ibex
Line No.TotalCoveredPercent
TOTAL858094.12
CONT_ASSIGN20211100.00
CONT_ASSIGN20311100.00
CONT_ASSIGN21611100.00
CONT_ASSIGN21711100.00
CONT_ASSIGN21811100.00
CONT_ASSIGN22511100.00
CONT_ASSIGN26311100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26811100.00
CONT_ASSIGN34211100.00
CONT_ASSIGN34811100.00
CONT_ASSIGN36311100.00
ALWAYS49233100.00
CONT_ASSIGN51211100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51411100.00
CONT_ASSIGN51511100.00
ALWAYS51888100.00
CONT_ASSIGN70211100.00
CONT_ASSIGN70211100.00
CONT_ASSIGN70311100.00
CONT_ASSIGN70311100.00
CONT_ASSIGN70411100.00
CONT_ASSIGN70411100.00
CONT_ASSIGN70811100.00
CONT_ASSIGN70811100.00
CONT_ASSIGN70911100.00
CONT_ASSIGN70911100.00
CONT_ASSIGN71011100.00
CONT_ASSIGN71011100.00
CONT_ASSIGN71711100.00
CONT_ASSIGN71811100.00
CONT_ASSIGN71911100.00
CONT_ASSIGN72211100.00
CONT_ASSIGN72411100.00
CONT_ASSIGN72611100.00
CONT_ASSIGN72811100.00
CONT_ASSIGN73511100.00
CONT_ASSIGN73711100.00
CONT_ASSIGN73911100.00
CONT_ASSIGN74111100.00
CONT_ASSIGN75111100.00
CONT_ASSIGN752100.00
CONT_ASSIGN75311100.00
CONT_ASSIGN75411100.00
CONT_ASSIGN75711100.00
CONT_ASSIGN760100.00
ALWAYS7921111100.00
ALWAYS80877100.00
CONT_ASSIGN81911100.00
CONT_ASSIGN83811100.00
CONT_ASSIGN83911100.00
CONT_ASSIGN84011100.00
CONT_ASSIGN843100.00
CONT_ASSIGN84700
CONT_ASSIGN88611100.00
ALWAYS94500
CONT_ASSIGN986100.00
CONT_ASSIGN988100.00
CONT_ASSIGN99011100.00
CONT_ASSIGN99211100.00
CONT_ASSIGN99411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
202 1 1
203 1 1
216 1 1
217 1 1
218 1 1
225 1 1
263 1 1
265 1 1
268 1 1
342 1 1
348 1 1
363 1 1
492 1 1
493 1 1
495 1 1
512 1 1
513 1 1
514 1 1
515 1 1
518 1 1
519 1 1
520 1 1
521 1 1
522 1 1
523 1 1
524 1 1
525 1 1
MISSING_ELSE
702 2 2
703 2 2
704 2 2
708 2 2
709 2 2
710 2 2
717 1 1
718 1 1
719 1 1
722 1 1
724 1 1
726 1 1
728 1 1
735 1 1
737 1 1
739 1 1
741 1 1
751 1 1
752 0 1
753 1 1
754 1 1
757 1 1
760 0 1
792 1 1
793 1 1
794 1 1
796 1 1
797 1 1
798 1 1
799 1 1
800 1 1
801 1 1
802 1 1
803 1 1
MISSING_ELSE
808 1 1
809 1 1
810 1 1
811 1 1
813 1 1
814 1 1
815 1 1
819 1 1
838 1 1
839 1 1
840 1 1
843 0 1
847 unreachable
886 1 1
945 unreachable
946 unreachable
947 unreachable
948 unreachable
==> MISSING_ELSE
986 0 1
988 0 1
990 1 1
992 1 1
994 1 1


Cond Coverage for Module : rv_core_ibex
TotalCoveredPercent
Conditions282589.29
Logical282589.29
Non-Logical00
Event00

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------
-1--2--3-StatusTests
000CoveredT4,T5,T6
001CoveredT187,T263,T264
010Not Covered
100Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT188,T265,T266
10CoveredT18,T38,T73

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT18,T38,T188

 LINE       735
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------
-1--2-StatusTests
01CoveredT166,T25,T230
10CoveredT4,T6,T20
11CoveredT123,T124,T125

 LINE       737
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------
-1--2-StatusTests
01CoveredT123,T124,T125
10CoveredT4,T6,T20
11CoveredT166,T25,T230

 LINE       739
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------
-1--2-StatusTests
01CoveredT166,T25,T230
10CoveredT4,T6,T20
11CoveredT123,T124,T125

 LINE       741
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------
-1--2-StatusTests
01CoveredT166,T25,T230
10CoveredT4,T6,T20
11CoveredT123,T124,T125

 LINE       753
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------
-1--2--3-StatusTests
000CoveredT4,T5,T6
001CoveredT18,T38,T188
010CoveredT187,T263,T264
100CoveredT267,T268,T269

 LINE       800
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT4,T17,T18
11CoveredT4,T6,T20

Toggle Coverage for Module : rv_core_ibex
TotalCoveredPercent
Totals 123 90 73.17
Total Bits 1628 1397 85.81
Total Bits 0->1 814 699 85.87
Total Bits 1->0 814 698 85.75

Ports 123 90 73.17
Port Bits 1628 1397 85.81
Port Bits 0->1 814 699 85.87
Port Bits 1->0 814 698 85.75

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T17,T18,T19 Yes T4,T5,T6 INPUT
clk_edn_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_edn_ni Yes Yes T17,T18,T19 Yes T4,T5,T6 INPUT
clk_esc_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_esc_ni Yes Yes T17,T18,T19 Yes T4,T5,T6 INPUT
rst_cpu_n_o Yes Yes T17,T18,T19 Yes T4,T5,T6 OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.rf_cfg.test No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.test No No No INPUT
hart_id_i[31:0] Unreachable Unreachable Unreachable INPUT
boot_addr_i[31:0] Unreachable Unreachable Unreachable INPUT
corei_tl_h_o.d_ready No No No OUTPUT
corei_tl_h_o.a_user.data_intg[6:0] No No No OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 OUTPUT
corei_tl_h_o.a_user.instr_type[3:0] No No No OUTPUT
corei_tl_h_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
corei_tl_h_o.a_data[31:0] No No No OUTPUT
corei_tl_h_o.a_mask[3:0] No No No OUTPUT
corei_tl_h_o.a_address[1:0] No No No OUTPUT
corei_tl_h_o.a_address[16:2] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 OUTPUT
corei_tl_h_o.a_address[18:17] No No No OUTPUT
corei_tl_h_o.a_address[19] No No Yes T77,T191,T270 OUTPUT
corei_tl_h_o.a_address[27:20] No No No OUTPUT
corei_tl_h_o.a_address[29:28] Yes Yes *T263,*T264,*T74 Yes T26,T263,T264 OUTPUT
corei_tl_h_o.a_address[31:30] No No No OUTPUT
corei_tl_h_o.a_source[2:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 OUTPUT
corei_tl_h_o.a_source[5:3] No No No OUTPUT
corei_tl_h_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
corei_tl_h_o.a_size[1:0] No No No OUTPUT
corei_tl_h_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
corei_tl_h_o.a_opcode[2:0] No No No OUTPUT
corei_tl_h_o.a_valid Yes Yes T4,T6,T20 Yes T4,T6,T20 OUTPUT
corei_tl_h_i.a_ready Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
corei_tl_h_i.d_error Yes Yes T19,T160,T161 Yes T19,T160,T161 INPUT
corei_tl_h_i.d_user.data_intg[6:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
corei_tl_h_i.d_user.rsp_intg[5:0] Yes Yes *T19,*T160,*T161 Yes T19,T160,T161 INPUT
corei_tl_h_i.d_user.rsp_intg[6] No No No INPUT
corei_tl_h_i.d_data[31:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
corei_tl_h_i.d_sink No No No INPUT
corei_tl_h_i.d_source[2:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
corei_tl_h_i.d_source[5:3] No No No INPUT
corei_tl_h_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
corei_tl_h_i.d_size[0] No No No INPUT
corei_tl_h_i.d_size[1] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
corei_tl_h_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
corei_tl_h_i.d_opcode[0] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 INPUT
corei_tl_h_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
corei_tl_h_i.d_valid Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
cored_tl_h_o.d_ready Yes Yes T23,T24,T28 Yes T23,T24,T28 OUTPUT
cored_tl_h_o.a_user.data_intg[6:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 OUTPUT
cored_tl_h_o.a_user.instr_type[3:0] Yes Yes T23,T60,T62 Yes T23,T60,T62 OUTPUT
cored_tl_h_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
cored_tl_h_o.a_data[31:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 OUTPUT
cored_tl_h_o.a_mask[3:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 OUTPUT
cored_tl_h_o.a_address[31:0] Yes Yes T23,T60,T62 Yes T23,T60,T62 OUTPUT
cored_tl_h_o.a_source[5:0] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 OUTPUT
cored_tl_h_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
cored_tl_h_o.a_size[1:0] Yes Yes T23,T60,T61 Yes T23,T60,T61 OUTPUT
cored_tl_h_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
cored_tl_h_o.a_opcode[0] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 OUTPUT
cored_tl_h_o.a_opcode[1] No No No OUTPUT
cored_tl_h_o.a_opcode[2] Yes Yes T4,T6,T20 Yes T4,T6,T20 OUTPUT
cored_tl_h_o.a_valid Yes Yes T4,T6,T20 Yes T4,T6,T20 OUTPUT
cored_tl_h_i.a_ready Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
cored_tl_h_i.d_error Yes Yes T17,T19,T160 Yes T17,T19,T160 INPUT
cored_tl_h_i.d_user.data_intg[6:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
cored_tl_h_i.d_user.rsp_intg[5:0] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 INPUT
cored_tl_h_i.d_user.rsp_intg[6] No No No INPUT
cored_tl_h_i.d_data[31:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
cored_tl_h_i.d_sink No No No INPUT
cored_tl_h_i.d_source[5:0] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 INPUT
cored_tl_h_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
cored_tl_h_i.d_size[1:0] Yes Yes T60,T61,T62 Yes T60,T61,T62 INPUT
cored_tl_h_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
cored_tl_h_i.d_opcode[0] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 INPUT
cored_tl_h_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
cored_tl_h_i.d_valid Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
irq_software_i Yes Yes T271,T272,T28 Yes T271,T272,T28 INPUT
irq_timer_i Yes Yes T157,T273,T158 Yes T157,T273,T158 INPUT
irq_external_i Yes Yes T6,T20,T21 Yes T6,T20,T21 INPUT
esc_tx_i.esc_n Yes Yes T17,T19,T31 Yes T17,T19,T31 INPUT
esc_tx_i.esc_p Yes Yes T17,T19,T31 Yes T17,T19,T31 INPUT
esc_rx_o.resp_n Yes Yes T17,T19,T31 Yes T17,T19,T31 OUTPUT
esc_rx_o.resp_p Yes Yes T17,T19,T31 Yes T17,T19,T31 OUTPUT
nmi_wdog_i Yes Yes T274,T249,T88 Yes T274,T249,T88 INPUT
debug_req_i Yes Yes T26,T27,T22 Yes T26,T27,T22 INPUT
crash_dump_o.current.exception_addr[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.current.exception_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.current.last_data_addr[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.current.next_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.current.current_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.prev_exception_addr[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.prev_exception_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.prev_valid Unreachable Unreachable Unreachable OUTPUT
lc_cpu_en_i[3:0] Yes Yes T17,T18,T19 Yes T4,T6,T20 INPUT
pwrmgr_cpu_en_i[3:0] Yes Yes T17,T18,T19 Yes T4,T5,T6 INPUT
pwrmgr_o.core_sleeping Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
scan_rst_ni Unreachable Unreachable Unreachable INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT
cfg_tl_d_i.d_ready Yes Yes T4,T6,T20 Yes T4,T5,T6 INPUT
cfg_tl_d_i.a_user.data_intg[6:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
cfg_tl_d_i.a_user.cmd_intg[0] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 INPUT
cfg_tl_d_i.a_user.cmd_intg[1] No No No INPUT
cfg_tl_d_i.a_user.cmd_intg[6:2] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
cfg_tl_d_i.a_user.instr_type[0] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 INPUT
cfg_tl_d_i.a_user.instr_type[2:1] No No No INPUT
cfg_tl_d_i.a_user.instr_type[3] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
cfg_tl_d_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
cfg_tl_d_i.a_data[31:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
cfg_tl_d_i.a_mask[3:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
cfg_tl_d_i.a_address[1:0] No No No INPUT
cfg_tl_d_i.a_address[7:2] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 INPUT
cfg_tl_d_i.a_address[15:8] Unreachable Unreachable Unreachable INPUT
cfg_tl_d_i.a_address[20:16] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
cfg_tl_d_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
cfg_tl_d_i.a_address[24] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 INPUT
cfg_tl_d_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
cfg_tl_d_i.a_address[30] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 INPUT
cfg_tl_d_i.a_address[31] Unreachable Unreachable Unreachable INPUT
cfg_tl_d_i.a_source[0] No No No INPUT
cfg_tl_d_i.a_source[1] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 INPUT
cfg_tl_d_i.a_source[5:2] No No No INPUT
cfg_tl_d_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
cfg_tl_d_i.a_size[0] No No No INPUT
cfg_tl_d_i.a_size[1] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
cfg_tl_d_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
cfg_tl_d_i.a_opcode[1:0] No No No INPUT
cfg_tl_d_i.a_opcode[2] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
cfg_tl_d_i.a_valid Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
cfg_tl_d_o.a_ready Yes Yes T4,T6,T20 Yes T4,T6,T20 OUTPUT
cfg_tl_d_o.d_error No No No OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0] Yes Yes T4,T17,T19 Yes T4,T17,T19 OUTPUT
cfg_tl_d_o.d_user.rsp_intg[1:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 OUTPUT
cfg_tl_d_o.d_user.rsp_intg[3:2] No No No OUTPUT
cfg_tl_d_o.d_user.rsp_intg[5:4] Yes Yes T17,T18,T19 Yes T4,T6,T20 OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6] No No No OUTPUT
cfg_tl_d_o.d_data[31:0] Yes Yes T4,T17,T19 Yes T4,T17,T19 OUTPUT
cfg_tl_d_o.d_sink No No No OUTPUT
cfg_tl_d_o.d_source[0] No No No OUTPUT
cfg_tl_d_o.d_source[1] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 OUTPUT
cfg_tl_d_o.d_source[5:2] No No No OUTPUT
cfg_tl_d_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
cfg_tl_d_o.d_size[0] No No No OUTPUT
cfg_tl_d_o.d_size[1] Yes Yes T17,T18,T19 Yes T4,T6,T20 OUTPUT
cfg_tl_d_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
cfg_tl_d_o.d_opcode[0] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 OUTPUT
cfg_tl_d_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
cfg_tl_d_o.d_valid Yes Yes T4,T6,T20 Yes T4,T6,T20 OUTPUT
edn_o.edn_req Yes Yes T4,T6,T20 Yes T4,T5,T6 OUTPUT
edn_i.edn_bus[31:0] Yes Yes T4,T17,T19 Yes T4,T21,T132 INPUT
edn_i.edn_fips Yes Yes T101,T103,T181 Yes T101,T103,T181 INPUT
edn_i.edn_ack Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
clk_otp_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_otp_ni Yes Yes T17,T18,T19 Yes T4,T5,T6 INPUT
icache_otp_key_o.req Yes Yes T219,T220,T221 Yes T219,T220,T221 OUTPUT
icache_otp_key_i.seed_valid Yes Yes T17,T18,T19 Yes T4,T6,T20 INPUT
icache_otp_key_i.nonce[127:0] Yes Yes T4,T6,T21 Yes T4,T6,T20 INPUT
icache_otp_key_i.key[127:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
icache_otp_key_i.ack Yes Yes T219,T220,T221 Yes T219,T220,T221 INPUT
fpga_info_i[31:0] Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T17,T161,T33 Yes T17,T161,T33 INPUT
alert_rx_i[0].ping_n Yes Yes T33,T34,T35 Yes T33,T34,T35 INPUT
alert_rx_i[0].ping_p Yes Yes T33,T34,T35 Yes T33,T34,T35 INPUT
alert_rx_i[1].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[1].ack_p Yes Yes T166,T25,T131 Yes T166,T25,T131 INPUT
alert_rx_i[1].ping_n Yes Yes T131,T33,T34 Yes T131,T33,T34 INPUT
alert_rx_i[1].ping_p Yes Yes T131,T33,T34 Yes T131,T33,T34 INPUT
alert_rx_i[2].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[2].ack_p Yes Yes T187,T188,T267 Yes T187,T188,T267 INPUT
alert_rx_i[2].ping_n Yes Yes T33,T34,T35 Yes T33,T34,T35 INPUT
alert_rx_i[2].ping_p Yes Yes T33,T34,T35 Yes T33,T34,T35 INPUT
alert_rx_i[3].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[3].ack_p Yes Yes T33,T123,T34 Yes T33,T123,T34 INPUT
alert_rx_i[3].ping_n Yes Yes T33,T34,T35 Yes T33,T34,T35 INPUT
alert_rx_i[3].ping_p Yes Yes T33,T34,T35 Yes T33,T34,T35 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T17,T161,T33 Yes T17,T161,T33 OUTPUT
alert_tx_o[1].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[1].alert_p Yes Yes T166,T25,T131 Yes T166,T25,T131 OUTPUT
alert_tx_o[2].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[2].alert_p Yes Yes T187,T188,T267 Yes T187,T188,T267 OUTPUT
alert_tx_o[3].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[3].alert_p Yes Yes T33,T123,T34 Yes T33,T123,T34 OUTPUT

*Tests covering at least one bit in the range

Branch Coverage for Module : rv_core_ibex
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 348 2 2 100.00
IF 492 2 2 100.00
IF 518 3 3 100.00
IF 796 3 3 100.00
IF 808 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 348 (fatal_core_err) ?

Branches:
-1-StatusTests
1 Covered T18,T38,T188
0 Covered T4,T5,T6


LineNo. Expression -1-: 492 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 518 if ((!rst_ni)) -2-: 522 if (double_fault)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T188,T265,T266
0 0 Covered T4,T5,T6


LineNo. Expression -1-: 796 if (reg2hw.rnd_data.re) -2-: 800 if ((edn_req && edn_ack))

Branches:
-1--2-StatusTests
1 - Covered T4,T17,T19
0 1 Covered T4,T6,T20
0 0 Covered T4,T6,T20


LineNo. Expression -1-: 808 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


Assert Coverage for Module : rv_core_ibex
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 22 22 100.00 15 68.18
Cover properties 0 0 0
Cover sequences 0 0 0
Total 22 22 100.00 15 68.18




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
FpvSecCmIbexFetchEnable0_A 470097304 6 0 0
FpvSecCmIbexFetchEnable1_A 470097304 24506185 0 74
FpvSecCmIbexFetchEnable2_A 470097304 64734617 0 60
FpvSecCmIbexFetchEnable3Rev_A 470097304 400669813 0 1970
FpvSecCmIbexFetchEnable3_A 470097304 400671680 0 1887
FpvSecCmIbexInstrIntgErrCheck_A 470097304 155 0 0
FpvSecCmIbexLoadRespIntgErrCheck_A 470097304 587 0 0
FpvSecCmIbexLockstepResetCountAlertCheck_A 470097304 0 0 0
FpvSecCmIbexPcMismatchCheck_A 470097304 0 0 0
FpvSecCmIbexRfEccErrCheck_A 470097304 0 0 0
FpvSecCmIbexStoreRespIntgErrCheck_A 470097304 0 0 0
FpvSecCmRegWeOnehotCheck_A 470097304 5 0 0
FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A 470097304 0 0 0
FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A 470097304 0 0 0
FpvSecCmRvCoreRegWeOnehotCheck_A 470097304 0 0 0
g_instr_intg_err_assert_signals.AssertConnected_A 992 992 0 0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A 992 992 0 0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A 992 992 0 0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A 992 992 0 0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A 992 992 0 0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A 470097304 185 0 0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A 470097304 195 0 0


FpvSecCmIbexFetchEnable0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470097304 6 0 0
T45 235746 0 0 0
T73 189644 0 0 0
T172 79138 0 0 0
T185 130146 0 0 0
T188 257609 1 0 0
T191 223629 0 0 0
T241 239260 0 0 0
T265 0 1 0 0
T266 0 1 0 0
T275 0 1 0 0
T276 0 1 0 0
T277 0 1 0 0
T278 113843 0 0 0
T279 97448 0 0 0
T280 160562 0 0 0

FpvSecCmIbexFetchEnable1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470097304 24506185 0 74
T4 134245 9923 0 0
T5 41365 41312 0 2
T6 197158 9923 0 0
T17 221235 41081 0 0
T18 219998 19846 0 0
T19 261468 41104 0 0
T20 218705 9931 0 0
T21 663418 9931 0 0
T23 0 0 0 2
T24 0 0 0 2
T73 0 0 0 2
T74 0 0 0 2
T79 0 0 0 2
T80 0 0 0 2
T91 217010 9927 0 0
T132 212915 9931 0 0
T217 0 0 0 2
T281 0 0 0 2
T282 0 0 0 2

FpvSecCmIbexFetchEnable2_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470097304 64734617 0 60
T4 134245 34775 0 0
T5 41365 34775 0 0
T6 197158 34775 0 0
T17 221235 69554 0 0
T18 219998 69555 0 0
T19 261468 69551 0 0
T20 218705 34775 0 0
T21 663418 34775 0 0
T23 0 0 0 2
T24 0 0 0 2
T28 0 0 0 2
T73 0 0 0 2
T74 0 0 0 2
T79 0 0 0 2
T91 217010 34775 0 0
T132 212915 34775 0 0
T150 0 0 0 2
T168 0 0 0 2
T217 0 0 0 2
T218 0 0 0 2

FpvSecCmIbexFetchEnable3Rev_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470097304 400669813 0 1970
T4 134245 130763 0 2
T5 41365 0 0 2
T6 197158 162329 0 2
T17 221235 130336 0 2
T18 219998 150331 0 2
T19 261468 170545 0 2
T20 218705 183865 0 2
T21 663418 628578 0 2
T31 0 171088 0 0
T91 217010 182174 0 2
T132 212915 178075 0 2

FpvSecCmIbexFetchEnable3_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470097304 400671680 0 1887
T4 134245 130763 0 2
T5 41365 0 0 0
T6 197158 162330 0 2
T17 221235 130338 0 2
T18 219998 150333 0 2
T19 261468 170546 0 2
T20 218705 183866 0 2
T21 663418 628579 0 2
T31 0 171090 0 2
T91 217010 182175 0 2
T132 212915 178076 0 2

FpvSecCmIbexInstrIntgErrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470097304 155 0 0
T84 167235 0 0 0
T138 0 77 0 0
T216 424187 0 0 0
T263 276057 78 0 0
T264 299433 0 0 0
T283 95815 0 0 0
T284 354020 0 0 0
T285 288317 0 0 0
T286 361548 0 0 0
T287 60218 0 0 0
T288 183967 0 0 0

FpvSecCmIbexLoadRespIntgErrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470097304 587 0 0
T23 114721 0 0 0
T79 54139 0 0 0
T87 321816 0 0 0
T88 290079 0 0 0
T94 0 32 0 0
T95 0 31 0 0
T96 0 32 0 0
T102 216886 0 0 0
T152 61484 0 0 0
T171 74171 0 0 0
T187 191367 32 0 0
T231 125514 0 0 0
T264 0 1 0 0
T289 0 32 0 0
T290 0 32 0 0
T291 0 99 0 0
T292 0 31 0 0
T293 0 32 0 0
T294 42238 0 0 0

FpvSecCmIbexLockstepResetCountAlertCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470097304 0 0 0

FpvSecCmIbexPcMismatchCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470097304 0 0 0

FpvSecCmIbexRfEccErrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470097304 0 0 0

FpvSecCmIbexStoreRespIntgErrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470097304 0 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470097304 5 0 0
T26 872290 0 0 0
T48 186091 0 0 0
T110 315763 0 0 0
T170 275093 0 0 0
T267 262270 1 0 0
T268 0 1 0 0
T269 0 1 0 0
T295 0 1 0 0
T296 0 1 0 0
T297 151438 0 0 0
T298 229682 0 0 0
T299 237363 0 0 0
T300 662936 0 0 0
T301 265229 0 0 0

FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470097304 0 0 0

FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470097304 0 0 0

FpvSecCmRvCoreRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470097304 0 0 0

g_instr_intg_err_assert_signals.AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 992 992 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T91 1 1 0 0
T132 1 1 0 0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 992 992 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T91 1 1 0 0
T132 1 1 0 0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 992 992 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T91 1 1 0 0
T132 1 1 0 0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 992 992 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T91 1 1 0 0
T132 1 1 0 0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 992 992 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T91 1 1 0 0
T132 1 1 0 0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470097304 185 0 0
T30 281838 0 0 0
T182 166829 0 0 0
T204 274625 0 0 0
T219 69565 28 0 0
T220 90942 33 0 0
T221 0 49 0 0
T302 0 8 0 0
T303 0 33 0 0
T304 0 34 0 0
T305 500836 0 0 0
T306 244134 0 0 0
T307 106667 0 0 0
T308 889506 0 0 0
T309 102304 0 0 0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470097304 195 0 0
T30 281838 0 0 0
T182 166829 0 0 0
T189 0 16 0 0
T190 0 16 0 0
T204 274625 0 0 0
T219 69565 7 0 0
T220 90942 42 0 0
T221 0 12 0 0
T302 0 2 0 0
T303 0 42 0 0
T304 0 42 0 0
T305 500836 0 0 0
T306 244134 0 0 0
T307 106667 0 0 0
T308 889506 0 0 0
T309 102304 0 0 0
T310 0 16 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex
Line No.TotalCoveredPercent
TOTAL858094.12
CONT_ASSIGN20211100.00
CONT_ASSIGN20311100.00
CONT_ASSIGN21611100.00
CONT_ASSIGN21711100.00
CONT_ASSIGN21811100.00
CONT_ASSIGN22511100.00
CONT_ASSIGN26311100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26811100.00
CONT_ASSIGN34211100.00
CONT_ASSIGN34811100.00
CONT_ASSIGN36311100.00
ALWAYS49233100.00
CONT_ASSIGN51211100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51411100.00
CONT_ASSIGN51511100.00
ALWAYS51888100.00
CONT_ASSIGN70211100.00
CONT_ASSIGN70211100.00
CONT_ASSIGN70311100.00
CONT_ASSIGN70311100.00
CONT_ASSIGN70411100.00
CONT_ASSIGN70411100.00
CONT_ASSIGN70811100.00
CONT_ASSIGN70811100.00
CONT_ASSIGN70911100.00
CONT_ASSIGN70911100.00
CONT_ASSIGN71011100.00
CONT_ASSIGN71011100.00
CONT_ASSIGN71711100.00
CONT_ASSIGN71811100.00
CONT_ASSIGN71911100.00
CONT_ASSIGN72211100.00
CONT_ASSIGN72411100.00
CONT_ASSIGN72611100.00
CONT_ASSIGN72811100.00
CONT_ASSIGN73511100.00
CONT_ASSIGN73711100.00
CONT_ASSIGN73911100.00
CONT_ASSIGN74111100.00
CONT_ASSIGN75111100.00
CONT_ASSIGN752100.00
CONT_ASSIGN75311100.00
CONT_ASSIGN75411100.00
CONT_ASSIGN75711100.00
CONT_ASSIGN760100.00
ALWAYS7921111100.00
ALWAYS80877100.00
CONT_ASSIGN81911100.00
CONT_ASSIGN83811100.00
CONT_ASSIGN83911100.00
CONT_ASSIGN84011100.00
CONT_ASSIGN843100.00
CONT_ASSIGN84700
CONT_ASSIGN88611100.00
ALWAYS94500
CONT_ASSIGN986100.00
CONT_ASSIGN988100.00
CONT_ASSIGN99011100.00
CONT_ASSIGN99211100.00
CONT_ASSIGN99411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
202 1 1
203 1 1
216 1 1
217 1 1
218 1 1
225 1 1
263 1 1
265 1 1
268 1 1
342 1 1
348 1 1
363 1 1
492 1 1
493 1 1
495 1 1
512 1 1
513 1 1
514 1 1
515 1 1
518 1 1
519 1 1
520 1 1
521 1 1
522 1 1
523 1 1
524 1 1
525 1 1
MISSING_ELSE
702 2 2
703 2 2
704 2 2
708 2 2
709 2 2
710 2 2
717 1 1
718 1 1
719 1 1
722 1 1
724 1 1
726 1 1
728 1 1
735 1 1
737 1 1
739 1 1
741 1 1
751 1 1
752 0 1
753 1 1
754 1 1
757 1 1
760 0 1
792 1 1
793 1 1
794 1 1
796 1 1
797 1 1
798 1 1
799 1 1
800 1 1
801 1 1
802 1 1
803 1 1
MISSING_ELSE
808 1 1
809 1 1
810 1 1
811 1 1
813 1 1
814 1 1
815 1 1
819 1 1
838 1 1
839 1 1
840 1 1
843 0 1
847 unreachable
886 1 1
945 unreachable
946 unreachable
947 unreachable
948 unreachable
==> MISSING_ELSE
986 0 1
988 0 1
990 1 1
992 1 1
994 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex
TotalCoveredPercent
Conditions282589.29
Logical282589.29
Non-Logical00
Event00

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------
-1--2--3-StatusTests
000CoveredT4,T5,T6
001CoveredT187,T263,T264
010Not Covered
100Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT188,T265,T266
10CoveredT18,T38,T73

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT18,T38,T188

 LINE       735
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------
-1--2-StatusTests
01CoveredT166,T25,T230
10CoveredT4,T6,T20
11CoveredT123,T124,T125

 LINE       737
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------
-1--2-StatusTests
01CoveredT123,T124,T125
10CoveredT4,T6,T20
11CoveredT166,T25,T230

 LINE       739
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------
-1--2-StatusTests
01CoveredT166,T25,T230
10CoveredT4,T6,T20
11CoveredT123,T124,T125

 LINE       741
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------
-1--2-StatusTests
01CoveredT166,T25,T230
10CoveredT4,T6,T20
11CoveredT123,T124,T125

 LINE       753
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------
-1--2--3-StatusTests
000CoveredT4,T5,T6
001CoveredT18,T38,T188
010CoveredT187,T263,T264
100CoveredT267,T268,T269

 LINE       800
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT4,T17,T18
11CoveredT4,T6,T20

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex
TotalCoveredPercent
Totals 119 90 75.63
Total Bits 1608 1397 86.88
Total Bits 0->1 804 699 86.94
Total Bits 1->0 804 698 86.82

Ports 119 90 75.63
Port Bits 1608 1397 86.88
Port Bits 0->1 804 699 86.94
Port Bits 1->0 804 698 86.82

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T17,T18,T19 Yes T4,T5,T6 INPUT
clk_edn_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_edn_ni Yes Yes T17,T18,T19 Yes T4,T5,T6 INPUT
clk_esc_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_esc_ni Yes Yes T17,T18,T19 Yes T4,T5,T6 INPUT
rst_cpu_n_o Yes Yes T17,T18,T19 Yes T4,T5,T6 OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.test No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.test No No No INPUT
hart_id_i[31:0] Unreachable Unreachable Unreachable INPUT
boot_addr_i[31:0] Unreachable Unreachable Unreachable INPUT
corei_tl_h_o.d_ready No No No OUTPUT
corei_tl_h_o.a_user.data_intg[6:0] No No No OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 OUTPUT
corei_tl_h_o.a_user.instr_type[3:0] No No No OUTPUT
corei_tl_h_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
corei_tl_h_o.a_data[31:0] No No No OUTPUT
corei_tl_h_o.a_mask[3:0] No No No OUTPUT
corei_tl_h_o.a_address[1:0] No No No OUTPUT
corei_tl_h_o.a_address[16:2] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 OUTPUT
corei_tl_h_o.a_address[18:17] No No No OUTPUT
corei_tl_h_o.a_address[19] No No Yes T77,T191,T270 OUTPUT
corei_tl_h_o.a_address[27:20] No No No OUTPUT
corei_tl_h_o.a_address[29:28] Yes Yes *T263,*T264,*T74 Yes T26,T263,T264 OUTPUT
corei_tl_h_o.a_address[31:30] No No No OUTPUT
corei_tl_h_o.a_source[2:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 OUTPUT
corei_tl_h_o.a_source[5:3] No No No OUTPUT
corei_tl_h_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
corei_tl_h_o.a_size[1:0] No No No OUTPUT
corei_tl_h_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
corei_tl_h_o.a_opcode[2:0] No No No OUTPUT
corei_tl_h_o.a_valid Yes Yes T4,T6,T20 Yes T4,T6,T20 OUTPUT
corei_tl_h_i.a_ready Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
corei_tl_h_i.d_error Yes Yes T19,T160,T161 Yes T19,T160,T161 INPUT
corei_tl_h_i.d_user.data_intg[6:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
corei_tl_h_i.d_user.rsp_intg[5:0] Yes Yes *T19,*T160,*T161 Yes T19,T160,T161 INPUT
corei_tl_h_i.d_user.rsp_intg[6] No No No INPUT
corei_tl_h_i.d_data[31:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
corei_tl_h_i.d_sink No No No INPUT
corei_tl_h_i.d_source[2:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
corei_tl_h_i.d_source[5:3] No No No INPUT
corei_tl_h_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
corei_tl_h_i.d_size[0] No No No INPUT
corei_tl_h_i.d_size[1] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
corei_tl_h_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
corei_tl_h_i.d_opcode[0] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 INPUT
corei_tl_h_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
corei_tl_h_i.d_valid Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
cored_tl_h_o.d_ready Yes Yes T23,T24,T28 Yes T23,T24,T28 OUTPUT
cored_tl_h_o.a_user.data_intg[6:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 OUTPUT
cored_tl_h_o.a_user.instr_type[3:0] Yes Yes T23,T60,T62 Yes T23,T60,T62 OUTPUT
cored_tl_h_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
cored_tl_h_o.a_data[31:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 OUTPUT
cored_tl_h_o.a_mask[3:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 OUTPUT
cored_tl_h_o.a_address[31:0] Yes Yes T23,T60,T62 Yes T23,T60,T62 OUTPUT
cored_tl_h_o.a_source[5:0] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 OUTPUT
cored_tl_h_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
cored_tl_h_o.a_size[1:0] Yes Yes T23,T60,T61 Yes T23,T60,T61 OUTPUT
cored_tl_h_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
cored_tl_h_o.a_opcode[0] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 OUTPUT
cored_tl_h_o.a_opcode[1] No No No OUTPUT
cored_tl_h_o.a_opcode[2] Yes Yes T4,T6,T20 Yes T4,T6,T20 OUTPUT
cored_tl_h_o.a_valid Yes Yes T4,T6,T20 Yes T4,T6,T20 OUTPUT
cored_tl_h_i.a_ready Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
cored_tl_h_i.d_error Yes Yes T17,T19,T160 Yes T17,T19,T160 INPUT
cored_tl_h_i.d_user.data_intg[6:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
cored_tl_h_i.d_user.rsp_intg[5:0] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 INPUT
cored_tl_h_i.d_user.rsp_intg[6] No No No INPUT
cored_tl_h_i.d_data[31:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
cored_tl_h_i.d_sink No No No INPUT
cored_tl_h_i.d_source[5:0] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 INPUT
cored_tl_h_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
cored_tl_h_i.d_size[1:0] Yes Yes T60,T61,T62 Yes T60,T61,T62 INPUT
cored_tl_h_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
cored_tl_h_i.d_opcode[0] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 INPUT
cored_tl_h_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
cored_tl_h_i.d_valid Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
irq_software_i Yes Yes T271,T272,T28 Yes T271,T272,T28 INPUT
irq_timer_i Yes Yes T157,T273,T158 Yes T157,T273,T158 INPUT
irq_external_i Yes Yes T6,T20,T21 Yes T6,T20,T21 INPUT
esc_tx_i.esc_n Yes Yes T17,T19,T31 Yes T17,T19,T31 INPUT
esc_tx_i.esc_p Yes Yes T17,T19,T31 Yes T17,T19,T31 INPUT
esc_rx_o.resp_n Yes Yes T17,T19,T31 Yes T17,T19,T31 OUTPUT
esc_rx_o.resp_p Yes Yes T17,T19,T31 Yes T17,T19,T31 OUTPUT
nmi_wdog_i Yes Yes T274,T249,T88 Yes T274,T249,T88 INPUT
debug_req_i Yes Yes T26,T27,T22 Yes T26,T27,T22 INPUT
crash_dump_o.current.exception_addr[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.current.exception_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.current.last_data_addr[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.current.next_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.current.current_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.prev_exception_addr[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.prev_exception_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.prev_valid Unreachable Unreachable Unreachable OUTPUT
lc_cpu_en_i[3:0] Yes Yes T17,T18,T19 Yes T4,T6,T20 INPUT
pwrmgr_cpu_en_i[3:0] Yes Yes T17,T18,T19 Yes T4,T5,T6 INPUT
pwrmgr_o.core_sleeping Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
scan_rst_ni Unreachable Unreachable Unreachable INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT
cfg_tl_d_i.d_ready Yes Yes T4,T6,T20 Yes T4,T5,T6 INPUT
cfg_tl_d_i.a_user.data_intg[6:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
cfg_tl_d_i.a_user.cmd_intg[0] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 INPUT
cfg_tl_d_i.a_user.cmd_intg[1] No No No INPUT
cfg_tl_d_i.a_user.cmd_intg[6:2] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
cfg_tl_d_i.a_user.instr_type[0] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 INPUT
cfg_tl_d_i.a_user.instr_type[2:1] No No No INPUT
cfg_tl_d_i.a_user.instr_type[3] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
cfg_tl_d_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
cfg_tl_d_i.a_data[31:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
cfg_tl_d_i.a_mask[3:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
cfg_tl_d_i.a_address[1:0] No No No INPUT
cfg_tl_d_i.a_address[7:2] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 INPUT
cfg_tl_d_i.a_address[15:8] Unreachable Unreachable Unreachable INPUT
cfg_tl_d_i.a_address[20:16] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
cfg_tl_d_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
cfg_tl_d_i.a_address[24] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 INPUT
cfg_tl_d_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
cfg_tl_d_i.a_address[30] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 INPUT
cfg_tl_d_i.a_address[31] Unreachable Unreachable Unreachable INPUT
cfg_tl_d_i.a_source[0] No No No INPUT
cfg_tl_d_i.a_source[1] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 INPUT
cfg_tl_d_i.a_source[5:2] No No No INPUT
cfg_tl_d_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
cfg_tl_d_i.a_size[0] No No No INPUT
cfg_tl_d_i.a_size[1] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
cfg_tl_d_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
cfg_tl_d_i.a_opcode[1:0] No No No INPUT
cfg_tl_d_i.a_opcode[2] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
cfg_tl_d_i.a_valid Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
cfg_tl_d_o.a_ready Yes Yes T4,T6,T20 Yes T4,T6,T20 OUTPUT
cfg_tl_d_o.d_error No No No OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0] Yes Yes T4,T17,T19 Yes T4,T17,T19 OUTPUT
cfg_tl_d_o.d_user.rsp_intg[1:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 OUTPUT
cfg_tl_d_o.d_user.rsp_intg[3:2] No No No OUTPUT
cfg_tl_d_o.d_user.rsp_intg[5:4] Yes Yes T17,T18,T19 Yes T4,T6,T20 OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6] No No No OUTPUT
cfg_tl_d_o.d_data[31:0] Yes Yes T4,T17,T19 Yes T4,T17,T19 OUTPUT
cfg_tl_d_o.d_sink No No No OUTPUT
cfg_tl_d_o.d_source[0] No No No OUTPUT
cfg_tl_d_o.d_source[1] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 OUTPUT
cfg_tl_d_o.d_source[5:2] No No No OUTPUT
cfg_tl_d_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
cfg_tl_d_o.d_size[0] No No No OUTPUT
cfg_tl_d_o.d_size[1] Yes Yes T17,T18,T19 Yes T4,T6,T20 OUTPUT
cfg_tl_d_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
cfg_tl_d_o.d_opcode[0] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 OUTPUT
cfg_tl_d_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
cfg_tl_d_o.d_valid Yes Yes T4,T6,T20 Yes T4,T6,T20 OUTPUT
edn_o.edn_req Yes Yes T4,T6,T20 Yes T4,T5,T6 OUTPUT
edn_i.edn_bus[31:0] Yes Yes T4,T17,T19 Yes T4,T21,T132 INPUT
edn_i.edn_fips Yes Yes T101,T103,T181 Yes T101,T103,T181 INPUT
edn_i.edn_ack Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
clk_otp_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_otp_ni Yes Yes T17,T18,T19 Yes T4,T5,T6 INPUT
icache_otp_key_o.req Yes Yes T219,T220,T221 Yes T219,T220,T221 OUTPUT
icache_otp_key_i.seed_valid Yes Yes T17,T18,T19 Yes T4,T6,T20 INPUT
icache_otp_key_i.nonce[127:0] Yes Yes T4,T6,T21 Yes T4,T6,T20 INPUT
icache_otp_key_i.key[127:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
icache_otp_key_i.ack Yes Yes T219,T220,T221 Yes T219,T220,T221 INPUT
fpga_info_i[31:0] Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T17,T161,T33 Yes T17,T161,T33 INPUT
alert_rx_i[0].ping_n Yes Yes T33,T34,T35 Yes T33,T34,T35 INPUT
alert_rx_i[0].ping_p Yes Yes T33,T34,T35 Yes T33,T34,T35 INPUT
alert_rx_i[1].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[1].ack_p Yes Yes T166,T25,T131 Yes T166,T25,T131 INPUT
alert_rx_i[1].ping_n Yes Yes T131,T33,T34 Yes T131,T33,T34 INPUT
alert_rx_i[1].ping_p Yes Yes T131,T33,T34 Yes T131,T33,T34 INPUT
alert_rx_i[2].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[2].ack_p Yes Yes T187,T188,T267 Yes T187,T188,T267 INPUT
alert_rx_i[2].ping_n Yes Yes T33,T34,T35 Yes T33,T34,T35 INPUT
alert_rx_i[2].ping_p Yes Yes T33,T34,T35 Yes T33,T34,T35 INPUT
alert_rx_i[3].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[3].ack_p Yes Yes T33,T123,T34 Yes T33,T123,T34 INPUT
alert_rx_i[3].ping_n Yes Yes T33,T34,T35 Yes T33,T34,T35 INPUT
alert_rx_i[3].ping_p Yes Yes T33,T34,T35 Yes T33,T34,T35 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T17,T161,T33 Yes T17,T161,T33 OUTPUT
alert_tx_o[1].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[1].alert_p Yes Yes T166,T25,T131 Yes T166,T25,T131 OUTPUT
alert_tx_o[2].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[2].alert_p Yes Yes T187,T188,T267 Yes T187,T188,T267 OUTPUT
alert_tx_o[3].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[3].alert_p Yes Yes T33,T123,T34 Yes T33,T123,T34 OUTPUT

*Tests covering at least one bit in the range

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 348 2 2 100.00
IF 492 2 2 100.00
IF 518 3 3 100.00
IF 796 3 3 100.00
IF 808 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 348 (fatal_core_err) ?

Branches:
-1-StatusTests
1 Covered T18,T38,T188
0 Covered T4,T5,T6


LineNo. Expression -1-: 492 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 518 if ((!rst_ni)) -2-: 522 if (double_fault)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T188,T265,T266
0 0 Covered T4,T5,T6


LineNo. Expression -1-: 796 if (reg2hw.rnd_data.re) -2-: 800 if ((edn_req && edn_ack))

Branches:
-1--2-StatusTests
1 - Covered T4,T17,T19
0 1 Covered T4,T6,T20
0 0 Covered T4,T6,T20


LineNo. Expression -1-: 808 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 22 22 100.00 15 68.18
Cover properties 0 0 0
Cover sequences 0 0 0
Total 22 22 100.00 15 68.18




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
FpvSecCmIbexFetchEnable0_A 470097304 6 0 0
FpvSecCmIbexFetchEnable1_A 470097304 24506185 0 74
FpvSecCmIbexFetchEnable2_A 470097304 64734617 0 60
FpvSecCmIbexFetchEnable3Rev_A 470097304 400669813 0 1970
FpvSecCmIbexFetchEnable3_A 470097304 400671680 0 1887
FpvSecCmIbexInstrIntgErrCheck_A 470097304 155 0 0
FpvSecCmIbexLoadRespIntgErrCheck_A 470097304 587 0 0
FpvSecCmIbexLockstepResetCountAlertCheck_A 470097304 0 0 0
FpvSecCmIbexPcMismatchCheck_A 470097304 0 0 0
FpvSecCmIbexRfEccErrCheck_A 470097304 0 0 0
FpvSecCmIbexStoreRespIntgErrCheck_A 470097304 0 0 0
FpvSecCmRegWeOnehotCheck_A 470097304 5 0 0
FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A 470097304 0 0 0
FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A 470097304 0 0 0
FpvSecCmRvCoreRegWeOnehotCheck_A 470097304 0 0 0
g_instr_intg_err_assert_signals.AssertConnected_A 992 992 0 0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A 992 992 0 0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A 992 992 0 0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A 992 992 0 0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A 992 992 0 0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A 470097304 185 0 0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A 470097304 195 0 0


FpvSecCmIbexFetchEnable0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470097304 6 0 0
T45 235746 0 0 0
T73 189644 0 0 0
T172 79138 0 0 0
T185 130146 0 0 0
T188 257609 1 0 0
T191 223629 0 0 0
T241 239260 0 0 0
T265 0 1 0 0
T266 0 1 0 0
T275 0 1 0 0
T276 0 1 0 0
T277 0 1 0 0
T278 113843 0 0 0
T279 97448 0 0 0
T280 160562 0 0 0

FpvSecCmIbexFetchEnable1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470097304 24506185 0 74
T4 134245 9923 0 0
T5 41365 41312 0 2
T6 197158 9923 0 0
T17 221235 41081 0 0
T18 219998 19846 0 0
T19 261468 41104 0 0
T20 218705 9931 0 0
T21 663418 9931 0 0
T23 0 0 0 2
T24 0 0 0 2
T73 0 0 0 2
T74 0 0 0 2
T79 0 0 0 2
T80 0 0 0 2
T91 217010 9927 0 0
T132 212915 9931 0 0
T217 0 0 0 2
T281 0 0 0 2
T282 0 0 0 2

FpvSecCmIbexFetchEnable2_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470097304 64734617 0 60
T4 134245 34775 0 0
T5 41365 34775 0 0
T6 197158 34775 0 0
T17 221235 69554 0 0
T18 219998 69555 0 0
T19 261468 69551 0 0
T20 218705 34775 0 0
T21 663418 34775 0 0
T23 0 0 0 2
T24 0 0 0 2
T28 0 0 0 2
T73 0 0 0 2
T74 0 0 0 2
T79 0 0 0 2
T91 217010 34775 0 0
T132 212915 34775 0 0
T150 0 0 0 2
T168 0 0 0 2
T217 0 0 0 2
T218 0 0 0 2

FpvSecCmIbexFetchEnable3Rev_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470097304 400669813 0 1970
T4 134245 130763 0 2
T5 41365 0 0 2
T6 197158 162329 0 2
T17 221235 130336 0 2
T18 219998 150331 0 2
T19 261468 170545 0 2
T20 218705 183865 0 2
T21 663418 628578 0 2
T31 0 171088 0 0
T91 217010 182174 0 2
T132 212915 178075 0 2

FpvSecCmIbexFetchEnable3_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470097304 400671680 0 1887
T4 134245 130763 0 2
T5 41365 0 0 0
T6 197158 162330 0 2
T17 221235 130338 0 2
T18 219998 150333 0 2
T19 261468 170546 0 2
T20 218705 183866 0 2
T21 663418 628579 0 2
T31 0 171090 0 2
T91 217010 182175 0 2
T132 212915 178076 0 2

FpvSecCmIbexInstrIntgErrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470097304 155 0 0
T84 167235 0 0 0
T138 0 77 0 0
T216 424187 0 0 0
T263 276057 78 0 0
T264 299433 0 0 0
T283 95815 0 0 0
T284 354020 0 0 0
T285 288317 0 0 0
T286 361548 0 0 0
T287 60218 0 0 0
T288 183967 0 0 0

FpvSecCmIbexLoadRespIntgErrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470097304 587 0 0
T23 114721 0 0 0
T79 54139 0 0 0
T87 321816 0 0 0
T88 290079 0 0 0
T94 0 32 0 0
T95 0 31 0 0
T96 0 32 0 0
T102 216886 0 0 0
T152 61484 0 0 0
T171 74171 0 0 0
T187 191367 32 0 0
T231 125514 0 0 0
T264 0 1 0 0
T289 0 32 0 0
T290 0 32 0 0
T291 0 99 0 0
T292 0 31 0 0
T293 0 32 0 0
T294 42238 0 0 0

FpvSecCmIbexLockstepResetCountAlertCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470097304 0 0 0

FpvSecCmIbexPcMismatchCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470097304 0 0 0

FpvSecCmIbexRfEccErrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470097304 0 0 0

FpvSecCmIbexStoreRespIntgErrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470097304 0 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470097304 5 0 0
T26 872290 0 0 0
T48 186091 0 0 0
T110 315763 0 0 0
T170 275093 0 0 0
T267 262270 1 0 0
T268 0 1 0 0
T269 0 1 0 0
T295 0 1 0 0
T296 0 1 0 0
T297 151438 0 0 0
T298 229682 0 0 0
T299 237363 0 0 0
T300 662936 0 0 0
T301 265229 0 0 0

FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470097304 0 0 0

FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470097304 0 0 0

FpvSecCmRvCoreRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470097304 0 0 0

g_instr_intg_err_assert_signals.AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 992 992 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T91 1 1 0 0
T132 1 1 0 0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 992 992 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T91 1 1 0 0
T132 1 1 0 0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 992 992 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T91 1 1 0 0
T132 1 1 0 0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 992 992 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T91 1 1 0 0
T132 1 1 0 0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 992 992 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T91 1 1 0 0
T132 1 1 0 0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470097304 185 0 0
T30 281838 0 0 0
T182 166829 0 0 0
T204 274625 0 0 0
T219 69565 28 0 0
T220 90942 33 0 0
T221 0 49 0 0
T302 0 8 0 0
T303 0 33 0 0
T304 0 34 0 0
T305 500836 0 0 0
T306 244134 0 0 0
T307 106667 0 0 0
T308 889506 0 0 0
T309 102304 0 0 0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470097304 195 0 0
T30 281838 0 0 0
T182 166829 0 0 0
T189 0 16 0 0
T190 0 16 0 0
T204 274625 0 0 0
T219 69565 7 0 0
T220 90942 42 0 0
T221 0 12 0 0
T302 0 2 0 0
T303 0 42 0 0
T304 0 42 0 0
T305 500836 0 0 0
T306 244134 0 0 0
T307 106667 0 0 0
T308 889506 0 0 0
T309 102304 0 0 0
T310 0 16 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%