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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 95.47 93.78 95.32 94.52 97.53 99.61


Total test records in report: 2936
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T254 /workspace/coverage/default/27.chip_sw_all_escalation_resets.1969438892 Jul 31 08:42:23 PM PDT 24 Jul 31 08:54:05 PM PDT 24 6219747400 ps
T931 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.4235428798 Jul 31 08:39:04 PM PDT 24 Jul 31 09:36:46 PM PDT 24 15591441438 ps
T343 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.2325220929 Jul 31 08:29:15 PM PDT 24 Jul 31 08:40:31 PM PDT 24 4160215400 ps
T187 /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.1178150572 Jul 31 08:12:57 PM PDT 24 Jul 31 08:15:41 PM PDT 24 2937438961 ps
T311 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.2045612335 Jul 31 08:16:11 PM PDT 24 Jul 31 08:32:48 PM PDT 24 12210763950 ps
T221 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.4154019345 Jul 31 08:15:03 PM PDT 24 Jul 31 08:29:57 PM PDT 24 5440189264 ps
T307 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3055524859 Jul 31 08:34:23 PM PDT 24 Jul 31 08:42:37 PM PDT 24 5066585180 ps
T443 /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2420049045 Jul 31 08:38:31 PM PDT 24 Jul 31 10:23:28 PM PDT 24 27013173546 ps
T932 /workspace/coverage/default/2.chip_sw_plic_sw_irq.3899018002 Jul 31 08:35:38 PM PDT 24 Jul 31 08:40:33 PM PDT 24 3399515076 ps
T216 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2305725632 Jul 31 08:12:05 PM PDT 24 Jul 31 08:46:18 PM PDT 24 24574843002 ps
T236 /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.2949872080 Jul 31 08:21:01 PM PDT 24 Jul 31 09:21:40 PM PDT 24 15605447892 ps
T933 /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.2871388226 Jul 31 08:29:55 PM PDT 24 Jul 31 08:40:35 PM PDT 24 6781980339 ps
T251 /workspace/coverage/default/82.chip_sw_all_escalation_resets.1122924244 Jul 31 08:44:59 PM PDT 24 Jul 31 08:54:27 PM PDT 24 4914831580 ps
T91 /workspace/coverage/default/2.chip_sw_gpio_smoketest.3757828773 Jul 31 08:35:35 PM PDT 24 Jul 31 08:39:46 PM PDT 24 2873572394 ps
T61 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.502983543 Jul 31 08:34:08 PM PDT 24 Jul 31 08:58:36 PM PDT 24 24681732416 ps
T240 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.1599209604 Jul 31 08:25:21 PM PDT 24 Jul 31 08:55:41 PM PDT 24 17023551841 ps
T289 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.478521153 Jul 31 08:17:05 PM PDT 24 Jul 31 08:26:28 PM PDT 24 5111331658 ps
T934 /workspace/coverage/default/0.rom_keymgr_functest.2876519461 Jul 31 08:15:53 PM PDT 24 Jul 31 08:22:41 PM PDT 24 4961843100 ps
T13 /workspace/coverage/default/2.chip_sw_power_virus.583871867 Jul 31 08:38:55 PM PDT 24 Jul 31 09:02:38 PM PDT 24 5598772508 ps
T188 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.1915439969 Jul 31 08:15:08 PM PDT 24 Jul 31 08:51:44 PM PDT 24 26483833600 ps
T338 /workspace/coverage/default/1.chip_sw_uart_tx_rx.3405228041 Jul 31 08:22:30 PM PDT 24 Jul 31 08:35:13 PM PDT 24 4238630128 ps
T336 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.597776588 Jul 31 08:32:09 PM PDT 24 Jul 31 09:08:26 PM PDT 24 7517127496 ps
T217 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.2477462067 Jul 31 08:31:36 PM PDT 24 Jul 31 09:02:12 PM PDT 24 23951403240 ps
T935 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.1410602951 Jul 31 08:32:09 PM PDT 24 Jul 31 09:25:17 PM PDT 24 14813978314 ps
T238 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.753367233 Jul 31 08:35:12 PM PDT 24 Jul 31 09:02:25 PM PDT 24 24921357109 ps
T765 /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2255696754 Jul 31 08:41:49 PM PDT 24 Jul 31 08:47:47 PM PDT 24 3829027280 ps
T936 /workspace/coverage/default/13.chip_sw_all_escalation_resets.3212308424 Jul 31 08:42:14 PM PDT 24 Jul 31 08:50:54 PM PDT 24 4387779080 ps
T937 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.3341168245 Jul 31 08:18:02 PM PDT 24 Jul 31 08:30:46 PM PDT 24 4399367652 ps
T90 /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1071797528 Jul 31 08:21:39 PM PDT 24 Jul 31 11:26:33 PM PDT 24 255051355736 ps
T756 /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2933191101 Jul 31 08:42:54 PM PDT 24 Jul 31 08:48:49 PM PDT 24 3942560342 ps
T258 /workspace/coverage/default/2.chip_sw_rv_timer_irq.2198596573 Jul 31 08:29:17 PM PDT 24 Jul 31 08:34:43 PM PDT 24 3395902690 ps
T212 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.548024194 Jul 31 08:18:23 PM PDT 24 Jul 31 11:52:59 PM PDT 24 64823692410 ps
T938 /workspace/coverage/default/1.chip_sw_hmac_enc.2635276650 Jul 31 08:22:56 PM PDT 24 Jul 31 08:27:46 PM PDT 24 2570550250 ps
T939 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.1975463343 Jul 31 08:22:53 PM PDT 24 Jul 31 08:27:45 PM PDT 24 2868334072 ps
T313 /workspace/coverage/default/59.chip_sw_all_escalation_resets.3900279684 Jul 31 08:46:15 PM PDT 24 Jul 31 08:56:26 PM PDT 24 5546287200 ps
T940 /workspace/coverage/default/0.chip_sw_hmac_oneshot.4123674099 Jul 31 08:12:50 PM PDT 24 Jul 31 08:17:28 PM PDT 24 2605676074 ps
T775 /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1672461936 Jul 31 08:43:56 PM PDT 24 Jul 31 08:51:32 PM PDT 24 3588355240 ps
T811 /workspace/coverage/default/31.chip_sw_all_escalation_resets.3473643844 Jul 31 08:42:50 PM PDT 24 Jul 31 08:55:08 PM PDT 24 6162395860 ps
T174 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2365236050 Jul 31 08:11:39 PM PDT 24 Jul 31 08:13:21 PM PDT 24 2312185336 ps
T755 /workspace/coverage/default/1.chip_sw_edn_kat.604122756 Jul 31 08:21:39 PM PDT 24 Jul 31 08:32:47 PM PDT 24 3564782120 ps
T265 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.631633783 Jul 31 08:20:55 PM PDT 24 Jul 31 08:31:04 PM PDT 24 5345688800 ps
T941 /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.3005347784 Jul 31 08:35:07 PM PDT 24 Jul 31 09:10:52 PM PDT 24 30579286800 ps
T942 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3912989379 Jul 31 08:14:23 PM PDT 24 Jul 31 08:25:35 PM PDT 24 3999317840 ps
T943 /workspace/coverage/default/0.chip_sw_example_rom.21488289 Jul 31 08:12:20 PM PDT 24 Jul 31 08:14:13 PM PDT 24 2499614964 ps
T944 /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.2465706992 Jul 31 08:20:39 PM PDT 24 Jul 31 09:06:51 PM PDT 24 10877658912 ps
T149 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3170027247 Jul 31 08:34:28 PM PDT 24 Jul 31 08:51:00 PM PDT 24 8463725108 ps
T331 /workspace/coverage/default/0.chip_plic_all_irqs_0.2023727872 Jul 31 08:16:12 PM PDT 24 Jul 31 08:38:44 PM PDT 24 6351830336 ps
T945 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1104462819 Jul 31 08:23:23 PM PDT 24 Jul 31 08:39:59 PM PDT 24 11722474437 ps
T946 /workspace/coverage/default/1.chip_sw_edn_sw_mode.850176844 Jul 31 08:22:50 PM PDT 24 Jul 31 08:58:06 PM PDT 24 9291662748 ps
T252 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.3427336211 Jul 31 08:31:06 PM PDT 24 Jul 31 08:39:19 PM PDT 24 4850521878 ps
T747 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2591602891 Jul 31 08:13:57 PM PDT 24 Jul 31 08:20:06 PM PDT 24 4026082956 ps
T745 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.4092143030 Jul 31 08:38:46 PM PDT 24 Jul 31 08:45:48 PM PDT 24 4504334432 ps
T947 /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3153238526 Jul 31 08:23:11 PM PDT 24 Jul 31 08:50:29 PM PDT 24 10802577896 ps
T948 /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.101874765 Jul 31 08:13:51 PM PDT 24 Jul 31 08:24:03 PM PDT 24 7856550890 ps
T949 /workspace/coverage/default/4.chip_tap_straps_dev.3168420591 Jul 31 08:37:21 PM PDT 24 Jul 31 08:41:02 PM PDT 24 4043782806 ps
T749 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1238172409 Jul 31 08:44:08 PM PDT 24 Jul 31 08:50:51 PM PDT 24 3980903904 ps
T314 /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2655817738 Jul 31 08:39:00 PM PDT 24 Jul 31 08:48:34 PM PDT 24 3895465070 ps
T950 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.2974298626 Jul 31 08:28:36 PM PDT 24 Jul 31 08:37:18 PM PDT 24 4240938628 ps
T951 /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.1609196997 Jul 31 08:23:24 PM PDT 24 Jul 31 08:32:16 PM PDT 24 4701382076 ps
T952 /workspace/coverage/default/1.chip_sw_aes_entropy.2712869135 Jul 31 08:21:16 PM PDT 24 Jul 31 08:25:51 PM PDT 24 3073861416 ps
T812 /workspace/coverage/default/38.chip_sw_all_escalation_resets.4080337605 Jul 31 08:42:32 PM PDT 24 Jul 31 08:51:45 PM PDT 24 5622923576 ps
T953 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1805729028 Jul 31 08:33:13 PM PDT 24 Jul 31 08:59:27 PM PDT 24 7960603428 ps
T954 /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.227306218 Jul 31 08:38:19 PM PDT 24 Jul 31 08:56:48 PM PDT 24 12719615560 ps
T955 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1462741057 Jul 31 08:20:48 PM PDT 24 Jul 31 08:54:09 PM PDT 24 21917766822 ps
T757 /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2858792245 Jul 31 08:43:29 PM PDT 24 Jul 31 08:49:53 PM PDT 24 3765910088 ps
T348 /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.221726364 Jul 31 08:23:54 PM PDT 24 Jul 31 08:30:13 PM PDT 24 3507089928 ps
T956 /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.1089216976 Jul 31 08:19:02 PM PDT 24 Jul 31 09:05:04 PM PDT 24 25360001056 ps
T957 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.307413469 Jul 31 08:37:30 PM PDT 24 Jul 31 08:41:28 PM PDT 24 2438411232 ps
T958 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.3118882396 Jul 31 08:22:25 PM PDT 24 Jul 31 09:39:25 PM PDT 24 13746924391 ps
T959 /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.2499934537 Jul 31 08:17:48 PM PDT 24 Jul 31 08:21:23 PM PDT 24 2790569852 ps
T14 /workspace/coverage/default/1.chip_sw_power_virus.566132688 Jul 31 08:31:56 PM PDT 24 Jul 31 08:58:51 PM PDT 24 5944848344 ps
T241 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.224586729 Jul 31 08:15:37 PM PDT 24 Jul 31 09:51:05 PM PDT 24 50546298750 ps
T960 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3411629112 Jul 31 08:22:32 PM PDT 24 Jul 31 09:30:12 PM PDT 24 15035000150 ps
T329 /workspace/coverage/default/0.chip_plic_all_irqs_20.2083441115 Jul 31 08:18:37 PM PDT 24 Jul 31 08:32:12 PM PDT 24 4710217708 ps
T109 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3091180230 Jul 31 08:14:20 PM PDT 24 Jul 31 08:22:22 PM PDT 24 6924564864 ps
T760 /workspace/coverage/default/24.chip_sw_all_escalation_resets.673922421 Jul 31 08:41:57 PM PDT 24 Jul 31 08:53:01 PM PDT 24 5166235320 ps
T961 /workspace/coverage/default/0.chip_sw_aes_idle.1413746265 Jul 31 08:13:37 PM PDT 24 Jul 31 08:18:42 PM PDT 24 3191160792 ps
T344 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.574880454 Jul 31 08:17:56 PM PDT 24 Jul 31 08:31:09 PM PDT 24 5307911352 ps
T165 /workspace/coverage/default/2.rom_raw_unlock.1250734957 Jul 31 08:36:00 PM PDT 24 Jul 31 08:41:47 PM PDT 24 6303828991 ps
T750 /workspace/coverage/default/90.chip_sw_all_escalation_resets.2275722042 Jul 31 08:45:23 PM PDT 24 Jul 31 08:53:20 PM PDT 24 5119275840 ps
T962 /workspace/coverage/default/1.chip_sw_clkmgr_jitter.3123653360 Jul 31 08:24:33 PM PDT 24 Jul 31 08:29:28 PM PDT 24 2837976785 ps
T751 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.521638453 Jul 31 08:43:04 PM PDT 24 Jul 31 08:48:44 PM PDT 24 3654169050 ps
T127 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.2943832790 Jul 31 08:31:29 PM PDT 24 Jul 31 08:48:00 PM PDT 24 6844931785 ps
T244 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.1697860940 Jul 31 08:14:24 PM PDT 24 Jul 31 09:54:01 PM PDT 24 51269535093 ps
T76 /workspace/coverage/default/0.chip_sw_usbdev_pullup.2385347688 Jul 31 08:13:36 PM PDT 24 Jul 31 08:17:52 PM PDT 24 2892108072 ps
T754 /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2478716525 Jul 31 08:45:17 PM PDT 24 Jul 31 08:51:19 PM PDT 24 4017256520 ps
T366 /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2455958657 Jul 31 08:21:16 PM PDT 24 Jul 31 08:50:04 PM PDT 24 13382782996 ps
T963 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1158107527 Jul 31 08:22:03 PM PDT 24 Jul 31 08:31:29 PM PDT 24 4303413994 ps
T964 /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.606476272 Jul 31 08:41:38 PM PDT 24 Jul 31 08:50:31 PM PDT 24 4600104676 ps
T965 /workspace/coverage/default/2.chip_sw_aes_entropy.3231004124 Jul 31 08:32:22 PM PDT 24 Jul 31 08:37:06 PM PDT 24 3626790666 ps
T761 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.753999878 Jul 31 08:37:32 PM PDT 24 Jul 31 08:43:43 PM PDT 24 3576987004 ps
T43 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.2417185821 Jul 31 08:17:01 PM PDT 24 Jul 31 08:23:15 PM PDT 24 4454877761 ps
T966 /workspace/coverage/default/3.chip_tap_straps_prod.3504111267 Jul 31 08:37:55 PM PDT 24 Jul 31 08:40:39 PM PDT 24 2701064153 ps
T290 /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.4057968406 Jul 31 08:14:05 PM PDT 24 Jul 31 08:22:05 PM PDT 24 3639038840 ps
T967 /workspace/coverage/default/1.chip_sw_hmac_smoketest.2298590169 Jul 31 08:27:21 PM PDT 24 Jul 31 08:32:47 PM PDT 24 3365929740 ps
T387 /workspace/coverage/default/0.chip_sw_edn_boot_mode.3225311079 Jul 31 08:13:38 PM PDT 24 Jul 31 08:22:50 PM PDT 24 3033080988 ps
T968 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3869846067 Jul 31 08:20:54 PM PDT 24 Jul 31 09:25:15 PM PDT 24 14268744886 ps
T52 /workspace/coverage/default/1.chip_sw_alert_test.1251449249 Jul 31 08:20:25 PM PDT 24 Jul 31 08:26:02 PM PDT 24 3513907800 ps
T969 /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.1867910532 Jul 31 08:39:09 PM PDT 24 Jul 31 08:42:17 PM PDT 24 3100854410 ps
T970 /workspace/coverage/default/2.chip_sw_kmac_idle.2568925346 Jul 31 08:31:55 PM PDT 24 Jul 31 08:37:40 PM PDT 24 3496911344 ps
T169 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2752440115 Jul 31 08:21:07 PM PDT 24 Jul 31 08:44:30 PM PDT 24 11765035712 ps
T971 /workspace/coverage/default/1.rom_e2e_asm_init_rma.1120610084 Jul 31 08:36:40 PM PDT 24 Jul 31 09:31:05 PM PDT 24 14678539382 ps
T972 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.3023000428 Jul 31 08:31:54 PM PDT 24 Jul 31 10:02:22 PM PDT 24 22173528418 ps
T196 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1221884511 Jul 31 08:15:39 PM PDT 24 Jul 31 08:21:18 PM PDT 24 2975062660 ps
T395 /workspace/coverage/default/79.chip_sw_all_escalation_resets.99813477 Jul 31 08:47:01 PM PDT 24 Jul 31 08:56:27 PM PDT 24 5882209244 ps
T359 /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3809171939 Jul 31 08:30:22 PM PDT 24 Jul 31 08:38:48 PM PDT 24 18466373374 ps
T77 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1171991010 Jul 31 08:13:19 PM PDT 24 Jul 31 08:20:17 PM PDT 24 3568365076 ps
T396 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.2109804993 Jul 31 08:32:06 PM PDT 24 Jul 31 09:01:48 PM PDT 24 9317670296 ps
T397 /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2673682533 Jul 31 08:46:46 PM PDT 24 Jul 31 08:52:01 PM PDT 24 3856334260 ps
T398 /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.4152442084 Jul 31 08:24:24 PM PDT 24 Jul 31 08:31:50 PM PDT 24 3141385912 ps
T197 /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.1990777828 Jul 31 08:34:15 PM PDT 24 Jul 31 08:38:43 PM PDT 24 2848652816 ps
T399 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1324061997 Jul 31 08:21:19 PM PDT 24 Jul 31 09:30:59 PM PDT 24 15868004760 ps
T218 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.1643470261 Jul 31 08:15:13 PM PDT 24 Jul 31 08:19:56 PM PDT 24 3201481331 ps
T302 /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.3483704131 Jul 31 08:16:49 PM PDT 24 Jul 31 08:21:10 PM PDT 24 2910100413 ps
T772 /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2262783764 Jul 31 08:42:32 PM PDT 24 Jul 31 08:49:26 PM PDT 24 4298859150 ps
T973 /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.2689484810 Jul 31 08:29:45 PM PDT 24 Jul 31 08:35:27 PM PDT 24 2884183027 ps
T389 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.232899659 Jul 31 08:22:13 PM PDT 24 Jul 31 09:56:31 PM PDT 24 24558390680 ps
T518 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3743573844 Jul 31 08:17:13 PM PDT 24 Jul 31 08:32:20 PM PDT 24 5023726850 ps
T974 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1636282453 Jul 31 08:27:56 PM PDT 24 Jul 31 08:54:17 PM PDT 24 8463782426 ps
T110 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3815672584 Jul 31 08:17:14 PM PDT 24 Jul 31 08:47:23 PM PDT 24 24313917336 ps
T975 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1547058769 Jul 31 08:15:11 PM PDT 24 Jul 31 08:25:37 PM PDT 24 5033989052 ps
T213 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.401773594 Jul 31 08:13:59 PM PDT 24 Jul 31 11:58:55 PM PDT 24 78621022820 ps
T976 /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.847511202 Jul 31 08:21:02 PM PDT 24 Jul 31 08:27:46 PM PDT 24 6111292312 ps
T367 /workspace/coverage/default/2.chip_sw_aon_timer_irq.1725336630 Jul 31 08:31:08 PM PDT 24 Jul 31 08:39:49 PM PDT 24 3919967572 ps
T341 /workspace/coverage/default/2.chip_plic_all_irqs_20.3308747209 Jul 31 08:33:22 PM PDT 24 Jul 31 08:47:55 PM PDT 24 4304579084 ps
T977 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1533950861 Jul 31 08:26:48 PM PDT 24 Jul 31 08:31:35 PM PDT 24 2730054494 ps
T978 /workspace/coverage/default/0.chip_sw_uart_smoketest.641059172 Jul 31 08:17:36 PM PDT 24 Jul 31 08:21:27 PM PDT 24 2698912260 ps
T732 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.377673070 Jul 31 08:46:06 PM PDT 24 Jul 31 08:51:26 PM PDT 24 3503077562 ps
T979 /workspace/coverage/default/0.chip_sw_edn_kat.438342059 Jul 31 08:15:04 PM PDT 24 Jul 31 08:27:53 PM PDT 24 3461083376 ps
T980 /workspace/coverage/default/1.chip_sw_kmac_idle.2535184473 Jul 31 08:22:23 PM PDT 24 Jul 31 08:25:27 PM PDT 24 2266146168 ps
T981 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.3952722912 Jul 31 08:24:09 PM PDT 24 Jul 31 08:58:23 PM PDT 24 8838317744 ps
T982 /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.934508866 Jul 31 08:33:34 PM PDT 24 Jul 31 08:42:17 PM PDT 24 4068899926 ps
T816 /workspace/coverage/default/34.chip_sw_all_escalation_resets.2859420497 Jul 31 08:42:56 PM PDT 24 Jul 31 08:54:39 PM PDT 24 4631946066 ps
T983 /workspace/coverage/default/1.chip_sw_rv_timer_irq.3205081371 Jul 31 08:20:32 PM PDT 24 Jul 31 08:25:36 PM PDT 24 3208970336 ps
T984 /workspace/coverage/default/0.chip_sw_usbdev_vbus.3692223875 Jul 31 08:12:03 PM PDT 24 Jul 31 08:16:27 PM PDT 24 3149587760 ps
T303 /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.486796761 Jul 31 08:34:59 PM PDT 24 Jul 31 08:40:20 PM PDT 24 2726694243 ps
T985 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3102961950 Jul 31 08:21:35 PM PDT 24 Jul 31 09:33:01 PM PDT 24 15297634248 ps
T986 /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.3824440462 Jul 31 08:30:02 PM PDT 24 Jul 31 09:08:26 PM PDT 24 36527468810 ps
T173 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1557938723 Jul 31 08:31:56 PM PDT 24 Jul 31 08:35:09 PM PDT 24 2481182893 ps
T291 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1235044445 Jul 31 08:13:45 PM PDT 24 Jul 31 08:22:32 PM PDT 24 3416652785 ps
T987 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2008848812 Jul 31 08:14:23 PM PDT 24 Jul 31 08:36:51 PM PDT 24 6164769900 ps
T988 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2510518878 Jul 31 08:37:40 PM PDT 24 Jul 31 08:44:07 PM PDT 24 6642866760 ps
T740 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.678311207 Jul 31 08:43:09 PM PDT 24 Jul 31 08:49:07 PM PDT 24 3355258298 ps
T989 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.2398905665 Jul 31 08:22:42 PM PDT 24 Jul 31 09:12:57 PM PDT 24 11468065360 ps
T990 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.3422927142 Jul 31 08:16:33 PM PDT 24 Jul 31 08:21:01 PM PDT 24 3381863869 ps
T219 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.2908544715 Jul 31 08:15:00 PM PDT 24 Jul 31 08:24:06 PM PDT 24 4797837004 ps
T128 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.686546914 Jul 31 08:21:53 PM PDT 24 Jul 31 08:39:54 PM PDT 24 7205692615 ps
T991 /workspace/coverage/default/2.chip_sw_example_manufacturer.2923654050 Jul 31 08:28:03 PM PDT 24 Jul 31 08:31:38 PM PDT 24 2298580144 ps
T992 /workspace/coverage/default/1.chip_sw_flash_crash_alert.3628588049 Jul 31 08:26:21 PM PDT 24 Jul 31 08:40:22 PM PDT 24 4693994760 ps
T993 /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.3543553233 Jul 31 08:17:25 PM PDT 24 Jul 31 08:21:25 PM PDT 24 3167413362 ps
T777 /workspace/coverage/default/37.chip_sw_all_escalation_resets.2217868385 Jul 31 08:43:56 PM PDT 24 Jul 31 08:53:49 PM PDT 24 4341230638 ps
T371 /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3363519087 Jul 31 08:36:10 PM PDT 24 Jul 31 08:44:40 PM PDT 24 5573276120 ps
T994 /workspace/coverage/default/0.chip_sw_aes_masking_off.3202473259 Jul 31 08:14:43 PM PDT 24 Jul 31 08:21:10 PM PDT 24 3416022021 ps
T995 /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3863947681 Jul 31 08:44:02 PM PDT 24 Jul 31 08:53:40 PM PDT 24 4256529990 ps
T121 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1358319004 Jul 31 08:15:53 PM PDT 24 Jul 31 08:22:58 PM PDT 24 3426289670 ps
T996 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2178483134 Jul 31 08:25:45 PM PDT 24 Jul 31 08:31:48 PM PDT 24 3323363840 ps
T997 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.1877998986 Jul 31 08:30:03 PM PDT 24 Jul 31 08:40:40 PM PDT 24 4146032288 ps
T998 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1774198121 Jul 31 08:13:42 PM PDT 24 Jul 31 08:21:37 PM PDT 24 4852378962 ps
T748 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.638046600 Jul 31 08:11:53 PM PDT 24 Jul 31 08:24:23 PM PDT 24 5872050516 ps
T828 /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1867176741 Jul 31 08:41:54 PM PDT 24 Jul 31 08:48:38 PM PDT 24 3809369248 ps
T999 /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.461239072 Jul 31 08:19:20 PM PDT 24 Jul 31 08:26:05 PM PDT 24 4448286504 ps
T1000 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.3566443491 Jul 31 08:23:20 PM PDT 24 Jul 31 08:36:56 PM PDT 24 5479815880 ps
T1001 /workspace/coverage/default/2.chip_sw_edn_sw_mode.1670158529 Jul 31 08:31:51 PM PDT 24 Jul 31 09:01:05 PM PDT 24 8939761988 ps
T1002 /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.4006217074 Jul 31 08:39:40 PM PDT 24 Jul 31 09:34:08 PM PDT 24 15370650424 ps
T690 /workspace/coverage/default/0.chip_sw_power_sleep_load.2663086203 Jul 31 08:14:30 PM PDT 24 Jul 31 08:19:37 PM PDT 24 4717571852 ps
T1003 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2723752466 Jul 31 08:14:29 PM PDT 24 Jul 31 08:24:55 PM PDT 24 4104377608 ps
T1004 /workspace/coverage/default/2.chip_sw_csrng_smoketest.1337298946 Jul 31 08:37:09 PM PDT 24 Jul 31 08:41:37 PM PDT 24 2861921884 ps
T1005 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.2926139148 Jul 31 08:28:01 PM PDT 24 Jul 31 08:34:12 PM PDT 24 3828906900 ps
T327 /workspace/coverage/default/1.chip_plic_all_irqs_0.1671442576 Jul 31 08:23:56 PM PDT 24 Jul 31 08:45:42 PM PDT 24 6448748038 ps
T1006 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2018155045 Jul 31 08:15:47 PM PDT 24 Jul 31 08:23:16 PM PDT 24 5281387524 ps
T296 /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2390656360 Jul 31 08:45:54 PM PDT 24 Jul 31 08:54:47 PM PDT 24 3612547884 ps
T1007 /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.1002724327 Jul 31 08:28:40 PM PDT 24 Jul 31 08:37:45 PM PDT 24 5533915400 ps
T1008 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.143637278 Jul 31 08:13:15 PM PDT 24 Jul 31 08:20:23 PM PDT 24 3880027956 ps
T1009 /workspace/coverage/default/0.rom_e2e_asm_init_dev.2776858067 Jul 31 08:22:38 PM PDT 24 Jul 31 09:36:24 PM PDT 24 15264730271 ps
T278 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.1921926361 Jul 31 08:14:45 PM PDT 24 Jul 31 08:27:04 PM PDT 24 5529482218 ps
T281 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2952491862 Jul 31 08:21:41 PM PDT 24 Jul 31 09:44:08 PM PDT 24 18346539672 ps
T282 /workspace/coverage/default/0.chip_sw_example_flash.2839350637 Jul 31 08:11:17 PM PDT 24 Jul 31 08:15:26 PM PDT 24 2803842684 ps
T283 /workspace/coverage/default/35.chip_sw_all_escalation_resets.3408821919 Jul 31 08:41:32 PM PDT 24 Jul 31 08:54:16 PM PDT 24 4750682844 ps
T284 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3956825374 Jul 31 08:30:23 PM PDT 24 Jul 31 08:32:25 PM PDT 24 2460875159 ps
T198 /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.3565969528 Jul 31 08:31:37 PM PDT 24 Jul 31 08:38:27 PM PDT 24 5101061192 ps
T285 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.820911172 Jul 31 08:20:54 PM PDT 24 Jul 31 08:29:13 PM PDT 24 6191338260 ps
T286 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1925715291 Jul 31 08:13:01 PM PDT 24 Jul 31 08:39:38 PM PDT 24 10591905297 ps
T287 /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.2873425012 Jul 31 08:34:42 PM PDT 24 Jul 31 08:44:03 PM PDT 24 4783822692 ps
T150 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.1119502384 Jul 31 08:39:36 PM PDT 24 Jul 31 08:56:55 PM PDT 24 8668999316 ps
T738 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.95144779 Jul 31 08:44:20 PM PDT 24 Jul 31 08:52:40 PM PDT 24 4412406112 ps
T1010 /workspace/coverage/default/2.rom_e2e_self_hash.3739405997 Jul 31 08:39:33 PM PDT 24 Jul 31 10:22:14 PM PDT 24 27340564242 ps
T1011 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.2460346482 Jul 31 08:19:20 PM PDT 24 Jul 31 08:29:46 PM PDT 24 4584135798 ps
T1012 /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.94745689 Jul 31 08:19:28 PM PDT 24 Jul 31 08:31:57 PM PDT 24 5658414668 ps
T189 /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1572643345 Jul 31 08:13:01 PM PDT 24 Jul 31 08:18:29 PM PDT 24 3120529398 ps
T1013 /workspace/coverage/default/0.chip_sw_edn_auto_mode.319795081 Jul 31 08:13:25 PM PDT 24 Jul 31 08:28:17 PM PDT 24 3739169488 ps
T1014 /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.3707856255 Jul 31 08:29:54 PM PDT 24 Jul 31 08:36:26 PM PDT 24 3211926274 ps
T346 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.805576990 Jul 31 08:20:31 PM PDT 24 Jul 31 08:29:34 PM PDT 24 4049261450 ps
T388 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.4257115752 Jul 31 08:22:01 PM PDT 24 Jul 31 08:33:15 PM PDT 24 8130188137 ps
T35 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3808315788 Jul 31 08:31:30 PM PDT 24 Jul 31 08:36:17 PM PDT 24 3294531914 ps
T172 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2816047586 Jul 31 08:33:32 PM PDT 24 Jul 31 08:59:57 PM PDT 24 12660688616 ps
T25 /workspace/coverage/default/0.chip_sw_usbdev_dpi.3117759431 Jul 31 08:13:41 PM PDT 24 Jul 31 09:08:06 PM PDT 24 12130306116 ps
T801 /workspace/coverage/default/23.chip_sw_all_escalation_resets.2917080651 Jul 31 08:41:26 PM PDT 24 Jul 31 08:51:25 PM PDT 24 5618637208 ps
T818 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3303201806 Jul 31 08:43:12 PM PDT 24 Jul 31 08:47:51 PM PDT 24 3315717368 ps
T406 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2922217145 Jul 31 08:33:52 PM PDT 24 Jul 31 08:42:34 PM PDT 24 9555703334 ps
T214 /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.3739964891 Jul 31 08:22:36 PM PDT 24 Aug 01 12:17:39 AM PDT 24 77583256200 ps
T752 /workspace/coverage/default/66.chip_sw_all_escalation_resets.531520094 Jul 31 08:45:25 PM PDT 24 Jul 31 08:55:01 PM PDT 24 4894947030 ps
T1015 /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3756980172 Jul 31 08:18:48 PM PDT 24 Jul 31 09:40:24 PM PDT 24 44286672896 ps
T1016 /workspace/coverage/default/0.chip_sw_hmac_smoketest.172073207 Jul 31 08:21:04 PM PDT 24 Jul 31 08:28:26 PM PDT 24 3378430868 ps
T243 /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.2086513928 Jul 31 08:19:37 PM PDT 24 Jul 31 09:48:34 PM PDT 24 46915461785 ps
T1017 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3819789438 Jul 31 08:25:19 PM PDT 24 Jul 31 09:06:03 PM PDT 24 11332087000 ps
T737 /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2119549834 Jul 31 08:42:19 PM PDT 24 Jul 31 08:49:38 PM PDT 24 3951482440 ps
T1018 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.3154215142 Jul 31 08:22:30 PM PDT 24 Jul 31 08:26:55 PM PDT 24 2448272746 ps
T279 /workspace/coverage/default/3.chip_sw_data_integrity_escalation.757247821 Jul 31 08:36:12 PM PDT 24 Jul 31 08:53:08 PM PDT 24 6644186270 ps
T1019 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.1893361957 Jul 31 08:12:35 PM PDT 24 Jul 31 08:35:07 PM PDT 24 6017567296 ps
T95 /workspace/coverage/default/9.chip_sw_all_escalation_resets.3201472595 Jul 31 08:37:57 PM PDT 24 Jul 31 08:49:32 PM PDT 24 5014545088 ps
T233 /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.1659659841 Jul 31 08:23:22 PM PDT 24 Jul 31 09:06:22 PM PDT 24 12841820380 ps
T830 /workspace/coverage/default/43.chip_sw_all_escalation_resets.3169871057 Jul 31 08:42:41 PM PDT 24 Jul 31 08:52:45 PM PDT 24 4564097690 ps
T166 /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.3936759280 Jul 31 08:17:18 PM PDT 24 Jul 31 11:16:09 PM PDT 24 59007383797 ps
T1020 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.2750264762 Jul 31 08:25:36 PM PDT 24 Jul 31 08:36:01 PM PDT 24 5722251488 ps
T1021 /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3109378311 Jul 31 08:44:34 PM PDT 24 Jul 31 08:54:35 PM PDT 24 7539335585 ps
T1022 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.36024989 Jul 31 08:21:12 PM PDT 24 Jul 31 08:30:23 PM PDT 24 7715807728 ps
T1023 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.2199849553 Jul 31 08:39:10 PM PDT 24 Jul 31 08:50:20 PM PDT 24 6730494717 ps
T181 /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.973123190 Jul 31 08:14:39 PM PDT 24 Jul 31 08:25:54 PM PDT 24 4516618700 ps
T354 /workspace/coverage/default/2.chip_sw_pattgen_ios.1674501340 Jul 31 08:27:59 PM PDT 24 Jul 31 08:31:09 PM PDT 24 2809556648 ps
T1024 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.840877224 Jul 31 08:32:11 PM PDT 24 Jul 31 08:48:24 PM PDT 24 5627887288 ps
T1025 /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.2713153465 Jul 31 08:21:42 PM PDT 24 Jul 31 09:25:35 PM PDT 24 15787370216 ps
T807 /workspace/coverage/default/81.chip_sw_all_escalation_resets.2452329445 Jul 31 08:47:32 PM PDT 24 Jul 31 08:58:14 PM PDT 24 6432162840 ps
T1026 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.4271265619 Jul 31 08:45:04 PM PDT 24 Jul 31 09:26:15 PM PDT 24 13312856208 ps
T694 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1218785414 Jul 31 08:21:14 PM PDT 24 Jul 31 08:23:09 PM PDT 24 2491275473 ps
T1027 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.715988788 Jul 31 08:15:29 PM PDT 24 Jul 31 08:19:08 PM PDT 24 3103787674 ps
T676 /workspace/coverage/default/2.chip_sw_edn_boot_mode.2188277304 Jul 31 08:31:56 PM PDT 24 Jul 31 08:42:59 PM PDT 24 2718615994 ps
T695 /workspace/coverage/default/2.rom_volatile_raw_unlock.260782962 Jul 31 08:36:53 PM PDT 24 Jul 31 08:38:56 PM PDT 24 1923157461 ps
T1028 /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.3622026664 Jul 31 08:42:04 PM PDT 24 Jul 31 08:51:15 PM PDT 24 4108421656 ps
T790 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2803472795 Jul 31 08:46:54 PM PDT 24 Jul 31 08:53:17 PM PDT 24 3239442376 ps
T355 /workspace/coverage/default/0.chip_sw_pattgen_ios.593386107 Jul 31 08:14:05 PM PDT 24 Jul 31 08:18:18 PM PDT 24 2877477064 ps
T1029 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.312250712 Jul 31 08:22:42 PM PDT 24 Jul 31 09:37:14 PM PDT 24 15127632132 ps
T125 /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.3823998176 Jul 31 08:27:10 PM PDT 24 Jul 31 09:27:34 PM PDT 24 23209129199 ps
T339 /workspace/coverage/default/4.chip_sw_uart_tx_rx.4062554304 Jul 31 08:36:17 PM PDT 24 Jul 31 08:47:23 PM PDT 24 4231737644 ps
T1030 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.1299746788 Jul 31 08:16:46 PM PDT 24 Jul 31 08:26:16 PM PDT 24 3974402736 ps
T1031 /workspace/coverage/default/2.chip_sw_hmac_enc.3359688927 Jul 31 08:32:08 PM PDT 24 Jul 31 08:38:04 PM PDT 24 3358002044 ps
T1032 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.474936865 Jul 31 08:13:38 PM PDT 24 Jul 31 08:44:21 PM PDT 24 8511002000 ps
T770 /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3689095752 Jul 31 08:43:01 PM PDT 24 Jul 31 08:48:51 PM PDT 24 3938521120 ps
T36 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.1321494918 Jul 31 08:19:45 PM PDT 24 Jul 31 08:24:14 PM PDT 24 2918681640 ps
T796 /workspace/coverage/default/2.chip_sw_all_escalation_resets.1579985861 Jul 31 08:29:09 PM PDT 24 Jul 31 08:39:46 PM PDT 24 4696787296 ps
T1033 /workspace/coverage/default/1.rom_e2e_asm_init_dev.4204057056 Jul 31 08:32:49 PM PDT 24 Jul 31 09:36:18 PM PDT 24 15602563234 ps
T1034 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.2363210105 Jul 31 08:23:43 PM PDT 24 Jul 31 08:31:07 PM PDT 24 4143942264 ps
T163 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.3612743437 Jul 31 08:21:06 PM PDT 24 Jul 31 09:21:03 PM PDT 24 18820629591 ps
T9 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.639238229 Jul 31 08:19:13 PM PDT 24 Jul 31 08:24:20 PM PDT 24 2656562450 ps
T1035 /workspace/coverage/default/2.rom_e2e_asm_init_dev.1914251462 Jul 31 08:40:40 PM PDT 24 Jul 31 09:40:51 PM PDT 24 15761386003 ps
T74 /workspace/coverage/default/4.chip_tap_straps_testunlock0.2717972162 Jul 31 08:37:32 PM PDT 24 Jul 31 08:48:25 PM PDT 24 6041040885 ps
T1036 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.116599915 Jul 31 08:24:27 PM PDT 24 Jul 31 08:34:09 PM PDT 24 4243481160 ps
T804 /workspace/coverage/default/46.chip_sw_all_escalation_resets.2145132658 Jul 31 08:42:51 PM PDT 24 Jul 31 08:52:03 PM PDT 24 4291970934 ps
T315 /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.264619649 Jul 31 08:45:25 PM PDT 24 Jul 31 08:51:23 PM PDT 24 3417655072 ps
T1037 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.2959921173 Jul 31 08:39:56 PM PDT 24 Jul 31 08:43:42 PM PDT 24 3425738768 ps
T1038 /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.3784589850 Jul 31 08:26:26 PM PDT 24 Jul 31 08:33:43 PM PDT 24 5373612904 ps
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