| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.04 | 95.47 | 93.78 | 95.32 | 94.52 | 97.53 | 99.61 |
| T2762 | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.682000535 | Jul 31 08:01:59 PM PDT 24 | Jul 31 08:02:53 PM PDT 24 | 752317397 ps | ||
| T2763 | /workspace/coverage/cover_reg_top/83.xbar_access_same_device.1363829662 | Jul 31 08:02:27 PM PDT 24 | Jul 31 08:03:18 PM PDT 24 | 973204605 ps | ||
| T2764 | /workspace/coverage/cover_reg_top/82.xbar_unmapped_addr.3176793843 | Jul 31 08:02:26 PM PDT 24 | Jul 31 08:03:15 PM PDT 24 | 1048863973 ps | ||
| T2765 | /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.846904206 | Jul 31 07:46:02 PM PDT 24 | Jul 31 07:47:36 PM PDT 24 | 5094540758 ps | ||
| T2766 | /workspace/coverage/cover_reg_top/70.xbar_error_random.2785263739 | Jul 31 08:00:24 PM PDT 24 | Jul 31 08:00:35 PM PDT 24 | 253519414 ps | ||
| T2767 | /workspace/coverage/cover_reg_top/67.xbar_smoke.3497235295 | Jul 31 07:59:59 PM PDT 24 | Jul 31 08:00:05 PM PDT 24 | 43303713 ps | ||
| T2768 | /workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.4224872551 | Jul 31 07:47:33 PM PDT 24 | Jul 31 07:47:48 PM PDT 24 | 158497177 ps | ||
| T2769 | /workspace/coverage/cover_reg_top/41.xbar_smoke.1047206864 | Jul 31 07:55:26 PM PDT 24 | Jul 31 07:55:36 PM PDT 24 | 216184549 ps | ||
| T2770 | /workspace/coverage/cover_reg_top/13.xbar_error_random.610149237 | Jul 31 07:49:09 PM PDT 24 | Jul 31 07:50:06 PM PDT 24 | 1772682555 ps | ||
| T2771 | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.4140679419 | Jul 31 07:50:18 PM PDT 24 | Jul 31 07:54:34 PM PDT 24 | 731274395 ps | ||
| T2772 | /workspace/coverage/cover_reg_top/65.xbar_stress_all.3731245107 | Jul 31 07:59:40 PM PDT 24 | Jul 31 08:00:08 PM PDT 24 | 704015887 ps | ||
| T2773 | /workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.38047261 | Jul 31 07:53:50 PM PDT 24 | Jul 31 07:58:55 PM PDT 24 | 18160709805 ps | ||
| T2774 | /workspace/coverage/cover_reg_top/51.xbar_access_same_device.327893301 | Jul 31 07:57:20 PM PDT 24 | Jul 31 07:57:34 PM PDT 24 | 290383458 ps | ||
| T2775 | /workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.1892224051 | Jul 31 08:02:29 PM PDT 24 | Jul 31 08:03:17 PM PDT 24 | 525315739 ps | ||
| T2776 | /workspace/coverage/cover_reg_top/7.xbar_random_zero_delays.4278888636 | Jul 31 07:47:16 PM PDT 24 | Jul 31 07:47:43 PM PDT 24 | 311960354 ps | ||
| T2777 | /workspace/coverage/cover_reg_top/50.xbar_stress_all.2740737595 | Jul 31 07:57:16 PM PDT 24 | Jul 31 08:00:52 PM PDT 24 | 7215409292 ps | ||
| T2778 | /workspace/coverage/cover_reg_top/99.xbar_same_source.1202691988 | Jul 31 08:04:50 PM PDT 24 | Jul 31 08:05:06 PM PDT 24 | 175702750 ps | ||
| T2779 | /workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.2784853582 | Jul 31 08:03:27 PM PDT 24 | Jul 31 08:05:05 PM PDT 24 | 5670226047 ps | ||
| T2780 | /workspace/coverage/cover_reg_top/50.xbar_error_random.1818423669 | Jul 31 07:57:11 PM PDT 24 | Jul 31 07:57:17 PM PDT 24 | 37372916 ps | ||
| T2781 | /workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.2692750854 | Jul 31 07:45:24 PM PDT 24 | Jul 31 07:46:51 PM PDT 24 | 5196118742 ps | ||
| T2782 | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.3536967768 | Jul 31 08:00:59 PM PDT 24 | Jul 31 08:04:20 PM PDT 24 | 527537207 ps | ||
| T2783 | /workspace/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.3035763106 | Jul 31 08:04:17 PM PDT 24 | Jul 31 08:05:41 PM PDT 24 | 4861666283 ps | ||
| T2784 | /workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.663829799 | Jul 31 08:01:26 PM PDT 24 | Jul 31 08:01:47 PM PDT 24 | 245448197 ps | ||
| T2785 | /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.2927430259 | Jul 31 07:48:39 PM PDT 24 | Jul 31 08:21:19 PM PDT 24 | 14371731374 ps | ||
| T2786 | /workspace/coverage/cover_reg_top/78.xbar_smoke_zero_delays.2168711213 | Jul 31 08:01:45 PM PDT 24 | Jul 31 08:01:51 PM PDT 24 | 44291907 ps | ||
| T2787 | /workspace/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.1708708597 | Jul 31 07:58:26 PM PDT 24 | Jul 31 07:59:48 PM PDT 24 | 5068483459 ps | ||
| T2788 | /workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.3240595256 | Jul 31 08:04:41 PM PDT 24 | Jul 31 08:04:59 PM PDT 24 | 148197548 ps | ||
| T2789 | /workspace/coverage/cover_reg_top/16.xbar_random.2650002171 | Jul 31 07:50:01 PM PDT 24 | Jul 31 07:51:04 PM PDT 24 | 1678453182 ps | ||
| T2790 | /workspace/coverage/cover_reg_top/39.xbar_same_source.3144504729 | Jul 31 07:55:12 PM PDT 24 | Jul 31 07:56:25 PM PDT 24 | 2220596849 ps | ||
| T2791 | /workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.2854045086 | Jul 31 07:58:44 PM PDT 24 | Jul 31 08:00:05 PM PDT 24 | 7929433458 ps | ||
| T2792 | /workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.3407470777 | Jul 31 08:01:17 PM PDT 24 | Jul 31 08:01:29 PM PDT 24 | 79275247 ps | ||
| T2793 | /workspace/coverage/cover_reg_top/32.xbar_access_same_device.2321867069 | Jul 31 07:53:50 PM PDT 24 | Jul 31 07:54:21 PM PDT 24 | 678965381 ps | ||
| T626 | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.4157259651 | Jul 31 08:03:35 PM PDT 24 | Jul 31 08:07:37 PM PDT 24 | 3121902340 ps | ||
| T2794 | /workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.3991130819 | Jul 31 07:59:38 PM PDT 24 | Jul 31 08:14:13 PM PDT 24 | 48529121840 ps | ||
| T2795 | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.1580867552 | Jul 31 07:50:10 PM PDT 24 | Jul 31 07:52:50 PM PDT 24 | 2555173892 ps | ||
| T2796 | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.3685732624 | Jul 31 07:55:02 PM PDT 24 | Jul 31 07:58:53 PM PDT 24 | 6059237383 ps | ||
| T2797 | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.1170623292 | Jul 31 07:58:52 PM PDT 24 | Jul 31 08:00:09 PM PDT 24 | 136107167 ps | ||
| T2798 | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.3170701962 | Jul 31 08:02:35 PM PDT 24 | Jul 31 08:05:40 PM PDT 24 | 2881101571 ps | ||
| T2799 | /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.1847810933 | Jul 31 07:45:37 PM PDT 24 | Jul 31 07:53:51 PM PDT 24 | 14018268458 ps | ||
| T2800 | /workspace/coverage/cover_reg_top/87.xbar_random.2459455183 | Jul 31 08:03:03 PM PDT 24 | Jul 31 08:03:25 PM PDT 24 | 264506041 ps | ||
| T2801 | /workspace/coverage/cover_reg_top/80.xbar_stress_all.468935720 | Jul 31 08:02:06 PM PDT 24 | Jul 31 08:11:57 PM PDT 24 | 13609506356 ps | ||
| T2802 | /workspace/coverage/cover_reg_top/90.xbar_smoke.2548814393 | Jul 31 08:03:24 PM PDT 24 | Jul 31 08:03:33 PM PDT 24 | 201491933 ps | ||
| T2803 | /workspace/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.2331946339 | Jul 31 08:04:20 PM PDT 24 | Jul 31 08:04:54 PM PDT 24 | 321784578 ps | ||
| T2804 | /workspace/coverage/cover_reg_top/83.xbar_error_random.2167069889 | Jul 31 08:02:29 PM PDT 24 | Jul 31 08:02:55 PM PDT 24 | 657726192 ps | ||
| T2805 | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.1564950390 | Jul 31 08:01:20 PM PDT 24 | Jul 31 08:06:21 PM PDT 24 | 9281261642 ps | ||
| T2806 | /workspace/coverage/cover_reg_top/13.chip_tl_errors.4181931580 | Jul 31 07:48:59 PM PDT 24 | Jul 31 07:53:56 PM PDT 24 | 4167177268 ps | ||
| T2807 | /workspace/coverage/cover_reg_top/22.chip_tl_errors.1202882222 | Jul 31 07:51:30 PM PDT 24 | Jul 31 07:54:43 PM PDT 24 | 3994787850 ps | ||
| T2808 | /workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.3171473093 | Jul 31 07:51:32 PM PDT 24 | Jul 31 07:51:47 PM PDT 24 | 104497038 ps | ||
| T2809 | /workspace/coverage/cover_reg_top/1.xbar_stress_all.2876084579 | Jul 31 07:45:31 PM PDT 24 | Jul 31 07:53:03 PM PDT 24 | 13347202543 ps | ||
| T2810 | /workspace/coverage/cover_reg_top/53.xbar_random.2875680726 | Jul 31 07:57:40 PM PDT 24 | Jul 31 07:58:10 PM PDT 24 | 374179629 ps | ||
| T2811 | /workspace/coverage/cover_reg_top/9.chip_tl_errors.3247122890 | Jul 31 07:47:45 PM PDT 24 | Jul 31 07:51:29 PM PDT 24 | 3686003330 ps | ||
| T2812 | /workspace/coverage/cover_reg_top/68.xbar_same_source.2013648178 | Jul 31 08:00:08 PM PDT 24 | Jul 31 08:00:47 PM PDT 24 | 587501234 ps | ||
| T2813 | /workspace/coverage/cover_reg_top/60.xbar_same_source.3953952475 | Jul 31 07:58:52 PM PDT 24 | Jul 31 07:59:10 PM PDT 24 | 523139530 ps | ||
| T2814 | /workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.1236824813 | Jul 31 07:58:44 PM PDT 24 | Jul 31 08:06:42 PM PDT 24 | 28613357735 ps | ||
| T2815 | /workspace/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.3060247993 | Jul 31 07:59:29 PM PDT 24 | Jul 31 07:59:34 PM PDT 24 | 44010467 ps | ||
| T2816 | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.1645553987 | Jul 31 07:57:50 PM PDT 24 | Jul 31 07:58:47 PM PDT 24 | 219140688 ps | ||
| T2817 | /workspace/coverage/cover_reg_top/55.xbar_random_large_delays.2571097758 | Jul 31 07:57:58 PM PDT 24 | Jul 31 08:04:18 PM PDT 24 | 36191825013 ps | ||
| T2818 | /workspace/coverage/cover_reg_top/74.xbar_error_random.4063878955 | Jul 31 08:01:13 PM PDT 24 | Jul 31 08:01:24 PM PDT 24 | 246100432 ps | ||
| T2819 | /workspace/coverage/cover_reg_top/5.xbar_random.2604213949 | Jul 31 07:46:36 PM PDT 24 | Jul 31 07:47:31 PM PDT 24 | 1536570071 ps | ||
| T2820 | /workspace/coverage/cover_reg_top/41.xbar_random_large_delays.2781382824 | Jul 31 07:55:30 PM PDT 24 | Jul 31 08:05:19 PM PDT 24 | 54874642742 ps | ||
| T2821 | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.3724780066 | Jul 31 07:59:26 PM PDT 24 | Jul 31 08:00:41 PM PDT 24 | 150586192 ps | ||
| T2822 | /workspace/coverage/cover_reg_top/43.xbar_random.3804333791 | Jul 31 07:55:47 PM PDT 24 | Jul 31 07:56:19 PM PDT 24 | 811764394 ps | ||
| T2823 | /workspace/coverage/cover_reg_top/36.xbar_error_random.2083303490 | Jul 31 07:54:40 PM PDT 24 | Jul 31 07:56:16 PM PDT 24 | 2510905666 ps | ||
| T2824 | /workspace/coverage/cover_reg_top/83.xbar_random_large_delays.3967471086 | Jul 31 08:02:27 PM PDT 24 | Jul 31 08:22:51 PM PDT 24 | 101793129447 ps | ||
| T2825 | /workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.2201338336 | Jul 31 07:59:24 PM PDT 24 | Jul 31 08:00:01 PM PDT 24 | 1011522823 ps | ||
| T2826 | /workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.3718008904 | Jul 31 07:51:26 PM PDT 24 | Jul 31 07:52:58 PM PDT 24 | 5555905261 ps | ||
| T2827 | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.2894535897 | Jul 31 08:02:59 PM PDT 24 | Jul 31 08:09:01 PM PDT 24 | 3610454829 ps | ||
| T2828 | /workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.3416390258 | Jul 31 07:57:58 PM PDT 24 | Jul 31 07:58:25 PM PDT 24 | 275300480 ps | ||
| T2829 | /workspace/coverage/cover_reg_top/2.xbar_smoke.292375344 | Jul 31 07:45:35 PM PDT 24 | Jul 31 07:45:43 PM PDT 24 | 167329438 ps | ||
| T2830 | /workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.4251952659 | Jul 31 08:01:42 PM PDT 24 | Jul 31 08:17:20 PM PDT 24 | 49554209997 ps | ||
| T2831 | /workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.971082003 | Jul 31 08:00:54 PM PDT 24 | Jul 31 08:02:22 PM PDT 24 | 8215528066 ps | ||
| T2832 | /workspace/coverage/cover_reg_top/67.xbar_smoke_large_delays.2379753611 | Jul 31 07:59:51 PM PDT 24 | Jul 31 08:01:26 PM PDT 24 | 9371824449 ps | ||
| T2833 | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.3814783433 | Jul 31 08:00:29 PM PDT 24 | Jul 31 08:04:23 PM PDT 24 | 2878271821 ps | ||
| T2834 | /workspace/coverage/cover_reg_top/78.xbar_error_random.2453213521 | Jul 31 08:01:45 PM PDT 24 | Jul 31 08:02:29 PM PDT 24 | 514091318 ps | ||
| T2835 | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.4244273206 | Jul 31 08:01:11 PM PDT 24 | Jul 31 08:13:23 PM PDT 24 | 21101042866 ps | ||
| T2836 | /workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.981669803 | Jul 31 08:00:56 PM PDT 24 | Jul 31 08:02:26 PM PDT 24 | 5637479606 ps | ||
| T2837 | /workspace/coverage/cover_reg_top/19.xbar_same_source.1351918703 | Jul 31 07:50:47 PM PDT 24 | Jul 31 07:51:47 PM PDT 24 | 2406653890 ps | ||
| T2838 | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.825109828 | Jul 31 07:58:14 PM PDT 24 | Jul 31 08:00:20 PM PDT 24 | 1672759080 ps | ||
| T2839 | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.2452078863 | Jul 31 08:02:42 PM PDT 24 | Jul 31 08:05:46 PM PDT 24 | 501348776 ps | ||
| T2840 | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.1903827830 | Jul 31 08:01:51 PM PDT 24 | Jul 31 08:02:21 PM PDT 24 | 330072910 ps | ||
| T2841 | /workspace/coverage/cover_reg_top/21.xbar_smoke.984021912 | Jul 31 07:51:17 PM PDT 24 | Jul 31 07:51:23 PM PDT 24 | 45587279 ps | ||
| T2842 | /workspace/coverage/cover_reg_top/51.xbar_random_large_delays.653017950 | Jul 31 07:57:18 PM PDT 24 | Jul 31 08:07:39 PM PDT 24 | 54972520498 ps | ||
| T2843 | /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.88277225 | Jul 31 08:00:30 PM PDT 24 | Jul 31 08:00:49 PM PDT 24 | 160156216 ps | ||
| T2844 | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.1308048578 | Jul 31 07:52:27 PM PDT 24 | Jul 31 07:52:50 PM PDT 24 | 34750351 ps | ||
| T2845 | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.3278580407 | Jul 31 07:54:14 PM PDT 24 | Jul 31 07:58:44 PM PDT 24 | 766158245 ps | ||
| T2846 | /workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.3058060364 | Jul 31 07:59:07 PM PDT 24 | Jul 31 08:41:41 PM PDT 24 | 138681036860 ps | ||
| T2847 | /workspace/coverage/cover_reg_top/33.xbar_unmapped_addr.1823867504 | Jul 31 07:54:01 PM PDT 24 | Jul 31 07:54:53 PM PDT 24 | 1366576454 ps | ||
| T2848 | /workspace/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.4200439560 | Jul 31 07:53:00 PM PDT 24 | Jul 31 07:54:25 PM PDT 24 | 4957871379 ps | ||
| T2849 | /workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.2809119165 | Jul 31 07:49:54 PM PDT 24 | Jul 31 07:51:11 PM PDT 24 | 4364812243 ps | ||
| T2850 | /workspace/coverage/cover_reg_top/83.xbar_stress_all.586776136 | Jul 31 08:02:33 PM PDT 24 | Jul 31 08:12:27 PM PDT 24 | 13987862838 ps | ||
| T2851 | /workspace/coverage/cover_reg_top/47.xbar_error_random.483075505 | Jul 31 07:56:39 PM PDT 24 | Jul 31 07:56:47 PM PDT 24 | 137879445 ps | ||
| T2852 | /workspace/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.4259090729 | Jul 31 07:55:58 PM PDT 24 | Jul 31 07:56:07 PM PDT 24 | 55965412 ps | ||
| T2853 | /workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.3325424282 | Jul 31 07:59:59 PM PDT 24 | Jul 31 08:00:31 PM PDT 24 | 378492185 ps | ||
| T2854 | /workspace/coverage/cover_reg_top/30.xbar_random.3845463586 | Jul 31 07:53:25 PM PDT 24 | Jul 31 07:53:58 PM PDT 24 | 932689454 ps | ||
| T2855 | /workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.244571202 | Jul 31 08:00:27 PM PDT 24 | Jul 31 08:01:03 PM PDT 24 | 774201383 ps | ||
| T2856 | /workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.4137803891 | Jul 31 07:48:53 PM PDT 24 | Jul 31 07:49:21 PM PDT 24 | 267944402 ps | ||
| T2857 | /workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.542382038 | Jul 31 07:58:29 PM PDT 24 | Jul 31 07:59:48 PM PDT 24 | 7298592349 ps | ||
| T2858 | /workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.3877565892 | Jul 31 07:59:57 PM PDT 24 | Jul 31 08:01:37 PM PDT 24 | 5875849188 ps | ||
| T2859 | /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.3320793735 | Jul 31 07:52:06 PM PDT 24 | Jul 31 07:53:11 PM PDT 24 | 5832455165 ps | ||
| T2860 | /workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.4223735215 | Jul 31 07:50:19 PM PDT 24 | Jul 31 07:54:36 PM PDT 24 | 15858879085 ps | ||
| T2861 | /workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2721250235 | Jul 31 07:45:06 PM PDT 24 | Jul 31 07:46:36 PM PDT 24 | 5002569349 ps | ||
| T2862 | /workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.3893857534 | Jul 31 07:54:56 PM PDT 24 | Jul 31 08:02:46 PM PDT 24 | 30257586379 ps | ||
| T2863 | /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.3708255161 | Jul 31 08:01:16 PM PDT 24 | Jul 31 08:26:12 PM PDT 24 | 78515748868 ps | ||
| T2864 | /workspace/coverage/cover_reg_top/83.xbar_random.1615137496 | Jul 31 08:02:29 PM PDT 24 | Jul 31 08:02:45 PM PDT 24 | 367125507 ps | ||
| T2865 | /workspace/coverage/cover_reg_top/26.xbar_random_large_delays.4027865330 | Jul 31 07:52:35 PM PDT 24 | Jul 31 08:06:34 PM PDT 24 | 77207570802 ps | ||
| T2866 | /workspace/coverage/cover_reg_top/23.xbar_smoke_zero_delays.111037606 | Jul 31 07:51:53 PM PDT 24 | Jul 31 07:51:59 PM PDT 24 | 44749512 ps | ||
| T2867 | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.2638118682 | Jul 31 07:48:19 PM PDT 24 | Jul 31 07:49:02 PM PDT 24 | 159716778 ps | ||
| T2868 | /workspace/coverage/cover_reg_top/4.xbar_smoke.3464197888 | Jul 31 07:46:21 PM PDT 24 | Jul 31 07:46:30 PM PDT 24 | 206618016 ps | ||
| T2869 | /workspace/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.1522764155 | Jul 31 07:59:07 PM PDT 24 | Jul 31 07:59:39 PM PDT 24 | 761470281 ps | ||
| T2870 | /workspace/coverage/cover_reg_top/35.xbar_random_large_delays.176349093 | Jul 31 07:54:25 PM PDT 24 | Jul 31 08:06:18 PM PDT 24 | 68286180570 ps | ||
| T2871 | /workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.176550234 | Jul 31 07:50:47 PM PDT 24 | Jul 31 08:10:36 PM PDT 24 | 68514256239 ps | ||
| T2872 | /workspace/coverage/cover_reg_top/88.xbar_random_zero_delays.1444045973 | Jul 31 08:03:10 PM PDT 24 | Jul 31 08:03:47 PM PDT 24 | 441435237 ps | ||
| T2873 | /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.930622383 | Jul 31 08:04:49 PM PDT 24 | Jul 31 08:04:56 PM PDT 24 | 78592052 ps | ||
| T2874 | /workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.646758586 | Jul 31 07:57:52 PM PDT 24 | Jul 31 08:17:48 PM PDT 24 | 70166567320 ps | ||
| T2875 | /workspace/coverage/cover_reg_top/90.xbar_error_random.1667361734 | Jul 31 08:03:29 PM PDT 24 | Jul 31 08:03:49 PM PDT 24 | 238512671 ps | ||
| T2876 | /workspace/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.3245242660 | Jul 31 07:54:50 PM PDT 24 | Jul 31 07:55:05 PM PDT 24 | 155052574 ps | ||
| T2877 | /workspace/coverage/cover_reg_top/63.xbar_smoke_zero_delays.3470640621 | Jul 31 07:59:15 PM PDT 24 | Jul 31 07:59:22 PM PDT 24 | 51167198 ps | ||
| T2878 | /workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.4259168791 | Jul 31 08:00:15 PM PDT 24 | Jul 31 08:06:40 PM PDT 24 | 24906509898 ps | ||
| T2879 | /workspace/coverage/cover_reg_top/40.xbar_smoke.3502174627 | Jul 31 07:55:17 PM PDT 24 | Jul 31 07:55:26 PM PDT 24 | 192121454 ps | ||
| T2880 | /workspace/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.2330012423 | Jul 31 07:59:47 PM PDT 24 | Jul 31 08:00:53 PM PDT 24 | 3969620759 ps | ||
| T2881 | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.2327480004 | Jul 31 08:00:15 PM PDT 24 | Jul 31 08:04:41 PM PDT 24 | 3063542604 ps | ||
| T2882 | /workspace/coverage/cover_reg_top/84.xbar_error_random.1045441961 | Jul 31 08:02:45 PM PDT 24 | Jul 31 08:03:26 PM PDT 24 | 1315875187 ps | ||
| T2883 | /workspace/coverage/cover_reg_top/76.xbar_smoke_zero_delays.338145833 | Jul 31 08:01:20 PM PDT 24 | Jul 31 08:01:26 PM PDT 24 | 46675423 ps | ||
| T2884 | /workspace/coverage/cover_reg_top/59.xbar_error_random.2695990801 | Jul 31 07:58:51 PM PDT 24 | Jul 31 08:00:08 PM PDT 24 | 2399387475 ps | ||
| T2885 | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.2022293474 | Jul 31 07:55:34 PM PDT 24 | Jul 31 07:58:24 PM PDT 24 | 3724075727 ps | ||
| T2886 | /workspace/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.3137317616 | Jul 31 07:59:02 PM PDT 24 | Jul 31 07:59:37 PM PDT 24 | 1081866508 ps | ||
| T2887 | /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.3251561792 | Jul 31 08:04:50 PM PDT 24 | Jul 31 08:08:44 PM PDT 24 | 13815813148 ps | ||
| T2888 | /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.1368990749 | Jul 31 08:02:50 PM PDT 24 | Jul 31 08:03:28 PM PDT 24 | 962788590 ps | ||
| T2889 | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.1198502666 | Jul 31 08:03:43 PM PDT 24 | Jul 31 08:08:03 PM PDT 24 | 2300003613 ps | ||
| T2890 | /workspace/coverage/cover_reg_top/98.xbar_stress_all.3061692367 | Jul 31 08:04:45 PM PDT 24 | Jul 31 08:08:47 PM PDT 24 | 2967471485 ps | ||
| T2891 | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.3867292701 | Jul 31 07:58:39 PM PDT 24 | Jul 31 07:59:39 PM PDT 24 | 160699053 ps | ||
| T2892 | /workspace/coverage/cover_reg_top/84.xbar_random_slow_rsp.1544746882 | Jul 31 08:02:34 PM PDT 24 | Jul 31 08:08:13 PM PDT 24 | 21465193191 ps | ||
| T2893 | /workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.4107637777 | Jul 31 08:03:47 PM PDT 24 | Jul 31 08:19:21 PM PDT 24 | 47255438947 ps | ||
| T2894 | /workspace/coverage/cover_reg_top/28.xbar_access_same_device.1608405039 | Jul 31 07:53:07 PM PDT 24 | Jul 31 07:54:18 PM PDT 24 | 1688728828 ps | ||
| T2895 | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.1278783308 | Jul 31 07:53:30 PM PDT 24 | Jul 31 07:57:42 PM PDT 24 | 6790443022 ps | ||
| T2896 | /workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.1269523300 | Jul 31 07:53:43 PM PDT 24 | Jul 31 07:55:14 PM PDT 24 | 8272268146 ps | ||
| T2897 | /workspace/coverage/cover_reg_top/9.xbar_random_large_delays.2776826161 | Jul 31 07:47:52 PM PDT 24 | Jul 31 08:03:35 PM PDT 24 | 91862480152 ps | ||
| T2898 | /workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.3833313048 | Jul 31 07:54:33 PM PDT 24 | Jul 31 08:13:34 PM PDT 24 | 67820241073 ps | ||
| T2899 | /workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.236294296 | Jul 31 07:56:28 PM PDT 24 | Jul 31 08:31:20 PM PDT 24 | 109559521277 ps | ||
| T2900 | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.3366351576 | Jul 31 07:59:20 PM PDT 24 | Jul 31 08:02:44 PM PDT 24 | 6285667819 ps | ||
| T2901 | /workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.3800141156 | Jul 31 07:57:41 PM PDT 24 | Jul 31 08:12:54 PM PDT 24 | 51118072284 ps | ||
| T2902 | /workspace/coverage/cover_reg_top/18.xbar_random_large_delays.2864701866 | Jul 31 07:50:30 PM PDT 24 | Jul 31 07:51:04 PM PDT 24 | 3194761897 ps | ||
| T2903 | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.190684965 | Jul 31 08:03:06 PM PDT 24 | Jul 31 08:10:38 PM PDT 24 | 1734660979 ps | ||
| T2904 | /workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.1298014650 | Jul 31 08:02:02 PM PDT 24 | Jul 31 08:02:08 PM PDT 24 | 40949656 ps | ||
| T2905 | /workspace/coverage/cover_reg_top/45.xbar_access_same_device.2552220170 | Jul 31 07:56:19 PM PDT 24 | Jul 31 07:57:17 PM PDT 24 | 651092765 ps | ||
| T2906 | /workspace/coverage/cover_reg_top/44.xbar_smoke_large_delays.712527345 | Jul 31 07:56:05 PM PDT 24 | Jul 31 07:57:34 PM PDT 24 | 8887616982 ps | ||
| T2907 | /workspace/coverage/cover_reg_top/44.xbar_random.2683817453 | Jul 31 07:56:08 PM PDT 24 | Jul 31 07:56:44 PM PDT 24 | 391018072 ps | ||
| T2908 | /workspace/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.1430041011 | Jul 31 07:58:51 PM PDT 24 | Jul 31 07:59:15 PM PDT 24 | 541373403 ps | ||
| T2909 | /workspace/coverage/cover_reg_top/34.xbar_stress_all.1495102648 | Jul 31 07:54:15 PM PDT 24 | Jul 31 08:01:18 PM PDT 24 | 10445795670 ps | ||
| T2910 | /workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.3242425362 | Jul 31 07:59:31 PM PDT 24 | Jul 31 07:59:38 PM PDT 24 | 48714639 ps | ||
| T2911 | /workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.3857714474 | Jul 31 07:48:02 PM PDT 24 | Jul 31 07:48:09 PM PDT 24 | 51123104 ps | ||
| T2912 | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.4231774979 | Jul 31 07:49:33 PM PDT 24 | Jul 31 07:49:53 PM PDT 24 | 47392477 ps | ||
| T2913 | /workspace/coverage/cover_reg_top/45.xbar_random_large_delays.3532457870 | Jul 31 07:56:19 PM PDT 24 | Jul 31 08:06:52 PM PDT 24 | 63712614373 ps | ||
| T2914 | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.1407260094 | Jul 31 07:47:49 PM PDT 24 | Jul 31 07:55:51 PM PDT 24 | 5064406696 ps | ||
| T2915 | /workspace/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.1239365146 | Jul 31 07:50:59 PM PDT 24 | Jul 31 08:05:39 PM PDT 24 | 11689871875 ps | ||
| T2916 | /workspace/coverage/cover_reg_top/2.chip_csr_aliasing.502636032 | Jul 31 07:45:30 PM PDT 24 | Jul 31 09:04:53 PM PDT 24 | 26385884170 ps | ||
| T2917 | /workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.481424817 | Jul 31 08:00:21 PM PDT 24 | Jul 31 08:02:08 PM PDT 24 | 6154351544 ps | ||
| T2918 | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.1158183119 | Jul 31 07:55:47 PM PDT 24 | Jul 31 08:00:42 PM PDT 24 | 819462380 ps | ||
| T2919 | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.3023267093 | Jul 31 07:57:04 PM PDT 24 | Jul 31 08:02:15 PM PDT 24 | 2716807617 ps | ||
| T2920 | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.1382802764 | Jul 31 07:48:16 PM PDT 24 | Jul 31 07:48:30 PM PDT 24 | 130570970 ps | ||
| T2921 | /workspace/coverage/cover_reg_top/98.xbar_access_same_device.284256305 | Jul 31 08:04:40 PM PDT 24 | Jul 31 08:05:34 PM PDT 24 | 1481243886 ps | ||
| T2922 | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.301970843 | Jul 31 07:46:41 PM PDT 24 | Jul 31 07:48:34 PM PDT 24 | 261789403 ps | ||
| T2923 | /workspace/coverage/cover_reg_top/17.xbar_same_source.1354031731 | Jul 31 07:50:18 PM PDT 24 | Jul 31 07:50:31 PM PDT 24 | 399548572 ps | ||
| T2924 | /workspace/coverage/cover_reg_top/96.xbar_error_random.2417122400 | Jul 31 08:04:30 PM PDT 24 | Jul 31 08:05:50 PM PDT 24 | 2647713855 ps | ||
| T2925 | /workspace/coverage/cover_reg_top/44.xbar_error_random.204831754 | Jul 31 07:56:12 PM PDT 24 | Jul 31 07:57:40 PM PDT 24 | 2390166289 ps | ||
| T2926 | /workspace/coverage/cover_reg_top/3.xbar_random_zero_delays.3520959260 | Jul 31 07:46:02 PM PDT 24 | Jul 31 07:46:39 PM PDT 24 | 450279103 ps | ||
| T2927 | /workspace/coverage/cover_reg_top/25.xbar_same_source.1618591290 | Jul 31 07:52:22 PM PDT 24 | Jul 31 07:52:53 PM PDT 24 | 424690879 ps | ||
| T2928 | /workspace/coverage/cover_reg_top/4.xbar_same_source.3170797405 | Jul 31 07:46:35 PM PDT 24 | Jul 31 07:47:32 PM PDT 24 | 2045612618 ps | ||
| T2929 | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.1219655484 | Jul 31 07:54:14 PM PDT 24 | Jul 31 07:55:18 PM PDT 24 | 1925772978 ps | ||
| T2930 | /workspace/coverage/cover_reg_top/65.xbar_random.3114129167 | Jul 31 07:59:39 PM PDT 24 | Jul 31 08:00:45 PM PDT 24 | 1894949264 ps | ||
| T2931 | /workspace/coverage/cover_reg_top/39.xbar_random_large_delays.3597222337 | Jul 31 07:55:09 PM PDT 24 | Jul 31 08:00:09 PM PDT 24 | 30503414056 ps | ||
| T2932 | /workspace/coverage/cover_reg_top/45.xbar_random.552814335 | Jul 31 07:56:17 PM PDT 24 | Jul 31 07:56:50 PM PDT 24 | 422183237 ps | ||
| T2933 | /workspace/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.1345253550 | Jul 31 07:57:07 PM PDT 24 | Jul 31 07:57:49 PM PDT 24 | 1138312759 ps | ||
| T2934 | /workspace/coverage/cover_reg_top/6.xbar_random_large_delays.1375739583 | Jul 31 07:46:57 PM PDT 24 | Jul 31 07:52:04 PM PDT 24 | 30087062084 ps | ||
| T2935 | /workspace/coverage/cover_reg_top/3.xbar_smoke.347614357 | Jul 31 07:45:53 PM PDT 24 | Jul 31 07:45:59 PM PDT 24 | 41317077 ps | ||
| T2936 | /workspace/coverage/cover_reg_top/34.xbar_smoke_zero_delays.3173237246 | Jul 31 07:54:09 PM PDT 24 | Jul 31 07:54:15 PM PDT 24 | 56360366 ps | ||
| T31 | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3025543986 | Jul 31 07:44:56 PM PDT 24 | Jul 31 07:48:51 PM PDT 24 | 4618263420 ps | ||
| T32 | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1538960740 | Jul 31 07:45:00 PM PDT 24 | Jul 31 07:49:21 PM PDT 24 | 5436411328 ps | ||
| T33 | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2740592565 | Jul 31 07:44:55 PM PDT 24 | Jul 31 07:49:31 PM PDT 24 | 4652181152 ps | ||
| T34 | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2045240816 | Jul 31 07:44:59 PM PDT 24 | Jul 31 07:47:59 PM PDT 24 | 3717727280 ps | ||
| T199 | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2425787393 | Jul 31 07:45:03 PM PDT 24 | Jul 31 07:49:16 PM PDT 24 | 5005822944 ps | ||
| T200 | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3909217737 | Jul 31 07:45:03 PM PDT 24 | Jul 31 07:48:45 PM PDT 24 | 3839139275 ps | ||
| T201 | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.421526056 | Jul 31 07:45:02 PM PDT 24 | Jul 31 07:48:58 PM PDT 24 | 4574767240 ps | ||
| T202 | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.765018562 | Jul 31 07:44:56 PM PDT 24 | Jul 31 07:49:56 PM PDT 24 | 4488850144 ps | ||
| T204 | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2248588599 | Jul 31 07:45:00 PM PDT 24 | Jul 31 07:48:32 PM PDT 24 | 4049497374 ps | ||
| T203 | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1077677341 | Jul 31 07:45:00 PM PDT 24 | Jul 31 07:50:24 PM PDT 24 | 5275185952 ps |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_10.1073630544 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 3828267894 ps |
| CPU time | 511.5 seconds |
| Started | Jul 31 08:16:31 PM PDT 24 |
| Finished | Jul 31 08:25:03 PM PDT 24 |
| Peak memory | 609748 kb |
| Host | smart-6ba72d65-cd7d-42dc-9885-7056d2d3d7fd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073630544 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_10.1073630544 |
| Directory | /workspace/0.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.817833677 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 11323859228 ps |
| CPU time | 833.16 seconds |
| Started | Jul 31 07:48:02 PM PDT 24 |
| Finished | Jul 31 08:01:55 PM PDT 24 |
| Peak memory | 648980 kb |
| Host | smart-26951c63-d0ea-4eaf-9889-f8f8bbcc01fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817833677 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 9.chip_csr_mem_rw_with_rand_reset.817833677 |
| Directory | /workspace/9.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.2385495479 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 128152201254 ps |
| CPU time | 2311.54 seconds |
| Started | Jul 31 07:48:16 PM PDT 24 |
| Finished | Jul 31 08:26:48 PM PDT 24 |
| Peak memory | 576060 kb |
| Host | smart-7288d456-9650-4156-8166-fd185f5be206 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385495479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_ device_slow_rsp.2385495479 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1763426420 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5222592197 ps |
| CPU time | 445.33 seconds |
| Started | Jul 31 08:30:34 PM PDT 24 |
| Finished | Jul 31 08:37:59 PM PDT 24 |
| Peak memory | 610888 kb |
| Host | smart-e9833de3-96be-4e82-b686-6c163b07dd5e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17 63426420 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_lc_rw_en.1763426420 |
| Directory | /workspace/2.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.3897237637 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 119124130576 ps |
| CPU time | 2133.74 seconds |
| Started | Jul 31 07:54:59 PM PDT 24 |
| Finished | Jul 31 08:30:33 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-dd1f88d2-9226-4c41-8784-50ae3fec42b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897237637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_ device_slow_rsp.3897237637 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3025543986 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 4618263420 ps |
| CPU time | 234.92 seconds |
| Started | Jul 31 07:44:56 PM PDT 24 |
| Finished | Jul 31 07:48:51 PM PDT 24 |
| Peak memory | 655208 kb |
| Host | smart-4706df7a-ab8d-4ef9-a886-a212989ec05c |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025543986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 2.chip_padctrl_attributes.3025543986 |
| Directory | /workspace/2.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all.208928642 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 19467675820 ps |
| CPU time | 744.99 seconds |
| Started | Jul 31 07:53:56 PM PDT 24 |
| Finished | Jul 31 08:06:21 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-3118e148-83bd-4599-9138-4b6d36a1c926 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208928642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.208928642 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.3451915339 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 15417190556 ps |
| CPU time | 3551.91 seconds |
| Started | Jul 31 08:22:29 PM PDT 24 |
| Finished | Jul 31 09:21:42 PM PDT 24 |
| Peak memory | 610208 kb |
| Host | smart-9ee00b04-41e1-497f-b27f-7b132b604c6b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451915339 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.3451915339 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.679283913 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 126864899010 ps |
| CPU time | 2432.44 seconds |
| Started | Jul 31 08:02:32 PM PDT 24 |
| Finished | Jul 31 08:43:05 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-ea2c21ee-fd9c-4a4a-b82d-04ca6dffdf17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679283913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_d evice_slow_rsp.679283913 |
| Directory | /workspace/84.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_virus.583871867 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5598772508 ps |
| CPU time | 1423.45 seconds |
| Started | Jul 31 08:38:55 PM PDT 24 |
| Finished | Jul 31 09:02:38 PM PDT 24 |
| Peak memory | 625024 kb |
| Host | smart-34ca08a7-b87b-4043-a7dc-2ac2d31ed5c4 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +accelerate_cold_ power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtes t_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=583871867 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_virus.583871867 |
| Directory | /workspace/2.chip_sw_power_virus/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.2706553332 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 26290506824 ps |
| CPU time | 2545.81 seconds |
| Started | Jul 31 08:20:12 PM PDT 24 |
| Finished | Jul 31 09:02:38 PM PDT 24 |
| Peak memory | 621220 kb |
| Host | smart-f396ed79-9c1b-49ee-9661-c9e32acc0bfd |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2706553332 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testun locks.2706553332 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.2443469322 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 88157233695 ps |
| CPU time | 1503.55 seconds |
| Started | Jul 31 07:53:29 PM PDT 24 |
| Finished | Jul 31 08:18:33 PM PDT 24 |
| Peak memory | 576044 kb |
| Host | smart-1336c53a-629e-451c-9c7e-b00b76f8ce3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443469322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_ device_slow_rsp.2443469322 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_0.1913934836 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 6465895426 ps |
| CPU time | 1261.17 seconds |
| Started | Jul 31 08:33:28 PM PDT 24 |
| Finished | Jul 31 08:54:30 PM PDT 24 |
| Peak memory | 608872 kb |
| Host | smart-0be8dc74-2526-4a1a-9667-85c2be4b7bdb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913934836 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_plic_all_irqs_0.1913934836 |
| Directory | /workspace/2.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.639238229 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 2656562450 ps |
| CPU time | 306.64 seconds |
| Started | Jul 31 08:19:13 PM PDT 24 |
| Finished | Jul 31 08:24:20 PM PDT 24 |
| Peak memory | 610024 kb |
| Host | smart-f9be7766-49b6-4330-8423-947795318604 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6392 38229 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.639238229 |
| Directory | /workspace/1.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2926490704 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 12781911800 ps |
| CPU time | 3091.56 seconds |
| Started | Jul 31 08:13:22 PM PDT 24 |
| Finished | Jul 31 09:04:54 PM PDT 24 |
| Peak memory | 611176 kb |
| Host | smart-9d32be57-3337-40de-9220-cbbc3c344c65 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292649 0704 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_aes.2926490704 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.3687210099 |
| Short name | T1500 |
| Test name | |
| Test status | |
| Simulation time | 101439475404 ps |
| CPU time | 2025.8 seconds |
| Started | Jul 31 08:02:30 PM PDT 24 |
| Finished | Jul 31 08:36:16 PM PDT 24 |
| Peak memory | 576124 kb |
| Host | smart-7015d6bf-e5ef-4c56-8a5a-40fcd053dd9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687210099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_ device_slow_rsp.3687210099 |
| Directory | /workspace/83.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2430908654 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 22485228392 ps |
| CPU time | 1651.39 seconds |
| Started | Jul 31 08:33:38 PM PDT 24 |
| Finished | Jul 31 09:01:09 PM PDT 24 |
| Peak memory | 610628 kb |
| Host | smart-1ceca97f-61d6-4826-9e40-032c09929024 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2430908654 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2430908654 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1221884511 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 2975062660 ps |
| CPU time | 338.46 seconds |
| Started | Jul 31 08:15:39 PM PDT 24 |
| Finished | Jul 31 08:21:18 PM PDT 24 |
| Peak memory | 609876 kb |
| Host | smart-60f14034-1024-43d4-96fd-4653a53af98e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1221884511 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.1221884511 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_20.2083441115 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 4710217708 ps |
| CPU time | 814.75 seconds |
| Started | Jul 31 08:18:37 PM PDT 24 |
| Finished | Jul 31 08:32:12 PM PDT 24 |
| Peak memory | 610008 kb |
| Host | smart-bcca184e-51d3-4024-820c-5cfb219800ad |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083441115 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_20.2083441115 |
| Directory | /workspace/0.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_csr_rw.726697243 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 12443660613 ps |
| CPU time | 1498.01 seconds |
| Started | Jul 31 08:17:04 PM PDT 24 |
| Finished | Jul 31 08:42:03 PM PDT 24 |
| Peak memory | 608048 kb |
| Host | smart-87dc0252-e6f0-4670-925b-699e1fa862f4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726697243 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.ch ip_jtag_csr_rw.726697243 |
| Directory | /workspace/1.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.4064149222 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 1162813868 ps |
| CPU time | 190.22 seconds |
| Started | Jul 31 07:53:18 PM PDT 24 |
| Finished | Jul 31 07:56:29 PM PDT 24 |
| Peak memory | 576704 kb |
| Host | smart-90c41406-454e-4189-b718-1ff9d11d5bf2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064149222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all _with_rand_reset.4064149222 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3368529697 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 4003955252 ps |
| CPU time | 357.59 seconds |
| Started | Jul 31 08:42:18 PM PDT 24 |
| Finished | Jul 31 08:48:16 PM PDT 24 |
| Peak memory | 649104 kb |
| Host | smart-24d294ce-b60f-455a-9fbf-2c08d86af320 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368529697 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3368529697 |
| Directory | /workspace/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2752440115 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 11765035712 ps |
| CPU time | 1403.12 seconds |
| Started | Jul 31 08:21:07 PM PDT 24 |
| Finished | Jul 31 08:44:30 PM PDT 24 |
| Peak memory | 610960 kb |
| Host | smart-59127adc-c6ba-4634-842e-2e2c7b22c980 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752440115 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_sleep_mode_pings.2752440115 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio.2353681268 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4220607275 ps |
| CPU time | 522.39 seconds |
| Started | Jul 31 08:11:58 PM PDT 24 |
| Finished | Jul 31 08:20:40 PM PDT 24 |
| Peak memory | 610024 kb |
| Host | smart-036aa581-0064-486a-81b6-0a2fe520f472 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353681268 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_gpio.2353681268 |
| Directory | /workspace/0.chip_sw_gpio/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_csr_rw.1824524235 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 5415863732 ps |
| CPU time | 505.24 seconds |
| Started | Jul 31 07:50:10 PM PDT 24 |
| Finished | Jul 31 07:58:36 PM PDT 24 |
| Peak memory | 598624 kb |
| Host | smart-9d08637d-cb55-4b8c-b1a2-432374c39acf |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824524235 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_csr_rw.1824524235 |
| Directory | /workspace/16.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.3506377798 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 8836816566 ps |
| CPU time | 460.38 seconds |
| Started | Jul 31 08:00:16 PM PDT 24 |
| Finished | Jul 31 08:07:57 PM PDT 24 |
| Peak memory | 576760 kb |
| Host | smart-470764ae-529a-40b5-b2fa-547153c97414 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506377798 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_al l_with_reset_error.3506377798 |
| Directory | /workspace/68.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.3720218367 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 90689231049 ps |
| CPU time | 1769.37 seconds |
| Started | Jul 31 08:04:53 PM PDT 24 |
| Finished | Jul 31 08:34:23 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-4f53215c-8deb-48eb-8ebd-207ca826f087 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720218367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_ device_slow_rsp.3720218367 |
| Directory | /workspace/99.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.chip_tl_errors.1101301333 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 4774306420 ps |
| CPU time | 370.06 seconds |
| Started | Jul 31 07:52:03 PM PDT 24 |
| Finished | Jul 31 07:58:13 PM PDT 24 |
| Peak memory | 598608 kb |
| Host | smart-2251602b-d3a7-4bdf-b9eb-89f2ee7fc122 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101301333 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.chip_tl_errors.1101301333 |
| Directory | /workspace/24.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.2047417479 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 6580397822 ps |
| CPU time | 1252.99 seconds |
| Started | Jul 31 08:24:08 PM PDT 24 |
| Finished | Jul 31 08:45:01 PM PDT 24 |
| Peak memory | 610652 kb |
| Host | smart-9cf380d3-ad9e-4897-8da9-0774afbe2966 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2047417479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.2047417479 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/47.chip_sw_all_escalation_resets.1748374313 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 5815231004 ps |
| CPU time | 590.98 seconds |
| Started | Jul 31 08:43:46 PM PDT 24 |
| Finished | Jul 31 08:53:37 PM PDT 24 |
| Peak memory | 619752 kb |
| Host | smart-8d3839fd-dc00-45b6-825f-eaf61f00bd2c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1748374313 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.1748374313 |
| Directory | /workspace/47.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.555306540 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 3661106073 ps |
| CPU time | 329.08 seconds |
| Started | Jul 31 08:13:18 PM PDT 24 |
| Finished | Jul 31 08:18:47 PM PDT 24 |
| Peak memory | 610296 kb |
| Host | smart-5bfade5c-fb7d-4d30-b30f-1a41f008b928 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5553 06540 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.555306540 |
| Directory | /workspace/0.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4063283620 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 5283317326 ps |
| CPU time | 561.14 seconds |
| Started | Jul 31 08:16:04 PM PDT 24 |
| Finished | Jul 31 08:25:25 PM PDT 24 |
| Peak memory | 610104 kb |
| Host | smart-484857af-d1ae-4ccf-b2e7-bb2ae39a9b30 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40632836 20 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4063283620 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.3962899660 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 150033478327 ps |
| CPU time | 2605.39 seconds |
| Started | Jul 31 08:02:12 PM PDT 24 |
| Finished | Jul 31 08:45:37 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-82fd6f5e-3c9f-4161-87c9-6931c415c8ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962899660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_ device_slow_rsp.3962899660 |
| Directory | /workspace/81.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_large_delays.1487904459 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 94872962946 ps |
| CPU time | 954.09 seconds |
| Started | Jul 31 07:51:35 PM PDT 24 |
| Finished | Jul 31 08:07:29 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-615c5c5b-da78-4109-b930-9836140ba147 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487904459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.1487904459 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.3547094996 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 7331224006 ps |
| CPU time | 778.09 seconds |
| Started | Jul 31 07:51:11 PM PDT 24 |
| Finished | Jul 31 08:04:09 PM PDT 24 |
| Peak memory | 576996 kb |
| Host | smart-b2ab69b9-818a-4bb1-8a30-0a73a50554c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547094996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all _with_rand_reset.3547094996 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.798478627 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 51672778402 ps |
| CPU time | 6005.67 seconds |
| Started | Jul 31 08:30:13 PM PDT 24 |
| Finished | Jul 31 10:10:19 PM PDT 24 |
| Peak memory | 620640 kb |
| Host | smart-e73dd83b-ba65-45c9-bcf0-f4efa98b6207 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798478627 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_ sw_lc_walkthrough_dev.798478627 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3103925343 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 7682908006 ps |
| CPU time | 845.06 seconds |
| Started | Jul 31 08:23:14 PM PDT 24 |
| Finished | Jul 31 08:37:19 PM PDT 24 |
| Peak memory | 610456 kb |
| Host | smart-dabb59b2-e032-4ff6-84df-6065a0de32a1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103925343 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.3103925343 |
| Directory | /workspace/1.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.3702048906 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 3508109821 ps |
| CPU time | 346.91 seconds |
| Started | Jul 31 08:12:41 PM PDT 24 |
| Finished | Jul 31 08:18:28 PM PDT 24 |
| Peak memory | 618040 kb |
| Host | smart-6c42a334-7ba8-48bf-9302-4456d70839fa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702048906 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pinmux_sleep_retention.3702048906 |
| Directory | /workspace/0.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2305725632 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 24574843002 ps |
| CPU time | 2051.97 seconds |
| Started | Jul 31 08:12:05 PM PDT 24 |
| Finished | Jul 31 08:46:18 PM PDT 24 |
| Peak memory | 614928 kb |
| Host | smart-0eba585f-c6b1-4473-b193-7a7029f79e11 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23057256 32 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.2305725632 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_test.1251449249 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 3513907800 ps |
| CPU time | 337.16 seconds |
| Started | Jul 31 08:20:25 PM PDT 24 |
| Finished | Jul 31 08:26:02 PM PDT 24 |
| Peak memory | 609720 kb |
| Host | smart-b710d7c8-b7c2-4cab-a7ec-2d44a925c85f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251449249 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.chip_sw_alert_test.1251449249 |
| Directory | /workspace/1.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_tl_errors.731391621 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 4607376635 ps |
| CPU time | 359.37 seconds |
| Started | Jul 31 07:49:38 PM PDT 24 |
| Finished | Jul 31 07:55:37 PM PDT 24 |
| Peak memory | 603696 kb |
| Host | smart-89ece00a-e0d1-4ba8-bd36-36d81a23e7de |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731391621 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_tl_errors.731391621 |
| Directory | /workspace/15.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3679281613 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 3081964774 ps |
| CPU time | 260.97 seconds |
| Started | Jul 31 08:27:25 PM PDT 24 |
| Finished | Jul 31 08:31:46 PM PDT 24 |
| Peak memory | 610200 kb |
| Host | smart-1b1915c6-9832-4d73-9b4c-5155c59abb7b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679 281613 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.3679281613 |
| Directory | /workspace/2.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3861191091 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 5023610078 ps |
| CPU time | 567.22 seconds |
| Started | Jul 31 08:33:15 PM PDT 24 |
| Finished | Jul 31 08:42:43 PM PDT 24 |
| Peak memory | 611180 kb |
| Host | smart-326332c2-3aba-4eeb-b9c8-c1207cfe1e86 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861191091 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3861191091 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.1290738197 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 6249100636 ps |
| CPU time | 757.9 seconds |
| Started | Jul 31 08:16:47 PM PDT 24 |
| Finished | Jul 31 08:29:26 PM PDT 24 |
| Peak memory | 610492 kb |
| Host | smart-82e85462-37c1-4000-8278-3a7762695c58 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290738197 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_rstmgr_cpu_info.1290738197 |
| Directory | /workspace/0.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_all_escalation_resets.1387118045 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 5040614440 ps |
| CPU time | 729.27 seconds |
| Started | Jul 31 08:13:30 PM PDT 24 |
| Finished | Jul 31 08:25:40 PM PDT 24 |
| Peak memory | 650260 kb |
| Host | smart-b7ac86ef-916f-4d69-964c-93815a94576e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1387118045 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.1387118045 |
| Directory | /workspace/0.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.1882633018 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 28789524065 ps |
| CPU time | 4191.22 seconds |
| Started | Jul 31 07:45:49 PM PDT 24 |
| Finished | Jul 31 08:55:41 PM PDT 24 |
| Peak memory | 593288 kb |
| Host | smart-3324929b-abf6-49e8-ae9e-bec1375acae8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882633018 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 3.chip_same_csr_outstanding.1882633018 |
| Directory | /workspace/3.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.765018562 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 4488850144 ps |
| CPU time | 299.83 seconds |
| Started | Jul 31 07:44:56 PM PDT 24 |
| Finished | Jul 31 07:49:56 PM PDT 24 |
| Peak memory | 649156 kb |
| Host | smart-d6f4d5da-6359-49ee-8a25-fcdfd5263de5 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765018562 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 1.chip_padctrl_attributes.765018562 |
| Directory | /workspace/1.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/default/78.chip_sw_all_escalation_resets.1207776346 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 4735977528 ps |
| CPU time | 604.72 seconds |
| Started | Jul 31 08:45:30 PM PDT 24 |
| Finished | Jul 31 08:55:35 PM PDT 24 |
| Peak memory | 650200 kb |
| Host | smart-0d7ae97d-2872-49a4-a4c2-fdc4a4058cbd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1207776346 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.1207776346 |
| Directory | /workspace/78.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3756980172 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 44286672896 ps |
| CPU time | 4895.35 seconds |
| Started | Jul 31 08:18:48 PM PDT 24 |
| Finished | Jul 31 09:40:24 PM PDT 24 |
| Peak memory | 620980 kb |
| Host | smart-3f324f12-4f40-4712-8cf0-d07b5ac3f981 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3756980172 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_rma_unlocked.3756980172 |
| Directory | /workspace/1.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_auto_mode.3845503715 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4950941868 ps |
| CPU time | 993.71 seconds |
| Started | Jul 31 08:24:45 PM PDT 24 |
| Finished | Jul 31 08:41:19 PM PDT 24 |
| Peak memory | 610104 kb |
| Host | smart-9c473932-7eb8-44d7-ad1d-53bc90378688 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845503715 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ auto_mode.3845503715 |
| Directory | /workspace/1.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/95.chip_sw_all_escalation_resets.2002082150 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 5284180818 ps |
| CPU time | 570.03 seconds |
| Started | Jul 31 08:48:29 PM PDT 24 |
| Finished | Jul 31 08:57:59 PM PDT 24 |
| Peak memory | 650336 kb |
| Host | smart-9966be39-49b5-4913-a891-d6087fb09510 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2002082150 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.2002082150 |
| Directory | /workspace/95.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_all_escalation_resets.1260113759 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 4387872292 ps |
| CPU time | 562.7 seconds |
| Started | Jul 31 08:36:46 PM PDT 24 |
| Finished | Jul 31 08:46:09 PM PDT 24 |
| Peak memory | 650868 kb |
| Host | smart-9937544c-0fe5-4bd3-abc4-9c0760059a43 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1260113759 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.1260113759 |
| Directory | /workspace/4.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_testunlock0.2081580074 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 7915946428 ps |
| CPU time | 892.8 seconds |
| Started | Jul 31 08:36:50 PM PDT 24 |
| Finished | Jul 31 08:51:43 PM PDT 24 |
| Peak memory | 631724 kb |
| Host | smart-f89a5467-7d5b-4e79-b5ef-202da82cacd2 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2081580074 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_testunlock0.2081580074 |
| Directory | /workspace/3.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.3337124796 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 4162132707 ps |
| CPU time | 534.47 seconds |
| Started | Jul 31 08:04:09 PM PDT 24 |
| Finished | Jul 31 08:13:04 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-ad016f2d-7d86-4c19-ba85-47c6dd7121d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337124796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all _with_rand_reset.3337124796 |
| Directory | /workspace/94.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_tl_errors.2496370464 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 4592176600 ps |
| CPU time | 330.85 seconds |
| Started | Jul 31 07:45:50 PM PDT 24 |
| Finished | Jul 31 07:51:21 PM PDT 24 |
| Peak memory | 599648 kb |
| Host | smart-e1efe49f-e487-467f-b789-b633a82dab1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496370464 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_tl_errors.2496370464 |
| Directory | /workspace/3.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_data_integrity_escalation.1921926361 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 5529482218 ps |
| CPU time | 738.47 seconds |
| Started | Jul 31 08:14:45 PM PDT 24 |
| Finished | Jul 31 08:27:04 PM PDT 24 |
| Peak memory | 610904 kb |
| Host | smart-111b2b95-e7b0-468e-a37b-a2d1ffb0244d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1921926361 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.1921926361 |
| Directory | /workspace/0.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_0.1671442576 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 6448748038 ps |
| CPU time | 1306.18 seconds |
| Started | Jul 31 08:23:56 PM PDT 24 |
| Finished | Jul 31 08:45:42 PM PDT 24 |
| Peak memory | 609856 kb |
| Host | smart-0bca6fe4-07ac-4c65-b505-bcc7b05ab5aa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671442576 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_plic_all_irqs_0.1671442576 |
| Directory | /workspace/1.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1842228672 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 8922307728 ps |
| CPU time | 1231.14 seconds |
| Started | Jul 31 08:39:07 PM PDT 24 |
| Finished | Jul 31 08:59:39 PM PDT 24 |
| Peak memory | 619732 kb |
| Host | smart-336077f8-8f8d-4740-b46d-686efaded7c1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842228672 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.1842228672 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2154426327 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 7186128120 ps |
| CPU time | 1014.28 seconds |
| Started | Jul 31 08:16:38 PM PDT 24 |
| Finished | Jul 31 08:33:33 PM PDT 24 |
| Peak memory | 610228 kb |
| Host | smart-77db50e4-2754-49cc-a2df-32dd0410eee4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21544263 27 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.2154426327 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.1178150572 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 2937438961 ps |
| CPU time | 163.67 seconds |
| Started | Jul 31 08:12:57 PM PDT 24 |
| Finished | Jul 31 08:15:41 PM PDT 24 |
| Peak memory | 620000 kb |
| Host | smart-73aa2a5b-c16c-49fe-9da0-4fc56d3b0e1b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11781505 72 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.1178150572 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_wake.1092605514 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 2789916130 ps |
| CPU time | 219.1 seconds |
| Started | Jul 31 08:16:00 PM PDT 24 |
| Finished | Jul 31 08:19:40 PM PDT 24 |
| Peak memory | 609432 kb |
| Host | smart-3c1820f5-422c-4d35-a5bb-0119ba943c34 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092605514 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.1092605514 |
| Directory | /workspace/1.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.1813882031 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 6372349000 ps |
| CPU time | 371.88 seconds |
| Started | Jul 31 07:45:15 PM PDT 24 |
| Finished | Jul 31 07:51:27 PM PDT 24 |
| Peak memory | 662112 kb |
| Host | smart-3b57d92f-ef68-4aae-88d0-4bbc6c5c971b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813882031 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_hw_r eset.1813882031 |
| Directory | /workspace/0.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_wake.2274632722 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 6689513600 ps |
| CPU time | 581.74 seconds |
| Started | Jul 31 08:27:44 PM PDT 24 |
| Finished | Jul 31 08:37:26 PM PDT 24 |
| Peak memory | 610892 kb |
| Host | smart-9ea23cec-c577-4631-b23c-ed099c8c79bc |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274632722 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.2274632722 |
| Directory | /workspace/2.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_retention.2496495989 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 4337500546 ps |
| CPU time | 333.15 seconds |
| Started | Jul 31 08:11:59 PM PDT 24 |
| Finished | Jul 31 08:17:33 PM PDT 24 |
| Peak memory | 610416 kb |
| Host | smart-c5160fa5-68c0-4f4f-89fd-17f7ac1aaa28 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496495989 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_retention.2496495989 |
| Directory | /workspace/0.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.1697860940 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 51269535093 ps |
| CPU time | 5975.19 seconds |
| Started | Jul 31 08:14:24 PM PDT 24 |
| Finished | Jul 31 09:54:01 PM PDT 24 |
| Peak memory | 620712 kb |
| Host | smart-f193c1af-bd37-4b5e-bcea-c53d81cc1f94 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697860940 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_dev.1697860940 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_20.3308747209 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 4304579084 ps |
| CPU time | 872.8 seconds |
| Started | Jul 31 08:33:22 PM PDT 24 |
| Finished | Jul 31 08:47:55 PM PDT 24 |
| Peak memory | 610012 kb |
| Host | smart-0988ad3c-9ad5-4acc-a221-db9eb4114f78 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308747209 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_20.3308747209 |
| Directory | /workspace/2.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.4146125510 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 8713990852 ps |
| CPU time | 473.34 seconds |
| Started | Jul 31 07:53:24 PM PDT 24 |
| Finished | Jul 31 08:01:17 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-c6ae47d7-a9d7-4c6c-91e3-6f92229830d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146125510 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_al l_with_reset_error.4146125510 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_tl_errors.453730146 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 4525714399 ps |
| CPU time | 316.96 seconds |
| Started | Jul 31 07:46:36 PM PDT 24 |
| Finished | Jul 31 07:51:53 PM PDT 24 |
| Peak memory | 603724 kb |
| Host | smart-380c1179-e8f8-4af0-a303-2dd631c58513 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453730146 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_tl_errors.453730146 |
| Directory | /workspace/5.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1171991010 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 3568365076 ps |
| CPU time | 418.18 seconds |
| Started | Jul 31 08:13:19 PM PDT 24 |
| Finished | Jul 31 08:20:17 PM PDT 24 |
| Peak memory | 609772 kb |
| Host | smart-f4228802-3997-47df-b1fc-70073351a744 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_aon_pullup_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117199 1010 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_aon_pullup.1171991010 |
| Directory | /workspace/0.chip_sw_usbdev_aon_pullup/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.2108259204 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 14781325316 ps |
| CPU time | 3209.57 seconds |
| Started | Jul 31 08:31:58 PM PDT 24 |
| Finished | Jul 31 09:25:28 PM PDT 24 |
| Peak memory | 611288 kb |
| Host | smart-a3a46289-a3a3-4b7f-a5e7-159a6caa8d3a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108259204 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_ shutdown_exception_c.2108259204 |
| Directory | /workspace/1.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.1389866201 |
| Short name | T1326 |
| Test name | |
| Test status | |
| Simulation time | 43295734120 ps |
| CPU time | 5093.18 seconds |
| Started | Jul 31 08:27:53 PM PDT 24 |
| Finished | Jul 31 09:52:47 PM PDT 24 |
| Peak memory | 619688 kb |
| Host | smart-50382172-a412-4074-a349-b0a6a6ae77e4 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1389866201 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_rma_unlocked.1389866201 |
| Directory | /workspace/2.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.2040139659 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 8783406205 ps |
| CPU time | 648.09 seconds |
| Started | Jul 31 07:57:26 PM PDT 24 |
| Finished | Jul 31 08:08:15 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-8c20bafa-be19-4ff4-8a6b-50da14eda0aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040139659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all _with_rand_reset.2040139659 |
| Directory | /workspace/51.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_0.2023727872 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 6351830336 ps |
| CPU time | 1349.67 seconds |
| Started | Jul 31 08:16:12 PM PDT 24 |
| Finished | Jul 31 08:38:44 PM PDT 24 |
| Peak memory | 610112 kb |
| Host | smart-2aa79eb2-9249-4b3b-9eea-423254c9810e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023727872 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_plic_all_irqs_0.2023727872 |
| Directory | /workspace/0.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_tl_errors.625085491 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 3586612566 ps |
| CPU time | 203.33 seconds |
| Started | Jul 31 07:50:13 PM PDT 24 |
| Finished | Jul 31 07:53:36 PM PDT 24 |
| Peak memory | 603668 kb |
| Host | smart-3de39d14-1f04-4372-8b58-9f333e91318d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625085491 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_tl_errors.625085491 |
| Directory | /workspace/17.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1358319004 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 3426289670 ps |
| CPU time | 424.71 seconds |
| Started | Jul 31 08:15:53 PM PDT 24 |
| Finished | Jul 31 08:22:58 PM PDT 24 |
| Peak memory | 620060 kb |
| Host | smart-06b70d16-0e2c-4e3b-bb11-2c8bf8f53948 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1 358319004 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.1358319004 |
| Directory | /workspace/0.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.1662747407 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4456993280 ps |
| CPU time | 625.39 seconds |
| Started | Jul 31 08:27:28 PM PDT 24 |
| Finished | Jul 31 08:37:54 PM PDT 24 |
| Peak memory | 624224 kb |
| Host | smart-816b5766-d09c-46ae-81d8-53c537dfdde0 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662747407 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.1662747407 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1565497003 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 6497732068 ps |
| CPU time | 671.78 seconds |
| Started | Jul 31 08:22:32 PM PDT 24 |
| Finished | Jul 31 08:33:44 PM PDT 24 |
| Peak memory | 609416 kb |
| Host | smart-ddd4e914-78d7-4eaf-be24-c0df50318543 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15654970 03 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.1565497003 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.2531927026 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 22325498959 ps |
| CPU time | 3272.5 seconds |
| Started | Jul 31 08:36:01 PM PDT 24 |
| Finished | Jul 31 09:30:35 PM PDT 24 |
| Peak memory | 610776 kb |
| Host | smart-b650dd9b-d23a-4621-8855-b639db420f5d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531927026 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_rst_inputs.2531927026 |
| Directory | /workspace/2.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.464943229 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 15545431998 ps |
| CPU time | 763.9 seconds |
| Started | Jul 31 07:52:12 PM PDT 24 |
| Finished | Jul 31 08:04:56 PM PDT 24 |
| Peak memory | 576804 kb |
| Host | smart-5967cacd-dd06-428e-9cf5-6de1b89e65f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464943229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_ with_rand_reset.464943229 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.2684740195 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 59480544800 ps |
| CPU time | 10971.1 seconds |
| Started | Jul 31 08:27:38 PM PDT 24 |
| Finished | Jul 31 11:30:30 PM PDT 24 |
| Peak memory | 624812 kb |
| Host | smart-ed67162c-c9a6-4342-bc53-3e71bc03f1af |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=2684740195 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_exit_test_unlocked_bootstrap.2684740195 |
| Directory | /workspace/2.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_10.1648736813 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 3477030934 ps |
| CPU time | 487.03 seconds |
| Started | Jul 31 08:23:22 PM PDT 24 |
| Finished | Jul 31 08:31:29 PM PDT 24 |
| Peak memory | 608540 kb |
| Host | smart-dc1fae56-b083-4de9-ad11-6bbf0b25d951 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648736813 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_10.1648736813 |
| Directory | /workspace/1.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2365236050 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 2312185336 ps |
| CPU time | 101.6 seconds |
| Started | Jul 31 08:11:39 PM PDT 24 |
| Finished | Jul 31 08:13:21 PM PDT 24 |
| Peak memory | 623080 kb |
| Host | smart-b60355b9-c78b-4849-8a98-8df501e1e878 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365236050 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.2365236050 |
| Directory | /workspace/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.401773594 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 78621022820 ps |
| CPU time | 13494.9 seconds |
| Started | Jul 31 08:13:59 PM PDT 24 |
| Finished | Jul 31 11:58:55 PM PDT 24 |
| Peak memory | 635064 kb |
| Host | smart-5a81cef9-ec9e-4b8a-b4ab-5fe75dcd9b4a |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=401773594 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_bootstrap.401773594 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all.2784324594 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 21123228988 ps |
| CPU time | 822.27 seconds |
| Started | Jul 31 07:47:11 PM PDT 24 |
| Finished | Jul 31 08:00:53 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-23b1c88b-c504-4e59-bb3f-a969f7861129 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784324594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.2784324594 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.1400872038 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 12083097429 ps |
| CPU time | 659.51 seconds |
| Started | Jul 31 07:56:55 PM PDT 24 |
| Finished | Jul 31 08:07:55 PM PDT 24 |
| Peak memory | 576800 kb |
| Host | smart-2dbfbee2-a209-46b2-834e-ae1e3652bc93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400872038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all _with_rand_reset.1400872038 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/75.chip_sw_all_escalation_resets.872155379 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 5414416060 ps |
| CPU time | 507.33 seconds |
| Started | Jul 31 08:46:17 PM PDT 24 |
| Finished | Jul 31 08:54:44 PM PDT 24 |
| Peak memory | 650304 kb |
| Host | smart-3f22bdc7-88bd-4ba7-b2df-bfc64517ee6f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 872155379 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.872155379 |
| Directory | /workspace/75.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.3935751708 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 1024888371 ps |
| CPU time | 433.95 seconds |
| Started | Jul 31 07:59:07 PM PDT 24 |
| Finished | Jul 31 08:06:21 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-a0250aff-0f51-4e08-a23d-453b1748d35a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935751708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all _with_rand_reset.3935751708 |
| Directory | /workspace/62.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/20.chip_tl_errors.3321973801 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 3010162576 ps |
| CPU time | 269.85 seconds |
| Started | Jul 31 07:51:00 PM PDT 24 |
| Finished | Jul 31 07:55:30 PM PDT 24 |
| Peak memory | 599764 kb |
| Host | smart-dd3b29ef-7e50-4d63-8e41-98faa886d408 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321973801 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.chip_tl_errors.3321973801 |
| Directory | /workspace/20.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2674517698 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 3936915937 ps |
| CPU time | 708.59 seconds |
| Started | Jul 31 08:16:14 PM PDT 24 |
| Finished | Jul 31 08:28:03 PM PDT 24 |
| Peak memory | 609920 kb |
| Host | smart-93cc29d6-fa9e-4a8d-b0ff-1fa5e54e63f2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2674517698 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.2674517698 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2723752466 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 4104377608 ps |
| CPU time | 625.77 seconds |
| Started | Jul 31 08:14:29 PM PDT 24 |
| Finished | Jul 31 08:24:55 PM PDT 24 |
| Peak memory | 612896 kb |
| Host | smart-9fb7db91-04ed-4ebf-9e57-593379eb7dd6 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723752466 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.2723752466 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.2614781808 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 3912972904 ps |
| CPU time | 360.05 seconds |
| Started | Jul 31 07:59:26 PM PDT 24 |
| Finished | Jul 31 08:05:26 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-93b12138-6606-4274-8e96-8ff0fb8b4590 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614781808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all _with_rand_reset.2614781808 |
| Directory | /workspace/64.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_mem_access.2916946591 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 13456658696 ps |
| CPU time | 1715.5 seconds |
| Started | Jul 31 08:26:27 PM PDT 24 |
| Finished | Jul 31 08:55:03 PM PDT 24 |
| Peak memory | 607980 kb |
| Host | smart-f0412a55-e1a7-4e8b-87b7-36e03129e953 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916946591 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.2 916946591 |
| Directory | /workspace/2.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_20.1642092287 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 4628823000 ps |
| CPU time | 794.7 seconds |
| Started | Jul 31 08:24:27 PM PDT 24 |
| Finished | Jul 31 08:37:42 PM PDT 24 |
| Peak memory | 608888 kb |
| Host | smart-ea325eae-4e37-4a55-9281-67daef5b5b0e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642092287 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_20.1642092287 |
| Directory | /workspace/1.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.2968880868 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 335898686 ps |
| CPU time | 112.82 seconds |
| Started | Jul 31 07:54:14 PM PDT 24 |
| Finished | Jul 31 07:56:07 PM PDT 24 |
| Peak memory | 576808 kb |
| Host | smart-4e4d38b8-9944-4df8-8a41-7d8bcb50b0e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968880868 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_al l_with_reset_error.2968880868 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.1247689651 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 732418132 ps |
| CPU time | 252.25 seconds |
| Started | Jul 31 08:01:19 PM PDT 24 |
| Finished | Jul 31 08:05:31 PM PDT 24 |
| Peak memory | 576636 kb |
| Host | smart-aff7e2ca-bf27-442b-af51-319ec678e316 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247689651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all _with_rand_reset.1247689651 |
| Directory | /workspace/75.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_csrng.1135182278 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 6982874630 ps |
| CPU time | 1251.78 seconds |
| Started | Jul 31 08:22:19 PM PDT 24 |
| Finished | Jul 31 08:43:12 PM PDT 24 |
| Peak memory | 610100 kb |
| Host | smart-ddec8144-f5c2-4906-8f5e-648f4ad8f780 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1135182278 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.1135182278 |
| Directory | /workspace/1.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.3764395489 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 9770532774 ps |
| CPU time | 718.02 seconds |
| Started | Jul 31 07:48:45 PM PDT 24 |
| Finished | Jul 31 08:00:43 PM PDT 24 |
| Peak memory | 653020 kb |
| Host | smart-c2d8ac45-65b2-4968-a613-d3e3a316917c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764395489 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 11.chip_csr_mem_rw_with_rand_reset.3764395489 |
| Directory | /workspace/11.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/default/99.chip_sw_all_escalation_resets.1996493859 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 4477398616 ps |
| CPU time | 517.87 seconds |
| Started | Jul 31 08:45:01 PM PDT 24 |
| Finished | Jul 31 08:53:39 PM PDT 24 |
| Peak memory | 651056 kb |
| Host | smart-f055f452-b508-4297-9bbe-042e98cf4830 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1996493859 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.1996493859 |
| Directory | /workspace/99.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_config_host.3738432441 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 8157210240 ps |
| CPU time | 2129.67 seconds |
| Started | Jul 31 08:13:05 PM PDT 24 |
| Finished | Jul 31 08:48:35 PM PDT 24 |
| Peak memory | 608964 kb |
| Host | smart-9fa2dd9d-4d20-4c96-a46f-9f343af7bd94 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_config_host_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37384 32441 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_config_host.3738432441 |
| Directory | /workspace/0.chip_sw_usbdev_config_host/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_tl_errors.35122974 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 5457042076 ps |
| CPU time | 454.5 seconds |
| Started | Jul 31 07:48:40 PM PDT 24 |
| Finished | Jul 31 07:56:15 PM PDT 24 |
| Peak memory | 603736 kb |
| Host | smart-b3c02b74-af78-4f25-824b-6200f0827ee9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35122974 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_tl_errors.35122974 |
| Directory | /workspace/12.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1093741110 |
| Short name | T1327 |
| Test name | |
| Test status | |
| Simulation time | 43630537525 ps |
| CPU time | 5051.52 seconds |
| Started | Jul 31 08:14:36 PM PDT 24 |
| Finished | Jul 31 09:38:49 PM PDT 24 |
| Peak memory | 619800 kb |
| Host | smart-e5dcc7a0-4556-49c3-8a6b-e953051e185b |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1093741110 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_rma_unlocked.1093741110 |
| Directory | /workspace/0.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1557938723 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 2481182893 ps |
| CPU time | 193.26 seconds |
| Started | Jul 31 08:31:56 PM PDT 24 |
| Finished | Jul 31 08:35:09 PM PDT 24 |
| Peak memory | 623900 kb |
| Host | smart-e6c75cb9-453c-485c-b12d-eab7803e6704 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557938723 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.1557938723 |
| Directory | /workspace/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1384417166 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4631114895 ps |
| CPU time | 579.59 seconds |
| Started | Jul 31 08:14:58 PM PDT 24 |
| Finished | Jul 31 08:24:38 PM PDT 24 |
| Peak memory | 624796 kb |
| Host | smart-5f77b3f5-68c5-4e2e-ad94-fa11a6768112 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384417166 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.1384417166 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/19.chip_sw_all_escalation_resets.1559494964 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 6333586486 ps |
| CPU time | 720.3 seconds |
| Started | Jul 31 08:42:21 PM PDT 24 |
| Finished | Jul 31 08:54:21 PM PDT 24 |
| Peak memory | 650268 kb |
| Host | smart-63ad75af-b5d4-4b73-a48f-6cd3c14546dd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1559494964 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.1559494964 |
| Directory | /workspace/19.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_error.1571833826 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 5150103653 ps |
| CPU time | 168.48 seconds |
| Started | Jul 31 07:56:35 PM PDT 24 |
| Finished | Jul 31 07:59:24 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-44afc0d9-d72c-4832-b487-18bc63f0e99d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571833826 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.1571833826 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all.3272780564 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 3353184730 ps |
| CPU time | 302.52 seconds |
| Started | Jul 31 07:53:05 PM PDT 24 |
| Finished | Jul 31 07:58:08 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-024bb57f-f9d4-48a6-b11a-4d3802fd8348 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272780564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.3272780564 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3481125463 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 13688344024 ps |
| CPU time | 1979.19 seconds |
| Started | Jul 31 08:21:41 PM PDT 24 |
| Finished | Jul 31 08:54:41 PM PDT 24 |
| Peak memory | 610900 kb |
| Host | smart-2fb9995c-fac0-41f1-97a7-17e575e7264f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=3481125463 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.3481125463 |
| Directory | /workspace/1.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.927204541 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 8177631516 ps |
| CPU time | 1877.29 seconds |
| Started | Jul 31 08:17:18 PM PDT 24 |
| Finished | Jul 31 08:48:36 PM PDT 24 |
| Peak memory | 624536 kb |
| Host | smart-88bca919-ab4b-4b1f-9fa8-f56097193be5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=927204541 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.927204541 |
| Directory | /workspace/1.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2770630706 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 4065221456 ps |
| CPU time | 461.78 seconds |
| Started | Jul 31 08:45:15 PM PDT 24 |
| Finished | Jul 31 08:52:57 PM PDT 24 |
| Peak memory | 649204 kb |
| Host | smart-f09e0cba-868a-4f05-8fb1-e6bce8b980b1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770630706 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2770630706 |
| Directory | /workspace/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.1835014715 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 4849635269 ps |
| CPU time | 566.59 seconds |
| Started | Jul 31 08:27:29 PM PDT 24 |
| Finished | Jul 31 08:36:56 PM PDT 24 |
| Peak memory | 624288 kb |
| Host | smart-8acdf032-1b68-4a0c-95a1-38c64f799c50 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835014715 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.1835014715 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.3783578206 |
| Short name | T2416 |
| Test name | |
| Test status | |
| Simulation time | 19949216191 ps |
| CPU time | 1011.64 seconds |
| Started | Jul 31 07:50:08 PM PDT 24 |
| Finished | Jul 31 08:07:00 PM PDT 24 |
| Peak memory | 576960 kb |
| Host | smart-db454ccc-d4ce-4750-a8ca-fd805689795f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783578206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all _with_rand_reset.3783578206 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.202008840 |
| Short name | T2713 |
| Test name | |
| Test status | |
| Simulation time | 9912342464 ps |
| CPU time | 490.19 seconds |
| Started | Jul 31 07:46:05 PM PDT 24 |
| Finished | Jul 31 07:54:15 PM PDT 24 |
| Peak memory | 576792 kb |
| Host | smart-7813c989-4eae-4be6-b037-bcfa5300d574 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202008840 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_ with_reset_error.202008840 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2591602891 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 4026082956 ps |
| CPU time | 368.77 seconds |
| Started | Jul 31 08:13:57 PM PDT 24 |
| Finished | Jul 31 08:20:06 PM PDT 24 |
| Peak memory | 648748 kb |
| Host | smart-81f2b1a6-0013-44b5-b57b-2265c0208ea1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591602891 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_alert_handler_lpg_sleep_mode_alerts.2591602891 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.339205105 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 4445239928 ps |
| CPU time | 468.61 seconds |
| Started | Jul 31 08:21:27 PM PDT 24 |
| Finished | Jul 31 08:29:17 PM PDT 24 |
| Peak memory | 649100 kb |
| Host | smart-bcc1abf6-3350-48cf-a5b0-f5f3e30cde12 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339205105 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _alert_handler_lpg_sleep_mode_alerts.339205105 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2562114400 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 4529296714 ps |
| CPU time | 466.12 seconds |
| Started | Jul 31 08:40:30 PM PDT 24 |
| Finished | Jul 31 08:48:17 PM PDT 24 |
| Peak memory | 649280 kb |
| Host | smart-aab4820c-5f0f-4585-bf40-daaefd724893 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562114400 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2562114400 |
| Directory | /workspace/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.994274759 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 3263197256 ps |
| CPU time | 452.04 seconds |
| Started | Jul 31 08:42:11 PM PDT 24 |
| Finished | Jul 31 08:49:44 PM PDT 24 |
| Peak memory | 649288 kb |
| Host | smart-7ac2d685-4e96-4097-ae90-b9c83a74e648 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994274759 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_s w_alert_handler_lpg_sleep_mode_alerts.994274759 |
| Directory | /workspace/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/11.chip_sw_all_escalation_resets.4163696096 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 4865669270 ps |
| CPU time | 594.61 seconds |
| Started | Jul 31 08:40:02 PM PDT 24 |
| Finished | Jul 31 08:49:56 PM PDT 24 |
| Peak memory | 649940 kb |
| Host | smart-5c1ff090-608a-4d57-920a-5be97f1a8fd4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4163696096 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.4163696096 |
| Directory | /workspace/11.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2376397670 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 4031694760 ps |
| CPU time | 445.14 seconds |
| Started | Jul 31 08:42:12 PM PDT 24 |
| Finished | Jul 31 08:49:38 PM PDT 24 |
| Peak memory | 649088 kb |
| Host | smart-e3c9d963-9eb8-45b3-9587-6806a85949b5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376397670 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2376397670 |
| Directory | /workspace/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.135102393 |
| Short name | T1374 |
| Test name | |
| Test status | |
| Simulation time | 3863943224 ps |
| CPU time | 436.9 seconds |
| Started | Jul 31 08:42:32 PM PDT 24 |
| Finished | Jul 31 08:49:49 PM PDT 24 |
| Peak memory | 649144 kb |
| Host | smart-a8f47239-327e-4ef2-800e-2091b3ee7e7b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135102393 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_s w_alert_handler_lpg_sleep_mode_alerts.135102393 |
| Directory | /workspace/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/14.chip_sw_all_escalation_resets.834732795 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 5477756826 ps |
| CPU time | 510.5 seconds |
| Started | Jul 31 08:42:57 PM PDT 24 |
| Finished | Jul 31 08:51:28 PM PDT 24 |
| Peak memory | 650028 kb |
| Host | smart-8bc221b9-e266-4f2a-90c8-ea04655121a0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 834732795 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.834732795 |
| Directory | /workspace/14.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.4003131851 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 3859788390 ps |
| CPU time | 417.65 seconds |
| Started | Jul 31 08:41:40 PM PDT 24 |
| Finished | Jul 31 08:48:38 PM PDT 24 |
| Peak memory | 648800 kb |
| Host | smart-5dca59cb-63af-4ba0-9c8f-84a0bf03969d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003131851 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4003131851 |
| Directory | /workspace/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/15.chip_sw_all_escalation_resets.561797616 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 5200661300 ps |
| CPU time | 639 seconds |
| Started | Jul 31 08:41:55 PM PDT 24 |
| Finished | Jul 31 08:52:34 PM PDT 24 |
| Peak memory | 649840 kb |
| Host | smart-bccc557c-431f-4076-9f87-e106415bfcaa |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 561797616 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.561797616 |
| Directory | /workspace/15.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.695767751 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 3531371932 ps |
| CPU time | 385.63 seconds |
| Started | Jul 31 08:41:40 PM PDT 24 |
| Finished | Jul 31 08:48:07 PM PDT 24 |
| Peak memory | 648496 kb |
| Host | smart-cfcb09ba-83a4-4362-922c-bfab35f2159f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695767751 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_s w_alert_handler_lpg_sleep_mode_alerts.695767751 |
| Directory | /workspace/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/16.chip_sw_all_escalation_resets.512638349 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 4840652852 ps |
| CPU time | 678.82 seconds |
| Started | Jul 31 08:42:29 PM PDT 24 |
| Finished | Jul 31 08:53:48 PM PDT 24 |
| Peak memory | 650268 kb |
| Host | smart-0d0b5141-e4e0-49fa-9abe-57915dda9f93 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 512638349 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.512638349 |
| Directory | /workspace/16.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2262783764 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 4298859150 ps |
| CPU time | 413.23 seconds |
| Started | Jul 31 08:42:32 PM PDT 24 |
| Finished | Jul 31 08:49:26 PM PDT 24 |
| Peak memory | 649296 kb |
| Host | smart-ffacf8b0-c8b9-4989-83cc-17877728c8ce |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262783764 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2262783764 |
| Directory | /workspace/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/18.chip_sw_all_escalation_resets.2833294281 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 6248902816 ps |
| CPU time | 662.19 seconds |
| Started | Jul 31 08:41:15 PM PDT 24 |
| Finished | Jul 31 08:52:17 PM PDT 24 |
| Peak memory | 650728 kb |
| Host | smart-c879d12a-6b56-4a08-ab42-23ec46f67641 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2833294281 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.2833294281 |
| Directory | /workspace/18.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.4217043783 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 4041485922 ps |
| CPU time | 418.58 seconds |
| Started | Jul 31 08:43:30 PM PDT 24 |
| Finished | Jul 31 08:50:28 PM PDT 24 |
| Peak memory | 649240 kb |
| Host | smart-5688622b-5d5a-4ee5-97df-928cbd0ab4a2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217043783 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4217043783 |
| Directory | /workspace/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.1972288118 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 3553086138 ps |
| CPU time | 412.96 seconds |
| Started | Jul 31 08:36:53 PM PDT 24 |
| Finished | Jul 31 08:43:46 PM PDT 24 |
| Peak memory | 649100 kb |
| Host | smart-43cdfe3c-92c2-444f-9234-25021648fa4c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972288118 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s w_alert_handler_lpg_sleep_mode_alerts.1972288118 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.2527875417 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 3455208550 ps |
| CPU time | 403.89 seconds |
| Started | Jul 31 08:47:49 PM PDT 24 |
| Finished | Jul 31 08:54:33 PM PDT 24 |
| Peak memory | 649200 kb |
| Host | smart-a434bf8e-cf2a-4dbc-868d-130b1bc178cb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527875417 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2527875417 |
| Directory | /workspace/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/20.chip_sw_all_escalation_resets.293756219 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 5279373400 ps |
| CPU time | 846.8 seconds |
| Started | Jul 31 08:42:30 PM PDT 24 |
| Finished | Jul 31 08:56:37 PM PDT 24 |
| Peak memory | 649968 kb |
| Host | smart-10b3c7af-4cf0-4b3d-a947-60969aa971ef |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 293756219 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.293756219 |
| Directory | /workspace/20.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2445001979 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 3669625652 ps |
| CPU time | 341.34 seconds |
| Started | Jul 31 08:41:51 PM PDT 24 |
| Finished | Jul 31 08:47:33 PM PDT 24 |
| Peak memory | 648864 kb |
| Host | smart-a36fdc63-bcd3-4898-98ee-0a39a5eaf096 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445001979 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2445001979 |
| Directory | /workspace/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.1814947992 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 3583145324 ps |
| CPU time | 362.15 seconds |
| Started | Jul 31 08:43:22 PM PDT 24 |
| Finished | Jul 31 08:49:24 PM PDT 24 |
| Peak memory | 649004 kb |
| Host | smart-5c85e450-497a-4f13-9d97-ac3d7134fb10 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814947992 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1814947992 |
| Directory | /workspace/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/23.chip_sw_all_escalation_resets.2917080651 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 5618637208 ps |
| CPU time | 598.67 seconds |
| Started | Jul 31 08:41:26 PM PDT 24 |
| Finished | Jul 31 08:51:25 PM PDT 24 |
| Peak memory | 650508 kb |
| Host | smart-5cabbeb0-1337-4233-9db3-265fc44d2627 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2917080651 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.2917080651 |
| Directory | /workspace/23.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2579833400 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 3382767112 ps |
| CPU time | 350.79 seconds |
| Started | Jul 31 08:42:39 PM PDT 24 |
| Finished | Jul 31 08:48:30 PM PDT 24 |
| Peak memory | 648844 kb |
| Host | smart-9e23cf6e-54e3-4be8-9bd9-3dd6968d080d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579833400 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2579833400 |
| Directory | /workspace/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/24.chip_sw_all_escalation_resets.673922421 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 5166235320 ps |
| CPU time | 663.82 seconds |
| Started | Jul 31 08:41:57 PM PDT 24 |
| Finished | Jul 31 08:53:01 PM PDT 24 |
| Peak memory | 650172 kb |
| Host | smart-a123938b-3c8b-42e0-8081-0e04e34f4d23 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 673922421 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.673922421 |
| Directory | /workspace/24.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.615706036 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 3586919980 ps |
| CPU time | 330.81 seconds |
| Started | Jul 31 08:42:31 PM PDT 24 |
| Finished | Jul 31 08:48:02 PM PDT 24 |
| Peak memory | 649108 kb |
| Host | smart-555a6e63-4c2f-4aa6-a4e3-b6909adc343a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615706036 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_s w_alert_handler_lpg_sleep_mode_alerts.615706036 |
| Directory | /workspace/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/25.chip_sw_all_escalation_resets.3225792241 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 4938965500 ps |
| CPU time | 581.11 seconds |
| Started | Jul 31 08:41:57 PM PDT 24 |
| Finished | Jul 31 08:51:39 PM PDT 24 |
| Peak memory | 650176 kb |
| Host | smart-461565ad-1343-43b0-aac6-ce6a1ccbc38a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3225792241 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.3225792241 |
| Directory | /workspace/25.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/26.chip_sw_all_escalation_resets.539890698 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 4713313700 ps |
| CPU time | 694.78 seconds |
| Started | Jul 31 08:41:02 PM PDT 24 |
| Finished | Jul 31 08:52:37 PM PDT 24 |
| Peak memory | 650172 kb |
| Host | smart-477aa6e3-c82d-4a6e-988b-0f34efe78c3d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 539890698 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.539890698 |
| Directory | /workspace/26.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.4099307073 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 3147171016 ps |
| CPU time | 395.74 seconds |
| Started | Jul 31 08:42:15 PM PDT 24 |
| Finished | Jul 31 08:48:51 PM PDT 24 |
| Peak memory | 649096 kb |
| Host | smart-3d0c7b35-ec54-4042-9bd7-d952da1ef6c5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099307073 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4099307073 |
| Directory | /workspace/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/27.chip_sw_all_escalation_resets.1969438892 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 6219747400 ps |
| CPU time | 701.49 seconds |
| Started | Jul 31 08:42:23 PM PDT 24 |
| Finished | Jul 31 08:54:05 PM PDT 24 |
| Peak memory | 649952 kb |
| Host | smart-0f1db7bc-2eb6-436c-a08f-025281ac0790 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1969438892 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.1969438892 |
| Directory | /workspace/27.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/28.chip_sw_all_escalation_resets.1930242679 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 5550334002 ps |
| CPU time | 725.62 seconds |
| Started | Jul 31 08:41:06 PM PDT 24 |
| Finished | Jul 31 08:53:11 PM PDT 24 |
| Peak memory | 650168 kb |
| Host | smart-37657e2a-608c-47fb-afa9-31bfa7d5f1c2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1930242679 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.1930242679 |
| Directory | /workspace/28.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/29.chip_sw_all_escalation_resets.3972970017 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 5382824390 ps |
| CPU time | 674.92 seconds |
| Started | Jul 31 08:42:46 PM PDT 24 |
| Finished | Jul 31 08:54:01 PM PDT 24 |
| Peak memory | 650304 kb |
| Host | smart-5258c4d1-5035-4491-bce8-efb6ba69888e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3972970017 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_all_escalation_resets.3972970017 |
| Directory | /workspace/29.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.811983468 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 3197699736 ps |
| CPU time | 411.83 seconds |
| Started | Jul 31 08:39:27 PM PDT 24 |
| Finished | Jul 31 08:46:19 PM PDT 24 |
| Peak memory | 648996 kb |
| Host | smart-04c446a5-493c-4ba0-a00c-b4e0de06b0c8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811983468 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw _alert_handler_lpg_sleep_mode_alerts.811983468 |
| Directory | /workspace/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/3.chip_sw_all_escalation_resets.2278399811 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 4808467130 ps |
| CPU time | 524.52 seconds |
| Started | Jul 31 08:36:10 PM PDT 24 |
| Finished | Jul 31 08:44:55 PM PDT 24 |
| Peak memory | 650328 kb |
| Host | smart-cb74e53a-4af4-4320-8bed-7090f8fc43c4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2278399811 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.2278399811 |
| Directory | /workspace/3.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3117256430 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 4008610032 ps |
| CPU time | 458.73 seconds |
| Started | Jul 31 08:41:52 PM PDT 24 |
| Finished | Jul 31 08:49:30 PM PDT 24 |
| Peak memory | 649172 kb |
| Host | smart-f4639f49-8eca-4426-8a5a-71b7645618a0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117256430 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3117256430 |
| Directory | /workspace/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3455834321 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 4066726522 ps |
| CPU time | 352.19 seconds |
| Started | Jul 31 08:41:48 PM PDT 24 |
| Finished | Jul 31 08:47:41 PM PDT 24 |
| Peak memory | 649032 kb |
| Host | smart-7df2e621-849c-4888-932a-d434e308e0db |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455834321 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3455834321 |
| Directory | /workspace/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1073060558 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 3599629852 ps |
| CPU time | 383.09 seconds |
| Started | Jul 31 08:42:48 PM PDT 24 |
| Finished | Jul 31 08:49:12 PM PDT 24 |
| Peak memory | 649040 kb |
| Host | smart-a711a28b-f685-4d65-80bd-577e8f444ddf |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073060558 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1073060558 |
| Directory | /workspace/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/33.chip_sw_all_escalation_resets.857353669 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 5937225512 ps |
| CPU time | 528.8 seconds |
| Started | Jul 31 08:41:50 PM PDT 24 |
| Finished | Jul 31 08:50:39 PM PDT 24 |
| Peak memory | 650360 kb |
| Host | smart-de9b8903-5447-40a6-89a5-08e0249899e3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 857353669 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.857353669 |
| Directory | /workspace/33.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.604568801 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 3446570118 ps |
| CPU time | 347.18 seconds |
| Started | Jul 31 08:43:20 PM PDT 24 |
| Finished | Jul 31 08:49:08 PM PDT 24 |
| Peak memory | 649184 kb |
| Host | smart-e69dd52a-7217-47c7-bee1-ff22ad3bb4e8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604568801 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_s w_alert_handler_lpg_sleep_mode_alerts.604568801 |
| Directory | /workspace/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/35.chip_sw_all_escalation_resets.3408821919 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 4750682844 ps |
| CPU time | 763.51 seconds |
| Started | Jul 31 08:41:32 PM PDT 24 |
| Finished | Jul 31 08:54:16 PM PDT 24 |
| Peak memory | 649916 kb |
| Host | smart-823ecc76-d08e-4380-9e8f-14a9b316287f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3408821919 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.3408821919 |
| Directory | /workspace/35.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.971067825 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 3911851272 ps |
| CPU time | 424.25 seconds |
| Started | Jul 31 08:43:44 PM PDT 24 |
| Finished | Jul 31 08:50:48 PM PDT 24 |
| Peak memory | 649148 kb |
| Host | smart-b11ef07d-98ae-476c-9ccf-715cd207af06 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971067825 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_s w_alert_handler_lpg_sleep_mode_alerts.971067825 |
| Directory | /workspace/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3363508706 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 3160096796 ps |
| CPU time | 356.67 seconds |
| Started | Jul 31 08:42:36 PM PDT 24 |
| Finished | Jul 31 08:48:33 PM PDT 24 |
| Peak memory | 648972 kb |
| Host | smart-3cbf9270-3a95-421b-9495-671c3d1f39f9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363508706 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3363508706 |
| Directory | /workspace/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/41.chip_sw_all_escalation_resets.3581410070 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 4541804182 ps |
| CPU time | 503.85 seconds |
| Started | Jul 31 08:43:36 PM PDT 24 |
| Finished | Jul 31 08:52:00 PM PDT 24 |
| Peak memory | 650468 kb |
| Host | smart-750d889d-3fab-493f-a73b-4bab86890dbc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3581410070 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.3581410070 |
| Directory | /workspace/41.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/42.chip_sw_all_escalation_resets.3612251616 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 4188075192 ps |
| CPU time | 537.94 seconds |
| Started | Jul 31 08:43:31 PM PDT 24 |
| Finished | Jul 31 08:52:29 PM PDT 24 |
| Peak memory | 650144 kb |
| Host | smart-669459ce-be6a-4164-9378-4555fee0bf8f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3612251616 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.3612251616 |
| Directory | /workspace/42.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/44.chip_sw_all_escalation_resets.837002635 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 6649855734 ps |
| CPU time | 777.81 seconds |
| Started | Jul 31 08:43:11 PM PDT 24 |
| Finished | Jul 31 08:56:09 PM PDT 24 |
| Peak memory | 650628 kb |
| Host | smart-fb856128-bf83-46c0-8f6d-231e13f4d3ff |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 837002635 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.837002635 |
| Directory | /workspace/44.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2119549834 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 3951482440 ps |
| CPU time | 439.22 seconds |
| Started | Jul 31 08:42:19 PM PDT 24 |
| Finished | Jul 31 08:49:38 PM PDT 24 |
| Peak memory | 649072 kb |
| Host | smart-7df40120-8de8-44e9-87ee-8e53edb0cbcb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119549834 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2119549834 |
| Directory | /workspace/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.678311207 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 3355258298 ps |
| CPU time | 357.58 seconds |
| Started | Jul 31 08:43:09 PM PDT 24 |
| Finished | Jul 31 08:49:07 PM PDT 24 |
| Peak memory | 648880 kb |
| Host | smart-6da5f0f8-5f87-4a0f-9d25-9c9b00241d91 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678311207 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_s w_alert_handler_lpg_sleep_mode_alerts.678311207 |
| Directory | /workspace/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/48.chip_sw_all_escalation_resets.820205214 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 6160172810 ps |
| CPU time | 625.37 seconds |
| Started | Jul 31 08:43:40 PM PDT 24 |
| Finished | Jul 31 08:54:06 PM PDT 24 |
| Peak memory | 650300 kb |
| Host | smart-2638e613-c2d9-4d70-a983-2021e522e92c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 820205214 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.820205214 |
| Directory | /workspace/48.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/5.chip_sw_all_escalation_resets.963271349 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 4277898140 ps |
| CPU time | 603.37 seconds |
| Started | Jul 31 08:38:14 PM PDT 24 |
| Finished | Jul 31 08:48:17 PM PDT 24 |
| Peak memory | 650368 kb |
| Host | smart-90fea157-21d5-42b6-84fa-8b39c521b408 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 963271349 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.963271349 |
| Directory | /workspace/5.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/51.chip_sw_all_escalation_resets.3280810574 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 4723340704 ps |
| CPU time | 641.5 seconds |
| Started | Jul 31 08:42:37 PM PDT 24 |
| Finished | Jul 31 08:53:18 PM PDT 24 |
| Peak memory | 650236 kb |
| Host | smart-bb5c9434-a877-47d6-ac2e-796e0e2a7d43 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3280810574 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.3280810574 |
| Directory | /workspace/51.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.521638453 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 3654169050 ps |
| CPU time | 339.52 seconds |
| Started | Jul 31 08:43:04 PM PDT 24 |
| Finished | Jul 31 08:48:44 PM PDT 24 |
| Peak memory | 648700 kb |
| Host | smart-0d4f2e50-46c8-48c8-9c4b-674c1e2c2c8d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521638453 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_s w_alert_handler_lpg_sleep_mode_alerts.521638453 |
| Directory | /workspace/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/54.chip_sw_all_escalation_resets.2507446875 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 4084423928 ps |
| CPU time | 540 seconds |
| Started | Jul 31 08:44:42 PM PDT 24 |
| Finished | Jul 31 08:53:42 PM PDT 24 |
| Peak memory | 650048 kb |
| Host | smart-9ff06b9a-53f6-4286-b910-b836115e5b71 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2507446875 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.2507446875 |
| Directory | /workspace/54.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.863991798 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 3874485190 ps |
| CPU time | 419.86 seconds |
| Started | Jul 31 08:43:34 PM PDT 24 |
| Finished | Jul 31 08:50:34 PM PDT 24 |
| Peak memory | 649332 kb |
| Host | smart-1ac44e52-8726-42f9-9df2-f6f63d481b6f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863991798 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_s w_alert_handler_lpg_sleep_mode_alerts.863991798 |
| Directory | /workspace/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/56.chip_sw_all_escalation_resets.1132354271 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 5227357844 ps |
| CPU time | 591.73 seconds |
| Started | Jul 31 08:44:18 PM PDT 24 |
| Finished | Jul 31 08:54:10 PM PDT 24 |
| Peak memory | 650204 kb |
| Host | smart-0ff10248-94bc-40d2-b88d-ed758ee293bf |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1132354271 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.1132354271 |
| Directory | /workspace/56.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/57.chip_sw_all_escalation_resets.3239907579 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 6237687338 ps |
| CPU time | 656.45 seconds |
| Started | Jul 31 08:43:57 PM PDT 24 |
| Finished | Jul 31 08:54:54 PM PDT 24 |
| Peak memory | 650596 kb |
| Host | smart-0f919335-6f12-4732-bd10-49825507aa7a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3239907579 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.3239907579 |
| Directory | /workspace/57.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/59.chip_sw_all_escalation_resets.3900279684 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 5546287200 ps |
| CPU time | 611.2 seconds |
| Started | Jul 31 08:46:15 PM PDT 24 |
| Finished | Jul 31 08:56:26 PM PDT 24 |
| Peak memory | 650464 kb |
| Host | smart-fcfefe03-c730-469b-8a70-e2c4919cf7ec |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3900279684 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.3900279684 |
| Directory | /workspace/59.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.4092143030 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 4504334432 ps |
| CPU time | 422.68 seconds |
| Started | Jul 31 08:38:46 PM PDT 24 |
| Finished | Jul 31 08:45:48 PM PDT 24 |
| Peak memory | 649356 kb |
| Host | smart-a89faec2-fb8e-4ae5-af47-96a4059ca8b2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092143030 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_s w_alert_handler_lpg_sleep_mode_alerts.4092143030 |
| Directory | /workspace/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/61.chip_sw_all_escalation_resets.2102955488 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 5681435066 ps |
| CPU time | 587.59 seconds |
| Started | Jul 31 08:44:10 PM PDT 24 |
| Finished | Jul 31 08:53:58 PM PDT 24 |
| Peak memory | 649972 kb |
| Host | smart-30a7c9d1-6273-423c-957e-eb4b76fb9ecf |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2102955488 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.2102955488 |
| Directory | /workspace/61.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/66.chip_sw_all_escalation_resets.531520094 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 4894947030 ps |
| CPU time | 575.46 seconds |
| Started | Jul 31 08:45:25 PM PDT 24 |
| Finished | Jul 31 08:55:01 PM PDT 24 |
| Peak memory | 649980 kb |
| Host | smart-99dce794-6508-4860-add1-97f0a4e7a9c0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 531520094 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.531520094 |
| Directory | /workspace/66.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3303201806 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 3315717368 ps |
| CPU time | 278.8 seconds |
| Started | Jul 31 08:43:12 PM PDT 24 |
| Finished | Jul 31 08:47:51 PM PDT 24 |
| Peak memory | 648996 kb |
| Host | smart-55843d75-bc4a-4db0-ba86-9e7c3dd00e62 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303201806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3303201806 |
| Directory | /workspace/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.223740767 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 3709703240 ps |
| CPU time | 368.62 seconds |
| Started | Jul 31 08:44:20 PM PDT 24 |
| Finished | Jul 31 08:50:29 PM PDT 24 |
| Peak memory | 648868 kb |
| Host | smart-1255e182-57d2-4287-a693-4be6631839ac |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223740767 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_s w_alert_handler_lpg_sleep_mode_alerts.223740767 |
| Directory | /workspace/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3169286907 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 3700142292 ps |
| CPU time | 372.21 seconds |
| Started | Jul 31 08:43:44 PM PDT 24 |
| Finished | Jul 31 08:49:56 PM PDT 24 |
| Peak memory | 649048 kb |
| Host | smart-d700f79f-8c49-49cb-a951-96df198008ca |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169286907 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3169286907 |
| Directory | /workspace/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.130299021 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 3665947240 ps |
| CPU time | 293.11 seconds |
| Started | Jul 31 08:46:56 PM PDT 24 |
| Finished | Jul 31 08:51:49 PM PDT 24 |
| Peak memory | 649012 kb |
| Host | smart-ab2f47fa-ee12-40ea-9e3d-c15d4e895f4d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130299021 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_s w_alert_handler_lpg_sleep_mode_alerts.130299021 |
| Directory | /workspace/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1270725740 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 3689015044 ps |
| CPU time | 334.07 seconds |
| Started | Jul 31 08:46:34 PM PDT 24 |
| Finished | Jul 31 08:52:08 PM PDT 24 |
| Peak memory | 649012 kb |
| Host | smart-ae50e496-f191-423a-ae0e-36126058c485 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270725740 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1270725740 |
| Directory | /workspace/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2803472795 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 3239442376 ps |
| CPU time | 383.19 seconds |
| Started | Jul 31 08:46:54 PM PDT 24 |
| Finished | Jul 31 08:53:17 PM PDT 24 |
| Peak memory | 648988 kb |
| Host | smart-2791ecad-6371-4659-bdf4-3d8ab9c87d93 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803472795 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2803472795 |
| Directory | /workspace/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/84.chip_sw_all_escalation_resets.3126156966 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 6029980200 ps |
| CPU time | 590.73 seconds |
| Started | Jul 31 08:46:00 PM PDT 24 |
| Finished | Jul 31 08:55:51 PM PDT 24 |
| Peak memory | 649936 kb |
| Host | smart-fb8375af-746b-4936-884f-c7c860419cb7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3126156966 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.3126156966 |
| Directory | /workspace/84.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3878149451 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 3512267700 ps |
| CPU time | 420.48 seconds |
| Started | Jul 31 08:45:18 PM PDT 24 |
| Finished | Jul 31 08:52:19 PM PDT 24 |
| Peak memory | 649040 kb |
| Host | smart-3154d01c-f477-4a95-b86a-cb4b9e3120f0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878149451 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3878149451 |
| Directory | /workspace/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/90.chip_sw_all_escalation_resets.2275722042 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 5119275840 ps |
| CPU time | 476.24 seconds |
| Started | Jul 31 08:45:23 PM PDT 24 |
| Finished | Jul 31 08:53:20 PM PDT 24 |
| Peak memory | 650324 kb |
| Host | smart-d4a8276a-0629-4e15-bc80-fb84c76cb6aa |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2275722042 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.2275722042 |
| Directory | /workspace/90.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.3466807175 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 2199224042 ps |
| CPU time | 118.6 seconds |
| Started | Jul 31 08:15:10 PM PDT 24 |
| Finished | Jul 31 08:17:09 PM PDT 24 |
| Peak memory | 608856 kb |
| Host | smart-4c370cef-0701-4921-88d2-ac2dfd61738b |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466807175 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_lockstep_glitch.3466807175 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/cover_reg_top/23.chip_tl_errors.2753188596 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 4758221681 ps |
| CPU time | 459.61 seconds |
| Started | Jul 31 07:51:47 PM PDT 24 |
| Finished | Jul 31 07:59:27 PM PDT 24 |
| Peak memory | 598728 kb |
| Host | smart-f8b54e85-b79b-4782-a984-1a0127725f63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753188596 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.chip_tl_errors.2753188596 |
| Directory | /workspace/23.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.1107550403 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 3651496460 ps |
| CPU time | 366.87 seconds |
| Started | Jul 31 08:16:04 PM PDT 24 |
| Finished | Jul 31 08:22:12 PM PDT 24 |
| Peak memory | 609600 kb |
| Host | smart-f3a15063-a2a1-4b0b-9abe-8b921dbf3ca3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107550403 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_pwrmgr_lowpower_cancel.1107550403 |
| Directory | /workspace/0.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2940109746 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 5120338972 ps |
| CPU time | 425.46 seconds |
| Started | Jul 31 08:16:27 PM PDT 24 |
| Finished | Jul 31 08:23:33 PM PDT 24 |
| Peak memory | 611320 kb |
| Host | smart-89046e81-cc06-4a65-a46d-b6ae03437e2a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2940109746 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.2940109746 |
| Directory | /workspace/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_10.3646169009 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 3677705194 ps |
| CPU time | 543.84 seconds |
| Started | Jul 31 08:38:03 PM PDT 24 |
| Finished | Jul 31 08:47:07 PM PDT 24 |
| Peak memory | 609648 kb |
| Host | smart-36abd4cd-c7a2-473e-b100-56d040c5b2d3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646169009 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_10.3646169009 |
| Directory | /workspace/2.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.1053692338 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 4577438075 ps |
| CPU time | 222.98 seconds |
| Started | Jul 31 07:45:48 PM PDT 24 |
| Finished | Jul 31 07:49:32 PM PDT 24 |
| Peak memory | 661900 kb |
| Host | smart-1d524a11-4b9c-4e88-8d9e-9f64851a2261 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053692338 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_hw_r eset.1053692338 |
| Directory | /workspace/2.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_large_delays.2905961147 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 46997351166 ps |
| CPU time | 512.53 seconds |
| Started | Jul 31 08:01:47 PM PDT 24 |
| Finished | Jul 31 08:10:19 PM PDT 24 |
| Peak memory | 576100 kb |
| Host | smart-2b956ab2-f0a5-4ee9-8edb-383e67b8f457 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905961147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_large_delays.2905961147 |
| Directory | /workspace/78.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.224586729 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 50546298750 ps |
| CPU time | 5727.86 seconds |
| Started | Jul 31 08:15:37 PM PDT 24 |
| Finished | Jul 31 09:51:05 PM PDT 24 |
| Peak memory | 620960 kb |
| Host | smart-e10cf6bb-4316-4f3f-af88-25930e1b752d |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224586729 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_prod.224586729 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3436072647 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 7892678017 ps |
| CPU time | 628.55 seconds |
| Started | Jul 31 08:12:05 PM PDT 24 |
| Finished | Jul 31 08:22:34 PM PDT 24 |
| Peak memory | 610860 kb |
| Host | smart-2719fa8c-d39e-473c-a550-b02a488e5f27 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436072647 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_full_aon_reset.3436072647 |
| Directory | /workspace/0.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.532152206 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 5774481504 ps |
| CPU time | 570.97 seconds |
| Started | Jul 31 08:17:38 PM PDT 24 |
| Finished | Jul 31 08:27:09 PM PDT 24 |
| Peak memory | 621348 kb |
| Host | smart-7aede9ed-4723-4777-b63b-b00b8cb71b0b |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532152 206 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.532152206 |
| Directory | /workspace/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3815672584 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 24313917336 ps |
| CPU time | 1808.48 seconds |
| Started | Jul 31 08:17:14 PM PDT 24 |
| Finished | Jul 31 08:47:23 PM PDT 24 |
| Peak memory | 610848 kb |
| Host | smart-53cd3937-e3d8-4823-8caa-d6f39a8d574e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3815672584 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3815672584 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_dev.1067200243 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 11302774540 ps |
| CPU time | 1247.12 seconds |
| Started | Jul 31 08:24:36 PM PDT 24 |
| Finished | Jul 31 08:45:24 PM PDT 24 |
| Peak memory | 624548 kb |
| Host | smart-fae761e3-5d08-4c63-bb1f-00b9c1705f46 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1067200243 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.1067200243 |
| Directory | /workspace/1.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.1895354935 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 893084658 ps |
| CPU time | 36.24 seconds |
| Started | Jul 31 07:45:16 PM PDT 24 |
| Finished | Jul 31 07:45:52 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-c8c5d718-80f1-46c6-8ea4-b9450ebe9b24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895354935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.1895354935 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device.254349067 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 1323941134 ps |
| CPU time | 53.25 seconds |
| Started | Jul 31 07:49:04 PM PDT 24 |
| Finished | Jul 31 07:49:58 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-12260a8d-d71c-44f0-94b1-6316da21412c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254349067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device. 254349067 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.67858701 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 8919679116 ps |
| CPU time | 361.03 seconds |
| Started | Jul 31 08:01:38 PM PDT 24 |
| Finished | Jul 31 08:07:39 PM PDT 24 |
| Peak memory | 576076 kb |
| Host | smart-e36903b8-0ad9-45b3-b623-19d52baf2d63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67858701 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_error.67858701 |
| Directory | /workspace/77.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio.3882128054 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 3660373776 ps |
| CPU time | 495.76 seconds |
| Started | Jul 31 08:17:51 PM PDT 24 |
| Finished | Jul 31 08:26:07 PM PDT 24 |
| Peak memory | 610328 kb |
| Host | smart-399b645a-5b0a-4dbb-98b9-00186ca08ebb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882128054 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_gpio.3882128054 |
| Directory | /workspace/1.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.2873425012 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 4783822692 ps |
| CPU time | 561.01 seconds |
| Started | Jul 31 08:34:42 PM PDT 24 |
| Finished | Jul 31 08:44:03 PM PDT 24 |
| Peak memory | 610136 kb |
| Host | smart-3b87cf7b-0bf1-49d5-be62-55196a5d4654 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873425012 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_pwrmgr_lowpower_cancel.2873425012 |
| Directory | /workspace/2.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3808393568 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 18867208092 ps |
| CPU time | 699.63 seconds |
| Started | Jul 31 08:17:37 PM PDT 24 |
| Finished | Jul 31 08:29:19 PM PDT 24 |
| Peak memory | 619148 kb |
| Host | smart-8a3a76e2-c593-462d-b574-39d76246c73f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3808393568 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3808393568 |
| Directory | /workspace/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.2945186956 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 2321252315 ps |
| CPU time | 107.76 seconds |
| Started | Jul 31 08:19:38 PM PDT 24 |
| Finished | Jul 31 08:21:26 PM PDT 24 |
| Peak memory | 623040 kb |
| Host | smart-08ef7bf3-a5e2-43a6-89e9-e1625545fe40 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945186956 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.2945186956 |
| Directory | /workspace/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3808315788 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 3294531914 ps |
| CPU time | 286.15 seconds |
| Started | Jul 31 08:31:30 PM PDT 24 |
| Finished | Jul 31 08:36:17 PM PDT 24 |
| Peak memory | 610136 kb |
| Host | smart-26e7d7b5-53b9-4418-a346-b72bf84f6160 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808315788 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_spi_host_tx_rx.3808315788 |
| Directory | /workspace/2.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.1218759891 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 6767238266 ps |
| CPU time | 349.58 seconds |
| Started | Jul 31 07:46:32 PM PDT 24 |
| Finished | Jul 31 07:52:21 PM PDT 24 |
| Peak memory | 661988 kb |
| Host | smart-483c6dc0-f367-4cc7-a1ea-9b774eec00fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218759891 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_hw_r eset.1218759891 |
| Directory | /workspace/4.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.3493899357 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 8387601772 ps |
| CPU time | 1962.53 seconds |
| Started | Jul 31 08:15:34 PM PDT 24 |
| Finished | Jul 31 08:48:17 PM PDT 24 |
| Peak memory | 609988 kb |
| Host | smart-9bc1aaba-1d0d-41e1-93e2-ed50a6c59068 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3493899357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.3493899357 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2202979942 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 26269292819 ps |
| CPU time | 2132.4 seconds |
| Started | Jul 31 08:13:48 PM PDT 24 |
| Finished | Jul 31 08:49:22 PM PDT 24 |
| Peak memory | 614528 kb |
| Host | smart-13623fcb-5edb-4ac0-a0b3-f1bc71bcc88b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2202979942 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.2202979942 |
| Directory | /workspace/0.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.973123190 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 4516618700 ps |
| CPU time | 674.64 seconds |
| Started | Jul 31 08:14:39 PM PDT 24 |
| Finished | Jul 31 08:25:54 PM PDT 24 |
| Peak memory | 610868 kb |
| Host | smart-34366778-3b26-4aa2-9eda-2d51351a90b8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=973123190 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_program_error.973123190 |
| Directory | /workspace/0.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3202049026 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 24480977202 ps |
| CPU time | 4035.96 seconds |
| Started | Jul 31 08:14:30 PM PDT 24 |
| Finished | Jul 31 09:21:48 PM PDT 24 |
| Peak memory | 610284 kb |
| Host | smart-2ae5b0bb-7626-4652-9d77-9759e4833135 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202049026 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.3202049026 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3982854122 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 7243526614 ps |
| CPU time | 454.77 seconds |
| Started | Jul 31 08:12:45 PM PDT 24 |
| Finished | Jul 31 08:20:20 PM PDT 24 |
| Peak memory | 617348 kb |
| Host | smart-15461eeb-147c-4ab1-a10f-2a8a8938d092 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3982854122 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3982854122 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.2949872080 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 15605447892 ps |
| CPU time | 3638.98 seconds |
| Started | Jul 31 08:21:01 PM PDT 24 |
| Finished | Jul 31 09:21:40 PM PDT 24 |
| Peak memory | 610920 kb |
| Host | smart-33c74b78-ddc2-4018-b28c-ba7faf59aaba |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29498 72080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.2949872080 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.2431205714 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 13482866515 ps |
| CPU time | 677.68 seconds |
| Started | Jul 31 07:48:43 PM PDT 24 |
| Finished | Jul 31 08:00:01 PM PDT 24 |
| Peak memory | 576992 kb |
| Host | smart-7f014fc6-d6ad-4594-abb0-7a74ea9c6680 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431205714 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_al l_with_reset_error.2431205714 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.chip_tl_errors.3488714660 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 4049499247 ps |
| CPU time | 195.08 seconds |
| Started | Jul 31 07:52:29 PM PDT 24 |
| Finished | Jul 31 07:55:44 PM PDT 24 |
| Peak memory | 603676 kb |
| Host | smart-6dcb37a6-c5a4-494e-963e-50c3edefdb83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488714660 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.chip_tl_errors.3488714660 |
| Directory | /workspace/26.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.3149428340 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 7058742221 ps |
| CPU time | 262.37 seconds |
| Started | Jul 31 07:58:02 PM PDT 24 |
| Finished | Jul 31 08:02:25 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-294308a8-73f8-4986-a33b-245432ff207a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149428340 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_error.3149428340 |
| Directory | /workspace/55.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.1385629701 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 4136370791 ps |
| CPU time | 460.57 seconds |
| Started | Jul 31 07:58:30 PM PDT 24 |
| Finished | Jul 31 08:06:11 PM PDT 24 |
| Peak memory | 578356 kb |
| Host | smart-d48f4203-363e-49df-b50a-3ce14e88d9da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385629701 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_al l_with_reset_error.1385629701 |
| Directory | /workspace/57.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_random.866724292 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 395275423 ps |
| CPU time | 28.41 seconds |
| Started | Jul 31 08:04:22 PM PDT 24 |
| Finished | Jul 31 08:04:50 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-6d151ab3-be10-43de-af61-237d894c809a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866724292 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_random.866724292 |
| Directory | /workspace/88.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.4157259651 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 3121902340 ps |
| CPU time | 241.16 seconds |
| Started | Jul 31 08:03:35 PM PDT 24 |
| Finished | Jul 31 08:07:37 PM PDT 24 |
| Peak memory | 576740 kb |
| Host | smart-434b8bea-c235-49a4-af55-9d8a27eb581d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157259651 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_error.4157259651 |
| Directory | /workspace/91.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.2715935726 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 6527982775 ps |
| CPU time | 427.49 seconds |
| Started | Jul 31 08:03:47 PM PDT 24 |
| Finished | Jul 31 08:10:55 PM PDT 24 |
| Peak memory | 576804 kb |
| Host | smart-915282ec-4d8b-4acd-b6bd-3b5ce51910a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715935726 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_al l_with_reset_error.2715935726 |
| Directory | /workspace/92.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.3534312237 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 4062203898 ps |
| CPU time | 726.5 seconds |
| Started | Jul 31 08:14:13 PM PDT 24 |
| Finished | Jul 31 08:26:20 PM PDT 24 |
| Peak memory | 609588 kb |
| Host | smart-07e2e110-05e4-4a72-b70e-7771c501f285 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534312237 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.3534312237 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2134860630 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 4390197550 ps |
| CPU time | 815.46 seconds |
| Started | Jul 31 08:13:01 PM PDT 24 |
| Finished | Jul 31 08:26:37 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-0a7c9e5f-8660-4fe1-a067-0a7c3827f85d |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134860630 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.2134860630 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1216983792 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 11991415720 ps |
| CPU time | 2031.25 seconds |
| Started | Jul 31 08:13:06 PM PDT 24 |
| Finished | Jul 31 08:46:58 PM PDT 24 |
| Peak memory | 611000 kb |
| Host | smart-8301920f-7ada-41e6-82ac-a4e6c47f536d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1216983792 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.1216983792 |
| Directory | /workspace/0.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3743573844 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 5023726850 ps |
| CPU time | 906.85 seconds |
| Started | Jul 31 08:17:13 PM PDT 24 |
| Finished | Jul 31 08:32:20 PM PDT 24 |
| Peak memory | 610096 kb |
| Host | smart-5fe1f9ef-04e1-465c-97cb-a0714a07250f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37435 73844 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.3743573844 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_csr_rw.3526945129 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 17538132144 ps |
| CPU time | 2014.24 seconds |
| Started | Jul 31 08:26:21 PM PDT 24 |
| Finished | Jul 31 08:59:55 PM PDT 24 |
| Peak memory | 608072 kb |
| Host | smart-2981a90d-6589-46b1-9914-cf33cd8cd8f0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526945129 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_jtag_csr_rw.3526945129 |
| Directory | /workspace/2.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2740592565 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 4652181152 ps |
| CPU time | 275.54 seconds |
| Started | Jul 31 07:44:55 PM PDT 24 |
| Finished | Jul 31 07:49:31 PM PDT 24 |
| Peak memory | 649144 kb |
| Host | smart-68c774e0-426b-406f-a311-68e49871d816 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740592565 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 0.chip_padctrl_attributes.2740592565 |
| Directory | /workspace/0.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_rma.3299114853 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 5369029418 ps |
| CPU time | 600.64 seconds |
| Started | Jul 31 08:37:44 PM PDT 24 |
| Finished | Jul 31 08:47:47 PM PDT 24 |
| Peak memory | 624688 kb |
| Host | smart-b00a2ca2-9881-4219-b0e4-3046ab7ef204 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299114853 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_rma.3299114853 |
| Directory | /workspace/4.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_plic_sw_irq.2004238420 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 3155243160 ps |
| CPU time | 297.5 seconds |
| Started | Jul 31 08:14:02 PM PDT 24 |
| Finished | Jul 31 08:18:59 PM PDT 24 |
| Peak memory | 609680 kb |
| Host | smart-a6f0cca5-de66-425a-b0de-978c17f8ef6f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004238420 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_plic_sw_irq.2004238420 |
| Directory | /workspace/0.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_boot_mode.3225311079 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 3033080988 ps |
| CPU time | 551.53 seconds |
| Started | Jul 31 08:13:38 PM PDT 24 |
| Finished | Jul 31 08:22:50 PM PDT 24 |
| Peak memory | 610092 kb |
| Host | smart-0d58fd91-5d66-4eb8-a428-b7c86c6df7f5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225311079 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ boot_mode.3225311079 |
| Directory | /workspace/0.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_manufacturer.1604266815 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 2591090410 ps |
| CPU time | 160.55 seconds |
| Started | Jul 31 08:12:37 PM PDT 24 |
| Finished | Jul 31 08:15:18 PM PDT 24 |
| Peak memory | 609452 kb |
| Host | smart-ab377b8a-6752-46be-a4ac-54e1e3201206 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604266815 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_manufacturer.1604266815 |
| Directory | /workspace/0.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3029886778 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 151482611384 ps |
| CPU time | 20822.1 seconds |
| Started | Jul 31 08:27:15 PM PDT 24 |
| Finished | Aug 01 02:14:20 AM PDT 24 |
| Peak memory | 610444 kb |
| Host | smart-88a9d364-16a7-4548-bebb-f1c702b9465c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3029886778 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency_reduced_freq.3029886778 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1116995895 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 24089765602 ps |
| CPU time | 6570.69 seconds |
| Started | Jul 31 08:22:25 PM PDT 24 |
| Finished | Jul 31 10:11:57 PM PDT 24 |
| Peak memory | 610080 kb |
| Host | smart-1c1b4c43-80af-4c36-bb89-a957ca6ce6be |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1116995895 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1116995895 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.3398331849 |
| Short name | T2504 |
| Test name | |
| Test status | |
| Simulation time | 3862154825 ps |
| CPU time | 176.92 seconds |
| Started | Jul 31 07:45:01 PM PDT 24 |
| Finished | Jul 31 07:47:58 PM PDT 24 |
| Peak memory | 590516 kb |
| Host | smart-c8447bea-5bc0-42be-9ba6-df330feed92b |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398331849 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 0.chip_csr_bit_bash.3398331849 |
| Directory | /workspace/0.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.4248365155 |
| Short name | T1543 |
| Test name | |
| Test status | |
| Simulation time | 12259384296 ps |
| CPU time | 781.59 seconds |
| Started | Jul 31 07:45:15 PM PDT 24 |
| Finished | Jul 31 07:58:16 PM PDT 24 |
| Peak memory | 652972 kb |
| Host | smart-50f5ba52-409f-4fb2-a12c-a8cf3f42ac62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248365155 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 0.chip_csr_mem_rw_with_rand_reset.4248365155 |
| Directory | /workspace/0.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_rw.1857574863 |
| Short name | T2248 |
| Test name | |
| Test status | |
| Simulation time | 4207902012 ps |
| CPU time | 331.38 seconds |
| Started | Jul 31 07:45:11 PM PDT 24 |
| Finished | Jul 31 07:50:43 PM PDT 24 |
| Peak memory | 597108 kb |
| Host | smart-f8dee14a-f471-4cf7-aa5a-7e9777c7e1f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857574863 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_rw.1857574863 |
| Directory | /workspace/0.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_prim_tl_access.4123633520 |
| Short name | T2158 |
| Test name | |
| Test status | |
| Simulation time | 8230885052 ps |
| CPU time | 394.37 seconds |
| Started | Jul 31 07:45:02 PM PDT 24 |
| Finished | Jul 31 07:51:37 PM PDT 24 |
| Peak memory | 591504 kb |
| Host | smart-d9e242d3-aab3-406c-a71e-2e1122766f39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123633520 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_prim_tl_access.4123633520 |
| Directory | /workspace/0.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.4083404488 |
| Short name | T1520 |
| Test name | |
| Test status | |
| Simulation time | 11751311531 ps |
| CPU time | 317.73 seconds |
| Started | Jul 31 07:45:05 PM PDT 24 |
| Finished | Jul 31 07:50:23 PM PDT 24 |
| Peak memory | 591308 kb |
| Host | smart-93d1bc12-5240-4b01-a809-aa6412fe367f |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083404488 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_lc_disabled.4083404488 |
| Directory | /workspace/0.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.4042828555 |
| Short name | T2647 |
| Test name | |
| Test status | |
| Simulation time | 16350506184 ps |
| CPU time | 2397.11 seconds |
| Started | Jul 31 07:45:01 PM PDT 24 |
| Finished | Jul 31 08:24:58 PM PDT 24 |
| Peak memory | 592824 kb |
| Host | smart-d84579de-234f-4bb6-bf1a-3602389d40c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042828555 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 0.chip_same_csr_outstanding.4042828555 |
| Directory | /workspace/0.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_tl_errors.1327120150 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 3082970178 ps |
| CPU time | 159.93 seconds |
| Started | Jul 31 07:45:01 PM PDT 24 |
| Finished | Jul 31 07:47:41 PM PDT 24 |
| Peak memory | 598636 kb |
| Host | smart-036c6b2b-0fb7-48e9-9575-41f914f989f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327120150 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_tl_errors.1327120150 |
| Directory | /workspace/0.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device.394686536 |
| Short name | T2503 |
| Test name | |
| Test status | |
| Simulation time | 2962925082 ps |
| CPU time | 118.76 seconds |
| Started | Jul 31 07:45:13 PM PDT 24 |
| Finished | Jul 31 07:47:12 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-993399ca-38f2-4a9b-bf0c-47e258d9a9d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394686536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.394686536 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.3172612498 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 43812459003 ps |
| CPU time | 752.75 seconds |
| Started | Jul 31 07:45:11 PM PDT 24 |
| Finished | Jul 31 07:57:44 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-58803b32-e300-4c6c-b4a4-9c78497fd07a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172612498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_d evice_slow_rsp.3172612498 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.3260992441 |
| Short name | T2744 |
| Test name | |
| Test status | |
| Simulation time | 174663665 ps |
| CPU time | 20.99 seconds |
| Started | Jul 31 07:45:15 PM PDT 24 |
| Finished | Jul 31 07:45:36 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-9067ddd0-b934-47d1-b629-40c60616902c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260992441 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr .3260992441 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_random.3320691096 |
| Short name | T1788 |
| Test name | |
| Test status | |
| Simulation time | 359908681 ps |
| CPU time | 15.96 seconds |
| Started | Jul 31 07:45:13 PM PDT 24 |
| Finished | Jul 31 07:45:29 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-7261bcda-3cbb-4816-b167-eaf3fe859ec5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320691096 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.3320691096 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random.2939284881 |
| Short name | T2413 |
| Test name | |
| Test status | |
| Simulation time | 1628154559 ps |
| CPU time | 58.03 seconds |
| Started | Jul 31 07:45:08 PM PDT 24 |
| Finished | Jul 31 07:46:06 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-361de9b4-980e-4cfd-9f0e-ca2b686d8593 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939284881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random.2939284881 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_large_delays.711316381 |
| Short name | T2720 |
| Test name | |
| Test status | |
| Simulation time | 67278995545 ps |
| CPU time | 685.57 seconds |
| Started | Jul 31 07:45:05 PM PDT 24 |
| Finished | Jul 31 07:56:31 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-cc86ecf7-9c74-4f45-a78e-59fb47e2b23b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711316381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.711316381 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.187227313 |
| Short name | T2082 |
| Test name | |
| Test status | |
| Simulation time | 42269907463 ps |
| CPU time | 748.1 seconds |
| Started | Jul 31 07:45:07 PM PDT 24 |
| Finished | Jul 31 07:57:36 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-80250cd0-3d5b-4ea0-8e5e-682eacba0b72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187227313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.187227313 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.4099919829 |
| Short name | T1624 |
| Test name | |
| Test status | |
| Simulation time | 151916362 ps |
| CPU time | 13.6 seconds |
| Started | Jul 31 07:45:08 PM PDT 24 |
| Finished | Jul 31 07:45:22 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-eed4e495-7d3c-4753-96f0-ae8ea00b10fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099919829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_dela ys.4099919829 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_same_source.2623996021 |
| Short name | T1508 |
| Test name | |
| Test status | |
| Simulation time | 321089778 ps |
| CPU time | 11.97 seconds |
| Started | Jul 31 07:45:15 PM PDT 24 |
| Finished | Jul 31 07:45:27 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-71080a56-720f-471a-a2e7-18571443c87c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623996021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2623996021 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke.408461956 |
| Short name | T1681 |
| Test name | |
| Test status | |
| Simulation time | 131187821 ps |
| CPU time | 7.41 seconds |
| Started | Jul 31 07:45:06 PM PDT 24 |
| Finished | Jul 31 07:45:13 PM PDT 24 |
| Peak memory | 573840 kb |
| Host | smart-b93c3b85-ad31-4030-ab6e-4ad761ae1631 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408461956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.408461956 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.4134930829 |
| Short name | T1880 |
| Test name | |
| Test status | |
| Simulation time | 10266601121 ps |
| CPU time | 97.51 seconds |
| Started | Jul 31 07:45:08 PM PDT 24 |
| Finished | Jul 31 07:46:46 PM PDT 24 |
| Peak memory | 574556 kb |
| Host | smart-8210882f-8600-436b-bb78-4788bd0868ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134930829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.4134930829 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2721250235 |
| Short name | T2861 |
| Test name | |
| Test status | |
| Simulation time | 5002569349 ps |
| CPU time | 89.99 seconds |
| Started | Jul 31 07:45:06 PM PDT 24 |
| Finished | Jul 31 07:46:36 PM PDT 24 |
| Peak memory | 573912 kb |
| Host | smart-44787af6-2050-45d9-bea0-6b227b47d014 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721250235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.2721250235 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.509888926 |
| Short name | T1851 |
| Test name | |
| Test status | |
| Simulation time | 53673398 ps |
| CPU time | 6.47 seconds |
| Started | Jul 31 07:45:08 PM PDT 24 |
| Finished | Jul 31 07:45:15 PM PDT 24 |
| Peak memory | 574480 kb |
| Host | smart-71c9da0a-4161-45ea-ba42-fa1891bcf272 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509888926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays. 509888926 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all.1666677905 |
| Short name | T1971 |
| Test name | |
| Test status | |
| Simulation time | 4600961304 ps |
| CPU time | 196.81 seconds |
| Started | Jul 31 07:45:13 PM PDT 24 |
| Finished | Jul 31 07:48:30 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-d85fcc7f-843b-45c4-b084-ce4fd719c158 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666677905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.1666677905 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.3428503462 |
| Short name | T2468 |
| Test name | |
| Test status | |
| Simulation time | 16297942977 ps |
| CPU time | 566.35 seconds |
| Started | Jul 31 07:45:14 PM PDT 24 |
| Finished | Jul 31 07:54:41 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-618d1a66-9fcb-42c4-8e95-f62935670470 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428503462 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.3428503462 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.629419846 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 1923371035 ps |
| CPU time | 330.16 seconds |
| Started | Jul 31 07:45:11 PM PDT 24 |
| Finished | Jul 31 07:50:41 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-84f750b1-44a3-4fa5-b2fd-3ece603d6102 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629419846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_w ith_rand_reset.629419846 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.1526553721 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 743226375 ps |
| CPU time | 218.57 seconds |
| Started | Jul 31 07:45:14 PM PDT 24 |
| Finished | Jul 31 07:48:53 PM PDT 24 |
| Peak memory | 576720 kb |
| Host | smart-fbc20c6e-826a-4a78-aba8-47695a8c0a9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526553721 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all _with_reset_error.1526553721 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_aliasing.1708787085 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 71650894623 ps |
| CPU time | 10257.3 seconds |
| Started | Jul 31 07:45:19 PM PDT 24 |
| Finished | Jul 31 10:36:18 PM PDT 24 |
| Peak memory | 645476 kb |
| Host | smart-4265266b-a891-41f5-b826-5d791797cf3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708787085 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.chip_csr_aliasing.1708787085 |
| Directory | /workspace/1.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.2805443884 |
| Short name | T2245 |
| Test name | |
| Test status | |
| Simulation time | 7326042592 ps |
| CPU time | 614.45 seconds |
| Started | Jul 31 07:45:13 PM PDT 24 |
| Finished | Jul 31 07:55:27 PM PDT 24 |
| Peak memory | 592852 kb |
| Host | smart-ceee594b-df29-4f72-a11f-90f0311dedfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805443884 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 1.chip_csr_bit_bash.2805443884 |
| Directory | /workspace/1.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.4262538978 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 5005983480 ps |
| CPU time | 229.4 seconds |
| Started | Jul 31 07:45:30 PM PDT 24 |
| Finished | Jul 31 07:49:20 PM PDT 24 |
| Peak memory | 659752 kb |
| Host | smart-c6f02595-9155-42cc-90a8-fbc194866c25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262538978 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_hw_r eset.4262538978 |
| Directory | /workspace/1.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.3469062800 |
| Short name | T2525 |
| Test name | |
| Test status | |
| Simulation time | 6768890758 ps |
| CPU time | 410.77 seconds |
| Started | Jul 31 07:45:31 PM PDT 24 |
| Finished | Jul 31 07:52:23 PM PDT 24 |
| Peak memory | 638540 kb |
| Host | smart-b97cb5e3-3314-49a2-bf4b-f4aa741b8ba8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469062800 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 1.chip_csr_mem_rw_with_rand_reset.3469062800 |
| Directory | /workspace/1.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_rw.2518904018 |
| Short name | T2629 |
| Test name | |
| Test status | |
| Simulation time | 5338742900 ps |
| CPU time | 566.72 seconds |
| Started | Jul 31 07:45:32 PM PDT 24 |
| Finished | Jul 31 07:54:59 PM PDT 24 |
| Peak memory | 598256 kb |
| Host | smart-a8c77d72-21ae-4824-b8f5-85509dd64570 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518904018 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_rw.2518904018 |
| Directory | /workspace/1.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_prim_tl_access.1342501537 |
| Short name | T2555 |
| Test name | |
| Test status | |
| Simulation time | 7359825075 ps |
| CPU time | 243.24 seconds |
| Started | Jul 31 07:45:21 PM PDT 24 |
| Finished | Jul 31 07:49:25 PM PDT 24 |
| Peak memory | 589992 kb |
| Host | smart-dd4f2879-f543-4aeb-b610-929bbee61c67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342501537 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_prim_tl_access.1342501537 |
| Directory | /workspace/1.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.940830877 |
| Short name | T1405 |
| Test name | |
| Test status | |
| Simulation time | 6402765309 ps |
| CPU time | 264.48 seconds |
| Started | Jul 31 07:45:19 PM PDT 24 |
| Finished | Jul 31 07:49:43 PM PDT 24 |
| Peak memory | 590248 kb |
| Host | smart-36c53e29-31cd-44ac-bf5a-c60f437f7cf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940830877 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 1.chip_rv_dm_lc_disabled.940830877 |
| Directory | /workspace/1.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.110757100 |
| Short name | T1855 |
| Test name | |
| Test status | |
| Simulation time | 28197258184 ps |
| CPU time | 3558.72 seconds |
| Started | Jul 31 07:45:18 PM PDT 24 |
| Finished | Jul 31 08:44:38 PM PDT 24 |
| Peak memory | 593240 kb |
| Host | smart-6f5b41b3-6f6e-4b5f-b960-03884c5fb58b |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110757100 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 1.chip_same_csr_outstanding.110757100 |
| Directory | /workspace/1.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_tl_errors.2849469231 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 2798491024 ps |
| CPU time | 149.76 seconds |
| Started | Jul 31 07:45:18 PM PDT 24 |
| Finished | Jul 31 07:47:48 PM PDT 24 |
| Peak memory | 598600 kb |
| Host | smart-5fba3366-e427-4632-8f42-ed258033238a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849469231 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_tl_errors.2849469231 |
| Directory | /workspace/1.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device.2283005012 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 726071179 ps |
| CPU time | 25.02 seconds |
| Started | Jul 31 07:45:29 PM PDT 24 |
| Finished | Jul 31 07:45:54 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-a5af1052-6b62-47f6-a8c9-fb7112df7569 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283005012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device. 2283005012 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.1318014004 |
| Short name | T2223 |
| Test name | |
| Test status | |
| Simulation time | 128174350142 ps |
| CPU time | 2228.68 seconds |
| Started | Jul 31 07:45:29 PM PDT 24 |
| Finished | Jul 31 08:22:38 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-7997b0d1-f715-43b8-8b2d-8e02636ed6c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318014004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_d evice_slow_rsp.1318014004 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.2902931798 |
| Short name | T1888 |
| Test name | |
| Test status | |
| Simulation time | 65881901 ps |
| CPU time | 8.79 seconds |
| Started | Jul 31 07:45:25 PM PDT 24 |
| Finished | Jul 31 07:45:34 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-a7f34c6f-161e-4581-a703-d5d4ae317102 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902931798 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr .2902931798 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_random.1244192203 |
| Short name | T1394 |
| Test name | |
| Test status | |
| Simulation time | 574600897 ps |
| CPU time | 48.88 seconds |
| Started | Jul 31 07:45:25 PM PDT 24 |
| Finished | Jul 31 07:46:14 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-af60dfe8-74d9-4078-81fd-cfa20abe4496 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244192203 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.1244192203 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random.3462418345 |
| Short name | T1947 |
| Test name | |
| Test status | |
| Simulation time | 538614023 ps |
| CPU time | 41.43 seconds |
| Started | Jul 31 07:45:29 PM PDT 24 |
| Finished | Jul 31 07:46:10 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-a8e89013-c73a-4a27-acbc-65a6b42ca00c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462418345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random.3462418345 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2553848636 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 90693702635 ps |
| CPU time | 841.62 seconds |
| Started | Jul 31 07:45:24 PM PDT 24 |
| Finished | Jul 31 07:59:26 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-1bde444d-d5be-421e-825e-09c5eaf7b215 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553848636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.2553848636 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.368504303 |
| Short name | T2043 |
| Test name | |
| Test status | |
| Simulation time | 3352513328 ps |
| CPU time | 54.45 seconds |
| Started | Jul 31 07:45:24 PM PDT 24 |
| Finished | Jul 31 07:46:18 PM PDT 24 |
| Peak memory | 573836 kb |
| Host | smart-74544bd0-426d-4cf6-9714-1cd01ee5a656 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368504303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.368504303 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.3858764961 |
| Short name | T2393 |
| Test name | |
| Test status | |
| Simulation time | 256523306 ps |
| CPU time | 23.68 seconds |
| Started | Jul 31 07:45:24 PM PDT 24 |
| Finished | Jul 31 07:45:48 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-9a70fb31-90e0-4e69-a4d1-bc18a770b99e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858764961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_dela ys.3858764961 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_same_source.254033548 |
| Short name | T2576 |
| Test name | |
| Test status | |
| Simulation time | 1285302025 ps |
| CPU time | 38.96 seconds |
| Started | Jul 31 07:45:23 PM PDT 24 |
| Finished | Jul 31 07:46:02 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-0f8b1e69-55e4-4680-a661-096495db6e8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254033548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.254033548 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke.2745343721 |
| Short name | T2475 |
| Test name | |
| Test status | |
| Simulation time | 232254017 ps |
| CPU time | 10.21 seconds |
| Started | Jul 31 07:45:18 PM PDT 24 |
| Finished | Jul 31 07:45:28 PM PDT 24 |
| Peak memory | 573764 kb |
| Host | smart-12e9ea31-c7cb-49db-94f8-81a07e7313cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745343721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.2745343721 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.2560204738 |
| Short name | T1392 |
| Test name | |
| Test status | |
| Simulation time | 9437236101 ps |
| CPU time | 94.67 seconds |
| Started | Jul 31 07:45:19 PM PDT 24 |
| Finished | Jul 31 07:46:54 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-c5e4da00-da32-4e8b-8f42-aefbfbd5dadd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560204738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.2560204738 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.2692750854 |
| Short name | T2781 |
| Test name | |
| Test status | |
| Simulation time | 5196118742 ps |
| CPU time | 86.85 seconds |
| Started | Jul 31 07:45:24 PM PDT 24 |
| Finished | Jul 31 07:46:51 PM PDT 24 |
| Peak memory | 573856 kb |
| Host | smart-5dd1d765-0109-4fea-9164-97993079bf20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692750854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.2692750854 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.611550362 |
| Short name | T1770 |
| Test name | |
| Test status | |
| Simulation time | 45761504 ps |
| CPU time | 6.52 seconds |
| Started | Jul 31 07:45:19 PM PDT 24 |
| Finished | Jul 31 07:45:25 PM PDT 24 |
| Peak memory | 573708 kb |
| Host | smart-ad8d96b0-df58-495d-9cc4-fe3b24d0c9ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611550362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays. 611550362 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all.2876084579 |
| Short name | T2809 |
| Test name | |
| Test status | |
| Simulation time | 13347202543 ps |
| CPU time | 451.88 seconds |
| Started | Jul 31 07:45:31 PM PDT 24 |
| Finished | Jul 31 07:53:03 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-18f81b0d-2b39-45d8-9236-d9f34c03dd08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876084579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.2876084579 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.1743988104 |
| Short name | T2643 |
| Test name | |
| Test status | |
| Simulation time | 8901084561 ps |
| CPU time | 331.65 seconds |
| Started | Jul 31 07:45:29 PM PDT 24 |
| Finished | Jul 31 07:51:00 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-9b773087-8304-475e-948a-c1a2f813e9c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743988104 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.1743988104 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3233632893 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 3889251014 ps |
| CPU time | 554.78 seconds |
| Started | Jul 31 07:45:28 PM PDT 24 |
| Finished | Jul 31 07:54:43 PM PDT 24 |
| Peak memory | 576756 kb |
| Host | smart-de93bfed-6e2d-4e23-a821-024666cbbc3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233632893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_ with_rand_reset.3233632893 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.4146713035 |
| Short name | T1679 |
| Test name | |
| Test status | |
| Simulation time | 560735737 ps |
| CPU time | 143.47 seconds |
| Started | Jul 31 07:45:32 PM PDT 24 |
| Finished | Jul 31 07:47:55 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-3ed4ef8d-6cdd-408a-bc02-64c47f285b9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146713035 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all _with_reset_error.4146713035 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.2920360468 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 301607447 ps |
| CPU time | 35.01 seconds |
| Started | Jul 31 07:45:29 PM PDT 24 |
| Finished | Jul 31 07:46:04 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-7f2d94e3-1fa4-4635-85c9-5f41e5cc9660 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920360468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.2920360468 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.2129519228 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 10903246705 ps |
| CPU time | 843.22 seconds |
| Started | Jul 31 07:48:19 PM PDT 24 |
| Finished | Jul 31 08:02:22 PM PDT 24 |
| Peak memory | 644808 kb |
| Host | smart-2cdaa3ed-f679-469b-8a2a-b40fb12bdea0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129519228 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 10.chip_csr_mem_rw_with_rand_reset.2129519228 |
| Directory | /workspace/10.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_csr_rw.3170350287 |
| Short name | T2298 |
| Test name | |
| Test status | |
| Simulation time | 6102896952 ps |
| CPU time | 726.76 seconds |
| Started | Jul 31 07:48:21 PM PDT 24 |
| Finished | Jul 31 08:00:28 PM PDT 24 |
| Peak memory | 599020 kb |
| Host | smart-18a5eb65-113d-4cc6-879b-67598b0ecddb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170350287 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_rw.3170350287 |
| Directory | /workspace/10.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.1232102099 |
| Short name | T2369 |
| Test name | |
| Test status | |
| Simulation time | 14554976274 ps |
| CPU time | 1949.47 seconds |
| Started | Jul 31 07:48:05 PM PDT 24 |
| Finished | Jul 31 08:20:35 PM PDT 24 |
| Peak memory | 593156 kb |
| Host | smart-a0c148e1-741f-42f3-83f4-ed872c814651 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232102099 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 10.chip_same_csr_outstanding.1232102099 |
| Directory | /workspace/10.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_tl_errors.3063396843 |
| Short name | T2654 |
| Test name | |
| Test status | |
| Simulation time | 3643519044 ps |
| CPU time | 249.91 seconds |
| Started | Jul 31 07:48:05 PM PDT 24 |
| Finished | Jul 31 07:52:15 PM PDT 24 |
| Peak memory | 603828 kb |
| Host | smart-837ca8bc-a02e-450d-9695-cf6ed68ab5a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063396843 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_tl_errors.3063396843 |
| Directory | /workspace/10.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device.3741557134 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 265408901 ps |
| CPU time | 21.15 seconds |
| Started | Jul 31 07:48:11 PM PDT 24 |
| Finished | Jul 31 07:48:33 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-cc71d4f0-93d6-45c3-ad5c-bef5ab148afc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741557134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device .3741557134 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.3757238070 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 57047084 ps |
| CPU time | 8.25 seconds |
| Started | Jul 31 07:48:15 PM PDT 24 |
| Finished | Jul 31 07:48:24 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-76d3a56c-d07a-4099-8177-5291742dbb89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757238070 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_add r.3757238070 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_random.3554502606 |
| Short name | T1663 |
| Test name | |
| Test status | |
| Simulation time | 1041672369 ps |
| CPU time | 32.92 seconds |
| Started | Jul 31 07:48:19 PM PDT 24 |
| Finished | Jul 31 07:48:52 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-83914e1a-3e62-47be-a199-f8b73241954a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554502606 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.3554502606 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random.2065543602 |
| Short name | T1387 |
| Test name | |
| Test status | |
| Simulation time | 111377687 ps |
| CPU time | 7.22 seconds |
| Started | Jul 31 07:48:10 PM PDT 24 |
| Finished | Jul 31 07:48:17 PM PDT 24 |
| Peak memory | 574452 kb |
| Host | smart-ea0e640c-8776-4943-a065-66fe72ff4c7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065543602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random.2065543602 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_large_delays.2923621661 |
| Short name | T1885 |
| Test name | |
| Test status | |
| Simulation time | 27463395852 ps |
| CPU time | 295.86 seconds |
| Started | Jul 31 07:48:08 PM PDT 24 |
| Finished | Jul 31 07:53:04 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-487d5b31-f0bc-4768-ad15-97a96c3d097d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923621661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.2923621661 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.2866931589 |
| Short name | T2479 |
| Test name | |
| Test status | |
| Simulation time | 42359345303 ps |
| CPU time | 757.83 seconds |
| Started | Jul 31 07:48:12 PM PDT 24 |
| Finished | Jul 31 08:00:50 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-247447c6-108e-4c1c-bab4-d9a1a7b072e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866931589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.2866931589 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.576874652 |
| Short name | T1719 |
| Test name | |
| Test status | |
| Simulation time | 85961350 ps |
| CPU time | 11.31 seconds |
| Started | Jul 31 07:48:08 PM PDT 24 |
| Finished | Jul 31 07:48:19 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-fe7317a3-2b1f-4d4f-9bce-1a530ac08cf3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576874652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_dela ys.576874652 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_same_source.1168033932 |
| Short name | T1615 |
| Test name | |
| Test status | |
| Simulation time | 153424376 ps |
| CPU time | 13.89 seconds |
| Started | Jul 31 07:48:15 PM PDT 24 |
| Finished | Jul 31 07:48:29 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-0f977524-3ce0-4b47-9ccd-4cef139de2f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168033932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.1168033932 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke.1825725605 |
| Short name | T1604 |
| Test name | |
| Test status | |
| Simulation time | 45056810 ps |
| CPU time | 5.82 seconds |
| Started | Jul 31 07:48:03 PM PDT 24 |
| Finished | Jul 31 07:48:08 PM PDT 24 |
| Peak memory | 573732 kb |
| Host | smart-00a9c8f1-b110-4021-b3e9-21a364e20707 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825725605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.1825725605 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.482191443 |
| Short name | T2453 |
| Test name | |
| Test status | |
| Simulation time | 7691277450 ps |
| CPU time | 85.56 seconds |
| Started | Jul 31 07:48:04 PM PDT 24 |
| Finished | Jul 31 07:49:30 PM PDT 24 |
| Peak memory | 574580 kb |
| Host | smart-07054242-bd95-454b-bb12-8e183e3b5dd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482191443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.482191443 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2607517417 |
| Short name | T2040 |
| Test name | |
| Test status | |
| Simulation time | 5037049905 ps |
| CPU time | 76.99 seconds |
| Started | Jul 31 07:48:02 PM PDT 24 |
| Finished | Jul 31 07:49:19 PM PDT 24 |
| Peak memory | 573900 kb |
| Host | smart-36224d09-c4a3-4f63-a3eb-3e989de6f401 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607517417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.2607517417 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.3857714474 |
| Short name | T2911 |
| Test name | |
| Test status | |
| Simulation time | 51123104 ps |
| CPU time | 6.76 seconds |
| Started | Jul 31 07:48:02 PM PDT 24 |
| Finished | Jul 31 07:48:09 PM PDT 24 |
| Peak memory | 573824 kb |
| Host | smart-80f5a427-0332-48be-9048-6b5bcde98c3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857714474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delay s.3857714474 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all.2902698441 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 2075395695 ps |
| CPU time | 71.99 seconds |
| Started | Jul 31 07:48:16 PM PDT 24 |
| Finished | Jul 31 07:49:28 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-18f78cc4-039e-43e6-acce-89086cb2445d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902698441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.2902698441 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.1382802764 |
| Short name | T2920 |
| Test name | |
| Test status | |
| Simulation time | 130570970 ps |
| CPU time | 13.58 seconds |
| Started | Jul 31 07:48:16 PM PDT 24 |
| Finished | Jul 31 07:48:30 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-43c57932-a39d-4efd-aea6-80ed23a4a311 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382802764 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.1382802764 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.2638118682 |
| Short name | T2867 |
| Test name | |
| Test status | |
| Simulation time | 159716778 ps |
| CPU time | 42.92 seconds |
| Started | Jul 31 07:48:19 PM PDT 24 |
| Finished | Jul 31 07:49:02 PM PDT 24 |
| Peak memory | 576700 kb |
| Host | smart-f3905f00-0ba9-4e70-88d0-9911ca01b4ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638118682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all _with_rand_reset.2638118682 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.3794182212 |
| Short name | T2501 |
| Test name | |
| Test status | |
| Simulation time | 3469747873 ps |
| CPU time | 255.51 seconds |
| Started | Jul 31 07:48:19 PM PDT 24 |
| Finished | Jul 31 07:52:35 PM PDT 24 |
| Peak memory | 576796 kb |
| Host | smart-74649456-6dd3-45e2-9c5c-3ef887cbbc0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794182212 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_al l_with_reset_error.3794182212 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.2842124250 |
| Short name | T1820 |
| Test name | |
| Test status | |
| Simulation time | 1328048667 ps |
| CPU time | 53.06 seconds |
| Started | Jul 31 07:48:15 PM PDT 24 |
| Finished | Jul 31 07:49:08 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-4e5e0a12-8169-4cae-831e-223025ae7968 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842124250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.2842124250 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_csr_rw.2281090296 |
| Short name | T2469 |
| Test name | |
| Test status | |
| Simulation time | 5309746570 ps |
| CPU time | 590.19 seconds |
| Started | Jul 31 07:48:40 PM PDT 24 |
| Finished | Jul 31 07:58:30 PM PDT 24 |
| Peak memory | 598560 kb |
| Host | smart-7e111a18-db3b-4e89-ad54-e3461ad9be7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281090296 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_rw.2281090296 |
| Directory | /workspace/11.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_tl_errors.1323484995 |
| Short name | T2531 |
| Test name | |
| Test status | |
| Simulation time | 3043055098 ps |
| CPU time | 156.43 seconds |
| Started | Jul 31 07:48:21 PM PDT 24 |
| Finished | Jul 31 07:50:58 PM PDT 24 |
| Peak memory | 598484 kb |
| Host | smart-23878503-7bf1-400c-a066-f1de6e59580c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323484995 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_tl_errors.1323484995 |
| Directory | /workspace/11.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device.3590860415 |
| Short name | T2642 |
| Test name | |
| Test status | |
| Simulation time | 2901907067 ps |
| CPU time | 115.26 seconds |
| Started | Jul 31 07:48:33 PM PDT 24 |
| Finished | Jul 31 07:50:29 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-bb483601-7210-4cea-8190-e338d74432ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590860415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device .3590860415 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1756572741 |
| Short name | T2290 |
| Test name | |
| Test status | |
| Simulation time | 36943979986 ps |
| CPU time | 654.57 seconds |
| Started | Jul 31 07:48:33 PM PDT 24 |
| Finished | Jul 31 07:59:28 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-8b3651ab-2bba-466f-8920-805011f24860 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756572741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_ device_slow_rsp.1756572741 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3923105784 |
| Short name | T2222 |
| Test name | |
| Test status | |
| Simulation time | 269189679 ps |
| CPU time | 26.46 seconds |
| Started | Jul 31 07:48:32 PM PDT 24 |
| Finished | Jul 31 07:48:59 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-7fd7660d-b284-48f1-94be-914ccfe276d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923105784 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_add r.3923105784 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_random.1032505672 |
| Short name | T1490 |
| Test name | |
| Test status | |
| Simulation time | 695605540 ps |
| CPU time | 26.8 seconds |
| Started | Jul 31 07:48:34 PM PDT 24 |
| Finished | Jul 31 07:49:01 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-5cdb599c-f529-4cda-a499-d34b4260662a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032505672 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.1032505672 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random.873435109 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 687862447 ps |
| CPU time | 22.61 seconds |
| Started | Jul 31 07:48:27 PM PDT 24 |
| Finished | Jul 31 07:48:50 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-4f9e07e0-8c00-40f2-b632-fa8bad174e86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873435109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random.873435109 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_large_delays.535676846 |
| Short name | T2140 |
| Test name | |
| Test status | |
| Simulation time | 18148178961 ps |
| CPU time | 186.93 seconds |
| Started | Jul 31 07:48:29 PM PDT 24 |
| Finished | Jul 31 07:51:36 PM PDT 24 |
| Peak memory | 576124 kb |
| Host | smart-f6be3107-e1ae-45ae-9cb9-f4c1693c6ce5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535676846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.535676846 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.4028484740 |
| Short name | T2354 |
| Test name | |
| Test status | |
| Simulation time | 27286209129 ps |
| CPU time | 452.68 seconds |
| Started | Jul 31 07:48:27 PM PDT 24 |
| Finished | Jul 31 07:56:00 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-bc8cdc72-e2db-4c49-b6dd-8277fdde0850 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028484740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.4028484740 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.361046185 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 430307833 ps |
| CPU time | 38.63 seconds |
| Started | Jul 31 07:48:27 PM PDT 24 |
| Finished | Jul 31 07:49:06 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-3df0909f-e869-4b83-a2e0-b8a59b040f21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361046185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_dela ys.361046185 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_same_source.1290444147 |
| Short name | T2431 |
| Test name | |
| Test status | |
| Simulation time | 362458699 ps |
| CPU time | 26.2 seconds |
| Started | Jul 31 07:48:33 PM PDT 24 |
| Finished | Jul 31 07:49:00 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-cb58163a-45a3-4930-8a40-259854d4a320 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290444147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.1290444147 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke.1775432963 |
| Short name | T1708 |
| Test name | |
| Test status | |
| Simulation time | 53422251 ps |
| CPU time | 6.1 seconds |
| Started | Jul 31 07:48:24 PM PDT 24 |
| Finished | Jul 31 07:48:30 PM PDT 24 |
| Peak memory | 574592 kb |
| Host | smart-4a06e6d4-53f3-4e83-a93a-e89b52e767fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775432963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.1775432963 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.903759437 |
| Short name | T1915 |
| Test name | |
| Test status | |
| Simulation time | 7835483172 ps |
| CPU time | 75.26 seconds |
| Started | Jul 31 07:48:33 PM PDT 24 |
| Finished | Jul 31 07:49:48 PM PDT 24 |
| Peak memory | 573920 kb |
| Host | smart-f5ebf005-d926-4b12-b504-532ce40147eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903759437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.903759437 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.3471091082 |
| Short name | T1493 |
| Test name | |
| Test status | |
| Simulation time | 4539826507 ps |
| CPU time | 75.48 seconds |
| Started | Jul 31 07:48:30 PM PDT 24 |
| Finished | Jul 31 07:49:45 PM PDT 24 |
| Peak memory | 573840 kb |
| Host | smart-f5c1f39f-d153-4100-8654-968cfc858592 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471091082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.3471091082 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.1545380750 |
| Short name | T2139 |
| Test name | |
| Test status | |
| Simulation time | 43311902 ps |
| CPU time | 6.36 seconds |
| Started | Jul 31 07:48:30 PM PDT 24 |
| Finished | Jul 31 07:48:37 PM PDT 24 |
| Peak memory | 573912 kb |
| Host | smart-7bbb22ac-3db3-45e8-9fc5-69f94a240c40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545380750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delay s.1545380750 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all.184801259 |
| Short name | T2574 |
| Test name | |
| Test status | |
| Simulation time | 237888222 ps |
| CPU time | 19.87 seconds |
| Started | Jul 31 07:48:35 PM PDT 24 |
| Finished | Jul 31 07:48:54 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-bbf8f759-b618-4146-9671-bd11400f1233 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184801259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.184801259 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.3340590300 |
| Short name | T1438 |
| Test name | |
| Test status | |
| Simulation time | 678137619 ps |
| CPU time | 47.58 seconds |
| Started | Jul 31 07:48:33 PM PDT 24 |
| Finished | Jul 31 07:49:21 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-f26c720f-8211-4453-b6ef-5cf3ec8deb78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340590300 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.3340590300 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2776702501 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 2292167419 ps |
| CPU time | 362.62 seconds |
| Started | Jul 31 07:48:34 PM PDT 24 |
| Finished | Jul 31 07:54:37 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-11e45158-6f6f-4f6b-9a17-2aed52a8d694 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776702501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all _with_rand_reset.2776702501 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.327242345 |
| Short name | T2526 |
| Test name | |
| Test status | |
| Simulation time | 316853893 ps |
| CPU time | 38.87 seconds |
| Started | Jul 31 07:48:33 PM PDT 24 |
| Finished | Jul 31 07:49:12 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-87f1244f-a57e-441f-842b-a0a27fe89369 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327242345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.327242345 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.89016956 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 6754864276 ps |
| CPU time | 513.17 seconds |
| Started | Jul 31 07:48:59 PM PDT 24 |
| Finished | Jul 31 07:57:32 PM PDT 24 |
| Peak memory | 637632 kb |
| Host | smart-e9c7f452-69da-4e18-ab8c-92353a5c7a70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89016956 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 12.chip_csr_mem_rw_with_rand_reset.89016956 |
| Directory | /workspace/12.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_csr_rw.920061564 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 5072862051 ps |
| CPU time | 537.56 seconds |
| Started | Jul 31 07:48:59 PM PDT 24 |
| Finished | Jul 31 07:57:57 PM PDT 24 |
| Peak memory | 598924 kb |
| Host | smart-9c053244-b48f-4adc-b2bf-62ca9b3647e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920061564 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_rw.920061564 |
| Directory | /workspace/12.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.2927430259 |
| Short name | T2785 |
| Test name | |
| Test status | |
| Simulation time | 14371731374 ps |
| CPU time | 1959.73 seconds |
| Started | Jul 31 07:48:39 PM PDT 24 |
| Finished | Jul 31 08:21:19 PM PDT 24 |
| Peak memory | 593040 kb |
| Host | smart-92bd7b8c-2fbf-48fc-a999-b01c1263f32a |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927430259 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 12.chip_same_csr_outstanding.2927430259 |
| Directory | /workspace/12.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device.1677018357 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 293229354 ps |
| CPU time | 20.79 seconds |
| Started | Jul 31 07:48:50 PM PDT 24 |
| Finished | Jul 31 07:49:11 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-3b73b481-7471-4bd5-ad21-75fdf4cb14ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677018357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device .1677018357 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1029201113 |
| Short name | T2220 |
| Test name | |
| Test status | |
| Simulation time | 66453653492 ps |
| CPU time | 1102.97 seconds |
| Started | Jul 31 07:48:46 PM PDT 24 |
| Finished | Jul 31 08:07:09 PM PDT 24 |
| Peak memory | 576072 kb |
| Host | smart-78bd939e-b27d-411a-b7d6-914ad9a40f5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029201113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_ device_slow_rsp.1029201113 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.4137803891 |
| Short name | T2856 |
| Test name | |
| Test status | |
| Simulation time | 267944402 ps |
| CPU time | 28.72 seconds |
| Started | Jul 31 07:48:53 PM PDT 24 |
| Finished | Jul 31 07:49:21 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-21855818-d0ab-4b86-aa49-5c388315677d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137803891 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_add r.4137803891 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_random.3989721224 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 1295445385 ps |
| CPU time | 46.64 seconds |
| Started | Jul 31 07:48:52 PM PDT 24 |
| Finished | Jul 31 07:49:38 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-b3cd49be-0b5b-43ac-8402-2b0320d3448a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989721224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.3989721224 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random.1061955930 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 1858400244 ps |
| CPU time | 69.54 seconds |
| Started | Jul 31 07:48:48 PM PDT 24 |
| Finished | Jul 31 07:49:57 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-41bd0f3e-6123-4921-a498-98ca17ca9d3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061955930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random.1061955930 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_large_delays.806933816 |
| Short name | T1841 |
| Test name | |
| Test status | |
| Simulation time | 61163752995 ps |
| CPU time | 649.87 seconds |
| Started | Jul 31 07:48:51 PM PDT 24 |
| Finished | Jul 31 07:59:41 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-51c7bd01-ab2b-4817-b128-3008bb8adc40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806933816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.806933816 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.3213749111 |
| Short name | T1413 |
| Test name | |
| Test status | |
| Simulation time | 8494269115 ps |
| CPU time | 146.79 seconds |
| Started | Jul 31 07:48:46 PM PDT 24 |
| Finished | Jul 31 07:51:13 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-7dfeb686-d093-4c4d-bc0e-bb88ad5885ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213749111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.3213749111 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.574454962 |
| Short name | T1731 |
| Test name | |
| Test status | |
| Simulation time | 256527640 ps |
| CPU time | 22.91 seconds |
| Started | Jul 31 07:48:49 PM PDT 24 |
| Finished | Jul 31 07:49:12 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-519f414f-4326-42ed-bbad-cbdcc46744fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574454962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_dela ys.574454962 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_same_source.4053603295 |
| Short name | T2451 |
| Test name | |
| Test status | |
| Simulation time | 898305661 ps |
| CPU time | 26.26 seconds |
| Started | Jul 31 07:48:47 PM PDT 24 |
| Finished | Jul 31 07:49:13 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-c69be61f-ee19-4305-baba-2da5d14dd129 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053603295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.4053603295 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke.582784971 |
| Short name | T2754 |
| Test name | |
| Test status | |
| Simulation time | 246895359 ps |
| CPU time | 9.45 seconds |
| Started | Jul 31 07:48:44 PM PDT 24 |
| Finished | Jul 31 07:48:54 PM PDT 24 |
| Peak memory | 573800 kb |
| Host | smart-76c1bafc-9c32-4449-982d-2fa2c4fe3850 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582784971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.582784971 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.2703470533 |
| Short name | T1654 |
| Test name | |
| Test status | |
| Simulation time | 7368252232 ps |
| CPU time | 75.71 seconds |
| Started | Jul 31 07:48:46 PM PDT 24 |
| Finished | Jul 31 07:50:02 PM PDT 24 |
| Peak memory | 573932 kb |
| Host | smart-a328303b-b91b-4d8d-a9a8-9d306e2d057f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703470533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.2703470533 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.1854090245 |
| Short name | T2667 |
| Test name | |
| Test status | |
| Simulation time | 5423225148 ps |
| CPU time | 87.56 seconds |
| Started | Jul 31 07:48:46 PM PDT 24 |
| Finished | Jul 31 07:50:13 PM PDT 24 |
| Peak memory | 574540 kb |
| Host | smart-d971c1cf-87cc-48fa-986f-0fa27dbd89ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854090245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.1854090245 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.3634626418 |
| Short name | T2138 |
| Test name | |
| Test status | |
| Simulation time | 51409979 ps |
| CPU time | 6.65 seconds |
| Started | Jul 31 07:48:43 PM PDT 24 |
| Finished | Jul 31 07:48:50 PM PDT 24 |
| Peak memory | 574484 kb |
| Host | smart-c57de225-4920-4652-9499-229bf7024129 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634626418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delay s.3634626418 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all.1991605786 |
| Short name | T1754 |
| Test name | |
| Test status | |
| Simulation time | 2287637806 ps |
| CPU time | 197.77 seconds |
| Started | Jul 31 07:48:51 PM PDT 24 |
| Finished | Jul 31 07:52:09 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-458eb72c-9075-4e7c-b4b4-a36808075925 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991605786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.1991605786 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.1857033760 |
| Short name | T1850 |
| Test name | |
| Test status | |
| Simulation time | 7145699229 ps |
| CPU time | 251.35 seconds |
| Started | Jul 31 07:48:53 PM PDT 24 |
| Finished | Jul 31 07:53:04 PM PDT 24 |
| Peak memory | 576056 kb |
| Host | smart-5d4b1b92-efcb-4c8b-8a93-9ca0a12afa90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857033760 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.1857033760 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.1389250214 |
| Short name | T1726 |
| Test name | |
| Test status | |
| Simulation time | 8433455078 ps |
| CPU time | 443.44 seconds |
| Started | Jul 31 07:48:53 PM PDT 24 |
| Finished | Jul 31 07:56:16 PM PDT 24 |
| Peak memory | 576796 kb |
| Host | smart-8acbff2f-5414-47e7-b478-97f97ddc2a4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389250214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all _with_rand_reset.1389250214 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.1421104764 |
| Short name | T2649 |
| Test name | |
| Test status | |
| Simulation time | 587674454 ps |
| CPU time | 178.2 seconds |
| Started | Jul 31 07:48:59 PM PDT 24 |
| Finished | Jul 31 07:51:58 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-69ff024e-57ac-43ed-bd0f-2844cc96dbc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421104764 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_al l_with_reset_error.1421104764 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.754769105 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 72958133 ps |
| CPU time | 9.21 seconds |
| Started | Jul 31 07:48:48 PM PDT 24 |
| Finished | Jul 31 07:48:58 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-20d535a8-8fb5-4a1f-ae97-8c293354d385 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754769105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.754769105 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.2709849901 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 13166040432 ps |
| CPU time | 1026.72 seconds |
| Started | Jul 31 07:49:18 PM PDT 24 |
| Finished | Jul 31 08:06:25 PM PDT 24 |
| Peak memory | 645604 kb |
| Host | smart-a3939776-e83e-433b-8828-2faea43dd01f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709849901 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 13.chip_csr_mem_rw_with_rand_reset.2709849901 |
| Directory | /workspace/13.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_csr_rw.3347301119 |
| Short name | T1680 |
| Test name | |
| Test status | |
| Simulation time | 6499818655 ps |
| CPU time | 597.45 seconds |
| Started | Jul 31 07:49:15 PM PDT 24 |
| Finished | Jul 31 07:59:12 PM PDT 24 |
| Peak memory | 599036 kb |
| Host | smart-1fc2e1d1-dda9-4a24-86d7-30980fd911b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347301119 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_rw.3347301119 |
| Directory | /workspace/13.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.892780452 |
| Short name | T2412 |
| Test name | |
| Test status | |
| Simulation time | 27592309483 ps |
| CPU time | 3947.79 seconds |
| Started | Jul 31 07:48:59 PM PDT 24 |
| Finished | Jul 31 08:54:47 PM PDT 24 |
| Peak memory | 593748 kb |
| Host | smart-b7a95ae6-5a5c-4b37-8fcc-f0b562d50c56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892780452 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 13.chip_same_csr_outstanding.892780452 |
| Directory | /workspace/13.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_tl_errors.4181931580 |
| Short name | T2806 |
| Test name | |
| Test status | |
| Simulation time | 4167177268 ps |
| CPU time | 296.77 seconds |
| Started | Jul 31 07:48:59 PM PDT 24 |
| Finished | Jul 31 07:53:56 PM PDT 24 |
| Peak memory | 603660 kb |
| Host | smart-c74fa65e-4027-4590-bed9-3eccf46caf8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181931580 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_tl_errors.4181931580 |
| Directory | /workspace/13.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.2706959265 |
| Short name | T2081 |
| Test name | |
| Test status | |
| Simulation time | 67679787136 ps |
| CPU time | 1224.14 seconds |
| Started | Jul 31 07:49:12 PM PDT 24 |
| Finished | Jul 31 08:09:36 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-9b2cb05d-42c1-4499-a164-af3a480e2568 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706959265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_ device_slow_rsp.2706959265 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.1489225949 |
| Short name | T1581 |
| Test name | |
| Test status | |
| Simulation time | 53254122 ps |
| CPU time | 8.19 seconds |
| Started | Jul 31 07:49:12 PM PDT 24 |
| Finished | Jul 31 07:49:20 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-dd96d8e8-b186-49f0-94d4-0e6db313485f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489225949 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_add r.1489225949 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_random.610149237 |
| Short name | T2770 |
| Test name | |
| Test status | |
| Simulation time | 1772682555 ps |
| CPU time | 56.88 seconds |
| Started | Jul 31 07:49:09 PM PDT 24 |
| Finished | Jul 31 07:50:06 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-71c6296b-9547-416a-bfba-6181cc0c0fb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610149237 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.610149237 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random.1166026966 |
| Short name | T1983 |
| Test name | |
| Test status | |
| Simulation time | 67095506 ps |
| CPU time | 9.06 seconds |
| Started | Jul 31 07:49:06 PM PDT 24 |
| Finished | Jul 31 07:49:15 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-98a2f0df-f7e2-4f4b-8c27-339acd277454 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166026966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random.1166026966 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_large_delays.324759127 |
| Short name | T2447 |
| Test name | |
| Test status | |
| Simulation time | 36362190793 ps |
| CPU time | 417.05 seconds |
| Started | Jul 31 07:49:05 PM PDT 24 |
| Finished | Jul 31 07:56:02 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-33a1df5a-f777-407a-91bd-97b2ae70b545 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324759127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.324759127 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.1807402275 |
| Short name | T1536 |
| Test name | |
| Test status | |
| Simulation time | 22963785384 ps |
| CPU time | 396.58 seconds |
| Started | Jul 31 07:49:04 PM PDT 24 |
| Finished | Jul 31 07:55:41 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-567d77f2-df0a-4b43-908e-7275750802ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807402275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.1807402275 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.1985219604 |
| Short name | T2242 |
| Test name | |
| Test status | |
| Simulation time | 227192691 ps |
| CPU time | 20.8 seconds |
| Started | Jul 31 07:49:04 PM PDT 24 |
| Finished | Jul 31 07:49:25 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-5f5ea934-94c4-4073-acb2-e4405e1dfa8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985219604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_del ays.1985219604 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_same_source.784859593 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 345099473 ps |
| CPU time | 24.36 seconds |
| Started | Jul 31 07:49:13 PM PDT 24 |
| Finished | Jul 31 07:49:37 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-cac22938-34e2-4926-91ad-dbb1b8dd6763 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784859593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.784859593 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke.2743823945 |
| Short name | T1922 |
| Test name | |
| Test status | |
| Simulation time | 40714306 ps |
| CPU time | 5.88 seconds |
| Started | Jul 31 07:49:00 PM PDT 24 |
| Finished | Jul 31 07:49:06 PM PDT 24 |
| Peak memory | 573804 kb |
| Host | smart-6ca7f6f6-69df-4bc1-9d69-9ba5abc53008 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743823945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.2743823945 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.136236256 |
| Short name | T1459 |
| Test name | |
| Test status | |
| Simulation time | 6203130725 ps |
| CPU time | 59.67 seconds |
| Started | Jul 31 07:49:04 PM PDT 24 |
| Finished | Jul 31 07:50:04 PM PDT 24 |
| Peak memory | 573868 kb |
| Host | smart-c67e9377-1a9f-4594-9958-562854348020 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136236256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.136236256 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.893470212 |
| Short name | T1661 |
| Test name | |
| Test status | |
| Simulation time | 6414800497 ps |
| CPU time | 105.69 seconds |
| Started | Jul 31 07:49:04 PM PDT 24 |
| Finished | Jul 31 07:50:50 PM PDT 24 |
| Peak memory | 574544 kb |
| Host | smart-6dc03eca-f3b1-454a-ba94-4248190d753a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893470212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.893470212 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.1509664923 |
| Short name | T1589 |
| Test name | |
| Test status | |
| Simulation time | 46038783 ps |
| CPU time | 6.85 seconds |
| Started | Jul 31 07:48:59 PM PDT 24 |
| Finished | Jul 31 07:49:06 PM PDT 24 |
| Peak memory | 573728 kb |
| Host | smart-204c1487-9277-4c1f-9a36-d13f7e927ca2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509664923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delay s.1509664923 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all.3068564100 |
| Short name | T2145 |
| Test name | |
| Test status | |
| Simulation time | 732503354 ps |
| CPU time | 28.32 seconds |
| Started | Jul 31 07:49:11 PM PDT 24 |
| Finished | Jul 31 07:49:39 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-721d1db3-f724-448e-8bb2-76cdc6d110e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068564100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.3068564100 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.4265112017 |
| Short name | T2237 |
| Test name | |
| Test status | |
| Simulation time | 2901132051 ps |
| CPU time | 99.8 seconds |
| Started | Jul 31 07:49:11 PM PDT 24 |
| Finished | Jul 31 07:50:51 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-d7f58d92-8527-4de4-b756-1a00f1adc369 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265112017 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.4265112017 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.4161437282 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 5619182022 ps |
| CPU time | 381.22 seconds |
| Started | Jul 31 07:49:15 PM PDT 24 |
| Finished | Jul 31 07:55:36 PM PDT 24 |
| Peak memory | 576796 kb |
| Host | smart-66a38435-7248-4a4b-9c71-f1edeaeb933a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161437282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all _with_rand_reset.4161437282 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.3866067167 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 104069195 ps |
| CPU time | 36.71 seconds |
| Started | Jul 31 07:49:10 PM PDT 24 |
| Finished | Jul 31 07:49:47 PM PDT 24 |
| Peak memory | 576080 kb |
| Host | smart-3de60328-d4cb-4172-98fb-25adc7b63480 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866067167 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_al l_with_reset_error.3866067167 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.387634959 |
| Short name | T2419 |
| Test name | |
| Test status | |
| Simulation time | 25620166 ps |
| CPU time | 5.63 seconds |
| Started | Jul 31 07:49:15 PM PDT 24 |
| Finished | Jul 31 07:49:21 PM PDT 24 |
| Peak memory | 573872 kb |
| Host | smart-97724024-1f4e-4c22-8ad3-552bc09508ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387634959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.387634959 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.2052211309 |
| Short name | T1810 |
| Test name | |
| Test status | |
| Simulation time | 6275858640 ps |
| CPU time | 509.17 seconds |
| Started | Jul 31 07:49:35 PM PDT 24 |
| Finished | Jul 31 07:58:05 PM PDT 24 |
| Peak memory | 640552 kb |
| Host | smart-1f8bf806-13b7-4cee-bdcb-e3d67ae3e738 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052211309 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 14.chip_csr_mem_rw_with_rand_reset.2052211309 |
| Directory | /workspace/14.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_csr_rw.646857733 |
| Short name | T2437 |
| Test name | |
| Test status | |
| Simulation time | 5241295329 ps |
| CPU time | 472.98 seconds |
| Started | Jul 31 07:49:31 PM PDT 24 |
| Finished | Jul 31 07:57:24 PM PDT 24 |
| Peak memory | 599208 kb |
| Host | smart-48995ef8-05ce-454c-a466-ffb5c912d692 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646857733 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_csr_rw.646857733 |
| Directory | /workspace/14.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.147172987 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 17370114938 ps |
| CPU time | 1907.41 seconds |
| Started | Jul 31 07:49:20 PM PDT 24 |
| Finished | Jul 31 08:21:08 PM PDT 24 |
| Peak memory | 593388 kb |
| Host | smart-54adb23c-5feb-4ad5-a7b0-522288c8a0e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147172987 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 14.chip_same_csr_outstanding.147172987 |
| Directory | /workspace/14.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_tl_errors.2608820959 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 3493991995 ps |
| CPU time | 189.13 seconds |
| Started | Jul 31 07:49:20 PM PDT 24 |
| Finished | Jul 31 07:52:29 PM PDT 24 |
| Peak memory | 603752 kb |
| Host | smart-be39ba19-93e9-4338-af1b-580aa3b78346 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608820959 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_tl_errors.2608820959 |
| Directory | /workspace/14.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device.40828451 |
| Short name | T2448 |
| Test name | |
| Test status | |
| Simulation time | 2351390443 ps |
| CPU time | 104.47 seconds |
| Started | Jul 31 07:49:25 PM PDT 24 |
| Finished | Jul 31 07:51:09 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-43c5bdae-89d3-4f92-9241-ffc498de5150 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40828451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.40828451 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.3963482052 |
| Short name | T2604 |
| Test name | |
| Test status | |
| Simulation time | 41558276940 ps |
| CPU time | 676.79 seconds |
| Started | Jul 31 07:49:25 PM PDT 24 |
| Finished | Jul 31 08:00:42 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-04426b2f-1220-46c0-a651-327880e57a4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963482052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_ device_slow_rsp.3963482052 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.1398905650 |
| Short name | T1660 |
| Test name | |
| Test status | |
| Simulation time | 1116684461 ps |
| CPU time | 43.01 seconds |
| Started | Jul 31 07:49:31 PM PDT 24 |
| Finished | Jul 31 07:50:14 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-93c80991-cc70-40ee-ba75-36398bc47b75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398905650 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_add r.1398905650 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_random.1998411621 |
| Short name | T2062 |
| Test name | |
| Test status | |
| Simulation time | 58053771 ps |
| CPU time | 7.76 seconds |
| Started | Jul 31 07:49:31 PM PDT 24 |
| Finished | Jul 31 07:49:39 PM PDT 24 |
| Peak memory | 573808 kb |
| Host | smart-dc595625-433a-4c28-ac8a-0fe1415aa5eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998411621 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.1998411621 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random.1953702002 |
| Short name | T2187 |
| Test name | |
| Test status | |
| Simulation time | 432861725 ps |
| CPU time | 38.64 seconds |
| Started | Jul 31 07:49:27 PM PDT 24 |
| Finished | Jul 31 07:50:06 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-12dbc20c-95a9-49a2-a091-6774b381592a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953702002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random.1953702002 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_large_delays.3545717491 |
| Short name | T2325 |
| Test name | |
| Test status | |
| Simulation time | 56682622959 ps |
| CPU time | 603.1 seconds |
| Started | Jul 31 07:49:26 PM PDT 24 |
| Finished | Jul 31 07:59:29 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-1d506e10-0cae-4197-8010-4d152392d718 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545717491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.3545717491 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.1858316045 |
| Short name | T2235 |
| Test name | |
| Test status | |
| Simulation time | 18516759625 ps |
| CPU time | 314.97 seconds |
| Started | Jul 31 07:49:24 PM PDT 24 |
| Finished | Jul 31 07:54:39 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-ee6f52c7-acfc-4bbb-8e3a-afccfed54d9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858316045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.1858316045 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.120836693 |
| Short name | T2067 |
| Test name | |
| Test status | |
| Simulation time | 415437985 ps |
| CPU time | 40.46 seconds |
| Started | Jul 31 07:49:24 PM PDT 24 |
| Finished | Jul 31 07:50:05 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-f97cdedd-7710-466c-81ee-fa6f5de65070 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120836693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_dela ys.120836693 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_same_source.4050629923 |
| Short name | T1648 |
| Test name | |
| Test status | |
| Simulation time | 500509347 ps |
| CPU time | 35.96 seconds |
| Started | Jul 31 07:49:30 PM PDT 24 |
| Finished | Jul 31 07:50:06 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-d7f89035-802a-4f7d-b8ee-90049189886f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050629923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.4050629923 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke.2647820177 |
| Short name | T2083 |
| Test name | |
| Test status | |
| Simulation time | 222863387 ps |
| CPU time | 9.38 seconds |
| Started | Jul 31 07:49:26 PM PDT 24 |
| Finished | Jul 31 07:49:35 PM PDT 24 |
| Peak memory | 573788 kb |
| Host | smart-8edf8bed-eafa-4668-a00c-f8ee0f7eff87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647820177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.2647820177 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.2253482261 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 9869784398 ps |
| CPU time | 96.74 seconds |
| Started | Jul 31 07:49:24 PM PDT 24 |
| Finished | Jul 31 07:51:01 PM PDT 24 |
| Peak memory | 573904 kb |
| Host | smart-2cfdb791-b9f2-4372-a5b0-fbcc385bc9b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253482261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.2253482261 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.2138951289 |
| Short name | T2032 |
| Test name | |
| Test status | |
| Simulation time | 4264460590 ps |
| CPU time | 73.16 seconds |
| Started | Jul 31 07:49:25 PM PDT 24 |
| Finished | Jul 31 07:50:38 PM PDT 24 |
| Peak memory | 573968 kb |
| Host | smart-d02ba4ff-f271-4b3f-8452-edf8863f4cee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138951289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.2138951289 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.2661798203 |
| Short name | T1436 |
| Test name | |
| Test status | |
| Simulation time | 51152096 ps |
| CPU time | 6.58 seconds |
| Started | Jul 31 07:49:24 PM PDT 24 |
| Finished | Jul 31 07:49:31 PM PDT 24 |
| Peak memory | 573800 kb |
| Host | smart-ebaf5ee7-1641-4cfa-815f-47398302d285 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661798203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delay s.2661798203 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all.1369959310 |
| Short name | T2352 |
| Test name | |
| Test status | |
| Simulation time | 19578616434 ps |
| CPU time | 733.5 seconds |
| Started | Jul 31 07:49:32 PM PDT 24 |
| Finished | Jul 31 08:01:46 PM PDT 24 |
| Peak memory | 576084 kb |
| Host | smart-345db4f8-bddc-43b0-aa48-f00bd284d970 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369959310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.1369959310 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.1819399181 |
| Short name | T2545 |
| Test name | |
| Test status | |
| Simulation time | 134776110 ps |
| CPU time | 14.64 seconds |
| Started | Jul 31 07:49:31 PM PDT 24 |
| Finished | Jul 31 07:49:45 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-d97498c5-d970-4ec7-b9c2-e3e9d328eb76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819399181 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.1819399181 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.2701665975 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 21063123802 ps |
| CPU time | 916.86 seconds |
| Started | Jul 31 07:49:32 PM PDT 24 |
| Finished | Jul 31 08:04:49 PM PDT 24 |
| Peak memory | 576820 kb |
| Host | smart-31be5980-e4bd-4f24-8b6d-05a9bf871c1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701665975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all _with_rand_reset.2701665975 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.4231774979 |
| Short name | T2912 |
| Test name | |
| Test status | |
| Simulation time | 47392477 ps |
| CPU time | 20.65 seconds |
| Started | Jul 31 07:49:33 PM PDT 24 |
| Finished | Jul 31 07:49:53 PM PDT 24 |
| Peak memory | 574012 kb |
| Host | smart-65e80c8c-5c9f-4260-95c9-ddc86a6ebdb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231774979 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_al l_with_reset_error.4231774979 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.2784824298 |
| Short name | T1540 |
| Test name | |
| Test status | |
| Simulation time | 566479290 ps |
| CPU time | 27.86 seconds |
| Started | Jul 31 07:49:31 PM PDT 24 |
| Finished | Jul 31 07:49:59 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-5cb2dded-9feb-495a-b03b-cc310bd2608e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784824298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.2784824298 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.185227285 |
| Short name | T2551 |
| Test name | |
| Test status | |
| Simulation time | 7729382760 ps |
| CPU time | 475.41 seconds |
| Started | Jul 31 07:50:01 PM PDT 24 |
| Finished | Jul 31 07:57:56 PM PDT 24 |
| Peak memory | 643628 kb |
| Host | smart-9f570045-cf35-4b7d-b075-346faa6d6a91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185227285 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 15.chip_csr_mem_rw_with_rand_reset.185227285 |
| Directory | /workspace/15.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_csr_rw.301547325 |
| Short name | T1631 |
| Test name | |
| Test status | |
| Simulation time | 4774866725 ps |
| CPU time | 343.52 seconds |
| Started | Jul 31 07:50:00 PM PDT 24 |
| Finished | Jul 31 07:55:43 PM PDT 24 |
| Peak memory | 598580 kb |
| Host | smart-ab3765c4-e158-471f-a594-c9800cb154df |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301547325 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_rw.301547325 |
| Directory | /workspace/15.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.858282592 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 16407721035 ps |
| CPU time | 2143.05 seconds |
| Started | Jul 31 07:49:38 PM PDT 24 |
| Finished | Jul 31 08:25:21 PM PDT 24 |
| Peak memory | 593388 kb |
| Host | smart-b90fc916-c72a-4b19-9e1a-8e9f953b95fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858282592 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 15.chip_same_csr_outstanding.858282592 |
| Directory | /workspace/15.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device.364301029 |
| Short name | T1832 |
| Test name | |
| Test status | |
| Simulation time | 1166570810 ps |
| CPU time | 45.03 seconds |
| Started | Jul 31 07:49:41 PM PDT 24 |
| Finished | Jul 31 07:50:26 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-d1718e2c-a743-4213-9828-31878657e15c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364301029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device. 364301029 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.2642358717 |
| Short name | T1576 |
| Test name | |
| Test status | |
| Simulation time | 145029638956 ps |
| CPU time | 2684.76 seconds |
| Started | Jul 31 07:49:46 PM PDT 24 |
| Finished | Jul 31 08:34:32 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-a6ca3b3f-2e43-4664-9f38-7bce0f0f486d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642358717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_ device_slow_rsp.2642358717 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.749471376 |
| Short name | T1755 |
| Test name | |
| Test status | |
| Simulation time | 1483169847 ps |
| CPU time | 56.05 seconds |
| Started | Jul 31 07:49:53 PM PDT 24 |
| Finished | Jul 31 07:50:49 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-5acd4bbf-c328-4cae-8480-409505daf2fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749471376 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr .749471376 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_random.2283834178 |
| Short name | T1517 |
| Test name | |
| Test status | |
| Simulation time | 1122792574 ps |
| CPU time | 37.69 seconds |
| Started | Jul 31 07:49:46 PM PDT 24 |
| Finished | Jul 31 07:50:24 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-d5c35158-1235-40e2-a0b2-b2a56667b924 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283834178 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.2283834178 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random.3766328466 |
| Short name | T2550 |
| Test name | |
| Test status | |
| Simulation time | 90602637 ps |
| CPU time | 6.96 seconds |
| Started | Jul 31 07:49:36 PM PDT 24 |
| Finished | Jul 31 07:49:43 PM PDT 24 |
| Peak memory | 573868 kb |
| Host | smart-6fe34bfc-3c44-48fb-9463-cb11b8c33c6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766328466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random.3766328466 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_large_delays.2120213598 |
| Short name | T1804 |
| Test name | |
| Test status | |
| Simulation time | 66013265344 ps |
| CPU time | 664.35 seconds |
| Started | Jul 31 07:49:36 PM PDT 24 |
| Finished | Jul 31 08:00:41 PM PDT 24 |
| Peak memory | 576052 kb |
| Host | smart-10f3b92b-95e7-4210-8bf0-eab57e64ac60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120213598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.2120213598 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.2831970983 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 43822160381 ps |
| CPU time | 751.04 seconds |
| Started | Jul 31 07:49:42 PM PDT 24 |
| Finished | Jul 31 08:02:13 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-eb010e79-5e1a-4ac7-bf7b-1764f11a4922 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831970983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.2831970983 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.338458453 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 564575470 ps |
| CPU time | 45.73 seconds |
| Started | Jul 31 07:49:38 PM PDT 24 |
| Finished | Jul 31 07:50:24 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-bfb1cb79-1fa6-4be2-a7c6-198606f463df |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338458453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_dela ys.338458453 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_same_source.1798404769 |
| Short name | T1879 |
| Test name | |
| Test status | |
| Simulation time | 1117261277 ps |
| CPU time | 35.03 seconds |
| Started | Jul 31 07:49:42 PM PDT 24 |
| Finished | Jul 31 07:50:17 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-b3283ec1-e8a8-4189-9193-5144533d0794 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798404769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.1798404769 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke.3126236965 |
| Short name | T2488 |
| Test name | |
| Test status | |
| Simulation time | 195376378 ps |
| CPU time | 8.75 seconds |
| Started | Jul 31 07:49:35 PM PDT 24 |
| Finished | Jul 31 07:49:44 PM PDT 24 |
| Peak memory | 573868 kb |
| Host | smart-6e5dfb0d-cc35-4e3c-a085-601c11bff439 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126236965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.3126236965 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.920828894 |
| Short name | T2598 |
| Test name | |
| Test status | |
| Simulation time | 6271312081 ps |
| CPU time | 61.65 seconds |
| Started | Jul 31 07:49:36 PM PDT 24 |
| Finished | Jul 31 07:50:38 PM PDT 24 |
| Peak memory | 573884 kb |
| Host | smart-95efd9ca-a064-44f1-a446-745849f4bacf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920828894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.920828894 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.2096351573 |
| Short name | T1474 |
| Test name | |
| Test status | |
| Simulation time | 5774375095 ps |
| CPU time | 94.85 seconds |
| Started | Jul 31 07:49:37 PM PDT 24 |
| Finished | Jul 31 07:51:12 PM PDT 24 |
| Peak memory | 574576 kb |
| Host | smart-f13b8857-1442-4cc7-b4ba-ea6bf9fc348f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096351573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.2096351573 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.284503237 |
| Short name | T1477 |
| Test name | |
| Test status | |
| Simulation time | 53360324 ps |
| CPU time | 6.5 seconds |
| Started | Jul 31 07:49:36 PM PDT 24 |
| Finished | Jul 31 07:49:43 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-495dce8e-54b9-493c-8851-d22b9a6f7b23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284503237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays .284503237 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all.1833658900 |
| Short name | T2123 |
| Test name | |
| Test status | |
| Simulation time | 8503906076 ps |
| CPU time | 323.29 seconds |
| Started | Jul 31 07:49:52 PM PDT 24 |
| Finished | Jul 31 07:55:15 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-fb0f5a4c-5ecd-4430-89a7-dee5df996fe5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833658900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.1833658900 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.3135310689 |
| Short name | T1472 |
| Test name | |
| Test status | |
| Simulation time | 11107021251 ps |
| CPU time | 436.55 seconds |
| Started | Jul 31 07:49:52 PM PDT 24 |
| Finished | Jul 31 07:57:09 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-263b3dcf-1695-43ad-9f15-294803c024aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135310689 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.3135310689 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.3143574972 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 2239555991 ps |
| CPU time | 166.82 seconds |
| Started | Jul 31 07:49:53 PM PDT 24 |
| Finished | Jul 31 07:52:40 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-28d369d3-3927-44a6-b509-2cfa9b8341a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143574972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all _with_rand_reset.3143574972 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.952185600 |
| Short name | T2603 |
| Test name | |
| Test status | |
| Simulation time | 167365444 ps |
| CPU time | 71.8 seconds |
| Started | Jul 31 07:49:55 PM PDT 24 |
| Finished | Jul 31 07:51:07 PM PDT 24 |
| Peak memory | 576684 kb |
| Host | smart-3b36fa4f-57a6-417e-b2fc-b9c177d9b8bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952185600 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all _with_reset_error.952185600 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.1344861341 |
| Short name | T2415 |
| Test name | |
| Test status | |
| Simulation time | 34482330 ps |
| CPU time | 7 seconds |
| Started | Jul 31 07:49:52 PM PDT 24 |
| Finished | Jul 31 07:49:59 PM PDT 24 |
| Peak memory | 574032 kb |
| Host | smart-8a3baaa8-dbd6-480b-972b-631923d1dca8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344861341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.1344861341 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.2061958388 |
| Short name | T2671 |
| Test name | |
| Test status | |
| Simulation time | 12979979670 ps |
| CPU time | 861.11 seconds |
| Started | Jul 31 07:50:10 PM PDT 24 |
| Finished | Jul 31 08:04:32 PM PDT 24 |
| Peak memory | 653104 kb |
| Host | smart-bdc2af55-8817-42d3-a93c-c9b5da5116f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061958388 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 16.chip_csr_mem_rw_with_rand_reset.2061958388 |
| Directory | /workspace/16.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.3733773043 |
| Short name | T2633 |
| Test name | |
| Test status | |
| Simulation time | 30854634228 ps |
| CPU time | 4252.25 seconds |
| Started | Jul 31 07:49:55 PM PDT 24 |
| Finished | Jul 31 09:00:47 PM PDT 24 |
| Peak memory | 593196 kb |
| Host | smart-26c13974-e433-440d-8f5c-a57aa2616048 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733773043 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 16.chip_same_csr_outstanding.3733773043 |
| Directory | /workspace/16.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_tl_errors.824739128 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 3180882147 ps |
| CPU time | 153.85 seconds |
| Started | Jul 31 07:50:01 PM PDT 24 |
| Finished | Jul 31 07:52:35 PM PDT 24 |
| Peak memory | 598632 kb |
| Host | smart-50a05596-f1eb-4d86-a50f-a11be8ad2452 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824739128 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_tl_errors.824739128 |
| Directory | /workspace/16.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device.128202091 |
| Short name | T2434 |
| Test name | |
| Test status | |
| Simulation time | 444907530 ps |
| CPU time | 34.43 seconds |
| Started | Jul 31 07:50:02 PM PDT 24 |
| Finished | Jul 31 07:50:36 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-26d92c5f-0b76-4f71-b2d1-ea14bd00ecaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128202091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device. 128202091 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.691092078 |
| Short name | T2027 |
| Test name | |
| Test status | |
| Simulation time | 74323745248 ps |
| CPU time | 1248.84 seconds |
| Started | Jul 31 07:50:00 PM PDT 24 |
| Finished | Jul 31 08:10:50 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-f4df04bd-3b15-4947-8d13-371b2b0e6827 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691092078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_d evice_slow_rsp.691092078 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.813670567 |
| Short name | T2521 |
| Test name | |
| Test status | |
| Simulation time | 836096061 ps |
| CPU time | 35.87 seconds |
| Started | Jul 31 07:50:00 PM PDT 24 |
| Finished | Jul 31 07:50:36 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-becf2178-04c9-4a42-9969-fc6b2168b514 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813670567 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr .813670567 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_random.3074749853 |
| Short name | T1601 |
| Test name | |
| Test status | |
| Simulation time | 177273879 ps |
| CPU time | 15.67 seconds |
| Started | Jul 31 07:50:03 PM PDT 24 |
| Finished | Jul 31 07:50:19 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-8b391776-429b-4743-9fc5-cb8b16dddd5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074749853 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.3074749853 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random.2650002171 |
| Short name | T2789 |
| Test name | |
| Test status | |
| Simulation time | 1678453182 ps |
| CPU time | 62.59 seconds |
| Started | Jul 31 07:50:01 PM PDT 24 |
| Finished | Jul 31 07:51:04 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-9af76ab7-567d-49bc-91d8-d4f4687b6e4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650002171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random.2650002171 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_large_delays.4077853045 |
| Short name | T1461 |
| Test name | |
| Test status | |
| Simulation time | 61941701640 ps |
| CPU time | 621.4 seconds |
| Started | Jul 31 07:50:00 PM PDT 24 |
| Finished | Jul 31 08:00:21 PM PDT 24 |
| Peak memory | 576044 kb |
| Host | smart-c44a1f6c-17ae-48de-9c75-f1955dcd15e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077853045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.4077853045 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.1409814660 |
| Short name | T2049 |
| Test name | |
| Test status | |
| Simulation time | 41091380761 ps |
| CPU time | 650.76 seconds |
| Started | Jul 31 07:50:04 PM PDT 24 |
| Finished | Jul 31 08:00:55 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-01b9e423-fff7-4ba6-b9f3-7934542de1f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409814660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.1409814660 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.4050594319 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 101285787 ps |
| CPU time | 12.86 seconds |
| Started | Jul 31 07:50:00 PM PDT 24 |
| Finished | Jul 31 07:50:13 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-bbdd37df-1e02-47a1-9fef-9b0ebe876c29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050594319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_del ays.4050594319 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_same_source.1292121706 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 1644586351 ps |
| CPU time | 50.83 seconds |
| Started | Jul 31 07:50:00 PM PDT 24 |
| Finished | Jul 31 07:50:50 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-050c9bba-2bfc-4ead-9703-9ace75d7cff1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292121706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.1292121706 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke.124429406 |
| Short name | T2727 |
| Test name | |
| Test status | |
| Simulation time | 39667898 ps |
| CPU time | 5.91 seconds |
| Started | Jul 31 07:49:55 PM PDT 24 |
| Finished | Jul 31 07:50:01 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-4802a871-e52d-4220-9e48-587d783750bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124429406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.124429406 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.3719037620 |
| Short name | T1691 |
| Test name | |
| Test status | |
| Simulation time | 6733295858 ps |
| CPU time | 65.64 seconds |
| Started | Jul 31 07:49:54 PM PDT 24 |
| Finished | Jul 31 07:51:00 PM PDT 24 |
| Peak memory | 573912 kb |
| Host | smart-419f520c-83f9-4724-91d2-1a9888205684 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719037620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.3719037620 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.2809119165 |
| Short name | T2849 |
| Test name | |
| Test status | |
| Simulation time | 4364812243 ps |
| CPU time | 76.06 seconds |
| Started | Jul 31 07:49:54 PM PDT 24 |
| Finished | Jul 31 07:51:11 PM PDT 24 |
| Peak memory | 573920 kb |
| Host | smart-1053af47-bae3-4787-8282-837767c7680a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809119165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.2809119165 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.2854467358 |
| Short name | T1686 |
| Test name | |
| Test status | |
| Simulation time | 51910425 ps |
| CPU time | 6.67 seconds |
| Started | Jul 31 07:49:56 PM PDT 24 |
| Finished | Jul 31 07:50:03 PM PDT 24 |
| Peak memory | 573784 kb |
| Host | smart-12711929-413e-4efc-8fef-10172e250515 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854467358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delay s.2854467358 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all.423148220 |
| Short name | T2373 |
| Test name | |
| Test status | |
| Simulation time | 2970613357 ps |
| CPU time | 251.83 seconds |
| Started | Jul 31 07:50:07 PM PDT 24 |
| Finished | Jul 31 07:54:19 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-d15c60c4-2764-4d78-9f19-c3794dc9e8d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423148220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.423148220 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.3143880407 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 572024804 ps |
| CPU time | 43.77 seconds |
| Started | Jul 31 07:50:08 PM PDT 24 |
| Finished | Jul 31 07:50:51 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-7a1dafc6-2620-465a-9488-f9654519366e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143880407 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.3143880407 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.1580867552 |
| Short name | T2795 |
| Test name | |
| Test status | |
| Simulation time | 2555173892 ps |
| CPU time | 159.97 seconds |
| Started | Jul 31 07:50:10 PM PDT 24 |
| Finished | Jul 31 07:52:50 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-136ee19d-36ea-44f9-a76c-68ccf42275ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580867552 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_al l_with_reset_error.1580867552 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.1354352409 |
| Short name | T2430 |
| Test name | |
| Test status | |
| Simulation time | 1460338939 ps |
| CPU time | 52.61 seconds |
| Started | Jul 31 07:50:03 PM PDT 24 |
| Finished | Jul 31 07:50:56 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-021e682c-7c5b-4d93-9b39-9ca6d1c0cfab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354352409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.1354352409 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.978955491 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 13139337205 ps |
| CPU time | 810.22 seconds |
| Started | Jul 31 07:50:23 PM PDT 24 |
| Finished | Jul 31 08:03:54 PM PDT 24 |
| Peak memory | 647508 kb |
| Host | smart-a4decc67-37fc-4093-b04d-3cec523d0070 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978955491 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 17.chip_csr_mem_rw_with_rand_reset.978955491 |
| Directory | /workspace/17.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_csr_rw.1263824119 |
| Short name | T2059 |
| Test name | |
| Test status | |
| Simulation time | 3439648056 ps |
| CPU time | 303.57 seconds |
| Started | Jul 31 07:50:24 PM PDT 24 |
| Finished | Jul 31 07:55:27 PM PDT 24 |
| Peak memory | 596924 kb |
| Host | smart-14f3e5e1-27f4-4898-87fa-345e8e78daf0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263824119 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_rw.1263824119 |
| Directory | /workspace/17.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.3236051508 |
| Short name | T1951 |
| Test name | |
| Test status | |
| Simulation time | 27526881702 ps |
| CPU time | 3653.74 seconds |
| Started | Jul 31 07:50:13 PM PDT 24 |
| Finished | Jul 31 08:51:07 PM PDT 24 |
| Peak memory | 592980 kb |
| Host | smart-af61f4b3-2a96-4cbd-b13b-f82e52c9ddee |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236051508 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 17.chip_same_csr_outstanding.3236051508 |
| Directory | /workspace/17.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device.1789314516 |
| Short name | T1496 |
| Test name | |
| Test status | |
| Simulation time | 2332638472 ps |
| CPU time | 95.28 seconds |
| Started | Jul 31 07:50:19 PM PDT 24 |
| Finished | Jul 31 07:51:54 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-a6fe81c5-34bf-4c6a-9866-8ab804f8739a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789314516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device .1789314516 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.4223735215 |
| Short name | T2860 |
| Test name | |
| Test status | |
| Simulation time | 15858879085 ps |
| CPU time | 256.06 seconds |
| Started | Jul 31 07:50:19 PM PDT 24 |
| Finished | Jul 31 07:54:36 PM PDT 24 |
| Peak memory | 576060 kb |
| Host | smart-73866d27-6f01-4158-99b9-13d0283b2bf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223735215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_ device_slow_rsp.4223735215 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.1619472394 |
| Short name | T2155 |
| Test name | |
| Test status | |
| Simulation time | 553885499 ps |
| CPU time | 25.3 seconds |
| Started | Jul 31 07:50:18 PM PDT 24 |
| Finished | Jul 31 07:50:43 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-3bd27b7e-906c-48e3-aabe-f1340c511299 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619472394 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_add r.1619472394 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_random.788360062 |
| Short name | T1551 |
| Test name | |
| Test status | |
| Simulation time | 633361549 ps |
| CPU time | 48.03 seconds |
| Started | Jul 31 07:50:17 PM PDT 24 |
| Finished | Jul 31 07:51:05 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-d82dfcb5-434e-4567-b460-3ed238316944 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788360062 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.788360062 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random.3258150930 |
| Short name | T2446 |
| Test name | |
| Test status | |
| Simulation time | 304368628 ps |
| CPU time | 14.15 seconds |
| Started | Jul 31 07:50:11 PM PDT 24 |
| Finished | Jul 31 07:50:25 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-e4bb05ec-a964-4a52-8bd6-41414a8a5461 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258150930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random.3258150930 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_large_delays.354093730 |
| Short name | T1696 |
| Test name | |
| Test status | |
| Simulation time | 67793428134 ps |
| CPU time | 700.6 seconds |
| Started | Jul 31 07:50:17 PM PDT 24 |
| Finished | Jul 31 08:01:57 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-950178f6-ce3c-4ea3-9d8a-c302e570602c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354093730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.354093730 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.1748346674 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 44293895380 ps |
| CPU time | 701.56 seconds |
| Started | Jul 31 07:50:16 PM PDT 24 |
| Finished | Jul 31 08:01:58 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-77b3f034-3ac2-42fd-a995-ed8262246306 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748346674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.1748346674 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.3400408875 |
| Short name | T2109 |
| Test name | |
| Test status | |
| Simulation time | 210462807 ps |
| CPU time | 22.43 seconds |
| Started | Jul 31 07:50:13 PM PDT 24 |
| Finished | Jul 31 07:50:35 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-e2b74917-80c2-4012-b64e-676b54831b65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400408875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_del ays.3400408875 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_same_source.1354031731 |
| Short name | T2923 |
| Test name | |
| Test status | |
| Simulation time | 399548572 ps |
| CPU time | 13.28 seconds |
| Started | Jul 31 07:50:18 PM PDT 24 |
| Finished | Jul 31 07:50:31 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-7261ec4b-cbee-4f79-963d-dcdae0c66a78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354031731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.1354031731 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke.1540436232 |
| Short name | T1837 |
| Test name | |
| Test status | |
| Simulation time | 167390105 ps |
| CPU time | 8.11 seconds |
| Started | Jul 31 07:50:12 PM PDT 24 |
| Finished | Jul 31 07:50:20 PM PDT 24 |
| Peak memory | 574480 kb |
| Host | smart-9728e6a6-e18d-458c-8fbe-da79004dab99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540436232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.1540436232 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.3674432039 |
| Short name | T2102 |
| Test name | |
| Test status | |
| Simulation time | 9657784179 ps |
| CPU time | 99.25 seconds |
| Started | Jul 31 07:50:12 PM PDT 24 |
| Finished | Jul 31 07:51:51 PM PDT 24 |
| Peak memory | 573940 kb |
| Host | smart-a4bfd28e-27f0-4a43-afe1-662aae3212ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674432039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.3674432039 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.2972185366 |
| Short name | T2405 |
| Test name | |
| Test status | |
| Simulation time | 6755723110 ps |
| CPU time | 114.48 seconds |
| Started | Jul 31 07:50:11 PM PDT 24 |
| Finished | Jul 31 07:52:06 PM PDT 24 |
| Peak memory | 573872 kb |
| Host | smart-4631a48e-84f2-4062-81fd-656216abd782 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972185366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.2972185366 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.1339878942 |
| Short name | T2403 |
| Test name | |
| Test status | |
| Simulation time | 47154847 ps |
| CPU time | 5.83 seconds |
| Started | Jul 31 07:50:11 PM PDT 24 |
| Finished | Jul 31 07:50:17 PM PDT 24 |
| Peak memory | 573744 kb |
| Host | smart-e723b3be-a00a-4e63-8f5e-7663d2ec40be |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339878942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delay s.1339878942 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all.3658558161 |
| Short name | T2097 |
| Test name | |
| Test status | |
| Simulation time | 4551903908 ps |
| CPU time | 172.82 seconds |
| Started | Jul 31 07:50:19 PM PDT 24 |
| Finished | Jul 31 07:53:12 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-7bf72dbc-0f6a-47ee-8dd9-09528390debd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658558161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.3658558161 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.136365844 |
| Short name | T1703 |
| Test name | |
| Test status | |
| Simulation time | 5280393212 ps |
| CPU time | 198.05 seconds |
| Started | Jul 31 07:50:22 PM PDT 24 |
| Finished | Jul 31 07:53:41 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-095ff835-1ffa-446d-a621-c0ceea8e0a95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136365844 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.136365844 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.4140679419 |
| Short name | T2771 |
| Test name | |
| Test status | |
| Simulation time | 731274395 ps |
| CPU time | 256.48 seconds |
| Started | Jul 31 07:50:18 PM PDT 24 |
| Finished | Jul 31 07:54:34 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-0683cc17-f305-4f08-a257-bbc7ded5bcab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140679419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all _with_rand_reset.4140679419 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.1265150322 |
| Short name | T2426 |
| Test name | |
| Test status | |
| Simulation time | 182092456 ps |
| CPU time | 75.02 seconds |
| Started | Jul 31 07:50:24 PM PDT 24 |
| Finished | Jul 31 07:51:39 PM PDT 24 |
| Peak memory | 576700 kb |
| Host | smart-53107ee5-d873-4534-8ee3-caee35bafe3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265150322 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_al l_with_reset_error.1265150322 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.733672752 |
| Short name | T2745 |
| Test name | |
| Test status | |
| Simulation time | 1218312485 ps |
| CPU time | 56.2 seconds |
| Started | Jul 31 07:50:18 PM PDT 24 |
| Finished | Jul 31 07:51:14 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-62a6c7e3-bbef-42b0-8685-e922acd99477 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733672752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.733672752 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.3830762184 |
| Short name | T1549 |
| Test name | |
| Test status | |
| Simulation time | 7593084828 ps |
| CPU time | 414.92 seconds |
| Started | Jul 31 07:50:41 PM PDT 24 |
| Finished | Jul 31 07:57:36 PM PDT 24 |
| Peak memory | 641636 kb |
| Host | smart-093e5824-6fea-426a-9525-8f14a2e3a003 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830762184 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 18.chip_csr_mem_rw_with_rand_reset.3830762184 |
| Directory | /workspace/18.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_csr_rw.2409944523 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 6457931485 ps |
| CPU time | 639.98 seconds |
| Started | Jul 31 07:50:41 PM PDT 24 |
| Finished | Jul 31 08:01:21 PM PDT 24 |
| Peak memory | 598252 kb |
| Host | smart-f3d66837-dfa5-487f-aeec-f8c065083c4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409944523 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_rw.2409944523 |
| Directory | /workspace/18.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.3246445205 |
| Short name | T2543 |
| Test name | |
| Test status | |
| Simulation time | 16286784128 ps |
| CPU time | 2251.57 seconds |
| Started | Jul 31 07:50:23 PM PDT 24 |
| Finished | Jul 31 08:27:55 PM PDT 24 |
| Peak memory | 592908 kb |
| Host | smart-65778bda-aa96-4d78-90b1-b5714aebb234 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246445205 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 18.chip_same_csr_outstanding.3246445205 |
| Directory | /workspace/18.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_tl_errors.2778201892 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 3798633065 ps |
| CPU time | 255.86 seconds |
| Started | Jul 31 07:50:23 PM PDT 24 |
| Finished | Jul 31 07:54:39 PM PDT 24 |
| Peak memory | 598624 kb |
| Host | smart-8642e78b-1d0b-4d5b-9505-8d954e0deab9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778201892 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_tl_errors.2778201892 |
| Directory | /workspace/18.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device.1988310056 |
| Short name | T2721 |
| Test name | |
| Test status | |
| Simulation time | 1992803948 ps |
| CPU time | 86.44 seconds |
| Started | Jul 31 07:50:30 PM PDT 24 |
| Finished | Jul 31 07:51:56 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-28a662ec-836b-4797-8e00-9a4bed3c8d0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988310056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device .1988310056 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.1901021071 |
| Short name | T1867 |
| Test name | |
| Test status | |
| Simulation time | 45698545670 ps |
| CPU time | 828.54 seconds |
| Started | Jul 31 07:50:35 PM PDT 24 |
| Finished | Jul 31 08:04:24 PM PDT 24 |
| Peak memory | 576052 kb |
| Host | smart-20759779-596b-4c38-9621-dcd33043801f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901021071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_ device_slow_rsp.1901021071 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.628787242 |
| Short name | T1469 |
| Test name | |
| Test status | |
| Simulation time | 736712494 ps |
| CPU time | 30.76 seconds |
| Started | Jul 31 07:50:36 PM PDT 24 |
| Finished | Jul 31 07:51:07 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-776ef24e-3db6-4d36-bb0d-7408a994bb56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628787242 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr .628787242 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_random.2313576949 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 238194774 ps |
| CPU time | 23.93 seconds |
| Started | Jul 31 07:50:37 PM PDT 24 |
| Finished | Jul 31 07:51:01 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-80e2c8cf-0cf9-4a72-a23b-7ea5fabecbc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313576949 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.2313576949 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random.310010475 |
| Short name | T2137 |
| Test name | |
| Test status | |
| Simulation time | 1202983038 ps |
| CPU time | 39.12 seconds |
| Started | Jul 31 07:50:29 PM PDT 24 |
| Finished | Jul 31 07:51:09 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-8d820402-f999-4f46-a45c-7a99248036bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310010475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random.310010475 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_large_delays.2864701866 |
| Short name | T2902 |
| Test name | |
| Test status | |
| Simulation time | 3194761897 ps |
| CPU time | 33.8 seconds |
| Started | Jul 31 07:50:30 PM PDT 24 |
| Finished | Jul 31 07:51:04 PM PDT 24 |
| Peak memory | 573868 kb |
| Host | smart-5ef1b139-cede-41c4-b349-0148560ca914 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864701866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.2864701866 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.3514814510 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 67249972461 ps |
| CPU time | 1082.16 seconds |
| Started | Jul 31 07:50:29 PM PDT 24 |
| Finished | Jul 31 08:08:32 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-253c7292-0326-434e-93a7-a6cdc849aa38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514814510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.3514814510 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.2076558626 |
| Short name | T2701 |
| Test name | |
| Test status | |
| Simulation time | 318033409 ps |
| CPU time | 25.4 seconds |
| Started | Jul 31 07:50:29 PM PDT 24 |
| Finished | Jul 31 07:50:55 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-3f13ea94-aeaa-482c-a9c9-7bfc200fb9af |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076558626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_del ays.2076558626 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_same_source.3846393215 |
| Short name | T2613 |
| Test name | |
| Test status | |
| Simulation time | 1992149131 ps |
| CPU time | 57.12 seconds |
| Started | Jul 31 07:50:37 PM PDT 24 |
| Finished | Jul 31 07:51:34 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-44d94e6b-f8d0-4fd6-abf1-b37329b3e961 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846393215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.3846393215 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke.3030750202 |
| Short name | T1603 |
| Test name | |
| Test status | |
| Simulation time | 245829764 ps |
| CPU time | 9.56 seconds |
| Started | Jul 31 07:50:24 PM PDT 24 |
| Finished | Jul 31 07:50:34 PM PDT 24 |
| Peak memory | 573924 kb |
| Host | smart-9e65fb2a-97ac-4d3d-846e-82f149a61b54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030750202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.3030750202 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.426656740 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 8371338682 ps |
| CPU time | 85.45 seconds |
| Started | Jul 31 07:50:23 PM PDT 24 |
| Finished | Jul 31 07:51:49 PM PDT 24 |
| Peak memory | 573904 kb |
| Host | smart-4533bae0-ece2-4e0f-95b3-b69004a0623f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426656740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.426656740 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.155485377 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 4905794035 ps |
| CPU time | 80.21 seconds |
| Started | Jul 31 07:50:27 PM PDT 24 |
| Finished | Jul 31 07:51:48 PM PDT 24 |
| Peak memory | 573992 kb |
| Host | smart-423eb739-2757-42b1-aa45-94ec57aad48d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155485377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.155485377 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.3780736267 |
| Short name | T1470 |
| Test name | |
| Test status | |
| Simulation time | 47392608 ps |
| CPU time | 6.57 seconds |
| Started | Jul 31 07:50:22 PM PDT 24 |
| Finished | Jul 31 07:50:29 PM PDT 24 |
| Peak memory | 574432 kb |
| Host | smart-e9f5c796-a104-4f3d-a639-8cbe82873347 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780736267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delay s.3780736267 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all.2017428667 |
| Short name | T2042 |
| Test name | |
| Test status | |
| Simulation time | 2145926392 ps |
| CPU time | 82.7 seconds |
| Started | Jul 31 07:50:39 PM PDT 24 |
| Finished | Jul 31 07:52:02 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-edb56c7a-6ca4-40cc-83b1-e6f3dd183f15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017428667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.2017428667 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.2297904902 |
| Short name | T2740 |
| Test name | |
| Test status | |
| Simulation time | 3597033288 ps |
| CPU time | 275.58 seconds |
| Started | Jul 31 07:50:40 PM PDT 24 |
| Finished | Jul 31 07:55:15 PM PDT 24 |
| Peak memory | 576824 kb |
| Host | smart-5e301fa5-0fd4-4e64-810e-513e220613cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297904902 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.2297904902 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.4030610464 |
| Short name | T1972 |
| Test name | |
| Test status | |
| Simulation time | 66598815 ps |
| CPU time | 51.01 seconds |
| Started | Jul 31 07:50:42 PM PDT 24 |
| Finished | Jul 31 07:51:33 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-cfaa0ed5-be06-4ea5-b584-7a81b016da3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030610464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all _with_rand_reset.4030610464 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.269685052 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 2368891434 ps |
| CPU time | 316.86 seconds |
| Started | Jul 31 07:50:40 PM PDT 24 |
| Finished | Jul 31 07:55:57 PM PDT 24 |
| Peak memory | 576888 kb |
| Host | smart-eeecbd6c-55c3-4866-b029-a22407e81c6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269685052 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all _with_reset_error.269685052 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.3852858892 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 62874128 ps |
| CPU time | 9.48 seconds |
| Started | Jul 31 07:50:37 PM PDT 24 |
| Finished | Jul 31 07:50:46 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-da7bcb1a-3504-4ae0-af24-706393b62ab8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852858892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.3852858892 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.1239365146 |
| Short name | T2915 |
| Test name | |
| Test status | |
| Simulation time | 11689871875 ps |
| CPU time | 879.74 seconds |
| Started | Jul 31 07:50:59 PM PDT 24 |
| Finished | Jul 31 08:05:39 PM PDT 24 |
| Peak memory | 652892 kb |
| Host | smart-0bef5bed-8bb9-4ae7-bae1-6ac8ef2d1003 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239365146 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 19.chip_csr_mem_rw_with_rand_reset.1239365146 |
| Directory | /workspace/19.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_csr_rw.3320224551 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 5750101491 ps |
| CPU time | 464.73 seconds |
| Started | Jul 31 07:50:59 PM PDT 24 |
| Finished | Jul 31 07:58:44 PM PDT 24 |
| Peak memory | 599400 kb |
| Host | smart-b3d7fa34-e716-49c1-8106-dad7513bcad9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320224551 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_csr_rw.3320224551 |
| Directory | /workspace/19.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.8959859 |
| Short name | T2165 |
| Test name | |
| Test status | |
| Simulation time | 30496834498 ps |
| CPU time | 4303.55 seconds |
| Started | Jul 31 07:50:42 PM PDT 24 |
| Finished | Jul 31 09:02:26 PM PDT 24 |
| Peak memory | 593556 kb |
| Host | smart-96a637d4-91cb-449a-8519-d86d11772876 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8959859 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 19.chip_same_csr_outstanding.8959859 |
| Directory | /workspace/19.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_tl_errors.644310412 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 3642089159 ps |
| CPU time | 255.16 seconds |
| Started | Jul 31 07:50:41 PM PDT 24 |
| Finished | Jul 31 07:54:57 PM PDT 24 |
| Peak memory | 598532 kb |
| Host | smart-7d19d71f-39ea-4f9d-aaa7-08fc939e0f7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644310412 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_tl_errors.644310412 |
| Directory | /workspace/19.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device.79376862 |
| Short name | T1494 |
| Test name | |
| Test status | |
| Simulation time | 1690608678 ps |
| CPU time | 69.42 seconds |
| Started | Jul 31 07:50:47 PM PDT 24 |
| Finished | Jul 31 07:51:57 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-f2794848-219b-4d7a-97ae-b2710ec65fc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79376862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.79376862 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.912703875 |
| Short name | T1817 |
| Test name | |
| Test status | |
| Simulation time | 58480313472 ps |
| CPU time | 979.74 seconds |
| Started | Jul 31 07:50:51 PM PDT 24 |
| Finished | Jul 31 08:07:11 PM PDT 24 |
| Peak memory | 576040 kb |
| Host | smart-ab674adf-ae8b-4115-aeac-5bef0565285c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912703875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_d evice_slow_rsp.912703875 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.1484616167 |
| Short name | T1690 |
| Test name | |
| Test status | |
| Simulation time | 297950006 ps |
| CPU time | 29.88 seconds |
| Started | Jul 31 07:50:47 PM PDT 24 |
| Finished | Jul 31 07:51:17 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-52e1fe71-8543-4b40-851f-f39b8e0ef703 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484616167 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_add r.1484616167 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_random.1413408533 |
| Short name | T1425 |
| Test name | |
| Test status | |
| Simulation time | 433409409 ps |
| CPU time | 32.15 seconds |
| Started | Jul 31 07:50:50 PM PDT 24 |
| Finished | Jul 31 07:51:23 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-55fbb50a-ea20-4f8f-9920-26e12f45b96a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413408533 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.1413408533 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random.4156653767 |
| Short name | T1977 |
| Test name | |
| Test status | |
| Simulation time | 271398450 ps |
| CPU time | 12.9 seconds |
| Started | Jul 31 07:50:47 PM PDT 24 |
| Finished | Jul 31 07:51:00 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-dd199f77-927a-4a22-a5f4-32f1f4c0a35e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156653767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random.4156653767 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_large_delays.3074732146 |
| Short name | T2735 |
| Test name | |
| Test status | |
| Simulation time | 17769279720 ps |
| CPU time | 188.23 seconds |
| Started | Jul 31 07:50:48 PM PDT 24 |
| Finished | Jul 31 07:53:56 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-1cbcd3df-675d-4e73-bc81-d98485eccaf5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074732146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.3074732146 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.176550234 |
| Short name | T2871 |
| Test name | |
| Test status | |
| Simulation time | 68514256239 ps |
| CPU time | 1188.93 seconds |
| Started | Jul 31 07:50:47 PM PDT 24 |
| Finished | Jul 31 08:10:36 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-7483898b-fa47-4235-bf32-6cedd624e20b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176550234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.176550234 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.2501514241 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 335019250 ps |
| CPU time | 30.58 seconds |
| Started | Jul 31 07:50:47 PM PDT 24 |
| Finished | Jul 31 07:51:18 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-94b1fabd-a43a-43e0-b9e4-70111814f06c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501514241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_del ays.2501514241 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_same_source.1351918703 |
| Short name | T2837 |
| Test name | |
| Test status | |
| Simulation time | 2406653890 ps |
| CPU time | 60.11 seconds |
| Started | Jul 31 07:50:47 PM PDT 24 |
| Finished | Jul 31 07:51:47 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-550726fa-e444-46a8-b14f-d8fa056bab01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351918703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.1351918703 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke.3805022208 |
| Short name | T1541 |
| Test name | |
| Test status | |
| Simulation time | 106232671 ps |
| CPU time | 6.9 seconds |
| Started | Jul 31 07:50:41 PM PDT 24 |
| Finished | Jul 31 07:50:48 PM PDT 24 |
| Peak memory | 574488 kb |
| Host | smart-664054ae-0645-42e3-ae91-32dbe3f16999 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805022208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.3805022208 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_large_delays.1499541435 |
| Short name | T1877 |
| Test name | |
| Test status | |
| Simulation time | 10433416486 ps |
| CPU time | 103.69 seconds |
| Started | Jul 31 07:50:41 PM PDT 24 |
| Finished | Jul 31 07:52:25 PM PDT 24 |
| Peak memory | 573888 kb |
| Host | smart-e6a7015b-5b5f-4e2c-a224-de7cde893033 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499541435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.1499541435 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.3780282385 |
| Short name | T2134 |
| Test name | |
| Test status | |
| Simulation time | 4911266344 ps |
| CPU time | 73.03 seconds |
| Started | Jul 31 07:50:43 PM PDT 24 |
| Finished | Jul 31 07:51:56 PM PDT 24 |
| Peak memory | 573848 kb |
| Host | smart-84ac4313-1ebc-477e-bb8a-2b2e669d4ff7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780282385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.3780282385 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.2966523832 |
| Short name | T2227 |
| Test name | |
| Test status | |
| Simulation time | 53667239 ps |
| CPU time | 6.33 seconds |
| Started | Jul 31 07:50:43 PM PDT 24 |
| Finished | Jul 31 07:50:50 PM PDT 24 |
| Peak memory | 573812 kb |
| Host | smart-8c182b9c-5485-4629-b8de-eb619da5c19b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966523832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delay s.2966523832 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all.2842899319 |
| Short name | T1740 |
| Test name | |
| Test status | |
| Simulation time | 15851797364 ps |
| CPU time | 543.06 seconds |
| Started | Jul 31 07:50:53 PM PDT 24 |
| Finished | Jul 31 07:59:56 PM PDT 24 |
| Peak memory | 576444 kb |
| Host | smart-12140d0f-9a2a-4ab3-8902-fb7f72d4607a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842899319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.2842899319 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.1732062527 |
| Short name | T1687 |
| Test name | |
| Test status | |
| Simulation time | 4850607618 ps |
| CPU time | 160.88 seconds |
| Started | Jul 31 07:50:59 PM PDT 24 |
| Finished | Jul 31 07:53:40 PM PDT 24 |
| Peak memory | 576072 kb |
| Host | smart-184aaddb-cdb9-4aa2-a08e-f896705e04a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732062527 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.1732062527 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.2396842736 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 458215342 ps |
| CPU time | 142.64 seconds |
| Started | Jul 31 07:50:52 PM PDT 24 |
| Finished | Jul 31 07:53:14 PM PDT 24 |
| Peak memory | 576832 kb |
| Host | smart-07a3bcc4-562d-4e9d-8076-a6161d018945 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396842736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all _with_rand_reset.2396842736 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.3038152145 |
| Short name | T2143 |
| Test name | |
| Test status | |
| Simulation time | 285190851 ps |
| CPU time | 85.29 seconds |
| Started | Jul 31 07:50:59 PM PDT 24 |
| Finished | Jul 31 07:52:25 PM PDT 24 |
| Peak memory | 576700 kb |
| Host | smart-43ea5422-13bd-4f07-98b7-9e5dbe63d491 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038152145 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_al l_with_reset_error.3038152145 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.4094469535 |
| Short name | T1768 |
| Test name | |
| Test status | |
| Simulation time | 188714142 ps |
| CPU time | 23.92 seconds |
| Started | Jul 31 07:50:47 PM PDT 24 |
| Finished | Jul 31 07:51:11 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-328a44af-d159-434e-89b1-2ac0b035dc85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094469535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.4094469535 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_aliasing.502636032 |
| Short name | T2916 |
| Test name | |
| Test status | |
| Simulation time | 26385884170 ps |
| CPU time | 4761.67 seconds |
| Started | Jul 31 07:45:30 PM PDT 24 |
| Finished | Jul 31 09:04:53 PM PDT 24 |
| Peak memory | 594412 kb |
| Host | smart-3c0d01b9-36d0-44c9-9aa5-2a50b9208289 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502636032 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 2.chip_csr_aliasing.502636032 |
| Directory | /workspace/2.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.755733720 |
| Short name | T2556 |
| Test name | |
| Test status | |
| Simulation time | 32599297480 ps |
| CPU time | 4093.7 seconds |
| Started | Jul 31 07:45:28 PM PDT 24 |
| Finished | Jul 31 08:53:42 PM PDT 24 |
| Peak memory | 592944 kb |
| Host | smart-747663db-0de6-442c-b728-d6190b0e143c |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755733720 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 2.chip_csr_bit_bash.755733720 |
| Directory | /workspace/2.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.1563840254 |
| Short name | T2130 |
| Test name | |
| Test status | |
| Simulation time | 8105623976 ps |
| CPU time | 594.61 seconds |
| Started | Jul 31 07:45:49 PM PDT 24 |
| Finished | Jul 31 07:55:44 PM PDT 24 |
| Peak memory | 640656 kb |
| Host | smart-5f5515d2-ec1c-4cd0-84ec-670d88ddc01b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563840254 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 2.chip_csr_mem_rw_with_rand_reset.1563840254 |
| Directory | /workspace/2.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_rw.3709541543 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 5839934120 ps |
| CPU time | 611.75 seconds |
| Started | Jul 31 07:45:48 PM PDT 24 |
| Finished | Jul 31 07:56:00 PM PDT 24 |
| Peak memory | 599044 kb |
| Host | smart-8b5e09d6-bbd8-47e2-9996-2fcf543b8f18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709541543 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_rw.3709541543 |
| Directory | /workspace/2.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_prim_tl_access.2705008420 |
| Short name | T1919 |
| Test name | |
| Test status | |
| Simulation time | 8937064350 ps |
| CPU time | 354.68 seconds |
| Started | Jul 31 07:45:40 PM PDT 24 |
| Finished | Jul 31 07:51:35 PM PDT 24 |
| Peak memory | 591488 kb |
| Host | smart-78b94536-ed88-4146-93cb-18cbeaee1aa8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705008420 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_prim_tl_access.2705008420 |
| Directory | /workspace/2.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.1847810933 |
| Short name | T2799 |
| Test name | |
| Test status | |
| Simulation time | 14018268458 ps |
| CPU time | 494.66 seconds |
| Started | Jul 31 07:45:37 PM PDT 24 |
| Finished | Jul 31 07:53:51 PM PDT 24 |
| Peak memory | 591324 kb |
| Host | smart-7661bfb9-84cb-454b-a61b-795ca1a642f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847810933 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_lc_disabled.1847810933 |
| Directory | /workspace/2.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.3019532614 |
| Short name | T1815 |
| Test name | |
| Test status | |
| Simulation time | 15301321024 ps |
| CPU time | 1983.05 seconds |
| Started | Jul 31 07:45:32 PM PDT 24 |
| Finished | Jul 31 08:18:36 PM PDT 24 |
| Peak memory | 593384 kb |
| Host | smart-b49a5c87-4603-44ac-874c-90ae69b03b1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019532614 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 2.chip_same_csr_outstanding.3019532614 |
| Directory | /workspace/2.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_tl_errors.1074458788 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 3043280325 ps |
| CPU time | 196.54 seconds |
| Started | Jul 31 07:45:40 PM PDT 24 |
| Finished | Jul 31 07:48:57 PM PDT 24 |
| Peak memory | 603764 kb |
| Host | smart-8044ef02-c198-48c3-8cd9-3873fffad710 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074458788 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_tl_errors.1074458788 |
| Directory | /workspace/2.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device.2812457912 |
| Short name | T2474 |
| Test name | |
| Test status | |
| Simulation time | 2809171371 ps |
| CPU time | 122.7 seconds |
| Started | Jul 31 07:45:41 PM PDT 24 |
| Finished | Jul 31 07:47:44 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-f27f1ebf-7ff3-4c57-af15-a41913ab5eab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812457912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device. 2812457912 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.3492463061 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 49967614325 ps |
| CPU time | 851.79 seconds |
| Started | Jul 31 07:45:42 PM PDT 24 |
| Finished | Jul 31 07:59:54 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-29bb3c4d-047b-44b2-8967-75c8d71c358c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492463061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_d evice_slow_rsp.3492463061 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.3159017125 |
| Short name | T1735 |
| Test name | |
| Test status | |
| Simulation time | 290490335 ps |
| CPU time | 34.25 seconds |
| Started | Jul 31 07:45:42 PM PDT 24 |
| Finished | Jul 31 07:46:16 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-fa50fce7-a139-4aee-a074-40d8a5cd9b53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159017125 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr .3159017125 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_random.1343430943 |
| Short name | T1495 |
| Test name | |
| Test status | |
| Simulation time | 2101989725 ps |
| CPU time | 73.22 seconds |
| Started | Jul 31 07:45:42 PM PDT 24 |
| Finished | Jul 31 07:46:56 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-7d360a43-6bd1-47d5-a125-6c46a4376205 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343430943 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.1343430943 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random.2475555790 |
| Short name | T2700 |
| Test name | |
| Test status | |
| Simulation time | 582328803 ps |
| CPU time | 53.67 seconds |
| Started | Jul 31 07:45:44 PM PDT 24 |
| Finished | Jul 31 07:46:38 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-00b6405d-17f6-411d-8785-2714d6d62afb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475555790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random.2475555790 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_large_delays.2741042315 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 31817993789 ps |
| CPU time | 327.6 seconds |
| Started | Jul 31 07:45:42 PM PDT 24 |
| Finished | Jul 31 07:51:10 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-b8977953-3050-407d-ac4b-aad9cd332128 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741042315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.2741042315 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_slow_rsp.3457875819 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 42017786034 ps |
| CPU time | 750.85 seconds |
| Started | Jul 31 07:45:42 PM PDT 24 |
| Finished | Jul 31 07:58:13 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-841ec900-dfa8-444c-9247-142546ffa476 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457875819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.3457875819 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_zero_delays.3114404501 |
| Short name | T1721 |
| Test name | |
| Test status | |
| Simulation time | 103466379 ps |
| CPU time | 11.13 seconds |
| Started | Jul 31 07:45:45 PM PDT 24 |
| Finished | Jul 31 07:45:56 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-d43d2ab7-f4e8-4b39-a318-65f53e2e636d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114404501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_dela ys.3114404501 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_same_source.2568093487 |
| Short name | T2428 |
| Test name | |
| Test status | |
| Simulation time | 1657058139 ps |
| CPU time | 48.66 seconds |
| Started | Jul 31 07:45:45 PM PDT 24 |
| Finished | Jul 31 07:46:34 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-91895be8-6045-4847-af7a-5f6440bc75dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568093487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.2568093487 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke.292375344 |
| Short name | T2829 |
| Test name | |
| Test status | |
| Simulation time | 167329438 ps |
| CPU time | 7.64 seconds |
| Started | Jul 31 07:45:35 PM PDT 24 |
| Finished | Jul 31 07:45:43 PM PDT 24 |
| Peak memory | 574500 kb |
| Host | smart-2904a0ab-bb71-420c-b410-7c6132d96f60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292375344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.292375344 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.2513110185 |
| Short name | T1408 |
| Test name | |
| Test status | |
| Simulation time | 10351203247 ps |
| CPU time | 107.07 seconds |
| Started | Jul 31 07:45:36 PM PDT 24 |
| Finished | Jul 31 07:47:24 PM PDT 24 |
| Peak memory | 574552 kb |
| Host | smart-f9baf966-1204-4606-a9b0-1638c260f7b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513110185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.2513110185 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.539084706 |
| Short name | T2269 |
| Test name | |
| Test status | |
| Simulation time | 5531689971 ps |
| CPU time | 95.93 seconds |
| Started | Jul 31 07:45:37 PM PDT 24 |
| Finished | Jul 31 07:47:13 PM PDT 24 |
| Peak memory | 573872 kb |
| Host | smart-a557a257-c560-46e2-a37b-d02830797447 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539084706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.539084706 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_zero_delays.2861514055 |
| Short name | T1446 |
| Test name | |
| Test status | |
| Simulation time | 48177716 ps |
| CPU time | 6.53 seconds |
| Started | Jul 31 07:45:38 PM PDT 24 |
| Finished | Jul 31 07:45:44 PM PDT 24 |
| Peak memory | 573816 kb |
| Host | smart-6121d362-212d-4584-8616-926626bc5597 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861514055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays .2861514055 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all.3610222081 |
| Short name | T2273 |
| Test name | |
| Test status | |
| Simulation time | 2237480634 ps |
| CPU time | 64.56 seconds |
| Started | Jul 31 07:45:50 PM PDT 24 |
| Finished | Jul 31 07:46:55 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-df9dc305-9cf2-4806-8c33-e3e1b8a59cba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610222081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.3610222081 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.2562534445 |
| Short name | T1656 |
| Test name | |
| Test status | |
| Simulation time | 116386895 ps |
| CPU time | 12.59 seconds |
| Started | Jul 31 07:45:50 PM PDT 24 |
| Finished | Jul 31 07:46:02 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-36d9c5fb-ca23-43f9-a418-e8fc16eb3ccd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562534445 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.2562534445 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.438249372 |
| Short name | T2150 |
| Test name | |
| Test status | |
| Simulation time | 2504381940 ps |
| CPU time | 453.35 seconds |
| Started | Jul 31 07:45:48 PM PDT 24 |
| Finished | Jul 31 07:53:21 PM PDT 24 |
| Peak memory | 576812 kb |
| Host | smart-c6f3a62d-469d-4ca6-97d9-45b196f01b75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438249372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_w ith_rand_reset.438249372 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.773320634 |
| Short name | T2096 |
| Test name | |
| Test status | |
| Simulation time | 591123958 ps |
| CPU time | 261.15 seconds |
| Started | Jul 31 07:45:47 PM PDT 24 |
| Finished | Jul 31 07:50:08 PM PDT 24 |
| Peak memory | 576732 kb |
| Host | smart-57c770e0-6984-440e-91cc-0345e0d69c7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773320634 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_ with_reset_error.773320634 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_unmapped_addr.1436431695 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 126341299 ps |
| CPU time | 14.83 seconds |
| Started | Jul 31 07:45:44 PM PDT 24 |
| Finished | Jul 31 07:45:58 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-e2712988-676a-46dd-9e99-00b73d6ffb34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436431695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.1436431695 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device.2126128461 |
| Short name | T2621 |
| Test name | |
| Test status | |
| Simulation time | 347538139 ps |
| CPU time | 22.61 seconds |
| Started | Jul 31 07:51:07 PM PDT 24 |
| Finished | Jul 31 07:51:29 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-1104780f-82af-44a2-a9b4-975b07b9b39c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126128461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device .2126128461 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.93619690 |
| Short name | T1883 |
| Test name | |
| Test status | |
| Simulation time | 75950522279 ps |
| CPU time | 1295.88 seconds |
| Started | Jul 31 07:51:10 PM PDT 24 |
| Finished | Jul 31 08:12:46 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-0cb5aa81-8460-43b7-8ecf-ccc76f307df9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93619690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_de vice_slow_rsp.93619690 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.2489844819 |
| Short name | T1458 |
| Test name | |
| Test status | |
| Simulation time | 167079838 ps |
| CPU time | 18.27 seconds |
| Started | Jul 31 07:51:09 PM PDT 24 |
| Finished | Jul 31 07:51:27 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-c4884a83-a449-4071-8f6f-6831a6ec0d3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489844819 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_add r.2489844819 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_random.2639903541 |
| Short name | T1531 |
| Test name | |
| Test status | |
| Simulation time | 1895521907 ps |
| CPU time | 61.81 seconds |
| Started | Jul 31 07:51:14 PM PDT 24 |
| Finished | Jul 31 07:52:16 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-a5f4edbb-b5f7-49e9-acb2-90d66781f0ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639903541 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.2639903541 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random.4267894408 |
| Short name | T2124 |
| Test name | |
| Test status | |
| Simulation time | 2088679910 ps |
| CPU time | 82.74 seconds |
| Started | Jul 31 07:51:06 PM PDT 24 |
| Finished | Jul 31 07:52:29 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-112258b4-5854-4f00-aba6-1685c8963217 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267894408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random.4267894408 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_large_delays.1227714846 |
| Short name | T2384 |
| Test name | |
| Test status | |
| Simulation time | 99826297828 ps |
| CPU time | 1058.48 seconds |
| Started | Jul 31 07:51:06 PM PDT 24 |
| Finished | Jul 31 08:08:44 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-e835dd25-c6a7-4c5a-8133-fae38c8232c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227714846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.1227714846 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_slow_rsp.3603404262 |
| Short name | T1388 |
| Test name | |
| Test status | |
| Simulation time | 7542973327 ps |
| CPU time | 129.37 seconds |
| Started | Jul 31 07:51:04 PM PDT 24 |
| Finished | Jul 31 07:53:14 PM PDT 24 |
| Peak memory | 576104 kb |
| Host | smart-a16c4f6e-9835-4252-90fc-a9055dbc16c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603404262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.3603404262 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.3489809507 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 457056166 ps |
| CPU time | 39.59 seconds |
| Started | Jul 31 07:51:06 PM PDT 24 |
| Finished | Jul 31 07:51:46 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-fb0293e1-6c3c-41ea-8526-cb9a994adc1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489809507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_del ays.3489809507 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_same_source.2288334893 |
| Short name | T1907 |
| Test name | |
| Test status | |
| Simulation time | 2210925512 ps |
| CPU time | 69.24 seconds |
| Started | Jul 31 07:51:10 PM PDT 24 |
| Finished | Jul 31 07:52:20 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-18a7c75f-b610-4999-b6c1-e50d671c3003 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288334893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.2288334893 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke.1915972430 |
| Short name | T2340 |
| Test name | |
| Test status | |
| Simulation time | 52921514 ps |
| CPU time | 6.72 seconds |
| Started | Jul 31 07:51:28 PM PDT 24 |
| Finished | Jul 31 07:51:35 PM PDT 24 |
| Peak memory | 573864 kb |
| Host | smart-5d360f78-8b7b-4b50-8ad8-a76ea6af2e9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915972430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.1915972430 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.1405146316 |
| Short name | T1698 |
| Test name | |
| Test status | |
| Simulation time | 6799361606 ps |
| CPU time | 72.1 seconds |
| Started | Jul 31 07:51:07 PM PDT 24 |
| Finished | Jul 31 07:52:19 PM PDT 24 |
| Peak memory | 574012 kb |
| Host | smart-06216b9c-3079-4b6c-b576-22e6f0a40c9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405146316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.1405146316 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.2430875480 |
| Short name | T1553 |
| Test name | |
| Test status | |
| Simulation time | 4110042515 ps |
| CPU time | 75.84 seconds |
| Started | Jul 31 07:51:05 PM PDT 24 |
| Finished | Jul 31 07:52:21 PM PDT 24 |
| Peak memory | 573824 kb |
| Host | smart-ce58f754-160e-45a1-b4cf-51bc3a3c2b01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430875480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.2430875480 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_zero_delays.3022403278 |
| Short name | T2215 |
| Test name | |
| Test status | |
| Simulation time | 57090503 ps |
| CPU time | 7.25 seconds |
| Started | Jul 31 07:51:05 PM PDT 24 |
| Finished | Jul 31 07:51:12 PM PDT 24 |
| Peak memory | 573796 kb |
| Host | smart-883ffd34-1b99-48c8-a52d-a8bca3e66ab6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022403278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delay s.3022403278 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all.3749420075 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 1317140647 ps |
| CPU time | 100.66 seconds |
| Started | Jul 31 07:51:11 PM PDT 24 |
| Finished | Jul 31 07:52:52 PM PDT 24 |
| Peak memory | 576520 kb |
| Host | smart-fc3be953-34d3-4674-8dca-9a4cb43348aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749420075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.3749420075 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.23752072 |
| Short name | T2125 |
| Test name | |
| Test status | |
| Simulation time | 2160780265 ps |
| CPU time | 174.49 seconds |
| Started | Jul 31 07:51:20 PM PDT 24 |
| Finished | Jul 31 07:54:14 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-b2ced99f-269e-4fbb-8ed8-a5f0524b7f5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23752072 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.23752072 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.2056120902 |
| Short name | T2651 |
| Test name | |
| Test status | |
| Simulation time | 3478093933 ps |
| CPU time | 561.53 seconds |
| Started | Jul 31 07:51:19 PM PDT 24 |
| Finished | Jul 31 08:00:41 PM PDT 24 |
| Peak memory | 576728 kb |
| Host | smart-1396f35b-8d04-4add-8a30-e7d8e9d4027b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056120902 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_al l_with_reset_error.2056120902 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.181529901 |
| Short name | T2527 |
| Test name | |
| Test status | |
| Simulation time | 109988168 ps |
| CPU time | 15.28 seconds |
| Started | Jul 31 07:51:10 PM PDT 24 |
| Finished | Jul 31 07:51:26 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-851bff98-c38f-4d67-9c0e-77ab62b4dfc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181529901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.181529901 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.chip_tl_errors.171405958 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 3377260370 ps |
| CPU time | 140.86 seconds |
| Started | Jul 31 07:51:17 PM PDT 24 |
| Finished | Jul 31 07:53:38 PM PDT 24 |
| Peak memory | 598624 kb |
| Host | smart-435fb84e-cda5-46ec-af2c-d353ed272f77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171405958 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.chip_tl_errors.171405958 |
| Directory | /workspace/21.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device.692304436 |
| Short name | T1571 |
| Test name | |
| Test status | |
| Simulation time | 308688861 ps |
| CPU time | 31.33 seconds |
| Started | Jul 31 07:51:31 PM PDT 24 |
| Finished | Jul 31 07:52:03 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-1f57b83e-4af3-427a-8be2-8594ecc175dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692304436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device. 692304436 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.3204574885 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 76208070672 ps |
| CPU time | 1374.53 seconds |
| Started | Jul 31 07:51:30 PM PDT 24 |
| Finished | Jul 31 08:14:25 PM PDT 24 |
| Peak memory | 576140 kb |
| Host | smart-4145b24b-cf80-468d-ac5d-de0479442dfe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204574885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_ device_slow_rsp.3204574885 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.1321836307 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 943306671 ps |
| CPU time | 36.86 seconds |
| Started | Jul 31 07:51:31 PM PDT 24 |
| Finished | Jul 31 07:52:08 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-d3f624b7-7151-4b51-a6bb-43c76816ad98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321836307 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_add r.1321836307 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_random.2419574037 |
| Short name | T1416 |
| Test name | |
| Test status | |
| Simulation time | 933851015 ps |
| CPU time | 32.29 seconds |
| Started | Jul 31 07:51:30 PM PDT 24 |
| Finished | Jul 31 07:52:03 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-bfe5a45f-ef40-48b4-a249-ec19a3d16487 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419574037 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.2419574037 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random.1777220635 |
| Short name | T2182 |
| Test name | |
| Test status | |
| Simulation time | 514327488 ps |
| CPU time | 44.55 seconds |
| Started | Jul 31 07:51:24 PM PDT 24 |
| Finished | Jul 31 07:52:09 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-4f70a90e-4f55-449f-b2c1-15b22ce43bfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777220635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random.1777220635 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_large_delays.1635924259 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 60293036526 ps |
| CPU time | 617.74 seconds |
| Started | Jul 31 07:51:24 PM PDT 24 |
| Finished | Jul 31 08:01:42 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-b5e86031-4d39-4cb1-99a6-accb712da38a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635924259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.1635924259 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_slow_rsp.259336494 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 51453059571 ps |
| CPU time | 815.9 seconds |
| Started | Jul 31 07:51:24 PM PDT 24 |
| Finished | Jul 31 08:05:00 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-d0bc899c-6ad3-46db-8ee8-e7b0ee00b37a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259336494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.259336494 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.5489110 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 337059849 ps |
| CPU time | 32.71 seconds |
| Started | Jul 31 07:51:22 PM PDT 24 |
| Finished | Jul 31 07:51:55 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-507bdf3a-a736-44ed-819d-11d189e6766f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5489110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.5489110 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_same_source.1954977481 |
| Short name | T1545 |
| Test name | |
| Test status | |
| Simulation time | 688740628 ps |
| CPU time | 22.91 seconds |
| Started | Jul 31 07:51:30 PM PDT 24 |
| Finished | Jul 31 07:51:53 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-9ae76bc9-7867-4704-8e87-acdfb961ad71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954977481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.1954977481 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke.984021912 |
| Short name | T2841 |
| Test name | |
| Test status | |
| Simulation time | 45587279 ps |
| CPU time | 6.17 seconds |
| Started | Jul 31 07:51:17 PM PDT 24 |
| Finished | Jul 31 07:51:23 PM PDT 24 |
| Peak memory | 573784 kb |
| Host | smart-0fdc24d6-2c88-42f1-ab59-a4473443170c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984021912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.984021912 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_large_delays.2667943882 |
| Short name | T1658 |
| Test name | |
| Test status | |
| Simulation time | 8167821718 ps |
| CPU time | 87.59 seconds |
| Started | Jul 31 07:51:23 PM PDT 24 |
| Finished | Jul 31 07:52:51 PM PDT 24 |
| Peak memory | 573840 kb |
| Host | smart-2a40b69f-6587-40c6-9e6e-b07b6ff7cc85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667943882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.2667943882 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.3718008904 |
| Short name | T2826 |
| Test name | |
| Test status | |
| Simulation time | 5555905261 ps |
| CPU time | 91.78 seconds |
| Started | Jul 31 07:51:26 PM PDT 24 |
| Finished | Jul 31 07:52:58 PM PDT 24 |
| Peak memory | 573924 kb |
| Host | smart-512ec35d-4ffd-4524-8930-71ff3c38d212 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718008904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.3718008904 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.1894688756 |
| Short name | T2331 |
| Test name | |
| Test status | |
| Simulation time | 48967623 ps |
| CPU time | 6.81 seconds |
| Started | Jul 31 07:51:16 PM PDT 24 |
| Finished | Jul 31 07:51:23 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-aadda821-84e2-48e0-86e1-6567b27770a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894688756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delay s.1894688756 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all.626792081 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 3906649099 ps |
| CPU time | 129.02 seconds |
| Started | Jul 31 07:51:32 PM PDT 24 |
| Finished | Jul 31 07:53:41 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-88a94587-af76-488c-b1ec-833d06a19afc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626792081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.626792081 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.3465512656 |
| Short name | T1910 |
| Test name | |
| Test status | |
| Simulation time | 8051623258 ps |
| CPU time | 299.95 seconds |
| Started | Jul 31 07:51:31 PM PDT 24 |
| Finished | Jul 31 07:56:31 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-090c357c-2c39-4c52-bda9-9c1aebea6dbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465512656 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.3465512656 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.1947018326 |
| Short name | T2514 |
| Test name | |
| Test status | |
| Simulation time | 306708436 ps |
| CPU time | 173.96 seconds |
| Started | Jul 31 07:51:29 PM PDT 24 |
| Finished | Jul 31 07:54:23 PM PDT 24 |
| Peak memory | 576812 kb |
| Host | smart-e1d7c11c-d1c5-4477-8e55-e8e50760870d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947018326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all _with_rand_reset.1947018326 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.2449572113 |
| Short name | T1705 |
| Test name | |
| Test status | |
| Simulation time | 291690226 ps |
| CPU time | 73.81 seconds |
| Started | Jul 31 07:51:30 PM PDT 24 |
| Finished | Jul 31 07:52:44 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-849fc4c8-8bdc-48df-9ab4-145d87e06985 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449572113 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_al l_with_reset_error.2449572113 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.3171473093 |
| Short name | T2808 |
| Test name | |
| Test status | |
| Simulation time | 104497038 ps |
| CPU time | 14.51 seconds |
| Started | Jul 31 07:51:32 PM PDT 24 |
| Finished | Jul 31 07:51:47 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-46b14e4b-ccb2-4494-ad9f-0bcaf96d606f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171473093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.3171473093 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.chip_tl_errors.1202882222 |
| Short name | T2807 |
| Test name | |
| Test status | |
| Simulation time | 3994787850 ps |
| CPU time | 192.62 seconds |
| Started | Jul 31 07:51:30 PM PDT 24 |
| Finished | Jul 31 07:54:43 PM PDT 24 |
| Peak memory | 603748 kb |
| Host | smart-36323c7a-703f-4477-95f7-0539cd3df15c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202882222 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.chip_tl_errors.1202882222 |
| Directory | /workspace/22.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device.92695243 |
| Short name | T1990 |
| Test name | |
| Test status | |
| Simulation time | 694171561 ps |
| CPU time | 32.95 seconds |
| Started | Jul 31 07:51:35 PM PDT 24 |
| Finished | Jul 31 07:52:08 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-500faff1-0a16-464b-b561-9247eedd9ab9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92695243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.92695243 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.2799715875 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 68495118688 ps |
| CPU time | 1297.85 seconds |
| Started | Jul 31 07:51:35 PM PDT 24 |
| Finished | Jul 31 08:13:13 PM PDT 24 |
| Peak memory | 576096 kb |
| Host | smart-ad8aad2b-d6f8-4c14-ad4e-7f2bcd88c418 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799715875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_ device_slow_rsp.2799715875 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.482109900 |
| Short name | T2110 |
| Test name | |
| Test status | |
| Simulation time | 1213862521 ps |
| CPU time | 48.9 seconds |
| Started | Jul 31 07:51:41 PM PDT 24 |
| Finished | Jul 31 07:52:30 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-dd081f68-2e6b-478d-808d-68b217410a8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482109900 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr .482109900 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_random.2729751768 |
| Short name | T2567 |
| Test name | |
| Test status | |
| Simulation time | 1200950094 ps |
| CPU time | 42.91 seconds |
| Started | Jul 31 07:51:43 PM PDT 24 |
| Finished | Jul 31 07:52:26 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-a44289b9-8c84-4eff-b79e-3ab420358108 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729751768 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.2729751768 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random.3288590658 |
| Short name | T1789 |
| Test name | |
| Test status | |
| Simulation time | 727274570 ps |
| CPU time | 21.98 seconds |
| Started | Jul 31 07:51:35 PM PDT 24 |
| Finished | Jul 31 07:51:57 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-4bb9d462-4aa4-4007-83b8-54c4670dcec0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288590658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random.3288590658 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_slow_rsp.1527908745 |
| Short name | T2669 |
| Test name | |
| Test status | |
| Simulation time | 34984088171 ps |
| CPU time | 510.14 seconds |
| Started | Jul 31 07:51:34 PM PDT 24 |
| Finished | Jul 31 08:00:05 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-3c9216d7-aa4e-44ac-8154-c7fdc6d8a33a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527908745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.1527908745 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.1016365425 |
| Short name | T1943 |
| Test name | |
| Test status | |
| Simulation time | 609275202 ps |
| CPU time | 57.31 seconds |
| Started | Jul 31 07:51:35 PM PDT 24 |
| Finished | Jul 31 07:52:32 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-2a62888b-b072-4b01-86e2-24ae6769bc98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016365425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_del ays.1016365425 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_same_source.171938451 |
| Short name | T1966 |
| Test name | |
| Test status | |
| Simulation time | 2480037970 ps |
| CPU time | 72.55 seconds |
| Started | Jul 31 07:51:40 PM PDT 24 |
| Finished | Jul 31 07:52:53 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-232ac0e8-306f-4e22-b462-be3cc35c64f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171938451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.171938451 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke.1661450166 |
| Short name | T2496 |
| Test name | |
| Test status | |
| Simulation time | 36146283 ps |
| CPU time | 5.71 seconds |
| Started | Jul 31 07:51:32 PM PDT 24 |
| Finished | Jul 31 07:51:38 PM PDT 24 |
| Peak memory | 573756 kb |
| Host | smart-05abc4e2-77d0-4975-8aaa-3435f66c20ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661450166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.1661450166 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_large_delays.3934575323 |
| Short name | T1878 |
| Test name | |
| Test status | |
| Simulation time | 6992885447 ps |
| CPU time | 72.97 seconds |
| Started | Jul 31 07:51:36 PM PDT 24 |
| Finished | Jul 31 07:52:49 PM PDT 24 |
| Peak memory | 574532 kb |
| Host | smart-2ffcf073-3749-4ce2-8a4d-238d6ab59c24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934575323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.3934575323 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.1562789258 |
| Short name | T2536 |
| Test name | |
| Test status | |
| Simulation time | 5036070438 ps |
| CPU time | 93.81 seconds |
| Started | Jul 31 07:51:35 PM PDT 24 |
| Finished | Jul 31 07:53:09 PM PDT 24 |
| Peak memory | 574544 kb |
| Host | smart-d5d40c8f-fbf5-420e-a4a0-291850d72be5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562789258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.1562789258 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_zero_delays.4146719465 |
| Short name | T1923 |
| Test name | |
| Test status | |
| Simulation time | 49514766 ps |
| CPU time | 6.25 seconds |
| Started | Jul 31 07:51:29 PM PDT 24 |
| Finished | Jul 31 07:51:36 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-0e28daa4-f106-43e3-be29-cf3a261fd16c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146719465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delay s.4146719465 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all.2789966724 |
| Short name | T2579 |
| Test name | |
| Test status | |
| Simulation time | 11317540296 ps |
| CPU time | 428.55 seconds |
| Started | Jul 31 07:51:42 PM PDT 24 |
| Finished | Jul 31 07:58:50 PM PDT 24 |
| Peak memory | 576788 kb |
| Host | smart-887931e7-cb2f-479c-bf07-a6f5d5506d08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789966724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.2789966724 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.665473254 |
| Short name | T1572 |
| Test name | |
| Test status | |
| Simulation time | 5057195361 ps |
| CPU time | 165.04 seconds |
| Started | Jul 31 07:51:40 PM PDT 24 |
| Finished | Jul 31 07:54:25 PM PDT 24 |
| Peak memory | 576072 kb |
| Host | smart-e3c5d54d-0da6-4ac5-8aca-c8a009311706 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665473254 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.665473254 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.1802972928 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 3817526775 ps |
| CPU time | 485.16 seconds |
| Started | Jul 31 07:51:44 PM PDT 24 |
| Finished | Jul 31 07:59:49 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-3a711b8c-6512-4ae4-a348-4bc1eaac4cbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802972928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all _with_rand_reset.1802972928 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.3357077840 |
| Short name | T2297 |
| Test name | |
| Test status | |
| Simulation time | 11308694027 ps |
| CPU time | 577.98 seconds |
| Started | Jul 31 07:51:47 PM PDT 24 |
| Finished | Jul 31 08:01:25 PM PDT 24 |
| Peak memory | 576804 kb |
| Host | smart-0800242c-a683-4dc9-a193-9a9e6b2b72fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357077840 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_al l_with_reset_error.3357077840 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_unmapped_addr.3557793921 |
| Short name | T2315 |
| Test name | |
| Test status | |
| Simulation time | 151349438 ps |
| CPU time | 19.99 seconds |
| Started | Jul 31 07:51:43 PM PDT 24 |
| Finished | Jul 31 07:52:03 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-6739c959-8335-4c12-9016-2cf65587b06e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557793921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.3557793921 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device.2018038252 |
| Short name | T1786 |
| Test name | |
| Test status | |
| Simulation time | 2681093972 ps |
| CPU time | 125.59 seconds |
| Started | Jul 31 07:51:53 PM PDT 24 |
| Finished | Jul 31 07:53:59 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-20252c96-45f6-496c-9979-69c638b4b59c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018038252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device .2018038252 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.1590580214 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 55882479995 ps |
| CPU time | 952.26 seconds |
| Started | Jul 31 07:51:54 PM PDT 24 |
| Finished | Jul 31 08:07:46 PM PDT 24 |
| Peak memory | 576048 kb |
| Host | smart-c8e787bc-382d-4000-bf5e-a8752ba7403f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590580214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_ device_slow_rsp.1590580214 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.421036753 |
| Short name | T2697 |
| Test name | |
| Test status | |
| Simulation time | 130624631 ps |
| CPU time | 8.47 seconds |
| Started | Jul 31 07:51:55 PM PDT 24 |
| Finished | Jul 31 07:52:03 PM PDT 24 |
| Peak memory | 573896 kb |
| Host | smart-73ef225f-1d41-42e2-91ef-4723f637e13f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421036753 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr .421036753 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_random.594827904 |
| Short name | T1473 |
| Test name | |
| Test status | |
| Simulation time | 2417525427 ps |
| CPU time | 86.3 seconds |
| Started | Jul 31 07:52:00 PM PDT 24 |
| Finished | Jul 31 07:53:27 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-5cafc3aa-106a-447c-992f-13be80f5f886 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594827904 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.594827904 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random.1496468438 |
| Short name | T2113 |
| Test name | |
| Test status | |
| Simulation time | 275737773 ps |
| CPU time | 28.11 seconds |
| Started | Jul 31 07:51:53 PM PDT 24 |
| Finished | Jul 31 07:52:21 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-f72fcca3-fbe3-40ab-b56b-ddf66e072ccc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496468438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random.1496468438 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_large_delays.785325273 |
| Short name | T2231 |
| Test name | |
| Test status | |
| Simulation time | 22362599129 ps |
| CPU time | 228.33 seconds |
| Started | Jul 31 07:51:53 PM PDT 24 |
| Finished | Jul 31 07:55:42 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-99e9f4e3-fbf5-4b20-9bda-a8d812d0bb15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785325273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.785325273 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.102010960 |
| Short name | T1980 |
| Test name | |
| Test status | |
| Simulation time | 42049045843 ps |
| CPU time | 719.95 seconds |
| Started | Jul 31 07:51:59 PM PDT 24 |
| Finished | Jul 31 08:04:00 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-e3e0dd1f-429d-493f-982d-79ff15dcfa40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102010960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.102010960 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_zero_delays.1810464235 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 427566745 ps |
| CPU time | 35.39 seconds |
| Started | Jul 31 07:51:53 PM PDT 24 |
| Finished | Jul 31 07:52:28 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-158abfc0-d645-4d6f-9045-42b20f5d38fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810464235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_del ays.1810464235 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_same_source.3614085966 |
| Short name | T2000 |
| Test name | |
| Test status | |
| Simulation time | 491668203 ps |
| CPU time | 16.08 seconds |
| Started | Jul 31 07:51:53 PM PDT 24 |
| Finished | Jul 31 07:52:10 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-fe0a7dee-eb35-4b2b-a512-74cf5f851489 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614085966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.3614085966 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke.562952278 |
| Short name | T1924 |
| Test name | |
| Test status | |
| Simulation time | 40737159 ps |
| CPU time | 5.91 seconds |
| Started | Jul 31 07:51:47 PM PDT 24 |
| Finished | Jul 31 07:51:53 PM PDT 24 |
| Peak memory | 573840 kb |
| Host | smart-75453301-659f-42cb-a2cb-978cec9b7b4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562952278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.562952278 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_large_delays.2988535 |
| Short name | T1728 |
| Test name | |
| Test status | |
| Simulation time | 9224176021 ps |
| CPU time | 93.37 seconds |
| Started | Jul 31 07:51:53 PM PDT 24 |
| Finished | Jul 31 07:53:27 PM PDT 24 |
| Peak memory | 574532 kb |
| Host | smart-d3136858-57cd-4715-be2e-f578772eebb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.2988535 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.3331037771 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 5726615860 ps |
| CPU time | 96.71 seconds |
| Started | Jul 31 07:51:46 PM PDT 24 |
| Finished | Jul 31 07:53:23 PM PDT 24 |
| Peak memory | 573932 kb |
| Host | smart-fee50116-9e23-4011-8981-0ec0aacf46f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331037771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.3331037771 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_zero_delays.111037606 |
| Short name | T2866 |
| Test name | |
| Test status | |
| Simulation time | 44749512 ps |
| CPU time | 6.21 seconds |
| Started | Jul 31 07:51:53 PM PDT 24 |
| Finished | Jul 31 07:51:59 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-a9d5fa00-79e6-44ce-85d4-7ccb23e72160 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111037606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays .111037606 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all.948402457 |
| Short name | T2587 |
| Test name | |
| Test status | |
| Simulation time | 2202455981 ps |
| CPU time | 92.23 seconds |
| Started | Jul 31 07:51:53 PM PDT 24 |
| Finished | Jul 31 07:53:25 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-6b0321da-a8ce-4d89-b14b-8b9fb4b81b1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948402457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.948402457 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.584599692 |
| Short name | T1403 |
| Test name | |
| Test status | |
| Simulation time | 771938725 ps |
| CPU time | 64.2 seconds |
| Started | Jul 31 07:52:00 PM PDT 24 |
| Finished | Jul 31 07:53:05 PM PDT 24 |
| Peak memory | 576088 kb |
| Host | smart-c15f91d5-a59c-4469-810c-c63137174804 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584599692 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.584599692 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.1248394696 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 4730819222 ps |
| CPU time | 341.74 seconds |
| Started | Jul 31 07:52:02 PM PDT 24 |
| Finished | Jul 31 07:57:44 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-35448857-e40b-4368-9a8c-570e5ecfe2e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248394696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all _with_rand_reset.1248394696 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.1048747758 |
| Short name | T2678 |
| Test name | |
| Test status | |
| Simulation time | 6944472390 ps |
| CPU time | 327.33 seconds |
| Started | Jul 31 07:52:00 PM PDT 24 |
| Finished | Jul 31 07:57:27 PM PDT 24 |
| Peak memory | 576716 kb |
| Host | smart-7bff55ce-e6a3-4ab6-ab99-3a5c4915ef1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048747758 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_al l_with_reset_error.1048747758 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.2351330209 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 306630697 ps |
| CPU time | 33.98 seconds |
| Started | Jul 31 07:51:53 PM PDT 24 |
| Finished | Jul 31 07:52:27 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-9a58fd26-6739-4f60-9af6-b8ab53f81478 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351330209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.2351330209 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device.2537433350 |
| Short name | T2696 |
| Test name | |
| Test status | |
| Simulation time | 194467046 ps |
| CPU time | 12.46 seconds |
| Started | Jul 31 07:52:07 PM PDT 24 |
| Finished | Jul 31 07:52:19 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-2e6fad19-6018-433a-aabb-3fff621dc50d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537433350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device .2537433350 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.2744719413 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 91686427478 ps |
| CPU time | 1611.07 seconds |
| Started | Jul 31 07:52:06 PM PDT 24 |
| Finished | Jul 31 08:18:57 PM PDT 24 |
| Peak memory | 576052 kb |
| Host | smart-ecf72762-b81f-43b3-a43f-7b801a8fa69c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744719413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_ device_slow_rsp.2744719413 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.1082310673 |
| Short name | T2454 |
| Test name | |
| Test status | |
| Simulation time | 642174573 ps |
| CPU time | 24.41 seconds |
| Started | Jul 31 07:52:13 PM PDT 24 |
| Finished | Jul 31 07:52:37 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-3687e5a2-4789-415e-ae59-d161bafba1ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082310673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_add r.1082310673 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_random.681226395 |
| Short name | T2342 |
| Test name | |
| Test status | |
| Simulation time | 2130666568 ps |
| CPU time | 71.88 seconds |
| Started | Jul 31 07:52:14 PM PDT 24 |
| Finished | Jul 31 07:53:26 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-a65821d0-61fb-41ae-b6cb-55da6b3dd75f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681226395 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.681226395 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random.225025586 |
| Short name | T1511 |
| Test name | |
| Test status | |
| Simulation time | 151480628 ps |
| CPU time | 13.91 seconds |
| Started | Jul 31 07:52:06 PM PDT 24 |
| Finished | Jul 31 07:52:20 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-b5aa98f0-7e53-4df8-b320-79b39b624d35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225025586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random.225025586 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.3320793735 |
| Short name | T2859 |
| Test name | |
| Test status | |
| Simulation time | 5832455165 ps |
| CPU time | 64.38 seconds |
| Started | Jul 31 07:52:06 PM PDT 24 |
| Finished | Jul 31 07:53:11 PM PDT 24 |
| Peak memory | 573944 kb |
| Host | smart-d3163372-08eb-497f-94e0-2950952ab139 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320793735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.3320793735 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_slow_rsp.4093936519 |
| Short name | T2098 |
| Test name | |
| Test status | |
| Simulation time | 28969863544 ps |
| CPU time | 509.44 seconds |
| Started | Jul 31 07:52:05 PM PDT 24 |
| Finished | Jul 31 08:00:34 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-865f525f-71c5-4372-bb00-6adfe9adf6e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093936519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.4093936519 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_zero_delays.4279949424 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 125422836 ps |
| CPU time | 11.61 seconds |
| Started | Jul 31 07:52:07 PM PDT 24 |
| Finished | Jul 31 07:52:18 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-755f0ef9-279c-48c3-b925-bb0350d47e71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279949424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_del ays.4279949424 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_same_source.2886340438 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 1095873312 ps |
| CPU time | 33.96 seconds |
| Started | Jul 31 07:52:05 PM PDT 24 |
| Finished | Jul 31 07:52:40 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-0f09216e-f840-437b-936f-e048d3f38845 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886340438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.2886340438 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke.2420353633 |
| Short name | T2391 |
| Test name | |
| Test status | |
| Simulation time | 49723660 ps |
| CPU time | 6.75 seconds |
| Started | Jul 31 07:51:59 PM PDT 24 |
| Finished | Jul 31 07:52:06 PM PDT 24 |
| Peak memory | 573860 kb |
| Host | smart-fe29595d-2398-4d03-ac31-d833f2e99719 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420353633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.2420353633 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.1590327708 |
| Short name | T1452 |
| Test name | |
| Test status | |
| Simulation time | 7401052588 ps |
| CPU time | 79.36 seconds |
| Started | Jul 31 07:52:01 PM PDT 24 |
| Finished | Jul 31 07:53:21 PM PDT 24 |
| Peak memory | 573872 kb |
| Host | smart-0c94b7ca-1ec3-479f-927f-9ad852506465 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590327708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.1590327708 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.3243179075 |
| Short name | T2318 |
| Test name | |
| Test status | |
| Simulation time | 6749901536 ps |
| CPU time | 119.16 seconds |
| Started | Jul 31 07:52:05 PM PDT 24 |
| Finished | Jul 31 07:54:05 PM PDT 24 |
| Peak memory | 573876 kb |
| Host | smart-6cd6c85f-0a31-4404-bbc4-2be36e49b912 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243179075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.3243179075 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_zero_delays.3064971109 |
| Short name | T2491 |
| Test name | |
| Test status | |
| Simulation time | 53511488 ps |
| CPU time | 7.4 seconds |
| Started | Jul 31 07:52:00 PM PDT 24 |
| Finished | Jul 31 07:52:08 PM PDT 24 |
| Peak memory | 573808 kb |
| Host | smart-4e1580c7-37c5-45be-aa9f-19f8d0715acb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064971109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delay s.3064971109 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all.1219349016 |
| Short name | T1991 |
| Test name | |
| Test status | |
| Simulation time | 19061361412 ps |
| CPU time | 741.77 seconds |
| Started | Jul 31 07:52:11 PM PDT 24 |
| Finished | Jul 31 08:04:33 PM PDT 24 |
| Peak memory | 576044 kb |
| Host | smart-6995be47-a437-4d42-95d4-55a618389b0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219349016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.1219349016 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.3196228105 |
| Short name | T2108 |
| Test name | |
| Test status | |
| Simulation time | 11929181148 ps |
| CPU time | 447.7 seconds |
| Started | Jul 31 07:52:14 PM PDT 24 |
| Finished | Jul 31 07:59:42 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-06f3e40b-593c-4970-b224-c1444c5d956f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196228105 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.3196228105 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.3379409401 |
| Short name | T2680 |
| Test name | |
| Test status | |
| Simulation time | 995946524 ps |
| CPU time | 133.37 seconds |
| Started | Jul 31 07:52:12 PM PDT 24 |
| Finished | Jul 31 07:54:25 PM PDT 24 |
| Peak memory | 576684 kb |
| Host | smart-499bad1e-34cd-4b4b-ab43-2f7f3bf9784a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379409401 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_al l_with_reset_error.3379409401 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_unmapped_addr.996527741 |
| Short name | T2310 |
| Test name | |
| Test status | |
| Simulation time | 102591053 ps |
| CPU time | 15.39 seconds |
| Started | Jul 31 07:52:11 PM PDT 24 |
| Finished | Jul 31 07:52:26 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-b4ac6b35-9a0e-4bf3-a237-fbc7774026cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996527741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.996527741 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.chip_tl_errors.2167024228 |
| Short name | T1671 |
| Test name | |
| Test status | |
| Simulation time | 2737871380 ps |
| CPU time | 95.21 seconds |
| Started | Jul 31 07:52:12 PM PDT 24 |
| Finished | Jul 31 07:53:48 PM PDT 24 |
| Peak memory | 603724 kb |
| Host | smart-d4a25fee-e918-4de2-b0b8-b9202eb3303b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167024228 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.chip_tl_errors.2167024228 |
| Directory | /workspace/25.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device.3198777884 |
| Short name | T1447 |
| Test name | |
| Test status | |
| Simulation time | 742655839 ps |
| CPU time | 48.74 seconds |
| Started | Jul 31 07:52:19 PM PDT 24 |
| Finished | Jul 31 07:53:08 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-c324c5d8-3b0d-4cd9-8b73-183d7bc45dd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198777884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device .3198777884 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.3249127237 |
| Short name | T1777 |
| Test name | |
| Test status | |
| Simulation time | 12648113467 ps |
| CPU time | 211.93 seconds |
| Started | Jul 31 07:52:21 PM PDT 24 |
| Finished | Jul 31 07:55:53 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-7793cb8d-83d2-4140-a2dd-d34b26b8e367 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249127237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_ device_slow_rsp.3249127237 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.4037556456 |
| Short name | T2174 |
| Test name | |
| Test status | |
| Simulation time | 851575916 ps |
| CPU time | 32.56 seconds |
| Started | Jul 31 07:52:28 PM PDT 24 |
| Finished | Jul 31 07:53:01 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-b73fd4eb-a42d-4cd1-9b16-ae5bfdeb44e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037556456 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_add r.4037556456 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_random.3440421188 |
| Short name | T2549 |
| Test name | |
| Test status | |
| Simulation time | 493696712 ps |
| CPU time | 40.82 seconds |
| Started | Jul 31 07:52:27 PM PDT 24 |
| Finished | Jul 31 07:53:08 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-793d77a5-9b26-40f4-b824-214740201ce4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440421188 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.3440421188 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random.3394915441 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 2402704244 ps |
| CPU time | 86.78 seconds |
| Started | Jul 31 07:52:12 PM PDT 24 |
| Finished | Jul 31 07:53:39 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-6876534e-f0bf-43e7-a5e3-dd018fdbbb49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394915441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random.3394915441 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_large_delays.4134918681 |
| Short name | T1498 |
| Test name | |
| Test status | |
| Simulation time | 50377668222 ps |
| CPU time | 535.02 seconds |
| Started | Jul 31 07:52:22 PM PDT 24 |
| Finished | Jul 31 08:01:17 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-72a02100-aa13-4f6a-a664-a3539a966b0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134918681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.4134918681 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_slow_rsp.1092968910 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 47084617746 ps |
| CPU time | 773.32 seconds |
| Started | Jul 31 07:52:21 PM PDT 24 |
| Finished | Jul 31 08:05:14 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-4954e0f1-2772-4c2b-8180-225052bdc8c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092968910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.1092968910 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_zero_delays.1411137913 |
| Short name | T1830 |
| Test name | |
| Test status | |
| Simulation time | 43316191 ps |
| CPU time | 6.51 seconds |
| Started | Jul 31 07:52:22 PM PDT 24 |
| Finished | Jul 31 07:52:28 PM PDT 24 |
| Peak memory | 573788 kb |
| Host | smart-e58a61d8-fc9f-4f0d-93cb-d1ae3781c79d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411137913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_del ays.1411137913 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_same_source.1618591290 |
| Short name | T2927 |
| Test name | |
| Test status | |
| Simulation time | 424690879 ps |
| CPU time | 31.43 seconds |
| Started | Jul 31 07:52:22 PM PDT 24 |
| Finished | Jul 31 07:52:53 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-a7cc6df7-97bc-46fe-961f-0a5b78fdb15c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618591290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.1618591290 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke.3374541496 |
| Short name | T1882 |
| Test name | |
| Test status | |
| Simulation time | 44577414 ps |
| CPU time | 6.45 seconds |
| Started | Jul 31 07:52:13 PM PDT 24 |
| Finished | Jul 31 07:52:19 PM PDT 24 |
| Peak memory | 573820 kb |
| Host | smart-1b6afeec-c2ff-431f-b0d6-40ed5df1521e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374541496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.3374541496 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_large_delays.3445579620 |
| Short name | T1800 |
| Test name | |
| Test status | |
| Simulation time | 10019960222 ps |
| CPU time | 104.55 seconds |
| Started | Jul 31 07:52:11 PM PDT 24 |
| Finished | Jul 31 07:53:56 PM PDT 24 |
| Peak memory | 573868 kb |
| Host | smart-877b3b46-71c7-42ec-8ad2-2883f9f268f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445579620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.3445579620 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.2131372047 |
| Short name | T1994 |
| Test name | |
| Test status | |
| Simulation time | 5761940055 ps |
| CPU time | 96.71 seconds |
| Started | Jul 31 07:52:14 PM PDT 24 |
| Finished | Jul 31 07:53:51 PM PDT 24 |
| Peak memory | 573876 kb |
| Host | smart-27749f66-30ee-40c0-a5ca-a6cd61d1400d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131372047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.2131372047 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_zero_delays.916735526 |
| Short name | T2035 |
| Test name | |
| Test status | |
| Simulation time | 46589354 ps |
| CPU time | 6.61 seconds |
| Started | Jul 31 07:52:12 PM PDT 24 |
| Finished | Jul 31 07:52:19 PM PDT 24 |
| Peak memory | 574304 kb |
| Host | smart-fe1422bb-4835-4e40-8142-7816f4e2a5d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916735526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays .916735526 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all.564853408 |
| Short name | T2160 |
| Test name | |
| Test status | |
| Simulation time | 2476664101 ps |
| CPU time | 226.31 seconds |
| Started | Jul 31 07:52:27 PM PDT 24 |
| Finished | Jul 31 07:56:14 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-e579802c-db28-459a-8be1-45b44ab30b1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564853408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.564853408 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.3831803532 |
| Short name | T1758 |
| Test name | |
| Test status | |
| Simulation time | 8881396271 ps |
| CPU time | 288.61 seconds |
| Started | Jul 31 07:52:30 PM PDT 24 |
| Finished | Jul 31 07:57:19 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-6be337a8-4ed7-49ca-bf6a-7d43d42487ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831803532 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.3831803532 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.1191587181 |
| Short name | T1778 |
| Test name | |
| Test status | |
| Simulation time | 16181171224 ps |
| CPU time | 741.09 seconds |
| Started | Jul 31 07:52:29 PM PDT 24 |
| Finished | Jul 31 08:04:50 PM PDT 24 |
| Peak memory | 576784 kb |
| Host | smart-da25be23-7f0f-4700-adcb-48f597cf7943 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191587181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all _with_rand_reset.1191587181 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.1308048578 |
| Short name | T2844 |
| Test name | |
| Test status | |
| Simulation time | 34750351 ps |
| CPU time | 23.29 seconds |
| Started | Jul 31 07:52:27 PM PDT 24 |
| Finished | Jul 31 07:52:50 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-85f6feee-663d-4e33-8035-7627242174a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308048578 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_al l_with_reset_error.1308048578 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_unmapped_addr.3871206468 |
| Short name | T1574 |
| Test name | |
| Test status | |
| Simulation time | 1472169785 ps |
| CPU time | 64.63 seconds |
| Started | Jul 31 07:52:26 PM PDT 24 |
| Finished | Jul 31 07:53:31 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-f04e9684-a8e9-454e-a936-cf828e58132b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871206468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.3871206468 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device.1966634711 |
| Short name | T1568 |
| Test name | |
| Test status | |
| Simulation time | 431483892 ps |
| CPU time | 16.4 seconds |
| Started | Jul 31 07:52:41 PM PDT 24 |
| Finished | Jul 31 07:52:58 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-3bd3563c-fe4b-4d01-ac94-6390e04cb6e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966634711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device .1966634711 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.3197011286 |
| Short name | T1960 |
| Test name | |
| Test status | |
| Simulation time | 14018026389 ps |
| CPU time | 242.82 seconds |
| Started | Jul 31 07:52:42 PM PDT 24 |
| Finished | Jul 31 07:56:45 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-8ad08b27-6978-4155-87ba-6dfedee4c2f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197011286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_ device_slow_rsp.3197011286 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.2630306152 |
| Short name | T2505 |
| Test name | |
| Test status | |
| Simulation time | 327203341 ps |
| CPU time | 15.9 seconds |
| Started | Jul 31 07:52:41 PM PDT 24 |
| Finished | Jul 31 07:52:57 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-0eaac42f-e612-4075-aded-af5380bb0092 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630306152 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_add r.2630306152 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_random.4103710180 |
| Short name | T2100 |
| Test name | |
| Test status | |
| Simulation time | 146142087 ps |
| CPU time | 15.02 seconds |
| Started | Jul 31 07:52:41 PM PDT 24 |
| Finished | Jul 31 07:52:56 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-c39b44a2-fd79-4c34-b607-c70ff3cc4057 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103710180 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.4103710180 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random.261225628 |
| Short name | T1527 |
| Test name | |
| Test status | |
| Simulation time | 113828813 ps |
| CPU time | 7.35 seconds |
| Started | Jul 31 07:52:35 PM PDT 24 |
| Finished | Jul 31 07:52:43 PM PDT 24 |
| Peak memory | 573796 kb |
| Host | smart-4c77db56-ee30-47f3-a090-d0cb8e87d112 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261225628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random.261225628 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_large_delays.4027865330 |
| Short name | T2865 |
| Test name | |
| Test status | |
| Simulation time | 77207570802 ps |
| CPU time | 839.02 seconds |
| Started | Jul 31 07:52:35 PM PDT 24 |
| Finished | Jul 31 08:06:34 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-695db653-39a5-4906-8ba7-39870d30c4af |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027865330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.4027865330 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_slow_rsp.1014815055 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 59248795338 ps |
| CPU time | 1000.93 seconds |
| Started | Jul 31 07:52:42 PM PDT 24 |
| Finished | Jul 31 08:09:24 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-cf01f327-62f7-41ec-bed3-9e3f345aac81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014815055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.1014815055 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.3616081585 |
| Short name | T1506 |
| Test name | |
| Test status | |
| Simulation time | 196405872 ps |
| CPU time | 18.43 seconds |
| Started | Jul 31 07:52:37 PM PDT 24 |
| Finished | Jul 31 07:52:55 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-78258236-d6fb-48c8-b099-5223563e41ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616081585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_del ays.3616081585 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_same_source.711008902 |
| Short name | T2610 |
| Test name | |
| Test status | |
| Simulation time | 2685612209 ps |
| CPU time | 82.59 seconds |
| Started | Jul 31 07:52:41 PM PDT 24 |
| Finished | Jul 31 07:54:03 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-73af9c9d-f69e-4a2a-827f-22945c296a4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711008902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.711008902 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke.2754236404 |
| Short name | T2686 |
| Test name | |
| Test status | |
| Simulation time | 174983573 ps |
| CPU time | 8.89 seconds |
| Started | Jul 31 07:52:36 PM PDT 24 |
| Finished | Jul 31 07:52:45 PM PDT 24 |
| Peak memory | 573860 kb |
| Host | smart-b24dc927-8d23-4d68-8e96-c759dd226187 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754236404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.2754236404 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_large_delays.1755521002 |
| Short name | T1391 |
| Test name | |
| Test status | |
| Simulation time | 6945712450 ps |
| CPU time | 78.67 seconds |
| Started | Jul 31 07:52:35 PM PDT 24 |
| Finished | Jul 31 07:53:54 PM PDT 24 |
| Peak memory | 573904 kb |
| Host | smart-cd345f6e-019a-4efa-90a4-90dadf980e68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755521002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.1755521002 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.1062155700 |
| Short name | T2357 |
| Test name | |
| Test status | |
| Simulation time | 5535429898 ps |
| CPU time | 90.01 seconds |
| Started | Jul 31 07:52:34 PM PDT 24 |
| Finished | Jul 31 07:54:04 PM PDT 24 |
| Peak memory | 573916 kb |
| Host | smart-35ac8053-7066-416a-a71e-b9d9da06cff4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062155700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.1062155700 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.2079488979 |
| Short name | T2164 |
| Test name | |
| Test status | |
| Simulation time | 48232779 ps |
| CPU time | 6.47 seconds |
| Started | Jul 31 07:52:36 PM PDT 24 |
| Finished | Jul 31 07:52:42 PM PDT 24 |
| Peak memory | 573828 kb |
| Host | smart-78291e3e-271d-404b-9e07-89564935eb44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079488979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delay s.2079488979 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all.3127077726 |
| Short name | T2524 |
| Test name | |
| Test status | |
| Simulation time | 3070984756 ps |
| CPU time | 233.99 seconds |
| Started | Jul 31 07:52:41 PM PDT 24 |
| Finished | Jul 31 07:56:35 PM PDT 24 |
| Peak memory | 576052 kb |
| Host | smart-ced10ba3-fe0a-472d-a709-da978654c903 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127077726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.3127077726 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.3755896246 |
| Short name | T1430 |
| Test name | |
| Test status | |
| Simulation time | 319241848 ps |
| CPU time | 35.05 seconds |
| Started | Jul 31 07:52:44 PM PDT 24 |
| Finished | Jul 31 07:53:19 PM PDT 24 |
| Peak memory | 576124 kb |
| Host | smart-3ad1d49f-82e0-4e86-b506-ebbef2a38cab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755896246 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.3755896246 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.633016723 |
| Short name | T2247 |
| Test name | |
| Test status | |
| Simulation time | 562146518 ps |
| CPU time | 205.83 seconds |
| Started | Jul 31 07:52:43 PM PDT 24 |
| Finished | Jul 31 07:56:08 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-099c88a5-d78f-4427-854c-51376dd083bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633016723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_ with_rand_reset.633016723 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.1850466712 |
| Short name | T1579 |
| Test name | |
| Test status | |
| Simulation time | 6119034192 ps |
| CPU time | 604.19 seconds |
| Started | Jul 31 07:52:42 PM PDT 24 |
| Finished | Jul 31 08:02:47 PM PDT 24 |
| Peak memory | 576736 kb |
| Host | smart-c8ca3382-93b7-4e75-afb7-6b03618f29d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850466712 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_al l_with_reset_error.1850466712 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_unmapped_addr.3702338487 |
| Short name | T2605 |
| Test name | |
| Test status | |
| Simulation time | 1491475995 ps |
| CPU time | 62.61 seconds |
| Started | Jul 31 07:52:43 PM PDT 24 |
| Finished | Jul 31 07:53:46 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-5cbdaad5-b4f2-44d5-94d2-c6ac6783e4ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702338487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.3702338487 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.chip_tl_errors.2170641189 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 4183959082 ps |
| CPU time | 308.71 seconds |
| Started | Jul 31 07:52:48 PM PDT 24 |
| Finished | Jul 31 07:57:57 PM PDT 24 |
| Peak memory | 598688 kb |
| Host | smart-f375d931-7471-4c26-acc1-9b2351d6054f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170641189 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.chip_tl_errors.2170641189 |
| Directory | /workspace/27.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device.2754503208 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 3285329393 ps |
| CPU time | 140.6 seconds |
| Started | Jul 31 07:52:54 PM PDT 24 |
| Finished | Jul 31 07:55:15 PM PDT 24 |
| Peak memory | 576084 kb |
| Host | smart-e5ab55b9-a5d1-49a1-ad73-870719d1a061 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754503208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device .2754503208 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.143880561 |
| Short name | T1489 |
| Test name | |
| Test status | |
| Simulation time | 32699874151 ps |
| CPU time | 530.74 seconds |
| Started | Jul 31 07:52:56 PM PDT 24 |
| Finished | Jul 31 08:01:47 PM PDT 24 |
| Peak memory | 576092 kb |
| Host | smart-9a9d98d5-b05e-4e0f-b518-a96a6996e492 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143880561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_d evice_slow_rsp.143880561 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.233095763 |
| Short name | T1902 |
| Test name | |
| Test status | |
| Simulation time | 330770581 ps |
| CPU time | 33.45 seconds |
| Started | Jul 31 07:52:58 PM PDT 24 |
| Finished | Jul 31 07:53:32 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-b8872842-f85d-4cf4-9cbe-e6ef74aa58c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233095763 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr .233095763 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_random.2799384191 |
| Short name | T1528 |
| Test name | |
| Test status | |
| Simulation time | 153616050 ps |
| CPU time | 13.37 seconds |
| Started | Jul 31 07:53:06 PM PDT 24 |
| Finished | Jul 31 07:53:20 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-53a07995-5d77-4273-b29f-e8bb256ce556 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799384191 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.2799384191 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random.2307609792 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 425030113 ps |
| CPU time | 40.45 seconds |
| Started | Jul 31 07:52:54 PM PDT 24 |
| Finished | Jul 31 07:53:34 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-513a6781-bcf4-4dfa-acb6-52606a36d23f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307609792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random.2307609792 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_large_delays.3269452390 |
| Short name | T1548 |
| Test name | |
| Test status | |
| Simulation time | 77676039258 ps |
| CPU time | 791.95 seconds |
| Started | Jul 31 07:52:54 PM PDT 24 |
| Finished | Jul 31 08:06:06 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-d10e27a6-747a-41e5-b5a6-e95d9c7d3568 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269452390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.3269452390 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.1206185313 |
| Short name | T1962 |
| Test name | |
| Test status | |
| Simulation time | 29771769340 ps |
| CPU time | 496.04 seconds |
| Started | Jul 31 07:53:06 PM PDT 24 |
| Finished | Jul 31 08:01:23 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-fa72f30a-5f5e-4cf6-aae4-c12be4797d5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206185313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.1206185313 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_zero_delays.3941136387 |
| Short name | T1909 |
| Test name | |
| Test status | |
| Simulation time | 32361322 ps |
| CPU time | 5.85 seconds |
| Started | Jul 31 07:52:56 PM PDT 24 |
| Finished | Jul 31 07:53:02 PM PDT 24 |
| Peak memory | 573736 kb |
| Host | smart-a140a4f1-e99a-4fc9-bc89-c456f92cb6e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941136387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_del ays.3941136387 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_same_source.819687050 |
| Short name | T2266 |
| Test name | |
| Test status | |
| Simulation time | 1878308079 ps |
| CPU time | 57.77 seconds |
| Started | Jul 31 07:53:06 PM PDT 24 |
| Finished | Jul 31 07:54:04 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-4119db09-6332-4284-999a-55dd425d6021 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819687050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.819687050 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke.1490508006 |
| Short name | T1688 |
| Test name | |
| Test status | |
| Simulation time | 242046883 ps |
| CPU time | 9.51 seconds |
| Started | Jul 31 07:52:47 PM PDT 24 |
| Finished | Jul 31 07:52:56 PM PDT 24 |
| Peak memory | 573764 kb |
| Host | smart-27518abb-16de-47a0-b9a5-ca88e9d8d405 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490508006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.1490508006 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.2303096799 |
| Short name | T2756 |
| Test name | |
| Test status | |
| Simulation time | 8207018936 ps |
| CPU time | 82.25 seconds |
| Started | Jul 31 07:53:06 PM PDT 24 |
| Finished | Jul 31 07:54:29 PM PDT 24 |
| Peak memory | 573936 kb |
| Host | smart-b9351658-6d9e-44a7-b13e-ea8460abe34a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303096799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.2303096799 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.2082534358 |
| Short name | T1752 |
| Test name | |
| Test status | |
| Simulation time | 5112938619 ps |
| CPU time | 83.75 seconds |
| Started | Jul 31 07:52:55 PM PDT 24 |
| Finished | Jul 31 07:54:18 PM PDT 24 |
| Peak memory | 573904 kb |
| Host | smart-ef8d30e2-5b77-4e11-8dfb-33026dd5264f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082534358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.2082534358 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.1651486891 |
| Short name | T1428 |
| Test name | |
| Test status | |
| Simulation time | 49045209 ps |
| CPU time | 6.37 seconds |
| Started | Jul 31 07:52:54 PM PDT 24 |
| Finished | Jul 31 07:53:00 PM PDT 24 |
| Peak memory | 573788 kb |
| Host | smart-f8c71132-d1f4-4b31-a6df-63743eb8e9b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651486891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delay s.1651486891 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all.3098088790 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 9571546268 ps |
| CPU time | 344.32 seconds |
| Started | Jul 31 07:52:59 PM PDT 24 |
| Finished | Jul 31 07:58:44 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-339b04de-bd9c-4835-a371-3e53d7f05dab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098088790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.3098088790 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.3623619863 |
| Short name | T2566 |
| Test name | |
| Test status | |
| Simulation time | 1990894876 ps |
| CPU time | 154 seconds |
| Started | Jul 31 07:52:59 PM PDT 24 |
| Finished | Jul 31 07:55:33 PM PDT 24 |
| Peak memory | 576072 kb |
| Host | smart-f08dbb10-dacf-48f6-9654-80498b1eb27f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623619863 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.3623619863 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.1974731892 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 4176287534 ps |
| CPU time | 361.17 seconds |
| Started | Jul 31 07:53:00 PM PDT 24 |
| Finished | Jul 31 07:59:01 PM PDT 24 |
| Peak memory | 576716 kb |
| Host | smart-84290d34-7009-4e51-8d4d-2193b202e681 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974731892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all _with_rand_reset.1974731892 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.3330593069 |
| Short name | T2101 |
| Test name | |
| Test status | |
| Simulation time | 767149161 ps |
| CPU time | 218.67 seconds |
| Started | Jul 31 07:53:09 PM PDT 24 |
| Finished | Jul 31 07:56:48 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-3db3d381-65a6-43ab-a32c-ab1677242c38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330593069 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_al l_with_reset_error.3330593069 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_unmapped_addr.1658340826 |
| Short name | T2600 |
| Test name | |
| Test status | |
| Simulation time | 225071161 ps |
| CPU time | 26.3 seconds |
| Started | Jul 31 07:52:55 PM PDT 24 |
| Finished | Jul 31 07:53:21 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-c4beb824-0a1c-4de9-8bd3-3d119e2cb175 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658340826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.1658340826 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.chip_tl_errors.989754293 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 3011310413 ps |
| CPU time | 180.09 seconds |
| Started | Jul 31 07:53:01 PM PDT 24 |
| Finished | Jul 31 07:56:01 PM PDT 24 |
| Peak memory | 602980 kb |
| Host | smart-c99f1f63-c9c1-4a16-8053-de266dec0e8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989754293 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.chip_tl_errors.989754293 |
| Directory | /workspace/28.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device.1608405039 |
| Short name | T2894 |
| Test name | |
| Test status | |
| Simulation time | 1688728828 ps |
| CPU time | 71.16 seconds |
| Started | Jul 31 07:53:07 PM PDT 24 |
| Finished | Jul 31 07:54:18 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-09f2a3d2-9477-4fc7-a940-c5235f048842 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608405039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device .1608405039 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.338499999 |
| Short name | T2611 |
| Test name | |
| Test status | |
| Simulation time | 118032029865 ps |
| CPU time | 2220.16 seconds |
| Started | Jul 31 07:53:09 PM PDT 24 |
| Finished | Jul 31 08:30:10 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-73e0a1a9-8316-4329-986f-d9c8538d357c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338499999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_d evice_slow_rsp.338499999 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.1126060020 |
| Short name | T1550 |
| Test name | |
| Test status | |
| Simulation time | 106491903 ps |
| CPU time | 7.91 seconds |
| Started | Jul 31 07:53:05 PM PDT 24 |
| Finished | Jul 31 07:53:13 PM PDT 24 |
| Peak memory | 573896 kb |
| Host | smart-63cc586e-bfb3-43e8-b858-f82959f27b48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126060020 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_add r.1126060020 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_random.976778130 |
| Short name | T1756 |
| Test name | |
| Test status | |
| Simulation time | 1671258505 ps |
| CPU time | 64.68 seconds |
| Started | Jul 31 07:53:07 PM PDT 24 |
| Finished | Jul 31 07:54:12 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-f3ad5210-cf3c-4b78-8bac-c256dc6591f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976778130 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.976778130 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random.3445913096 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 1096061037 ps |
| CPU time | 35.44 seconds |
| Started | Jul 31 07:53:06 PM PDT 24 |
| Finished | Jul 31 07:53:41 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-d6301b14-5ab5-42f8-a791-f563b9a3be2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445913096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random.3445913096 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_large_delays.2261322791 |
| Short name | T2255 |
| Test name | |
| Test status | |
| Simulation time | 75713133246 ps |
| CPU time | 760.71 seconds |
| Started | Jul 31 07:53:07 PM PDT 24 |
| Finished | Jul 31 08:05:47 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-9c582a34-2adb-476f-896c-1410b1213808 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261322791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.2261322791 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_slow_rsp.4228988617 |
| Short name | T2631 |
| Test name | |
| Test status | |
| Simulation time | 57217968483 ps |
| CPU time | 1020.55 seconds |
| Started | Jul 31 07:53:07 PM PDT 24 |
| Finished | Jul 31 08:10:08 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-80901f21-d1e2-4963-995a-552eda6c9067 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228988617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.4228988617 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_zero_delays.75792156 |
| Short name | T2275 |
| Test name | |
| Test status | |
| Simulation time | 232899295 ps |
| CPU time | 20.79 seconds |
| Started | Jul 31 07:53:06 PM PDT 24 |
| Finished | Jul 31 07:53:27 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-9b3a5f4d-a2ad-4ad9-92ae-2bb2976ef0bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75792156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delay s.75792156 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_same_source.3703309247 |
| Short name | T1954 |
| Test name | |
| Test status | |
| Simulation time | 2440200796 ps |
| CPU time | 77.35 seconds |
| Started | Jul 31 07:53:07 PM PDT 24 |
| Finished | Jul 31 07:54:24 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-c58fb76c-635b-4378-bc88-e3699159e371 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703309247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.3703309247 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke.1711052996 |
| Short name | T1925 |
| Test name | |
| Test status | |
| Simulation time | 235675181 ps |
| CPU time | 9.53 seconds |
| Started | Jul 31 07:53:05 PM PDT 24 |
| Finished | Jul 31 07:53:15 PM PDT 24 |
| Peak memory | 573796 kb |
| Host | smart-17d5a2ca-30a6-4c28-9198-c08491f4862b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711052996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.1711052996 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_large_delays.2583815688 |
| Short name | T2012 |
| Test name | |
| Test status | |
| Simulation time | 5806323654 ps |
| CPU time | 58.6 seconds |
| Started | Jul 31 07:53:01 PM PDT 24 |
| Finished | Jul 31 07:54:00 PM PDT 24 |
| Peak memory | 573816 kb |
| Host | smart-21f0bb60-d8a6-4d24-b738-757ab6a54104 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583815688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.2583815688 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.4200439560 |
| Short name | T2848 |
| Test name | |
| Test status | |
| Simulation time | 4957871379 ps |
| CPU time | 85.33 seconds |
| Started | Jul 31 07:53:00 PM PDT 24 |
| Finished | Jul 31 07:54:25 PM PDT 24 |
| Peak memory | 574552 kb |
| Host | smart-a7110dc6-c7b4-4704-a7c3-cb8a11a09847 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200439560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.4200439560 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.1875767280 |
| Short name | T2481 |
| Test name | |
| Test status | |
| Simulation time | 53380753 ps |
| CPU time | 6.04 seconds |
| Started | Jul 31 07:53:06 PM PDT 24 |
| Finished | Jul 31 07:53:12 PM PDT 24 |
| Peak memory | 573748 kb |
| Host | smart-597535ac-f68d-48f0-ad82-b46e2d1a1d08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875767280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delay s.1875767280 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.1664497129 |
| Short name | T2518 |
| Test name | |
| Test status | |
| Simulation time | 560614228 ps |
| CPU time | 39.93 seconds |
| Started | Jul 31 07:53:12 PM PDT 24 |
| Finished | Jul 31 07:53:52 PM PDT 24 |
| Peak memory | 576032 kb |
| Host | smart-28cb88ca-9c42-45be-9512-67abc8c59730 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664497129 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.1664497129 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.3615627035 |
| Short name | T1694 |
| Test name | |
| Test status | |
| Simulation time | 222559869 ps |
| CPU time | 116.7 seconds |
| Started | Jul 31 07:53:13 PM PDT 24 |
| Finished | Jul 31 07:55:10 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-2b7c9961-c2b0-4ec2-86a0-7a91c7ed0566 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615627035 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_al l_with_reset_error.3615627035 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_unmapped_addr.1329765892 |
| Short name | T2484 |
| Test name | |
| Test status | |
| Simulation time | 38732483 ps |
| CPU time | 7.39 seconds |
| Started | Jul 31 07:53:07 PM PDT 24 |
| Finished | Jul 31 07:53:14 PM PDT 24 |
| Peak memory | 573956 kb |
| Host | smart-40423bc3-879d-45d2-b758-0db8771280d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329765892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.1329765892 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.chip_tl_errors.1541401180 |
| Short name | T2687 |
| Test name | |
| Test status | |
| Simulation time | 2991206667 ps |
| CPU time | 185.03 seconds |
| Started | Jul 31 07:53:14 PM PDT 24 |
| Finished | Jul 31 07:56:19 PM PDT 24 |
| Peak memory | 599916 kb |
| Host | smart-b0dbd86a-32cd-46ac-90a8-99f5673c6648 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541401180 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.chip_tl_errors.1541401180 |
| Directory | /workspace/29.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device.1666766391 |
| Short name | T2209 |
| Test name | |
| Test status | |
| Simulation time | 745944357 ps |
| CPU time | 63.77 seconds |
| Started | Jul 31 07:53:18 PM PDT 24 |
| Finished | Jul 31 07:54:22 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-756405eb-e01c-4ca4-8dea-42c34e7f8795 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666766391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device .1666766391 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.1686119101 |
| Short name | T2238 |
| Test name | |
| Test status | |
| Simulation time | 118206793553 ps |
| CPU time | 2149.46 seconds |
| Started | Jul 31 07:53:25 PM PDT 24 |
| Finished | Jul 31 08:29:15 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-48bbca68-478b-43a4-876a-4b61a4fdcf76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686119101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_ device_slow_rsp.1686119101 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.70014556 |
| Short name | T2051 |
| Test name | |
| Test status | |
| Simulation time | 92458617 ps |
| CPU time | 6.75 seconds |
| Started | Jul 31 07:53:23 PM PDT 24 |
| Finished | Jul 31 07:53:30 PM PDT 24 |
| Peak memory | 573888 kb |
| Host | smart-1d2b5d02-c2c7-4dd3-a9a3-623d0dbd4cac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70014556 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.70014556 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_random.2738182047 |
| Short name | T2564 |
| Test name | |
| Test status | |
| Simulation time | 2160131391 ps |
| CPU time | 69.03 seconds |
| Started | Jul 31 07:53:26 PM PDT 24 |
| Finished | Jul 31 07:54:36 PM PDT 24 |
| Peak memory | 576072 kb |
| Host | smart-4197519c-c3fa-4c8b-81ec-bfa90385f723 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738182047 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.2738182047 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random.1098390674 |
| Short name | T1590 |
| Test name | |
| Test status | |
| Simulation time | 1888790178 ps |
| CPU time | 69.08 seconds |
| Started | Jul 31 07:53:19 PM PDT 24 |
| Finished | Jul 31 07:54:28 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-6a7c9701-b152-4510-a09c-a6c8a315db84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098390674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random.1098390674 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_large_delays.607050205 |
| Short name | T2717 |
| Test name | |
| Test status | |
| Simulation time | 98101240161 ps |
| CPU time | 1119.29 seconds |
| Started | Jul 31 07:53:18 PM PDT 24 |
| Finished | Jul 31 08:11:58 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-2bcb6a9a-7b05-47c9-8586-b9f46ce7ff65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607050205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.607050205 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.4252362836 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 27938908723 ps |
| CPU time | 491.68 seconds |
| Started | Jul 31 07:53:18 PM PDT 24 |
| Finished | Jul 31 08:01:30 PM PDT 24 |
| Peak memory | 576024 kb |
| Host | smart-5459005a-9f58-4f31-b7c9-6948455aa84a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252362836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.4252362836 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_zero_delays.1818785592 |
| Short name | T1825 |
| Test name | |
| Test status | |
| Simulation time | 133325663 ps |
| CPU time | 13.47 seconds |
| Started | Jul 31 07:53:19 PM PDT 24 |
| Finished | Jul 31 07:53:32 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-71bfae89-29a6-4794-8ccd-877752da02ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818785592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_del ays.1818785592 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_same_source.1447650665 |
| Short name | T1464 |
| Test name | |
| Test status | |
| Simulation time | 400811325 ps |
| CPU time | 14.81 seconds |
| Started | Jul 31 07:53:24 PM PDT 24 |
| Finished | Jul 31 07:53:39 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-24fb195e-1e9c-44f6-a766-bca22ba139bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447650665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.1447650665 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke.793678644 |
| Short name | T1424 |
| Test name | |
| Test status | |
| Simulation time | 56262923 ps |
| CPU time | 7.11 seconds |
| Started | Jul 31 07:53:14 PM PDT 24 |
| Finished | Jul 31 07:53:21 PM PDT 24 |
| Peak memory | 573788 kb |
| Host | smart-fd752b30-7089-49d5-83b9-4af627d7f3e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793678644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.793678644 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_large_delays.254313267 |
| Short name | T2326 |
| Test name | |
| Test status | |
| Simulation time | 9807378534 ps |
| CPU time | 100.62 seconds |
| Started | Jul 31 07:53:14 PM PDT 24 |
| Finished | Jul 31 07:54:55 PM PDT 24 |
| Peak memory | 573844 kb |
| Host | smart-030f23f7-8a24-44dc-ad46-c3a44afeb270 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254313267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.254313267 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.503302864 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 4635271527 ps |
| CPU time | 76.78 seconds |
| Started | Jul 31 07:53:12 PM PDT 24 |
| Finished | Jul 31 07:54:29 PM PDT 24 |
| Peak memory | 574568 kb |
| Host | smart-53ab3561-98ef-4419-b34c-e6e4930ccd46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503302864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.503302864 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_zero_delays.1333854414 |
| Short name | T2465 |
| Test name | |
| Test status | |
| Simulation time | 52394251 ps |
| CPU time | 6.26 seconds |
| Started | Jul 31 07:53:18 PM PDT 24 |
| Finished | Jul 31 07:53:24 PM PDT 24 |
| Peak memory | 573820 kb |
| Host | smart-20cb58a9-5944-486d-b633-98fc8e4d7f3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333854414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delay s.1333854414 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all.2287073895 |
| Short name | T2658 |
| Test name | |
| Test status | |
| Simulation time | 5768401813 ps |
| CPU time | 182.1 seconds |
| Started | Jul 31 07:53:24 PM PDT 24 |
| Finished | Jul 31 07:56:27 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-f0546151-e0f5-43a5-a86c-9cdbe5cd045b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287073895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.2287073895 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.666331052 |
| Short name | T1525 |
| Test name | |
| Test status | |
| Simulation time | 2171224240 ps |
| CPU time | 172.23 seconds |
| Started | Jul 31 07:53:29 PM PDT 24 |
| Finished | Jul 31 07:56:22 PM PDT 24 |
| Peak memory | 576256 kb |
| Host | smart-820e9eaa-a783-44b4-8fa8-13f2aba7ef9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666331052 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.666331052 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.2025926088 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 16213823504 ps |
| CPU time | 728.84 seconds |
| Started | Jul 31 07:53:24 PM PDT 24 |
| Finished | Jul 31 08:05:33 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-69991d5a-d133-4bf7-b202-90a0b27eb2ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025926088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all _with_rand_reset.2025926088 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_unmapped_addr.3278958437 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 954330174 ps |
| CPU time | 44.21 seconds |
| Started | Jul 31 07:53:28 PM PDT 24 |
| Finished | Jul 31 07:54:12 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-8eac59ff-c8e9-4c7f-9c08-f421584f2dbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278958437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.3278958437 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_aliasing.1735118871 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 57364241215 ps |
| CPU time | 8494.11 seconds |
| Started | Jul 31 07:45:47 PM PDT 24 |
| Finished | Jul 31 10:07:23 PM PDT 24 |
| Peak memory | 645876 kb |
| Host | smart-48bebdda-65de-4dce-b73d-50158f7ec869 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735118871 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.chip_csr_aliasing.1735118871 |
| Directory | /workspace/3.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_bit_bash.567150717 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 67718766392 ps |
| CPU time | 6897.82 seconds |
| Started | Jul 31 07:45:49 PM PDT 24 |
| Finished | Jul 31 09:40:48 PM PDT 24 |
| Peak memory | 593624 kb |
| Host | smart-ae68faea-3216-4e88-8385-d60fbb2988b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567150717 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 3.chip_csr_bit_bash.567150717 |
| Directory | /workspace/3.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.3138239473 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 4724764252 ps |
| CPU time | 224.96 seconds |
| Started | Jul 31 07:46:16 PM PDT 24 |
| Finished | Jul 31 07:50:01 PM PDT 24 |
| Peak memory | 663380 kb |
| Host | smart-5f60d4ec-6227-4a26-b287-e899632d1afb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138239473 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_hw_r eset.3138239473 |
| Directory | /workspace/3.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.3898078841 |
| Short name | T2482 |
| Test name | |
| Test status | |
| Simulation time | 6166808411 ps |
| CPU time | 417.98 seconds |
| Started | Jul 31 07:46:12 PM PDT 24 |
| Finished | Jul 31 07:53:10 PM PDT 24 |
| Peak memory | 645840 kb |
| Host | smart-357bc550-a8fa-48ca-9341-5f9d11e19012 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898078841 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 3.chip_csr_mem_rw_with_rand_reset.3898078841 |
| Directory | /workspace/3.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_rw.1534784097 |
| Short name | T2072 |
| Test name | |
| Test status | |
| Simulation time | 3873594646 ps |
| CPU time | 295.19 seconds |
| Started | Jul 31 07:46:14 PM PDT 24 |
| Finished | Jul 31 07:51:09 PM PDT 24 |
| Peak memory | 598844 kb |
| Host | smart-be217707-9cca-4fe2-88d0-cfe2a9ce8ec5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534784097 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_rw.1534784097 |
| Directory | /workspace/3.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device.2328509405 |
| Short name | T2677 |
| Test name | |
| Test status | |
| Simulation time | 2091789035 ps |
| CPU time | 87.06 seconds |
| Started | Jul 31 07:46:02 PM PDT 24 |
| Finished | Jul 31 07:47:29 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-839c2eb9-99a9-43ab-8b72-0131522557d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328509405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device. 2328509405 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.846904206 |
| Short name | T2765 |
| Test name | |
| Test status | |
| Simulation time | 5094540758 ps |
| CPU time | 94.49 seconds |
| Started | Jul 31 07:46:02 PM PDT 24 |
| Finished | Jul 31 07:47:36 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-05eaf59a-ef43-44be-ae88-9a3817027ffb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846904206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_de vice_slow_rsp.846904206 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.1870267533 |
| Short name | T2232 |
| Test name | |
| Test status | |
| Simulation time | 102427372 ps |
| CPU time | 7.25 seconds |
| Started | Jul 31 07:46:07 PM PDT 24 |
| Finished | Jul 31 07:46:14 PM PDT 24 |
| Peak memory | 573728 kb |
| Host | smart-5ccfe035-4ca0-47b8-a8ad-1b96f602f6fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870267533 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr .1870267533 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_random.4076208128 |
| Short name | T1449 |
| Test name | |
| Test status | |
| Simulation time | 1233559114 ps |
| CPU time | 39.11 seconds |
| Started | Jul 31 07:46:08 PM PDT 24 |
| Finished | Jul 31 07:46:47 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-95d1a13a-0eac-46ff-b4e5-a21f58a3402b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076208128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.4076208128 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random.3707804803 |
| Short name | T1865 |
| Test name | |
| Test status | |
| Simulation time | 121458449 ps |
| CPU time | 13.57 seconds |
| Started | Jul 31 07:45:57 PM PDT 24 |
| Finished | Jul 31 07:46:11 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-36e2c6e3-b39c-4a00-bdd8-9645233eb7d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707804803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random.3707804803 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_large_delays.1410744223 |
| Short name | T2239 |
| Test name | |
| Test status | |
| Simulation time | 79285209216 ps |
| CPU time | 778.44 seconds |
| Started | Jul 31 07:46:00 PM PDT 24 |
| Finished | Jul 31 07:58:58 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-8e19fd6c-7b08-4acf-a0f1-9aa51c489850 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410744223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.1410744223 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.3635981074 |
| Short name | T1957 |
| Test name | |
| Test status | |
| Simulation time | 40704107298 ps |
| CPU time | 665.66 seconds |
| Started | Jul 31 07:46:00 PM PDT 24 |
| Finished | Jul 31 07:57:05 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-c5398119-84b8-4d36-ab24-3dcf1e08dd27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635981074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.3635981074 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_zero_delays.3520959260 |
| Short name | T2926 |
| Test name | |
| Test status | |
| Simulation time | 450279103 ps |
| CPU time | 37.65 seconds |
| Started | Jul 31 07:46:02 PM PDT 24 |
| Finished | Jul 31 07:46:39 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-bbb12ca1-02a4-4d8d-8eef-85aedc913c2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520959260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_dela ys.3520959260 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_same_source.3692476361 |
| Short name | T2050 |
| Test name | |
| Test status | |
| Simulation time | 1098288280 ps |
| CPU time | 29.54 seconds |
| Started | Jul 31 07:46:05 PM PDT 24 |
| Finished | Jul 31 07:46:34 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-870a604a-e79e-43bc-a4b7-542c02b34677 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692476361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.3692476361 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke.347614357 |
| Short name | T2935 |
| Test name | |
| Test status | |
| Simulation time | 41317077 ps |
| CPU time | 5.68 seconds |
| Started | Jul 31 07:45:53 PM PDT 24 |
| Finished | Jul 31 07:45:59 PM PDT 24 |
| Peak memory | 573772 kb |
| Host | smart-b6685216-99db-4daa-810a-c53adb097027 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347614357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.347614357 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_large_delays.884271455 |
| Short name | T2593 |
| Test name | |
| Test status | |
| Simulation time | 7383724420 ps |
| CPU time | 74.89 seconds |
| Started | Jul 31 07:45:57 PM PDT 24 |
| Finished | Jul 31 07:47:12 PM PDT 24 |
| Peak memory | 573812 kb |
| Host | smart-5b012c87-3d2c-4ce8-86bf-0de98b5f7ccb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884271455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.884271455 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.2527846787 |
| Short name | T1484 |
| Test name | |
| Test status | |
| Simulation time | 5544463487 ps |
| CPU time | 88.28 seconds |
| Started | Jul 31 07:45:55 PM PDT 24 |
| Finished | Jul 31 07:47:24 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-dce64c17-f024-4f08-ae62-e534e01b6cb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527846787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.2527846787 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.3361222716 |
| Short name | T2359 |
| Test name | |
| Test status | |
| Simulation time | 44068804 ps |
| CPU time | 6.2 seconds |
| Started | Jul 31 07:45:53 PM PDT 24 |
| Finished | Jul 31 07:45:59 PM PDT 24 |
| Peak memory | 573788 kb |
| Host | smart-ca55c28c-0fad-47cb-a40b-ea677cfd3ca4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361222716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays .3361222716 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all.1138242632 |
| Short name | T2362 |
| Test name | |
| Test status | |
| Simulation time | 775022785 ps |
| CPU time | 55.46 seconds |
| Started | Jul 31 07:46:05 PM PDT 24 |
| Finished | Jul 31 07:47:01 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-478afe30-ba6c-45b8-942d-64f8b7e4f44d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138242632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.1138242632 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.1597367351 |
| Short name | T1643 |
| Test name | |
| Test status | |
| Simulation time | 496380580 ps |
| CPU time | 45.33 seconds |
| Started | Jul 31 07:46:10 PM PDT 24 |
| Finished | Jul 31 07:46:55 PM PDT 24 |
| Peak memory | 576056 kb |
| Host | smart-5dbdfc83-74e0-4807-a11e-cd846f6b5602 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597367351 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.1597367351 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.404138230 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 610618790 ps |
| CPU time | 262.36 seconds |
| Started | Jul 31 07:46:08 PM PDT 24 |
| Finished | Jul 31 07:50:30 PM PDT 24 |
| Peak memory | 576692 kb |
| Host | smart-97b18025-9616-4987-9503-3f7743f5db53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404138230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_w ith_rand_reset.404138230 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_unmapped_addr.2776211632 |
| Short name | T1729 |
| Test name | |
| Test status | |
| Simulation time | 940669096 ps |
| CPU time | 37.42 seconds |
| Started | Jul 31 07:46:06 PM PDT 24 |
| Finished | Jul 31 07:46:44 PM PDT 24 |
| Peak memory | 576048 kb |
| Host | smart-9520a721-bef2-4233-b33c-2b33524abb8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776211632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.2776211632 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device.769278198 |
| Short name | T2676 |
| Test name | |
| Test status | |
| Simulation time | 743532175 ps |
| CPU time | 36.41 seconds |
| Started | Jul 31 07:53:29 PM PDT 24 |
| Finished | Jul 31 07:54:06 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-6be7b57f-4da4-4355-984f-fa3945808d8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769278198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device. 769278198 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.536452535 |
| Short name | T2068 |
| Test name | |
| Test status | |
| Simulation time | 642509594 ps |
| CPU time | 28.43 seconds |
| Started | Jul 31 07:53:33 PM PDT 24 |
| Finished | Jul 31 07:54:02 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-4b56ad1c-e566-473a-ba7e-5752f3d91b03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536452535 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr .536452535 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_random.1906669017 |
| Short name | T2644 |
| Test name | |
| Test status | |
| Simulation time | 291005568 ps |
| CPU time | 23.63 seconds |
| Started | Jul 31 07:53:29 PM PDT 24 |
| Finished | Jul 31 07:53:53 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-5af1eeff-8e71-4043-8de6-29bce9d8e47e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906669017 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.1906669017 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random.3845463586 |
| Short name | T2854 |
| Test name | |
| Test status | |
| Simulation time | 932689454 ps |
| CPU time | 33.5 seconds |
| Started | Jul 31 07:53:25 PM PDT 24 |
| Finished | Jul 31 07:53:58 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-899f7caf-2b9a-4b6d-a79e-d2ae001d08eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845463586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random.3845463586 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_large_delays.1224192141 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 107726278858 ps |
| CPU time | 1207.78 seconds |
| Started | Jul 31 07:53:27 PM PDT 24 |
| Finished | Jul 31 08:13:35 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-15ef32ea-d6af-462d-ab0b-877685a11286 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224192141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.1224192141 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_slow_rsp.3547849459 |
| Short name | T2276 |
| Test name | |
| Test status | |
| Simulation time | 10378699375 ps |
| CPU time | 171.2 seconds |
| Started | Jul 31 07:53:24 PM PDT 24 |
| Finished | Jul 31 07:56:15 PM PDT 24 |
| Peak memory | 576684 kb |
| Host | smart-76159660-0a59-4ff1-a8fe-e588dc838fb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547849459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.3547849459 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_zero_delays.982771039 |
| Short name | T1440 |
| Test name | |
| Test status | |
| Simulation time | 131288163 ps |
| CPU time | 15.35 seconds |
| Started | Jul 31 07:53:27 PM PDT 24 |
| Finished | Jul 31 07:53:42 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-69ff9991-2ef9-4a8c-8fd8-2df78aeb076f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982771039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_dela ys.982771039 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_same_source.1898308039 |
| Short name | T2349 |
| Test name | |
| Test status | |
| Simulation time | 235156108 ps |
| CPU time | 20.53 seconds |
| Started | Jul 31 07:53:33 PM PDT 24 |
| Finished | Jul 31 07:53:53 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-01e30d35-befb-4af6-b43b-0e6b7ab0f212 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898308039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.1898308039 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke.576479677 |
| Short name | T1599 |
| Test name | |
| Test status | |
| Simulation time | 213822736 ps |
| CPU time | 9.58 seconds |
| Started | Jul 31 07:53:24 PM PDT 24 |
| Finished | Jul 31 07:53:33 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-9ea5a24e-a9fd-4370-9792-7230fc413919 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576479677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.576479677 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_large_delays.1430164156 |
| Short name | T1594 |
| Test name | |
| Test status | |
| Simulation time | 9511310218 ps |
| CPU time | 101.33 seconds |
| Started | Jul 31 07:53:25 PM PDT 24 |
| Finished | Jul 31 07:55:06 PM PDT 24 |
| Peak memory | 574676 kb |
| Host | smart-6f910d3d-1062-4ef3-bfd9-8bf63557c6c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430164156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.1430164156 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.3134153626 |
| Short name | T1640 |
| Test name | |
| Test status | |
| Simulation time | 5639476579 ps |
| CPU time | 97.34 seconds |
| Started | Jul 31 07:53:24 PM PDT 24 |
| Finished | Jul 31 07:55:02 PM PDT 24 |
| Peak memory | 573836 kb |
| Host | smart-69118c4a-d724-43b7-8fa3-ec8923e6044e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134153626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.3134153626 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_zero_delays.2014537219 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 42711842 ps |
| CPU time | 6.49 seconds |
| Started | Jul 31 07:53:26 PM PDT 24 |
| Finished | Jul 31 07:53:32 PM PDT 24 |
| Peak memory | 573828 kb |
| Host | smart-922784cf-0071-4dbe-8fb7-dc88b2e791e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014537219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delay s.2014537219 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all.141428316 |
| Short name | T2710 |
| Test name | |
| Test status | |
| Simulation time | 2713823947 ps |
| CPU time | 187.2 seconds |
| Started | Jul 31 07:53:32 PM PDT 24 |
| Finished | Jul 31 07:56:39 PM PDT 24 |
| Peak memory | 576756 kb |
| Host | smart-1e2e27e7-7659-4240-b8da-893803fa57b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141428316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.141428316 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.1278783308 |
| Short name | T2895 |
| Test name | |
| Test status | |
| Simulation time | 6790443022 ps |
| CPU time | 251.29 seconds |
| Started | Jul 31 07:53:30 PM PDT 24 |
| Finished | Jul 31 07:57:42 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-8d84fc31-0cc6-44df-a22a-609eb6f4538c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278783308 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.1278783308 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.3190174272 |
| Short name | T2646 |
| Test name | |
| Test status | |
| Simulation time | 640004460 ps |
| CPU time | 234.43 seconds |
| Started | Jul 31 07:53:32 PM PDT 24 |
| Finished | Jul 31 07:57:26 PM PDT 24 |
| Peak memory | 576700 kb |
| Host | smart-ae4dbb03-1bb0-4873-9065-a3fb95b18000 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190174272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all _with_rand_reset.3190174272 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.1366760178 |
| Short name | T1932 |
| Test name | |
| Test status | |
| Simulation time | 4581318034 ps |
| CPU time | 467.23 seconds |
| Started | Jul 31 07:53:37 PM PDT 24 |
| Finished | Jul 31 08:01:24 PM PDT 24 |
| Peak memory | 576756 kb |
| Host | smart-e7513f6a-cc20-41bb-8a92-5dddef2a848e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366760178 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_al l_with_reset_error.1366760178 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_unmapped_addr.2517769763 |
| Short name | T1592 |
| Test name | |
| Test status | |
| Simulation time | 719779331 ps |
| CPU time | 29.56 seconds |
| Started | Jul 31 07:53:32 PM PDT 24 |
| Finished | Jul 31 07:54:02 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-71b9e8fe-7852-4dfd-8f48-36f9c6f8b94f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517769763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.2517769763 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device.2814946217 |
| Short name | T2341 |
| Test name | |
| Test status | |
| Simulation time | 1377953639 ps |
| CPU time | 91.86 seconds |
| Started | Jul 31 07:53:43 PM PDT 24 |
| Finished | Jul 31 07:55:15 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-cebc9d30-42e7-4874-b15c-086f27254bbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814946217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device .2814946217 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.848138466 |
| Short name | T2586 |
| Test name | |
| Test status | |
| Simulation time | 33055668992 ps |
| CPU time | 530.18 seconds |
| Started | Jul 31 07:53:41 PM PDT 24 |
| Finished | Jul 31 08:02:31 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-b96bce47-6311-4c4e-a499-78756df89bd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848138466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_d evice_slow_rsp.848138466 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.654452667 |
| Short name | T1437 |
| Test name | |
| Test status | |
| Simulation time | 61792661 ps |
| CPU time | 8.4 seconds |
| Started | Jul 31 07:53:49 PM PDT 24 |
| Finished | Jul 31 07:53:57 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-08e47320-6332-4aa9-b29a-a1e3b928323f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654452667 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr .654452667 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_random.191477002 |
| Short name | T1562 |
| Test name | |
| Test status | |
| Simulation time | 519313263 ps |
| CPU time | 21.6 seconds |
| Started | Jul 31 07:53:37 PM PDT 24 |
| Finished | Jul 31 07:53:59 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-bd6829a5-0e6a-4b41-80ea-9d84146cc9b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191477002 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.191477002 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random.950945656 |
| Short name | T2374 |
| Test name | |
| Test status | |
| Simulation time | 313649353 ps |
| CPU time | 32.81 seconds |
| Started | Jul 31 07:53:40 PM PDT 24 |
| Finished | Jul 31 07:54:12 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-16f5cc75-6eb1-4848-927a-e01b98d01093 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950945656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random.950945656 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_large_delays.2960137197 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 51150088660 ps |
| CPU time | 577.84 seconds |
| Started | Jul 31 07:53:43 PM PDT 24 |
| Finished | Jul 31 08:03:21 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-630acdf7-fa3e-4d57-a818-58b871d70185 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960137197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.2960137197 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_slow_rsp.2535339604 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 60828869666 ps |
| CPU time | 1070.57 seconds |
| Started | Jul 31 07:53:38 PM PDT 24 |
| Finished | Jul 31 08:11:29 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-4a28cdf4-c9c8-4076-ba89-d15a111ba44a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535339604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.2535339604 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_zero_delays.224168749 |
| Short name | T2265 |
| Test name | |
| Test status | |
| Simulation time | 364558018 ps |
| CPU time | 35.74 seconds |
| Started | Jul 31 07:53:37 PM PDT 24 |
| Finished | Jul 31 07:54:13 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-0b89d49a-05f5-430e-8b24-f1ea33ceac49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224168749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_dela ys.224168749 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_same_source.962807911 |
| Short name | T2560 |
| Test name | |
| Test status | |
| Simulation time | 343727730 ps |
| CPU time | 26.16 seconds |
| Started | Jul 31 07:53:43 PM PDT 24 |
| Finished | Jul 31 07:54:09 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-f5321c9f-cd6e-4d17-9d96-63075bbe1880 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962807911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.962807911 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke.4219327865 |
| Short name | T1598 |
| Test name | |
| Test status | |
| Simulation time | 192345438 ps |
| CPU time | 8.37 seconds |
| Started | Jul 31 07:53:32 PM PDT 24 |
| Finished | Jul 31 07:53:41 PM PDT 24 |
| Peak memory | 574412 kb |
| Host | smart-97e1dc53-da46-4004-a942-d42bc6bec9de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219327865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.4219327865 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_large_delays.53389533 |
| Short name | T2141 |
| Test name | |
| Test status | |
| Simulation time | 10164881298 ps |
| CPU time | 104.58 seconds |
| Started | Jul 31 07:53:33 PM PDT 24 |
| Finished | Jul 31 07:55:17 PM PDT 24 |
| Peak memory | 573824 kb |
| Host | smart-79291d6a-d8c0-4ce9-8ee6-acd4e5c18ad2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53389533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.53389533 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.4246159919 |
| Short name | T1638 |
| Test name | |
| Test status | |
| Simulation time | 5947671766 ps |
| CPU time | 93.98 seconds |
| Started | Jul 31 07:53:37 PM PDT 24 |
| Finished | Jul 31 07:55:11 PM PDT 24 |
| Peak memory | 574580 kb |
| Host | smart-4db98014-693a-456e-9079-875fe76ec630 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246159919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.4246159919 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.978976984 |
| Short name | T1476 |
| Test name | |
| Test status | |
| Simulation time | 48095517 ps |
| CPU time | 6.26 seconds |
| Started | Jul 31 07:53:31 PM PDT 24 |
| Finished | Jul 31 07:53:38 PM PDT 24 |
| Peak memory | 573716 kb |
| Host | smart-948abc29-0f9a-4daf-925c-bee284cd4b43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978976984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays .978976984 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all.1915683196 |
| Short name | T1593 |
| Test name | |
| Test status | |
| Simulation time | 1102745929 ps |
| CPU time | 51 seconds |
| Started | Jul 31 07:53:43 PM PDT 24 |
| Finished | Jul 31 07:54:34 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-6f0c83cf-1fd8-4534-9477-00039f15ae77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915683196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.1915683196 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_error.2310137663 |
| Short name | T1968 |
| Test name | |
| Test status | |
| Simulation time | 6475968556 ps |
| CPU time | 216.77 seconds |
| Started | Jul 31 07:53:44 PM PDT 24 |
| Finished | Jul 31 07:57:21 PM PDT 24 |
| Peak memory | 576284 kb |
| Host | smart-9ad327eb-9e42-4c33-9a39-f674d6f6936f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310137663 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.2310137663 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.2996914371 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 269664792 ps |
| CPU time | 65.75 seconds |
| Started | Jul 31 07:53:43 PM PDT 24 |
| Finished | Jul 31 07:54:49 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-cbad5352-6cb5-4ce5-8a67-0455ae023146 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996914371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all _with_rand_reset.2996914371 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.677106902 |
| Short name | T1863 |
| Test name | |
| Test status | |
| Simulation time | 4976864566 ps |
| CPU time | 314.22 seconds |
| Started | Jul 31 07:53:43 PM PDT 24 |
| Finished | Jul 31 07:58:58 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-d57618f0-ab85-4acc-aef1-de5e76b70e1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677106902 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all _with_reset_error.677106902 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_unmapped_addr.4063580294 |
| Short name | T2024 |
| Test name | |
| Test status | |
| Simulation time | 716123080 ps |
| CPU time | 34.89 seconds |
| Started | Jul 31 07:53:36 PM PDT 24 |
| Finished | Jul 31 07:54:11 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-fd2defaf-be45-40ef-899c-cc643adb2003 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063580294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.4063580294 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device.2321867069 |
| Short name | T2793 |
| Test name | |
| Test status | |
| Simulation time | 678965381 ps |
| CPU time | 31.28 seconds |
| Started | Jul 31 07:53:50 PM PDT 24 |
| Finished | Jul 31 07:54:21 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-d272f2b3-6664-4e7b-9702-744ddbff6e26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321867069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device .2321867069 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.2737733529 |
| Short name | T2339 |
| Test name | |
| Test status | |
| Simulation time | 36425826264 ps |
| CPU time | 666.79 seconds |
| Started | Jul 31 07:53:50 PM PDT 24 |
| Finished | Jul 31 08:04:57 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-3a81b627-8ecc-400a-802d-0632482be074 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737733529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_ device_slow_rsp.2737733529 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.3941005714 |
| Short name | T2278 |
| Test name | |
| Test status | |
| Simulation time | 1414332514 ps |
| CPU time | 60.56 seconds |
| Started | Jul 31 07:53:57 PM PDT 24 |
| Finished | Jul 31 07:54:58 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-6acf53ff-8515-44ba-9f86-dcc7a7fda22e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941005714 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_add r.3941005714 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_random.3680920588 |
| Short name | T1852 |
| Test name | |
| Test status | |
| Simulation time | 502312345 ps |
| CPU time | 42.73 seconds |
| Started | Jul 31 07:53:50 PM PDT 24 |
| Finished | Jul 31 07:54:33 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-04ba5929-4e6d-4161-a22c-d5fd6e88ffe5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680920588 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.3680920588 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random.1720197465 |
| Short name | T2122 |
| Test name | |
| Test status | |
| Simulation time | 242287572 ps |
| CPU time | 21.02 seconds |
| Started | Jul 31 07:53:50 PM PDT 24 |
| Finished | Jul 31 07:54:11 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-0767a8e8-12b9-4279-8d20-6578fcaa5f45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720197465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random.1720197465 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_large_delays.572049974 |
| Short name | T2033 |
| Test name | |
| Test status | |
| Simulation time | 50108087050 ps |
| CPU time | 498.41 seconds |
| Started | Jul 31 07:53:50 PM PDT 24 |
| Finished | Jul 31 08:02:08 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-88276f9f-1eb6-4974-9630-df0a0e5c4e12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572049974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.572049974 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.38047261 |
| Short name | T2773 |
| Test name | |
| Test status | |
| Simulation time | 18160709805 ps |
| CPU time | 305.71 seconds |
| Started | Jul 31 07:53:50 PM PDT 24 |
| Finished | Jul 31 07:58:55 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-93568717-072f-41ae-9412-e4ad0a24b90c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38047261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.38047261 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.3610461588 |
| Short name | T2689 |
| Test name | |
| Test status | |
| Simulation time | 376552582 ps |
| CPU time | 34.13 seconds |
| Started | Jul 31 07:53:51 PM PDT 24 |
| Finished | Jul 31 07:54:25 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-40c8023c-6d70-4d90-bb23-621b07293bcd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610461588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_del ays.3610461588 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_same_source.2079454272 |
| Short name | T2284 |
| Test name | |
| Test status | |
| Simulation time | 36563262 ps |
| CPU time | 6.23 seconds |
| Started | Jul 31 07:53:50 PM PDT 24 |
| Finished | Jul 31 07:53:56 PM PDT 24 |
| Peak memory | 574524 kb |
| Host | smart-95d85acb-3543-45f7-8841-2cadb43b3c84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079454272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.2079454272 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke.4250908120 |
| Short name | T1421 |
| Test name | |
| Test status | |
| Simulation time | 54336399 ps |
| CPU time | 6.62 seconds |
| Started | Jul 31 07:53:42 PM PDT 24 |
| Finished | Jul 31 07:53:49 PM PDT 24 |
| Peak memory | 574500 kb |
| Host | smart-2c3ca661-b193-4d72-bb34-81329c276562 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250908120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.4250908120 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.1269523300 |
| Short name | T2896 |
| Test name | |
| Test status | |
| Simulation time | 8272268146 ps |
| CPU time | 90.5 seconds |
| Started | Jul 31 07:53:43 PM PDT 24 |
| Finished | Jul 31 07:55:14 PM PDT 24 |
| Peak memory | 573892 kb |
| Host | smart-21fb1b82-9fe9-41db-8bd3-89b35f17991e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269523300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.1269523300 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.4210830685 |
| Short name | T1958 |
| Test name | |
| Test status | |
| Simulation time | 6116601183 ps |
| CPU time | 98.37 seconds |
| Started | Jul 31 07:53:48 PM PDT 24 |
| Finished | Jul 31 07:55:27 PM PDT 24 |
| Peak memory | 573844 kb |
| Host | smart-6eeee7b4-0c54-42af-95af-23037b12c84e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210830685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.4210830685 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.2667559829 |
| Short name | T2065 |
| Test name | |
| Test status | |
| Simulation time | 38932772 ps |
| CPU time | 5.83 seconds |
| Started | Jul 31 07:53:47 PM PDT 24 |
| Finished | Jul 31 07:53:53 PM PDT 24 |
| Peak memory | 574448 kb |
| Host | smart-fa6757e0-10e8-4a17-82a4-4758b2fedb29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667559829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delay s.2667559829 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.3861788380 |
| Short name | T1794 |
| Test name | |
| Test status | |
| Simulation time | 11767758129 ps |
| CPU time | 379.79 seconds |
| Started | Jul 31 07:53:54 PM PDT 24 |
| Finished | Jul 31 08:00:14 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-82bfcbbf-1551-41d6-9bae-20f909a803c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861788380 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.3861788380 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.2425714283 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 926874110 ps |
| CPU time | 105.72 seconds |
| Started | Jul 31 07:53:56 PM PDT 24 |
| Finished | Jul 31 07:55:42 PM PDT 24 |
| Peak memory | 576212 kb |
| Host | smart-bef3a42b-9e5f-4e6f-ac0d-a084122f5e32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425714283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all _with_rand_reset.2425714283 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.3212064194 |
| Short name | T1937 |
| Test name | |
| Test status | |
| Simulation time | 454325344 ps |
| CPU time | 162.89 seconds |
| Started | Jul 31 07:53:56 PM PDT 24 |
| Finished | Jul 31 07:56:39 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-b123d719-1ba5-491c-9ad0-24d5746e6797 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212064194 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_al l_with_reset_error.3212064194 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_unmapped_addr.1357407094 |
| Short name | T2023 |
| Test name | |
| Test status | |
| Simulation time | 66862758 ps |
| CPU time | 9.51 seconds |
| Started | Jul 31 07:53:55 PM PDT 24 |
| Finished | Jul 31 07:54:05 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-eba73264-76e7-4bce-bfd4-8f5d4fbf55b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357407094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.1357407094 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device.3016983099 |
| Short name | T1586 |
| Test name | |
| Test status | |
| Simulation time | 3114248284 ps |
| CPU time | 146.15 seconds |
| Started | Jul 31 07:54:05 PM PDT 24 |
| Finished | Jul 31 07:56:31 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-883dc7c2-9eab-4494-b637-4272b0a0673d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016983099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device .3016983099 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.1180939946 |
| Short name | T2118 |
| Test name | |
| Test status | |
| Simulation time | 32120674424 ps |
| CPU time | 580.89 seconds |
| Started | Jul 31 07:54:03 PM PDT 24 |
| Finished | Jul 31 08:03:44 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-397ee018-c5d0-44bb-9518-97553305358c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180939946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_ device_slow_rsp.1180939946 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.3048866702 |
| Short name | T2046 |
| Test name | |
| Test status | |
| Simulation time | 1261423292 ps |
| CPU time | 52.59 seconds |
| Started | Jul 31 07:54:05 PM PDT 24 |
| Finished | Jul 31 07:54:57 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-181e5e9a-863e-4aad-9ba9-77908ba4a763 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048866702 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_add r.3048866702 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_random.4238039545 |
| Short name | T2459 |
| Test name | |
| Test status | |
| Simulation time | 472507350 ps |
| CPU time | 17.14 seconds |
| Started | Jul 31 07:54:04 PM PDT 24 |
| Finished | Jul 31 07:54:21 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-61849b39-4493-4393-99b9-b003ede08d15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238039545 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.4238039545 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random.529540034 |
| Short name | T2264 |
| Test name | |
| Test status | |
| Simulation time | 296943354 ps |
| CPU time | 26.86 seconds |
| Started | Jul 31 07:54:01 PM PDT 24 |
| Finished | Jul 31 07:54:28 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-f5a5411b-0eff-4ab1-a470-b7a828638eb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529540034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random.529540034 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_large_delays.3052882578 |
| Short name | T2208 |
| Test name | |
| Test status | |
| Simulation time | 15545938312 ps |
| CPU time | 162.38 seconds |
| Started | Jul 31 07:54:02 PM PDT 24 |
| Finished | Jul 31 07:56:44 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-fed35f98-57ba-4895-b1ca-20d2b9298620 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052882578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.3052882578 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.2319008004 |
| Short name | T1895 |
| Test name | |
| Test status | |
| Simulation time | 40218603919 ps |
| CPU time | 668.33 seconds |
| Started | Jul 31 07:54:04 PM PDT 24 |
| Finished | Jul 31 08:05:12 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-84a4216e-fb5a-437e-8fc9-8046368acf08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319008004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.2319008004 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.2364355235 |
| Short name | T2186 |
| Test name | |
| Test status | |
| Simulation time | 346434622 ps |
| CPU time | 30.48 seconds |
| Started | Jul 31 07:54:04 PM PDT 24 |
| Finished | Jul 31 07:54:35 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-a0551eb5-9259-4fdc-bb53-c02a17a416cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364355235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_del ays.2364355235 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_same_source.3945461513 |
| Short name | T2228 |
| Test name | |
| Test status | |
| Simulation time | 2453343444 ps |
| CPU time | 75.38 seconds |
| Started | Jul 31 07:54:04 PM PDT 24 |
| Finished | Jul 31 07:55:20 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-01e5cc93-a89b-45cd-b0d5-7f44f81710ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945461513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.3945461513 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke.247581968 |
| Short name | T1816 |
| Test name | |
| Test status | |
| Simulation time | 43356523 ps |
| CPU time | 5.61 seconds |
| Started | Jul 31 07:53:56 PM PDT 24 |
| Finished | Jul 31 07:54:01 PM PDT 24 |
| Peak memory | 574512 kb |
| Host | smart-71d33f27-3acf-46ad-b1dd-0e4ac82777ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247581968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.247581968 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_large_delays.3669240605 |
| Short name | T2303 |
| Test name | |
| Test status | |
| Simulation time | 8293604768 ps |
| CPU time | 87.33 seconds |
| Started | Jul 31 07:53:56 PM PDT 24 |
| Finished | Jul 31 07:55:24 PM PDT 24 |
| Peak memory | 573888 kb |
| Host | smart-2f529285-9215-4a32-be1b-3ac1d6d7b350 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669240605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.3669240605 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.1829831036 |
| Short name | T2085 |
| Test name | |
| Test status | |
| Simulation time | 6144654635 ps |
| CPU time | 102.43 seconds |
| Started | Jul 31 07:53:57 PM PDT 24 |
| Finished | Jul 31 07:55:40 PM PDT 24 |
| Peak memory | 573936 kb |
| Host | smart-377797d4-f463-43a8-9200-4ed146bb4d87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829831036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.1829831036 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_zero_delays.1646007107 |
| Short name | T2193 |
| Test name | |
| Test status | |
| Simulation time | 45207461 ps |
| CPU time | 6.42 seconds |
| Started | Jul 31 07:53:56 PM PDT 24 |
| Finished | Jul 31 07:54:03 PM PDT 24 |
| Peak memory | 573784 kb |
| Host | smart-6a46a474-f020-45e1-9290-16a367e521be |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646007107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delay s.1646007107 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all.3621546653 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 1811258270 ps |
| CPU time | 145.02 seconds |
| Started | Jul 31 07:54:03 PM PDT 24 |
| Finished | Jul 31 07:56:28 PM PDT 24 |
| Peak memory | 576320 kb |
| Host | smart-1f5d2cb8-f984-4e2d-821c-15e5229e0692 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621546653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.3621546653 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.1344109950 |
| Short name | T1995 |
| Test name | |
| Test status | |
| Simulation time | 7407109333 ps |
| CPU time | 281.81 seconds |
| Started | Jul 31 07:54:07 PM PDT 24 |
| Finished | Jul 31 07:58:49 PM PDT 24 |
| Peak memory | 576536 kb |
| Host | smart-4ae514be-401a-4d7b-8fa6-605df9b94d04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344109950 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.1344109950 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.2486318337 |
| Short name | T2008 |
| Test name | |
| Test status | |
| Simulation time | 143291465 ps |
| CPU time | 55.14 seconds |
| Started | Jul 31 07:54:10 PM PDT 24 |
| Finished | Jul 31 07:55:05 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-21ef419e-9eda-4957-855e-6d440764ab32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486318337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all _with_rand_reset.2486318337 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.2411453037 |
| Short name | T2301 |
| Test name | |
| Test status | |
| Simulation time | 150648620 ps |
| CPU time | 27 seconds |
| Started | Jul 31 07:54:10 PM PDT 24 |
| Finished | Jul 31 07:54:37 PM PDT 24 |
| Peak memory | 576076 kb |
| Host | smart-4da470a7-27a2-4df3-a589-01c3342fe468 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411453037 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_al l_with_reset_error.2411453037 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_unmapped_addr.1823867504 |
| Short name | T2847 |
| Test name | |
| Test status | |
| Simulation time | 1366576454 ps |
| CPU time | 52.16 seconds |
| Started | Jul 31 07:54:01 PM PDT 24 |
| Finished | Jul 31 07:54:53 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-1fc29ce4-7fda-4d09-88b1-4ec09d9e3df1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823867504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.1823867504 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device.4251420879 |
| Short name | T1790 |
| Test name | |
| Test status | |
| Simulation time | 1776943041 ps |
| CPU time | 79.46 seconds |
| Started | Jul 31 07:54:15 PM PDT 24 |
| Finished | Jul 31 07:55:34 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-d6515f4d-c72a-4554-9311-6da08f4c3e9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251420879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device .4251420879 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.4097416871 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 17272256466 ps |
| CPU time | 319.1 seconds |
| Started | Jul 31 07:54:21 PM PDT 24 |
| Finished | Jul 31 07:59:40 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-3b378b9b-2fa2-45f6-a678-bd866446163f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097416871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_ device_slow_rsp.4097416871 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.47076869 |
| Short name | T1776 |
| Test name | |
| Test status | |
| Simulation time | 1285157489 ps |
| CPU time | 50.8 seconds |
| Started | Jul 31 07:54:14 PM PDT 24 |
| Finished | Jul 31 07:55:05 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-083e44bc-8ac4-4345-9d55-ab236d6bd832 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47076869 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.47076869 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_random.2273762113 |
| Short name | T2022 |
| Test name | |
| Test status | |
| Simulation time | 375102554 ps |
| CPU time | 29.47 seconds |
| Started | Jul 31 07:54:16 PM PDT 24 |
| Finished | Jul 31 07:54:45 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-857fc8bc-bb68-4134-8427-3993109a6251 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273762113 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.2273762113 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random.1424547649 |
| Short name | T1760 |
| Test name | |
| Test status | |
| Simulation time | 2562707146 ps |
| CPU time | 95.19 seconds |
| Started | Jul 31 07:54:09 PM PDT 24 |
| Finished | Jul 31 07:55:44 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-69923d74-4521-4145-ab05-f844f003c027 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424547649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random.1424547649 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_large_delays.4030705470 |
| Short name | T2153 |
| Test name | |
| Test status | |
| Simulation time | 17847106311 ps |
| CPU time | 190.51 seconds |
| Started | Jul 31 07:54:16 PM PDT 24 |
| Finished | Jul 31 07:57:26 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-76ce9df0-ccca-43db-8620-15bda6cc016c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030705470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.4030705470 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_slow_rsp.1283658567 |
| Short name | T1886 |
| Test name | |
| Test status | |
| Simulation time | 60409443942 ps |
| CPU time | 1007.33 seconds |
| Started | Jul 31 07:54:14 PM PDT 24 |
| Finished | Jul 31 08:11:02 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-adeb0dc1-336c-4fc6-b0ea-537726c2d268 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283658567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.1283658567 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_zero_delays.1968241338 |
| Short name | T2666 |
| Test name | |
| Test status | |
| Simulation time | 582649584 ps |
| CPU time | 49.44 seconds |
| Started | Jul 31 07:54:14 PM PDT 24 |
| Finished | Jul 31 07:55:04 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-fa7a0221-d4f7-4595-86a8-7148b66321c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968241338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_del ays.1968241338 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_same_source.3672998426 |
| Short name | T2724 |
| Test name | |
| Test status | |
| Simulation time | 320564803 ps |
| CPU time | 11.26 seconds |
| Started | Jul 31 07:54:20 PM PDT 24 |
| Finished | Jul 31 07:54:31 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-bac63198-371f-4452-80e3-6b7b38359b07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672998426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.3672998426 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke.3992068896 |
| Short name | T1432 |
| Test name | |
| Test status | |
| Simulation time | 47940602 ps |
| CPU time | 5.93 seconds |
| Started | Jul 31 07:54:13 PM PDT 24 |
| Finished | Jul 31 07:54:20 PM PDT 24 |
| Peak memory | 574588 kb |
| Host | smart-a48cc321-dc5a-4ab5-b6cc-9cd73a802d4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992068896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.3992068896 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_large_delays.570496418 |
| Short name | T2329 |
| Test name | |
| Test status | |
| Simulation time | 7863060227 ps |
| CPU time | 78.75 seconds |
| Started | Jul 31 07:54:14 PM PDT 24 |
| Finished | Jul 31 07:55:33 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-b3078ca5-07cb-4802-933d-191b1adcb125 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570496418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.570496418 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.1249965856 |
| Short name | T2534 |
| Test name | |
| Test status | |
| Simulation time | 6119002110 ps |
| CPU time | 101.96 seconds |
| Started | Jul 31 07:54:08 PM PDT 24 |
| Finished | Jul 31 07:55:50 PM PDT 24 |
| Peak memory | 574556 kb |
| Host | smart-169036e7-d347-44d2-b28c-72d970a421d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249965856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.1249965856 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_zero_delays.3173237246 |
| Short name | T2936 |
| Test name | |
| Test status | |
| Simulation time | 56360366 ps |
| CPU time | 6.44 seconds |
| Started | Jul 31 07:54:09 PM PDT 24 |
| Finished | Jul 31 07:54:15 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-6f22f61b-bab9-438d-b764-030b95cd33e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173237246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delay s.3173237246 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all.1495102648 |
| Short name | T2909 |
| Test name | |
| Test status | |
| Simulation time | 10445795670 ps |
| CPU time | 423.26 seconds |
| Started | Jul 31 07:54:15 PM PDT 24 |
| Finished | Jul 31 08:01:18 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-405e1063-3b69-46e1-9b73-b36fd54afd38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495102648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.1495102648 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.1219655484 |
| Short name | T2929 |
| Test name | |
| Test status | |
| Simulation time | 1925772978 ps |
| CPU time | 63.75 seconds |
| Started | Jul 31 07:54:14 PM PDT 24 |
| Finished | Jul 31 07:55:18 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-353f7129-cd91-44eb-9518-f56623faedbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219655484 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.1219655484 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.3278580407 |
| Short name | T2845 |
| Test name | |
| Test status | |
| Simulation time | 766158245 ps |
| CPU time | 270.43 seconds |
| Started | Jul 31 07:54:14 PM PDT 24 |
| Finished | Jul 31 07:58:44 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-20922510-a9f0-4208-ab0c-a84727645752 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278580407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all _with_rand_reset.3278580407 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_unmapped_addr.3589321674 |
| Short name | T2126 |
| Test name | |
| Test status | |
| Simulation time | 1098935218 ps |
| CPU time | 47.92 seconds |
| Started | Jul 31 07:54:13 PM PDT 24 |
| Finished | Jul 31 07:55:02 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-5ad65316-ad67-4f14-b924-bcc3b208aff4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589321674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.3589321674 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device.4249347071 |
| Short name | T2639 |
| Test name | |
| Test status | |
| Simulation time | 24301115 ps |
| CPU time | 8.48 seconds |
| Started | Jul 31 07:54:32 PM PDT 24 |
| Finished | Jul 31 07:54:40 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-0f4f6238-f4d5-4a80-83f3-159afa1d78f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249347071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device .4249347071 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.718326020 |
| Short name | T1773 |
| Test name | |
| Test status | |
| Simulation time | 75877653026 ps |
| CPU time | 1391.35 seconds |
| Started | Jul 31 07:54:31 PM PDT 24 |
| Finished | Jul 31 08:17:43 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-c5f174a2-afb3-45dd-9d4f-00ad5cb767f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718326020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_d evice_slow_rsp.718326020 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.2958613131 |
| Short name | T1761 |
| Test name | |
| Test status | |
| Simulation time | 789678820 ps |
| CPU time | 30.65 seconds |
| Started | Jul 31 07:54:32 PM PDT 24 |
| Finished | Jul 31 07:55:03 PM PDT 24 |
| Peak memory | 576044 kb |
| Host | smart-3d135f41-f76f-4b23-afa3-fbdb10821420 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958613131 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_add r.2958613131 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_random.2937191297 |
| Short name | T2201 |
| Test name | |
| Test status | |
| Simulation time | 1259975955 ps |
| CPU time | 44.62 seconds |
| Started | Jul 31 07:54:31 PM PDT 24 |
| Finished | Jul 31 07:55:16 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-65ca1aaa-33cf-4581-bcb1-73985bf143a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937191297 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.2937191297 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random.3182115498 |
| Short name | T2648 |
| Test name | |
| Test status | |
| Simulation time | 1763522882 ps |
| CPU time | 56.07 seconds |
| Started | Jul 31 07:54:20 PM PDT 24 |
| Finished | Jul 31 07:55:16 PM PDT 24 |
| Peak memory | 576024 kb |
| Host | smart-05003023-e734-434f-89e5-4bb564e7b921 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182115498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random.3182115498 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_large_delays.176349093 |
| Short name | T2870 |
| Test name | |
| Test status | |
| Simulation time | 68286180570 ps |
| CPU time | 713.49 seconds |
| Started | Jul 31 07:54:25 PM PDT 24 |
| Finished | Jul 31 08:06:18 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-3c62dfec-438e-484d-b68d-14d1b519cee3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176349093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.176349093 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_slow_rsp.1561367463 |
| Short name | T2104 |
| Test name | |
| Test status | |
| Simulation time | 37823114862 ps |
| CPU time | 669.02 seconds |
| Started | Jul 31 07:54:32 PM PDT 24 |
| Finished | Jul 31 08:05:41 PM PDT 24 |
| Peak memory | 576096 kb |
| Host | smart-5f255ffb-73b6-4133-a605-f29563d35b20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561367463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.1561367463 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_zero_delays.935641182 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 416814870 ps |
| CPU time | 34.9 seconds |
| Started | Jul 31 07:54:21 PM PDT 24 |
| Finished | Jul 31 07:54:55 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-facf543f-3e88-4ec5-a052-901f7de4433a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935641182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_dela ys.935641182 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_same_source.2464553147 |
| Short name | T1824 |
| Test name | |
| Test status | |
| Simulation time | 90456298 ps |
| CPU time | 9.78 seconds |
| Started | Jul 31 07:54:30 PM PDT 24 |
| Finished | Jul 31 07:54:39 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-6e356109-6c13-49b2-af03-1dbd799d0408 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464553147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.2464553147 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke.3084376926 |
| Short name | T1635 |
| Test name | |
| Test status | |
| Simulation time | 47723255 ps |
| CPU time | 6.1 seconds |
| Started | Jul 31 07:54:19 PM PDT 24 |
| Finished | Jul 31 07:54:25 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-7bd0d76b-3b53-47ed-8f4a-b631be8b56cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084376926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.3084376926 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_large_delays.1993750969 |
| Short name | T2395 |
| Test name | |
| Test status | |
| Simulation time | 7478580421 ps |
| CPU time | 79.73 seconds |
| Started | Jul 31 07:54:24 PM PDT 24 |
| Finished | Jul 31 07:55:44 PM PDT 24 |
| Peak memory | 573752 kb |
| Host | smart-f99b8307-c2e9-4f3f-86c4-31ee68cbfc1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993750969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.1993750969 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.1965162532 |
| Short name | T1422 |
| Test name | |
| Test status | |
| Simulation time | 5958680978 ps |
| CPU time | 98.73 seconds |
| Started | Jul 31 07:54:24 PM PDT 24 |
| Finished | Jul 31 07:56:03 PM PDT 24 |
| Peak memory | 573768 kb |
| Host | smart-a1012de9-bd39-4e64-9f94-60abada9bfc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965162532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.1965162532 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.1173944178 |
| Short name | T2653 |
| Test name | |
| Test status | |
| Simulation time | 45708821 ps |
| CPU time | 6.59 seconds |
| Started | Jul 31 07:54:25 PM PDT 24 |
| Finished | Jul 31 07:54:32 PM PDT 24 |
| Peak memory | 574488 kb |
| Host | smart-26338d5a-faf1-478f-a9f1-b33b23167bab |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173944178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delay s.1173944178 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all.953496048 |
| Short name | T1871 |
| Test name | |
| Test status | |
| Simulation time | 1413101328 ps |
| CPU time | 56.49 seconds |
| Started | Jul 31 07:54:31 PM PDT 24 |
| Finished | Jul 31 07:55:27 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-59805c07-1151-4331-a6d4-eaf3e1162e2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953496048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.953496048 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.1864737223 |
| Short name | T1808 |
| Test name | |
| Test status | |
| Simulation time | 10847414807 ps |
| CPU time | 412.9 seconds |
| Started | Jul 31 07:54:31 PM PDT 24 |
| Finished | Jul 31 08:01:24 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-ebd1ab96-7e55-46ab-b250-227cb2eae0f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864737223 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.1864737223 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.3532880382 |
| Short name | T1563 |
| Test name | |
| Test status | |
| Simulation time | 693815263 ps |
| CPU time | 219.51 seconds |
| Started | Jul 31 07:54:31 PM PDT 24 |
| Finished | Jul 31 07:58:10 PM PDT 24 |
| Peak memory | 576720 kb |
| Host | smart-0395a249-f9d5-49c9-8126-231fdfd32c38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532880382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all _with_rand_reset.3532880382 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.646353877 |
| Short name | T2147 |
| Test name | |
| Test status | |
| Simulation time | 4737047907 ps |
| CPU time | 613.1 seconds |
| Started | Jul 31 07:54:32 PM PDT 24 |
| Finished | Jul 31 08:04:45 PM PDT 24 |
| Peak memory | 578164 kb |
| Host | smart-0646da7d-86a0-401a-be9b-3a063fad94df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646353877 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all _with_reset_error.646353877 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_unmapped_addr.15872931 |
| Short name | T2650 |
| Test name | |
| Test status | |
| Simulation time | 220338700 ps |
| CPU time | 29.34 seconds |
| Started | Jul 31 07:54:32 PM PDT 24 |
| Finished | Jul 31 07:55:01 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-95995419-1bbb-4c5f-a91e-ca686b84f27c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15872931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.15872931 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device.3711509404 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 2132658008 ps |
| CPU time | 104.55 seconds |
| Started | Jul 31 07:54:37 PM PDT 24 |
| Finished | Jul 31 07:56:22 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-9da84eb3-4cb8-4b58-bf90-c211dd5ccbad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711509404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device .3711509404 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.3437726801 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 30241724932 ps |
| CPU time | 498.62 seconds |
| Started | Jul 31 07:54:42 PM PDT 24 |
| Finished | Jul 31 08:03:01 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-ec91eb38-2a14-47ec-b07b-d9a7be524630 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437726801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_ device_slow_rsp.3437726801 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.1943768154 |
| Short name | T2718 |
| Test name | |
| Test status | |
| Simulation time | 1077132696 ps |
| CPU time | 40.8 seconds |
| Started | Jul 31 07:54:42 PM PDT 24 |
| Finished | Jul 31 07:55:23 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-8b7d1ae9-691e-4c21-a68f-153a9e253a43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943768154 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_add r.1943768154 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_random.2083303490 |
| Short name | T2823 |
| Test name | |
| Test status | |
| Simulation time | 2510905666 ps |
| CPU time | 95.95 seconds |
| Started | Jul 31 07:54:40 PM PDT 24 |
| Finished | Jul 31 07:56:16 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-9a833ff9-4aa7-4242-9484-b6375b196afd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083303490 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.2083303490 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random.1148294438 |
| Short name | T1959 |
| Test name | |
| Test status | |
| Simulation time | 337819123 ps |
| CPU time | 30.33 seconds |
| Started | Jul 31 07:54:34 PM PDT 24 |
| Finished | Jul 31 07:55:04 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-006f7b18-e2a7-41be-99d8-e3b3e45472fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148294438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random.1148294438 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_large_delays.1747532000 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 84544537932 ps |
| CPU time | 881.25 seconds |
| Started | Jul 31 07:54:33 PM PDT 24 |
| Finished | Jul 31 08:09:14 PM PDT 24 |
| Peak memory | 576056 kb |
| Host | smart-8d4a4d34-88c0-4c11-9a91-ac581a5197d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747532000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.1747532000 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.3833313048 |
| Short name | T2898 |
| Test name | |
| Test status | |
| Simulation time | 67820241073 ps |
| CPU time | 1140.89 seconds |
| Started | Jul 31 07:54:33 PM PDT 24 |
| Finished | Jul 31 08:13:34 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-18e0868f-099a-47ba-b8c3-d843cd1a2d44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833313048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.3833313048 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.2797299423 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 577260864 ps |
| CPU time | 51.58 seconds |
| Started | Jul 31 07:54:34 PM PDT 24 |
| Finished | Jul 31 07:55:25 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-b2c9230f-1f7f-472d-a730-b42863f00115 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797299423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_del ays.2797299423 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_same_source.1744299384 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 2710263274 ps |
| CPU time | 80.52 seconds |
| Started | Jul 31 07:54:41 PM PDT 24 |
| Finished | Jul 31 07:56:01 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-f187429d-3766-46b8-a399-5658c14e007c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744299384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.1744299384 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke.2017202757 |
| Short name | T2755 |
| Test name | |
| Test status | |
| Simulation time | 265595926 ps |
| CPU time | 11.31 seconds |
| Started | Jul 31 07:54:31 PM PDT 24 |
| Finished | Jul 31 07:54:43 PM PDT 24 |
| Peak memory | 573836 kb |
| Host | smart-96459db4-4632-4333-817d-ca927a373efd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017202757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.2017202757 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_large_delays.2042805138 |
| Short name | T2020 |
| Test name | |
| Test status | |
| Simulation time | 9883157165 ps |
| CPU time | 102.22 seconds |
| Started | Jul 31 07:54:32 PM PDT 24 |
| Finished | Jul 31 07:56:15 PM PDT 24 |
| Peak memory | 574520 kb |
| Host | smart-90e7fa5c-a163-4aa6-877b-c7cab7649c03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042805138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.2042805138 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.3076842779 |
| Short name | T1591 |
| Test name | |
| Test status | |
| Simulation time | 3210041199 ps |
| CPU time | 54.34 seconds |
| Started | Jul 31 07:54:33 PM PDT 24 |
| Finished | Jul 31 07:55:27 PM PDT 24 |
| Peak memory | 573900 kb |
| Host | smart-cdc0abd8-c82f-4e5f-b4f9-3fe2350e9359 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076842779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.3076842779 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_zero_delays.193723955 |
| Short name | T1942 |
| Test name | |
| Test status | |
| Simulation time | 43886864 ps |
| CPU time | 5.71 seconds |
| Started | Jul 31 07:54:32 PM PDT 24 |
| Finished | Jul 31 07:54:37 PM PDT 24 |
| Peak memory | 574496 kb |
| Host | smart-38891344-b353-4b4f-915d-a65c2c76049a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193723955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays .193723955 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all.3366270800 |
| Short name | T2312 |
| Test name | |
| Test status | |
| Simulation time | 19792316676 ps |
| CPU time | 766.82 seconds |
| Started | Jul 31 07:54:38 PM PDT 24 |
| Finished | Jul 31 08:07:25 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-ed35d646-4cfe-479e-8242-348339ddbeff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366270800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.3366270800 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_error.2000349457 |
| Short name | T1399 |
| Test name | |
| Test status | |
| Simulation time | 183330468 ps |
| CPU time | 19.02 seconds |
| Started | Jul 31 07:54:40 PM PDT 24 |
| Finished | Jul 31 07:54:59 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-59d99657-b96b-44f6-85ae-4e5bf0ba7d80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000349457 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.2000349457 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.2153245147 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 590558014 ps |
| CPU time | 165.88 seconds |
| Started | Jul 31 07:54:39 PM PDT 24 |
| Finished | Jul 31 07:57:25 PM PDT 24 |
| Peak memory | 576700 kb |
| Host | smart-d1f3c59d-5637-476a-80b2-e28bb8b6f5ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153245147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all _with_rand_reset.2153245147 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.489800520 |
| Short name | T2189 |
| Test name | |
| Test status | |
| Simulation time | 785325349 ps |
| CPU time | 273.05 seconds |
| Started | Jul 31 07:54:47 PM PDT 24 |
| Finished | Jul 31 07:59:20 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-dee08159-775e-40b2-9a2c-4c3dfcdd527b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489800520 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all _with_reset_error.489800520 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_unmapped_addr.2337059466 |
| Short name | T1748 |
| Test name | |
| Test status | |
| Simulation time | 670026524 ps |
| CPU time | 29.52 seconds |
| Started | Jul 31 07:54:41 PM PDT 24 |
| Finished | Jul 31 07:55:10 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-1c7ae7a4-1f85-4f8e-b337-6d93082add51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337059466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.2337059466 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device.245758913 |
| Short name | T2320 |
| Test name | |
| Test status | |
| Simulation time | 319337488 ps |
| CPU time | 13.89 seconds |
| Started | Jul 31 07:54:47 PM PDT 24 |
| Finished | Jul 31 07:55:01 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-a3150ab1-c144-4198-a986-ee4273bf3487 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245758913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device. 245758913 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.2650479239 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 71109728296 ps |
| CPU time | 1157.83 seconds |
| Started | Jul 31 07:54:45 PM PDT 24 |
| Finished | Jul 31 08:14:03 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-6594d976-4a1c-4dec-891d-0f477f0e6304 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650479239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_ device_slow_rsp.2650479239 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.3245242660 |
| Short name | T2876 |
| Test name | |
| Test status | |
| Simulation time | 155052574 ps |
| CPU time | 14.93 seconds |
| Started | Jul 31 07:54:50 PM PDT 24 |
| Finished | Jul 31 07:55:05 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-172b9bea-3923-4e20-9761-73ea5ca17bdc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245242660 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_add r.3245242660 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_random.1776180240 |
| Short name | T2291 |
| Test name | |
| Test status | |
| Simulation time | 1407274040 ps |
| CPU time | 53.65 seconds |
| Started | Jul 31 07:54:49 PM PDT 24 |
| Finished | Jul 31 07:55:43 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-4615d949-c919-44d5-a52a-ae6f9347882f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776180240 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.1776180240 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random.2028831057 |
| Short name | T1823 |
| Test name | |
| Test status | |
| Simulation time | 1330772697 ps |
| CPU time | 49.97 seconds |
| Started | Jul 31 07:54:44 PM PDT 24 |
| Finished | Jul 31 07:55:34 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-9ad52859-59db-40f3-8ea5-29c9918fb89b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028831057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random.2028831057 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_large_delays.564967395 |
| Short name | T1697 |
| Test name | |
| Test status | |
| Simulation time | 68251533130 ps |
| CPU time | 711.27 seconds |
| Started | Jul 31 07:54:45 PM PDT 24 |
| Finished | Jul 31 08:06:37 PM PDT 24 |
| Peak memory | 576132 kb |
| Host | smart-c11cf327-8be2-435b-b95a-81a897f57d59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564967395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.564967395 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_slow_rsp.1386207861 |
| Short name | T2190 |
| Test name | |
| Test status | |
| Simulation time | 23722024306 ps |
| CPU time | 382.35 seconds |
| Started | Jul 31 07:54:49 PM PDT 24 |
| Finished | Jul 31 08:01:12 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-d76b3d6d-f9cb-4a2e-83f6-44506c02f436 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386207861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.1386207861 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.3589556600 |
| Short name | T2234 |
| Test name | |
| Test status | |
| Simulation time | 147967487 ps |
| CPU time | 16.61 seconds |
| Started | Jul 31 07:54:43 PM PDT 24 |
| Finished | Jul 31 07:55:00 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-093b63f3-5841-4506-a703-326969e45ff0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589556600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_del ays.3589556600 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_same_source.3611602128 |
| Short name | T1637 |
| Test name | |
| Test status | |
| Simulation time | 234056373 ps |
| CPU time | 20.12 seconds |
| Started | Jul 31 07:54:45 PM PDT 24 |
| Finished | Jul 31 07:55:06 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-b9b68c6f-12ff-4169-9fe1-fdbab1bf78df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611602128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.3611602128 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke.2942431043 |
| Short name | T2218 |
| Test name | |
| Test status | |
| Simulation time | 49503285 ps |
| CPU time | 6.23 seconds |
| Started | Jul 31 07:54:47 PM PDT 24 |
| Finished | Jul 31 07:54:53 PM PDT 24 |
| Peak memory | 573776 kb |
| Host | smart-fb8abd3c-ebe4-464e-8f66-09b0b51bc870 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942431043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.2942431043 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_large_delays.2419083697 |
| Short name | T1507 |
| Test name | |
| Test status | |
| Simulation time | 11131226781 ps |
| CPU time | 112.93 seconds |
| Started | Jul 31 07:54:45 PM PDT 24 |
| Finished | Jul 31 07:56:38 PM PDT 24 |
| Peak memory | 573788 kb |
| Host | smart-0a7f6fb9-73d8-4147-b5d0-47a9ddfc0b62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419083697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.2419083697 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.2356348379 |
| Short name | T2294 |
| Test name | |
| Test status | |
| Simulation time | 4422897953 ps |
| CPU time | 77.19 seconds |
| Started | Jul 31 07:54:46 PM PDT 24 |
| Finished | Jul 31 07:56:03 PM PDT 24 |
| Peak memory | 574528 kb |
| Host | smart-2771c12a-f62d-445a-81a8-0a24162ee57c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356348379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.2356348379 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_zero_delays.1243191836 |
| Short name | T2396 |
| Test name | |
| Test status | |
| Simulation time | 45839780 ps |
| CPU time | 5.95 seconds |
| Started | Jul 31 07:54:44 PM PDT 24 |
| Finished | Jul 31 07:54:50 PM PDT 24 |
| Peak memory | 573812 kb |
| Host | smart-97bf74bd-ed64-46f0-9144-d53df2042888 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243191836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delay s.1243191836 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all.974231891 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 4717159537 ps |
| CPU time | 162.65 seconds |
| Started | Jul 31 07:54:51 PM PDT 24 |
| Finished | Jul 31 07:57:34 PM PDT 24 |
| Peak memory | 576072 kb |
| Host | smart-9ffecc9d-5efd-4404-b7d1-1c7cc9d11838 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974231891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.974231891 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.2707034284 |
| Short name | T2194 |
| Test name | |
| Test status | |
| Simulation time | 1606395754 ps |
| CPU time | 53.72 seconds |
| Started | Jul 31 07:55:01 PM PDT 24 |
| Finished | Jul 31 07:55:55 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-58a2da41-9e6a-4591-a263-b1f56de41d90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707034284 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.2707034284 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.3351107325 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 3940431950 ps |
| CPU time | 361.45 seconds |
| Started | Jul 31 07:54:51 PM PDT 24 |
| Finished | Jul 31 08:00:52 PM PDT 24 |
| Peak memory | 576804 kb |
| Host | smart-d19e8f4e-c15d-4688-9fa8-8bf9d91a97b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351107325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all _with_rand_reset.3351107325 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.3009113166 |
| Short name | T2199 |
| Test name | |
| Test status | |
| Simulation time | 4330672144 ps |
| CPU time | 524.53 seconds |
| Started | Jul 31 07:54:56 PM PDT 24 |
| Finished | Jul 31 08:03:41 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-6cfdbbff-2005-4fc7-92d1-2e6961d6f75e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009113166 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_al l_with_reset_error.3009113166 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_unmapped_addr.1765707426 |
| Short name | T2422 |
| Test name | |
| Test status | |
| Simulation time | 153823228 ps |
| CPU time | 19.55 seconds |
| Started | Jul 31 07:54:51 PM PDT 24 |
| Finished | Jul 31 07:55:10 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-f7f5da18-abc5-4409-8200-de2af58bd7b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765707426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.1765707426 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device.4146635213 |
| Short name | T2493 |
| Test name | |
| Test status | |
| Simulation time | 1405743583 ps |
| CPU time | 57.67 seconds |
| Started | Jul 31 07:54:57 PM PDT 24 |
| Finished | Jul 31 07:55:55 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-2a226e16-5d2e-44e4-ab3d-0013db35edb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146635213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device .4146635213 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.2262072033 |
| Short name | T1799 |
| Test name | |
| Test status | |
| Simulation time | 125288618 ps |
| CPU time | 14.92 seconds |
| Started | Jul 31 07:55:02 PM PDT 24 |
| Finished | Jul 31 07:55:17 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-5d4d89b1-d213-4a63-9c57-7f3a46e2b55c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262072033 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_add r.2262072033 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_random.172556541 |
| Short name | T2217 |
| Test name | |
| Test status | |
| Simulation time | 1098002559 ps |
| CPU time | 34.84 seconds |
| Started | Jul 31 07:54:59 PM PDT 24 |
| Finished | Jul 31 07:55:34 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-72e3ecd6-d1a0-43d6-87b3-7298177c3e6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172556541 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.172556541 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random.1177451870 |
| Short name | T2216 |
| Test name | |
| Test status | |
| Simulation time | 2408093285 ps |
| CPU time | 78.12 seconds |
| Started | Jul 31 07:54:57 PM PDT 24 |
| Finished | Jul 31 07:56:15 PM PDT 24 |
| Peak memory | 576032 kb |
| Host | smart-0082bd0b-a101-496f-8e97-2e1fcde49bc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177451870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random.1177451870 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_large_delays.1763660078 |
| Short name | T2116 |
| Test name | |
| Test status | |
| Simulation time | 86986718396 ps |
| CPU time | 894.87 seconds |
| Started | Jul 31 07:54:58 PM PDT 24 |
| Finished | Jul 31 08:09:54 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-cc153a44-1995-4dbf-823d-7e5385c0be83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763660078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.1763660078 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.3893857534 |
| Short name | T2862 |
| Test name | |
| Test status | |
| Simulation time | 30257586379 ps |
| CPU time | 470.11 seconds |
| Started | Jul 31 07:54:56 PM PDT 24 |
| Finished | Jul 31 08:02:46 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-f2e454fe-7c48-4a2d-8380-4cf56f98996c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893857534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.3893857534 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.3967826494 |
| Short name | T2752 |
| Test name | |
| Test status | |
| Simulation time | 537991416 ps |
| CPU time | 50.1 seconds |
| Started | Jul 31 07:54:56 PM PDT 24 |
| Finished | Jul 31 07:55:46 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-2dbad3c1-4592-4436-8d4f-448709d23102 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967826494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_del ays.3967826494 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_same_source.3463193247 |
| Short name | T2334 |
| Test name | |
| Test status | |
| Simulation time | 529321247 ps |
| CPU time | 40.26 seconds |
| Started | Jul 31 07:54:57 PM PDT 24 |
| Finished | Jul 31 07:55:38 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-62841f4a-cf35-45e1-8ca2-c35cc9c1dcd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463193247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.3463193247 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke.1440064896 |
| Short name | T2246 |
| Test name | |
| Test status | |
| Simulation time | 169696300 ps |
| CPU time | 8.9 seconds |
| Started | Jul 31 07:54:57 PM PDT 24 |
| Finished | Jul 31 07:55:06 PM PDT 24 |
| Peak memory | 573772 kb |
| Host | smart-3eace4ab-a3c1-4533-b3e4-bdfe47a4e88a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440064896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.1440064896 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_large_delays.4082891467 |
| Short name | T2061 |
| Test name | |
| Test status | |
| Simulation time | 8277373107 ps |
| CPU time | 92.65 seconds |
| Started | Jul 31 07:54:58 PM PDT 24 |
| Finished | Jul 31 07:56:31 PM PDT 24 |
| Peak memory | 574608 kb |
| Host | smart-9198c214-f4cb-4820-93a1-0bafc3e92aa8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082891467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.4082891467 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.1314242645 |
| Short name | T1874 |
| Test name | |
| Test status | |
| Simulation time | 4442115688 ps |
| CPU time | 75.58 seconds |
| Started | Jul 31 07:54:59 PM PDT 24 |
| Finished | Jul 31 07:56:14 PM PDT 24 |
| Peak memory | 573864 kb |
| Host | smart-f098ba45-cc39-4fe8-abdc-98dfeb282317 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314242645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.1314242645 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.955157395 |
| Short name | T1926 |
| Test name | |
| Test status | |
| Simulation time | 49207258 ps |
| CPU time | 6.26 seconds |
| Started | Jul 31 07:54:59 PM PDT 24 |
| Finished | Jul 31 07:55:05 PM PDT 24 |
| Peak memory | 573724 kb |
| Host | smart-422608ed-b384-4f27-ab68-efbb8b5679c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955157395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays .955157395 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all.1134131023 |
| Short name | T2450 |
| Test name | |
| Test status | |
| Simulation time | 1584420292 ps |
| CPU time | 71.62 seconds |
| Started | Jul 31 07:55:04 PM PDT 24 |
| Finished | Jul 31 07:56:16 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-19fb5e43-0274-4d50-a172-e30c056e6818 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134131023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.1134131023 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.3685732624 |
| Short name | T2796 |
| Test name | |
| Test status | |
| Simulation time | 6059237383 ps |
| CPU time | 230.26 seconds |
| Started | Jul 31 07:55:02 PM PDT 24 |
| Finished | Jul 31 07:58:53 PM PDT 24 |
| Peak memory | 576124 kb |
| Host | smart-dc721c77-8379-4e4c-8664-4658f520b220 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685732624 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.3685732624 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.288834351 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 1458604296 ps |
| CPU time | 137.82 seconds |
| Started | Jul 31 07:55:04 PM PDT 24 |
| Finished | Jul 31 07:57:22 PM PDT 24 |
| Peak memory | 576668 kb |
| Host | smart-b857852b-e17b-442e-a029-aa0544bcbf41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288834351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_ with_rand_reset.288834351 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.2860611817 |
| Short name | T2759 |
| Test name | |
| Test status | |
| Simulation time | 4162739183 ps |
| CPU time | 384.85 seconds |
| Started | Jul 31 07:55:05 PM PDT 24 |
| Finished | Jul 31 08:01:30 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-56e10df6-bee4-4be3-9e51-3154719d712c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860611817 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_al l_with_reset_error.2860611817 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_unmapped_addr.3334464812 |
| Short name | T2414 |
| Test name | |
| Test status | |
| Simulation time | 25247032 ps |
| CPU time | 5.73 seconds |
| Started | Jul 31 07:55:06 PM PDT 24 |
| Finished | Jul 31 07:55:12 PM PDT 24 |
| Peak memory | 574536 kb |
| Host | smart-7a41782f-0d5d-42bf-8691-393251aa8881 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334464812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.3334464812 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device.3885847146 |
| Short name | T2069 |
| Test name | |
| Test status | |
| Simulation time | 660218760 ps |
| CPU time | 57.66 seconds |
| Started | Jul 31 07:55:13 PM PDT 24 |
| Finished | Jul 31 07:56:11 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-6cf25261-0aec-4fc2-8ef9-4fd010542f0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885847146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device .3885847146 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.289418698 |
| Short name | T1619 |
| Test name | |
| Test status | |
| Simulation time | 42597491062 ps |
| CPU time | 746.43 seconds |
| Started | Jul 31 07:55:13 PM PDT 24 |
| Finished | Jul 31 08:07:40 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-96ab352a-d3bf-4723-84f1-8367aefaba6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289418698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_d evice_slow_rsp.289418698 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.766935861 |
| Short name | T2314 |
| Test name | |
| Test status | |
| Simulation time | 899400253 ps |
| CPU time | 39.22 seconds |
| Started | Jul 31 07:55:09 PM PDT 24 |
| Finished | Jul 31 07:55:49 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-d2696987-58a5-42bc-8d25-435913d8bb0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766935861 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr .766935861 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_random.4280555651 |
| Short name | T2367 |
| Test name | |
| Test status | |
| Simulation time | 566882238 ps |
| CPU time | 45.96 seconds |
| Started | Jul 31 07:55:10 PM PDT 24 |
| Finished | Jul 31 07:55:56 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-1930c162-febc-4137-9031-b07db4ba2230 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280555651 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.4280555651 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random.1556607241 |
| Short name | T2198 |
| Test name | |
| Test status | |
| Simulation time | 2047666964 ps |
| CPU time | 78.68 seconds |
| Started | Jul 31 07:55:10 PM PDT 24 |
| Finished | Jul 31 07:56:29 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-a082a6a9-8572-4629-b953-fb048f3a2c25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556607241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random.1556607241 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_large_delays.3597222337 |
| Short name | T2931 |
| Test name | |
| Test status | |
| Simulation time | 30503414056 ps |
| CPU time | 299.93 seconds |
| Started | Jul 31 07:55:09 PM PDT 24 |
| Finished | Jul 31 08:00:09 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-4b6b09b9-7baa-4a3f-a944-e63896d6d86e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597222337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.3597222337 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_slow_rsp.2478387044 |
| Short name | T2156 |
| Test name | |
| Test status | |
| Simulation time | 22037562366 ps |
| CPU time | 375.82 seconds |
| Started | Jul 31 07:55:09 PM PDT 24 |
| Finished | Jul 31 08:01:25 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-b34328e9-410e-4c93-b779-21793c3f07ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478387044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.2478387044 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_zero_delays.372815638 |
| Short name | T2093 |
| Test name | |
| Test status | |
| Simulation time | 160986330 ps |
| CPU time | 17.55 seconds |
| Started | Jul 31 07:55:09 PM PDT 24 |
| Finished | Jul 31 07:55:27 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-0248e689-3783-4e64-ae36-b905d6624152 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372815638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_dela ys.372815638 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_same_source.3144504729 |
| Short name | T2790 |
| Test name | |
| Test status | |
| Simulation time | 2220596849 ps |
| CPU time | 72.51 seconds |
| Started | Jul 31 07:55:12 PM PDT 24 |
| Finished | Jul 31 07:56:25 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-1866504c-96ff-4b0b-bbc5-c5e78740bd64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144504729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.3144504729 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke.1255364854 |
| Short name | T2443 |
| Test name | |
| Test status | |
| Simulation time | 49836846 ps |
| CPU time | 6.06 seconds |
| Started | Jul 31 07:55:05 PM PDT 24 |
| Finished | Jul 31 07:55:11 PM PDT 24 |
| Peak memory | 573844 kb |
| Host | smart-f3c2df3d-f241-4404-8633-857b96b62fca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255364854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.1255364854 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_large_delays.1485390087 |
| Short name | T2732 |
| Test name | |
| Test status | |
| Simulation time | 8692276021 ps |
| CPU time | 84.59 seconds |
| Started | Jul 31 07:55:03 PM PDT 24 |
| Finished | Jul 31 07:56:27 PM PDT 24 |
| Peak memory | 573956 kb |
| Host | smart-31ff5ec9-5ddb-454d-ab1a-0a584c0e2d1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485390087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.1485390087 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.1175061589 |
| Short name | T1632 |
| Test name | |
| Test status | |
| Simulation time | 4228826983 ps |
| CPU time | 71.43 seconds |
| Started | Jul 31 07:55:03 PM PDT 24 |
| Finished | Jul 31 07:56:15 PM PDT 24 |
| Peak memory | 573804 kb |
| Host | smart-3cf6f7ad-b3f2-480c-8fbb-0907c64cb541 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175061589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.1175061589 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_zero_delays.1067781883 |
| Short name | T2157 |
| Test name | |
| Test status | |
| Simulation time | 55943355 ps |
| CPU time | 6.85 seconds |
| Started | Jul 31 07:55:06 PM PDT 24 |
| Finished | Jul 31 07:55:13 PM PDT 24 |
| Peak memory | 574480 kb |
| Host | smart-86de1dc6-e754-4641-af04-f64a34f6a70f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067781883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delay s.1067781883 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all.3456864171 |
| Short name | T2390 |
| Test name | |
| Test status | |
| Simulation time | 5908397790 ps |
| CPU time | 399.08 seconds |
| Started | Jul 31 07:55:09 PM PDT 24 |
| Finished | Jul 31 08:01:49 PM PDT 24 |
| Peak memory | 576800 kb |
| Host | smart-10247e8e-b9d8-493f-9cc2-d3649c2a5823 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456864171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.3456864171 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.3683662947 |
| Short name | T1468 |
| Test name | |
| Test status | |
| Simulation time | 1216196035 ps |
| CPU time | 100.5 seconds |
| Started | Jul 31 07:55:16 PM PDT 24 |
| Finished | Jul 31 07:56:57 PM PDT 24 |
| Peak memory | 576060 kb |
| Host | smart-cc5cf5d5-e287-401c-acb9-37bbba53763a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683662947 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.3683662947 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.12893112 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 4038295198 ps |
| CPU time | 299.03 seconds |
| Started | Jul 31 07:55:15 PM PDT 24 |
| Finished | Jul 31 08:00:14 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-ad2f95c1-3c3f-4783-bb29-e3af8eee74b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12893112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_w ith_rand_reset.12893112 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.3154231587 |
| Short name | T1949 |
| Test name | |
| Test status | |
| Simulation time | 2353432619 ps |
| CPU time | 321.82 seconds |
| Started | Jul 31 07:55:14 PM PDT 24 |
| Finished | Jul 31 08:00:36 PM PDT 24 |
| Peak memory | 576836 kb |
| Host | smart-9c4c8a74-af68-470e-a757-4b9d6079f449 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154231587 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_al l_with_reset_error.3154231587 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_unmapped_addr.256828073 |
| Short name | T2436 |
| Test name | |
| Test status | |
| Simulation time | 1002427920 ps |
| CPU time | 43.7 seconds |
| Started | Jul 31 07:55:13 PM PDT 24 |
| Finished | Jul 31 07:55:57 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-9d5e7589-5422-41ea-89db-849080b657f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256828073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.256828073 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_bit_bash.2956102395 |
| Short name | T2464 |
| Test name | |
| Test status | |
| Simulation time | 7095900924 ps |
| CPU time | 659.76 seconds |
| Started | Jul 31 07:46:12 PM PDT 24 |
| Finished | Jul 31 07:57:12 PM PDT 24 |
| Peak memory | 592336 kb |
| Host | smart-f46f00e7-eefd-48ab-ad64-6300320f784d |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956102395 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 4.chip_csr_bit_bash.2956102395 |
| Directory | /workspace/4.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.382477567 |
| Short name | T1554 |
| Test name | |
| Test status | |
| Simulation time | 11386167015 ps |
| CPU time | 812.46 seconds |
| Started | Jul 31 07:46:37 PM PDT 24 |
| Finished | Jul 31 08:00:09 PM PDT 24 |
| Peak memory | 649804 kb |
| Host | smart-5be73257-ad36-4386-801c-85ff3d61ec6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382477567 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 4.chip_csr_mem_rw_with_rand_reset.382477567 |
| Directory | /workspace/4.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_rw.1612009197 |
| Short name | T2260 |
| Test name | |
| Test status | |
| Simulation time | 5279514322 ps |
| CPU time | 517.06 seconds |
| Started | Jul 31 07:46:31 PM PDT 24 |
| Finished | Jul 31 07:55:08 PM PDT 24 |
| Peak memory | 599100 kb |
| Host | smart-9989b799-31d1-4023-99ef-448a7cbd0ee5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612009197 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_rw.1612009197 |
| Directory | /workspace/4.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.1525153225 |
| Short name | T2196 |
| Test name | |
| Test status | |
| Simulation time | 26356251108 ps |
| CPU time | 4024.62 seconds |
| Started | Jul 31 07:46:18 PM PDT 24 |
| Finished | Jul 31 08:53:23 PM PDT 24 |
| Peak memory | 593400 kb |
| Host | smart-4430f545-2556-4733-a139-adfe25b85fcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525153225 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 4.chip_same_csr_outstanding.1525153225 |
| Directory | /workspace/4.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_tl_errors.2049904733 |
| Short name | T2319 |
| Test name | |
| Test status | |
| Simulation time | 6036273638 ps |
| CPU time | 685.24 seconds |
| Started | Jul 31 07:46:19 PM PDT 24 |
| Finished | Jul 31 07:57:45 PM PDT 24 |
| Peak memory | 598988 kb |
| Host | smart-42aaa420-a63b-40f2-af13-8a4a8baa1bdb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049904733 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_tl_errors.2049904733 |
| Directory | /workspace/4.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device.4277974078 |
| Short name | T2601 |
| Test name | |
| Test status | |
| Simulation time | 1454757503 ps |
| CPU time | 56.38 seconds |
| Started | Jul 31 07:46:30 PM PDT 24 |
| Finished | Jul 31 07:47:26 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-983bd076-e5b3-42b3-83d2-bf3232d75daf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277974078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device. 4277974078 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.1301119534 |
| Short name | T2178 |
| Test name | |
| Test status | |
| Simulation time | 9105402379 ps |
| CPU time | 158.29 seconds |
| Started | Jul 31 07:46:34 PM PDT 24 |
| Finished | Jul 31 07:49:13 PM PDT 24 |
| Peak memory | 574572 kb |
| Host | smart-62a4ac4a-c09a-4c6a-8af9-93ca1ab2863e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301119534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_d evice_slow_rsp.1301119534 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.3153649362 |
| Short name | T2211 |
| Test name | |
| Test status | |
| Simulation time | 787705794 ps |
| CPU time | 31.65 seconds |
| Started | Jul 31 07:46:31 PM PDT 24 |
| Finished | Jul 31 07:47:03 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-4cfbf4ca-eb67-4d56-abbf-389f2f15ac5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153649362 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr .3153649362 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_random.3756787784 |
| Short name | T2112 |
| Test name | |
| Test status | |
| Simulation time | 616286285 ps |
| CPU time | 21.35 seconds |
| Started | Jul 31 07:46:30 PM PDT 24 |
| Finished | Jul 31 07:46:51 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-561c155b-3ceb-4b42-8199-b97fb6b5cef0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756787784 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.3756787784 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random.1483700676 |
| Short name | T1519 |
| Test name | |
| Test status | |
| Simulation time | 81428217 ps |
| CPU time | 10.06 seconds |
| Started | Jul 31 07:46:24 PM PDT 24 |
| Finished | Jul 31 07:46:34 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-f7e4d323-0890-4d24-983a-5580e9f2d647 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483700676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random.1483700676 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_large_delays.197729375 |
| Short name | T2509 |
| Test name | |
| Test status | |
| Simulation time | 87827528359 ps |
| CPU time | 959.12 seconds |
| Started | Jul 31 07:46:24 PM PDT 24 |
| Finished | Jul 31 08:02:24 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-913385a7-85df-487b-8824-0f8d518eec8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197729375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.197729375 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_slow_rsp.1545320797 |
| Short name | T2070 |
| Test name | |
| Test status | |
| Simulation time | 19810526582 ps |
| CPU time | 315.96 seconds |
| Started | Jul 31 07:46:41 PM PDT 24 |
| Finished | Jul 31 07:51:57 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-e9d4246f-9a54-4b0c-ac3b-b8cd19cfd714 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545320797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.1545320797 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_zero_delays.101023824 |
| Short name | T1583 |
| Test name | |
| Test status | |
| Simulation time | 436872827 ps |
| CPU time | 34.66 seconds |
| Started | Jul 31 07:46:27 PM PDT 24 |
| Finished | Jul 31 07:47:01 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-5bc83e46-209d-4ba1-b41c-f5519e8c6b82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101023824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delay s.101023824 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_same_source.3170797405 |
| Short name | T2928 |
| Test name | |
| Test status | |
| Simulation time | 2045612618 ps |
| CPU time | 56.66 seconds |
| Started | Jul 31 07:46:35 PM PDT 24 |
| Finished | Jul 31 07:47:32 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-828fd01f-712d-497d-9f2b-88b87a2a166b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170797405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.3170797405 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke.3464197888 |
| Short name | T2868 |
| Test name | |
| Test status | |
| Simulation time | 206618016 ps |
| CPU time | 9.11 seconds |
| Started | Jul 31 07:46:21 PM PDT 24 |
| Finished | Jul 31 07:46:30 PM PDT 24 |
| Peak memory | 574556 kb |
| Host | smart-5627ba43-490d-48c5-9594-af3c826cfffa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464197888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.3464197888 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.4035995490 |
| Short name | T1566 |
| Test name | |
| Test status | |
| Simulation time | 7392938169 ps |
| CPU time | 73.45 seconds |
| Started | Jul 31 07:46:18 PM PDT 24 |
| Finished | Jul 31 07:47:31 PM PDT 24 |
| Peak memory | 574568 kb |
| Host | smart-a77d1c23-75a7-4207-bd35-b6da4a26c220 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035995490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.4035995490 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.3609977721 |
| Short name | T1478 |
| Test name | |
| Test status | |
| Simulation time | 6590843738 ps |
| CPU time | 112.73 seconds |
| Started | Jul 31 07:46:18 PM PDT 24 |
| Finished | Jul 31 07:48:11 PM PDT 24 |
| Peak memory | 573872 kb |
| Host | smart-ec152e69-387e-4eca-9ea8-5ddf5052b56f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609977721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.3609977721 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_zero_delays.3301548009 |
| Short name | T1434 |
| Test name | |
| Test status | |
| Simulation time | 35398933 ps |
| CPU time | 5.95 seconds |
| Started | Jul 31 07:46:19 PM PDT 24 |
| Finished | Jul 31 07:46:25 PM PDT 24 |
| Peak memory | 573816 kb |
| Host | smart-4085d0f4-2517-4d44-a9b8-5a94f085b0ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301548009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays .3301548009 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all.2075401406 |
| Short name | T2620 |
| Test name | |
| Test status | |
| Simulation time | 3886197926 ps |
| CPU time | 146.62 seconds |
| Started | Jul 31 07:46:31 PM PDT 24 |
| Finished | Jul 31 07:48:58 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-f7784ba8-e869-452b-91cf-54ac1117fca9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075401406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.2075401406 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.2114128934 |
| Short name | T1828 |
| Test name | |
| Test status | |
| Simulation time | 15143013487 ps |
| CPU time | 512.19 seconds |
| Started | Jul 31 07:46:41 PM PDT 24 |
| Finished | Jul 31 07:55:13 PM PDT 24 |
| Peak memory | 576792 kb |
| Host | smart-44b72f71-d444-4893-a574-6f2de1df8691 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114128934 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.2114128934 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.301970843 |
| Short name | T2922 |
| Test name | |
| Test status | |
| Simulation time | 261789403 ps |
| CPU time | 113.04 seconds |
| Started | Jul 31 07:46:41 PM PDT 24 |
| Finished | Jul 31 07:48:34 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-6b5f06a1-0e56-418a-b145-359bb6a6c0b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301970843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_w ith_rand_reset.301970843 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.3345472652 |
| Short name | T2203 |
| Test name | |
| Test status | |
| Simulation time | 9219339449 ps |
| CPU time | 390.33 seconds |
| Started | Jul 31 07:46:35 PM PDT 24 |
| Finished | Jul 31 07:53:06 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-bc52a7be-0efc-4e2e-b51d-37cf17412d42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345472652 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all _with_reset_error.3345472652 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_unmapped_addr.2108426199 |
| Short name | T2623 |
| Test name | |
| Test status | |
| Simulation time | 229315205 ps |
| CPU time | 11.03 seconds |
| Started | Jul 31 07:46:41 PM PDT 24 |
| Finished | Jul 31 07:46:52 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-c45d58d9-5abf-4913-9262-9b1974f531f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108426199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.2108426199 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device.2846917610 |
| Short name | T2011 |
| Test name | |
| Test status | |
| Simulation time | 2366925262 ps |
| CPU time | 97.33 seconds |
| Started | Jul 31 07:55:20 PM PDT 24 |
| Finished | Jul 31 07:56:58 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-60f84058-b691-4db2-946c-01b4c9c3fd85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846917610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device .2846917610 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.3618277889 |
| Short name | T2185 |
| Test name | |
| Test status | |
| Simulation time | 95324260307 ps |
| CPU time | 1768.42 seconds |
| Started | Jul 31 07:55:22 PM PDT 24 |
| Finished | Jul 31 08:24:51 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-c152b362-2977-491c-9fc4-f58d4523586b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618277889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_ device_slow_rsp.3618277889 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.609778321 |
| Short name | T2025 |
| Test name | |
| Test status | |
| Simulation time | 222892178 ps |
| CPU time | 11.74 seconds |
| Started | Jul 31 07:55:23 PM PDT 24 |
| Finished | Jul 31 07:55:35 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-8e934e11-c455-4300-af5d-cc794f81945d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609778321 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr .609778321 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_random.1181270871 |
| Short name | T2173 |
| Test name | |
| Test status | |
| Simulation time | 2349837110 ps |
| CPU time | 79.05 seconds |
| Started | Jul 31 07:55:22 PM PDT 24 |
| Finished | Jul 31 07:56:41 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-0f28ebf5-2d66-4267-90cd-242d1537ed69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181270871 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.1181270871 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random.1549322484 |
| Short name | T1723 |
| Test name | |
| Test status | |
| Simulation time | 2009161376 ps |
| CPU time | 74.23 seconds |
| Started | Jul 31 07:55:20 PM PDT 24 |
| Finished | Jul 31 07:56:34 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-ca84ff5e-213a-4e57-91bf-52fa6e73d793 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549322484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random.1549322484 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_large_delays.2971954332 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 80058681825 ps |
| CPU time | 927.26 seconds |
| Started | Jul 31 07:55:16 PM PDT 24 |
| Finished | Jul 31 08:10:44 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-30f92ccb-4185-4f6d-affe-1a4922597bf2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971954332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.2971954332 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_slow_rsp.2177153433 |
| Short name | T2733 |
| Test name | |
| Test status | |
| Simulation time | 29258267155 ps |
| CPU time | 516.22 seconds |
| Started | Jul 31 07:55:15 PM PDT 24 |
| Finished | Jul 31 08:03:51 PM PDT 24 |
| Peak memory | 576108 kb |
| Host | smart-b11355bf-fc80-499a-b6ad-40d54e598e1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177153433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.2177153433 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.2038235878 |
| Short name | T1675 |
| Test name | |
| Test status | |
| Simulation time | 491644230 ps |
| CPU time | 44.35 seconds |
| Started | Jul 31 07:55:21 PM PDT 24 |
| Finished | Jul 31 07:56:05 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-9c221c99-a507-4e10-b03d-3ae1f6058f0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038235878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_del ays.2038235878 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_same_source.9290969 |
| Short name | T2001 |
| Test name | |
| Test status | |
| Simulation time | 113409044 ps |
| CPU time | 11.86 seconds |
| Started | Jul 31 07:55:22 PM PDT 24 |
| Finished | Jul 31 07:55:34 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-18830b1b-caaa-4d34-8bc2-867a1b794dfa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9290969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.9290969 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke.3502174627 |
| Short name | T2879 |
| Test name | |
| Test status | |
| Simulation time | 192121454 ps |
| CPU time | 8.99 seconds |
| Started | Jul 31 07:55:17 PM PDT 24 |
| Finished | Jul 31 07:55:26 PM PDT 24 |
| Peak memory | 574512 kb |
| Host | smart-2479b9d1-c03b-40a7-8858-489b8b4a441c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502174627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.3502174627 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.198375031 |
| Short name | T2307 |
| Test name | |
| Test status | |
| Simulation time | 8110099127 ps |
| CPU time | 82.07 seconds |
| Started | Jul 31 07:55:16 PM PDT 24 |
| Finished | Jul 31 07:56:38 PM PDT 24 |
| Peak memory | 573908 kb |
| Host | smart-210c3929-dae6-4f29-a537-65cb54d404b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198375031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.198375031 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.884690877 |
| Short name | T2305 |
| Test name | |
| Test status | |
| Simulation time | 4714220917 ps |
| CPU time | 78.5 seconds |
| Started | Jul 31 07:55:16 PM PDT 24 |
| Finished | Jul 31 07:56:35 PM PDT 24 |
| Peak memory | 573852 kb |
| Host | smart-35ae4fb0-7323-4204-b51c-4b1f1f6af1ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884690877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.884690877 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_zero_delays.3651896900 |
| Short name | T1739 |
| Test name | |
| Test status | |
| Simulation time | 54195863 ps |
| CPU time | 6.67 seconds |
| Started | Jul 31 07:55:16 PM PDT 24 |
| Finished | Jul 31 07:55:22 PM PDT 24 |
| Peak memory | 574464 kb |
| Host | smart-3bb7431b-11c7-491c-85a7-06e4ae568bd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651896900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delay s.3651896900 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all.3699286055 |
| Short name | T2494 |
| Test name | |
| Test status | |
| Simulation time | 2397827523 ps |
| CPU time | 191.2 seconds |
| Started | Jul 31 07:55:23 PM PDT 24 |
| Finished | Jul 31 07:58:34 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-3c0c6394-20a3-4ec8-9a44-112c8821fa8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699286055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.3699286055 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.4036488034 |
| Short name | T2037 |
| Test name | |
| Test status | |
| Simulation time | 1634890965 ps |
| CPU time | 123.45 seconds |
| Started | Jul 31 07:55:26 PM PDT 24 |
| Finished | Jul 31 07:57:29 PM PDT 24 |
| Peak memory | 576100 kb |
| Host | smart-5ce4f07b-fbde-4c02-b235-8d5d8b02c1c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036488034 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.4036488034 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.355033341 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 192334519 ps |
| CPU time | 70.21 seconds |
| Started | Jul 31 07:55:22 PM PDT 24 |
| Finished | Jul 31 07:56:32 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-c9c7aa54-c95f-4fae-83d3-ac72f05b9b2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355033341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_ with_rand_reset.355033341 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.1599244724 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 6784883847 ps |
| CPU time | 403.43 seconds |
| Started | Jul 31 07:55:28 PM PDT 24 |
| Finished | Jul 31 08:02:11 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-04760050-9c4a-4d1d-9c7f-78f2e376ae48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599244724 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_al l_with_reset_error.1599244724 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_unmapped_addr.483244604 |
| Short name | T1757 |
| Test name | |
| Test status | |
| Simulation time | 164536456 ps |
| CPU time | 23 seconds |
| Started | Jul 31 07:55:21 PM PDT 24 |
| Finished | Jul 31 07:55:44 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-7512e117-79f7-45f5-aa58-a6b79883e1aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483244604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.483244604 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device.3065098323 |
| Short name | T2761 |
| Test name | |
| Test status | |
| Simulation time | 960025453 ps |
| CPU time | 75.1 seconds |
| Started | Jul 31 07:55:28 PM PDT 24 |
| Finished | Jul 31 07:56:43 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-4cd8704d-7378-45b0-af54-ea87a9078338 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065098323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device .3065098323 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.2777522723 |
| Short name | T2191 |
| Test name | |
| Test status | |
| Simulation time | 113737044656 ps |
| CPU time | 2144.77 seconds |
| Started | Jul 31 07:55:28 PM PDT 24 |
| Finished | Jul 31 08:31:13 PM PDT 24 |
| Peak memory | 576056 kb |
| Host | smart-794e4219-3c59-4b97-a767-8b2c3b6274ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777522723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_ device_slow_rsp.2777522723 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.3164378329 |
| Short name | T2682 |
| Test name | |
| Test status | |
| Simulation time | 176861505 ps |
| CPU time | 20.46 seconds |
| Started | Jul 31 07:55:33 PM PDT 24 |
| Finished | Jul 31 07:55:53 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-69c985f2-4a90-497e-b117-803742117675 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164378329 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_add r.3164378329 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_random.3368028827 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 1986779537 ps |
| CPU time | 65.72 seconds |
| Started | Jul 31 07:55:37 PM PDT 24 |
| Finished | Jul 31 07:56:43 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-e2b527a7-ab56-4929-8f1e-f40202cca317 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368028827 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.3368028827 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random.3170162480 |
| Short name | T2358 |
| Test name | |
| Test status | |
| Simulation time | 298040528 ps |
| CPU time | 26.51 seconds |
| Started | Jul 31 07:55:29 PM PDT 24 |
| Finished | Jul 31 07:55:55 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-97314c93-5532-4cf4-b42f-1d34201c2bba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170162480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random.3170162480 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_large_delays.2781382824 |
| Short name | T2820 |
| Test name | |
| Test status | |
| Simulation time | 54874642742 ps |
| CPU time | 588.48 seconds |
| Started | Jul 31 07:55:30 PM PDT 24 |
| Finished | Jul 31 08:05:19 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-e1f71643-5aac-4170-bb3b-9ae26af8fe20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781382824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.2781382824 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.2249583879 |
| Short name | T2041 |
| Test name | |
| Test status | |
| Simulation time | 49012344852 ps |
| CPU time | 882.27 seconds |
| Started | Jul 31 07:55:27 PM PDT 24 |
| Finished | Jul 31 08:10:10 PM PDT 24 |
| Peak memory | 576040 kb |
| Host | smart-af1a23de-5de9-4d57-8bf0-12734263c2b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249583879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.2249583879 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_zero_delays.2418981011 |
| Short name | T1819 |
| Test name | |
| Test status | |
| Simulation time | 182650288 ps |
| CPU time | 17.09 seconds |
| Started | Jul 31 07:55:29 PM PDT 24 |
| Finished | Jul 31 07:55:46 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-9d104937-908b-47ac-8c08-2e73a081d277 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418981011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_del ays.2418981011 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_same_source.3576172723 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 445960735 ps |
| CPU time | 31.75 seconds |
| Started | Jul 31 07:55:33 PM PDT 24 |
| Finished | Jul 31 07:56:05 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-27d26b49-6d54-41e6-a28a-c0365f1dc41c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576172723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.3576172723 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke.1047206864 |
| Short name | T2769 |
| Test name | |
| Test status | |
| Simulation time | 216184549 ps |
| CPU time | 9.47 seconds |
| Started | Jul 31 07:55:26 PM PDT 24 |
| Finished | Jul 31 07:55:36 PM PDT 24 |
| Peak memory | 573812 kb |
| Host | smart-78e8b9f8-bbd5-448a-8683-abd205431d02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047206864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.1047206864 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.1859164423 |
| Short name | T2694 |
| Test name | |
| Test status | |
| Simulation time | 9531152137 ps |
| CPU time | 101.3 seconds |
| Started | Jul 31 07:55:28 PM PDT 24 |
| Finished | Jul 31 07:57:09 PM PDT 24 |
| Peak memory | 574588 kb |
| Host | smart-f8008381-c73e-4bd2-921d-84960780b39d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859164423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.1859164423 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.2194068113 |
| Short name | T2335 |
| Test name | |
| Test status | |
| Simulation time | 5412258772 ps |
| CPU time | 88.82 seconds |
| Started | Jul 31 07:55:29 PM PDT 24 |
| Finished | Jul 31 07:56:58 PM PDT 24 |
| Peak memory | 573940 kb |
| Host | smart-e52b1e20-84ad-4f6e-8e9f-2494092ba7bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194068113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.2194068113 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_zero_delays.2618510922 |
| Short name | T2660 |
| Test name | |
| Test status | |
| Simulation time | 48698770 ps |
| CPU time | 5.96 seconds |
| Started | Jul 31 07:55:27 PM PDT 24 |
| Finished | Jul 31 07:55:34 PM PDT 24 |
| Peak memory | 573764 kb |
| Host | smart-4dd62826-77a3-4b49-8521-1ab83d5a4493 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618510922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delay s.2618510922 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all.3170296027 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 2776760177 ps |
| CPU time | 103.91 seconds |
| Started | Jul 31 07:55:35 PM PDT 24 |
| Finished | Jul 31 07:57:19 PM PDT 24 |
| Peak memory | 576188 kb |
| Host | smart-a100e69c-6f19-41ae-be02-5d68ac5a810b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170296027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.3170296027 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.2120736659 |
| Short name | T1668 |
| Test name | |
| Test status | |
| Simulation time | 955119668 ps |
| CPU time | 71.17 seconds |
| Started | Jul 31 07:55:34 PM PDT 24 |
| Finished | Jul 31 07:56:46 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-9c458694-1736-4190-9f22-3aa609621536 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120736659 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.2120736659 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.2022293474 |
| Short name | T2885 |
| Test name | |
| Test status | |
| Simulation time | 3724075727 ps |
| CPU time | 170.25 seconds |
| Started | Jul 31 07:55:34 PM PDT 24 |
| Finished | Jul 31 07:58:24 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-1a965096-a3ea-4873-96f1-40725da14c72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022293474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all _with_rand_reset.2022293474 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.1072029317 |
| Short name | T2149 |
| Test name | |
| Test status | |
| Simulation time | 10808250738 ps |
| CPU time | 973.41 seconds |
| Started | Jul 31 07:55:33 PM PDT 24 |
| Finished | Jul 31 08:11:46 PM PDT 24 |
| Peak memory | 596844 kb |
| Host | smart-8c8f79e3-7eb4-4be1-bf66-7c027556cc79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072029317 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_al l_with_reset_error.1072029317 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_unmapped_addr.3106129189 |
| Short name | T1651 |
| Test name | |
| Test status | |
| Simulation time | 166582261 ps |
| CPU time | 9.33 seconds |
| Started | Jul 31 07:55:36 PM PDT 24 |
| Finished | Jul 31 07:55:46 PM PDT 24 |
| Peak memory | 573928 kb |
| Host | smart-34ac5d7c-39ad-4f94-9401-d6b162d8cee4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106129189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.3106129189 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device.705841355 |
| Short name | T1529 |
| Test name | |
| Test status | |
| Simulation time | 1430229286 ps |
| CPU time | 67.72 seconds |
| Started | Jul 31 07:55:41 PM PDT 24 |
| Finished | Jul 31 07:56:49 PM PDT 24 |
| Peak memory | 576048 kb |
| Host | smart-5a6530d2-c293-4240-a644-055f79b13b94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705841355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device. 705841355 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.440895936 |
| Short name | T1537 |
| Test name | |
| Test status | |
| Simulation time | 79225860804 ps |
| CPU time | 1400.9 seconds |
| Started | Jul 31 07:55:43 PM PDT 24 |
| Finished | Jul 31 08:19:04 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-bd5fe0dd-7dac-42a0-8380-01f457d6161c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440895936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_d evice_slow_rsp.440895936 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.3156736712 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 126355947 ps |
| CPU time | 15.15 seconds |
| Started | Jul 31 07:55:46 PM PDT 24 |
| Finished | Jul 31 07:56:01 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-86c6b9c2-b7d6-44fa-be1d-5438f17be31b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156736712 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_add r.3156736712 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_random.1452823855 |
| Short name | T1982 |
| Test name | |
| Test status | |
| Simulation time | 678215905 ps |
| CPU time | 26.6 seconds |
| Started | Jul 31 07:55:42 PM PDT 24 |
| Finished | Jul 31 07:56:08 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-782991e2-1351-4b69-bdea-b5552b4580e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452823855 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.1452823855 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random.3417627580 |
| Short name | T2584 |
| Test name | |
| Test status | |
| Simulation time | 479592439 ps |
| CPU time | 34.65 seconds |
| Started | Jul 31 07:55:42 PM PDT 24 |
| Finished | Jul 31 07:56:17 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-c89cffb9-d58d-45f1-b686-0cf7bb222e0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417627580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random.3417627580 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_large_delays.2162664739 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 97940789746 ps |
| CPU time | 997.73 seconds |
| Started | Jul 31 07:55:41 PM PDT 24 |
| Finished | Jul 31 08:12:19 PM PDT 24 |
| Peak memory | 576060 kb |
| Host | smart-ca43a6f3-9bf6-453c-aedf-2a49f0c9afe6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162664739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.2162664739 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_slow_rsp.2273619701 |
| Short name | T2285 |
| Test name | |
| Test status | |
| Simulation time | 63301497051 ps |
| CPU time | 1038.82 seconds |
| Started | Jul 31 07:55:41 PM PDT 24 |
| Finished | Jul 31 08:13:01 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-44691ae3-d233-4032-9dd0-fe84562c20b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273619701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.2273619701 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_zero_delays.878053459 |
| Short name | T2337 |
| Test name | |
| Test status | |
| Simulation time | 93335008 ps |
| CPU time | 12.37 seconds |
| Started | Jul 31 07:55:41 PM PDT 24 |
| Finished | Jul 31 07:55:54 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-5c8e180d-60ec-4d4b-8182-7e44ac1923ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878053459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_dela ys.878053459 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_same_source.3534071065 |
| Short name | T2166 |
| Test name | |
| Test status | |
| Simulation time | 130768351 ps |
| CPU time | 6.69 seconds |
| Started | Jul 31 07:55:43 PM PDT 24 |
| Finished | Jul 31 07:55:50 PM PDT 24 |
| Peak memory | 574484 kb |
| Host | smart-db777920-7efb-4670-b161-05c4ae839290 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534071065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.3534071065 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke.3966394260 |
| Short name | T1397 |
| Test name | |
| Test status | |
| Simulation time | 190821294 ps |
| CPU time | 9.3 seconds |
| Started | Jul 31 07:55:34 PM PDT 24 |
| Finished | Jul 31 07:55:43 PM PDT 24 |
| Peak memory | 573788 kb |
| Host | smart-5092dc56-0adf-4602-9814-6612ba3a91f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966394260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.3966394260 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_large_delays.517637933 |
| Short name | T1764 |
| Test name | |
| Test status | |
| Simulation time | 7881660849 ps |
| CPU time | 86.53 seconds |
| Started | Jul 31 07:55:43 PM PDT 24 |
| Finished | Jul 31 07:57:09 PM PDT 24 |
| Peak memory | 574580 kb |
| Host | smart-631a2944-b676-470b-b539-351df2ddcf46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517637933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.517637933 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.154455882 |
| Short name | T1649 |
| Test name | |
| Test status | |
| Simulation time | 4364702550 ps |
| CPU time | 68.83 seconds |
| Started | Jul 31 07:55:41 PM PDT 24 |
| Finished | Jul 31 07:56:50 PM PDT 24 |
| Peak memory | 573908 kb |
| Host | smart-05276365-a11e-484f-b740-d1248e764d83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154455882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.154455882 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_zero_delays.1333040211 |
| Short name | T2163 |
| Test name | |
| Test status | |
| Simulation time | 42591400 ps |
| CPU time | 6.07 seconds |
| Started | Jul 31 07:55:42 PM PDT 24 |
| Finished | Jul 31 07:55:48 PM PDT 24 |
| Peak memory | 573792 kb |
| Host | smart-3079a067-00e7-4c5d-bb50-67d3f2045f88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333040211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delay s.1333040211 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all.2003647115 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 171919817 ps |
| CPU time | 15.96 seconds |
| Started | Jul 31 07:55:50 PM PDT 24 |
| Finished | Jul 31 07:56:06 PM PDT 24 |
| Peak memory | 576056 kb |
| Host | smart-c1348fe1-c93f-4494-94d8-b328e351d3ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003647115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.2003647115 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.1231169181 |
| Short name | T2080 |
| Test name | |
| Test status | |
| Simulation time | 5252809608 ps |
| CPU time | 197.79 seconds |
| Started | Jul 31 07:55:51 PM PDT 24 |
| Finished | Jul 31 07:59:09 PM PDT 24 |
| Peak memory | 576168 kb |
| Host | smart-7016fc16-1bf1-4cdc-a954-2631ec1b07f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231169181 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.1231169181 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.2315419176 |
| Short name | T1781 |
| Test name | |
| Test status | |
| Simulation time | 8909348521 ps |
| CPU time | 942.37 seconds |
| Started | Jul 31 07:55:50 PM PDT 24 |
| Finished | Jul 31 08:11:33 PM PDT 24 |
| Peak memory | 582232 kb |
| Host | smart-13307703-d67b-4fe1-9c1d-3ed4a0423b9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315419176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all _with_rand_reset.2315419176 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.1158183119 |
| Short name | T2918 |
| Test name | |
| Test status | |
| Simulation time | 819462380 ps |
| CPU time | 294.47 seconds |
| Started | Jul 31 07:55:47 PM PDT 24 |
| Finished | Jul 31 08:00:42 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-7bf2b55a-7308-4098-a2d6-cfd7339341ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158183119 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_al l_with_reset_error.1158183119 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_unmapped_addr.429686202 |
| Short name | T1692 |
| Test name | |
| Test status | |
| Simulation time | 487078876 ps |
| CPU time | 23.56 seconds |
| Started | Jul 31 07:55:49 PM PDT 24 |
| Finished | Jul 31 07:56:13 PM PDT 24 |
| Peak memory | 576048 kb |
| Host | smart-6a89a1de-8bce-4ef9-a2d2-ec5d143541c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429686202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.429686202 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device.82249246 |
| Short name | T1798 |
| Test name | |
| Test status | |
| Simulation time | 2861991450 ps |
| CPU time | 120.95 seconds |
| Started | Jul 31 07:55:54 PM PDT 24 |
| Finished | Jul 31 07:57:55 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-b3e8edd4-50fc-4321-81d6-6347d0721904 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82249246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.82249246 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.647664852 |
| Short name | T2424 |
| Test name | |
| Test status | |
| Simulation time | 19999203597 ps |
| CPU time | 318.88 seconds |
| Started | Jul 31 07:55:54 PM PDT 24 |
| Finished | Jul 31 08:01:13 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-370c7724-27af-4d1e-9a2e-84efaf9dded5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647664852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_d evice_slow_rsp.647664852 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.4259090729 |
| Short name | T2852 |
| Test name | |
| Test status | |
| Simulation time | 55965412 ps |
| CPU time | 8.38 seconds |
| Started | Jul 31 07:55:58 PM PDT 24 |
| Finished | Jul 31 07:56:07 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-c31b0bea-7945-4bdb-a5cb-f0c1e53623a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259090729 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_add r.4259090729 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_random.2065301993 |
| Short name | T1454 |
| Test name | |
| Test status | |
| Simulation time | 61035137 ps |
| CPU time | 5.75 seconds |
| Started | Jul 31 07:56:00 PM PDT 24 |
| Finished | Jul 31 07:56:05 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-b20193b7-67d2-4d60-a7e6-3a94621e94c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065301993 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.2065301993 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random.3804333791 |
| Short name | T2822 |
| Test name | |
| Test status | |
| Simulation time | 811764394 ps |
| CPU time | 31.85 seconds |
| Started | Jul 31 07:55:47 PM PDT 24 |
| Finished | Jul 31 07:56:19 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-2deaa164-8322-4849-b451-a88eed3d2422 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804333791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random.3804333791 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_large_delays.1224130571 |
| Short name | T2271 |
| Test name | |
| Test status | |
| Simulation time | 5790179343 ps |
| CPU time | 61.34 seconds |
| Started | Jul 31 07:55:47 PM PDT 24 |
| Finished | Jul 31 07:56:48 PM PDT 24 |
| Peak memory | 573856 kb |
| Host | smart-8c33d4c3-13e3-41ad-9546-a9d3c683a65a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224130571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.1224130571 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_slow_rsp.1270934532 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 9985887587 ps |
| CPU time | 159.17 seconds |
| Started | Jul 31 07:55:53 PM PDT 24 |
| Finished | Jul 31 07:58:33 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-3dbbdedd-3526-4373-bd79-55d4a4c7792a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270934532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.1270934532 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_zero_delays.3027102951 |
| Short name | T2674 |
| Test name | |
| Test status | |
| Simulation time | 267747054 ps |
| CPU time | 25.66 seconds |
| Started | Jul 31 07:55:47 PM PDT 24 |
| Finished | Jul 31 07:56:13 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-5c6905e0-fe7f-47d9-a88b-e440934d911c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027102951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_del ays.3027102951 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_same_source.205205445 |
| Short name | T2306 |
| Test name | |
| Test status | |
| Simulation time | 1333327501 ps |
| CPU time | 41.28 seconds |
| Started | Jul 31 07:55:57 PM PDT 24 |
| Finished | Jul 31 07:56:38 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-69a32434-69b4-4f63-bce3-cde664fa5860 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205205445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.205205445 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke.2549370198 |
| Short name | T2183 |
| Test name | |
| Test status | |
| Simulation time | 51686930 ps |
| CPU time | 6.95 seconds |
| Started | Jul 31 07:55:46 PM PDT 24 |
| Finished | Jul 31 07:55:53 PM PDT 24 |
| Peak memory | 574584 kb |
| Host | smart-04e8504f-69ef-44cc-a1c4-4b0e8bbae05d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549370198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.2549370198 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.1813763690 |
| Short name | T1625 |
| Test name | |
| Test status | |
| Simulation time | 6660716124 ps |
| CPU time | 70.08 seconds |
| Started | Jul 31 07:55:48 PM PDT 24 |
| Finished | Jul 31 07:56:58 PM PDT 24 |
| Peak memory | 573932 kb |
| Host | smart-787b6241-b4ba-448d-84a8-99015fb727f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813763690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.1813763690 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.65982301 |
| Short name | T2142 |
| Test name | |
| Test status | |
| Simulation time | 5174213757 ps |
| CPU time | 86.18 seconds |
| Started | Jul 31 07:55:47 PM PDT 24 |
| Finished | Jul 31 07:57:13 PM PDT 24 |
| Peak memory | 573932 kb |
| Host | smart-65c00b57-83c1-4339-9dda-3e6cd8670fc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65982301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.65982301 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_zero_delays.3360158080 |
| Short name | T2596 |
| Test name | |
| Test status | |
| Simulation time | 49560932 ps |
| CPU time | 7 seconds |
| Started | Jul 31 07:55:47 PM PDT 24 |
| Finished | Jul 31 07:55:54 PM PDT 24 |
| Peak memory | 574460 kb |
| Host | smart-c915dc0c-17bf-4247-8a52-828051717241 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360158080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delay s.3360158080 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all.3475019177 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 840495385 ps |
| CPU time | 73.71 seconds |
| Started | Jul 31 07:56:00 PM PDT 24 |
| Finished | Jul 31 07:57:14 PM PDT 24 |
| Peak memory | 576124 kb |
| Host | smart-7d34d7dc-1fb5-4726-8b32-e6a18926c95f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475019177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.3475019177 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.2199600814 |
| Short name | T2375 |
| Test name | |
| Test status | |
| Simulation time | 2184060017 ps |
| CPU time | 165.33 seconds |
| Started | Jul 31 07:55:58 PM PDT 24 |
| Finished | Jul 31 07:58:43 PM PDT 24 |
| Peak memory | 576160 kb |
| Host | smart-2cdc18b2-291a-49f8-8c69-c72017507adc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199600814 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.2199600814 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.3879265117 |
| Short name | T2117 |
| Test name | |
| Test status | |
| Simulation time | 1550618899 ps |
| CPU time | 148.97 seconds |
| Started | Jul 31 07:56:01 PM PDT 24 |
| Finished | Jul 31 07:58:30 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-357be56c-e613-4e91-b903-c19a9e570eed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879265117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all _with_rand_reset.3879265117 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.3345368579 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 4888162494 ps |
| CPU time | 350.97 seconds |
| Started | Jul 31 07:55:59 PM PDT 24 |
| Finished | Jul 31 08:01:50 PM PDT 24 |
| Peak memory | 576804 kb |
| Host | smart-86e9a4d7-3b30-49de-b80d-cea01f84d4b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345368579 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_al l_with_reset_error.3345368579 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_unmapped_addr.1103980303 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 217883890 ps |
| CPU time | 24.85 seconds |
| Started | Jul 31 07:55:59 PM PDT 24 |
| Finished | Jul 31 07:56:24 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-ad583729-fc70-4197-aabd-528cb75d051e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103980303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.1103980303 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device.2370016881 |
| Short name | T2664 |
| Test name | |
| Test status | |
| Simulation time | 345389978 ps |
| CPU time | 27.27 seconds |
| Started | Jul 31 07:56:05 PM PDT 24 |
| Finished | Jul 31 07:56:32 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-ecd92fb4-2a3a-4b8d-bc67-39af79bb7825 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370016881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device .2370016881 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.1694994048 |
| Short name | T2730 |
| Test name | |
| Test status | |
| Simulation time | 118623385331 ps |
| CPU time | 2182.17 seconds |
| Started | Jul 31 07:56:14 PM PDT 24 |
| Finished | Jul 31 08:32:36 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-3323a6fb-b0e5-4fd0-a288-50ef7f4c9234 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694994048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_ device_slow_rsp.1694994048 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.858119429 |
| Short name | T2425 |
| Test name | |
| Test status | |
| Simulation time | 1000846357 ps |
| CPU time | 39.03 seconds |
| Started | Jul 31 07:56:11 PM PDT 24 |
| Finished | Jul 31 07:56:50 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-4ae471e0-6ca1-4d36-88f5-b4b49d3b3d26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858119429 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr .858119429 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_random.204831754 |
| Short name | T2925 |
| Test name | |
| Test status | |
| Simulation time | 2390166289 ps |
| CPU time | 87.98 seconds |
| Started | Jul 31 07:56:12 PM PDT 24 |
| Finished | Jul 31 07:57:40 PM PDT 24 |
| Peak memory | 576024 kb |
| Host | smart-81bdaea8-73be-4d30-ace9-09d587849dce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204831754 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.204831754 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random.2683817453 |
| Short name | T2907 |
| Test name | |
| Test status | |
| Simulation time | 391018072 ps |
| CPU time | 35.93 seconds |
| Started | Jul 31 07:56:08 PM PDT 24 |
| Finished | Jul 31 07:56:44 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-3e267edf-fcde-4369-9f78-9791b2739bb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683817453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random.2683817453 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_large_delays.1495224903 |
| Short name | T2467 |
| Test name | |
| Test status | |
| Simulation time | 43716270421 ps |
| CPU time | 457.9 seconds |
| Started | Jul 31 07:56:06 PM PDT 24 |
| Finished | Jul 31 08:03:44 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-1b0cf841-95bb-47dc-b478-6307ece38e84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495224903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.1495224903 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_slow_rsp.4130791228 |
| Short name | T2716 |
| Test name | |
| Test status | |
| Simulation time | 33062645271 ps |
| CPU time | 578.9 seconds |
| Started | Jul 31 07:56:10 PM PDT 24 |
| Finished | Jul 31 08:05:49 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-76fb2972-861e-4160-b68a-3f6a14819203 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130791228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.4130791228 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_zero_delays.2231955880 |
| Short name | T2014 |
| Test name | |
| Test status | |
| Simulation time | 136008551 ps |
| CPU time | 15.81 seconds |
| Started | Jul 31 07:56:05 PM PDT 24 |
| Finished | Jul 31 07:56:21 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-a7f11a93-40d4-494b-a554-19c2d103e534 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231955880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_del ays.2231955880 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_same_source.1835612057 |
| Short name | T2282 |
| Test name | |
| Test status | |
| Simulation time | 512775868 ps |
| CPU time | 18.13 seconds |
| Started | Jul 31 07:56:13 PM PDT 24 |
| Finished | Jul 31 07:56:31 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-1360031a-83bd-48a0-9310-fdd4fa7b578b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835612057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.1835612057 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke.308794853 |
| Short name | T1492 |
| Test name | |
| Test status | |
| Simulation time | 189119748 ps |
| CPU time | 8.85 seconds |
| Started | Jul 31 07:56:04 PM PDT 24 |
| Finished | Jul 31 07:56:13 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-392d80e8-c554-44a6-b7ed-e4f03543292a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308794853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.308794853 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_large_delays.712527345 |
| Short name | T2906 |
| Test name | |
| Test status | |
| Simulation time | 8887616982 ps |
| CPU time | 88.67 seconds |
| Started | Jul 31 07:56:05 PM PDT 24 |
| Finished | Jul 31 07:57:34 PM PDT 24 |
| Peak memory | 573932 kb |
| Host | smart-e7d3e7d6-01cb-42a8-9923-7919fa387253 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712527345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.712527345 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.267458921 |
| Short name | T2120 |
| Test name | |
| Test status | |
| Simulation time | 5761990656 ps |
| CPU time | 105.6 seconds |
| Started | Jul 31 07:56:08 PM PDT 24 |
| Finished | Jul 31 07:57:54 PM PDT 24 |
| Peak memory | 574440 kb |
| Host | smart-517862aa-77a0-4024-969b-6314e4a2bd70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267458921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.267458921 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_zero_delays.191778419 |
| Short name | T2010 |
| Test name | |
| Test status | |
| Simulation time | 47029459 ps |
| CPU time | 6.42 seconds |
| Started | Jul 31 07:56:11 PM PDT 24 |
| Finished | Jul 31 07:56:17 PM PDT 24 |
| Peak memory | 574472 kb |
| Host | smart-d66453ae-391d-4ff3-9e11-0a5bea44961a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191778419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays .191778419 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all.351987583 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 10443493661 ps |
| CPU time | 328.54 seconds |
| Started | Jul 31 07:56:13 PM PDT 24 |
| Finished | Jul 31 08:01:42 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-f519ae73-2eea-4e19-897f-fdc4efb3c154 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351987583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.351987583 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.2576571057 |
| Short name | T1596 |
| Test name | |
| Test status | |
| Simulation time | 7280525467 ps |
| CPU time | 270.25 seconds |
| Started | Jul 31 07:56:13 PM PDT 24 |
| Finished | Jul 31 08:00:44 PM PDT 24 |
| Peak memory | 576068 kb |
| Host | smart-9cd68f34-bd47-45a3-8717-9521f21b9825 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576571057 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.2576571057 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.2294835716 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 2450999497 ps |
| CPU time | 504.06 seconds |
| Started | Jul 31 07:56:12 PM PDT 24 |
| Finished | Jul 31 08:04:37 PM PDT 24 |
| Peak memory | 576796 kb |
| Host | smart-5ae168ec-3810-4d00-9df9-0fad269be98b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294835716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all _with_rand_reset.2294835716 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.3233622603 |
| Short name | T2751 |
| Test name | |
| Test status | |
| Simulation time | 3349494023 ps |
| CPU time | 120.64 seconds |
| Started | Jul 31 07:56:11 PM PDT 24 |
| Finished | Jul 31 07:58:12 PM PDT 24 |
| Peak memory | 576440 kb |
| Host | smart-8a0810b5-cca3-465d-af42-b398c56adc25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233622603 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_al l_with_reset_error.3233622603 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_unmapped_addr.3199736331 |
| Short name | T2705 |
| Test name | |
| Test status | |
| Simulation time | 152755000 ps |
| CPU time | 19.99 seconds |
| Started | Jul 31 07:56:13 PM PDT 24 |
| Finished | Jul 31 07:56:33 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-e6797302-97d1-4aa7-a91f-7519b6f5e460 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199736331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.3199736331 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device.2552220170 |
| Short name | T2905 |
| Test name | |
| Test status | |
| Simulation time | 651092765 ps |
| CPU time | 57.94 seconds |
| Started | Jul 31 07:56:19 PM PDT 24 |
| Finished | Jul 31 07:57:17 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-a39e73f8-5c08-4a6f-8428-98a451a1c187 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552220170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device .2552220170 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.1496813556 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 126746555027 ps |
| CPU time | 2213.61 seconds |
| Started | Jul 31 07:56:17 PM PDT 24 |
| Finished | Jul 31 08:33:11 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-65d01650-c4fb-4755-ad30-763431fc1616 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496813556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_ device_slow_rsp.1496813556 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.3281374800 |
| Short name | T2661 |
| Test name | |
| Test status | |
| Simulation time | 1282886950 ps |
| CPU time | 48.26 seconds |
| Started | Jul 31 07:56:16 PM PDT 24 |
| Finished | Jul 31 07:57:04 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-582a6680-1fc5-4518-baec-2f6b0c50b191 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281374800 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_add r.3281374800 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_random.1717404308 |
| Short name | T1986 |
| Test name | |
| Test status | |
| Simulation time | 2089589734 ps |
| CPU time | 65.25 seconds |
| Started | Jul 31 07:56:17 PM PDT 24 |
| Finished | Jul 31 07:57:22 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-492ac92a-9d72-41af-b8e0-00e36cd2ea8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717404308 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.1717404308 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random.552814335 |
| Short name | T2932 |
| Test name | |
| Test status | |
| Simulation time | 422183237 ps |
| CPU time | 33.05 seconds |
| Started | Jul 31 07:56:17 PM PDT 24 |
| Finished | Jul 31 07:56:50 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-2d73c182-ef72-4cf4-9b83-f9e0c66a68c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552814335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random.552814335 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_large_delays.3532457870 |
| Short name | T2913 |
| Test name | |
| Test status | |
| Simulation time | 63712614373 ps |
| CPU time | 633.11 seconds |
| Started | Jul 31 07:56:19 PM PDT 24 |
| Finished | Jul 31 08:06:52 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-f0db5ad9-63d2-488b-93a5-349366411e61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532457870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.3532457870 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.1489514098 |
| Short name | T2512 |
| Test name | |
| Test status | |
| Simulation time | 18783245114 ps |
| CPU time | 314.05 seconds |
| Started | Jul 31 07:56:19 PM PDT 24 |
| Finished | Jul 31 08:01:33 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-2c83f16b-fe95-4f27-924c-ba4a1072a09c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489514098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.1489514098 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_zero_delays.621253710 |
| Short name | T1772 |
| Test name | |
| Test status | |
| Simulation time | 284289297 ps |
| CPU time | 23 seconds |
| Started | Jul 31 07:56:17 PM PDT 24 |
| Finished | Jul 31 07:56:40 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-b945b59c-80dd-43a2-891d-2836861c28fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621253710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_dela ys.621253710 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_same_source.1677699253 |
| Short name | T2466 |
| Test name | |
| Test status | |
| Simulation time | 155581432 ps |
| CPU time | 7.7 seconds |
| Started | Jul 31 07:56:17 PM PDT 24 |
| Finished | Jul 31 07:56:24 PM PDT 24 |
| Peak memory | 573900 kb |
| Host | smart-75fae1e1-f49c-4404-965a-1c01d19be9b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677699253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.1677699253 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke.2318034181 |
| Short name | T1466 |
| Test name | |
| Test status | |
| Simulation time | 48715044 ps |
| CPU time | 6.26 seconds |
| Started | Jul 31 07:56:09 PM PDT 24 |
| Finished | Jul 31 07:56:16 PM PDT 24 |
| Peak memory | 574464 kb |
| Host | smart-775c2335-4cad-4601-8837-9c5b30d08af1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318034181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.2318034181 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_large_delays.1487595932 |
| Short name | T1813 |
| Test name | |
| Test status | |
| Simulation time | 7587255026 ps |
| CPU time | 76.89 seconds |
| Started | Jul 31 07:56:20 PM PDT 24 |
| Finished | Jul 31 07:57:37 PM PDT 24 |
| Peak memory | 573872 kb |
| Host | smart-1a41dd2b-0be9-487b-97ab-716bb745c566 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487595932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.1487595932 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.332174661 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 3482727718 ps |
| CPU time | 60.23 seconds |
| Started | Jul 31 07:56:18 PM PDT 24 |
| Finished | Jul 31 07:57:18 PM PDT 24 |
| Peak memory | 574536 kb |
| Host | smart-4b41ac54-fc11-4798-ab88-2c37e29e060f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332174661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.332174661 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_zero_delays.3005437711 |
| Short name | T1390 |
| Test name | |
| Test status | |
| Simulation time | 49071986 ps |
| CPU time | 6.68 seconds |
| Started | Jul 31 07:56:18 PM PDT 24 |
| Finished | Jul 31 07:56:24 PM PDT 24 |
| Peak memory | 573824 kb |
| Host | smart-98e6cb41-67af-4d1d-83d1-a6541840f801 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005437711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delay s.3005437711 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all.796787481 |
| Short name | T2537 |
| Test name | |
| Test status | |
| Simulation time | 1371995600 ps |
| CPU time | 124.57 seconds |
| Started | Jul 31 07:56:19 PM PDT 24 |
| Finished | Jul 31 07:58:24 PM PDT 24 |
| Peak memory | 576356 kb |
| Host | smart-ba0e216e-cd0e-4163-86fe-47e9aaf18fe5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796787481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.796787481 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.3729983369 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 2722115853 ps |
| CPU time | 181.76 seconds |
| Started | Jul 31 07:56:22 PM PDT 24 |
| Finished | Jul 31 07:59:23 PM PDT 24 |
| Peak memory | 576156 kb |
| Host | smart-e6c9901f-895d-40fa-a4f1-7bfe2d321f4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729983369 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.3729983369 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.4121332029 |
| Short name | T1929 |
| Test name | |
| Test status | |
| Simulation time | 654879350 ps |
| CPU time | 306.55 seconds |
| Started | Jul 31 07:56:17 PM PDT 24 |
| Finished | Jul 31 08:01:24 PM PDT 24 |
| Peak memory | 576652 kb |
| Host | smart-170f7691-a442-446a-a700-522202a64592 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121332029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all _with_rand_reset.4121332029 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.3000262316 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 820438099 ps |
| CPU time | 163.34 seconds |
| Started | Jul 31 07:56:24 PM PDT 24 |
| Finished | Jul 31 07:59:07 PM PDT 24 |
| Peak memory | 576748 kb |
| Host | smart-5c95e085-2ec1-43c0-9c57-da88c0c47aed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000262316 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_al l_with_reset_error.3000262316 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_unmapped_addr.599090015 |
| Short name | T1445 |
| Test name | |
| Test status | |
| Simulation time | 48136646 ps |
| CPU time | 7.96 seconds |
| Started | Jul 31 07:56:17 PM PDT 24 |
| Finished | Jul 31 07:56:25 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-9e0fcc8d-d353-4c4e-9633-d9f1659be37a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599090015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.599090015 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device.62851477 |
| Short name | T1889 |
| Test name | |
| Test status | |
| Simulation time | 327265941 ps |
| CPU time | 31.4 seconds |
| Started | Jul 31 07:56:29 PM PDT 24 |
| Finished | Jul 31 07:57:00 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-f1dfeb57-d7e4-49e6-9dc3-7d388575a4a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62851477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.62851477 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.236294296 |
| Short name | T2899 |
| Test name | |
| Test status | |
| Simulation time | 109559521277 ps |
| CPU time | 2091.16 seconds |
| Started | Jul 31 07:56:28 PM PDT 24 |
| Finished | Jul 31 08:31:20 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-21f2733c-90ce-40d0-ac30-99edfd2b13ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236294296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_d evice_slow_rsp.236294296 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.1824230347 |
| Short name | T2513 |
| Test name | |
| Test status | |
| Simulation time | 972070399 ps |
| CPU time | 38.11 seconds |
| Started | Jul 31 07:56:36 PM PDT 24 |
| Finished | Jul 31 07:57:14 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-76903f48-e728-4922-9cae-9acac6d18733 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824230347 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_add r.1824230347 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_random.4102751721 |
| Short name | T1457 |
| Test name | |
| Test status | |
| Simulation time | 254753765 ps |
| CPU time | 21.64 seconds |
| Started | Jul 31 07:56:29 PM PDT 24 |
| Finished | Jul 31 07:56:50 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-1192e229-4e46-4308-8343-534675568ff2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102751721 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.4102751721 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random.1360554623 |
| Short name | T2432 |
| Test name | |
| Test status | |
| Simulation time | 225063055 ps |
| CPU time | 20.7 seconds |
| Started | Jul 31 07:56:29 PM PDT 24 |
| Finished | Jul 31 07:56:50 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-232d822f-db53-4842-ae4c-26f3e44dc2e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360554623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random.1360554623 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_large_delays.3996457064 |
| Short name | T2627 |
| Test name | |
| Test status | |
| Simulation time | 54683230772 ps |
| CPU time | 560.29 seconds |
| Started | Jul 31 07:56:31 PM PDT 24 |
| Finished | Jul 31 08:05:51 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-a6010b43-8111-4f9c-b5b5-aa29fc6ad7a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996457064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.3996457064 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_slow_rsp.3197711374 |
| Short name | T1623 |
| Test name | |
| Test status | |
| Simulation time | 46033948165 ps |
| CPU time | 774.21 seconds |
| Started | Jul 31 07:56:28 PM PDT 24 |
| Finished | Jul 31 08:09:22 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-1ecc23d1-5f77-44a0-a60f-182ae5e43220 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197711374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.3197711374 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_zero_delays.3009124222 |
| Short name | T2074 |
| Test name | |
| Test status | |
| Simulation time | 489127107 ps |
| CPU time | 41.73 seconds |
| Started | Jul 31 07:56:29 PM PDT 24 |
| Finished | Jul 31 07:57:11 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-d7396cb2-e028-4ba4-9ee3-31c7190c6fd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009124222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_del ays.3009124222 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_same_source.763082183 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 407732143 ps |
| CPU time | 25.96 seconds |
| Started | Jul 31 07:56:30 PM PDT 24 |
| Finished | Jul 31 07:56:56 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-a05c5a5e-5a31-4770-a2e9-38a06bf75134 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763082183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.763082183 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke.371500139 |
| Short name | T2656 |
| Test name | |
| Test status | |
| Simulation time | 230263535 ps |
| CPU time | 10.06 seconds |
| Started | Jul 31 07:56:25 PM PDT 24 |
| Finished | Jul 31 07:56:35 PM PDT 24 |
| Peak memory | 574512 kb |
| Host | smart-2cc65035-ced5-4945-ba92-d1be70c498e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371500139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.371500139 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_large_delays.2895486940 |
| Short name | T1443 |
| Test name | |
| Test status | |
| Simulation time | 9566078773 ps |
| CPU time | 97.26 seconds |
| Started | Jul 31 07:56:24 PM PDT 24 |
| Finished | Jul 31 07:58:01 PM PDT 24 |
| Peak memory | 573844 kb |
| Host | smart-c8468305-e65a-4257-a758-864553d43380 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895486940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.2895486940 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.2727841737 |
| Short name | T2055 |
| Test name | |
| Test status | |
| Simulation time | 3133648006 ps |
| CPU time | 53.2 seconds |
| Started | Jul 31 07:56:31 PM PDT 24 |
| Finished | Jul 31 07:57:24 PM PDT 24 |
| Peak memory | 573792 kb |
| Host | smart-458849b9-22b3-497b-9673-fd946bd2cd6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727841737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.2727841737 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_zero_delays.1119531038 |
| Short name | T2659 |
| Test name | |
| Test status | |
| Simulation time | 46229504 ps |
| CPU time | 6.51 seconds |
| Started | Jul 31 07:56:24 PM PDT 24 |
| Finished | Jul 31 07:56:30 PM PDT 24 |
| Peak memory | 573904 kb |
| Host | smart-b815f50a-bd05-4ee2-9b66-f5323d4f50be |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119531038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delay s.1119531038 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all.2322064161 |
| Short name | T2478 |
| Test name | |
| Test status | |
| Simulation time | 2446457053 ps |
| CPU time | 195.75 seconds |
| Started | Jul 31 07:56:35 PM PDT 24 |
| Finished | Jul 31 07:59:51 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-a7f73f2f-d1d1-4095-9451-279b0a0ce199 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322064161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.2322064161 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.2704805117 |
| Short name | T2715 |
| Test name | |
| Test status | |
| Simulation time | 4703995820 ps |
| CPU time | 315.93 seconds |
| Started | Jul 31 07:56:35 PM PDT 24 |
| Finished | Jul 31 08:01:52 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-2e9abf60-2dc0-47d3-ad03-61c24e8f34d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704805117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all _with_rand_reset.2704805117 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.2712707291 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 2752532914 ps |
| CPU time | 285.44 seconds |
| Started | Jul 31 07:56:37 PM PDT 24 |
| Finished | Jul 31 08:01:22 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-e9a695be-9ce9-45b3-b359-5da0d9c73a0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712707291 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_al l_with_reset_error.2712707291 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_unmapped_addr.4046600681 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 366019275 ps |
| CPU time | 15.39 seconds |
| Started | Jul 31 07:56:28 PM PDT 24 |
| Finished | Jul 31 07:56:43 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-8ca20a68-9901-45de-bd45-bfc4b457422a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046600681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.4046600681 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device.973073033 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 467276143 ps |
| CPU time | 38.35 seconds |
| Started | Jul 31 07:56:42 PM PDT 24 |
| Finished | Jul 31 07:57:21 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-c6419b3f-b551-417c-b559-02ab16a9bd8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973073033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device. 973073033 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.86714520 |
| Short name | T2030 |
| Test name | |
| Test status | |
| Simulation time | 22526930987 ps |
| CPU time | 384.12 seconds |
| Started | Jul 31 07:56:40 PM PDT 24 |
| Finished | Jul 31 08:03:05 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-928545b8-f59a-435a-8bdb-e0e17cbb591d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86714520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_de vice_slow_rsp.86714520 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.105300021 |
| Short name | T2309 |
| Test name | |
| Test status | |
| Simulation time | 864944396 ps |
| CPU time | 33.95 seconds |
| Started | Jul 31 07:56:47 PM PDT 24 |
| Finished | Jul 31 07:57:21 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-f5139cb5-8bc5-437d-9f43-4883d28b5257 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105300021 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr .105300021 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_random.483075505 |
| Short name | T2851 |
| Test name | |
| Test status | |
| Simulation time | 137879445 ps |
| CPU time | 8.03 seconds |
| Started | Jul 31 07:56:39 PM PDT 24 |
| Finished | Jul 31 07:56:47 PM PDT 24 |
| Peak memory | 573804 kb |
| Host | smart-8c6d1ad7-7082-47ac-af14-ae4151b4e158 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483075505 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.483075505 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random.3203133830 |
| Short name | T2578 |
| Test name | |
| Test status | |
| Simulation time | 1712741890 ps |
| CPU time | 59.48 seconds |
| Started | Jul 31 07:56:37 PM PDT 24 |
| Finished | Jul 31 07:57:37 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-76a64ead-a6f4-40e4-8fe3-4ce1012848d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203133830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random.3203133830 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_large_delays.2205004437 |
| Short name | T1998 |
| Test name | |
| Test status | |
| Simulation time | 104512911722 ps |
| CPU time | 1199 seconds |
| Started | Jul 31 07:56:41 PM PDT 24 |
| Finished | Jul 31 08:16:40 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-382fe6ac-3bf9-49e1-89c7-28f7f616198f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205004437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.2205004437 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_slow_rsp.1170455010 |
| Short name | T2695 |
| Test name | |
| Test status | |
| Simulation time | 47148294824 ps |
| CPU time | 856.44 seconds |
| Started | Jul 31 07:56:40 PM PDT 24 |
| Finished | Jul 31 08:10:57 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-69777a65-550a-4004-bedc-5a93a25f7d04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170455010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.1170455010 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_zero_delays.3392464693 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 163617919 ps |
| CPU time | 15.48 seconds |
| Started | Jul 31 07:56:42 PM PDT 24 |
| Finished | Jul 31 07:56:58 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-a6bee1a0-0cb2-4375-ae68-6f5fac99df22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392464693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_del ays.3392464693 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_same_source.1019887178 |
| Short name | T2748 |
| Test name | |
| Test status | |
| Simulation time | 1542260177 ps |
| CPU time | 47.96 seconds |
| Started | Jul 31 07:56:39 PM PDT 24 |
| Finished | Jul 31 07:57:27 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-bba6592b-6521-429a-add4-fc23bcd77d30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019887178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.1019887178 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke.2236425235 |
| Short name | T1620 |
| Test name | |
| Test status | |
| Simulation time | 121342812 ps |
| CPU time | 6.71 seconds |
| Started | Jul 31 07:56:37 PM PDT 24 |
| Finished | Jul 31 07:56:44 PM PDT 24 |
| Peak memory | 573776 kb |
| Host | smart-5ff5d014-3149-4767-b79d-402ff6d2b964 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236425235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.2236425235 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_large_delays.3260538863 |
| Short name | T2200 |
| Test name | |
| Test status | |
| Simulation time | 6342976470 ps |
| CPU time | 64.03 seconds |
| Started | Jul 31 07:56:34 PM PDT 24 |
| Finished | Jul 31 07:57:39 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-a43bd5df-4666-4729-b9d1-8b267b859d89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260538863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.3260538863 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.3433759240 |
| Short name | T1693 |
| Test name | |
| Test status | |
| Simulation time | 5548716587 ps |
| CPU time | 95.34 seconds |
| Started | Jul 31 07:56:34 PM PDT 24 |
| Finished | Jul 31 07:58:10 PM PDT 24 |
| Peak memory | 574540 kb |
| Host | smart-42b07561-bbb6-4d00-bc42-1951fb2a9cf5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433759240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.3433759240 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_zero_delays.3775128216 |
| Short name | T2348 |
| Test name | |
| Test status | |
| Simulation time | 47987333 ps |
| CPU time | 5.76 seconds |
| Started | Jul 31 07:56:34 PM PDT 24 |
| Finished | Jul 31 07:56:40 PM PDT 24 |
| Peak memory | 573768 kb |
| Host | smart-d14bd465-dcbc-4bad-8f35-521ba4afc83b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775128216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delay s.3775128216 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all.3056359723 |
| Short name | T1844 |
| Test name | |
| Test status | |
| Simulation time | 3933623878 ps |
| CPU time | 140.8 seconds |
| Started | Jul 31 07:56:47 PM PDT 24 |
| Finished | Jul 31 07:59:08 PM PDT 24 |
| Peak memory | 576748 kb |
| Host | smart-5481405d-3c93-4d03-8492-9bccb905567b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056359723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.3056359723 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_error.39878231 |
| Short name | T2672 |
| Test name | |
| Test status | |
| Simulation time | 5827055013 ps |
| CPU time | 174.59 seconds |
| Started | Jul 31 07:56:53 PM PDT 24 |
| Finished | Jul 31 07:59:48 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-fef46786-cea7-411b-8e23-37c92dc85776 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39878231 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.39878231 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.787130335 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 1094135303 ps |
| CPU time | 297.13 seconds |
| Started | Jul 31 07:56:53 PM PDT 24 |
| Finished | Jul 31 08:01:50 PM PDT 24 |
| Peak memory | 576656 kb |
| Host | smart-f6b3128e-c9d2-4b6d-990b-92fbc9ab48b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787130335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_ with_rand_reset.787130335 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.1799001235 |
| Short name | T1607 |
| Test name | |
| Test status | |
| Simulation time | 288234825 ps |
| CPU time | 98.07 seconds |
| Started | Jul 31 07:56:48 PM PDT 24 |
| Finished | Jul 31 07:58:26 PM PDT 24 |
| Peak memory | 576704 kb |
| Host | smart-0d4034be-e22a-49c9-a542-eac28d5c75bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799001235 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_al l_with_reset_error.1799001235 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_unmapped_addr.1375745763 |
| Short name | T1573 |
| Test name | |
| Test status | |
| Simulation time | 195059994 ps |
| CPU time | 23.74 seconds |
| Started | Jul 31 07:56:42 PM PDT 24 |
| Finished | Jul 31 07:57:06 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-56c6cb31-a3ce-474c-90e6-a7b6329a33b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375745763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.1375745763 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device.2311124702 |
| Short name | T1584 |
| Test name | |
| Test status | |
| Simulation time | 2578453757 ps |
| CPU time | 87.88 seconds |
| Started | Jul 31 07:56:49 PM PDT 24 |
| Finished | Jul 31 07:58:17 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-415297c8-46e1-46b3-a632-ae6c9fc42106 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311124702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device .2311124702 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.2444517697 |
| Short name | T2127 |
| Test name | |
| Test status | |
| Simulation time | 112908554278 ps |
| CPU time | 2102.71 seconds |
| Started | Jul 31 07:56:45 PM PDT 24 |
| Finished | Jul 31 08:31:48 PM PDT 24 |
| Peak memory | 576076 kb |
| Host | smart-c00b0000-0e0e-4347-9d9d-5e3d6a434db7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444517697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_ device_slow_rsp.2444517697 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.774042272 |
| Short name | T1802 |
| Test name | |
| Test status | |
| Simulation time | 1338042488 ps |
| CPU time | 55.01 seconds |
| Started | Jul 31 07:56:59 PM PDT 24 |
| Finished | Jul 31 07:57:55 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-2c334582-db86-4f1a-aa38-7bb47ba0fc53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774042272 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr .774042272 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_random.2199517264 |
| Short name | T2622 |
| Test name | |
| Test status | |
| Simulation time | 320694936 ps |
| CPU time | 29.93 seconds |
| Started | Jul 31 07:56:53 PM PDT 24 |
| Finished | Jul 31 07:57:23 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-1203b624-3c37-4dba-a64a-df2b59f4c52c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199517264 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.2199517264 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random.1687419957 |
| Short name | T2417 |
| Test name | |
| Test status | |
| Simulation time | 606047452 ps |
| CPU time | 51.5 seconds |
| Started | Jul 31 07:56:46 PM PDT 24 |
| Finished | Jul 31 07:57:38 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-056cb44a-0576-4d4e-b7f8-8db484c0612e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687419957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random.1687419957 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_large_delays.2859967761 |
| Short name | T2283 |
| Test name | |
| Test status | |
| Simulation time | 27983762251 ps |
| CPU time | 302.25 seconds |
| Started | Jul 31 07:56:46 PM PDT 24 |
| Finished | Jul 31 08:01:49 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-95df0d9d-a44b-4c41-a9b7-28f74e5c07d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859967761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.2859967761 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_slow_rsp.232196484 |
| Short name | T2114 |
| Test name | |
| Test status | |
| Simulation time | 27936595927 ps |
| CPU time | 489.68 seconds |
| Started | Jul 31 07:56:46 PM PDT 24 |
| Finished | Jul 31 08:04:56 PM PDT 24 |
| Peak memory | 576052 kb |
| Host | smart-5a3028e0-140f-422f-a676-d650d21aa3c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232196484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.232196484 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_zero_delays.2216554642 |
| Short name | T1935 |
| Test name | |
| Test status | |
| Simulation time | 615364165 ps |
| CPU time | 53.09 seconds |
| Started | Jul 31 07:56:48 PM PDT 24 |
| Finished | Jul 31 07:57:41 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-d775db88-40e3-45d4-b47a-29b1276cdcc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216554642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_del ays.2216554642 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_same_source.759283311 |
| Short name | T2486 |
| Test name | |
| Test status | |
| Simulation time | 388623496 ps |
| CPU time | 28.83 seconds |
| Started | Jul 31 07:56:53 PM PDT 24 |
| Finished | Jul 31 07:57:22 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-cb785c3c-a097-4476-a5e3-51fb9019cccd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759283311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.759283311 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke.199265800 |
| Short name | T2299 |
| Test name | |
| Test status | |
| Simulation time | 217314904 ps |
| CPU time | 9.29 seconds |
| Started | Jul 31 07:56:50 PM PDT 24 |
| Finished | Jul 31 07:57:00 PM PDT 24 |
| Peak memory | 573808 kb |
| Host | smart-0948310d-1eba-470e-8c39-6690741713d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199265800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.199265800 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_large_delays.2766416233 |
| Short name | T2632 |
| Test name | |
| Test status | |
| Simulation time | 6780932830 ps |
| CPU time | 69.94 seconds |
| Started | Jul 31 07:56:47 PM PDT 24 |
| Finished | Jul 31 07:57:57 PM PDT 24 |
| Peak memory | 573860 kb |
| Host | smart-8d3f6aa1-1328-4349-a3a5-e0b7bab2c3cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766416233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.2766416233 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.3814826125 |
| Short name | T1710 |
| Test name | |
| Test status | |
| Simulation time | 3777013174 ps |
| CPU time | 67.89 seconds |
| Started | Jul 31 07:56:53 PM PDT 24 |
| Finished | Jul 31 07:58:01 PM PDT 24 |
| Peak memory | 574500 kb |
| Host | smart-a1895208-dbb9-42c8-8128-77bd3147fc8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814826125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.3814826125 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_zero_delays.3857181855 |
| Short name | T1646 |
| Test name | |
| Test status | |
| Simulation time | 44654328 ps |
| CPU time | 6.05 seconds |
| Started | Jul 31 07:56:45 PM PDT 24 |
| Finished | Jul 31 07:56:51 PM PDT 24 |
| Peak memory | 574472 kb |
| Host | smart-db5191c9-d856-424e-9565-792c80ad83a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857181855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delay s.3857181855 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all.2879594567 |
| Short name | T2635 |
| Test name | |
| Test status | |
| Simulation time | 3145879986 ps |
| CPU time | 127.44 seconds |
| Started | Jul 31 07:56:59 PM PDT 24 |
| Finished | Jul 31 07:59:07 PM PDT 24 |
| Peak memory | 576436 kb |
| Host | smart-f929e73a-9c09-4479-86d3-fa6ef62be22a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879594567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.2879594567 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.2689537104 |
| Short name | T2092 |
| Test name | |
| Test status | |
| Simulation time | 3031876470 ps |
| CPU time | 221.46 seconds |
| Started | Jul 31 07:56:58 PM PDT 24 |
| Finished | Jul 31 08:00:39 PM PDT 24 |
| Peak memory | 576436 kb |
| Host | smart-bb1ac12c-8cea-4ca6-a370-ae2ac6e67d9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689537104 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.2689537104 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.3830899077 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 7587781488 ps |
| CPU time | 522.45 seconds |
| Started | Jul 31 07:56:58 PM PDT 24 |
| Finished | Jul 31 08:05:40 PM PDT 24 |
| Peak memory | 576816 kb |
| Host | smart-109907ce-dee9-4292-a48f-7ba513f410c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830899077 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_al l_with_reset_error.3830899077 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.3460805105 |
| Short name | T2440 |
| Test name | |
| Test status | |
| Simulation time | 441944079 ps |
| CPU time | 20.49 seconds |
| Started | Jul 31 07:56:53 PM PDT 24 |
| Finished | Jul 31 07:57:14 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-22e317dd-989e-4567-b979-1b1ea86aaa32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460805105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.3460805105 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device.1007796531 |
| Short name | T2685 |
| Test name | |
| Test status | |
| Simulation time | 750501568 ps |
| CPU time | 37.45 seconds |
| Started | Jul 31 07:57:02 PM PDT 24 |
| Finished | Jul 31 07:57:39 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-4d27b5a7-6a26-4e4f-bc53-7e9e084f8a7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007796531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device .1007796531 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.1190095992 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 78869697409 ps |
| CPU time | 1451.02 seconds |
| Started | Jul 31 07:57:04 PM PDT 24 |
| Finished | Jul 31 08:21:16 PM PDT 24 |
| Peak memory | 576068 kb |
| Host | smart-fc5e2b93-a606-4652-b27f-5d1e2903636c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190095992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_ device_slow_rsp.1190095992 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.1345253550 |
| Short name | T2933 |
| Test name | |
| Test status | |
| Simulation time | 1138312759 ps |
| CPU time | 41.61 seconds |
| Started | Jul 31 07:57:07 PM PDT 24 |
| Finished | Jul 31 07:57:49 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-7bb66eee-8c1a-44fa-8a30-c191a359cfa6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345253550 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_add r.1345253550 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_random.396625271 |
| Short name | T2626 |
| Test name | |
| Test status | |
| Simulation time | 161413039 ps |
| CPU time | 15.5 seconds |
| Started | Jul 31 07:57:07 PM PDT 24 |
| Finished | Jul 31 07:57:23 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-732e3af7-305c-4cab-9ecb-80ab6ed678ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396625271 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.396625271 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random.2875039097 |
| Short name | T2581 |
| Test name | |
| Test status | |
| Simulation time | 206091977 ps |
| CPU time | 20.88 seconds |
| Started | Jul 31 07:57:02 PM PDT 24 |
| Finished | Jul 31 07:57:23 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-29794f64-1ea6-4ae1-91cc-1c1e0a7b029b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875039097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random.2875039097 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_large_delays.3944623153 |
| Short name | T1600 |
| Test name | |
| Test status | |
| Simulation time | 72737072959 ps |
| CPU time | 742.44 seconds |
| Started | Jul 31 07:56:58 PM PDT 24 |
| Finished | Jul 31 08:09:20 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-62f142b8-c019-40ca-a05b-d27dacba35c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944623153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.3944623153 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_slow_rsp.1213436057 |
| Short name | T2442 |
| Test name | |
| Test status | |
| Simulation time | 50804153585 ps |
| CPU time | 933.49 seconds |
| Started | Jul 31 07:57:06 PM PDT 24 |
| Finished | Jul 31 08:12:40 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-8e06d359-b855-404a-bca8-b3502d7c7f40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213436057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.1213436057 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.2782051136 |
| Short name | T2714 |
| Test name | |
| Test status | |
| Simulation time | 292874399 ps |
| CPU time | 25.73 seconds |
| Started | Jul 31 07:56:59 PM PDT 24 |
| Finished | Jul 31 07:57:25 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-ff6dd9a8-3695-41a1-9279-7a0d77b5a67f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782051136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_del ays.2782051136 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_same_source.3234849087 |
| Short name | T1774 |
| Test name | |
| Test status | |
| Simulation time | 2129530168 ps |
| CPU time | 62.49 seconds |
| Started | Jul 31 07:57:01 PM PDT 24 |
| Finished | Jul 31 07:58:04 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-46c4b195-a688-4a4d-b982-50d528559bce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234849087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.3234849087 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke.1775282027 |
| Short name | T1389 |
| Test name | |
| Test status | |
| Simulation time | 241445023 ps |
| CPU time | 10.16 seconds |
| Started | Jul 31 07:57:00 PM PDT 24 |
| Finished | Jul 31 07:57:10 PM PDT 24 |
| Peak memory | 573852 kb |
| Host | smart-9b5e0c75-73ec-4205-b493-494872932ace |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775282027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.1775282027 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_large_delays.1242625154 |
| Short name | T1858 |
| Test name | |
| Test status | |
| Simulation time | 8730342830 ps |
| CPU time | 92.05 seconds |
| Started | Jul 31 07:57:00 PM PDT 24 |
| Finished | Jul 31 07:58:32 PM PDT 24 |
| Peak memory | 574012 kb |
| Host | smart-e598f3f6-1b50-4449-b9bf-7ae3bd98fbff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242625154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.1242625154 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.788817990 |
| Short name | T2725 |
| Test name | |
| Test status | |
| Simulation time | 4102500002 ps |
| CPU time | 72.58 seconds |
| Started | Jul 31 07:56:58 PM PDT 24 |
| Finished | Jul 31 07:58:11 PM PDT 24 |
| Peak memory | 573908 kb |
| Host | smart-3455ac99-4f38-43f1-b6ad-c47521994cce |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788817990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.788817990 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_zero_delays.2803822664 |
| Short name | T1996 |
| Test name | |
| Test status | |
| Simulation time | 41685433 ps |
| CPU time | 6.14 seconds |
| Started | Jul 31 07:56:57 PM PDT 24 |
| Finished | Jul 31 07:57:03 PM PDT 24 |
| Peak memory | 573788 kb |
| Host | smart-ddd8112a-aa47-46ca-bd3a-eac2923d2f00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803822664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delay s.2803822664 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all.844595665 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 668208268 ps |
| CPU time | 56.34 seconds |
| Started | Jul 31 07:57:08 PM PDT 24 |
| Finished | Jul 31 07:58:05 PM PDT 24 |
| Peak memory | 576132 kb |
| Host | smart-ea84d0d9-043e-4d53-8ccb-1462f4480f0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844595665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.844595665 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.744945658 |
| Short name | T2079 |
| Test name | |
| Test status | |
| Simulation time | 1423304173 ps |
| CPU time | 107.89 seconds |
| Started | Jul 31 07:57:07 PM PDT 24 |
| Finished | Jul 31 07:58:55 PM PDT 24 |
| Peak memory | 576072 kb |
| Host | smart-86a58e58-4987-427b-a131-13cf1191ecca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744945658 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.744945658 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.3790363358 |
| Short name | T2279 |
| Test name | |
| Test status | |
| Simulation time | 227003943 ps |
| CPU time | 67.34 seconds |
| Started | Jul 31 07:57:05 PM PDT 24 |
| Finished | Jul 31 07:58:12 PM PDT 24 |
| Peak memory | 576040 kb |
| Host | smart-068b8cd2-3341-4679-94a5-a0043ab39d90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790363358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all _with_rand_reset.3790363358 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.3023267093 |
| Short name | T2919 |
| Test name | |
| Test status | |
| Simulation time | 2716807617 ps |
| CPU time | 310.44 seconds |
| Started | Jul 31 07:57:04 PM PDT 24 |
| Finished | Jul 31 08:02:15 PM PDT 24 |
| Peak memory | 576784 kb |
| Host | smart-a3c8b0de-9e07-421b-886e-db149f2f5a5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023267093 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_al l_with_reset_error.3023267093 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_unmapped_addr.2835256974 |
| Short name | T2214 |
| Test name | |
| Test status | |
| Simulation time | 142875979 ps |
| CPU time | 19 seconds |
| Started | Jul 31 07:57:07 PM PDT 24 |
| Finished | Jul 31 07:57:26 PM PDT 24 |
| Peak memory | 576076 kb |
| Host | smart-9dda1c6e-cdd5-4a33-a079-78d708ab8ad7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835256974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.2835256974 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.1046839458 |
| Short name | T2129 |
| Test name | |
| Test status | |
| Simulation time | 11591314960 ps |
| CPU time | 895.97 seconds |
| Started | Jul 31 07:46:50 PM PDT 24 |
| Finished | Jul 31 08:01:46 PM PDT 24 |
| Peak memory | 652724 kb |
| Host | smart-bcae00b5-eff9-4c46-970a-b20f0c8f3e9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046839458 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 5.chip_csr_mem_rw_with_rand_reset.1046839458 |
| Directory | /workspace/5.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_csr_rw.1997494452 |
| Short name | T2021 |
| Test name | |
| Test status | |
| Simulation time | 3456132840 ps |
| CPU time | 301.5 seconds |
| Started | Jul 31 07:46:47 PM PDT 24 |
| Finished | Jul 31 07:51:49 PM PDT 24 |
| Peak memory | 598692 kb |
| Host | smart-e0de6203-229e-45de-a1c0-be566b4218a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997494452 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_rw.1997494452 |
| Directory | /workspace/5.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.2445010337 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 30807525967 ps |
| CPU time | 4594.41 seconds |
| Started | Jul 31 07:46:36 PM PDT 24 |
| Finished | Jul 31 09:03:11 PM PDT 24 |
| Peak memory | 592964 kb |
| Host | smart-47d6ce3c-4b68-4b51-b62c-4642a41b0703 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445010337 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 5.chip_same_csr_outstanding.2445010337 |
| Directory | /workspace/5.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device.202180404 |
| Short name | T2607 |
| Test name | |
| Test status | |
| Simulation time | 3497467376 ps |
| CPU time | 111.18 seconds |
| Started | Jul 31 07:46:41 PM PDT 24 |
| Finished | Jul 31 07:48:32 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-945c6f55-6b2e-4453-9ef7-f7dd81f51bc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202180404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.202180404 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.2992597389 |
| Short name | T2350 |
| Test name | |
| Test status | |
| Simulation time | 87399331237 ps |
| CPU time | 1539.69 seconds |
| Started | Jul 31 07:46:40 PM PDT 24 |
| Finished | Jul 31 08:12:21 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-3742c317-8115-4708-8781-b7e83d04b0e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992597389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_d evice_slow_rsp.2992597389 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.179369647 |
| Short name | T1903 |
| Test name | |
| Test status | |
| Simulation time | 1196799791 ps |
| CPU time | 51.25 seconds |
| Started | Jul 31 07:46:42 PM PDT 24 |
| Finished | Jul 31 07:47:33 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-ea64f536-d965-45c4-afc0-4ac99c135dd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179369647 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr. 179369647 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_random.3696252011 |
| Short name | T1423 |
| Test name | |
| Test status | |
| Simulation time | 1841346231 ps |
| CPU time | 62.02 seconds |
| Started | Jul 31 07:46:41 PM PDT 24 |
| Finished | Jul 31 07:47:43 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-73dda103-9cfb-4098-a82e-c8f8c4d0959a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696252011 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.3696252011 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random.2604213949 |
| Short name | T2819 |
| Test name | |
| Test status | |
| Simulation time | 1536570071 ps |
| CPU time | 54.96 seconds |
| Started | Jul 31 07:46:36 PM PDT 24 |
| Finished | Jul 31 07:47:31 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-e156bcfb-6f99-47ca-9fc6-d279a32e2235 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604213949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random.2604213949 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_large_delays.1257291877 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 74532902075 ps |
| CPU time | 796.61 seconds |
| Started | Jul 31 07:46:40 PM PDT 24 |
| Finished | Jul 31 07:59:57 PM PDT 24 |
| Peak memory | 576052 kb |
| Host | smart-732c39d7-a581-454c-89a9-441b81ac297e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257291877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.1257291877 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.891727287 |
| Short name | T1642 |
| Test name | |
| Test status | |
| Simulation time | 26163719229 ps |
| CPU time | 437.08 seconds |
| Started | Jul 31 07:46:41 PM PDT 24 |
| Finished | Jul 31 07:53:58 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-23d0cf66-7e9b-4813-a7b5-aa77b6e35c4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891727287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.891727287 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_zero_delays.3927999150 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 303098812 ps |
| CPU time | 31.21 seconds |
| Started | Jul 31 07:46:41 PM PDT 24 |
| Finished | Jul 31 07:47:12 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-06585f90-104d-4d8e-a1b6-3e3da86be485 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927999150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_dela ys.3927999150 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_same_source.3275840890 |
| Short name | T1718 |
| Test name | |
| Test status | |
| Simulation time | 193002983 ps |
| CPU time | 16.8 seconds |
| Started | Jul 31 07:46:41 PM PDT 24 |
| Finished | Jul 31 07:46:58 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-c2d11563-e563-470b-a6d7-9666674bfaaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275840890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.3275840890 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke.268500591 |
| Short name | T1419 |
| Test name | |
| Test status | |
| Simulation time | 202268812 ps |
| CPU time | 8.95 seconds |
| Started | Jul 31 07:46:37 PM PDT 24 |
| Finished | Jul 31 07:46:46 PM PDT 24 |
| Peak memory | 574488 kb |
| Host | smart-60eb47c8-d89e-4007-9a72-d87ab01c3525 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268500591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.268500591 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_large_delays.3708606868 |
| Short name | T2692 |
| Test name | |
| Test status | |
| Simulation time | 10773570530 ps |
| CPU time | 123.34 seconds |
| Started | Jul 31 07:46:36 PM PDT 24 |
| Finished | Jul 31 07:48:39 PM PDT 24 |
| Peak memory | 573872 kb |
| Host | smart-ff08351b-130d-45ac-9197-083fde5639c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708606868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.3708606868 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.1306254679 |
| Short name | T1610 |
| Test name | |
| Test status | |
| Simulation time | 3900523080 ps |
| CPU time | 66.29 seconds |
| Started | Jul 31 07:46:36 PM PDT 24 |
| Finished | Jul 31 07:47:42 PM PDT 24 |
| Peak memory | 573748 kb |
| Host | smart-2073719b-34e1-4350-bd95-12d11a383c15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306254679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.1306254679 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_zero_delays.808366267 |
| Short name | T2401 |
| Test name | |
| Test status | |
| Simulation time | 40183583 ps |
| CPU time | 5.66 seconds |
| Started | Jul 31 07:46:36 PM PDT 24 |
| Finished | Jul 31 07:46:42 PM PDT 24 |
| Peak memory | 573828 kb |
| Host | smart-cc068df8-c0a6-4aa6-b5e1-631136906b09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808366267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays. 808366267 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all.3131773698 |
| Short name | T1427 |
| Test name | |
| Test status | |
| Simulation time | 5613912 ps |
| CPU time | 3.72 seconds |
| Started | Jul 31 07:46:53 PM PDT 24 |
| Finished | Jul 31 07:46:57 PM PDT 24 |
| Peak memory | 566144 kb |
| Host | smart-6c594496-b78b-4bc5-ab67-9189b39920a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131773698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.3131773698 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.540965990 |
| Short name | T1831 |
| Test name | |
| Test status | |
| Simulation time | 3236974237 ps |
| CPU time | 324.37 seconds |
| Started | Jul 31 07:46:50 PM PDT 24 |
| Finished | Jul 31 07:52:15 PM PDT 24 |
| Peak memory | 576636 kb |
| Host | smart-d4bec8b9-a2c4-49f4-8e17-67ccf004570a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540965990 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.540965990 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.2192544181 |
| Short name | T1433 |
| Test name | |
| Test status | |
| Simulation time | 7525893 ps |
| CPU time | 6.09 seconds |
| Started | Jul 31 07:46:48 PM PDT 24 |
| Finished | Jul 31 07:46:55 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-b10ca7a1-d2a5-480b-a714-518519a4a081 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192544181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_ with_rand_reset.2192544181 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.2815984086 |
| Short name | T2662 |
| Test name | |
| Test status | |
| Simulation time | 562467083 ps |
| CPU time | 159.3 seconds |
| Started | Jul 31 07:46:48 PM PDT 24 |
| Finished | Jul 31 07:49:27 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-9f577cc3-4332-4d79-a2a7-41435a3d8328 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815984086 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all _with_reset_error.2815984086 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.2327141762 |
| Short name | T1766 |
| Test name | |
| Test status | |
| Simulation time | 54262592 ps |
| CPU time | 5.78 seconds |
| Started | Jul 31 07:46:44 PM PDT 24 |
| Finished | Jul 31 07:46:49 PM PDT 24 |
| Peak memory | 573916 kb |
| Host | smart-e0284566-989c-4a4d-aaa1-b8af2b1b6778 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327141762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.2327141762 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device.1681753917 |
| Short name | T1641 |
| Test name | |
| Test status | |
| Simulation time | 365085192 ps |
| CPU time | 25.02 seconds |
| Started | Jul 31 07:57:15 PM PDT 24 |
| Finished | Jul 31 07:57:40 PM PDT 24 |
| Peak memory | 576040 kb |
| Host | smart-8d6c4179-4f85-431d-83fb-c06d6448d99d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681753917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device .1681753917 |
| Directory | /workspace/50.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.3596758954 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 67178541803 ps |
| CPU time | 1197.93 seconds |
| Started | Jul 31 07:57:11 PM PDT 24 |
| Finished | Jul 31 08:17:09 PM PDT 24 |
| Peak memory | 576076 kb |
| Host | smart-45c7ca64-96fd-4156-8eb8-5dce9acbc4dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596758954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_ device_slow_rsp.3596758954 |
| Directory | /workspace/50.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.3666105048 |
| Short name | T1970 |
| Test name | |
| Test status | |
| Simulation time | 152304903 ps |
| CPU time | 18.71 seconds |
| Started | Jul 31 07:57:17 PM PDT 24 |
| Finished | Jul 31 07:57:36 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-d7cb206e-d2df-44c7-bd72-30b0e5de3a69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666105048 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_and_unmapped_add r.3666105048 |
| Directory | /workspace/50.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_random.1818423669 |
| Short name | T2780 |
| Test name | |
| Test status | |
| Simulation time | 37372916 ps |
| CPU time | 6.2 seconds |
| Started | Jul 31 07:57:11 PM PDT 24 |
| Finished | Jul 31 07:57:17 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-d1e7ad86-e477-44da-8ecc-4995aec588e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818423669 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_random.1818423669 |
| Directory | /workspace/50.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random.1128908183 |
| Short name | T1709 |
| Test name | |
| Test status | |
| Simulation time | 858774022 ps |
| CPU time | 32.59 seconds |
| Started | Jul 31 07:57:12 PM PDT 24 |
| Finished | Jul 31 07:57:45 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-f90f33ac-4ac9-4dbd-90d7-d14627206eba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128908183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random.1128908183 |
| Directory | /workspace/50.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_large_delays.527021265 |
| Short name | T1613 |
| Test name | |
| Test status | |
| Simulation time | 104541423482 ps |
| CPU time | 1133.14 seconds |
| Started | Jul 31 07:57:12 PM PDT 24 |
| Finished | Jul 31 08:16:05 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-ad444828-4af5-49ed-8c5b-bb31b8958555 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527021265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_large_delays.527021265 |
| Directory | /workspace/50.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.4114915551 |
| Short name | T1955 |
| Test name | |
| Test status | |
| Simulation time | 5001016822 ps |
| CPU time | 83.46 seconds |
| Started | Jul 31 07:57:12 PM PDT 24 |
| Finished | Jul 31 07:58:36 PM PDT 24 |
| Peak memory | 574024 kb |
| Host | smart-f377e237-8ffd-45d9-a8ee-1c2e2a64d871 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114915551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_slow_rsp.4114915551 |
| Directory | /workspace/50.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_zero_delays.2389583947 |
| Short name | T2517 |
| Test name | |
| Test status | |
| Simulation time | 34816867 ps |
| CPU time | 6.12 seconds |
| Started | Jul 31 07:57:12 PM PDT 24 |
| Finished | Jul 31 07:57:18 PM PDT 24 |
| Peak memory | 573796 kb |
| Host | smart-fe814cb5-f669-4205-b210-9d7ae84d828a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389583947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_zero_del ays.2389583947 |
| Directory | /workspace/50.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_same_source.2329538861 |
| Short name | T1448 |
| Test name | |
| Test status | |
| Simulation time | 273621706 ps |
| CPU time | 19.61 seconds |
| Started | Jul 31 07:57:14 PM PDT 24 |
| Finished | Jul 31 07:57:34 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-1dc23aa1-3c61-4caf-9a71-a968fafb37f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329538861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_same_source.2329538861 |
| Directory | /workspace/50.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke.2576348516 |
| Short name | T2073 |
| Test name | |
| Test status | |
| Simulation time | 49178902 ps |
| CPU time | 6.88 seconds |
| Started | Jul 31 07:57:03 PM PDT 24 |
| Finished | Jul 31 07:57:10 PM PDT 24 |
| Peak memory | 573860 kb |
| Host | smart-5033b44a-eb0d-40c7-9422-39223a11cefc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576348516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke.2576348516 |
| Directory | /workspace/50.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_large_delays.2146693553 |
| Short name | T1724 |
| Test name | |
| Test status | |
| Simulation time | 9549650521 ps |
| CPU time | 105.55 seconds |
| Started | Jul 31 07:57:11 PM PDT 24 |
| Finished | Jul 31 07:58:57 PM PDT 24 |
| Peak memory | 573816 kb |
| Host | smart-c31602a8-09de-463c-87ab-1bad646fb55b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146693553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_large_delays.2146693553 |
| Directory | /workspace/50.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.976478135 |
| Short name | T1978 |
| Test name | |
| Test status | |
| Simulation time | 5576056655 ps |
| CPU time | 90.13 seconds |
| Started | Jul 31 07:57:12 PM PDT 24 |
| Finished | Jul 31 07:58:42 PM PDT 24 |
| Peak memory | 574568 kb |
| Host | smart-a67eb8a1-6c0c-4907-ba40-1effa4ed9011 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976478135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_slow_rsp.976478135 |
| Directory | /workspace/50.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_zero_delays.3722925369 |
| Short name | T2249 |
| Test name | |
| Test status | |
| Simulation time | 44132765 ps |
| CPU time | 6.29 seconds |
| Started | Jul 31 07:57:04 PM PDT 24 |
| Finished | Jul 31 07:57:10 PM PDT 24 |
| Peak memory | 573736 kb |
| Host | smart-fece5846-80a8-45cb-a0e1-27e6885063e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722925369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_zero_delay s.3722925369 |
| Directory | /workspace/50.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all.2740737595 |
| Short name | T2777 |
| Test name | |
| Test status | |
| Simulation time | 7215409292 ps |
| CPU time | 216.21 seconds |
| Started | Jul 31 07:57:16 PM PDT 24 |
| Finished | Jul 31 08:00:52 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-799786fb-39a3-4db5-9d24-eb1da4f913ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740737595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all.2740737595 |
| Directory | /workspace/50.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.1168678561 |
| Short name | T2429 |
| Test name | |
| Test status | |
| Simulation time | 15718130712 ps |
| CPU time | 537.81 seconds |
| Started | Jul 31 07:57:20 PM PDT 24 |
| Finished | Jul 31 08:06:18 PM PDT 24 |
| Peak memory | 576868 kb |
| Host | smart-bf51aea1-723a-4424-b0a2-506794617b58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168678561 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_error.1168678561 |
| Directory | /workspace/50.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.3459696148 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 23757274 ps |
| CPU time | 15.58 seconds |
| Started | Jul 31 07:57:17 PM PDT 24 |
| Finished | Jul 31 07:57:32 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-54a7e5eb-46bd-4dd3-8133-cd5d02fadefa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459696148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all _with_rand_reset.3459696148 |
| Directory | /workspace/50.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.1356000647 |
| Short name | T2746 |
| Test name | |
| Test status | |
| Simulation time | 3048260663 ps |
| CPU time | 171.05 seconds |
| Started | Jul 31 07:57:18 PM PDT 24 |
| Finished | Jul 31 08:00:09 PM PDT 24 |
| Peak memory | 576744 kb |
| Host | smart-995f9d66-bb9b-446c-bd1f-b1426bc8fb41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356000647 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_al l_with_reset_error.1356000647 |
| Directory | /workspace/50.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.1768962977 |
| Short name | T1860 |
| Test name | |
| Test status | |
| Simulation time | 444820486 ps |
| CPU time | 19.92 seconds |
| Started | Jul 31 07:57:18 PM PDT 24 |
| Finished | Jul 31 07:57:38 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-67234464-ddda-4c7a-80ec-17678c1ef7d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768962977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_unmapped_addr.1768962977 |
| Directory | /workspace/50.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device.327893301 |
| Short name | T2774 |
| Test name | |
| Test status | |
| Simulation time | 290383458 ps |
| CPU time | 13.32 seconds |
| Started | Jul 31 07:57:20 PM PDT 24 |
| Finished | Jul 31 07:57:34 PM PDT 24 |
| Peak memory | 573912 kb |
| Host | smart-e4e8c5eb-339e-4f7d-856c-bf3778c83903 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327893301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device. 327893301 |
| Directory | /workspace/51.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.4186469573 |
| Short name | T2322 |
| Test name | |
| Test status | |
| Simulation time | 97339241644 ps |
| CPU time | 1798.94 seconds |
| Started | Jul 31 07:57:23 PM PDT 24 |
| Finished | Jul 31 08:27:23 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-4f82810c-1795-44b0-b559-0eabd6e8308e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186469573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_ device_slow_rsp.4186469573 |
| Directory | /workspace/51.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.1278383459 |
| Short name | T1706 |
| Test name | |
| Test status | |
| Simulation time | 326736677 ps |
| CPU time | 37.55 seconds |
| Started | Jul 31 07:57:24 PM PDT 24 |
| Finished | Jul 31 07:58:02 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-34677c63-acc6-45bc-84be-1b1009497ce3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278383459 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_and_unmapped_add r.1278383459 |
| Directory | /workspace/51.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_random.423858052 |
| Short name | T2090 |
| Test name | |
| Test status | |
| Simulation time | 163417993 ps |
| CPU time | 17.58 seconds |
| Started | Jul 31 07:57:24 PM PDT 24 |
| Finished | Jul 31 07:57:42 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-88be918a-f333-4536-a8c6-6227d0953aac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423858052 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_random.423858052 |
| Directory | /workspace/51.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random.569183548 |
| Short name | T2470 |
| Test name | |
| Test status | |
| Simulation time | 2223595758 ps |
| CPU time | 85.54 seconds |
| Started | Jul 31 07:57:18 PM PDT 24 |
| Finished | Jul 31 07:58:44 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-5ba7af0d-f4e4-4567-b3ec-643f747756f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569183548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random.569183548 |
| Directory | /workspace/51.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_large_delays.653017950 |
| Short name | T2842 |
| Test name | |
| Test status | |
| Simulation time | 54972520498 ps |
| CPU time | 620.55 seconds |
| Started | Jul 31 07:57:18 PM PDT 24 |
| Finished | Jul 31 08:07:39 PM PDT 24 |
| Peak memory | 576032 kb |
| Host | smart-d93f271a-88e6-406b-877a-8682376f4643 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653017950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_large_delays.653017950 |
| Directory | /workspace/51.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_slow_rsp.3821876583 |
| Short name | T2511 |
| Test name | |
| Test status | |
| Simulation time | 47916985077 ps |
| CPU time | 851.96 seconds |
| Started | Jul 31 07:57:18 PM PDT 24 |
| Finished | Jul 31 08:11:31 PM PDT 24 |
| Peak memory | 576816 kb |
| Host | smart-ebd18263-f875-4940-99a9-d575f7faa5e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821876583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_slow_rsp.3821876583 |
| Directory | /workspace/51.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_zero_delays.3200569713 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 299296228 ps |
| CPU time | 23.24 seconds |
| Started | Jul 31 07:57:24 PM PDT 24 |
| Finished | Jul 31 07:57:47 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-11633e28-f480-4edd-8a7e-dcf3158ee88e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200569713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_zero_del ays.3200569713 |
| Directory | /workspace/51.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_same_source.627611646 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 264449131 ps |
| CPU time | 21.16 seconds |
| Started | Jul 31 07:57:24 PM PDT 24 |
| Finished | Jul 31 07:57:46 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-82125ea4-eea3-4976-9de6-114fe7302338 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627611646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_same_source.627611646 |
| Directory | /workspace/51.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke.2544782296 |
| Short name | T2272 |
| Test name | |
| Test status | |
| Simulation time | 241310531 ps |
| CPU time | 10.51 seconds |
| Started | Jul 31 07:57:25 PM PDT 24 |
| Finished | Jul 31 07:57:35 PM PDT 24 |
| Peak memory | 574524 kb |
| Host | smart-1f09d8ab-f4f1-4dec-ada1-118f295784b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544782296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke.2544782296 |
| Directory | /workspace/51.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_large_delays.651266774 |
| Short name | T1657 |
| Test name | |
| Test status | |
| Simulation time | 8861923876 ps |
| CPU time | 89.49 seconds |
| Started | Jul 31 07:57:21 PM PDT 24 |
| Finished | Jul 31 07:58:50 PM PDT 24 |
| Peak memory | 574592 kb |
| Host | smart-a53c081d-c354-44f7-b193-29e5bb806f81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651266774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_large_delays.651266774 |
| Directory | /workspace/51.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.3883288682 |
| Short name | T2704 |
| Test name | |
| Test status | |
| Simulation time | 4721795102 ps |
| CPU time | 76.74 seconds |
| Started | Jul 31 07:57:24 PM PDT 24 |
| Finished | Jul 31 07:58:41 PM PDT 24 |
| Peak memory | 573936 kb |
| Host | smart-9c04d09a-44c6-4604-a6cd-67bd9ca42670 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883288682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_slow_rsp.3883288682 |
| Directory | /workspace/51.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_zero_delays.468306364 |
| Short name | T1595 |
| Test name | |
| Test status | |
| Simulation time | 37667388 ps |
| CPU time | 5.73 seconds |
| Started | Jul 31 07:57:18 PM PDT 24 |
| Finished | Jul 31 07:57:24 PM PDT 24 |
| Peak memory | 573900 kb |
| Host | smart-a9fded92-3026-401a-8f05-0f9cb3a073ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468306364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_zero_delays .468306364 |
| Directory | /workspace/51.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all.1187461831 |
| Short name | T2394 |
| Test name | |
| Test status | |
| Simulation time | 1068369935 ps |
| CPU time | 36.57 seconds |
| Started | Jul 31 07:57:23 PM PDT 24 |
| Finished | Jul 31 07:57:59 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-0b87c9ec-ae23-44ac-956f-016d7e26fc93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187461831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all.1187461831 |
| Directory | /workspace/51.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.202139757 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 7328512824 ps |
| CPU time | 247.47 seconds |
| Started | Jul 31 07:57:25 PM PDT 24 |
| Finished | Jul 31 08:01:32 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-184e13a4-969a-4dd9-b79a-000afdabdba5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202139757 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_error.202139757 |
| Directory | /workspace/51.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.3922389149 |
| Short name | T2094 |
| Test name | |
| Test status | |
| Simulation time | 4558944338 ps |
| CPU time | 202.1 seconds |
| Started | Jul 31 07:57:24 PM PDT 24 |
| Finished | Jul 31 08:00:46 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-e51e1968-4fa9-4cce-8062-0963cbc2349e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922389149 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_al l_with_reset_error.3922389149 |
| Directory | /workspace/51.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.2310712949 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 131590960 ps |
| CPU time | 18.21 seconds |
| Started | Jul 31 07:57:26 PM PDT 24 |
| Finished | Jul 31 07:57:44 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-abacc285-3671-41f6-a40e-e0f65d8ee241 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310712949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_unmapped_addr.2310712949 |
| Directory | /workspace/51.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device.3463816093 |
| Short name | T1818 |
| Test name | |
| Test status | |
| Simulation time | 2279419496 ps |
| CPU time | 93.44 seconds |
| Started | Jul 31 07:57:34 PM PDT 24 |
| Finished | Jul 31 07:59:08 PM PDT 24 |
| Peak memory | 576040 kb |
| Host | smart-43aac58f-9959-4b45-b03f-a557da94acb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463816093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device .3463816093 |
| Directory | /workspace/52.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.3480676290 |
| Short name | T2599 |
| Test name | |
| Test status | |
| Simulation time | 119800541918 ps |
| CPU time | 2215.91 seconds |
| Started | Jul 31 07:57:35 PM PDT 24 |
| Finished | Jul 31 08:34:31 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-40f66cda-05fc-4691-97af-b2bc73affde9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480676290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_ device_slow_rsp.3480676290 |
| Directory | /workspace/52.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.906291472 |
| Short name | T1404 |
| Test name | |
| Test status | |
| Simulation time | 344998895 ps |
| CPU time | 38.77 seconds |
| Started | Jul 31 07:57:32 PM PDT 24 |
| Finished | Jul 31 07:58:11 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-6ace9b17-5c2c-4e18-98f9-3ba4799a33f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906291472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_and_unmapped_addr .906291472 |
| Directory | /workspace/52.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_random.977498904 |
| Short name | T2460 |
| Test name | |
| Test status | |
| Simulation time | 1385624035 ps |
| CPU time | 44.54 seconds |
| Started | Jul 31 07:57:34 PM PDT 24 |
| Finished | Jul 31 07:58:18 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-1d57c4a4-eebf-4900-8331-f0ae5be8c373 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977498904 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_random.977498904 |
| Directory | /workspace/52.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random.4140499069 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 489260630 ps |
| CPU time | 44.77 seconds |
| Started | Jul 31 07:57:35 PM PDT 24 |
| Finished | Jul 31 07:58:20 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-fd730817-7846-458a-bee2-131167b42451 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140499069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random.4140499069 |
| Directory | /workspace/52.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_large_delays.1618908325 |
| Short name | T2167 |
| Test name | |
| Test status | |
| Simulation time | 65807364358 ps |
| CPU time | 727.75 seconds |
| Started | Jul 31 07:57:32 PM PDT 24 |
| Finished | Jul 31 08:09:40 PM PDT 24 |
| Peak memory | 576056 kb |
| Host | smart-f5274fea-3d68-44a5-b6c5-58d4b992d06c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618908325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_large_delays.1618908325 |
| Directory | /workspace/52.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.63867431 |
| Short name | T1685 |
| Test name | |
| Test status | |
| Simulation time | 65128012655 ps |
| CPU time | 1175.51 seconds |
| Started | Jul 31 07:57:33 PM PDT 24 |
| Finished | Jul 31 08:17:08 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-7a075fae-146d-4df1-9b8e-67a7ff3dbb43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63867431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_slow_rsp.63867431 |
| Directory | /workspace/52.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_zero_delays.2088364594 |
| Short name | T1535 |
| Test name | |
| Test status | |
| Simulation time | 238973369 ps |
| CPU time | 22.44 seconds |
| Started | Jul 31 07:57:35 PM PDT 24 |
| Finished | Jul 31 07:57:57 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-88f661f3-d759-4fce-b131-303b8be18a11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088364594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_zero_del ays.2088364594 |
| Directory | /workspace/52.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_same_source.3439742677 |
| Short name | T1627 |
| Test name | |
| Test status | |
| Simulation time | 1498176883 ps |
| CPU time | 43.88 seconds |
| Started | Jul 31 07:57:33 PM PDT 24 |
| Finished | Jul 31 07:58:17 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-ddabb530-4f42-4a10-8638-addf61e29e57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439742677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_same_source.3439742677 |
| Directory | /workspace/52.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke.1408380447 |
| Short name | T1617 |
| Test name | |
| Test status | |
| Simulation time | 50937199 ps |
| CPU time | 6.84 seconds |
| Started | Jul 31 07:57:26 PM PDT 24 |
| Finished | Jul 31 07:57:33 PM PDT 24 |
| Peak memory | 573896 kb |
| Host | smart-6ff275af-b04e-49e1-ba34-ab5a145247f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408380447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke.1408380447 |
| Directory | /workspace/52.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.2031040071 |
| Short name | T1854 |
| Test name | |
| Test status | |
| Simulation time | 5479570939 ps |
| CPU time | 57.68 seconds |
| Started | Jul 31 07:57:36 PM PDT 24 |
| Finished | Jul 31 07:58:33 PM PDT 24 |
| Peak memory | 574628 kb |
| Host | smart-4b8624c8-2ecf-4149-92cd-1954d1c4b395 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031040071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_large_delays.2031040071 |
| Directory | /workspace/52.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.2958582712 |
| Short name | T2673 |
| Test name | |
| Test status | |
| Simulation time | 5565232585 ps |
| CPU time | 93.62 seconds |
| Started | Jul 31 07:57:34 PM PDT 24 |
| Finished | Jul 31 07:59:08 PM PDT 24 |
| Peak memory | 573928 kb |
| Host | smart-665c8d31-dd86-4c3d-9689-eddbbcb48144 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958582712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_slow_rsp.2958582712 |
| Directory | /workspace/52.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.442669544 |
| Short name | T2573 |
| Test name | |
| Test status | |
| Simulation time | 47771340 ps |
| CPU time | 6.61 seconds |
| Started | Jul 31 07:57:24 PM PDT 24 |
| Finished | Jul 31 07:57:31 PM PDT 24 |
| Peak memory | 573712 kb |
| Host | smart-271e2cfd-2c22-4b53-8b09-b486b1815ded |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442669544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_zero_delays .442669544 |
| Directory | /workspace/52.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all.2576563901 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 9477270309 ps |
| CPU time | 369.36 seconds |
| Started | Jul 31 07:57:33 PM PDT 24 |
| Finished | Jul 31 08:03:43 PM PDT 24 |
| Peak memory | 576144 kb |
| Host | smart-2c1a0bec-1059-4969-b5e2-ac26ca32224c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576563901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all.2576563901 |
| Directory | /workspace/52.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.500750239 |
| Short name | T1893 |
| Test name | |
| Test status | |
| Simulation time | 10811568429 ps |
| CPU time | 399.32 seconds |
| Started | Jul 31 07:57:40 PM PDT 24 |
| Finished | Jul 31 08:04:19 PM PDT 24 |
| Peak memory | 576872 kb |
| Host | smart-ebfa7f31-05b7-463c-ba62-de9b2a8bb5f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500750239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_error.500750239 |
| Directory | /workspace/52.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.714173836 |
| Short name | T1809 |
| Test name | |
| Test status | |
| Simulation time | 1751274023 ps |
| CPU time | 274.04 seconds |
| Started | Jul 31 07:57:34 PM PDT 24 |
| Finished | Jul 31 08:02:08 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-3b8de9d8-6323-420d-a9a2-a7923e57cffc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714173836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_ with_rand_reset.714173836 |
| Directory | /workspace/52.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.2061078690 |
| Short name | T1793 |
| Test name | |
| Test status | |
| Simulation time | 344932158 ps |
| CPU time | 121.98 seconds |
| Started | Jul 31 07:57:39 PM PDT 24 |
| Finished | Jul 31 07:59:41 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-0259420b-9709-4931-8e99-80ff9e30e618 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061078690 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_al l_with_reset_error.2061078690 |
| Directory | /workspace/52.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_unmapped_addr.2514509697 |
| Short name | T2207 |
| Test name | |
| Test status | |
| Simulation time | 258908107 ps |
| CPU time | 28.46 seconds |
| Started | Jul 31 07:57:34 PM PDT 24 |
| Finished | Jul 31 07:58:02 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-ea954149-404d-4aca-b8be-e91c06c41027 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514509697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_unmapped_addr.2514509697 |
| Directory | /workspace/52.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device.2866307811 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 925764380 ps |
| CPU time | 68.09 seconds |
| Started | Jul 31 07:57:44 PM PDT 24 |
| Finished | Jul 31 07:58:52 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-4b59bc33-170f-4655-a1eb-3292f46d7134 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866307811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device .2866307811 |
| Directory | /workspace/53.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.4100479545 |
| Short name | T2399 |
| Test name | |
| Test status | |
| Simulation time | 88530632874 ps |
| CPU time | 1620.83 seconds |
| Started | Jul 31 07:57:43 PM PDT 24 |
| Finished | Jul 31 08:24:44 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-233ebd1a-4607-4a75-bbaf-cf8d830e6214 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100479545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_ device_slow_rsp.4100479545 |
| Directory | /workspace/53.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.3836976915 |
| Short name | T2652 |
| Test name | |
| Test status | |
| Simulation time | 1011783528 ps |
| CPU time | 41.63 seconds |
| Started | Jul 31 07:57:41 PM PDT 24 |
| Finished | Jul 31 07:58:23 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-8c5879ad-6433-45e5-9406-74a4849232a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836976915 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_and_unmapped_add r.3836976915 |
| Directory | /workspace/53.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_random.3138422009 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 230997197 ps |
| CPU time | 20.76 seconds |
| Started | Jul 31 07:57:41 PM PDT 24 |
| Finished | Jul 31 07:58:02 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-03a6356c-903a-4adb-86da-98c90b90a470 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138422009 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_random.3138422009 |
| Directory | /workspace/53.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random.2875680726 |
| Short name | T2810 |
| Test name | |
| Test status | |
| Simulation time | 374179629 ps |
| CPU time | 29.68 seconds |
| Started | Jul 31 07:57:40 PM PDT 24 |
| Finished | Jul 31 07:58:10 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-f2e664d1-8c43-497a-bd16-10dcd6bc1322 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875680726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random.2875680726 |
| Directory | /workspace/53.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_large_delays.225794496 |
| Short name | T2152 |
| Test name | |
| Test status | |
| Simulation time | 92092640987 ps |
| CPU time | 1111.42 seconds |
| Started | Jul 31 07:57:43 PM PDT 24 |
| Finished | Jul 31 08:16:15 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-1a1d2c46-3174-4185-832b-df1f546a0dcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225794496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_large_delays.225794496 |
| Directory | /workspace/53.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.3800141156 |
| Short name | T2901 |
| Test name | |
| Test status | |
| Simulation time | 51118072284 ps |
| CPU time | 913.24 seconds |
| Started | Jul 31 07:57:41 PM PDT 24 |
| Finished | Jul 31 08:12:54 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-d1ad6685-6d8d-42ce-aba0-09a2a8207771 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800141156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_slow_rsp.3800141156 |
| Directory | /workspace/53.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_zero_delays.2037841207 |
| Short name | T2595 |
| Test name | |
| Test status | |
| Simulation time | 68089260 ps |
| CPU time | 9.13 seconds |
| Started | Jul 31 07:57:42 PM PDT 24 |
| Finished | Jul 31 07:57:51 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-75c5e2c2-d8b0-4541-959f-5810f8f9a1a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037841207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_zero_del ays.2037841207 |
| Directory | /workspace/53.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_same_source.1616025693 |
| Short name | T2641 |
| Test name | |
| Test status | |
| Simulation time | 171898080 ps |
| CPU time | 8.07 seconds |
| Started | Jul 31 07:57:42 PM PDT 24 |
| Finished | Jul 31 07:57:50 PM PDT 24 |
| Peak memory | 573840 kb |
| Host | smart-7eb0ac8d-d302-481c-85d9-8add67f3c515 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616025693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_same_source.1616025693 |
| Directory | /workspace/53.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke.3018139454 |
| Short name | T2690 |
| Test name | |
| Test status | |
| Simulation time | 246790826 ps |
| CPU time | 10.22 seconds |
| Started | Jul 31 07:57:43 PM PDT 24 |
| Finished | Jul 31 07:57:53 PM PDT 24 |
| Peak memory | 573828 kb |
| Host | smart-9dda3144-b45d-48a9-bb4f-7ad202b15035 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018139454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke.3018139454 |
| Directory | /workspace/53.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_large_delays.1271336953 |
| Short name | T2084 |
| Test name | |
| Test status | |
| Simulation time | 6250152821 ps |
| CPU time | 62.58 seconds |
| Started | Jul 31 07:57:41 PM PDT 24 |
| Finished | Jul 31 07:58:44 PM PDT 24 |
| Peak memory | 573900 kb |
| Host | smart-9e25eed3-7ddb-4966-b456-6bf7805803d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271336953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_large_delays.1271336953 |
| Directory | /workspace/53.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.1902184135 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 6144798177 ps |
| CPU time | 95.13 seconds |
| Started | Jul 31 07:57:40 PM PDT 24 |
| Finished | Jul 31 07:59:15 PM PDT 24 |
| Peak memory | 574568 kb |
| Host | smart-529ed065-e58a-4b91-a45c-80a3f9892369 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902184135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_slow_rsp.1902184135 |
| Directory | /workspace/53.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_zero_delays.2016655157 |
| Short name | T2259 |
| Test name | |
| Test status | |
| Simulation time | 44770518 ps |
| CPU time | 6.35 seconds |
| Started | Jul 31 07:57:41 PM PDT 24 |
| Finished | Jul 31 07:57:48 PM PDT 24 |
| Peak memory | 573824 kb |
| Host | smart-2c82ccc1-922a-462f-8358-c86e4421d474 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016655157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_zero_delay s.2016655157 |
| Directory | /workspace/53.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all.3291969134 |
| Short name | T2355 |
| Test name | |
| Test status | |
| Simulation time | 15834976483 ps |
| CPU time | 554.9 seconds |
| Started | Jul 31 07:57:41 PM PDT 24 |
| Finished | Jul 31 08:06:57 PM PDT 24 |
| Peak memory | 576800 kb |
| Host | smart-da23f141-0ac1-462e-a05a-d0fe1c7888dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291969134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all.3291969134 |
| Directory | /workspace/53.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.3356127897 |
| Short name | T2616 |
| Test name | |
| Test status | |
| Simulation time | 2149020907 ps |
| CPU time | 138.94 seconds |
| Started | Jul 31 07:57:50 PM PDT 24 |
| Finished | Jul 31 08:00:09 PM PDT 24 |
| Peak memory | 576232 kb |
| Host | smart-558457f6-8624-4a41-ae57-cd75de4bb0d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356127897 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_error.3356127897 |
| Directory | /workspace/53.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.1861576302 |
| Short name | T2734 |
| Test name | |
| Test status | |
| Simulation time | 7988916990 ps |
| CPU time | 473.14 seconds |
| Started | Jul 31 07:57:41 PM PDT 24 |
| Finished | Jul 31 08:05:34 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-97451973-7cf8-4f89-be09-1743a1af882a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861576302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all _with_rand_reset.1861576302 |
| Directory | /workspace/53.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.1645553987 |
| Short name | T2816 |
| Test name | |
| Test status | |
| Simulation time | 219140688 ps |
| CPU time | 56.86 seconds |
| Started | Jul 31 07:57:50 PM PDT 24 |
| Finished | Jul 31 07:58:47 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-05de2fba-edc9-41fb-aa6d-a5f8d9874048 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645553987 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_al l_with_reset_error.1645553987 |
| Directory | /workspace/53.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_unmapped_addr.213034385 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 210306398 ps |
| CPU time | 24.78 seconds |
| Started | Jul 31 07:57:40 PM PDT 24 |
| Finished | Jul 31 07:58:05 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-e9b8520c-da85-43d8-a406-104728100abe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213034385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_unmapped_addr.213034385 |
| Directory | /workspace/53.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device.3092263285 |
| Short name | T1999 |
| Test name | |
| Test status | |
| Simulation time | 1096556722 ps |
| CPU time | 47.54 seconds |
| Started | Jul 31 07:57:50 PM PDT 24 |
| Finished | Jul 31 07:58:38 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-a66c6798-57e9-49bf-a4b1-a2c64a85f978 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092263285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device .3092263285 |
| Directory | /workspace/54.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.646758586 |
| Short name | T2874 |
| Test name | |
| Test status | |
| Simulation time | 70166567320 ps |
| CPU time | 1196.21 seconds |
| Started | Jul 31 07:57:52 PM PDT 24 |
| Finished | Jul 31 08:17:48 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-5bf9f2bd-7d9d-4da1-8af5-30bdaeddd284 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646758586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_d evice_slow_rsp.646758586 |
| Directory | /workspace/54.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.1910857565 |
| Short name | T2179 |
| Test name | |
| Test status | |
| Simulation time | 170601929 ps |
| CPU time | 18.26 seconds |
| Started | Jul 31 07:57:51 PM PDT 24 |
| Finished | Jul 31 07:58:09 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-076cde81-36eb-458c-b9ea-092508b82656 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910857565 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_and_unmapped_add r.1910857565 |
| Directory | /workspace/54.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_random.1547292290 |
| Short name | T2161 |
| Test name | |
| Test status | |
| Simulation time | 1231782643 ps |
| CPU time | 42.76 seconds |
| Started | Jul 31 07:57:50 PM PDT 24 |
| Finished | Jul 31 07:58:33 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-0efff604-cbf0-4852-81ed-38edd41ac5b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547292290 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_random.1547292290 |
| Directory | /workspace/54.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random.3120995869 |
| Short name | T2064 |
| Test name | |
| Test status | |
| Simulation time | 67569177 ps |
| CPU time | 8.88 seconds |
| Started | Jul 31 07:57:50 PM PDT 24 |
| Finished | Jul 31 07:57:59 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-0612adfe-344a-4072-837d-030125f6a84e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120995869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random.3120995869 |
| Directory | /workspace/54.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_large_delays.2617373384 |
| Short name | T2148 |
| Test name | |
| Test status | |
| Simulation time | 103633491495 ps |
| CPU time | 1200.73 seconds |
| Started | Jul 31 07:57:50 PM PDT 24 |
| Finished | Jul 31 08:17:51 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-d503b5a9-eafd-452b-9c9c-dd6cd57667a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617373384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_large_delays.2617373384 |
| Directory | /workspace/54.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.4203425791 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 63103936238 ps |
| CPU time | 1038.96 seconds |
| Started | Jul 31 07:57:51 PM PDT 24 |
| Finished | Jul 31 08:15:10 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-0caffcb3-27cd-4b52-bbd8-084846cb6c2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203425791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_slow_rsp.4203425791 |
| Directory | /workspace/54.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_zero_delays.1654287387 |
| Short name | T1771 |
| Test name | |
| Test status | |
| Simulation time | 559547415 ps |
| CPU time | 45.91 seconds |
| Started | Jul 31 07:57:51 PM PDT 24 |
| Finished | Jul 31 07:58:37 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-3a07bf10-a6e6-43d3-9709-f1bf883e9bc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654287387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_zero_del ays.1654287387 |
| Directory | /workspace/54.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_same_source.1139813072 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 337858883 ps |
| CPU time | 28.57 seconds |
| Started | Jul 31 07:57:50 PM PDT 24 |
| Finished | Jul 31 07:58:19 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-6bcd5bb5-9300-4476-baaa-8e42c30b42c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139813072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_same_source.1139813072 |
| Directory | /workspace/54.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke.3553215344 |
| Short name | T2382 |
| Test name | |
| Test status | |
| Simulation time | 39766347 ps |
| CPU time | 5.86 seconds |
| Started | Jul 31 07:57:55 PM PDT 24 |
| Finished | Jul 31 07:58:01 PM PDT 24 |
| Peak memory | 573684 kb |
| Host | smart-1c3febee-a970-4240-8c15-bd7da61aae84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553215344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke.3553215344 |
| Directory | /workspace/54.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_large_delays.1464531699 |
| Short name | T2281 |
| Test name | |
| Test status | |
| Simulation time | 10041731417 ps |
| CPU time | 109.19 seconds |
| Started | Jul 31 07:57:51 PM PDT 24 |
| Finished | Jul 31 07:59:41 PM PDT 24 |
| Peak memory | 573936 kb |
| Host | smart-a10e4cec-a4f4-440e-bee0-df3fc4742fcd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464531699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_large_delays.1464531699 |
| Directory | /workspace/54.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.1185777222 |
| Short name | T2197 |
| Test name | |
| Test status | |
| Simulation time | 6791639138 ps |
| CPU time | 115.96 seconds |
| Started | Jul 31 07:57:49 PM PDT 24 |
| Finished | Jul 31 07:59:45 PM PDT 24 |
| Peak memory | 573924 kb |
| Host | smart-0b76f1a0-402e-4181-a7b7-1c37c2d455d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185777222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_slow_rsp.1185777222 |
| Directory | /workspace/54.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_zero_delays.466551999 |
| Short name | T1621 |
| Test name | |
| Test status | |
| Simulation time | 44908270 ps |
| CPU time | 6.21 seconds |
| Started | Jul 31 07:57:50 PM PDT 24 |
| Finished | Jul 31 07:57:57 PM PDT 24 |
| Peak memory | 573788 kb |
| Host | smart-7aa93473-8d6c-4ab5-aaa1-ea2fe80dfdd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466551999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_zero_delays .466551999 |
| Directory | /workspace/54.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all.917025516 |
| Short name | T2289 |
| Test name | |
| Test status | |
| Simulation time | 409288836 ps |
| CPU time | 29.59 seconds |
| Started | Jul 31 07:57:51 PM PDT 24 |
| Finished | Jul 31 07:58:20 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-5683f094-a0cb-46b1-9f6d-6ef4e197c497 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917025516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all.917025516 |
| Directory | /workspace/54.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.638870765 |
| Short name | T2749 |
| Test name | |
| Test status | |
| Simulation time | 18073768061 ps |
| CPU time | 580.27 seconds |
| Started | Jul 31 07:57:53 PM PDT 24 |
| Finished | Jul 31 08:07:33 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-d7ff7a5b-76d8-46fd-8844-ab80358fbca6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638870765 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_error.638870765 |
| Directory | /workspace/54.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.1959349708 |
| Short name | T1896 |
| Test name | |
| Test status | |
| Simulation time | 4056202257 ps |
| CPU time | 477.09 seconds |
| Started | Jul 31 07:57:50 PM PDT 24 |
| Finished | Jul 31 08:05:47 PM PDT 24 |
| Peak memory | 576724 kb |
| Host | smart-71cd2092-c65b-4f24-8d6a-b2a8d52eb76a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959349708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all _with_rand_reset.1959349708 |
| Directory | /workspace/54.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.905305942 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 1411652396 ps |
| CPU time | 248.93 seconds |
| Started | Jul 31 07:57:50 PM PDT 24 |
| Finished | Jul 31 08:01:59 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-77c7511c-b41e-4ef8-afc3-e770e36a3902 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905305942 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all _with_reset_error.905305942 |
| Directory | /workspace/54.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_unmapped_addr.2735224133 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 778502612 ps |
| CPU time | 32.92 seconds |
| Started | Jul 31 07:57:50 PM PDT 24 |
| Finished | Jul 31 07:58:23 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-fa5f17f8-7d90-4d11-88d1-b385dd3bd24e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735224133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_unmapped_addr.2735224133 |
| Directory | /workspace/54.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device.918296557 |
| Short name | T2308 |
| Test name | |
| Test status | |
| Simulation time | 2032768984 ps |
| CPU time | 78.05 seconds |
| Started | Jul 31 07:57:58 PM PDT 24 |
| Finished | Jul 31 07:59:16 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-037c366a-59ea-4aaf-9a21-5031cc3b3213 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918296557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device. 918296557 |
| Directory | /workspace/55.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.523410386 |
| Short name | T2162 |
| Test name | |
| Test status | |
| Simulation time | 10033978768 ps |
| CPU time | 175.58 seconds |
| Started | Jul 31 07:57:56 PM PDT 24 |
| Finished | Jul 31 08:00:51 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-47615899-a5a9-4374-b78a-c74b9a6b56cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523410386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_d evice_slow_rsp.523410386 |
| Directory | /workspace/55.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.161524142 |
| Short name | T2353 |
| Test name | |
| Test status | |
| Simulation time | 58214209 ps |
| CPU time | 8.53 seconds |
| Started | Jul 31 07:58:01 PM PDT 24 |
| Finished | Jul 31 07:58:10 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-bb6c478a-3bf7-4f9d-a73c-778dd82304fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161524142 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_and_unmapped_addr .161524142 |
| Directory | /workspace/55.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_random.383703184 |
| Short name | T1465 |
| Test name | |
| Test status | |
| Simulation time | 2160545246 ps |
| CPU time | 69.93 seconds |
| Started | Jul 31 07:57:57 PM PDT 24 |
| Finished | Jul 31 07:59:07 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-5be46a0c-9361-4b1c-a435-4599bff48c51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383703184 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_random.383703184 |
| Directory | /workspace/55.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random.4065636906 |
| Short name | T1936 |
| Test name | |
| Test status | |
| Simulation time | 459616067 ps |
| CPU time | 17.03 seconds |
| Started | Jul 31 07:57:59 PM PDT 24 |
| Finished | Jul 31 07:58:16 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-8738f590-e615-42a1-abcd-1ca57976d503 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065636906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random.4065636906 |
| Directory | /workspace/55.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_large_delays.2571097758 |
| Short name | T2817 |
| Test name | |
| Test status | |
| Simulation time | 36191825013 ps |
| CPU time | 380 seconds |
| Started | Jul 31 07:57:58 PM PDT 24 |
| Finished | Jul 31 08:04:18 PM PDT 24 |
| Peak memory | 576136 kb |
| Host | smart-0e8ebcbc-40e1-4745-88bf-09491974b1a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571097758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_large_delays.2571097758 |
| Directory | /workspace/55.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_slow_rsp.3741334064 |
| Short name | T2602 |
| Test name | |
| Test status | |
| Simulation time | 44049974918 ps |
| CPU time | 739.91 seconds |
| Started | Jul 31 07:57:56 PM PDT 24 |
| Finished | Jul 31 08:10:17 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-82bccc2c-42c9-4bdb-b536-d2ab4cb6632d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741334064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_slow_rsp.3741334064 |
| Directory | /workspace/55.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.3416390258 |
| Short name | T2828 |
| Test name | |
| Test status | |
| Simulation time | 275300480 ps |
| CPU time | 27.13 seconds |
| Started | Jul 31 07:57:58 PM PDT 24 |
| Finished | Jul 31 07:58:25 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-ff77b147-be1d-4f24-8dab-5c5d022723d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416390258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_zero_del ays.3416390258 |
| Directory | /workspace/55.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_same_source.3874631358 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 354759202 ps |
| CPU time | 27.06 seconds |
| Started | Jul 31 07:57:57 PM PDT 24 |
| Finished | Jul 31 07:58:24 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-4eb6130a-4304-4003-9c9d-be2b6747d674 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874631358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_same_source.3874631358 |
| Directory | /workspace/55.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke.516206596 |
| Short name | T1666 |
| Test name | |
| Test status | |
| Simulation time | 243364764 ps |
| CPU time | 10.38 seconds |
| Started | Jul 31 07:57:53 PM PDT 24 |
| Finished | Jul 31 07:58:03 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-110b5b04-6245-4149-8a03-dffcc77393a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516206596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke.516206596 |
| Directory | /workspace/55.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_large_delays.3157160927 |
| Short name | T1559 |
| Test name | |
| Test status | |
| Simulation time | 7229704154 ps |
| CPU time | 74.31 seconds |
| Started | Jul 31 07:57:56 PM PDT 24 |
| Finished | Jul 31 07:59:10 PM PDT 24 |
| Peak memory | 573872 kb |
| Host | smart-df14c366-cf5c-48ba-bd96-9d0504f3ffad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157160927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_large_delays.3157160927 |
| Directory | /workspace/55.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.2439281777 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 4572558876 ps |
| CPU time | 83.02 seconds |
| Started | Jul 31 07:57:56 PM PDT 24 |
| Finished | Jul 31 07:59:19 PM PDT 24 |
| Peak memory | 573840 kb |
| Host | smart-73ab6bea-1470-401e-b658-882fb8f497e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439281777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_slow_rsp.2439281777 |
| Directory | /workspace/55.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_zero_delays.3672604364 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 50583827 ps |
| CPU time | 6.66 seconds |
| Started | Jul 31 07:57:56 PM PDT 24 |
| Finished | Jul 31 07:58:03 PM PDT 24 |
| Peak memory | 574560 kb |
| Host | smart-e828bd9d-1609-4bd5-8f3d-f0d1d7ed3f95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672604364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_zero_delay s.3672604364 |
| Directory | /workspace/55.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all.1783291945 |
| Short name | T2204 |
| Test name | |
| Test status | |
| Simulation time | 999918591 ps |
| CPU time | 73.41 seconds |
| Started | Jul 31 07:58:02 PM PDT 24 |
| Finished | Jul 31 07:59:16 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-cde5e686-647a-41d4-8920-3c37ee6a901a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783291945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all.1783291945 |
| Directory | /workspace/55.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.3493398985 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 570458165 ps |
| CPU time | 239.35 seconds |
| Started | Jul 31 07:58:04 PM PDT 24 |
| Finished | Jul 31 08:02:03 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-007e65db-b304-4b6f-8c93-315f7987ab6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493398985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all _with_rand_reset.3493398985 |
| Directory | /workspace/55.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.3193779900 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 228356357 ps |
| CPU time | 64.4 seconds |
| Started | Jul 31 07:58:06 PM PDT 24 |
| Finished | Jul 31 07:59:11 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-39d67dc5-b48e-4573-a88d-ddc1a3319c67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193779900 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_al l_with_reset_error.3193779900 |
| Directory | /workspace/55.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_unmapped_addr.1187905103 |
| Short name | T1890 |
| Test name | |
| Test status | |
| Simulation time | 745494391 ps |
| CPU time | 35.25 seconds |
| Started | Jul 31 07:57:56 PM PDT 24 |
| Finished | Jul 31 07:58:31 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-ef751bcf-e1f5-481d-bdeb-d7cdb9d8058e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187905103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_unmapped_addr.1187905103 |
| Directory | /workspace/55.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device.1048877819 |
| Short name | T2296 |
| Test name | |
| Test status | |
| Simulation time | 249712950 ps |
| CPU time | 30.78 seconds |
| Started | Jul 31 07:58:09 PM PDT 24 |
| Finished | Jul 31 07:58:40 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-760e1c8e-1b52-4b5f-a9ba-0d39fba8cd0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048877819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device .1048877819 |
| Directory | /workspace/56.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.2000862438 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 111144816017 ps |
| CPU time | 2002.32 seconds |
| Started | Jul 31 07:58:10 PM PDT 24 |
| Finished | Jul 31 08:31:33 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-a2ef3e8a-41a6-4ce0-83c3-5928f1904d2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000862438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_ device_slow_rsp.2000862438 |
| Directory | /workspace/56.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.3432932587 |
| Short name | T1906 |
| Test name | |
| Test status | |
| Simulation time | 1354422751 ps |
| CPU time | 51.71 seconds |
| Started | Jul 31 07:58:19 PM PDT 24 |
| Finished | Jul 31 07:59:11 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-269456b8-f976-4ec3-944c-9a46e1526102 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432932587 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_and_unmapped_add r.3432932587 |
| Directory | /workspace/56.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_random.4100398478 |
| Short name | T2274 |
| Test name | |
| Test status | |
| Simulation time | 115250610 ps |
| CPU time | 11.6 seconds |
| Started | Jul 31 07:58:10 PM PDT 24 |
| Finished | Jul 31 07:58:22 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-1f97f770-3e47-4c17-b078-db810116cc79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100398478 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_random.4100398478 |
| Directory | /workspace/56.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random.2012963665 |
| Short name | T2538 |
| Test name | |
| Test status | |
| Simulation time | 70815776 ps |
| CPU time | 8.27 seconds |
| Started | Jul 31 07:58:07 PM PDT 24 |
| Finished | Jul 31 07:58:15 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-f52f2d4d-c3c7-4308-a54e-90414bde4811 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012963665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random.2012963665 |
| Directory | /workspace/56.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.80738732 |
| Short name | T1956 |
| Test name | |
| Test status | |
| Simulation time | 25506788987 ps |
| CPU time | 252.15 seconds |
| Started | Jul 31 07:58:09 PM PDT 24 |
| Finished | Jul 31 08:02:21 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-3eda5a38-ad03-4aca-bfe8-feb175c1f799 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80738732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_large_delays.80738732 |
| Directory | /workspace/56.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_slow_rsp.321311115 |
| Short name | T2492 |
| Test name | |
| Test status | |
| Simulation time | 18513595669 ps |
| CPU time | 323.15 seconds |
| Started | Jul 31 07:58:11 PM PDT 24 |
| Finished | Jul 31 08:03:34 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-9238f941-131f-4519-928e-4d6c4a965e85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321311115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_slow_rsp.321311115 |
| Directory | /workspace/56.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_zero_delays.3292182233 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 629820882 ps |
| CPU time | 53.68 seconds |
| Started | Jul 31 07:58:12 PM PDT 24 |
| Finished | Jul 31 07:59:06 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-8662e948-0bc7-4172-a43d-518651814d23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292182233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_zero_del ays.3292182233 |
| Directory | /workspace/56.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_same_source.4043183998 |
| Short name | T2645 |
| Test name | |
| Test status | |
| Simulation time | 1693628632 ps |
| CPU time | 50.41 seconds |
| Started | Jul 31 07:58:12 PM PDT 24 |
| Finished | Jul 31 07:59:03 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-13b75792-704e-46b4-a3ac-1fe2b1fa5d2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043183998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_same_source.4043183998 |
| Directory | /workspace/56.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke.1650316093 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 242084190 ps |
| CPU time | 9.88 seconds |
| Started | Jul 31 07:58:07 PM PDT 24 |
| Finished | Jul 31 07:58:17 PM PDT 24 |
| Peak memory | 574588 kb |
| Host | smart-e92777b8-87be-4ff0-ba13-44048d2ec21c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650316093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke.1650316093 |
| Directory | /workspace/56.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_large_delays.2741732950 |
| Short name | T2363 |
| Test name | |
| Test status | |
| Simulation time | 8716078996 ps |
| CPU time | 90.52 seconds |
| Started | Jul 31 07:58:04 PM PDT 24 |
| Finished | Jul 31 07:59:35 PM PDT 24 |
| Peak memory | 573928 kb |
| Host | smart-dee0dadf-466b-43e6-af0b-c0218c81a90a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741732950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_large_delays.2741732950 |
| Directory | /workspace/56.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.2929840090 |
| Short name | T1732 |
| Test name | |
| Test status | |
| Simulation time | 5157318065 ps |
| CPU time | 87.17 seconds |
| Started | Jul 31 07:58:07 PM PDT 24 |
| Finished | Jul 31 07:59:34 PM PDT 24 |
| Peak memory | 574584 kb |
| Host | smart-9fd131bf-a93c-4712-8beb-a48b287401ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929840090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_slow_rsp.2929840090 |
| Directory | /workspace/56.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_zero_delays.2555327353 |
| Short name | T2038 |
| Test name | |
| Test status | |
| Simulation time | 48248208 ps |
| CPU time | 6.57 seconds |
| Started | Jul 31 07:58:04 PM PDT 24 |
| Finished | Jul 31 07:58:11 PM PDT 24 |
| Peak memory | 573816 kb |
| Host | smart-a96784e0-cf95-4d89-b487-d8192d796e85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555327353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_zero_delay s.2555327353 |
| Directory | /workspace/56.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all.371782519 |
| Short name | T2324 |
| Test name | |
| Test status | |
| Simulation time | 1162685423 ps |
| CPU time | 111.42 seconds |
| Started | Jul 31 07:58:14 PM PDT 24 |
| Finished | Jul 31 08:00:06 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-d3299ca4-08dc-433e-af28-0f5e4de3c589 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371782519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all.371782519 |
| Directory | /workspace/56.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.825109828 |
| Short name | T2838 |
| Test name | |
| Test status | |
| Simulation time | 1672759080 ps |
| CPU time | 126.16 seconds |
| Started | Jul 31 07:58:14 PM PDT 24 |
| Finished | Jul 31 08:00:20 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-115612ff-fa53-4500-b7e2-2ca178d1a19e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825109828 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_error.825109828 |
| Directory | /workspace/56.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.3725082352 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 306461474 ps |
| CPU time | 66.7 seconds |
| Started | Jul 31 07:58:13 PM PDT 24 |
| Finished | Jul 31 07:59:20 PM PDT 24 |
| Peak memory | 576700 kb |
| Host | smart-82a995f0-8363-4e5c-9d2d-e2197319a509 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725082352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all _with_rand_reset.3725082352 |
| Directory | /workspace/56.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.1638894717 |
| Short name | T2287 |
| Test name | |
| Test status | |
| Simulation time | 2375558060 ps |
| CPU time | 247.11 seconds |
| Started | Jul 31 07:58:14 PM PDT 24 |
| Finished | Jul 31 08:02:21 PM PDT 24 |
| Peak memory | 576732 kb |
| Host | smart-ca1601bd-4624-4e31-aadf-968ff9c65858 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638894717 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_al l_with_reset_error.1638894717 |
| Directory | /workspace/56.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_unmapped_addr.2665326606 |
| Short name | T2665 |
| Test name | |
| Test status | |
| Simulation time | 155114504 ps |
| CPU time | 20.56 seconds |
| Started | Jul 31 07:58:19 PM PDT 24 |
| Finished | Jul 31 07:58:40 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-6dd744a7-cdd2-40dd-8123-0c3d8fbe3810 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665326606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_unmapped_addr.2665326606 |
| Directory | /workspace/56.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device.3691469793 |
| Short name | T1450 |
| Test name | |
| Test status | |
| Simulation time | 183985520 ps |
| CPU time | 19.37 seconds |
| Started | Jul 31 07:58:21 PM PDT 24 |
| Finished | Jul 31 07:58:40 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-8ae99ecf-a17b-487e-bbde-3d6cf1b4f93b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691469793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device .3691469793 |
| Directory | /workspace/57.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.2899548016 |
| Short name | T2547 |
| Test name | |
| Test status | |
| Simulation time | 21657181959 ps |
| CPU time | 374.49 seconds |
| Started | Jul 31 07:58:22 PM PDT 24 |
| Finished | Jul 31 08:04:36 PM PDT 24 |
| Peak memory | 576124 kb |
| Host | smart-f84bcb66-7d76-40ac-af95-7fa89929f527 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899548016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_ device_slow_rsp.2899548016 |
| Directory | /workspace/57.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.4118812906 |
| Short name | T2177 |
| Test name | |
| Test status | |
| Simulation time | 208202812 ps |
| CPU time | 22.72 seconds |
| Started | Jul 31 07:58:20 PM PDT 24 |
| Finished | Jul 31 07:58:43 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-1fda3798-1f7d-4003-acec-07737b7758f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118812906 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_and_unmapped_add r.4118812906 |
| Directory | /workspace/57.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_random.2252874292 |
| Short name | T2195 |
| Test name | |
| Test status | |
| Simulation time | 1973536403 ps |
| CPU time | 58.33 seconds |
| Started | Jul 31 07:58:21 PM PDT 24 |
| Finished | Jul 31 07:59:19 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-2328d38b-c784-47ee-ae22-f427554588c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252874292 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_random.2252874292 |
| Directory | /workspace/57.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random.2424081352 |
| Short name | T1848 |
| Test name | |
| Test status | |
| Simulation time | 552378405 ps |
| CPU time | 47.99 seconds |
| Started | Jul 31 07:58:19 PM PDT 24 |
| Finished | Jul 31 07:59:08 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-042d9c4e-3b53-4e1d-947b-77aab8878dac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424081352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random.2424081352 |
| Directory | /workspace/57.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_large_delays.4245054538 |
| Short name | T1713 |
| Test name | |
| Test status | |
| Simulation time | 16194798869 ps |
| CPU time | 165.42 seconds |
| Started | Jul 31 07:58:25 PM PDT 24 |
| Finished | Jul 31 08:01:10 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-0f87baee-56da-496e-9f2b-34b360cb19f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245054538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_large_delays.4245054538 |
| Directory | /workspace/57.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_slow_rsp.2255324196 |
| Short name | T2726 |
| Test name | |
| Test status | |
| Simulation time | 53723278727 ps |
| CPU time | 872.09 seconds |
| Started | Jul 31 07:58:20 PM PDT 24 |
| Finished | Jul 31 08:12:52 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-e7386fe4-f8ae-443a-9688-1e5b35f5949f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255324196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_slow_rsp.2255324196 |
| Directory | /workspace/57.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_zero_delays.3281926730 |
| Short name | T1985 |
| Test name | |
| Test status | |
| Simulation time | 518359496 ps |
| CPU time | 44.81 seconds |
| Started | Jul 31 07:58:23 PM PDT 24 |
| Finished | Jul 31 07:59:08 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-eafd1f1d-b018-41f9-ab33-0b67a102ff3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281926730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_zero_del ays.3281926730 |
| Directory | /workspace/57.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_same_source.1787562033 |
| Short name | T1873 |
| Test name | |
| Test status | |
| Simulation time | 2090591865 ps |
| CPU time | 62.8 seconds |
| Started | Jul 31 07:58:21 PM PDT 24 |
| Finished | Jul 31 07:59:23 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-9555bb01-cf1e-44eb-9470-72b7e52096ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787562033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_same_source.1787562033 |
| Directory | /workspace/57.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke.282219416 |
| Short name | T2625 |
| Test name | |
| Test status | |
| Simulation time | 43558366 ps |
| CPU time | 5.98 seconds |
| Started | Jul 31 07:58:14 PM PDT 24 |
| Finished | Jul 31 07:58:20 PM PDT 24 |
| Peak memory | 573820 kb |
| Host | smart-31e8b1fd-0f29-4588-846a-7be4e672dd3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282219416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke.282219416 |
| Directory | /workspace/57.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_large_delays.3234790971 |
| Short name | T1456 |
| Test name | |
| Test status | |
| Simulation time | 6909220977 ps |
| CPU time | 63.99 seconds |
| Started | Jul 31 07:58:13 PM PDT 24 |
| Finished | Jul 31 07:59:17 PM PDT 24 |
| Peak memory | 573904 kb |
| Host | smart-3e484189-abe9-4593-8519-6d597b14346a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234790971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_large_delays.3234790971 |
| Directory | /workspace/57.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.3186100940 |
| Short name | T1575 |
| Test name | |
| Test status | |
| Simulation time | 5734001646 ps |
| CPU time | 99.85 seconds |
| Started | Jul 31 07:58:16 PM PDT 24 |
| Finished | Jul 31 07:59:56 PM PDT 24 |
| Peak memory | 574580 kb |
| Host | smart-1f98ceb9-acef-4341-8bb5-2668c51fc5e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186100940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_slow_rsp.3186100940 |
| Directory | /workspace/57.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_zero_delays.2711447574 |
| Short name | T2608 |
| Test name | |
| Test status | |
| Simulation time | 46052091 ps |
| CPU time | 6.32 seconds |
| Started | Jul 31 07:58:14 PM PDT 24 |
| Finished | Jul 31 07:58:20 PM PDT 24 |
| Peak memory | 574464 kb |
| Host | smart-d9107beb-eeb4-4907-8656-d0daeb972c3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711447574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_zero_delay s.2711447574 |
| Directory | /workspace/57.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all.469349726 |
| Short name | T1836 |
| Test name | |
| Test status | |
| Simulation time | 18788412250 ps |
| CPU time | 694.42 seconds |
| Started | Jul 31 07:58:19 PM PDT 24 |
| Finished | Jul 31 08:09:54 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-b98c2499-1065-4c32-adaf-554e04c6d8ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469349726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all.469349726 |
| Directory | /workspace/57.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.2653613618 |
| Short name | T1900 |
| Test name | |
| Test status | |
| Simulation time | 1118065157 ps |
| CPU time | 32.35 seconds |
| Started | Jul 31 07:58:24 PM PDT 24 |
| Finished | Jul 31 07:58:57 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-35cfc4e8-7e2a-4eb5-89ad-91d7589c3769 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653613618 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_error.2653613618 |
| Directory | /workspace/57.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.3095458925 |
| Short name | T2376 |
| Test name | |
| Test status | |
| Simulation time | 2152348544 ps |
| CPU time | 271.35 seconds |
| Started | Jul 31 07:58:26 PM PDT 24 |
| Finished | Jul 31 08:02:58 PM PDT 24 |
| Peak memory | 576760 kb |
| Host | smart-8b3286eb-e54e-48c8-bd06-990680a3ee01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095458925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all _with_rand_reset.3095458925 |
| Directory | /workspace/57.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.561579572 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 1389713400 ps |
| CPU time | 49.32 seconds |
| Started | Jul 31 07:58:25 PM PDT 24 |
| Finished | Jul 31 07:59:14 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-2ab6aff5-359d-46c5-b2da-73f200624b62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561579572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_unmapped_addr.561579572 |
| Directory | /workspace/57.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device.1035257122 |
| Short name | T1779 |
| Test name | |
| Test status | |
| Simulation time | 86280658 ps |
| CPU time | 11.41 seconds |
| Started | Jul 31 07:58:26 PM PDT 24 |
| Finished | Jul 31 07:58:37 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-21ea5276-857d-448b-b38b-d8438a292412 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035257122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device .1035257122 |
| Directory | /workspace/58.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.517843147 |
| Short name | T1944 |
| Test name | |
| Test status | |
| Simulation time | 62510433295 ps |
| CPU time | 1065.67 seconds |
| Started | Jul 31 07:58:25 PM PDT 24 |
| Finished | Jul 31 08:16:11 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-7719fb8b-f897-490a-a157-7bde88e1f1f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517843147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_d evice_slow_rsp.517843147 |
| Directory | /workspace/58.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.978531258 |
| Short name | T1765 |
| Test name | |
| Test status | |
| Simulation time | 183550853 ps |
| CPU time | 17.56 seconds |
| Started | Jul 31 07:58:30 PM PDT 24 |
| Finished | Jul 31 07:58:48 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-9395fc24-c1ec-4840-9a1d-63b3c6368dfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978531258 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_and_unmapped_addr .978531258 |
| Directory | /workspace/58.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_random.3065969237 |
| Short name | T1683 |
| Test name | |
| Test status | |
| Simulation time | 508691336 ps |
| CPU time | 41.68 seconds |
| Started | Jul 31 07:58:32 PM PDT 24 |
| Finished | Jul 31 07:59:14 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-769157f1-3566-4150-9995-5f3b6d9f4652 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065969237 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_random.3065969237 |
| Directory | /workspace/58.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random.3577129265 |
| Short name | T2546 |
| Test name | |
| Test status | |
| Simulation time | 430105243 ps |
| CPU time | 35.8 seconds |
| Started | Jul 31 07:58:24 PM PDT 24 |
| Finished | Jul 31 07:59:00 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-47327546-c30a-4c3e-ae4b-970ee4dcf861 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577129265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random.3577129265 |
| Directory | /workspace/58.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_large_delays.2725039111 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 29480634933 ps |
| CPU time | 292.82 seconds |
| Started | Jul 31 07:58:26 PM PDT 24 |
| Finished | Jul 31 08:03:19 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-3d4ba025-bdd6-403f-806e-7d1a284f930b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725039111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_large_delays.2725039111 |
| Directory | /workspace/58.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.202016991 |
| Short name | T2132 |
| Test name | |
| Test status | |
| Simulation time | 35930716151 ps |
| CPU time | 617.09 seconds |
| Started | Jul 31 07:58:30 PM PDT 24 |
| Finished | Jul 31 08:08:47 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-9c6d50a1-081c-4326-913e-5f55c4f18351 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202016991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_slow_rsp.202016991 |
| Directory | /workspace/58.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_zero_delays.3419556108 |
| Short name | T2321 |
| Test name | |
| Test status | |
| Simulation time | 395967719 ps |
| CPU time | 39.82 seconds |
| Started | Jul 31 07:58:25 PM PDT 24 |
| Finished | Jul 31 07:59:05 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-0ad9ec71-8924-4633-880d-922e5ee73f9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419556108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_zero_del ays.3419556108 |
| Directory | /workspace/58.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_same_source.2179826309 |
| Short name | T2078 |
| Test name | |
| Test status | |
| Simulation time | 736171480 ps |
| CPU time | 20.39 seconds |
| Started | Jul 31 07:58:25 PM PDT 24 |
| Finished | Jul 31 07:58:46 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-1163286e-6545-4cb2-9c3a-3d7f0b8ac165 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179826309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_same_source.2179826309 |
| Directory | /workspace/58.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke.4168166394 |
| Short name | T2380 |
| Test name | |
| Test status | |
| Simulation time | 43134461 ps |
| CPU time | 6.56 seconds |
| Started | Jul 31 07:58:26 PM PDT 24 |
| Finished | Jul 31 07:58:33 PM PDT 24 |
| Peak memory | 573840 kb |
| Host | smart-26a1120c-b12e-4de1-8509-caa0b38d80c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168166394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke.4168166394 |
| Directory | /workspace/58.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.542382038 |
| Short name | T2857 |
| Test name | |
| Test status | |
| Simulation time | 7298592349 ps |
| CPU time | 78.69 seconds |
| Started | Jul 31 07:58:29 PM PDT 24 |
| Finished | Jul 31 07:59:48 PM PDT 24 |
| Peak memory | 573780 kb |
| Host | smart-283ed789-afae-45dc-9b5f-22ef0c550316 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542382038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_large_delays.542382038 |
| Directory | /workspace/58.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.1708708597 |
| Short name | T2787 |
| Test name | |
| Test status | |
| Simulation time | 5068483459 ps |
| CPU time | 82.16 seconds |
| Started | Jul 31 07:58:26 PM PDT 24 |
| Finished | Jul 31 07:59:48 PM PDT 24 |
| Peak memory | 573920 kb |
| Host | smart-c745c772-40c2-4db6-aa01-5b65daf4c06b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708708597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_slow_rsp.1708708597 |
| Directory | /workspace/58.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.3067870739 |
| Short name | T1665 |
| Test name | |
| Test status | |
| Simulation time | 47624867 ps |
| CPU time | 6.12 seconds |
| Started | Jul 31 07:58:26 PM PDT 24 |
| Finished | Jul 31 07:58:32 PM PDT 24 |
| Peak memory | 573908 kb |
| Host | smart-76c40e50-0a9f-4fb0-b174-8f3d50a14a4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067870739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_zero_delay s.3067870739 |
| Directory | /workspace/58.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all.104555497 |
| Short name | T2221 |
| Test name | |
| Test status | |
| Simulation time | 858766205 ps |
| CPU time | 81.78 seconds |
| Started | Jul 31 07:58:32 PM PDT 24 |
| Finished | Jul 31 07:59:54 PM PDT 24 |
| Peak memory | 576392 kb |
| Host | smart-661d8c3a-a671-49ee-82bc-651917b579c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104555497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all.104555497 |
| Directory | /workspace/58.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.2504840867 |
| Short name | T2500 |
| Test name | |
| Test status | |
| Simulation time | 8954270963 ps |
| CPU time | 320.22 seconds |
| Started | Jul 31 07:58:31 PM PDT 24 |
| Finished | Jul 31 08:03:51 PM PDT 24 |
| Peak memory | 576200 kb |
| Host | smart-e232b99f-cc6f-4ec7-8384-ddd26c80f160 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504840867 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_error.2504840867 |
| Directory | /workspace/58.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.581605601 |
| Short name | T2736 |
| Test name | |
| Test status | |
| Simulation time | 289218659 ps |
| CPU time | 125.54 seconds |
| Started | Jul 31 07:58:30 PM PDT 24 |
| Finished | Jul 31 08:00:36 PM PDT 24 |
| Peak memory | 576716 kb |
| Host | smart-8d1afb44-4c54-448a-97ce-65aaf080d714 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581605601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_ with_rand_reset.581605601 |
| Directory | /workspace/58.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.267724081 |
| Short name | T1846 |
| Test name | |
| Test status | |
| Simulation time | 4399968083 ps |
| CPU time | 490 seconds |
| Started | Jul 31 07:58:32 PM PDT 24 |
| Finished | Jul 31 08:06:42 PM PDT 24 |
| Peak memory | 582800 kb |
| Host | smart-3553fc77-f910-429c-8221-a54aa5cc0f76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267724081 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all _with_reset_error.267724081 |
| Directory | /workspace/58.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_unmapped_addr.3558619191 |
| Short name | T2539 |
| Test name | |
| Test status | |
| Simulation time | 220364197 ps |
| CPU time | 11.09 seconds |
| Started | Jul 31 07:58:33 PM PDT 24 |
| Finished | Jul 31 07:58:44 PM PDT 24 |
| Peak memory | 576076 kb |
| Host | smart-47b4ceea-a5b4-41f5-964e-3a973b0e4c33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558619191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_unmapped_addr.3558619191 |
| Directory | /workspace/58.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device.2124529919 |
| Short name | T1538 |
| Test name | |
| Test status | |
| Simulation time | 2024728532 ps |
| CPU time | 92.96 seconds |
| Started | Jul 31 07:58:37 PM PDT 24 |
| Finished | Jul 31 08:00:10 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-9fca8ed6-328f-40a6-90f1-e399d3656d9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124529919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device .2124529919 |
| Directory | /workspace/59.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.2152328334 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 56132415870 ps |
| CPU time | 971.38 seconds |
| Started | Jul 31 07:58:52 PM PDT 24 |
| Finished | Jul 31 08:15:03 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-62fda9aa-44ce-46fb-a9e5-002f63d7375a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152328334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_ device_slow_rsp.2152328334 |
| Directory | /workspace/59.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.3652016698 |
| Short name | T2144 |
| Test name | |
| Test status | |
| Simulation time | 1162105917 ps |
| CPU time | 49.75 seconds |
| Started | Jul 31 07:58:38 PM PDT 24 |
| Finished | Jul 31 07:59:27 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-f217b855-fa92-4248-a7b3-2b4d6f79bc6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652016698 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_and_unmapped_add r.3652016698 |
| Directory | /workspace/59.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_random.2695990801 |
| Short name | T2884 |
| Test name | |
| Test status | |
| Simulation time | 2399387475 ps |
| CPU time | 76.41 seconds |
| Started | Jul 31 07:58:51 PM PDT 24 |
| Finished | Jul 31 08:00:08 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-72993585-6fad-4403-bfb9-aa18e1dda5b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695990801 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_random.2695990801 |
| Directory | /workspace/59.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random.2026354433 |
| Short name | T1801 |
| Test name | |
| Test status | |
| Simulation time | 407487421 ps |
| CPU time | 34.76 seconds |
| Started | Jul 31 07:58:51 PM PDT 24 |
| Finished | Jul 31 07:59:26 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-8158915c-b519-407f-99da-af18d7b22190 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026354433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random.2026354433 |
| Directory | /workspace/59.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_large_delays.2048226139 |
| Short name | T1791 |
| Test name | |
| Test status | |
| Simulation time | 101899895144 ps |
| CPU time | 1195.03 seconds |
| Started | Jul 31 07:58:51 PM PDT 24 |
| Finished | Jul 31 08:18:46 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-eda24ace-7e98-49a4-94dc-93ffc2984c7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048226139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_large_delays.2048226139 |
| Directory | /workspace/59.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.3894773226 |
| Short name | T2597 |
| Test name | |
| Test status | |
| Simulation time | 20783022161 ps |
| CPU time | 334.25 seconds |
| Started | Jul 31 07:58:38 PM PDT 24 |
| Finished | Jul 31 08:04:12 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-a81bc25c-dd9f-4e11-976a-562131f365f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894773226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_slow_rsp.3894773226 |
| Directory | /workspace/59.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_zero_delays.3597918291 |
| Short name | T2036 |
| Test name | |
| Test status | |
| Simulation time | 273354793 ps |
| CPU time | 22.4 seconds |
| Started | Jul 31 07:58:52 PM PDT 24 |
| Finished | Jul 31 07:59:14 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-e6b3971f-d268-4307-8b13-d82d8800c0b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597918291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_zero_del ays.3597918291 |
| Directory | /workspace/59.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_same_source.40557404 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 1320959990 ps |
| CPU time | 40.11 seconds |
| Started | Jul 31 07:58:36 PM PDT 24 |
| Finished | Jul 31 07:59:17 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-68aa11cd-7864-48b4-a608-4e41551ab438 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40557404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_same_source.40557404 |
| Directory | /workspace/59.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke.2416960157 |
| Short name | T1787 |
| Test name | |
| Test status | |
| Simulation time | 172476579 ps |
| CPU time | 7.74 seconds |
| Started | Jul 31 07:58:31 PM PDT 24 |
| Finished | Jul 31 07:58:39 PM PDT 24 |
| Peak memory | 573820 kb |
| Host | smart-e8f40d6a-1934-4bc6-b003-f34b42ee6271 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416960157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke.2416960157 |
| Directory | /workspace/59.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.122343133 |
| Short name | T2638 |
| Test name | |
| Test status | |
| Simulation time | 8792213883 ps |
| CPU time | 98.55 seconds |
| Started | Jul 31 07:58:39 PM PDT 24 |
| Finished | Jul 31 08:00:17 PM PDT 24 |
| Peak memory | 574584 kb |
| Host | smart-5fdc1295-7d80-4cfe-86d3-71730395e6c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122343133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_large_delays.122343133 |
| Directory | /workspace/59.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.831146241 |
| Short name | T2571 |
| Test name | |
| Test status | |
| Simulation time | 3443680618 ps |
| CPU time | 54.52 seconds |
| Started | Jul 31 07:58:37 PM PDT 24 |
| Finished | Jul 31 07:59:32 PM PDT 24 |
| Peak memory | 573976 kb |
| Host | smart-b8e525fc-08d9-48ae-bff1-8dbafc0ededd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831146241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_slow_rsp.831146241 |
| Directory | /workspace/59.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_zero_delays.1562298882 |
| Short name | T1655 |
| Test name | |
| Test status | |
| Simulation time | 51378688 ps |
| CPU time | 6.37 seconds |
| Started | Jul 31 07:58:37 PM PDT 24 |
| Finished | Jul 31 07:58:44 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-91502976-3556-440d-8c08-d845c29cc70e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562298882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_zero_delay s.1562298882 |
| Directory | /workspace/59.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all.2200778120 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 7856117287 ps |
| CPU time | 310.85 seconds |
| Started | Jul 31 07:58:38 PM PDT 24 |
| Finished | Jul 31 08:03:49 PM PDT 24 |
| Peak memory | 576728 kb |
| Host | smart-7a956126-9c62-406e-ad7f-12ddab3ba1d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200778120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all.2200778120 |
| Directory | /workspace/59.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.3352629300 |
| Short name | T1950 |
| Test name | |
| Test status | |
| Simulation time | 4957402302 ps |
| CPU time | 159.56 seconds |
| Started | Jul 31 07:58:51 PM PDT 24 |
| Finished | Jul 31 08:01:31 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-b4059833-9485-4f3f-b5f5-a3c2c955e154 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352629300 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_error.3352629300 |
| Directory | /workspace/59.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.3867292701 |
| Short name | T2891 |
| Test name | |
| Test status | |
| Simulation time | 160699053 ps |
| CPU time | 59.73 seconds |
| Started | Jul 31 07:58:39 PM PDT 24 |
| Finished | Jul 31 07:59:39 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-8ecf70bb-eb8f-4eb1-ab58-5bbfd6a179ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867292701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all _with_rand_reset.3867292701 |
| Directory | /workspace/59.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.3268799466 |
| Short name | T2387 |
| Test name | |
| Test status | |
| Simulation time | 3461629126 ps |
| CPU time | 282.57 seconds |
| Started | Jul 31 07:58:44 PM PDT 24 |
| Finished | Jul 31 08:03:26 PM PDT 24 |
| Peak memory | 576800 kb |
| Host | smart-1ec49b32-2e64-4fb7-846a-6781236c3eec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268799466 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_al l_with_reset_error.3268799466 |
| Directory | /workspace/59.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_unmapped_addr.2087208738 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 517697039 ps |
| CPU time | 21.62 seconds |
| Started | Jul 31 07:58:36 PM PDT 24 |
| Finished | Jul 31 07:58:58 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-e1cfa330-b248-4dc8-ba85-2657bda8949f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087208738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_unmapped_addr.2087208738 |
| Directory | /workspace/59.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.1333504877 |
| Short name | T2212 |
| Test name | |
| Test status | |
| Simulation time | 7544949400 ps |
| CPU time | 459.65 seconds |
| Started | Jul 31 07:47:08 PM PDT 24 |
| Finished | Jul 31 07:54:48 PM PDT 24 |
| Peak memory | 638620 kb |
| Host | smart-5fc3d206-91e5-4f96-97f0-542158a8375d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333504877 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 6.chip_csr_mem_rw_with_rand_reset.1333504877 |
| Directory | /workspace/6.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_csr_rw.2039989033 |
| Short name | T1564 |
| Test name | |
| Test status | |
| Simulation time | 3895205711 ps |
| CPU time | 322.91 seconds |
| Started | Jul 31 07:47:11 PM PDT 24 |
| Finished | Jul 31 07:52:34 PM PDT 24 |
| Peak memory | 597112 kb |
| Host | smart-7c2a485b-5f08-4584-941d-55bb9737c645 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039989033 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_csr_rw.2039989033 |
| Directory | /workspace/6.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.3148034597 |
| Short name | T2292 |
| Test name | |
| Test status | |
| Simulation time | 15680670586 ps |
| CPU time | 1889.78 seconds |
| Started | Jul 31 07:46:48 PM PDT 24 |
| Finished | Jul 31 08:18:18 PM PDT 24 |
| Peak memory | 592936 kb |
| Host | smart-c7406afe-1f23-403c-af3d-1fb7d2334f14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148034597 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 6.chip_same_csr_outstanding.3148034597 |
| Directory | /workspace/6.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_tl_errors.35294442 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 3798252300 ps |
| CPU time | 220.8 seconds |
| Started | Jul 31 07:46:50 PM PDT 24 |
| Finished | Jul 31 07:50:31 PM PDT 24 |
| Peak memory | 603724 kb |
| Host | smart-beb4f620-56df-44d7-b28f-1b7b99d26d1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35294442 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_tl_errors.35294442 |
| Directory | /workspace/6.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device.2177848881 |
| Short name | T2519 |
| Test name | |
| Test status | |
| Simulation time | 300798594 ps |
| CPU time | 14.11 seconds |
| Started | Jul 31 07:47:03 PM PDT 24 |
| Finished | Jul 31 07:47:17 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-559037ee-1281-450e-b976-42146b21dd04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177848881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device. 2177848881 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.170227124 |
| Short name | T2580 |
| Test name | |
| Test status | |
| Simulation time | 143404234823 ps |
| CPU time | 2503.77 seconds |
| Started | Jul 31 07:47:00 PM PDT 24 |
| Finished | Jul 31 08:28:44 PM PDT 24 |
| Peak memory | 576104 kb |
| Host | smart-f3fdfbc0-066b-42a9-8622-62803d8cadd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170227124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_de vice_slow_rsp.170227124 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.1560938809 |
| Short name | T2086 |
| Test name | |
| Test status | |
| Simulation time | 1260584221 ps |
| CPU time | 45.33 seconds |
| Started | Jul 31 07:47:08 PM PDT 24 |
| Finished | Jul 31 07:47:53 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-a95cabb9-8d1b-4f58-a436-ff2cb0ffb2c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560938809 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr .1560938809 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_random.3222106370 |
| Short name | T2364 |
| Test name | |
| Test status | |
| Simulation time | 1843664902 ps |
| CPU time | 68.2 seconds |
| Started | Jul 31 07:47:01 PM PDT 24 |
| Finished | Jul 31 07:48:10 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-f286ea40-f12f-47cd-b047-0e418de77382 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222106370 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.3222106370 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random.2774171646 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 2620124746 ps |
| CPU time | 87.37 seconds |
| Started | Jul 31 07:46:55 PM PDT 24 |
| Finished | Jul 31 07:48:22 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-d553caf9-284d-4cff-8523-e5b56c401129 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774171646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random.2774171646 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_large_delays.1375739583 |
| Short name | T2934 |
| Test name | |
| Test status | |
| Simulation time | 30087062084 ps |
| CPU time | 306.34 seconds |
| Started | Jul 31 07:46:57 PM PDT 24 |
| Finished | Jul 31 07:52:04 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-4e7a95d2-ae1f-4124-b9cb-61a44d7ae845 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375739583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.1375739583 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_slow_rsp.687855290 |
| Short name | T1964 |
| Test name | |
| Test status | |
| Simulation time | 19118171581 ps |
| CPU time | 306.19 seconds |
| Started | Jul 31 07:46:58 PM PDT 24 |
| Finished | Jul 31 07:52:05 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-f02a6dca-846a-49f0-bcb1-0195bfcb3004 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687855290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.687855290 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_zero_delays.4143400203 |
| Short name | T2617 |
| Test name | |
| Test status | |
| Simulation time | 340945570 ps |
| CPU time | 31.49 seconds |
| Started | Jul 31 07:46:55 PM PDT 24 |
| Finished | Jul 31 07:47:27 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-e2f920fe-5272-48c0-8533-fde04863cef1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143400203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_dela ys.4143400203 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_same_source.2943493043 |
| Short name | T2495 |
| Test name | |
| Test status | |
| Simulation time | 78616657 ps |
| CPU time | 8.48 seconds |
| Started | Jul 31 07:47:00 PM PDT 24 |
| Finished | Jul 31 07:47:08 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-1c85b520-dfcf-4e98-aaed-80acf7e6306f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943493043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.2943493043 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke.2690672435 |
| Short name | T1533 |
| Test name | |
| Test status | |
| Simulation time | 50384196 ps |
| CPU time | 6.85 seconds |
| Started | Jul 31 07:46:49 PM PDT 24 |
| Finished | Jul 31 07:46:56 PM PDT 24 |
| Peak memory | 573860 kb |
| Host | smart-5b821227-09e6-48e5-914a-cd01003be3bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690672435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.2690672435 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_large_delays.1823161447 |
| Short name | T2588 |
| Test name | |
| Test status | |
| Simulation time | 5169291538 ps |
| CPU time | 55.99 seconds |
| Started | Jul 31 07:46:57 PM PDT 24 |
| Finished | Jul 31 07:47:53 PM PDT 24 |
| Peak memory | 573916 kb |
| Host | smart-18e406e4-001b-4d6a-939c-909f96552aea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823161447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.1823161447 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.1619677229 |
| Short name | T2029 |
| Test name | |
| Test status | |
| Simulation time | 5848243417 ps |
| CPU time | 105.73 seconds |
| Started | Jul 31 07:46:56 PM PDT 24 |
| Finished | Jul 31 07:48:41 PM PDT 24 |
| Peak memory | 573880 kb |
| Host | smart-e1fc5481-b9d0-4dbe-beb4-d7f161826e5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619677229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.1619677229 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.3201693559 |
| Short name | T2609 |
| Test name | |
| Test status | |
| Simulation time | 39897117 ps |
| CPU time | 5.63 seconds |
| Started | Jul 31 07:46:54 PM PDT 24 |
| Finished | Jul 31 07:47:00 PM PDT 24 |
| Peak memory | 573644 kb |
| Host | smart-61f1eaee-684a-4340-8412-bc503fc1e1b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201693559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays .3201693559 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_error.656335318 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 5480097858 ps |
| CPU time | 217.58 seconds |
| Started | Jul 31 07:47:10 PM PDT 24 |
| Finished | Jul 31 07:50:48 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-de219411-0a34-485d-b226-d4089f8d6bf2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656335318 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.656335318 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.1534638967 |
| Short name | T1997 |
| Test name | |
| Test status | |
| Simulation time | 195105035 ps |
| CPU time | 58.74 seconds |
| Started | Jul 31 07:47:07 PM PDT 24 |
| Finished | Jul 31 07:48:06 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-0218a874-d522-449a-a689-a53099d50c19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534638967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_ with_rand_reset.1534638967 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.1240703601 |
| Short name | T2075 |
| Test name | |
| Test status | |
| Simulation time | 17028801 ps |
| CPU time | 18.32 seconds |
| Started | Jul 31 07:47:09 PM PDT 24 |
| Finished | Jul 31 07:47:27 PM PDT 24 |
| Peak memory | 576068 kb |
| Host | smart-3c094939-ed2c-4a9e-9035-585631572aa9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240703601 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all _with_reset_error.1240703601 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_unmapped_addr.3998993487 |
| Short name | T1455 |
| Test name | |
| Test status | |
| Simulation time | 301598737 ps |
| CPU time | 14.96 seconds |
| Started | Jul 31 07:47:01 PM PDT 24 |
| Finished | Jul 31 07:47:16 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-7679ed5b-dae7-45a0-9746-7c34bb89c801 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998993487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.3998993487 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device.57046008 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 938146452 ps |
| CPU time | 67.98 seconds |
| Started | Jul 31 07:58:51 PM PDT 24 |
| Finished | Jul 31 07:59:59 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-cf41a013-52fd-49a0-9be6-e7ead26f0da1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57046008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device.57046008 |
| Directory | /workspace/60.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.2722216660 |
| Short name | T1847 |
| Test name | |
| Test status | |
| Simulation time | 81199164401 ps |
| CPU time | 1439.09 seconds |
| Started | Jul 31 07:58:49 PM PDT 24 |
| Finished | Jul 31 08:22:49 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-ec2755d1-2099-40d9-b184-dd10b28c99bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722216660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_ device_slow_rsp.2722216660 |
| Directory | /workspace/60.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.1430041011 |
| Short name | T2908 |
| Test name | |
| Test status | |
| Simulation time | 541373403 ps |
| CPU time | 23.57 seconds |
| Started | Jul 31 07:58:51 PM PDT 24 |
| Finished | Jul 31 07:59:15 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-0b7ed210-c28b-48af-9a9e-07ae878db35a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430041011 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_and_unmapped_add r.1430041011 |
| Directory | /workspace/60.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_random.4170342507 |
| Short name | T1426 |
| Test name | |
| Test status | |
| Simulation time | 34569203 ps |
| CPU time | 5.95 seconds |
| Started | Jul 31 07:58:49 PM PDT 24 |
| Finished | Jul 31 07:58:55 PM PDT 24 |
| Peak memory | 573824 kb |
| Host | smart-d5fa1e17-3820-42d9-a986-0f305cfd523e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170342507 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_random.4170342507 |
| Directory | /workspace/60.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random.693362367 |
| Short name | T1629 |
| Test name | |
| Test status | |
| Simulation time | 1976010122 ps |
| CPU time | 71.39 seconds |
| Started | Jul 31 07:58:42 PM PDT 24 |
| Finished | Jul 31 07:59:54 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-c78f761b-b39c-43bb-92eb-b189d3dc21aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693362367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random.693362367 |
| Directory | /workspace/60.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_large_delays.370255090 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 67018230114 ps |
| CPU time | 736.23 seconds |
| Started | Jul 31 07:58:42 PM PDT 24 |
| Finished | Jul 31 08:10:59 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-d0cfb4b5-6447-44aa-8772-a380e8da080c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370255090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_large_delays.370255090 |
| Directory | /workspace/60.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.1236824813 |
| Short name | T2814 |
| Test name | |
| Test status | |
| Simulation time | 28613357735 ps |
| CPU time | 477.63 seconds |
| Started | Jul 31 07:58:44 PM PDT 24 |
| Finished | Jul 31 08:06:42 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-3c0f7339-fa21-487f-8a95-2e66df8fa185 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236824813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_slow_rsp.1236824813 |
| Directory | /workspace/60.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_zero_delays.1024858600 |
| Short name | T2135 |
| Test name | |
| Test status | |
| Simulation time | 349649554 ps |
| CPU time | 35.04 seconds |
| Started | Jul 31 07:58:45 PM PDT 24 |
| Finished | Jul 31 07:59:20 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-cf2548d6-82ff-43c3-89bc-c03dc2a0ca66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024858600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_zero_del ays.1024858600 |
| Directory | /workspace/60.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_same_source.3953952475 |
| Short name | T2813 |
| Test name | |
| Test status | |
| Simulation time | 523139530 ps |
| CPU time | 18.24 seconds |
| Started | Jul 31 07:58:52 PM PDT 24 |
| Finished | Jul 31 07:59:10 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-4c85ea5c-4318-4901-a548-918a62a0bcab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953952475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_same_source.3953952475 |
| Directory | /workspace/60.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke.3526037542 |
| Short name | T2457 |
| Test name | |
| Test status | |
| Simulation time | 49483620 ps |
| CPU time | 6.71 seconds |
| Started | Jul 31 07:58:45 PM PDT 24 |
| Finished | Jul 31 07:58:52 PM PDT 24 |
| Peak memory | 573924 kb |
| Host | smart-13ee9a5c-fe48-4c22-8ba1-5d07efeac8e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526037542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke.3526037542 |
| Directory | /workspace/60.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.2854045086 |
| Short name | T2791 |
| Test name | |
| Test status | |
| Simulation time | 7929433458 ps |
| CPU time | 80.89 seconds |
| Started | Jul 31 07:58:44 PM PDT 24 |
| Finished | Jul 31 08:00:05 PM PDT 24 |
| Peak memory | 573872 kb |
| Host | smart-b20cfd58-eff0-4229-a54d-8bd402e18a23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854045086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_large_delays.2854045086 |
| Directory | /workspace/60.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.1933696055 |
| Short name | T2592 |
| Test name | |
| Test status | |
| Simulation time | 3909048250 ps |
| CPU time | 68.78 seconds |
| Started | Jul 31 07:58:43 PM PDT 24 |
| Finished | Jul 31 07:59:52 PM PDT 24 |
| Peak memory | 574572 kb |
| Host | smart-6432fb60-385a-4129-a910-ea30343143fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933696055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_slow_rsp.1933696055 |
| Directory | /workspace/60.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.2677760625 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 46923497 ps |
| CPU time | 6.46 seconds |
| Started | Jul 31 07:58:46 PM PDT 24 |
| Finished | Jul 31 07:58:52 PM PDT 24 |
| Peak memory | 573800 kb |
| Host | smart-eac039f5-51ca-4e7f-8630-dcf86499e334 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677760625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_zero_delay s.2677760625 |
| Directory | /workspace/60.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all.4194404320 |
| Short name | T2444 |
| Test name | |
| Test status | |
| Simulation time | 2780737915 ps |
| CPU time | 230.86 seconds |
| Started | Jul 31 07:58:51 PM PDT 24 |
| Finished | Jul 31 08:02:42 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-aba486aa-e375-4ced-93f6-4bcda29e88e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194404320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all.4194404320 |
| Directory | /workspace/60.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.852336717 |
| Short name | T2017 |
| Test name | |
| Test status | |
| Simulation time | 3104388185 ps |
| CPU time | 227.77 seconds |
| Started | Jul 31 07:58:50 PM PDT 24 |
| Finished | Jul 31 08:02:38 PM PDT 24 |
| Peak memory | 576856 kb |
| Host | smart-c26f021e-0157-4f28-858d-ab49a72619db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852336717 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_error.852336717 |
| Directory | /workspace/60.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.1170623292 |
| Short name | T2797 |
| Test name | |
| Test status | |
| Simulation time | 136107167 ps |
| CPU time | 77.18 seconds |
| Started | Jul 31 07:58:52 PM PDT 24 |
| Finished | Jul 31 08:00:09 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-5ad51e8b-f1e2-4f5a-b365-b9b585e14520 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170623292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all _with_rand_reset.1170623292 |
| Directory | /workspace/60.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.3226585089 |
| Short name | T2569 |
| Test name | |
| Test status | |
| Simulation time | 579423610 ps |
| CPU time | 177 seconds |
| Started | Jul 31 07:58:49 PM PDT 24 |
| Finished | Jul 31 08:01:46 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-f12b82b1-57cd-4372-ac12-1ad699ee1180 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226585089 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_al l_with_reset_error.3226585089 |
| Directory | /workspace/60.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_unmapped_addr.992708506 |
| Short name | T2388 |
| Test name | |
| Test status | |
| Simulation time | 184131597 ps |
| CPU time | 11.4 seconds |
| Started | Jul 31 07:58:52 PM PDT 24 |
| Finished | Jul 31 07:59:04 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-32d3103f-e673-44a0-ad50-6366af4406dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992708506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_unmapped_addr.992708506 |
| Directory | /workspace/60.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device.593389367 |
| Short name | T2044 |
| Test name | |
| Test status | |
| Simulation time | 301259560 ps |
| CPU time | 25.86 seconds |
| Started | Jul 31 07:59:02 PM PDT 24 |
| Finished | Jul 31 07:59:28 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-83c62c2e-bacf-4801-aa52-a8a717ac14d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593389367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device. 593389367 |
| Directory | /workspace/61.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.270789988 |
| Short name | T1678 |
| Test name | |
| Test status | |
| Simulation time | 4106093715 ps |
| CPU time | 69.5 seconds |
| Started | Jul 31 07:59:05 PM PDT 24 |
| Finished | Jul 31 08:00:14 PM PDT 24 |
| Peak memory | 573808 kb |
| Host | smart-e6f37402-1a4c-4c88-93a0-a2ac2e4e67d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270789988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_d evice_slow_rsp.270789988 |
| Directory | /workspace/61.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.3137317616 |
| Short name | T2886 |
| Test name | |
| Test status | |
| Simulation time | 1081866508 ps |
| CPU time | 35.03 seconds |
| Started | Jul 31 07:59:02 PM PDT 24 |
| Finished | Jul 31 07:59:37 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-afd5fe2d-09d8-4257-ae04-76e103bec888 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137317616 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_and_unmapped_add r.3137317616 |
| Directory | /workspace/61.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_random.151736050 |
| Short name | T2688 |
| Test name | |
| Test status | |
| Simulation time | 2091005604 ps |
| CPU time | 66.47 seconds |
| Started | Jul 31 07:59:01 PM PDT 24 |
| Finished | Jul 31 08:00:08 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-77981382-bcea-45c2-90a8-a76ec1a2b9f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151736050 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_random.151736050 |
| Directory | /workspace/61.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random.2165660753 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 530631139 ps |
| CPU time | 46.79 seconds |
| Started | Jul 31 07:58:57 PM PDT 24 |
| Finished | Jul 31 07:59:44 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-ad8b71de-7071-4f7b-84be-0867f65fbd91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165660753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random.2165660753 |
| Directory | /workspace/61.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_large_delays.1374827274 |
| Short name | T1967 |
| Test name | |
| Test status | |
| Simulation time | 52549680456 ps |
| CPU time | 572.15 seconds |
| Started | Jul 31 07:58:58 PM PDT 24 |
| Finished | Jul 31 08:08:30 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-fccf478f-a30e-4a57-a4f8-3d1dd9cae968 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374827274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_large_delays.1374827274 |
| Directory | /workspace/61.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_slow_rsp.2692284509 |
| Short name | T1827 |
| Test name | |
| Test status | |
| Simulation time | 8984775624 ps |
| CPU time | 143.59 seconds |
| Started | Jul 31 07:59:02 PM PDT 24 |
| Finished | Jul 31 08:01:25 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-ada132e0-8588-4df4-bca7-1880526de532 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692284509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_slow_rsp.2692284509 |
| Directory | /workspace/61.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_zero_delays.872512347 |
| Short name | T2066 |
| Test name | |
| Test status | |
| Simulation time | 351367911 ps |
| CPU time | 34.8 seconds |
| Started | Jul 31 07:58:57 PM PDT 24 |
| Finished | Jul 31 07:59:32 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-57dc45ce-a3f3-4e51-b5ad-0055661a43ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872512347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_zero_dela ys.872512347 |
| Directory | /workspace/61.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_same_source.1411554865 |
| Short name | T2128 |
| Test name | |
| Test status | |
| Simulation time | 105831012 ps |
| CPU time | 10.24 seconds |
| Started | Jul 31 07:59:04 PM PDT 24 |
| Finished | Jul 31 07:59:14 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-9b25388b-0eb6-466d-9350-f38252fc9f82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411554865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_same_source.1411554865 |
| Directory | /workspace/61.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke.850222238 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 233917496 ps |
| CPU time | 9.3 seconds |
| Started | Jul 31 07:58:50 PM PDT 24 |
| Finished | Jul 31 07:59:00 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-ac1a6c69-cc5e-452b-9ab0-a48f391f8262 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850222238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke.850222238 |
| Directory | /workspace/61.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_large_delays.2380696230 |
| Short name | T1435 |
| Test name | |
| Test status | |
| Simulation time | 7172126308 ps |
| CPU time | 72.8 seconds |
| Started | Jul 31 07:58:57 PM PDT 24 |
| Finished | Jul 31 08:00:10 PM PDT 24 |
| Peak memory | 574672 kb |
| Host | smart-330b91ab-b2f1-4085-9340-818cc707ec0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380696230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_large_delays.2380696230 |
| Directory | /workspace/61.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.1745073955 |
| Short name | T1516 |
| Test name | |
| Test status | |
| Simulation time | 5002495400 ps |
| CPU time | 83.52 seconds |
| Started | Jul 31 07:58:55 PM PDT 24 |
| Finished | Jul 31 08:00:18 PM PDT 24 |
| Peak memory | 573864 kb |
| Host | smart-48a7a474-6dd9-44b7-a0fa-45e58bdde341 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745073955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_slow_rsp.1745073955 |
| Directory | /workspace/61.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_zero_delays.2926754856 |
| Short name | T2663 |
| Test name | |
| Test status | |
| Simulation time | 42311463 ps |
| CPU time | 6.06 seconds |
| Started | Jul 31 07:58:59 PM PDT 24 |
| Finished | Jul 31 07:59:06 PM PDT 24 |
| Peak memory | 573584 kb |
| Host | smart-ece29bda-0454-41cc-adf2-481e5e79a09b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926754856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_zero_delay s.2926754856 |
| Directory | /workspace/61.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all.837934903 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 3700942734 ps |
| CPU time | 142.19 seconds |
| Started | Jul 31 07:59:01 PM PDT 24 |
| Finished | Jul 31 08:01:23 PM PDT 24 |
| Peak memory | 576048 kb |
| Host | smart-6342eee8-0f15-4b29-a616-3e8974f338c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837934903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all.837934903 |
| Directory | /workspace/61.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.2153675740 |
| Short name | T1618 |
| Test name | |
| Test status | |
| Simulation time | 15998300237 ps |
| CPU time | 624.29 seconds |
| Started | Jul 31 07:59:01 PM PDT 24 |
| Finished | Jul 31 08:09:25 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-b31a7165-96da-4612-a93a-4967be958119 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153675740 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_error.2153675740 |
| Directory | /workspace/61.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.3171087992 |
| Short name | T2171 |
| Test name | |
| Test status | |
| Simulation time | 245511925 ps |
| CPU time | 48.85 seconds |
| Started | Jul 31 07:59:03 PM PDT 24 |
| Finished | Jul 31 07:59:52 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-6b40cf18-49c6-42e2-8eac-20488c38c05e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171087992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all _with_rand_reset.3171087992 |
| Directory | /workspace/61.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.4243320079 |
| Short name | T1759 |
| Test name | |
| Test status | |
| Simulation time | 602027174 ps |
| CPU time | 232.07 seconds |
| Started | Jul 31 07:59:03 PM PDT 24 |
| Finished | Jul 31 08:02:55 PM PDT 24 |
| Peak memory | 576736 kb |
| Host | smart-b7b2c621-f6f1-432c-958d-cdd3c135dd54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243320079 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_al l_with_reset_error.4243320079 |
| Directory | /workspace/61.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_unmapped_addr.1739346473 |
| Short name | T1805 |
| Test name | |
| Test status | |
| Simulation time | 1443111227 ps |
| CPU time | 59.62 seconds |
| Started | Jul 31 07:59:04 PM PDT 24 |
| Finished | Jul 31 08:00:03 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-b0279306-c6f2-4055-a9d8-c7b36f7dcdb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739346473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_unmapped_addr.1739346473 |
| Directory | /workspace/61.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device.1053299790 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 3333170120 ps |
| CPU time | 135.86 seconds |
| Started | Jul 31 07:59:08 PM PDT 24 |
| Finished | Jul 31 08:01:24 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-6a137daa-0446-49e7-8604-74efaa860678 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053299790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device .1053299790 |
| Directory | /workspace/62.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.3058060364 |
| Short name | T2846 |
| Test name | |
| Test status | |
| Simulation time | 138681036860 ps |
| CPU time | 2553.19 seconds |
| Started | Jul 31 07:59:07 PM PDT 24 |
| Finished | Jul 31 08:41:41 PM PDT 24 |
| Peak memory | 576068 kb |
| Host | smart-cb73deb3-e489-4957-a839-9890daaa3262 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058060364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_ device_slow_rsp.3058060364 |
| Directory | /workspace/62.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.1522764155 |
| Short name | T2869 |
| Test name | |
| Test status | |
| Simulation time | 761470281 ps |
| CPU time | 31.83 seconds |
| Started | Jul 31 07:59:07 PM PDT 24 |
| Finished | Jul 31 07:59:39 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-b8cb196f-d640-4a34-a724-f9ae1b52a6d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522764155 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_and_unmapped_add r.1522764155 |
| Directory | /workspace/62.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_random.4123074165 |
| Short name | T1502 |
| Test name | |
| Test status | |
| Simulation time | 393454686 ps |
| CPU time | 16.42 seconds |
| Started | Jul 31 07:59:08 PM PDT 24 |
| Finished | Jul 31 07:59:25 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-d34eb298-ab41-4bdf-a61c-cb30df73a71d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123074165 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_random.4123074165 |
| Directory | /workspace/62.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random.457992039 |
| Short name | T1861 |
| Test name | |
| Test status | |
| Simulation time | 298124630 ps |
| CPU time | 30.34 seconds |
| Started | Jul 31 07:59:07 PM PDT 24 |
| Finished | Jul 31 07:59:38 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-fdc82630-4175-46eb-9929-f56989988100 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457992039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random.457992039 |
| Directory | /workspace/62.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_large_delays.2863648721 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 122715379816 ps |
| CPU time | 1245.35 seconds |
| Started | Jul 31 07:59:08 PM PDT 24 |
| Finished | Jul 31 08:19:54 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-b0416607-9178-4e9f-9163-0efa5539b591 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863648721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_large_delays.2863648721 |
| Directory | /workspace/62.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_slow_rsp.3369985326 |
| Short name | T2304 |
| Test name | |
| Test status | |
| Simulation time | 22252620255 ps |
| CPU time | 332.94 seconds |
| Started | Jul 31 07:59:06 PM PDT 24 |
| Finished | Jul 31 08:04:39 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-2d72224e-2a3c-4720-98d9-cb88e5ce5110 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369985326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_slow_rsp.3369985326 |
| Directory | /workspace/62.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_zero_delays.2166609811 |
| Short name | T2366 |
| Test name | |
| Test status | |
| Simulation time | 359661220 ps |
| CPU time | 30.22 seconds |
| Started | Jul 31 07:59:13 PM PDT 24 |
| Finished | Jul 31 07:59:43 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-7b132a26-14ca-4f3b-8650-35791b29e9a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166609811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_zero_del ays.2166609811 |
| Directory | /workspace/62.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_same_source.1622992566 |
| Short name | T1859 |
| Test name | |
| Test status | |
| Simulation time | 1553646894 ps |
| CPU time | 45.65 seconds |
| Started | Jul 31 07:59:13 PM PDT 24 |
| Finished | Jul 31 07:59:59 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-28a9eba8-2f0a-42d0-bc11-fee725571e6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622992566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_same_source.1622992566 |
| Directory | /workspace/62.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke.2164622057 |
| Short name | T1762 |
| Test name | |
| Test status | |
| Simulation time | 180684775 ps |
| CPU time | 9.18 seconds |
| Started | Jul 31 07:59:02 PM PDT 24 |
| Finished | Jul 31 07:59:11 PM PDT 24 |
| Peak memory | 573800 kb |
| Host | smart-0b081128-cd10-42c8-9761-a1425d800337 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164622057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke.2164622057 |
| Directory | /workspace/62.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_large_delays.1817926575 |
| Short name | T1515 |
| Test name | |
| Test status | |
| Simulation time | 9086158761 ps |
| CPU time | 90.27 seconds |
| Started | Jul 31 07:59:08 PM PDT 24 |
| Finished | Jul 31 08:00:38 PM PDT 24 |
| Peak memory | 573948 kb |
| Host | smart-294df8e3-121f-4cf9-8c64-556dbf69b9fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817926575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_large_delays.1817926575 |
| Directory | /workspace/62.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.3668326646 |
| Short name | T1849 |
| Test name | |
| Test status | |
| Simulation time | 4333790820 ps |
| CPU time | 73.63 seconds |
| Started | Jul 31 07:59:09 PM PDT 24 |
| Finished | Jul 31 08:00:22 PM PDT 24 |
| Peak memory | 573848 kb |
| Host | smart-16a589b8-5297-40ac-88c8-c8376d84b833 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668326646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_slow_rsp.3668326646 |
| Directory | /workspace/62.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_zero_delays.4132660848 |
| Short name | T2256 |
| Test name | |
| Test status | |
| Simulation time | 41014923 ps |
| CPU time | 6.13 seconds |
| Started | Jul 31 07:59:03 PM PDT 24 |
| Finished | Jul 31 07:59:09 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-f0a4f25b-4234-442f-ad62-a998b476e486 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132660848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_zero_delay s.4132660848 |
| Directory | /workspace/62.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all.4280967053 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 12252386844 ps |
| CPU time | 473.42 seconds |
| Started | Jul 31 07:59:06 PM PDT 24 |
| Finished | Jul 31 08:07:00 PM PDT 24 |
| Peak memory | 576800 kb |
| Host | smart-f3296042-c51f-423e-9e09-34ccfd8ecccf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280967053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all.4280967053 |
| Directory | /workspace/62.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.3366351576 |
| Short name | T2900 |
| Test name | |
| Test status | |
| Simulation time | 6285667819 ps |
| CPU time | 203.43 seconds |
| Started | Jul 31 07:59:20 PM PDT 24 |
| Finished | Jul 31 08:02:44 PM PDT 24 |
| Peak memory | 576140 kb |
| Host | smart-60a9cf38-ae62-4469-a8ff-aaa269f7362d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366351576 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_error.3366351576 |
| Directory | /workspace/62.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.1519841746 |
| Short name | T2758 |
| Test name | |
| Test status | |
| Simulation time | 391527851 ps |
| CPU time | 103.73 seconds |
| Started | Jul 31 07:59:13 PM PDT 24 |
| Finished | Jul 31 08:00:56 PM PDT 24 |
| Peak memory | 576736 kb |
| Host | smart-75193bef-4e17-48ce-bd70-6d71c39e54b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519841746 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_al l_with_reset_error.1519841746 |
| Directory | /workspace/62.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.990888226 |
| Short name | T1674 |
| Test name | |
| Test status | |
| Simulation time | 258530125 ps |
| CPU time | 26.72 seconds |
| Started | Jul 31 07:59:08 PM PDT 24 |
| Finished | Jul 31 07:59:35 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-402d0649-a740-492b-85a1-4f7808696fc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990888226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_unmapped_addr.990888226 |
| Directory | /workspace/62.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device.677676399 |
| Short name | T1912 |
| Test name | |
| Test status | |
| Simulation time | 1043661282 ps |
| CPU time | 71.98 seconds |
| Started | Jul 31 07:59:12 PM PDT 24 |
| Finished | Jul 31 08:00:24 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-39215f72-6ffe-4676-8249-11d503ec0a77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677676399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device. 677676399 |
| Directory | /workspace/63.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.3400678534 |
| Short name | T2031 |
| Test name | |
| Test status | |
| Simulation time | 152558404638 ps |
| CPU time | 2745.19 seconds |
| Started | Jul 31 07:59:13 PM PDT 24 |
| Finished | Jul 31 08:44:59 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-20372e6f-e6d0-4400-a2a4-f97e2b7a8888 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400678534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_ device_slow_rsp.3400678534 |
| Directory | /workspace/63.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.2354719232 |
| Short name | T1609 |
| Test name | |
| Test status | |
| Simulation time | 1088181408 ps |
| CPU time | 37.91 seconds |
| Started | Jul 31 07:59:20 PM PDT 24 |
| Finished | Jul 31 07:59:58 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-f130dc5d-d936-4692-b91a-a05f11b868b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354719232 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_and_unmapped_add r.2354719232 |
| Directory | /workspace/63.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_random.1354275713 |
| Short name | T1894 |
| Test name | |
| Test status | |
| Simulation time | 993836404 ps |
| CPU time | 35.08 seconds |
| Started | Jul 31 07:59:11 PM PDT 24 |
| Finished | Jul 31 07:59:46 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-27a6fa42-6efe-4afe-a789-564b1e5c018c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354275713 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_random.1354275713 |
| Directory | /workspace/63.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random.503175896 |
| Short name | T2054 |
| Test name | |
| Test status | |
| Simulation time | 162238405 ps |
| CPU time | 15.75 seconds |
| Started | Jul 31 07:59:16 PM PDT 24 |
| Finished | Jul 31 07:59:31 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-b49480b0-c1b4-42b7-9116-c7b299b0655c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503175896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random.503175896 |
| Directory | /workspace/63.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_large_delays.3494904489 |
| Short name | T1933 |
| Test name | |
| Test status | |
| Simulation time | 2969569539 ps |
| CPU time | 30.66 seconds |
| Started | Jul 31 07:59:12 PM PDT 24 |
| Finished | Jul 31 07:59:42 PM PDT 24 |
| Peak memory | 573864 kb |
| Host | smart-b7b61b71-17b9-4048-ad27-306944e10383 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494904489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_large_delays.3494904489 |
| Directory | /workspace/63.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_slow_rsp.338095264 |
| Short name | T2406 |
| Test name | |
| Test status | |
| Simulation time | 1946547290 ps |
| CPU time | 32.9 seconds |
| Started | Jul 31 07:59:16 PM PDT 24 |
| Finished | Jul 31 07:59:49 PM PDT 24 |
| Peak memory | 573840 kb |
| Host | smart-42b04c68-1310-4d84-8516-0d492a7e7dff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338095264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_slow_rsp.338095264 |
| Directory | /workspace/63.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_zero_delays.3393139169 |
| Short name | T2257 |
| Test name | |
| Test status | |
| Simulation time | 110708401 ps |
| CPU time | 11.87 seconds |
| Started | Jul 31 07:59:14 PM PDT 24 |
| Finished | Jul 31 07:59:26 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-d87c2c0d-6478-4fc7-adb7-c6d564eb2767 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393139169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_zero_del ays.3393139169 |
| Directory | /workspace/63.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_same_source.2632757528 |
| Short name | T2053 |
| Test name | |
| Test status | |
| Simulation time | 2032624188 ps |
| CPU time | 60.75 seconds |
| Started | Jul 31 07:59:13 PM PDT 24 |
| Finished | Jul 31 08:00:14 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-3cf5a769-d225-4cc1-b0d4-2cbd1f4e6289 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632757528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_same_source.2632757528 |
| Directory | /workspace/63.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke.569964501 |
| Short name | T1892 |
| Test name | |
| Test status | |
| Simulation time | 182237162 ps |
| CPU time | 7.82 seconds |
| Started | Jul 31 07:59:14 PM PDT 24 |
| Finished | Jul 31 07:59:22 PM PDT 24 |
| Peak memory | 573840 kb |
| Host | smart-14f85440-5879-410b-b179-3f63615486ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569964501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke.569964501 |
| Directory | /workspace/63.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_large_delays.1136902923 |
| Short name | T2371 |
| Test name | |
| Test status | |
| Simulation time | 7487373479 ps |
| CPU time | 85.97 seconds |
| Started | Jul 31 07:59:16 PM PDT 24 |
| Finished | Jul 31 08:00:42 PM PDT 24 |
| Peak memory | 574580 kb |
| Host | smart-b415685e-648d-419e-a2ef-8607e7fbd27d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136902923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_large_delays.1136902923 |
| Directory | /workspace/63.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.2951090909 |
| Short name | T2561 |
| Test name | |
| Test status | |
| Simulation time | 5354982959 ps |
| CPU time | 92.29 seconds |
| Started | Jul 31 07:59:22 PM PDT 24 |
| Finished | Jul 31 08:00:54 PM PDT 24 |
| Peak memory | 573888 kb |
| Host | smart-75389625-d6c6-4ab8-833d-60a7b4063a0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951090909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_slow_rsp.2951090909 |
| Directory | /workspace/63.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_zero_delays.3470640621 |
| Short name | T2877 |
| Test name | |
| Test status | |
| Simulation time | 51167198 ps |
| CPU time | 6.62 seconds |
| Started | Jul 31 07:59:15 PM PDT 24 |
| Finished | Jul 31 07:59:22 PM PDT 24 |
| Peak memory | 573792 kb |
| Host | smart-d5399a02-82e2-46e5-94c7-413c47c4e81b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470640621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_zero_delay s.3470640621 |
| Directory | /workspace/63.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all.2435585592 |
| Short name | T1979 |
| Test name | |
| Test status | |
| Simulation time | 337352898 ps |
| CPU time | 31.22 seconds |
| Started | Jul 31 07:59:28 PM PDT 24 |
| Finished | Jul 31 08:00:00 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-b9d6c849-9842-44ab-bc69-fd5a93792806 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435585592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all.2435585592 |
| Directory | /workspace/63.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.1602002459 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 6752178352 ps |
| CPU time | 257.41 seconds |
| Started | Jul 31 07:59:20 PM PDT 24 |
| Finished | Jul 31 08:03:37 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-fa4d0046-b8b5-4da9-92f2-3dd676d94c35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602002459 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_error.1602002459 |
| Directory | /workspace/63.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.3724780066 |
| Short name | T2821 |
| Test name | |
| Test status | |
| Simulation time | 150586192 ps |
| CPU time | 75.19 seconds |
| Started | Jul 31 07:59:26 PM PDT 24 |
| Finished | Jul 31 08:00:41 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-d3c25619-cf9d-457b-93e3-35c7035ad76a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724780066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all _with_rand_reset.3724780066 |
| Directory | /workspace/63.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.2683992773 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 383060743 ps |
| CPU time | 120.56 seconds |
| Started | Jul 31 07:59:27 PM PDT 24 |
| Finished | Jul 31 08:01:28 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-a19f062f-3c79-433d-afb9-6c3071eb3195 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683992773 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_al l_with_reset_error.2683992773 |
| Directory | /workspace/63.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_unmapped_addr.1885852358 |
| Short name | T2427 |
| Test name | |
| Test status | |
| Simulation time | 1112327514 ps |
| CPU time | 47.34 seconds |
| Started | Jul 31 07:59:18 PM PDT 24 |
| Finished | Jul 31 08:00:06 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-cb24ef6e-804c-4398-8747-c8804f568353 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885852358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_unmapped_addr.1885852358 |
| Directory | /workspace/63.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device.1469540247 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 354822874 ps |
| CPU time | 33.89 seconds |
| Started | Jul 31 07:59:28 PM PDT 24 |
| Finished | Jul 31 08:00:02 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-d5d97a11-103e-420f-8a66-8167849a6936 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469540247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device .1469540247 |
| Directory | /workspace/64.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.1178090599 |
| Short name | T2655 |
| Test name | |
| Test status | |
| Simulation time | 64769497890 ps |
| CPU time | 1201.81 seconds |
| Started | Jul 31 07:59:25 PM PDT 24 |
| Finished | Jul 31 08:19:27 PM PDT 24 |
| Peak memory | 576152 kb |
| Host | smart-e0bb184c-b5f5-426c-aef3-a5d9c3efadd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178090599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_ device_slow_rsp.1178090599 |
| Directory | /workspace/64.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.3060247993 |
| Short name | T2815 |
| Test name | |
| Test status | |
| Simulation time | 44010467 ps |
| CPU time | 5.72 seconds |
| Started | Jul 31 07:59:29 PM PDT 24 |
| Finished | Jul 31 07:59:34 PM PDT 24 |
| Peak memory | 573856 kb |
| Host | smart-d5ea6eef-a7c0-46a0-b01f-61976ecd07fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060247993 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_and_unmapped_add r.3060247993 |
| Directory | /workspace/64.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_random.4103594350 |
| Short name | T1653 |
| Test name | |
| Test status | |
| Simulation time | 303031858 ps |
| CPU time | 23.97 seconds |
| Started | Jul 31 07:59:28 PM PDT 24 |
| Finished | Jul 31 07:59:52 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-545a0910-e725-40fa-a026-b25a88d4846f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103594350 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_random.4103594350 |
| Directory | /workspace/64.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random.1646694356 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 2477752555 ps |
| CPU time | 90.97 seconds |
| Started | Jul 31 07:59:21 PM PDT 24 |
| Finished | Jul 31 08:00:52 PM PDT 24 |
| Peak memory | 576052 kb |
| Host | smart-4b252867-968e-4a15-aa4b-5d9b89b9776f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646694356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random.1646694356 |
| Directory | /workspace/64.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_large_delays.406630303 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 54012445922 ps |
| CPU time | 535.5 seconds |
| Started | Jul 31 07:59:29 PM PDT 24 |
| Finished | Jul 31 08:08:25 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-13d445cd-8419-4227-99ce-e0f222b412cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406630303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_large_delays.406630303 |
| Directory | /workspace/64.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.2521635723 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 60963568469 ps |
| CPU time | 1052.77 seconds |
| Started | Jul 31 07:59:26 PM PDT 24 |
| Finished | Jul 31 08:16:59 PM PDT 24 |
| Peak memory | 576084 kb |
| Host | smart-c886032a-7975-41b1-a7ac-1c076674d937 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521635723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_slow_rsp.2521635723 |
| Directory | /workspace/64.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_zero_delays.2417231462 |
| Short name | T1969 |
| Test name | |
| Test status | |
| Simulation time | 293725036 ps |
| CPU time | 27.51 seconds |
| Started | Jul 31 07:59:25 PM PDT 24 |
| Finished | Jul 31 07:59:53 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-38e14d0d-3abd-4dc9-b961-ef1a8dbba390 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417231462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_zero_del ays.2417231462 |
| Directory | /workspace/64.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_same_source.847573243 |
| Short name | T2540 |
| Test name | |
| Test status | |
| Simulation time | 205496826 ps |
| CPU time | 16.5 seconds |
| Started | Jul 31 07:59:27 PM PDT 24 |
| Finished | Jul 31 07:59:44 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-cde368da-cc99-4633-b5df-d3a6f7e482b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847573243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_same_source.847573243 |
| Directory | /workspace/64.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke.3457801202 |
| Short name | T2628 |
| Test name | |
| Test status | |
| Simulation time | 48148167 ps |
| CPU time | 6.41 seconds |
| Started | Jul 31 07:59:21 PM PDT 24 |
| Finished | Jul 31 07:59:27 PM PDT 24 |
| Peak memory | 573720 kb |
| Host | smart-61ceb53d-f885-4f33-8512-1d6fde601fb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457801202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke.3457801202 |
| Directory | /workspace/64.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_large_delays.664822780 |
| Short name | T1961 |
| Test name | |
| Test status | |
| Simulation time | 7360025162 ps |
| CPU time | 72.85 seconds |
| Started | Jul 31 07:59:27 PM PDT 24 |
| Finished | Jul 31 08:00:40 PM PDT 24 |
| Peak memory | 573880 kb |
| Host | smart-5bbb653e-5979-4dde-85e1-6fdc32d3968e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664822780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_large_delays.664822780 |
| Directory | /workspace/64.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.3234438715 |
| Short name | T1544 |
| Test name | |
| Test status | |
| Simulation time | 3940910327 ps |
| CPU time | 64 seconds |
| Started | Jul 31 07:59:19 PM PDT 24 |
| Finished | Jul 31 08:00:23 PM PDT 24 |
| Peak memory | 574560 kb |
| Host | smart-4e3171e1-ff7a-4cd2-bee8-ebfcd2e3452d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234438715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_slow_rsp.3234438715 |
| Directory | /workspace/64.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.787763711 |
| Short name | T1807 |
| Test name | |
| Test status | |
| Simulation time | 39773122 ps |
| CPU time | 5.92 seconds |
| Started | Jul 31 07:59:22 PM PDT 24 |
| Finished | Jul 31 07:59:28 PM PDT 24 |
| Peak memory | 573812 kb |
| Host | smart-15afcad4-12f2-4438-acb8-543d8ff60348 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787763711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_zero_delays .787763711 |
| Directory | /workspace/64.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all.700200933 |
| Short name | T2702 |
| Test name | |
| Test status | |
| Simulation time | 2135414135 ps |
| CPU time | 179.29 seconds |
| Started | Jul 31 07:59:25 PM PDT 24 |
| Finished | Jul 31 08:02:24 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-cbe642c8-93da-4fe5-a326-cd85a124dc79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700200933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all.700200933 |
| Directory | /workspace/64.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_error.2071521738 |
| Short name | T2202 |
| Test name | |
| Test status | |
| Simulation time | 2857472315 ps |
| CPU time | 238.78 seconds |
| Started | Jul 31 07:59:26 PM PDT 24 |
| Finished | Jul 31 08:03:25 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-541c4445-cb9e-40ac-a100-1a11f3c931b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071521738 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_error.2071521738 |
| Directory | /workspace/64.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.1546995289 |
| Short name | T1834 |
| Test name | |
| Test status | |
| Simulation time | 389612628 ps |
| CPU time | 95.39 seconds |
| Started | Jul 31 07:59:32 PM PDT 24 |
| Finished | Jul 31 08:01:07 PM PDT 24 |
| Peak memory | 576700 kb |
| Host | smart-5646b370-d6cb-41f4-8083-65b54c187ccb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546995289 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_al l_with_reset_error.1546995289 |
| Directory | /workspace/64.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.2201338336 |
| Short name | T2825 |
| Test name | |
| Test status | |
| Simulation time | 1011522823 ps |
| CPU time | 36.48 seconds |
| Started | Jul 31 07:59:24 PM PDT 24 |
| Finished | Jul 31 08:00:01 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-57fc8338-73fa-4fb8-ba52-08bef4ad4f6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201338336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_unmapped_addr.2201338336 |
| Directory | /workspace/64.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device.3636437145 |
| Short name | T2302 |
| Test name | |
| Test status | |
| Simulation time | 3349003912 ps |
| CPU time | 132.46 seconds |
| Started | Jul 31 07:59:39 PM PDT 24 |
| Finished | Jul 31 08:01:51 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-5fda8311-9bcb-4738-a123-db43bf31dc1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636437145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device .3636437145 |
| Directory | /workspace/65.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.3710015883 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 45335766506 ps |
| CPU time | 808.47 seconds |
| Started | Jul 31 07:59:38 PM PDT 24 |
| Finished | Jul 31 08:13:07 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-d7cc75fc-f6f3-4ecd-8c99-da67edbd06ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710015883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_ device_slow_rsp.3710015883 |
| Directory | /workspace/65.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.3267574015 |
| Short name | T2490 |
| Test name | |
| Test status | |
| Simulation time | 95864105 ps |
| CPU time | 12.7 seconds |
| Started | Jul 31 07:59:39 PM PDT 24 |
| Finished | Jul 31 07:59:52 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-31d162ff-24af-490d-9dcc-69cfac421ac9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267574015 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_and_unmapped_add r.3267574015 |
| Directory | /workspace/65.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_random.541996521 |
| Short name | T2456 |
| Test name | |
| Test status | |
| Simulation time | 362949208 ps |
| CPU time | 30.68 seconds |
| Started | Jul 31 07:59:39 PM PDT 24 |
| Finished | Jul 31 08:00:10 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-45587a13-ccba-47ca-90e4-9cef7550562f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541996521 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_random.541996521 |
| Directory | /workspace/65.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random.3114129167 |
| Short name | T2930 |
| Test name | |
| Test status | |
| Simulation time | 1894949264 ps |
| CPU time | 66.04 seconds |
| Started | Jul 31 07:59:39 PM PDT 24 |
| Finished | Jul 31 08:00:45 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-32fbb5ae-0ee3-4c66-b98c-c09c777bd2f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114129167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random.3114129167 |
| Directory | /workspace/65.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_large_delays.1891106529 |
| Short name | T2691 |
| Test name | |
| Test status | |
| Simulation time | 5696880718 ps |
| CPU time | 61.75 seconds |
| Started | Jul 31 07:59:40 PM PDT 24 |
| Finished | Jul 31 08:00:42 PM PDT 24 |
| Peak memory | 574664 kb |
| Host | smart-8a14e57c-9a3f-4be5-b5cb-92ddba1b01ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891106529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_large_delays.1891106529 |
| Directory | /workspace/65.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.3991130819 |
| Short name | T2794 |
| Test name | |
| Test status | |
| Simulation time | 48529121840 ps |
| CPU time | 874.92 seconds |
| Started | Jul 31 07:59:38 PM PDT 24 |
| Finished | Jul 31 08:14:13 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-3960224b-a468-48a8-b59b-4c4a92c03cba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991130819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_slow_rsp.3991130819 |
| Directory | /workspace/65.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.618817626 |
| Short name | T1792 |
| Test name | |
| Test status | |
| Simulation time | 283358172 ps |
| CPU time | 26.43 seconds |
| Started | Jul 31 07:59:41 PM PDT 24 |
| Finished | Jul 31 08:00:07 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-fea95393-3d73-4297-a809-7d5fec294001 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618817626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_zero_dela ys.618817626 |
| Directory | /workspace/65.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_same_source.826662673 |
| Short name | T1532 |
| Test name | |
| Test status | |
| Simulation time | 146076078 ps |
| CPU time | 13.39 seconds |
| Started | Jul 31 07:59:41 PM PDT 24 |
| Finished | Jul 31 07:59:54 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-b90cfaca-563e-4533-aa9f-e3544bc5ec7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826662673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_same_source.826662673 |
| Directory | /workspace/65.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke.3554768495 |
| Short name | T1741 |
| Test name | |
| Test status | |
| Simulation time | 245450073 ps |
| CPU time | 10.38 seconds |
| Started | Jul 31 07:59:33 PM PDT 24 |
| Finished | Jul 31 07:59:43 PM PDT 24 |
| Peak memory | 574512 kb |
| Host | smart-94425650-44cf-4e91-8722-e41193f618c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554768495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke.3554768495 |
| Directory | /workspace/65.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_large_delays.178456559 |
| Short name | T2258 |
| Test name | |
| Test status | |
| Simulation time | 6280087869 ps |
| CPU time | 69.12 seconds |
| Started | Jul 31 07:59:38 PM PDT 24 |
| Finished | Jul 31 08:00:48 PM PDT 24 |
| Peak memory | 573832 kb |
| Host | smart-f792b300-e838-44bf-902a-d81d783e00a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178456559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_large_delays.178456559 |
| Directory | /workspace/65.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.2919237591 |
| Short name | T1480 |
| Test name | |
| Test status | |
| Simulation time | 6221099017 ps |
| CPU time | 94.87 seconds |
| Started | Jul 31 07:59:38 PM PDT 24 |
| Finished | Jul 31 08:01:13 PM PDT 24 |
| Peak memory | 574580 kb |
| Host | smart-9ca0c96e-4780-4457-930f-defe8247cbad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919237591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_slow_rsp.2919237591 |
| Directory | /workspace/65.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.3242425362 |
| Short name | T2910 |
| Test name | |
| Test status | |
| Simulation time | 48714639 ps |
| CPU time | 6.76 seconds |
| Started | Jul 31 07:59:31 PM PDT 24 |
| Finished | Jul 31 07:59:38 PM PDT 24 |
| Peak memory | 574496 kb |
| Host | smart-83b78aa2-e020-44a9-8bc0-3419e16e812f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242425362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_zero_delay s.3242425362 |
| Directory | /workspace/65.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all.3731245107 |
| Short name | T2772 |
| Test name | |
| Test status | |
| Simulation time | 704015887 ps |
| CPU time | 28.03 seconds |
| Started | Jul 31 07:59:40 PM PDT 24 |
| Finished | Jul 31 08:00:08 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-ab4ee340-3ff7-4763-97c9-4d5f6b6ac705 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731245107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all.3731245107 |
| Directory | /workspace/65.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_error.3427512641 |
| Short name | T1940 |
| Test name | |
| Test status | |
| Simulation time | 2711838413 ps |
| CPU time | 102.59 seconds |
| Started | Jul 31 07:59:42 PM PDT 24 |
| Finished | Jul 31 08:01:25 PM PDT 24 |
| Peak memory | 576120 kb |
| Host | smart-e4e1d1b7-a65e-4bd4-be1b-2441e275b670 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427512641 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_error.3427512641 |
| Directory | /workspace/65.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.1299382752 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 6592717655 ps |
| CPU time | 351.99 seconds |
| Started | Jul 31 07:59:44 PM PDT 24 |
| Finished | Jul 31 08:05:36 PM PDT 24 |
| Peak memory | 576876 kb |
| Host | smart-2ab158a1-d81e-4620-89e5-55e354c6154f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299382752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all _with_rand_reset.1299382752 |
| Directory | /workspace/65.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.1117527474 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 66725590 ps |
| CPU time | 33.25 seconds |
| Started | Jul 31 07:59:46 PM PDT 24 |
| Finished | Jul 31 08:00:19 PM PDT 24 |
| Peak memory | 576308 kb |
| Host | smart-6d44906c-6296-440d-9930-d4b41e81e071 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117527474 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_al l_with_reset_error.1117527474 |
| Directory | /workspace/65.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_unmapped_addr.1738695273 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 325030461 ps |
| CPU time | 38.83 seconds |
| Started | Jul 31 07:59:43 PM PDT 24 |
| Finished | Jul 31 08:00:22 PM PDT 24 |
| Peak memory | 576056 kb |
| Host | smart-4e98562e-bcd9-44f7-ba45-c3bd49607d2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738695273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_unmapped_addr.1738695273 |
| Directory | /workspace/65.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device.2776856348 |
| Short name | T1587 |
| Test name | |
| Test status | |
| Simulation time | 2966891563 ps |
| CPU time | 114.9 seconds |
| Started | Jul 31 07:59:51 PM PDT 24 |
| Finished | Jul 31 08:01:46 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-d4f55ce8-93af-4e83-8552-a817892e3972 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776856348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device .2776856348 |
| Directory | /workspace/66.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.2191407129 |
| Short name | T2293 |
| Test name | |
| Test status | |
| Simulation time | 122286372557 ps |
| CPU time | 2209.16 seconds |
| Started | Jul 31 07:59:49 PM PDT 24 |
| Finished | Jul 31 08:36:39 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-1ca70071-c970-47eb-84eb-5dc78fab435b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191407129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_ device_slow_rsp.2191407129 |
| Directory | /workspace/66.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.1749472241 |
| Short name | T2003 |
| Test name | |
| Test status | |
| Simulation time | 141453625 ps |
| CPU time | 16.27 seconds |
| Started | Jul 31 07:59:51 PM PDT 24 |
| Finished | Jul 31 08:00:07 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-579e790e-8da8-451c-bcfd-c977922c896c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749472241 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_and_unmapped_add r.1749472241 |
| Directory | /workspace/66.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_random.3083254619 |
| Short name | T1884 |
| Test name | |
| Test status | |
| Simulation time | 256944926 ps |
| CPU time | 20.98 seconds |
| Started | Jul 31 07:59:50 PM PDT 24 |
| Finished | Jul 31 08:00:11 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-e4bec803-8a95-4396-a44f-af8ece2fc413 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083254619 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_random.3083254619 |
| Directory | /workspace/66.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random.3588076838 |
| Short name | T2018 |
| Test name | |
| Test status | |
| Simulation time | 1581431122 ps |
| CPU time | 60.66 seconds |
| Started | Jul 31 07:59:46 PM PDT 24 |
| Finished | Jul 31 08:00:46 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-b9f8e1a7-8031-45ab-a18d-19040cbcde1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588076838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random.3588076838 |
| Directory | /workspace/66.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_large_delays.2514857726 |
| Short name | T2683 |
| Test name | |
| Test status | |
| Simulation time | 101145238390 ps |
| CPU time | 1033.82 seconds |
| Started | Jul 31 07:59:44 PM PDT 24 |
| Finished | Jul 31 08:16:58 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-cb9a762f-8c31-491c-82d5-264c46144bce |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514857726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_large_delays.2514857726 |
| Directory | /workspace/66.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_slow_rsp.3101593801 |
| Short name | T1914 |
| Test name | |
| Test status | |
| Simulation time | 41165735179 ps |
| CPU time | 754.87 seconds |
| Started | Jul 31 07:59:49 PM PDT 24 |
| Finished | Jul 31 08:12:24 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-c7b6929d-acf8-4656-8a49-61e11cd7ceed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101593801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_slow_rsp.3101593801 |
| Directory | /workspace/66.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_zero_delays.2896836678 |
| Short name | T1763 |
| Test name | |
| Test status | |
| Simulation time | 599111473 ps |
| CPU time | 47.71 seconds |
| Started | Jul 31 07:59:44 PM PDT 24 |
| Finished | Jul 31 08:00:32 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-4d8237fb-5528-4f6d-b605-fc2eec989afd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896836678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_zero_del ays.2896836678 |
| Directory | /workspace/66.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_same_source.2972528789 |
| Short name | T2565 |
| Test name | |
| Test status | |
| Simulation time | 1936685900 ps |
| CPU time | 58.6 seconds |
| Started | Jul 31 07:59:50 PM PDT 24 |
| Finished | Jul 31 08:00:49 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-b65d72aa-c67c-4cc8-b17e-636661ccc264 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972528789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_same_source.2972528789 |
| Directory | /workspace/66.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke.3361943500 |
| Short name | T2313 |
| Test name | |
| Test status | |
| Simulation time | 216408550 ps |
| CPU time | 8.73 seconds |
| Started | Jul 31 07:59:45 PM PDT 24 |
| Finished | Jul 31 07:59:54 PM PDT 24 |
| Peak memory | 573840 kb |
| Host | smart-cd9f6a79-2637-47d5-8a40-964228e65191 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361943500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke.3361943500 |
| Directory | /workspace/66.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_large_delays.913562042 |
| Short name | T2244 |
| Test name | |
| Test status | |
| Simulation time | 8126171933 ps |
| CPU time | 85.83 seconds |
| Started | Jul 31 07:59:44 PM PDT 24 |
| Finished | Jul 31 08:01:10 PM PDT 24 |
| Peak memory | 573896 kb |
| Host | smart-c3d5b7d6-3996-4be0-89c5-37cddcc6ee53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913562042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_large_delays.913562042 |
| Directory | /workspace/66.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.2330012423 |
| Short name | T2880 |
| Test name | |
| Test status | |
| Simulation time | 3969620759 ps |
| CPU time | 66.23 seconds |
| Started | Jul 31 07:59:47 PM PDT 24 |
| Finished | Jul 31 08:00:53 PM PDT 24 |
| Peak memory | 573840 kb |
| Host | smart-22415bfb-8000-44a2-ab25-19ef737cb88d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330012423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_slow_rsp.2330012423 |
| Directory | /workspace/66.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.1133613587 |
| Short name | T2268 |
| Test name | |
| Test status | |
| Simulation time | 34520068 ps |
| CPU time | 5.9 seconds |
| Started | Jul 31 07:59:43 PM PDT 24 |
| Finished | Jul 31 07:59:49 PM PDT 24 |
| Peak memory | 573832 kb |
| Host | smart-fdcbe862-0bf8-47ff-ac85-81cab42ea8f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133613587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_zero_delay s.1133613587 |
| Directory | /workspace/66.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all.1571133894 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 2260241814 ps |
| CPU time | 177.52 seconds |
| Started | Jul 31 07:59:49 PM PDT 24 |
| Finished | Jul 31 08:02:46 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-72fafa29-c049-4636-8512-128debf2447a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571133894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all.1571133894 |
| Directory | /workspace/66.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.1338118529 |
| Short name | T2533 |
| Test name | |
| Test status | |
| Simulation time | 8279292638 ps |
| CPU time | 252.23 seconds |
| Started | Jul 31 07:59:50 PM PDT 24 |
| Finished | Jul 31 08:04:02 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-48709f36-8e84-4e96-abb2-44feaa64af66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338118529 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_error.1338118529 |
| Directory | /workspace/66.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.65719264 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 512045301 ps |
| CPU time | 121.51 seconds |
| Started | Jul 31 07:59:56 PM PDT 24 |
| Finished | Jul 31 08:01:57 PM PDT 24 |
| Peak memory | 576708 kb |
| Host | smart-b057b8c0-a011-4f66-8c70-f60296677aa8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65719264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_w ith_rand_reset.65719264 |
| Directory | /workspace/66.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.2935904621 |
| Short name | T1782 |
| Test name | |
| Test status | |
| Simulation time | 3502164857 ps |
| CPU time | 414.23 seconds |
| Started | Jul 31 07:59:52 PM PDT 24 |
| Finished | Jul 31 08:06:46 PM PDT 24 |
| Peak memory | 577068 kb |
| Host | smart-c09de8c8-38be-4321-b200-a816b9ec471a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935904621 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_al l_with_reset_error.2935904621 |
| Directory | /workspace/66.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.3477841013 |
| Short name | T2048 |
| Test name | |
| Test status | |
| Simulation time | 102464780 ps |
| CPU time | 13.84 seconds |
| Started | Jul 31 07:59:48 PM PDT 24 |
| Finished | Jul 31 08:00:02 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-70289242-bc2d-4215-b056-137d9ea1aad1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477841013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_unmapped_addr.3477841013 |
| Directory | /workspace/66.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device.2146453428 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 2147069993 ps |
| CPU time | 81.89 seconds |
| Started | Jul 31 07:59:57 PM PDT 24 |
| Finished | Jul 31 08:01:19 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-c7cf9d44-153a-438f-b1c1-a2120889cc9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146453428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device .2146453428 |
| Directory | /workspace/67.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.2215853848 |
| Short name | T2473 |
| Test name | |
| Test status | |
| Simulation time | 65279182727 ps |
| CPU time | 1217.48 seconds |
| Started | Jul 31 07:59:59 PM PDT 24 |
| Finished | Jul 31 08:20:17 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-ed6adb51-6de9-4885-818d-f04ed74cde03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215853848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_ device_slow_rsp.2215853848 |
| Directory | /workspace/67.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.69533421 |
| Short name | T2295 |
| Test name | |
| Test status | |
| Simulation time | 1441086244 ps |
| CPU time | 51 seconds |
| Started | Jul 31 08:00:00 PM PDT 24 |
| Finished | Jul 31 08:00:52 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-9cff5e78-3281-40b2-9250-0afe7caa3370 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69533421 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_and_unmapped_addr.69533421 |
| Directory | /workspace/67.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_random.153290175 |
| Short name | T1767 |
| Test name | |
| Test status | |
| Simulation time | 481145309 ps |
| CPU time | 38.18 seconds |
| Started | Jul 31 07:59:58 PM PDT 24 |
| Finished | Jul 31 08:00:36 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-30a46716-8e2b-4224-8a20-cc738e71e715 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153290175 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_random.153290175 |
| Directory | /workspace/67.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random.1832462393 |
| Short name | T2606 |
| Test name | |
| Test status | |
| Simulation time | 564215825 ps |
| CPU time | 50.05 seconds |
| Started | Jul 31 07:59:57 PM PDT 24 |
| Finished | Jul 31 08:00:47 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-b85ed006-9b98-44e9-af65-4044d562992f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832462393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random.1832462393 |
| Directory | /workspace/67.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_large_delays.2002445339 |
| Short name | T1720 |
| Test name | |
| Test status | |
| Simulation time | 18123679025 ps |
| CPU time | 189.52 seconds |
| Started | Jul 31 08:00:00 PM PDT 24 |
| Finished | Jul 31 08:03:10 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-666eb3cc-923c-4b7a-8352-0cfa110f5fc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002445339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_large_delays.2002445339 |
| Directory | /workspace/67.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_slow_rsp.103326604 |
| Short name | T2463 |
| Test name | |
| Test status | |
| Simulation time | 24048517788 ps |
| CPU time | 396.68 seconds |
| Started | Jul 31 07:59:57 PM PDT 24 |
| Finished | Jul 31 08:06:33 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-71c5fec3-9237-44e7-aa9c-07d92c447913 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103326604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_slow_rsp.103326604 |
| Directory | /workspace/67.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.3325424282 |
| Short name | T2853 |
| Test name | |
| Test status | |
| Simulation time | 378492185 ps |
| CPU time | 32.2 seconds |
| Started | Jul 31 07:59:59 PM PDT 24 |
| Finished | Jul 31 08:00:31 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-a05f1d33-18b3-42f5-b339-2bd8269ff7c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325424282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_zero_del ays.3325424282 |
| Directory | /workspace/67.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_same_source.3271767667 |
| Short name | T2438 |
| Test name | |
| Test status | |
| Simulation time | 642679360 ps |
| CPU time | 21.75 seconds |
| Started | Jul 31 07:59:59 PM PDT 24 |
| Finished | Jul 31 08:00:20 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-58689863-97d0-4ace-b982-1a427d90db7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271767667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_same_source.3271767667 |
| Directory | /workspace/67.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke.3497235295 |
| Short name | T2767 |
| Test name | |
| Test status | |
| Simulation time | 43303713 ps |
| CPU time | 5.97 seconds |
| Started | Jul 31 07:59:59 PM PDT 24 |
| Finished | Jul 31 08:00:05 PM PDT 24 |
| Peak memory | 573832 kb |
| Host | smart-377b42cf-90b8-4e7b-9e97-d237483e2a46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497235295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke.3497235295 |
| Directory | /workspace/67.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_large_delays.2379753611 |
| Short name | T2832 |
| Test name | |
| Test status | |
| Simulation time | 9371824449 ps |
| CPU time | 94.46 seconds |
| Started | Jul 31 07:59:51 PM PDT 24 |
| Finished | Jul 31 08:01:26 PM PDT 24 |
| Peak memory | 573912 kb |
| Host | smart-6b915f7a-9896-4c68-91bd-b278314524ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379753611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_large_delays.2379753611 |
| Directory | /workspace/67.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.3877565892 |
| Short name | T2858 |
| Test name | |
| Test status | |
| Simulation time | 5875849188 ps |
| CPU time | 100.21 seconds |
| Started | Jul 31 07:59:57 PM PDT 24 |
| Finished | Jul 31 08:01:37 PM PDT 24 |
| Peak memory | 573872 kb |
| Host | smart-449e6a79-de20-4afc-85ce-c98776780ece |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877565892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_slow_rsp.3877565892 |
| Directory | /workspace/67.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_zero_delays.2019998425 |
| Short name | T2181 |
| Test name | |
| Test status | |
| Simulation time | 54507165 ps |
| CPU time | 6.82 seconds |
| Started | Jul 31 08:00:00 PM PDT 24 |
| Finished | Jul 31 08:00:07 PM PDT 24 |
| Peak memory | 573908 kb |
| Host | smart-7a9390eb-909b-4ff6-a2e8-d58e3a5c4eb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019998425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_zero_delay s.2019998425 |
| Directory | /workspace/67.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all.1269095768 |
| Short name | T2332 |
| Test name | |
| Test status | |
| Simulation time | 3079135210 ps |
| CPU time | 238.39 seconds |
| Started | Jul 31 08:00:01 PM PDT 24 |
| Finished | Jul 31 08:04:04 PM PDT 24 |
| Peak memory | 576692 kb |
| Host | smart-0acf0078-8f61-4a79-a9a2-643c29ff663b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269095768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all.1269095768 |
| Directory | /workspace/67.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_error.3798543584 |
| Short name | T1486 |
| Test name | |
| Test status | |
| Simulation time | 1534805998 ps |
| CPU time | 55.88 seconds |
| Started | Jul 31 08:00:05 PM PDT 24 |
| Finished | Jul 31 08:01:01 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-620abf36-053f-447f-b537-ff38c15bb3cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798543584 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_error.3798543584 |
| Directory | /workspace/67.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.3292225890 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 17529619300 ps |
| CPU time | 900.85 seconds |
| Started | Jul 31 08:00:07 PM PDT 24 |
| Finished | Jul 31 08:15:08 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-e695cfb6-c57b-4382-bd9f-ab7bdcd6d0aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292225890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all _with_rand_reset.3292225890 |
| Directory | /workspace/67.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.2518459875 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 4328125690 ps |
| CPU time | 283.66 seconds |
| Started | Jul 31 08:00:07 PM PDT 24 |
| Finished | Jul 31 08:04:50 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-6e477ca2-4975-4872-b321-7343efdd524d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518459875 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_al l_with_reset_error.2518459875 |
| Directory | /workspace/67.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_unmapped_addr.1050129899 |
| Short name | T2172 |
| Test name | |
| Test status | |
| Simulation time | 757506311 ps |
| CPU time | 34.96 seconds |
| Started | Jul 31 07:59:57 PM PDT 24 |
| Finished | Jul 31 08:00:32 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-6b453ab6-b80b-4831-892a-5bfede05275f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050129899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_unmapped_addr.1050129899 |
| Directory | /workspace/67.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device.2282048798 |
| Short name | T2088 |
| Test name | |
| Test status | |
| Simulation time | 895974682 ps |
| CPU time | 65.32 seconds |
| Started | Jul 31 08:00:10 PM PDT 24 |
| Finished | Jul 31 08:01:15 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-590b6fd7-6c92-4236-8c2e-e215e57365e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282048798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device .2282048798 |
| Directory | /workspace/68.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.1026041471 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 23457254526 ps |
| CPU time | 428.91 seconds |
| Started | Jul 31 08:00:11 PM PDT 24 |
| Finished | Jul 31 08:07:20 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-2432dca7-00fb-4689-82de-819857589245 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026041471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_ device_slow_rsp.1026041471 |
| Directory | /workspace/68.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.974844933 |
| Short name | T2594 |
| Test name | |
| Test status | |
| Simulation time | 40865291 ps |
| CPU time | 7.09 seconds |
| Started | Jul 31 08:00:16 PM PDT 24 |
| Finished | Jul 31 08:00:23 PM PDT 24 |
| Peak memory | 573860 kb |
| Host | smart-451108cd-ecd6-4053-8437-c20eb009a237 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974844933 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_and_unmapped_addr .974844933 |
| Directory | /workspace/68.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_random.4267593165 |
| Short name | T1441 |
| Test name | |
| Test status | |
| Simulation time | 1714131276 ps |
| CPU time | 60.75 seconds |
| Started | Jul 31 08:00:09 PM PDT 24 |
| Finished | Jul 31 08:01:09 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-98e28c53-3995-4ea6-be82-efa349f35ebc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267593165 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_random.4267593165 |
| Directory | /workspace/68.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random.414711547 |
| Short name | T1467 |
| Test name | |
| Test status | |
| Simulation time | 303031105 ps |
| CPU time | 29.26 seconds |
| Started | Jul 31 08:00:04 PM PDT 24 |
| Finished | Jul 31 08:00:35 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-2ccbb3c0-a534-4016-86fb-2eb02118898b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414711547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random.414711547 |
| Directory | /workspace/68.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_large_delays.2352065437 |
| Short name | T2498 |
| Test name | |
| Test status | |
| Simulation time | 5731538501 ps |
| CPU time | 58.84 seconds |
| Started | Jul 31 08:00:02 PM PDT 24 |
| Finished | Jul 31 08:01:04 PM PDT 24 |
| Peak memory | 573916 kb |
| Host | smart-23dfedcb-b70d-42f2-8c99-119143d21511 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352065437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_large_delays.2352065437 |
| Directory | /workspace/68.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_slow_rsp.3614005106 |
| Short name | T2568 |
| Test name | |
| Test status | |
| Simulation time | 35913531997 ps |
| CPU time | 611.47 seconds |
| Started | Jul 31 08:00:08 PM PDT 24 |
| Finished | Jul 31 08:10:20 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-4bd8fac6-1f90-43ac-b871-3d1de42e8c3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614005106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_slow_rsp.3614005106 |
| Directory | /workspace/68.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_zero_delays.145376406 |
| Short name | T1806 |
| Test name | |
| Test status | |
| Simulation time | 483219534 ps |
| CPU time | 43.74 seconds |
| Started | Jul 31 08:00:02 PM PDT 24 |
| Finished | Jul 31 08:00:49 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-054498b8-6c3a-4cce-9ee7-5b7400236cdc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145376406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_zero_dela ys.145376406 |
| Directory | /workspace/68.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_same_source.2013648178 |
| Short name | T2812 |
| Test name | |
| Test status | |
| Simulation time | 587501234 ps |
| CPU time | 38.83 seconds |
| Started | Jul 31 08:00:08 PM PDT 24 |
| Finished | Jul 31 08:00:47 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-00891091-14a2-458c-a5bb-044489d3fe71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013648178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_same_source.2013648178 |
| Directory | /workspace/68.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke.1632907514 |
| Short name | T1521 |
| Test name | |
| Test status | |
| Simulation time | 229550326 ps |
| CPU time | 9.53 seconds |
| Started | Jul 31 08:00:03 PM PDT 24 |
| Finished | Jul 31 08:00:15 PM PDT 24 |
| Peak memory | 573748 kb |
| Host | smart-0b4064a7-2739-471a-81fa-95208d4a2511 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632907514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke.1632907514 |
| Directory | /workspace/68.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_large_delays.706887439 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 7854759193 ps |
| CPU time | 82.39 seconds |
| Started | Jul 31 08:00:02 PM PDT 24 |
| Finished | Jul 31 08:01:28 PM PDT 24 |
| Peak memory | 574584 kb |
| Host | smart-88950673-f1a0-4c03-a069-9f6015e128fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706887439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_large_delays.706887439 |
| Directory | /workspace/68.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.3062865981 |
| Short name | T1712 |
| Test name | |
| Test status | |
| Simulation time | 5378272984 ps |
| CPU time | 90.38 seconds |
| Started | Jul 31 08:00:06 PM PDT 24 |
| Finished | Jul 31 08:01:37 PM PDT 24 |
| Peak memory | 573880 kb |
| Host | smart-216bf5ff-f5c5-4e14-836b-76020ea37d4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062865981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_slow_rsp.3062865981 |
| Directory | /workspace/68.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_zero_delays.1037381942 |
| Short name | T2418 |
| Test name | |
| Test status | |
| Simulation time | 54424330 ps |
| CPU time | 7.34 seconds |
| Started | Jul 31 08:00:04 PM PDT 24 |
| Finished | Jul 31 08:00:13 PM PDT 24 |
| Peak memory | 573716 kb |
| Host | smart-fd7bbf2a-5670-43aa-9342-6fc24c0bc384 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037381942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_zero_delay s.1037381942 |
| Directory | /workspace/68.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all.3405190851 |
| Short name | T1780 |
| Test name | |
| Test status | |
| Simulation time | 1086793934 ps |
| CPU time | 86.58 seconds |
| Started | Jul 31 08:00:12 PM PDT 24 |
| Finished | Jul 31 08:01:39 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-a2ea9b68-8195-48d1-b21e-577716c38a43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405190851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all.3405190851 |
| Directory | /workspace/68.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.1624774607 |
| Short name | T2741 |
| Test name | |
| Test status | |
| Simulation time | 6292893100 ps |
| CPU time | 229.36 seconds |
| Started | Jul 31 08:00:17 PM PDT 24 |
| Finished | Jul 31 08:04:06 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-02b34647-024e-48b3-ac9e-34cc9158668a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624774607 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_error.1624774607 |
| Directory | /workspace/68.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.832637703 |
| Short name | T1963 |
| Test name | |
| Test status | |
| Simulation time | 5076403808 ps |
| CPU time | 754.22 seconds |
| Started | Jul 31 08:00:09 PM PDT 24 |
| Finished | Jul 31 08:12:44 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-0183ba61-6a05-4643-92ed-d7d3c791362b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832637703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_ with_rand_reset.832637703 |
| Directory | /workspace/68.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_unmapped_addr.2114305281 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 741683561 ps |
| CPU time | 34.1 seconds |
| Started | Jul 31 08:00:10 PM PDT 24 |
| Finished | Jul 31 08:00:44 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-ca28f310-a309-4e7a-812d-b459b94be2ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114305281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_unmapped_addr.2114305281 |
| Directory | /workspace/68.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device.3232691386 |
| Short name | T2205 |
| Test name | |
| Test status | |
| Simulation time | 631886921 ps |
| CPU time | 24.27 seconds |
| Started | Jul 31 08:00:17 PM PDT 24 |
| Finished | Jul 31 08:00:41 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-29ef4b0a-61f0-4fcc-9e95-80c965ed849b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232691386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device .3232691386 |
| Directory | /workspace/69.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.4259168791 |
| Short name | T2878 |
| Test name | |
| Test status | |
| Simulation time | 24906509898 ps |
| CPU time | 384.58 seconds |
| Started | Jul 31 08:00:15 PM PDT 24 |
| Finished | Jul 31 08:06:40 PM PDT 24 |
| Peak memory | 576052 kb |
| Host | smart-e820eda3-3949-48c9-b816-0ae5de004a71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259168791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_ device_slow_rsp.4259168791 |
| Directory | /workspace/69.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.3910415721 |
| Short name | T1406 |
| Test name | |
| Test status | |
| Simulation time | 360860688 ps |
| CPU time | 16.22 seconds |
| Started | Jul 31 08:00:15 PM PDT 24 |
| Finished | Jul 31 08:00:32 PM PDT 24 |
| Peak memory | 576048 kb |
| Host | smart-f5c3a7d6-aad7-4561-b98a-3ae3124aad17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910415721 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_and_unmapped_add r.3910415721 |
| Directory | /workspace/69.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_random.463659669 |
| Short name | T1585 |
| Test name | |
| Test status | |
| Simulation time | 515258481 ps |
| CPU time | 40.56 seconds |
| Started | Jul 31 08:00:17 PM PDT 24 |
| Finished | Jul 31 08:00:58 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-58fe8d39-3a3f-4fb7-8dfd-f8d1b0f9010d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463659669 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_random.463659669 |
| Directory | /workspace/69.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random.1718687720 |
| Short name | T2002 |
| Test name | |
| Test status | |
| Simulation time | 1821860672 ps |
| CPU time | 61.93 seconds |
| Started | Jul 31 08:00:08 PM PDT 24 |
| Finished | Jul 31 08:01:10 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-c2c2666c-2596-4dd6-9311-0d5e891eb197 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718687720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random.1718687720 |
| Directory | /workspace/69.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_large_delays.3361193082 |
| Short name | T2333 |
| Test name | |
| Test status | |
| Simulation time | 28360612366 ps |
| CPU time | 308.98 seconds |
| Started | Jul 31 08:00:17 PM PDT 24 |
| Finished | Jul 31 08:05:26 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-d769581b-eb53-43f1-aff1-0f7499e5d81a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361193082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_large_delays.3361193082 |
| Directory | /workspace/69.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_slow_rsp.4259619755 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 69830799872 ps |
| CPU time | 1270.08 seconds |
| Started | Jul 31 08:00:17 PM PDT 24 |
| Finished | Jul 31 08:21:28 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-85f0de96-ff88-444f-9baf-bfc8771b8b7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259619755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_slow_rsp.4259619755 |
| Directory | /workspace/69.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_zero_delays.870623952 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 396587200 ps |
| CPU time | 35.88 seconds |
| Started | Jul 31 08:00:17 PM PDT 24 |
| Finished | Jul 31 08:00:53 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-cca13086-bdae-4db2-bf19-9026837c441b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870623952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_zero_dela ys.870623952 |
| Directory | /workspace/69.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_same_source.2401844173 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 586743261 ps |
| CPU time | 41.57 seconds |
| Started | Jul 31 08:00:16 PM PDT 24 |
| Finished | Jul 31 08:00:58 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-94c5f98d-26b6-404e-a4df-aed848ff5956 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401844173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_same_source.2401844173 |
| Directory | /workspace/69.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke.108268294 |
| Short name | T1992 |
| Test name | |
| Test status | |
| Simulation time | 200887977 ps |
| CPU time | 8.36 seconds |
| Started | Jul 31 08:00:13 PM PDT 24 |
| Finished | Jul 31 08:00:21 PM PDT 24 |
| Peak memory | 573804 kb |
| Host | smart-8e582de7-cc16-4125-89ab-8286173610f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108268294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke.108268294 |
| Directory | /workspace/69.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_large_delays.1341043598 |
| Short name | T1420 |
| Test name | |
| Test status | |
| Simulation time | 9658297719 ps |
| CPU time | 100.63 seconds |
| Started | Jul 31 08:00:09 PM PDT 24 |
| Finished | Jul 31 08:01:50 PM PDT 24 |
| Peak memory | 573932 kb |
| Host | smart-135e2d57-704e-4b62-b144-35e5e12ed021 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341043598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_large_delays.1341043598 |
| Directory | /workspace/69.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.4103908542 |
| Short name | T2091 |
| Test name | |
| Test status | |
| Simulation time | 5303009025 ps |
| CPU time | 91.69 seconds |
| Started | Jul 31 08:00:13 PM PDT 24 |
| Finished | Jul 31 08:01:44 PM PDT 24 |
| Peak memory | 573872 kb |
| Host | smart-a09e238b-bc9f-4e01-a555-7c6d68961af7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103908542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_slow_rsp.4103908542 |
| Directory | /workspace/69.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_zero_delays.3193098741 |
| Short name | T2480 |
| Test name | |
| Test status | |
| Simulation time | 50756301 ps |
| CPU time | 6.78 seconds |
| Started | Jul 31 08:00:17 PM PDT 24 |
| Finished | Jul 31 08:00:24 PM PDT 24 |
| Peak memory | 573772 kb |
| Host | smart-77e50477-b514-4c39-9847-df2d440ed1e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193098741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_zero_delay s.3193098741 |
| Directory | /workspace/69.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all.353975028 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 356554707 ps |
| CPU time | 30.43 seconds |
| Started | Jul 31 08:00:17 PM PDT 24 |
| Finished | Jul 31 08:00:47 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-0c22886f-fb98-48b8-b87a-70386c71785f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353975028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all.353975028 |
| Directory | /workspace/69.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.3998608694 |
| Short name | T1934 |
| Test name | |
| Test status | |
| Simulation time | 1139944225 ps |
| CPU time | 81.93 seconds |
| Started | Jul 31 08:00:16 PM PDT 24 |
| Finished | Jul 31 08:01:38 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-71a4ac00-4456-487c-9d80-f57d62a67370 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998608694 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_error.3998608694 |
| Directory | /workspace/69.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.2327480004 |
| Short name | T2881 |
| Test name | |
| Test status | |
| Simulation time | 3063542604 ps |
| CPU time | 266.07 seconds |
| Started | Jul 31 08:00:15 PM PDT 24 |
| Finished | Jul 31 08:04:41 PM PDT 24 |
| Peak memory | 576804 kb |
| Host | smart-4fa9e8c9-620a-4526-83a1-bc609b1501aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327480004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all _with_rand_reset.2327480004 |
| Directory | /workspace/69.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.3715096334 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 14402763037 ps |
| CPU time | 760.01 seconds |
| Started | Jul 31 08:00:18 PM PDT 24 |
| Finished | Jul 31 08:12:58 PM PDT 24 |
| Peak memory | 576884 kb |
| Host | smart-854e4238-6965-4998-a378-8d854355a989 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715096334 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_al l_with_reset_error.3715096334 |
| Directory | /workspace/69.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.3727892357 |
| Short name | T2402 |
| Test name | |
| Test status | |
| Simulation time | 86810718 ps |
| CPU time | 12.5 seconds |
| Started | Jul 31 08:00:19 PM PDT 24 |
| Finished | Jul 31 08:00:32 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-1f805211-20ef-4853-b5d8-c8cd2e49804a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727892357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_unmapped_addr.3727892357 |
| Directory | /workspace/69.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.2348189845 |
| Short name | T1616 |
| Test name | |
| Test status | |
| Simulation time | 7345607628 ps |
| CPU time | 480.36 seconds |
| Started | Jul 31 07:47:33 PM PDT 24 |
| Finished | Jul 31 07:55:33 PM PDT 24 |
| Peak memory | 642916 kb |
| Host | smart-83fef06b-42f8-4bf4-8042-1b036d873478 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348189845 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 7.chip_csr_mem_rw_with_rand_reset.2348189845 |
| Directory | /workspace/7.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_csr_rw.4282590505 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 5287578510 ps |
| CPU time | 551.87 seconds |
| Started | Jul 31 07:47:25 PM PDT 24 |
| Finished | Jul 31 07:56:37 PM PDT 24 |
| Peak memory | 597616 kb |
| Host | smart-f51eddc2-57fe-482a-adc4-24b1fb945953 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282590505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_rw.4282590505 |
| Directory | /workspace/7.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.3692531553 |
| Short name | T2225 |
| Test name | |
| Test status | |
| Simulation time | 27197546212 ps |
| CPU time | 3824.75 seconds |
| Started | Jul 31 07:47:08 PM PDT 24 |
| Finished | Jul 31 08:50:53 PM PDT 24 |
| Peak memory | 593356 kb |
| Host | smart-1edf2d07-15f5-44a5-8a07-aea425388489 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692531553 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 7.chip_same_csr_outstanding.3692531553 |
| Directory | /workspace/7.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_tl_errors.3530916991 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 3848011904 ps |
| CPU time | 179.69 seconds |
| Started | Jul 31 07:47:11 PM PDT 24 |
| Finished | Jul 31 07:50:11 PM PDT 24 |
| Peak memory | 603740 kb |
| Host | smart-db86c682-a091-45b2-b03f-67b1ba92424b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530916991 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_tl_errors.3530916991 |
| Directory | /workspace/7.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device.3890600521 |
| Short name | T1811 |
| Test name | |
| Test status | |
| Simulation time | 644342007 ps |
| CPU time | 28.28 seconds |
| Started | Jul 31 07:47:25 PM PDT 24 |
| Finished | Jul 31 07:47:53 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-b088918c-a501-41a1-b023-7b8630d7b71d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890600521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device. 3890600521 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.2405557765 |
| Short name | T1747 |
| Test name | |
| Test status | |
| Simulation time | 94100761446 ps |
| CPU time | 1639.43 seconds |
| Started | Jul 31 07:47:24 PM PDT 24 |
| Finished | Jul 31 08:14:44 PM PDT 24 |
| Peak memory | 576056 kb |
| Host | smart-03cd98a1-4fff-4e91-b20c-9cb807c3497c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405557765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_d evice_slow_rsp.2405557765 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.2790986225 |
| Short name | T2711 |
| Test name | |
| Test status | |
| Simulation time | 21817992 ps |
| CPU time | 4.97 seconds |
| Started | Jul 31 07:47:24 PM PDT 24 |
| Finished | Jul 31 07:47:29 PM PDT 24 |
| Peak memory | 573788 kb |
| Host | smart-c8b985d7-f600-4918-9512-73d5d0d708dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790986225 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr .2790986225 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_random.3271440090 |
| Short name | T1588 |
| Test name | |
| Test status | |
| Simulation time | 276625310 ps |
| CPU time | 10.98 seconds |
| Started | Jul 31 07:47:25 PM PDT 24 |
| Finished | Jul 31 07:47:36 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-f217080c-a420-42a2-9aa0-7893be0bddd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271440090 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.3271440090 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random.4289630201 |
| Short name | T1785 |
| Test name | |
| Test status | |
| Simulation time | 1903154559 ps |
| CPU time | 70.55 seconds |
| Started | Jul 31 07:47:17 PM PDT 24 |
| Finished | Jul 31 07:48:28 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-fa5dfb0d-b064-492b-9673-aa6198d4e05e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289630201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random.4289630201 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_large_delays.175929451 |
| Short name | T2241 |
| Test name | |
| Test status | |
| Simulation time | 21109675181 ps |
| CPU time | 209.05 seconds |
| Started | Jul 31 07:47:18 PM PDT 24 |
| Finished | Jul 31 07:50:47 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-19996675-e872-4437-98a9-157390c36417 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175929451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.175929451 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.60397027 |
| Short name | T2133 |
| Test name | |
| Test status | |
| Simulation time | 35895076994 ps |
| CPU time | 610.46 seconds |
| Started | Jul 31 07:47:19 PM PDT 24 |
| Finished | Jul 31 07:57:29 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-1c6132a8-bea3-4770-9ab5-5f772be1f0a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60397027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.60397027 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_zero_delays.4278888636 |
| Short name | T2776 |
| Test name | |
| Test status | |
| Simulation time | 311960354 ps |
| CPU time | 27.33 seconds |
| Started | Jul 31 07:47:16 PM PDT 24 |
| Finished | Jul 31 07:47:43 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-dac36902-13b5-4255-b92b-066d04a48727 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278888636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_dela ys.4278888636 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_same_source.2747108261 |
| Short name | T1743 |
| Test name | |
| Test status | |
| Simulation time | 2189069600 ps |
| CPU time | 68 seconds |
| Started | Jul 31 07:47:25 PM PDT 24 |
| Finished | Jul 31 07:48:33 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-69b3ae54-3573-45b6-a09e-f276096f889e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747108261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.2747108261 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke.1959609577 |
| Short name | T1491 |
| Test name | |
| Test status | |
| Simulation time | 56009178 ps |
| CPU time | 6.96 seconds |
| Started | Jul 31 07:47:11 PM PDT 24 |
| Finished | Jul 31 07:47:18 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-c20c48a9-135f-419c-b033-d8f475e27721 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959609577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.1959609577 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_large_delays.411131200 |
| Short name | T1429 |
| Test name | |
| Test status | |
| Simulation time | 6192237217 ps |
| CPU time | 63.66 seconds |
| Started | Jul 31 07:47:16 PM PDT 24 |
| Finished | Jul 31 07:48:20 PM PDT 24 |
| Peak memory | 574580 kb |
| Host | smart-2f61d988-8bfc-4815-b51c-3093e4826597 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411131200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.411131200 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.3837011978 |
| Short name | T1699 |
| Test name | |
| Test status | |
| Simulation time | 5258164057 ps |
| CPU time | 86.63 seconds |
| Started | Jul 31 07:47:18 PM PDT 24 |
| Finished | Jul 31 07:48:45 PM PDT 24 |
| Peak memory | 573864 kb |
| Host | smart-0b82257f-89ec-42ae-aae5-da4fea8a6ceb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837011978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.3837011978 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_zero_delays.3617132997 |
| Short name | T1497 |
| Test name | |
| Test status | |
| Simulation time | 54328032 ps |
| CPU time | 7.11 seconds |
| Started | Jul 31 07:47:19 PM PDT 24 |
| Finished | Jul 31 07:47:26 PM PDT 24 |
| Peak memory | 574608 kb |
| Host | smart-074728ed-1415-46ba-8f15-ce6c7cbc44f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617132997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays .3617132997 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all.1580465324 |
| Short name | T2039 |
| Test name | |
| Test status | |
| Simulation time | 330757034 ps |
| CPU time | 25.95 seconds |
| Started | Jul 31 07:47:26 PM PDT 24 |
| Finished | Jul 31 07:47:52 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-90cfc80f-710f-4985-8997-7522752ff713 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580465324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.1580465324 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.2042137365 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 6409803884 ps |
| CPU time | 212.66 seconds |
| Started | Jul 31 07:47:26 PM PDT 24 |
| Finished | Jul 31 07:50:58 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-0a9bb907-ada9-429d-b869-45698338540c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042137365 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.2042137365 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.1296931467 |
| Short name | T2107 |
| Test name | |
| Test status | |
| Simulation time | 430643777 ps |
| CPU time | 159.35 seconds |
| Started | Jul 31 07:47:25 PM PDT 24 |
| Finished | Jul 31 07:50:05 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-9e05bab6-1dc9-4797-b159-7d7ff8b68afe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296931467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_ with_rand_reset.1296931467 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.3629394636 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 5606969211 ps |
| CPU time | 509.54 seconds |
| Started | Jul 31 07:47:25 PM PDT 24 |
| Finished | Jul 31 07:55:55 PM PDT 24 |
| Peak memory | 576796 kb |
| Host | smart-b0bf2cde-8023-4c34-9604-dad116b03094 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629394636 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all _with_reset_error.3629394636 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_unmapped_addr.2565521655 |
| Short name | T2693 |
| Test name | |
| Test status | |
| Simulation time | 258006143 ps |
| CPU time | 27.93 seconds |
| Started | Jul 31 07:47:24 PM PDT 24 |
| Finished | Jul 31 07:47:52 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-58bd2bfe-fec7-4ff3-8b7a-eef6bcf1bd80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565521655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.2565521655 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device.4030137065 |
| Short name | T2106 |
| Test name | |
| Test status | |
| Simulation time | 372541347 ps |
| CPU time | 29.89 seconds |
| Started | Jul 31 08:00:22 PM PDT 24 |
| Finished | Jul 31 08:00:52 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-b927048c-9732-4e0c-88c6-59a2d2d597c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030137065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device .4030137065 |
| Directory | /workspace/70.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.4224202919 |
| Short name | T2411 |
| Test name | |
| Test status | |
| Simulation time | 50603710389 ps |
| CPU time | 965.15 seconds |
| Started | Jul 31 08:00:23 PM PDT 24 |
| Finished | Jul 31 08:16:28 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-dd7b9d0c-b49d-43ce-8c46-a852a7176bc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224202919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_ device_slow_rsp.4224202919 |
| Directory | /workspace/70.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.244571202 |
| Short name | T2855 |
| Test name | |
| Test status | |
| Simulation time | 774201383 ps |
| CPU time | 35.59 seconds |
| Started | Jul 31 08:00:27 PM PDT 24 |
| Finished | Jul 31 08:01:03 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-018de313-4cda-424a-a95f-d0b132f09bec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244571202 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_and_unmapped_addr .244571202 |
| Directory | /workspace/70.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_random.2785263739 |
| Short name | T2766 |
| Test name | |
| Test status | |
| Simulation time | 253519414 ps |
| CPU time | 10.77 seconds |
| Started | Jul 31 08:00:24 PM PDT 24 |
| Finished | Jul 31 08:00:35 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-24feccaf-90e2-45c8-8570-303c1c2d78e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785263739 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_random.2785263739 |
| Directory | /workspace/70.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random.49300354 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 1869987339 ps |
| CPU time | 67.28 seconds |
| Started | Jul 31 08:00:21 PM PDT 24 |
| Finished | Jul 31 08:01:28 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-792fad0a-17e6-426f-aabf-13c0f6742bc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49300354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random.49300354 |
| Directory | /workspace/70.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_large_delays.143268109 |
| Short name | T2577 |
| Test name | |
| Test status | |
| Simulation time | 79028377575 ps |
| CPU time | 877.3 seconds |
| Started | Jul 31 08:00:22 PM PDT 24 |
| Finished | Jul 31 08:15:00 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-754d3aac-e342-427a-8af9-0be4fd075fbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143268109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_large_delays.143268109 |
| Directory | /workspace/70.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_slow_rsp.3603194797 |
| Short name | T2698 |
| Test name | |
| Test status | |
| Simulation time | 59074057484 ps |
| CPU time | 939.52 seconds |
| Started | Jul 31 08:00:24 PM PDT 24 |
| Finished | Jul 31 08:16:03 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-bdc6728c-3d13-4894-9839-adf1cc3f608a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603194797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_slow_rsp.3603194797 |
| Directory | /workspace/70.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.1025320428 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 533555052 ps |
| CPU time | 41.37 seconds |
| Started | Jul 31 08:00:20 PM PDT 24 |
| Finished | Jul 31 08:01:02 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-0a1e88dd-8736-4bb6-9a9f-ece09cde29af |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025320428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_zero_del ays.1025320428 |
| Directory | /workspace/70.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_same_source.1235134190 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 2313364989 ps |
| CPU time | 68.94 seconds |
| Started | Jul 31 08:00:22 PM PDT 24 |
| Finished | Jul 31 08:01:31 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-6dea0361-51cd-4e04-ae9a-7ee6b2e1c5dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235134190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_same_source.1235134190 |
| Directory | /workspace/70.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke.2824173622 |
| Short name | T2317 |
| Test name | |
| Test status | |
| Simulation time | 210433446 ps |
| CPU time | 9.09 seconds |
| Started | Jul 31 08:00:22 PM PDT 24 |
| Finished | Jul 31 08:00:31 PM PDT 24 |
| Peak memory | 573844 kb |
| Host | smart-83c71258-8993-4aa5-abca-f3b1ea7690b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824173622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke.2824173622 |
| Directory | /workspace/70.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_large_delays.2875762847 |
| Short name | T1746 |
| Test name | |
| Test status | |
| Simulation time | 8311674931 ps |
| CPU time | 82.85 seconds |
| Started | Jul 31 08:00:22 PM PDT 24 |
| Finished | Jul 31 08:01:45 PM PDT 24 |
| Peak memory | 574412 kb |
| Host | smart-797a901b-476e-4ac5-9ea5-f97e71e611c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875762847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_large_delays.2875762847 |
| Directory | /workspace/70.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.481424817 |
| Short name | T2917 |
| Test name | |
| Test status | |
| Simulation time | 6154351544 ps |
| CPU time | 106.58 seconds |
| Started | Jul 31 08:00:21 PM PDT 24 |
| Finished | Jul 31 08:02:08 PM PDT 24 |
| Peak memory | 573888 kb |
| Host | smart-478cf8ef-b5e8-4ed7-b603-41f5060c492c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481424817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_slow_rsp.481424817 |
| Directory | /workspace/70.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_zero_delays.411312712 |
| Short name | T2572 |
| Test name | |
| Test status | |
| Simulation time | 44599668 ps |
| CPU time | 6.55 seconds |
| Started | Jul 31 08:00:24 PM PDT 24 |
| Finished | Jul 31 08:00:30 PM PDT 24 |
| Peak memory | 573788 kb |
| Host | smart-d18059ba-57e8-4b18-8cba-46e77f031989 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411312712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_zero_delays .411312712 |
| Directory | /workspace/70.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all.1153487200 |
| Short name | T2121 |
| Test name | |
| Test status | |
| Simulation time | 3297812480 ps |
| CPU time | 108.92 seconds |
| Started | Jul 31 08:00:31 PM PDT 24 |
| Finished | Jul 31 08:02:20 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-4fb44731-ebfd-4350-a10d-14edb6653a6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153487200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all.1153487200 |
| Directory | /workspace/70.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.3814783433 |
| Short name | T2833 |
| Test name | |
| Test status | |
| Simulation time | 2878271821 ps |
| CPU time | 233.18 seconds |
| Started | Jul 31 08:00:29 PM PDT 24 |
| Finished | Jul 31 08:04:23 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-e79084be-83fc-4b0c-8273-7f65dcf75b37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814783433 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_error.3814783433 |
| Directory | /workspace/70.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.1356133155 |
| Short name | T2015 |
| Test name | |
| Test status | |
| Simulation time | 231704071 ps |
| CPU time | 93.83 seconds |
| Started | Jul 31 08:00:28 PM PDT 24 |
| Finished | Jul 31 08:02:02 PM PDT 24 |
| Peak memory | 576728 kb |
| Host | smart-2690f919-4e25-4113-b9f5-5e54e8f40bf6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356133155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all _with_rand_reset.1356133155 |
| Directory | /workspace/70.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.2072021827 |
| Short name | T1462 |
| Test name | |
| Test status | |
| Simulation time | 219599378 ps |
| CPU time | 104.08 seconds |
| Started | Jul 31 08:00:28 PM PDT 24 |
| Finished | Jul 31 08:02:12 PM PDT 24 |
| Peak memory | 576748 kb |
| Host | smart-c0304255-7884-40e7-94cf-e38502c4c6a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072021827 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_al l_with_reset_error.2072021827 |
| Directory | /workspace/70.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.88277225 |
| Short name | T2843 |
| Test name | |
| Test status | |
| Simulation time | 160156216 ps |
| CPU time | 19.58 seconds |
| Started | Jul 31 08:00:30 PM PDT 24 |
| Finished | Jul 31 08:00:49 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-c83bd12d-e138-43bb-87ea-64b715206c17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88277225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_unmapped_addr.88277225 |
| Directory | /workspace/70.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device.2239927264 |
| Short name | T2483 |
| Test name | |
| Test status | |
| Simulation time | 192742746 ps |
| CPU time | 18.96 seconds |
| Started | Jul 31 08:00:36 PM PDT 24 |
| Finished | Jul 31 08:00:55 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-db1c24f4-d04b-473e-aab7-265ba4625d92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239927264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device .2239927264 |
| Directory | /workspace/71.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.769204294 |
| Short name | T1555 |
| Test name | |
| Test status | |
| Simulation time | 46023095003 ps |
| CPU time | 867.64 seconds |
| Started | Jul 31 08:00:38 PM PDT 24 |
| Finished | Jul 31 08:15:06 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-357eff93-c25a-4d61-b2cd-22dd7ac36bb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769204294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_d evice_slow_rsp.769204294 |
| Directory | /workspace/71.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.1915435269 |
| Short name | T2344 |
| Test name | |
| Test status | |
| Simulation time | 1136735837 ps |
| CPU time | 36.8 seconds |
| Started | Jul 31 08:00:41 PM PDT 24 |
| Finished | Jul 31 08:01:18 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-d3de7dea-4fef-4896-bcbc-53c93068c8fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915435269 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_and_unmapped_add r.1915435269 |
| Directory | /workspace/71.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_random.3097627458 |
| Short name | T1639 |
| Test name | |
| Test status | |
| Simulation time | 2576118804 ps |
| CPU time | 90.18 seconds |
| Started | Jul 31 08:00:35 PM PDT 24 |
| Finished | Jul 31 08:02:06 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-f429375a-c22d-4530-9573-ee1d1b715cf3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097627458 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_random.3097627458 |
| Directory | /workspace/71.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random.327957806 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 526357329 ps |
| CPU time | 38.14 seconds |
| Started | Jul 31 08:00:27 PM PDT 24 |
| Finished | Jul 31 08:01:05 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-734dc493-841d-4469-8f27-6b664bd2fe3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327957806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random.327957806 |
| Directory | /workspace/71.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_large_delays.2774481793 |
| Short name | T2708 |
| Test name | |
| Test status | |
| Simulation time | 86278106320 ps |
| CPU time | 923.63 seconds |
| Started | Jul 31 08:00:36 PM PDT 24 |
| Finished | Jul 31 08:16:00 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-fe9ca2b4-3a86-4f6c-8b79-0b98fd3f68e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774481793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_large_delays.2774481793 |
| Directory | /workspace/71.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_slow_rsp.2581423529 |
| Short name | T2499 |
| Test name | |
| Test status | |
| Simulation time | 16817611093 ps |
| CPU time | 290.93 seconds |
| Started | Jul 31 08:00:33 PM PDT 24 |
| Finished | Jul 31 08:05:24 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-77af3d4d-336c-4708-9c4d-0e95c5279af7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581423529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_slow_rsp.2581423529 |
| Directory | /workspace/71.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.3805576388 |
| Short name | T2360 |
| Test name | |
| Test status | |
| Simulation time | 523776949 ps |
| CPU time | 51.01 seconds |
| Started | Jul 31 08:00:31 PM PDT 24 |
| Finished | Jul 31 08:01:22 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-5746757f-77b4-4df9-89c1-6dd31831f0fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805576388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_zero_del ays.3805576388 |
| Directory | /workspace/71.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_same_source.2682586103 |
| Short name | T1689 |
| Test name | |
| Test status | |
| Simulation time | 2452508648 ps |
| CPU time | 65.71 seconds |
| Started | Jul 31 08:00:43 PM PDT 24 |
| Finished | Jul 31 08:01:48 PM PDT 24 |
| Peak memory | 576052 kb |
| Host | smart-72e156ac-3cd8-434f-ac14-551bb4f3750b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682586103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_same_source.2682586103 |
| Directory | /workspace/71.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke.410659026 |
| Short name | T1973 |
| Test name | |
| Test status | |
| Simulation time | 163890706 ps |
| CPU time | 8.63 seconds |
| Started | Jul 31 08:00:30 PM PDT 24 |
| Finished | Jul 31 08:00:39 PM PDT 24 |
| Peak memory | 573760 kb |
| Host | smart-ee2acf90-8dbc-48e2-a3f2-da3e1863241b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410659026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke.410659026 |
| Directory | /workspace/71.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_large_delays.397986030 |
| Short name | T1398 |
| Test name | |
| Test status | |
| Simulation time | 7816336325 ps |
| CPU time | 82.59 seconds |
| Started | Jul 31 08:00:30 PM PDT 24 |
| Finished | Jul 31 08:01:52 PM PDT 24 |
| Peak memory | 573900 kb |
| Host | smart-b7ca43ef-8571-4db0-b6ad-b48ea6eb7f06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397986030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_large_delays.397986030 |
| Directory | /workspace/71.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.2553380650 |
| Short name | T2548 |
| Test name | |
| Test status | |
| Simulation time | 5273295388 ps |
| CPU time | 89.31 seconds |
| Started | Jul 31 08:00:30 PM PDT 24 |
| Finished | Jul 31 08:02:00 PM PDT 24 |
| Peak memory | 574016 kb |
| Host | smart-d5b8dede-2af5-4c35-bc49-2929827092fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553380650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_slow_rsp.2553380650 |
| Directory | /workspace/71.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_zero_delays.565967551 |
| Short name | T1412 |
| Test name | |
| Test status | |
| Simulation time | 46302278 ps |
| CPU time | 6.43 seconds |
| Started | Jul 31 08:00:28 PM PDT 24 |
| Finished | Jul 31 08:00:34 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-6c4dab28-b64d-447b-b7b5-f35acc558d63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565967551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_zero_delays .565967551 |
| Directory | /workspace/71.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all.675932702 |
| Short name | T2675 |
| Test name | |
| Test status | |
| Simulation time | 2268587272 ps |
| CPU time | 189.85 seconds |
| Started | Jul 31 08:00:46 PM PDT 24 |
| Finished | Jul 31 08:03:56 PM PDT 24 |
| Peak memory | 576896 kb |
| Host | smart-0b48c55b-c75c-4f95-bb4b-1a826cdb745d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675932702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all.675932702 |
| Directory | /workspace/71.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.3454863486 |
| Short name | T2019 |
| Test name | |
| Test status | |
| Simulation time | 1002396105 ps |
| CPU time | 82.86 seconds |
| Started | Jul 31 08:00:40 PM PDT 24 |
| Finished | Jul 31 08:02:03 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-a9ecdc62-0c20-46a1-bdcc-16ef7d899e4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454863486 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_error.3454863486 |
| Directory | /workspace/71.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.1209315759 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 398433249 ps |
| CPU time | 113.34 seconds |
| Started | Jul 31 08:00:40 PM PDT 24 |
| Finished | Jul 31 08:02:33 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-db6d298a-6ff9-4143-9801-872874ef55eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209315759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all _with_rand_reset.1209315759 |
| Directory | /workspace/71.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.4014148338 |
| Short name | T2541 |
| Test name | |
| Test status | |
| Simulation time | 500110698 ps |
| CPU time | 169.86 seconds |
| Started | Jul 31 08:00:41 PM PDT 24 |
| Finished | Jul 31 08:03:31 PM PDT 24 |
| Peak memory | 576740 kb |
| Host | smart-ee3cfc10-75da-43e5-bb82-66c9e7e8bb64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014148338 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_al l_with_reset_error.4014148338 |
| Directory | /workspace/71.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_unmapped_addr.203093971 |
| Short name | T2712 |
| Test name | |
| Test status | |
| Simulation time | 472904311 ps |
| CPU time | 20.91 seconds |
| Started | Jul 31 08:00:40 PM PDT 24 |
| Finished | Jul 31 08:01:01 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-9822f16d-58a3-465d-ba70-f30f0f1c1d4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203093971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_unmapped_addr.203093971 |
| Directory | /workspace/71.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device.3710122406 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 3304841822 ps |
| CPU time | 111.88 seconds |
| Started | Jul 31 08:00:50 PM PDT 24 |
| Finished | Jul 31 08:02:42 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-9d48f429-a172-439d-ae81-ca783e674ca2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710122406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device .3710122406 |
| Directory | /workspace/72.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.2710678083 |
| Short name | T2243 |
| Test name | |
| Test status | |
| Simulation time | 62257216586 ps |
| CPU time | 1124.64 seconds |
| Started | Jul 31 08:00:46 PM PDT 24 |
| Finished | Jul 31 08:19:31 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-2972de41-420a-420c-9a17-5e3e87f3bdf5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710678083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_ device_slow_rsp.2710678083 |
| Directory | /workspace/72.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.1774303174 |
| Short name | T2523 |
| Test name | |
| Test status | |
| Simulation time | 21209166 ps |
| CPU time | 5.3 seconds |
| Started | Jul 31 08:00:47 PM PDT 24 |
| Finished | Jul 31 08:00:52 PM PDT 24 |
| Peak memory | 573860 kb |
| Host | smart-c7d42c51-dc59-42ca-9e00-7466d9f833bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774303174 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_and_unmapped_add r.1774303174 |
| Directory | /workspace/72.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_random.842079155 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 491488107 ps |
| CPU time | 40.48 seconds |
| Started | Jul 31 08:00:47 PM PDT 24 |
| Finished | Jul 31 08:01:28 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-a13e9bcb-c6b5-439b-90a8-f92ab0812638 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842079155 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_random.842079155 |
| Directory | /workspace/72.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random.3181871318 |
| Short name | T2497 |
| Test name | |
| Test status | |
| Simulation time | 223163994 ps |
| CPU time | 19.68 seconds |
| Started | Jul 31 08:00:45 PM PDT 24 |
| Finished | Jul 31 08:01:05 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-d1756a46-baf3-456a-89e5-0ddfab6c8d3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181871318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random.3181871318 |
| Directory | /workspace/72.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_large_delays.2022664232 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 39814204000 ps |
| CPU time | 428.33 seconds |
| Started | Jul 31 08:00:48 PM PDT 24 |
| Finished | Jul 31 08:07:56 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-7591cfc4-eb61-4939-9484-90b23693a8f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022664232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_large_delays.2022664232 |
| Directory | /workspace/72.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_slow_rsp.172564168 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 5374266866 ps |
| CPU time | 89.56 seconds |
| Started | Jul 31 08:00:46 PM PDT 24 |
| Finished | Jul 31 08:02:16 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-2f668a44-2455-4029-9f93-2d861ba8da08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172564168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_slow_rsp.172564168 |
| Directory | /workspace/72.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.1594907797 |
| Short name | T2507 |
| Test name | |
| Test status | |
| Simulation time | 74665669 ps |
| CPU time | 9.76 seconds |
| Started | Jul 31 08:00:45 PM PDT 24 |
| Finished | Jul 31 08:00:55 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-477c8527-104c-416d-987f-5bcf9eee791b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594907797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_zero_del ays.1594907797 |
| Directory | /workspace/72.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_same_source.3430039412 |
| Short name | T2637 |
| Test name | |
| Test status | |
| Simulation time | 1532090536 ps |
| CPU time | 43.1 seconds |
| Started | Jul 31 08:00:46 PM PDT 24 |
| Finished | Jul 31 08:01:29 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-af3b4d2e-0692-4391-a887-94f450f54827 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430039412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_same_source.3430039412 |
| Directory | /workspace/72.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke.3812986685 |
| Short name | T1676 |
| Test name | |
| Test status | |
| Simulation time | 237471278 ps |
| CPU time | 9.8 seconds |
| Started | Jul 31 08:00:41 PM PDT 24 |
| Finished | Jul 31 08:00:51 PM PDT 24 |
| Peak memory | 573816 kb |
| Host | smart-72161719-773e-4c04-8168-924f1811ffee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812986685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke.3812986685 |
| Directory | /workspace/72.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.3572187810 |
| Short name | T1479 |
| Test name | |
| Test status | |
| Simulation time | 7041828344 ps |
| CPU time | 70.67 seconds |
| Started | Jul 31 08:00:41 PM PDT 24 |
| Finished | Jul 31 08:01:52 PM PDT 24 |
| Peak memory | 574012 kb |
| Host | smart-ff7466c7-3fc0-42db-8aaf-1b1ca2e76e5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572187810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_large_delays.3572187810 |
| Directory | /workspace/72.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.2666549771 |
| Short name | T1797 |
| Test name | |
| Test status | |
| Simulation time | 4909532642 ps |
| CPU time | 84.27 seconds |
| Started | Jul 31 08:00:40 PM PDT 24 |
| Finished | Jul 31 08:02:05 PM PDT 24 |
| Peak memory | 574616 kb |
| Host | smart-55b58be3-221d-471f-a1fe-b8bfefd3d3ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666549771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_slow_rsp.2666549771 |
| Directory | /workspace/72.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_zero_delays.846736957 |
| Short name | T1439 |
| Test name | |
| Test status | |
| Simulation time | 55522723 ps |
| CPU time | 6.29 seconds |
| Started | Jul 31 08:00:41 PM PDT 24 |
| Finished | Jul 31 08:00:47 PM PDT 24 |
| Peak memory | 573760 kb |
| Host | smart-ed8879b2-ed21-47c0-a6a3-bea4786f380a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846736957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_zero_delays .846736957 |
| Directory | /workspace/72.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all.2549016873 |
| Short name | T2739 |
| Test name | |
| Test status | |
| Simulation time | 800163058 ps |
| CPU time | 28.24 seconds |
| Started | Jul 31 08:00:47 PM PDT 24 |
| Finished | Jul 31 08:01:16 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-af005b96-4f3e-417c-8f21-4e9b67cf7060 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549016873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all.2549016873 |
| Directory | /workspace/72.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_error.1161582051 |
| Short name | T1751 |
| Test name | |
| Test status | |
| Simulation time | 1138559011 ps |
| CPU time | 85.61 seconds |
| Started | Jul 31 08:00:48 PM PDT 24 |
| Finished | Jul 31 08:02:14 PM PDT 24 |
| Peak memory | 576100 kb |
| Host | smart-7b661911-ee95-471a-a9f2-038e01536c76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161582051 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_error.1161582051 |
| Directory | /workspace/72.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.592519024 |
| Short name | T2409 |
| Test name | |
| Test status | |
| Simulation time | 8873075171 ps |
| CPU time | 619.28 seconds |
| Started | Jul 31 08:00:47 PM PDT 24 |
| Finished | Jul 31 08:11:06 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-11223f61-dd65-4eed-8922-8dd13b5ff83d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592519024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_ with_rand_reset.592519024 |
| Directory | /workspace/72.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.3536967768 |
| Short name | T2782 |
| Test name | |
| Test status | |
| Simulation time | 527537207 ps |
| CPU time | 201.1 seconds |
| Started | Jul 31 08:00:59 PM PDT 24 |
| Finished | Jul 31 08:04:20 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-ac218f06-2985-42c6-932f-a3a93d658109 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536967768 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_al l_with_reset_error.3536967768 |
| Directory | /workspace/72.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_unmapped_addr.1006152462 |
| Short name | T2630 |
| Test name | |
| Test status | |
| Simulation time | 29197558 ps |
| CPU time | 5.92 seconds |
| Started | Jul 31 08:00:47 PM PDT 24 |
| Finished | Jul 31 08:00:53 PM PDT 24 |
| Peak memory | 573844 kb |
| Host | smart-f199dad0-a27c-48c4-bee1-48c88ced4d3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006152462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_unmapped_addr.1006152462 |
| Directory | /workspace/72.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device.2456121160 |
| Short name | T2379 |
| Test name | |
| Test status | |
| Simulation time | 838754501 ps |
| CPU time | 74.16 seconds |
| Started | Jul 31 08:00:56 PM PDT 24 |
| Finished | Jul 31 08:02:10 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-c99d6e67-192f-4c3d-aba6-fac53b9b5acf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456121160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device .2456121160 |
| Directory | /workspace/73.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.1881171852 |
| Short name | T2719 |
| Test name | |
| Test status | |
| Simulation time | 92735945047 ps |
| CPU time | 1818.88 seconds |
| Started | Jul 31 08:00:57 PM PDT 24 |
| Finished | Jul 31 08:31:17 PM PDT 24 |
| Peak memory | 576092 kb |
| Host | smart-f0037723-4456-4ddb-b417-901da3263c8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881171852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_ device_slow_rsp.1881171852 |
| Directory | /workspace/73.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.1829700374 |
| Short name | T1612 |
| Test name | |
| Test status | |
| Simulation time | 206264718 ps |
| CPU time | 10.68 seconds |
| Started | Jul 31 08:01:00 PM PDT 24 |
| Finished | Jul 31 08:01:11 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-ab6b879d-a1c3-41ac-beb2-8b89e4eca287 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829700374 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_and_unmapped_add r.1829700374 |
| Directory | /workspace/73.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_random.2145405809 |
| Short name | T1673 |
| Test name | |
| Test status | |
| Simulation time | 255672422 ps |
| CPU time | 22.06 seconds |
| Started | Jul 31 08:00:55 PM PDT 24 |
| Finished | Jul 31 08:01:17 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-7c2142cf-5e56-4a29-adf5-66f0ff14516a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145405809 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_random.2145405809 |
| Directory | /workspace/73.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random.1891607269 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 567615207 ps |
| CPU time | 43.91 seconds |
| Started | Jul 31 08:00:59 PM PDT 24 |
| Finished | Jul 31 08:01:43 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-c0a7fbdf-82df-445f-8e3e-e94b879d64f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891607269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random.1891607269 |
| Directory | /workspace/73.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_large_delays.394959969 |
| Short name | T2045 |
| Test name | |
| Test status | |
| Simulation time | 64055347299 ps |
| CPU time | 647.14 seconds |
| Started | Jul 31 08:00:56 PM PDT 24 |
| Finished | Jul 31 08:11:44 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-8ce03af6-2989-4cd0-83df-a2afb3872a3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394959969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_large_delays.394959969 |
| Directory | /workspace/73.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_slow_rsp.3970773410 |
| Short name | T1753 |
| Test name | |
| Test status | |
| Simulation time | 32917700361 ps |
| CPU time | 572.71 seconds |
| Started | Jul 31 08:00:57 PM PDT 24 |
| Finished | Jul 31 08:10:30 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-f81f544e-e984-4f77-83eb-1c240610fdc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970773410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_slow_rsp.3970773410 |
| Directory | /workspace/73.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_zero_delays.4091307136 |
| Short name | T2263 |
| Test name | |
| Test status | |
| Simulation time | 380127897 ps |
| CPU time | 35.12 seconds |
| Started | Jul 31 08:00:56 PM PDT 24 |
| Finished | Jul 31 08:01:31 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-075339d8-6f02-466a-b3e6-f849403789c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091307136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_zero_del ays.4091307136 |
| Directory | /workspace/73.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_same_source.2986922934 |
| Short name | T2618 |
| Test name | |
| Test status | |
| Simulation time | 267203147 ps |
| CPU time | 20.9 seconds |
| Started | Jul 31 08:00:54 PM PDT 24 |
| Finished | Jul 31 08:01:15 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-0d80c3d4-3413-4055-abc4-2a70fa069301 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986922934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_same_source.2986922934 |
| Directory | /workspace/73.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke.1240455075 |
| Short name | T1418 |
| Test name | |
| Test status | |
| Simulation time | 43365530 ps |
| CPU time | 5.8 seconds |
| Started | Jul 31 08:00:53 PM PDT 24 |
| Finished | Jul 31 08:00:59 PM PDT 24 |
| Peak memory | 573852 kb |
| Host | smart-2876b969-5a06-4b94-9408-375578eeee8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240455075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke.1240455075 |
| Directory | /workspace/73.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.971082003 |
| Short name | T2831 |
| Test name | |
| Test status | |
| Simulation time | 8215528066 ps |
| CPU time | 87.73 seconds |
| Started | Jul 31 08:00:54 PM PDT 24 |
| Finished | Jul 31 08:02:22 PM PDT 24 |
| Peak memory | 573996 kb |
| Host | smart-0f82e8d8-8756-425e-83e6-815387db8ef8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971082003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_large_delays.971082003 |
| Directory | /workspace/73.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.981669803 |
| Short name | T2836 |
| Test name | |
| Test status | |
| Simulation time | 5637479606 ps |
| CPU time | 89.59 seconds |
| Started | Jul 31 08:00:56 PM PDT 24 |
| Finished | Jul 31 08:02:26 PM PDT 24 |
| Peak memory | 573916 kb |
| Host | smart-fb75afd0-0733-42ab-9d92-23dbc8576f6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981669803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_slow_rsp.981669803 |
| Directory | /workspace/73.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_zero_delays.2082460569 |
| Short name | T2311 |
| Test name | |
| Test status | |
| Simulation time | 54951980 ps |
| CPU time | 6.74 seconds |
| Started | Jul 31 08:00:55 PM PDT 24 |
| Finished | Jul 31 08:01:02 PM PDT 24 |
| Peak memory | 573808 kb |
| Host | smart-da3f8376-a7ba-44fd-902c-908356ae3886 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082460569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_zero_delay s.2082460569 |
| Directory | /workspace/73.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all.3118641867 |
| Short name | T2089 |
| Test name | |
| Test status | |
| Simulation time | 10004390267 ps |
| CPU time | 379.61 seconds |
| Started | Jul 31 08:01:00 PM PDT 24 |
| Finished | Jul 31 08:07:20 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-ab47415c-8aca-4c05-9773-424e965551ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118641867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all.3118641867 |
| Directory | /workspace/73.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.2694339795 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 3543484766 ps |
| CPU time | 128.69 seconds |
| Started | Jul 31 08:01:00 PM PDT 24 |
| Finished | Jul 31 08:03:09 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-cfd586ef-02d7-4871-8dc6-c1fc74bdba72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694339795 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_error.2694339795 |
| Directory | /workspace/73.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.1098154040 |
| Short name | T2398 |
| Test name | |
| Test status | |
| Simulation time | 267531198 ps |
| CPU time | 95.65 seconds |
| Started | Jul 31 08:01:01 PM PDT 24 |
| Finished | Jul 31 08:02:37 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-0a1602aa-9350-4bc9-b2e8-5129decdd7b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098154040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all _with_rand_reset.1098154040 |
| Directory | /workspace/73.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.3776399796 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 2924285881 ps |
| CPU time | 326.42 seconds |
| Started | Jul 31 08:01:00 PM PDT 24 |
| Finished | Jul 31 08:06:27 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-fd2bba18-4d34-49c7-a44b-aa3cb2ed2d27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776399796 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_al l_with_reset_error.3776399796 |
| Directory | /workspace/73.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_unmapped_addr.388026922 |
| Short name | T1514 |
| Test name | |
| Test status | |
| Simulation time | 97130338 ps |
| CPU time | 12.77 seconds |
| Started | Jul 31 08:00:54 PM PDT 24 |
| Finished | Jul 31 08:01:07 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-f77b1b2b-05b6-4cd0-a9a3-e2000bbc8bf3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388026922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_unmapped_addr.388026922 |
| Directory | /workspace/73.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device.3476099999 |
| Short name | T2461 |
| Test name | |
| Test status | |
| Simulation time | 865539261 ps |
| CPU time | 61.3 seconds |
| Started | Jul 31 08:01:10 PM PDT 24 |
| Finished | Jul 31 08:02:11 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-f91f71aa-8d16-4b2e-9ef0-0363e5c5fa5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476099999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device .3476099999 |
| Directory | /workspace/74.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.285005699 |
| Short name | T1981 |
| Test name | |
| Test status | |
| Simulation time | 53714006032 ps |
| CPU time | 966.21 seconds |
| Started | Jul 31 08:01:12 PM PDT 24 |
| Finished | Jul 31 08:17:18 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-6fc18af8-9ffa-4386-92a0-1a92b9e4fc0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285005699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_d evice_slow_rsp.285005699 |
| Directory | /workspace/74.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.338557869 |
| Short name | T2522 |
| Test name | |
| Test status | |
| Simulation time | 289215870 ps |
| CPU time | 31.19 seconds |
| Started | Jul 31 08:01:14 PM PDT 24 |
| Finished | Jul 31 08:01:45 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-05ec2fba-edde-4636-a20b-b74c3110cd2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338557869 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_and_unmapped_addr .338557869 |
| Directory | /workspace/74.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_random.4063878955 |
| Short name | T2818 |
| Test name | |
| Test status | |
| Simulation time | 246100432 ps |
| CPU time | 11.06 seconds |
| Started | Jul 31 08:01:13 PM PDT 24 |
| Finished | Jul 31 08:01:24 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-d7810ef9-92cd-4a84-af31-fdd664871326 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063878955 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_random.4063878955 |
| Directory | /workspace/74.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random.1495130891 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 624079020 ps |
| CPU time | 52.47 seconds |
| Started | Jul 31 08:01:01 PM PDT 24 |
| Finished | Jul 31 08:01:53 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-d78bc12f-c9d3-4309-98f8-e25031699455 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495130891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random.1495130891 |
| Directory | /workspace/74.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_large_delays.2919608691 |
| Short name | T1736 |
| Test name | |
| Test status | |
| Simulation time | 26163523813 ps |
| CPU time | 276.54 seconds |
| Started | Jul 31 08:01:08 PM PDT 24 |
| Finished | Jul 31 08:05:45 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-78269665-e8d3-4dc9-8dbf-b9915f04eef7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919608691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_large_delays.2919608691 |
| Directory | /workspace/74.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_slow_rsp.384974474 |
| Short name | T2636 |
| Test name | |
| Test status | |
| Simulation time | 34258980410 ps |
| CPU time | 630.02 seconds |
| Started | Jul 31 08:01:06 PM PDT 24 |
| Finished | Jul 31 08:11:37 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-f54477f3-33a9-449e-a672-729744dd62c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384974474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_slow_rsp.384974474 |
| Directory | /workspace/74.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_zero_delays.1805420449 |
| Short name | T2570 |
| Test name | |
| Test status | |
| Simulation time | 438492191 ps |
| CPU time | 40.04 seconds |
| Started | Jul 31 08:01:01 PM PDT 24 |
| Finished | Jul 31 08:01:41 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-1bfe6b29-4f0c-45d5-a77b-66480998def6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805420449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_zero_del ays.1805420449 |
| Directory | /workspace/74.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_same_source.3356038325 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 391931069 ps |
| CPU time | 12.5 seconds |
| Started | Jul 31 08:01:12 PM PDT 24 |
| Finished | Jul 31 08:01:25 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-f8df9565-abf3-4ec0-98c7-da9bfe2a199d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356038325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_same_source.3356038325 |
| Directory | /workspace/74.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke.1007014648 |
| Short name | T1917 |
| Test name | |
| Test status | |
| Simulation time | 45673498 ps |
| CPU time | 6.23 seconds |
| Started | Jul 31 08:01:01 PM PDT 24 |
| Finished | Jul 31 08:01:07 PM PDT 24 |
| Peak memory | 573792 kb |
| Host | smart-a4aa1eab-0a00-4340-999d-49dbd1be68a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007014648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke.1007014648 |
| Directory | /workspace/74.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_large_delays.1491777797 |
| Short name | T1667 |
| Test name | |
| Test status | |
| Simulation time | 6405040458 ps |
| CPU time | 64.34 seconds |
| Started | Jul 31 08:01:00 PM PDT 24 |
| Finished | Jul 31 08:02:05 PM PDT 24 |
| Peak memory | 574552 kb |
| Host | smart-8c2809cb-60f1-41d4-81c8-78dee1954fe4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491777797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_large_delays.1491777797 |
| Directory | /workspace/74.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.3245130345 |
| Short name | T1881 |
| Test name | |
| Test status | |
| Simulation time | 4103178684 ps |
| CPU time | 65.28 seconds |
| Started | Jul 31 08:01:01 PM PDT 24 |
| Finished | Jul 31 08:02:06 PM PDT 24 |
| Peak memory | 573924 kb |
| Host | smart-972269da-e0ac-438c-9d50-c09e2fcdc2ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245130345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_slow_rsp.3245130345 |
| Directory | /workspace/74.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_zero_delays.460437155 |
| Short name | T1460 |
| Test name | |
| Test status | |
| Simulation time | 54063007 ps |
| CPU time | 6.92 seconds |
| Started | Jul 31 08:01:01 PM PDT 24 |
| Finished | Jul 31 08:01:08 PM PDT 24 |
| Peak memory | 573748 kb |
| Host | smart-5fc8b61d-f73a-410d-b798-5393d7a722b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460437155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_zero_delays .460437155 |
| Directory | /workspace/74.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all.399262336 |
| Short name | T1921 |
| Test name | |
| Test status | |
| Simulation time | 5234210019 ps |
| CPU time | 180.04 seconds |
| Started | Jul 31 08:01:13 PM PDT 24 |
| Finished | Jul 31 08:04:13 PM PDT 24 |
| Peak memory | 576144 kb |
| Host | smart-fa735f14-533c-4f27-8269-9bed14f814e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399262336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all.399262336 |
| Directory | /workspace/74.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.4244273206 |
| Short name | T2835 |
| Test name | |
| Test status | |
| Simulation time | 21101042866 ps |
| CPU time | 731.09 seconds |
| Started | Jul 31 08:01:11 PM PDT 24 |
| Finished | Jul 31 08:13:23 PM PDT 24 |
| Peak memory | 576820 kb |
| Host | smart-5cb8ae0f-684c-482a-a908-12d79f0fc36f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244273206 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_error.4244273206 |
| Directory | /workspace/74.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.1127866424 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 6019918278 ps |
| CPU time | 691.29 seconds |
| Started | Jul 31 08:01:12 PM PDT 24 |
| Finished | Jul 31 08:12:44 PM PDT 24 |
| Peak memory | 576760 kb |
| Host | smart-fb745c1a-515b-404e-9b77-3e703e0a076d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127866424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all _with_rand_reset.1127866424 |
| Directory | /workspace/74.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.1370128135 |
| Short name | T1634 |
| Test name | |
| Test status | |
| Simulation time | 396206884 ps |
| CPU time | 82.18 seconds |
| Started | Jul 31 08:01:11 PM PDT 24 |
| Finished | Jul 31 08:02:34 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-865d71a1-e1fa-49d5-bdd9-1a3750d67fca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370128135 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_al l_with_reset_error.1370128135 |
| Directory | /workspace/74.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_unmapped_addr.1800804081 |
| Short name | T2151 |
| Test name | |
| Test status | |
| Simulation time | 887243470 ps |
| CPU time | 41.14 seconds |
| Started | Jul 31 08:01:12 PM PDT 24 |
| Finished | Jul 31 08:01:53 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-3c37198e-0693-4208-8bb3-313e4aee2edc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800804081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_unmapped_addr.1800804081 |
| Directory | /workspace/74.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device.1749669442 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 2625730574 ps |
| CPU time | 106.42 seconds |
| Started | Jul 31 08:01:16 PM PDT 24 |
| Finished | Jul 31 08:03:03 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-98d4aa78-658a-4576-8a1c-638c1eb3574d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749669442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device .1749669442 |
| Directory | /workspace/75.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.3708255161 |
| Short name | T2863 |
| Test name | |
| Test status | |
| Simulation time | 78515748868 ps |
| CPU time | 1496.36 seconds |
| Started | Jul 31 08:01:16 PM PDT 24 |
| Finished | Jul 31 08:26:12 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-f6894836-dddf-4d7c-ba99-8f07bde12900 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708255161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_ device_slow_rsp.3708255161 |
| Directory | /workspace/75.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.335819524 |
| Short name | T1393 |
| Test name | |
| Test status | |
| Simulation time | 22255570 ps |
| CPU time | 5.22 seconds |
| Started | Jul 31 08:01:13 PM PDT 24 |
| Finished | Jul 31 08:01:18 PM PDT 24 |
| Peak memory | 573800 kb |
| Host | smart-25df7cc6-54db-4526-a9cc-67a6697b956d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335819524 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_and_unmapped_addr .335819524 |
| Directory | /workspace/75.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_random.2356797170 |
| Short name | T1409 |
| Test name | |
| Test status | |
| Simulation time | 420997843 ps |
| CPU time | 33.27 seconds |
| Started | Jul 31 08:01:17 PM PDT 24 |
| Finished | Jul 31 08:01:51 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-ada10516-3b7f-4c9b-aef0-091fd327628c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356797170 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_random.2356797170 |
| Directory | /workspace/75.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random.101981394 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 609211750 ps |
| CPU time | 24.53 seconds |
| Started | Jul 31 08:01:11 PM PDT 24 |
| Finished | Jul 31 08:01:36 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-862e0faf-ce30-4a16-a731-f3c91bff98ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101981394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random.101981394 |
| Directory | /workspace/75.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.2553688455 |
| Short name | T1904 |
| Test name | |
| Test status | |
| Simulation time | 82217939993 ps |
| CPU time | 929.65 seconds |
| Started | Jul 31 08:01:11 PM PDT 24 |
| Finished | Jul 31 08:16:41 PM PDT 24 |
| Peak memory | 576056 kb |
| Host | smart-e635fe35-fd24-4102-9f04-f6a5a0cb80fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553688455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_large_delays.2553688455 |
| Directory | /workspace/75.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.3581038290 |
| Short name | T2532 |
| Test name | |
| Test status | |
| Simulation time | 23343715329 ps |
| CPU time | 393.1 seconds |
| Started | Jul 31 08:01:15 PM PDT 24 |
| Finished | Jul 31 08:07:48 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-08c9ec74-dc63-48a9-856d-25581d772f73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581038290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_slow_rsp.3581038290 |
| Directory | /workspace/75.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_zero_delays.3081044641 |
| Short name | T2288 |
| Test name | |
| Test status | |
| Simulation time | 320890975 ps |
| CPU time | 27.56 seconds |
| Started | Jul 31 08:01:12 PM PDT 24 |
| Finished | Jul 31 08:01:40 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-ef88c8fa-f2f9-4440-a19e-2e3fb4339900 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081044641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_zero_del ays.3081044641 |
| Directory | /workspace/75.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_same_source.3081789461 |
| Short name | T2230 |
| Test name | |
| Test status | |
| Simulation time | 2136946677 ps |
| CPU time | 65.04 seconds |
| Started | Jul 31 08:01:12 PM PDT 24 |
| Finished | Jul 31 08:02:17 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-49f9a8c4-eb86-40fd-9a08-1270ec7c16e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081789461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_same_source.3081789461 |
| Directory | /workspace/75.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke.3671163473 |
| Short name | T1795 |
| Test name | |
| Test status | |
| Simulation time | 231252414 ps |
| CPU time | 9.39 seconds |
| Started | Jul 31 08:01:14 PM PDT 24 |
| Finished | Jul 31 08:01:23 PM PDT 24 |
| Peak memory | 573752 kb |
| Host | smart-e22e97c0-edc7-4c5a-a340-6ed9bfb949db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671163473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke.3671163473 |
| Directory | /workspace/75.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.2293329471 |
| Short name | T2176 |
| Test name | |
| Test status | |
| Simulation time | 9509009616 ps |
| CPU time | 101.32 seconds |
| Started | Jul 31 08:01:13 PM PDT 24 |
| Finished | Jul 31 08:02:54 PM PDT 24 |
| Peak memory | 573936 kb |
| Host | smart-ca40d48a-3954-4be4-926c-e7ccfec0c07b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293329471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_large_delays.2293329471 |
| Directory | /workspace/75.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.1497710168 |
| Short name | T1866 |
| Test name | |
| Test status | |
| Simulation time | 6107130317 ps |
| CPU time | 101.93 seconds |
| Started | Jul 31 08:01:13 PM PDT 24 |
| Finished | Jul 31 08:02:55 PM PDT 24 |
| Peak memory | 573756 kb |
| Host | smart-83915305-6b7b-4c43-8853-5e131c980f60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497710168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_slow_rsp.1497710168 |
| Directory | /workspace/75.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_zero_delays.4102557424 |
| Short name | T1523 |
| Test name | |
| Test status | |
| Simulation time | 43710227 ps |
| CPU time | 6.28 seconds |
| Started | Jul 31 08:01:11 PM PDT 24 |
| Finished | Jul 31 08:01:18 PM PDT 24 |
| Peak memory | 573824 kb |
| Host | smart-ddb0320f-adae-4a81-9e2c-c706f1e0c8fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102557424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_zero_delay s.4102557424 |
| Directory | /workspace/75.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all.2004881690 |
| Short name | T1722 |
| Test name | |
| Test status | |
| Simulation time | 3304045834 ps |
| CPU time | 99.66 seconds |
| Started | Jul 31 08:01:13 PM PDT 24 |
| Finished | Jul 31 08:02:53 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-31fdbe4f-0e62-4028-a1aa-fcd55ab8f66d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004881690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all.2004881690 |
| Directory | /workspace/75.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.1564950390 |
| Short name | T2805 |
| Test name | |
| Test status | |
| Simulation time | 9281261642 ps |
| CPU time | 300.95 seconds |
| Started | Jul 31 08:01:20 PM PDT 24 |
| Finished | Jul 31 08:06:21 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-99ea5214-9c3e-4b5b-806c-d97ee005fe81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564950390 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_error.1564950390 |
| Directory | /workspace/75.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.2591887973 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 102011625 ps |
| CPU time | 21.9 seconds |
| Started | Jul 31 08:01:20 PM PDT 24 |
| Finished | Jul 31 08:01:42 PM PDT 24 |
| Peak memory | 576144 kb |
| Host | smart-dffedf8e-4600-429d-aa00-cf7d9d41872c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591887973 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_al l_with_reset_error.2591887973 |
| Directory | /workspace/75.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.3407470777 |
| Short name | T2792 |
| Test name | |
| Test status | |
| Simulation time | 79275247 ps |
| CPU time | 11.08 seconds |
| Started | Jul 31 08:01:17 PM PDT 24 |
| Finished | Jul 31 08:01:29 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-0aceed08-dbb0-4862-ab55-ad1ef8b3c610 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407470777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_unmapped_addr.3407470777 |
| Directory | /workspace/75.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device.1897181181 |
| Short name | T1727 |
| Test name | |
| Test status | |
| Simulation time | 1708670160 ps |
| CPU time | 68.69 seconds |
| Started | Jul 31 08:01:25 PM PDT 24 |
| Finished | Jul 31 08:02:34 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-16273150-907b-480a-aa06-5bb0e4ce2e72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897181181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device .1897181181 |
| Directory | /workspace/76.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.2955104787 |
| Short name | T2286 |
| Test name | |
| Test status | |
| Simulation time | 11560952531 ps |
| CPU time | 186.21 seconds |
| Started | Jul 31 08:01:24 PM PDT 24 |
| Finished | Jul 31 08:04:30 PM PDT 24 |
| Peak memory | 573844 kb |
| Host | smart-de58b251-5eb7-441a-97a4-2e24bf9f66bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955104787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_ device_slow_rsp.2955104787 |
| Directory | /workspace/76.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.1915716728 |
| Short name | T2515 |
| Test name | |
| Test status | |
| Simulation time | 41792603 ps |
| CPU time | 6.63 seconds |
| Started | Jul 31 08:01:26 PM PDT 24 |
| Finished | Jul 31 08:01:33 PM PDT 24 |
| Peak memory | 573920 kb |
| Host | smart-715bc2fc-9d86-4a9b-af75-6d4aacae6afe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915716728 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_and_unmapped_add r.1915716728 |
| Directory | /workspace/76.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_random.4078987975 |
| Short name | T1842 |
| Test name | |
| Test status | |
| Simulation time | 350699086 ps |
| CPU time | 13.84 seconds |
| Started | Jul 31 08:01:25 PM PDT 24 |
| Finished | Jul 31 08:01:39 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-0962ac91-30ec-4019-8b80-ad34df766b63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078987975 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_random.4078987975 |
| Directory | /workspace/76.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random.308359093 |
| Short name | T2747 |
| Test name | |
| Test status | |
| Simulation time | 1844904908 ps |
| CPU time | 70.71 seconds |
| Started | Jul 31 08:01:26 PM PDT 24 |
| Finished | Jul 31 08:02:37 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-af93d220-f3a1-4b7d-aee7-ddb856fab0c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308359093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random.308359093 |
| Directory | /workspace/76.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_large_delays.3001614124 |
| Short name | T2210 |
| Test name | |
| Test status | |
| Simulation time | 59673319651 ps |
| CPU time | 612.64 seconds |
| Started | Jul 31 08:01:24 PM PDT 24 |
| Finished | Jul 31 08:11:37 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-ef50aea2-260a-4ecb-8096-f943df3d3e4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001614124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_large_delays.3001614124 |
| Directory | /workspace/76.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_slow_rsp.2791732944 |
| Short name | T2251 |
| Test name | |
| Test status | |
| Simulation time | 57868806107 ps |
| CPU time | 1071.35 seconds |
| Started | Jul 31 08:01:27 PM PDT 24 |
| Finished | Jul 31 08:19:18 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-f0940a38-fa71-4411-81b1-7b133fa331bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791732944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_slow_rsp.2791732944 |
| Directory | /workspace/76.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.663829799 |
| Short name | T2784 |
| Test name | |
| Test status | |
| Simulation time | 245448197 ps |
| CPU time | 20.61 seconds |
| Started | Jul 31 08:01:26 PM PDT 24 |
| Finished | Jul 31 08:01:47 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-b61e5c80-05ce-4457-9e68-5a3027787226 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663829799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_zero_dela ys.663829799 |
| Directory | /workspace/76.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_same_source.299708040 |
| Short name | T2226 |
| Test name | |
| Test status | |
| Simulation time | 1945285473 ps |
| CPU time | 54.45 seconds |
| Started | Jul 31 08:01:28 PM PDT 24 |
| Finished | Jul 31 08:02:22 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-7e2c08b9-bf81-4a3b-ae51-4f9d7935ce06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299708040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_same_source.299708040 |
| Directory | /workspace/76.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke.415929042 |
| Short name | T1386 |
| Test name | |
| Test status | |
| Simulation time | 53399561 ps |
| CPU time | 6.36 seconds |
| Started | Jul 31 08:01:20 PM PDT 24 |
| Finished | Jul 31 08:01:26 PM PDT 24 |
| Peak memory | 573824 kb |
| Host | smart-7bc22ca5-aba3-4b68-8fab-0990176123fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415929042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke.415929042 |
| Directory | /workspace/76.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_large_delays.564749530 |
| Short name | T1522 |
| Test name | |
| Test status | |
| Simulation time | 7741385067 ps |
| CPU time | 77.49 seconds |
| Started | Jul 31 08:01:20 PM PDT 24 |
| Finished | Jul 31 08:02:38 PM PDT 24 |
| Peak memory | 573904 kb |
| Host | smart-79768379-99bd-4c0d-852f-ad67f62735b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564749530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_large_delays.564749530 |
| Directory | /workspace/76.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.1609801113 |
| Short name | T1869 |
| Test name | |
| Test status | |
| Simulation time | 3923086625 ps |
| CPU time | 66.25 seconds |
| Started | Jul 31 08:01:19 PM PDT 24 |
| Finished | Jul 31 08:02:25 PM PDT 24 |
| Peak memory | 574000 kb |
| Host | smart-b24a6c5a-38f5-4bb1-ba66-8ebff42e5c89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609801113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_slow_rsp.1609801113 |
| Directory | /workspace/76.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_zero_delays.338145833 |
| Short name | T2883 |
| Test name | |
| Test status | |
| Simulation time | 46675423 ps |
| CPU time | 6.03 seconds |
| Started | Jul 31 08:01:20 PM PDT 24 |
| Finished | Jul 31 08:01:26 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-336f4198-c1d9-4db9-ad1e-c8739f430e51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338145833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_zero_delays .338145833 |
| Directory | /workspace/76.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all.3651545404 |
| Short name | T1856 |
| Test name | |
| Test status | |
| Simulation time | 2523601954 ps |
| CPU time | 218.81 seconds |
| Started | Jul 31 08:01:25 PM PDT 24 |
| Finished | Jul 31 08:05:04 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-b782bca3-6e03-4b6f-a5e3-cf2f5fe17c3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651545404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all.3651545404 |
| Directory | /workspace/76.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.1660416534 |
| Short name | T2477 |
| Test name | |
| Test status | |
| Simulation time | 1934868994 ps |
| CPU time | 160.93 seconds |
| Started | Jul 31 08:01:31 PM PDT 24 |
| Finished | Jul 31 08:04:12 PM PDT 24 |
| Peak memory | 576100 kb |
| Host | smart-6c327332-c7cd-4e2a-97cd-441fa6d6c694 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660416534 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_error.1660416534 |
| Directory | /workspace/76.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.1560060572 |
| Short name | T2385 |
| Test name | |
| Test status | |
| Simulation time | 29721169 ps |
| CPU time | 22.65 seconds |
| Started | Jul 31 08:01:26 PM PDT 24 |
| Finished | Jul 31 08:01:48 PM PDT 24 |
| Peak memory | 574628 kb |
| Host | smart-e9da608c-6db2-4b2d-95f4-c5c2a19e57b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560060572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all _with_rand_reset.1560060572 |
| Directory | /workspace/76.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.1793747695 |
| Short name | T2760 |
| Test name | |
| Test status | |
| Simulation time | 483026550 ps |
| CPU time | 184.48 seconds |
| Started | Jul 31 08:01:32 PM PDT 24 |
| Finished | Jul 31 08:04:37 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-e6851a1c-3597-4c77-a4d7-15cbd011573f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793747695 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_al l_with_reset_error.1793747695 |
| Directory | /workspace/76.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_unmapped_addr.2533474621 |
| Short name | T2005 |
| Test name | |
| Test status | |
| Simulation time | 696104957 ps |
| CPU time | 29.45 seconds |
| Started | Jul 31 08:01:25 PM PDT 24 |
| Finished | Jul 31 08:01:54 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-cb228197-ecaf-4def-aeab-9be55c788f06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533474621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_unmapped_addr.2533474621 |
| Directory | /workspace/76.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device.2404501620 |
| Short name | T2421 |
| Test name | |
| Test status | |
| Simulation time | 232250106 ps |
| CPU time | 28.68 seconds |
| Started | Jul 31 08:01:38 PM PDT 24 |
| Finished | Jul 31 08:02:07 PM PDT 24 |
| Peak memory | 576068 kb |
| Host | smart-bfaf9d33-12b3-4d23-b189-3f1c7f24f037 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404501620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device .2404501620 |
| Directory | /workspace/77.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.4251952659 |
| Short name | T2830 |
| Test name | |
| Test status | |
| Simulation time | 49554209997 ps |
| CPU time | 937.89 seconds |
| Started | Jul 31 08:01:42 PM PDT 24 |
| Finished | Jul 31 08:17:20 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-b0cf66e7-5747-42e4-863c-828137b2783e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251952659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_ device_slow_rsp.4251952659 |
| Directory | /workspace/77.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.1523393287 |
| Short name | T1471 |
| Test name | |
| Test status | |
| Simulation time | 693197967 ps |
| CPU time | 27.03 seconds |
| Started | Jul 31 08:01:39 PM PDT 24 |
| Finished | Jul 31 08:02:06 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-71fcd33a-f21a-49f0-bfe9-7c550133804f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523393287 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_and_unmapped_add r.1523393287 |
| Directory | /workspace/77.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_random.1807821778 |
| Short name | T2057 |
| Test name | |
| Test status | |
| Simulation time | 774246700 ps |
| CPU time | 27.22 seconds |
| Started | Jul 31 08:01:37 PM PDT 24 |
| Finished | Jul 31 08:02:04 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-42b3a3e4-52fb-4f7f-946b-6db0edc60ae5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807821778 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_random.1807821778 |
| Directory | /workspace/77.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random.2895509215 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 1005188010 ps |
| CPU time | 33.57 seconds |
| Started | Jul 31 08:01:39 PM PDT 24 |
| Finished | Jul 31 08:02:13 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-80f4004a-e8fb-4863-8dea-4792debe045a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895509215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random.2895509215 |
| Directory | /workspace/77.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_large_delays.1511049218 |
| Short name | T2095 |
| Test name | |
| Test status | |
| Simulation time | 11653528291 ps |
| CPU time | 116.43 seconds |
| Started | Jul 31 08:01:38 PM PDT 24 |
| Finished | Jul 31 08:03:34 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-9a5c6a2a-f152-4a8a-a77c-dbe6dea82017 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511049218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_large_delays.1511049218 |
| Directory | /workspace/77.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_slow_rsp.658996444 |
| Short name | T1512 |
| Test name | |
| Test status | |
| Simulation time | 8196762110 ps |
| CPU time | 140.31 seconds |
| Started | Jul 31 08:01:40 PM PDT 24 |
| Finished | Jul 31 08:04:01 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-d080de91-baae-48bf-b077-be99cb7502dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658996444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_slow_rsp.658996444 |
| Directory | /workspace/77.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.3373123496 |
| Short name | T2535 |
| Test name | |
| Test status | |
| Simulation time | 230803882 ps |
| CPU time | 22.94 seconds |
| Started | Jul 31 08:01:37 PM PDT 24 |
| Finished | Jul 31 08:02:00 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-420719b2-fb48-48b3-aeee-8fc583406bab |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373123496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_zero_del ays.3373123496 |
| Directory | /workspace/77.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_same_source.308611507 |
| Short name | T1539 |
| Test name | |
| Test status | |
| Simulation time | 146773641 ps |
| CPU time | 12.77 seconds |
| Started | Jul 31 08:01:36 PM PDT 24 |
| Finished | Jul 31 08:01:49 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-891044f9-5cda-4a4f-8489-ffad3e17a75a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308611507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_same_source.308611507 |
| Directory | /workspace/77.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke.479042676 |
| Short name | T2753 |
| Test name | |
| Test status | |
| Simulation time | 50785841 ps |
| CPU time | 5.88 seconds |
| Started | Jul 31 08:01:30 PM PDT 24 |
| Finished | Jul 31 08:01:36 PM PDT 24 |
| Peak memory | 573776 kb |
| Host | smart-38835a13-c669-461f-994f-b4484d99e3df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479042676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke.479042676 |
| Directory | /workspace/77.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_large_delays.3645555925 |
| Short name | T2356 |
| Test name | |
| Test status | |
| Simulation time | 10443859114 ps |
| CPU time | 112.75 seconds |
| Started | Jul 31 08:01:32 PM PDT 24 |
| Finished | Jul 31 08:03:25 PM PDT 24 |
| Peak memory | 573884 kb |
| Host | smart-9b9df04e-fa1d-4bb7-8aca-275404d68c79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645555925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_large_delays.3645555925 |
| Directory | /workspace/77.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.3944702229 |
| Short name | T1411 |
| Test name | |
| Test status | |
| Simulation time | 5978309503 ps |
| CPU time | 98.83 seconds |
| Started | Jul 31 08:01:37 PM PDT 24 |
| Finished | Jul 31 08:03:16 PM PDT 24 |
| Peak memory | 573896 kb |
| Host | smart-91230d92-1cf7-4a66-9c55-5878e11bfc34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944702229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_slow_rsp.3944702229 |
| Directory | /workspace/77.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_zero_delays.386385945 |
| Short name | T1510 |
| Test name | |
| Test status | |
| Simulation time | 42906748 ps |
| CPU time | 6.04 seconds |
| Started | Jul 31 08:01:33 PM PDT 24 |
| Finished | Jul 31 08:01:39 PM PDT 24 |
| Peak memory | 573824 kb |
| Host | smart-a53cb212-297d-4fbf-9110-53e3efa8613d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386385945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_zero_delays .386385945 |
| Directory | /workspace/77.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all.633722238 |
| Short name | T1714 |
| Test name | |
| Test status | |
| Simulation time | 7316673286 ps |
| CPU time | 269.53 seconds |
| Started | Jul 31 08:01:40 PM PDT 24 |
| Finished | Jul 31 08:06:09 PM PDT 24 |
| Peak memory | 576716 kb |
| Host | smart-32cc53f2-bf0e-45f0-9582-3d241be97801 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633722238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all.633722238 |
| Directory | /workspace/77.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.549672079 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 2662921323 ps |
| CPU time | 305.82 seconds |
| Started | Jul 31 08:01:38 PM PDT 24 |
| Finished | Jul 31 08:06:44 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-122e2201-f1a9-475d-87f2-7a043047a4ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549672079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_ with_rand_reset.549672079 |
| Directory | /workspace/77.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.4087330978 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 5711087271 ps |
| CPU time | 551.34 seconds |
| Started | Jul 31 08:01:40 PM PDT 24 |
| Finished | Jul 31 08:10:51 PM PDT 24 |
| Peak memory | 578580 kb |
| Host | smart-90b89269-411d-43c7-a607-f56600b6f8f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087330978 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_al l_with_reset_error.4087330978 |
| Directory | /workspace/77.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.3389944989 |
| Short name | T1911 |
| Test name | |
| Test status | |
| Simulation time | 107842568 ps |
| CPU time | 12.97 seconds |
| Started | Jul 31 08:01:38 PM PDT 24 |
| Finished | Jul 31 08:01:51 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-b673eda8-caf6-46ec-b918-e6ad1263a7d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389944989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_unmapped_addr.3389944989 |
| Directory | /workspace/77.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device.896710335 |
| Short name | T2154 |
| Test name | |
| Test status | |
| Simulation time | 1288630617 ps |
| CPU time | 48.4 seconds |
| Started | Jul 31 08:01:49 PM PDT 24 |
| Finished | Jul 31 08:02:37 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-1cd9f5d7-46ad-4488-aa70-140d6c088562 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896710335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device. 896710335 |
| Directory | /workspace/78.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.372347552 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 80638958836 ps |
| CPU time | 1479.11 seconds |
| Started | Jul 31 08:01:46 PM PDT 24 |
| Finished | Jul 31 08:26:26 PM PDT 24 |
| Peak memory | 576056 kb |
| Host | smart-367ba7cf-e82b-4250-8247-714399ee3f9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372347552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_d evice_slow_rsp.372347552 |
| Directory | /workspace/78.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.3563009412 |
| Short name | T2552 |
| Test name | |
| Test status | |
| Simulation time | 1199806130 ps |
| CPU time | 43.36 seconds |
| Started | Jul 31 08:01:51 PM PDT 24 |
| Finished | Jul 31 08:02:34 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-8ac83b5d-39f6-46e2-ad95-fdb4ee34c744 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563009412 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_and_unmapped_add r.3563009412 |
| Directory | /workspace/78.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_random.2453213521 |
| Short name | T2834 |
| Test name | |
| Test status | |
| Simulation time | 514091318 ps |
| CPU time | 44.09 seconds |
| Started | Jul 31 08:01:45 PM PDT 24 |
| Finished | Jul 31 08:02:29 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-806c1c88-1f03-4776-b10d-547aa4518101 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453213521 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_random.2453213521 |
| Directory | /workspace/78.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random.4156518115 |
| Short name | T2557 |
| Test name | |
| Test status | |
| Simulation time | 498296647 ps |
| CPU time | 47.94 seconds |
| Started | Jul 31 08:01:44 PM PDT 24 |
| Finished | Jul 31 08:02:32 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-60b84428-1e67-49e0-881a-7a476795aaef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156518115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random.4156518115 |
| Directory | /workspace/78.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_slow_rsp.2005491839 |
| Short name | T1662 |
| Test name | |
| Test status | |
| Simulation time | 38112126868 ps |
| CPU time | 624.73 seconds |
| Started | Jul 31 08:01:44 PM PDT 24 |
| Finished | Jul 31 08:12:09 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-98a88fed-625a-4c43-ba3c-152b40e8dae7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005491839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_slow_rsp.2005491839 |
| Directory | /workspace/78.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.737955854 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 500550172 ps |
| CPU time | 45.7 seconds |
| Started | Jul 31 08:01:46 PM PDT 24 |
| Finished | Jul 31 08:02:32 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-cff1e0a2-6c21-4d21-ad60-0f3cf1710448 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737955854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_zero_dela ys.737955854 |
| Directory | /workspace/78.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_same_source.683583831 |
| Short name | T1897 |
| Test name | |
| Test status | |
| Simulation time | 761515811 ps |
| CPU time | 24.47 seconds |
| Started | Jul 31 08:01:46 PM PDT 24 |
| Finished | Jul 31 08:02:10 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-5d8adac8-eb12-4819-a776-f1a0be9567a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683583831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_same_source.683583831 |
| Directory | /workspace/78.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke.3508673881 |
| Short name | T2370 |
| Test name | |
| Test status | |
| Simulation time | 226975785 ps |
| CPU time | 9.64 seconds |
| Started | Jul 31 08:01:38 PM PDT 24 |
| Finished | Jul 31 08:01:48 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-ba6bc16c-1caa-4cbf-b40e-1b133ff0d9d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508673881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke.3508673881 |
| Directory | /workspace/78.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_large_delays.2252249063 |
| Short name | T1628 |
| Test name | |
| Test status | |
| Simulation time | 9757170523 ps |
| CPU time | 97.63 seconds |
| Started | Jul 31 08:01:47 PM PDT 24 |
| Finished | Jul 31 08:03:25 PM PDT 24 |
| Peak memory | 573892 kb |
| Host | smart-620f0695-2c65-45e2-acfe-cf555c72035b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252249063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_large_delays.2252249063 |
| Directory | /workspace/78.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.789773883 |
| Short name | T1843 |
| Test name | |
| Test status | |
| Simulation time | 4079760297 ps |
| CPU time | 67.65 seconds |
| Started | Jul 31 08:01:44 PM PDT 24 |
| Finished | Jul 31 08:02:51 PM PDT 24 |
| Peak memory | 573916 kb |
| Host | smart-9b870df2-bdc4-4303-98f6-0582e7275729 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789773883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_slow_rsp.789773883 |
| Directory | /workspace/78.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_zero_delays.2168711213 |
| Short name | T2786 |
| Test name | |
| Test status | |
| Simulation time | 44291907 ps |
| CPU time | 6.31 seconds |
| Started | Jul 31 08:01:45 PM PDT 24 |
| Finished | Jul 31 08:01:51 PM PDT 24 |
| Peak memory | 573780 kb |
| Host | smart-c02b3d7e-4f66-4e8c-84fb-e8852225cc32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168711213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_zero_delay s.2168711213 |
| Directory | /workspace/78.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all.2058593022 |
| Short name | T1630 |
| Test name | |
| Test status | |
| Simulation time | 883492672 ps |
| CPU time | 68.84 seconds |
| Started | Jul 31 08:01:51 PM PDT 24 |
| Finished | Jul 31 08:03:00 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-0ec3d1e0-f910-4286-9e90-5a1186d81129 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058593022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all.2058593022 |
| Directory | /workspace/78.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.1903827830 |
| Short name | T2840 |
| Test name | |
| Test status | |
| Simulation time | 330072910 ps |
| CPU time | 29.44 seconds |
| Started | Jul 31 08:01:51 PM PDT 24 |
| Finished | Jul 31 08:02:21 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-5b8c1ab1-637b-45ff-a8c4-dbbd0ba9c30a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903827830 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_error.1903827830 |
| Directory | /workspace/78.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.2790819611 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 7285708324 ps |
| CPU time | 322.52 seconds |
| Started | Jul 31 08:01:52 PM PDT 24 |
| Finished | Jul 31 08:07:14 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-44f2b9db-4e87-4e1c-8694-afed9985dfcc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790819611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all _with_rand_reset.2790819611 |
| Directory | /workspace/78.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.898380968 |
| Short name | T2056 |
| Test name | |
| Test status | |
| Simulation time | 15167284 ps |
| CPU time | 14.53 seconds |
| Started | Jul 31 08:01:51 PM PDT 24 |
| Finished | Jul 31 08:02:06 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-646e87e6-a173-41a4-a547-bc5d0dc5b935 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898380968 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all _with_reset_error.898380968 |
| Directory | /workspace/78.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_unmapped_addr.3312933011 |
| Short name | T1916 |
| Test name | |
| Test status | |
| Simulation time | 256754084 ps |
| CPU time | 30.8 seconds |
| Started | Jul 31 08:01:43 PM PDT 24 |
| Finished | Jul 31 08:02:14 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-1d71f54d-363c-4ec6-9d2f-23efff59d64b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312933011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_unmapped_addr.3312933011 |
| Directory | /workspace/78.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device.3678677598 |
| Short name | T1499 |
| Test name | |
| Test status | |
| Simulation time | 1388291061 ps |
| CPU time | 58.08 seconds |
| Started | Jul 31 08:01:53 PM PDT 24 |
| Finished | Jul 31 08:02:51 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-6be873a9-1be4-44ca-9b9b-cacdad9633f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678677598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device .3678677598 |
| Directory | /workspace/79.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.273410878 |
| Short name | T2300 |
| Test name | |
| Test status | |
| Simulation time | 51092064745 ps |
| CPU time | 875.12 seconds |
| Started | Jul 31 08:01:51 PM PDT 24 |
| Finished | Jul 31 08:16:26 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-c2dfbced-6c3d-4ef9-aeba-219bc6f9f208 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273410878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_d evice_slow_rsp.273410878 |
| Directory | /workspace/79.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.403053634 |
| Short name | T2408 |
| Test name | |
| Test status | |
| Simulation time | 154447626 ps |
| CPU time | 9.35 seconds |
| Started | Jul 31 08:01:59 PM PDT 24 |
| Finished | Jul 31 08:02:09 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-8818caa1-51c4-4a9e-a80a-3fc0a627c8cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403053634 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_and_unmapped_addr .403053634 |
| Directory | /workspace/79.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_random.3692944942 |
| Short name | T1835 |
| Test name | |
| Test status | |
| Simulation time | 223980135 ps |
| CPU time | 21.37 seconds |
| Started | Jul 31 08:01:59 PM PDT 24 |
| Finished | Jul 31 08:02:20 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-f5869a2f-4d2f-4550-b54a-6d0f5218a8da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692944942 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_random.3692944942 |
| Directory | /workspace/79.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random.807771077 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 34151803 ps |
| CPU time | 5.98 seconds |
| Started | Jul 31 08:01:53 PM PDT 24 |
| Finished | Jul 31 08:01:59 PM PDT 24 |
| Peak memory | 574448 kb |
| Host | smart-d40eceff-4e36-4531-96ee-ed6f625b4e39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807771077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random.807771077 |
| Directory | /workspace/79.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_large_delays.3428598851 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 93908979885 ps |
| CPU time | 1082.71 seconds |
| Started | Jul 31 08:01:54 PM PDT 24 |
| Finished | Jul 31 08:19:57 PM PDT 24 |
| Peak memory | 576784 kb |
| Host | smart-484b0b30-17c8-469f-9971-3728d140495d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428598851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_large_delays.3428598851 |
| Directory | /workspace/79.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_slow_rsp.3690176805 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 24553638316 ps |
| CPU time | 447.71 seconds |
| Started | Jul 31 08:01:52 PM PDT 24 |
| Finished | Jul 31 08:09:20 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-a2d91762-15b7-4bfc-9fc4-c4fa9a1e3ccd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690176805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_slow_rsp.3690176805 |
| Directory | /workspace/79.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_zero_delays.3719000139 |
| Short name | T1845 |
| Test name | |
| Test status | |
| Simulation time | 223283336 ps |
| CPU time | 22.03 seconds |
| Started | Jul 31 08:01:51 PM PDT 24 |
| Finished | Jul 31 08:02:13 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-a47dec8b-6b80-4980-95bd-36342a97141f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719000139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_zero_del ays.3719000139 |
| Directory | /workspace/79.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_same_source.3950729936 |
| Short name | T2619 |
| Test name | |
| Test status | |
| Simulation time | 504185178 ps |
| CPU time | 40.48 seconds |
| Started | Jul 31 08:01:57 PM PDT 24 |
| Finished | Jul 31 08:02:38 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-24ad2873-28f1-4598-a061-05be0c1eea87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950729936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_same_source.3950729936 |
| Directory | /workspace/79.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke.1150028683 |
| Short name | T2583 |
| Test name | |
| Test status | |
| Simulation time | 44163161 ps |
| CPU time | 6.19 seconds |
| Started | Jul 31 08:01:51 PM PDT 24 |
| Finished | Jul 31 08:01:58 PM PDT 24 |
| Peak memory | 573824 kb |
| Host | smart-e2f852ab-dbaa-40a2-8e13-2d56f804ec29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150028683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke.1150028683 |
| Directory | /workspace/79.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.2347794121 |
| Short name | T1611 |
| Test name | |
| Test status | |
| Simulation time | 10395823987 ps |
| CPU time | 113.7 seconds |
| Started | Jul 31 08:01:53 PM PDT 24 |
| Finished | Jul 31 08:03:47 PM PDT 24 |
| Peak memory | 573952 kb |
| Host | smart-03bc16d3-74a1-4268-b8b7-8c27f24badaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347794121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_large_delays.2347794121 |
| Directory | /workspace/79.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.4044342513 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 6317754292 ps |
| CPU time | 108.27 seconds |
| Started | Jul 31 08:01:52 PM PDT 24 |
| Finished | Jul 31 08:03:41 PM PDT 24 |
| Peak memory | 573880 kb |
| Host | smart-3d97336b-1c86-4da4-97f9-d81214f7becd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044342513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_slow_rsp.4044342513 |
| Directory | /workspace/79.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.725367072 |
| Short name | T1560 |
| Test name | |
| Test status | |
| Simulation time | 37687143 ps |
| CPU time | 5.84 seconds |
| Started | Jul 31 08:01:51 PM PDT 24 |
| Finished | Jul 31 08:01:57 PM PDT 24 |
| Peak memory | 573824 kb |
| Host | smart-7cb152f8-ba4a-44bc-a6b9-e3b7dfb44df1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725367072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_zero_delays .725367072 |
| Directory | /workspace/79.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all.3598109593 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 1438636997 ps |
| CPU time | 116.64 seconds |
| Started | Jul 31 08:02:02 PM PDT 24 |
| Finished | Jul 31 08:03:59 PM PDT 24 |
| Peak memory | 576288 kb |
| Host | smart-7bb71990-3fa6-4cb1-93e8-171f2f423949 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598109593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all.3598109593 |
| Directory | /workspace/79.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.682000535 |
| Short name | T2762 |
| Test name | |
| Test status | |
| Simulation time | 752317397 ps |
| CPU time | 53.09 seconds |
| Started | Jul 31 08:01:59 PM PDT 24 |
| Finished | Jul 31 08:02:53 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-2d985007-3845-4d67-ba8e-3b1ba40c3caf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682000535 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_error.682000535 |
| Directory | /workspace/79.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.3736314315 |
| Short name | T2175 |
| Test name | |
| Test status | |
| Simulation time | 6804011910 ps |
| CPU time | 470.55 seconds |
| Started | Jul 31 08:01:59 PM PDT 24 |
| Finished | Jul 31 08:09:50 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-e60ea543-27f1-49a5-9696-4079f1dd41b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736314315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all _with_rand_reset.3736314315 |
| Directory | /workspace/79.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.1199255490 |
| Short name | T2590 |
| Test name | |
| Test status | |
| Simulation time | 1595735267 ps |
| CPU time | 182.07 seconds |
| Started | Jul 31 08:01:59 PM PDT 24 |
| Finished | Jul 31 08:05:01 PM PDT 24 |
| Peak memory | 576736 kb |
| Host | smart-192ad69d-ccb6-41ac-8ae9-69735290b6b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199255490 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_al l_with_reset_error.1199255490 |
| Directory | /workspace/79.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_unmapped_addr.1180644176 |
| Short name | T1783 |
| Test name | |
| Test status | |
| Simulation time | 177975055 ps |
| CPU time | 22.23 seconds |
| Started | Jul 31 08:01:58 PM PDT 24 |
| Finished | Jul 31 08:02:20 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-a6530cea-4161-4457-9d52-503b6e9f09c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180644176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_unmapped_addr.1180644176 |
| Directory | /workspace/79.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.3590484431 |
| Short name | T2328 |
| Test name | |
| Test status | |
| Simulation time | 9154480028 ps |
| CPU time | 692.61 seconds |
| Started | Jul 31 07:47:47 PM PDT 24 |
| Finished | Jul 31 07:59:20 PM PDT 24 |
| Peak memory | 646672 kb |
| Host | smart-1cca3dc1-8235-423d-b218-8bc08407f4e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590484431 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 8.chip_csr_mem_rw_with_rand_reset.3590484431 |
| Directory | /workspace/8.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_csr_rw.1569377143 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 4045815055 ps |
| CPU time | 351.47 seconds |
| Started | Jul 31 07:47:48 PM PDT 24 |
| Finished | Jul 31 07:53:40 PM PDT 24 |
| Peak memory | 599492 kb |
| Host | smart-3a8e8876-8714-4be5-9442-c08a03f802d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569377143 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_csr_rw.1569377143 |
| Directory | /workspace/8.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.2345663456 |
| Short name | T2423 |
| Test name | |
| Test status | |
| Simulation time | 28385850428 ps |
| CPU time | 3812.77 seconds |
| Started | Jul 31 07:47:32 PM PDT 24 |
| Finished | Jul 31 08:51:06 PM PDT 24 |
| Peak memory | 593628 kb |
| Host | smart-2020b19d-3832-4627-845a-ea06226195a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345663456 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 8.chip_same_csr_outstanding.2345663456 |
| Directory | /workspace/8.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_tl_errors.3343006749 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 3331530626 ps |
| CPU time | 227.23 seconds |
| Started | Jul 31 07:47:33 PM PDT 24 |
| Finished | Jul 31 07:51:20 PM PDT 24 |
| Peak memory | 598584 kb |
| Host | smart-87ca8898-da33-4230-9a44-5049aecba5ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343006749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_tl_errors.3343006749 |
| Directory | /workspace/8.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device.4115521718 |
| Short name | T1738 |
| Test name | |
| Test status | |
| Simulation time | 889255076 ps |
| CPU time | 80.46 seconds |
| Started | Jul 31 07:47:42 PM PDT 24 |
| Finished | Jul 31 07:49:02 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-e720ecea-7c34-4ec6-b20b-dce340437547 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115521718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device. 4115521718 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.2957606795 |
| Short name | T1838 |
| Test name | |
| Test status | |
| Simulation time | 50512153074 ps |
| CPU time | 830.98 seconds |
| Started | Jul 31 07:47:38 PM PDT 24 |
| Finished | Jul 31 08:01:29 PM PDT 24 |
| Peak memory | 576040 kb |
| Host | smart-b6aa9994-0a9a-4ad7-b2e0-392c22a0abfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957606795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_d evice_slow_rsp.2957606795 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.4154335313 |
| Short name | T2738 |
| Test name | |
| Test status | |
| Simulation time | 1193993856 ps |
| CPU time | 47.66 seconds |
| Started | Jul 31 07:47:38 PM PDT 24 |
| Finished | Jul 31 07:48:25 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-11b514d4-784d-4ccd-a9e2-2a0ae30e5be0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154335313 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr .4154335313 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_random.2104890196 |
| Short name | T1875 |
| Test name | |
| Test status | |
| Simulation time | 641796913 ps |
| CPU time | 25.78 seconds |
| Started | Jul 31 07:47:39 PM PDT 24 |
| Finished | Jul 31 07:48:05 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-855ba260-4067-4d65-a767-15c0204acfd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104890196 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.2104890196 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random.77234821 |
| Short name | T2007 |
| Test name | |
| Test status | |
| Simulation time | 1118000063 ps |
| CPU time | 38.81 seconds |
| Started | Jul 31 07:47:34 PM PDT 24 |
| Finished | Jul 31 07:48:13 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-407dcace-d78f-42db-80e2-85d9e5bf147f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77234821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random.77234821 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_large_delays.1877325620 |
| Short name | T2028 |
| Test name | |
| Test status | |
| Simulation time | 53128620339 ps |
| CPU time | 569.23 seconds |
| Started | Jul 31 07:47:35 PM PDT 24 |
| Finished | Jul 31 07:57:04 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-12f6173f-ffcd-4d78-bc97-1ab180bf43bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877325620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.1877325620 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.3707155768 |
| Short name | T1928 |
| Test name | |
| Test status | |
| Simulation time | 57928561476 ps |
| CPU time | 939.67 seconds |
| Started | Jul 31 07:47:37 PM PDT 24 |
| Finished | Jul 31 08:03:17 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-a2e8f0ec-5844-4cb2-acfe-cd0e8a9f0d12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707155768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.3707155768 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.4224872551 |
| Short name | T2768 |
| Test name | |
| Test status | |
| Simulation time | 158497177 ps |
| CPU time | 15.22 seconds |
| Started | Jul 31 07:47:33 PM PDT 24 |
| Finished | Jul 31 07:47:48 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-13ed2920-0575-4751-83a0-b43b7c613823 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224872551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_dela ys.4224872551 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_same_source.4141064927 |
| Short name | T2709 |
| Test name | |
| Test status | |
| Simulation time | 216196873 ps |
| CPU time | 17.29 seconds |
| Started | Jul 31 07:47:41 PM PDT 24 |
| Finished | Jul 31 07:47:58 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-86e64d5b-b598-481e-90ac-03edc98e67d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141064927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.4141064927 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke.2916835449 |
| Short name | T1659 |
| Test name | |
| Test status | |
| Simulation time | 57135163 ps |
| CPU time | 6.98 seconds |
| Started | Jul 31 07:47:33 PM PDT 24 |
| Finished | Jul 31 07:47:40 PM PDT 24 |
| Peak memory | 573788 kb |
| Host | smart-7e95dd1d-9f1c-4c6d-84f4-b6a046facddc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916835449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.2916835449 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_large_delays.1756184431 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 5575669680 ps |
| CPU time | 55.22 seconds |
| Started | Jul 31 07:47:33 PM PDT 24 |
| Finished | Jul 31 07:48:28 PM PDT 24 |
| Peak memory | 573836 kb |
| Host | smart-77852ed5-e946-478d-b954-a623f8d3e439 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756184431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.1756184431 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.3079838434 |
| Short name | T2502 |
| Test name | |
| Test status | |
| Simulation time | 4602458139 ps |
| CPU time | 79.35 seconds |
| Started | Jul 31 07:47:34 PM PDT 24 |
| Finished | Jul 31 07:48:54 PM PDT 24 |
| Peak memory | 573908 kb |
| Host | smart-4b91c709-4a99-4d70-a318-b8a4f61b879f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079838434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.3079838434 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_zero_delays.3796759391 |
| Short name | T1542 |
| Test name | |
| Test status | |
| Simulation time | 42424831 ps |
| CPU time | 6.14 seconds |
| Started | Jul 31 07:47:35 PM PDT 24 |
| Finished | Jul 31 07:47:41 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-100fc2cc-8cac-40f2-91e7-aa9d882df191 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796759391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays .3796759391 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all.2523241092 |
| Short name | T2323 |
| Test name | |
| Test status | |
| Simulation time | 2860900563 ps |
| CPU time | 109.03 seconds |
| Started | Jul 31 07:47:38 PM PDT 24 |
| Finished | Jul 31 07:49:27 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-353e7cf0-bf6d-4997-b846-3d1d2a5ea13c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523241092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.2523241092 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.1699799087 |
| Short name | T2445 |
| Test name | |
| Test status | |
| Simulation time | 6274567787 ps |
| CPU time | 205.84 seconds |
| Started | Jul 31 07:47:48 PM PDT 24 |
| Finished | Jul 31 07:51:13 PM PDT 24 |
| Peak memory | 576152 kb |
| Host | smart-55e87c2c-727c-4191-bc81-785c8eaf56cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699799087 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.1699799087 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.2924980529 |
| Short name | T2722 |
| Test name | |
| Test status | |
| Simulation time | 2689185691 ps |
| CPU time | 372.62 seconds |
| Started | Jul 31 07:47:45 PM PDT 24 |
| Finished | Jul 31 07:53:58 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-ccf60fcf-f18d-4bc4-a2aa-340ec962a303 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924980529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_ with_rand_reset.2924980529 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.1407260094 |
| Short name | T2914 |
| Test name | |
| Test status | |
| Simulation time | 5064406696 ps |
| CPU time | 481.99 seconds |
| Started | Jul 31 07:47:49 PM PDT 24 |
| Finished | Jul 31 07:55:51 PM PDT 24 |
| Peak memory | 576636 kb |
| Host | smart-22ac3ed9-6ddb-47a4-a3b4-b11de078fb6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407260094 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all _with_reset_error.1407260094 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.1404898367 |
| Short name | T2377 |
| Test name | |
| Test status | |
| Simulation time | 747949285 ps |
| CPU time | 31.82 seconds |
| Started | Jul 31 07:47:39 PM PDT 24 |
| Finished | Jul 31 07:48:10 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-519d899d-6864-4e59-bc9c-969cd2ac317d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404898367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.1404898367 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device.4243097347 |
| Short name | T2270 |
| Test name | |
| Test status | |
| Simulation time | 712181604 ps |
| CPU time | 27.32 seconds |
| Started | Jul 31 08:02:02 PM PDT 24 |
| Finished | Jul 31 08:02:30 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-50075230-6db0-423d-b306-02297f0a3b7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243097347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device .4243097347 |
| Directory | /workspace/80.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.1415434276 |
| Short name | T2668 |
| Test name | |
| Test status | |
| Simulation time | 66371660456 ps |
| CPU time | 1204.24 seconds |
| Started | Jul 31 08:02:04 PM PDT 24 |
| Finished | Jul 31 08:22:09 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-e44f3a0c-1021-4dd8-9ea5-e8c4adc1d3cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415434276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_ device_slow_rsp.1415434276 |
| Directory | /workspace/80.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.2307262227 |
| Short name | T1577 |
| Test name | |
| Test status | |
| Simulation time | 1082252406 ps |
| CPU time | 42.77 seconds |
| Started | Jul 31 08:02:11 PM PDT 24 |
| Finished | Jul 31 08:02:54 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-d45225b2-0a70-4437-b0e1-d2b12088464f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307262227 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_and_unmapped_add r.2307262227 |
| Directory | /workspace/80.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_random.1421792128 |
| Short name | T2345 |
| Test name | |
| Test status | |
| Simulation time | 664606244 ps |
| CPU time | 27.46 seconds |
| Started | Jul 31 08:02:06 PM PDT 24 |
| Finished | Jul 31 08:02:34 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-ec984963-d59c-4751-9a3a-adc7d709de1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421792128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_random.1421792128 |
| Directory | /workspace/80.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random.46387562 |
| Short name | T2076 |
| Test name | |
| Test status | |
| Simulation time | 333053005 ps |
| CPU time | 31.13 seconds |
| Started | Jul 31 08:02:00 PM PDT 24 |
| Finished | Jul 31 08:02:31 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-9309eb03-1820-42a7-9da6-6e2a81441c0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46387562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random.46387562 |
| Directory | /workspace/80.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_large_delays.735430409 |
| Short name | T2614 |
| Test name | |
| Test status | |
| Simulation time | 67730480132 ps |
| CPU time | 675.74 seconds |
| Started | Jul 31 08:02:01 PM PDT 24 |
| Finished | Jul 31 08:13:17 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-68b52ab6-929e-482f-8941-739c6d6fe110 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735430409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_large_delays.735430409 |
| Directory | /workspace/80.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_slow_rsp.3506906585 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 34213167480 ps |
| CPU time | 588.28 seconds |
| Started | Jul 31 08:01:59 PM PDT 24 |
| Finished | Jul 31 08:11:48 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-dd47e557-4059-4577-acdf-e1c30b8e2d62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506906585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_slow_rsp.3506906585 |
| Directory | /workspace/80.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_zero_delays.2372850783 |
| Short name | T1567 |
| Test name | |
| Test status | |
| Simulation time | 595160261 ps |
| CPU time | 43.17 seconds |
| Started | Jul 31 08:01:58 PM PDT 24 |
| Finished | Jul 31 08:02:42 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-44ddd7cd-671c-4944-a007-b5243235e512 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372850783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_zero_del ays.2372850783 |
| Directory | /workspace/80.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_same_source.569146160 |
| Short name | T2383 |
| Test name | |
| Test status | |
| Simulation time | 1243382280 ps |
| CPU time | 34.5 seconds |
| Started | Jul 31 08:02:03 PM PDT 24 |
| Finished | Jul 31 08:02:37 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-e71a7450-aec6-49ea-b41f-627068630dd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569146160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_same_source.569146160 |
| Directory | /workspace/80.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke.138211872 |
| Short name | T2253 |
| Test name | |
| Test status | |
| Simulation time | 149325447 ps |
| CPU time | 7.61 seconds |
| Started | Jul 31 08:02:01 PM PDT 24 |
| Finished | Jul 31 08:02:09 PM PDT 24 |
| Peak memory | 573792 kb |
| Host | smart-4f4e26a8-9fec-4ec0-9019-4576ea2d3169 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138211872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke.138211872 |
| Directory | /workspace/80.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.797800965 |
| Short name | T1701 |
| Test name | |
| Test status | |
| Simulation time | 6998138419 ps |
| CPU time | 70.51 seconds |
| Started | Jul 31 08:01:59 PM PDT 24 |
| Finished | Jul 31 08:03:09 PM PDT 24 |
| Peak memory | 573872 kb |
| Host | smart-19fffe08-d2f8-4925-958d-2bf928aea2f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797800965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_large_delays.797800965 |
| Directory | /workspace/80.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.1468681523 |
| Short name | T1750 |
| Test name | |
| Test status | |
| Simulation time | 6345397382 ps |
| CPU time | 112.22 seconds |
| Started | Jul 31 08:01:58 PM PDT 24 |
| Finished | Jul 31 08:03:51 PM PDT 24 |
| Peak memory | 573892 kb |
| Host | smart-eeab9356-a82f-4b97-a1b6-29dd64965e18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468681523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_slow_rsp.1468681523 |
| Directory | /workspace/80.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.1298014650 |
| Short name | T2904 |
| Test name | |
| Test status | |
| Simulation time | 40949656 ps |
| CPU time | 6.21 seconds |
| Started | Jul 31 08:02:02 PM PDT 24 |
| Finished | Jul 31 08:02:08 PM PDT 24 |
| Peak memory | 573720 kb |
| Host | smart-8b298606-57c6-4582-927c-0c1f69ebcf3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298014650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_zero_delay s.1298014650 |
| Directory | /workspace/80.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all.468935720 |
| Short name | T2801 |
| Test name | |
| Test status | |
| Simulation time | 13609506356 ps |
| CPU time | 590.43 seconds |
| Started | Jul 31 08:02:06 PM PDT 24 |
| Finished | Jul 31 08:11:57 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-1022c716-9f5f-4986-9500-20049b62a5f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468935720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all.468935720 |
| Directory | /workspace/80.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.900878688 |
| Short name | T2575 |
| Test name | |
| Test status | |
| Simulation time | 14673847955 ps |
| CPU time | 590.8 seconds |
| Started | Jul 31 08:02:06 PM PDT 24 |
| Finished | Jul 31 08:11:56 PM PDT 24 |
| Peak memory | 576096 kb |
| Host | smart-84804ef8-a5df-41f7-8696-5c5e3b2d9314 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900878688 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_error.900878688 |
| Directory | /workspace/80.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.2148735885 |
| Short name | T2261 |
| Test name | |
| Test status | |
| Simulation time | 177001134 ps |
| CPU time | 104.66 seconds |
| Started | Jul 31 08:02:09 PM PDT 24 |
| Finished | Jul 31 08:03:54 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-effc8a6e-686d-4f54-8de0-72f5b3c219af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148735885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all _with_rand_reset.2148735885 |
| Directory | /workspace/80.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.3267207211 |
| Short name | T1952 |
| Test name | |
| Test status | |
| Simulation time | 1010015585 ps |
| CPU time | 284.25 seconds |
| Started | Jul 31 08:02:06 PM PDT 24 |
| Finished | Jul 31 08:06:50 PM PDT 24 |
| Peak memory | 576836 kb |
| Host | smart-3ec61dca-b304-48a8-8e86-02233f58f900 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267207211 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_al l_with_reset_error.3267207211 |
| Directory | /workspace/80.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_unmapped_addr.697995084 |
| Short name | T1557 |
| Test name | |
| Test status | |
| Simulation time | 1428749802 ps |
| CPU time | 63.31 seconds |
| Started | Jul 31 08:02:09 PM PDT 24 |
| Finished | Jul 31 08:03:12 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-04621fd9-efad-4d15-b185-a6d90855c413 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697995084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_unmapped_addr.697995084 |
| Directory | /workspace/80.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device.3780216528 |
| Short name | T2372 |
| Test name | |
| Test status | |
| Simulation time | 621934439 ps |
| CPU time | 29.72 seconds |
| Started | Jul 31 08:02:13 PM PDT 24 |
| Finished | Jul 31 08:02:43 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-d1b8a19d-a9d8-4a05-82ac-01dbf9649416 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780216528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device .3780216528 |
| Directory | /workspace/81.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.2580592928 |
| Short name | T1913 |
| Test name | |
| Test status | |
| Simulation time | 73332053 ps |
| CPU time | 6.5 seconds |
| Started | Jul 31 08:02:21 PM PDT 24 |
| Finished | Jul 31 08:02:28 PM PDT 24 |
| Peak memory | 573796 kb |
| Host | smart-0d7fb867-32b2-444a-85d1-bd5b084be020 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580592928 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_and_unmapped_add r.2580592928 |
| Directory | /workspace/81.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_random.1722877338 |
| Short name | T1453 |
| Test name | |
| Test status | |
| Simulation time | 1138026628 ps |
| CPU time | 37.41 seconds |
| Started | Jul 31 08:02:32 PM PDT 24 |
| Finished | Jul 31 08:03:09 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-0464994b-05b5-4377-b495-d001341a2b0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722877338 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_random.1722877338 |
| Directory | /workspace/81.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random.2552269063 |
| Short name | T1974 |
| Test name | |
| Test status | |
| Simulation time | 1546329936 ps |
| CPU time | 54.04 seconds |
| Started | Jul 31 08:02:11 PM PDT 24 |
| Finished | Jul 31 08:03:05 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-5dd18298-e63c-4275-b13c-103df2fb2597 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552269063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random.2552269063 |
| Directory | /workspace/81.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_large_delays.3622557082 |
| Short name | T2471 |
| Test name | |
| Test status | |
| Simulation time | 28223282767 ps |
| CPU time | 298.17 seconds |
| Started | Jul 31 08:02:12 PM PDT 24 |
| Finished | Jul 31 08:07:11 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-4cb2436f-6970-49b0-8a4d-877d752a3be2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622557082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_large_delays.3622557082 |
| Directory | /workspace/81.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.3871741702 |
| Short name | T2657 |
| Test name | |
| Test status | |
| Simulation time | 62033616918 ps |
| CPU time | 1075.1 seconds |
| Started | Jul 31 08:02:19 PM PDT 24 |
| Finished | Jul 31 08:20:14 PM PDT 24 |
| Peak memory | 576052 kb |
| Host | smart-fe9a0c67-cc1a-4c14-b299-5bb8e87040b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871741702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_slow_rsp.3871741702 |
| Directory | /workspace/81.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_zero_delays.2082786000 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 594134024 ps |
| CPU time | 51.95 seconds |
| Started | Jul 31 08:02:14 PM PDT 24 |
| Finished | Jul 31 08:03:06 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-1095888f-d610-4ed0-b2f0-7110b95d0bdb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082786000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_zero_del ays.2082786000 |
| Directory | /workspace/81.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_same_source.3471067552 |
| Short name | T1822 |
| Test name | |
| Test status | |
| Simulation time | 332897568 ps |
| CPU time | 12.6 seconds |
| Started | Jul 31 08:02:14 PM PDT 24 |
| Finished | Jul 31 08:02:27 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-337a50f6-6b39-46bc-ad36-5d2e9e73ffc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471067552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_same_source.3471067552 |
| Directory | /workspace/81.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke.4095527135 |
| Short name | T2180 |
| Test name | |
| Test status | |
| Simulation time | 45736920 ps |
| CPU time | 5.91 seconds |
| Started | Jul 31 08:02:04 PM PDT 24 |
| Finished | Jul 31 08:02:10 PM PDT 24 |
| Peak memory | 573844 kb |
| Host | smart-0bb90351-7a5b-4bbd-b81f-a4513b307111 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095527135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke.4095527135 |
| Directory | /workspace/81.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_large_delays.2013799021 |
| Short name | T1734 |
| Test name | |
| Test status | |
| Simulation time | 10829395643 ps |
| CPU time | 112.27 seconds |
| Started | Jul 31 08:02:12 PM PDT 24 |
| Finished | Jul 31 08:04:04 PM PDT 24 |
| Peak memory | 573936 kb |
| Host | smart-7a1d84f8-7e5a-4563-944c-2cc42ca31e39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013799021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_large_delays.2013799021 |
| Directory | /workspace/81.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.1378420248 |
| Short name | T1927 |
| Test name | |
| Test status | |
| Simulation time | 5300541502 ps |
| CPU time | 82.02 seconds |
| Started | Jul 31 08:02:20 PM PDT 24 |
| Finished | Jul 31 08:03:42 PM PDT 24 |
| Peak memory | 573868 kb |
| Host | smart-e96abe3c-9ab8-4811-84b2-0aa87dc493df |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378420248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_slow_rsp.1378420248 |
| Directory | /workspace/81.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_zero_delays.3454913377 |
| Short name | T1987 |
| Test name | |
| Test status | |
| Simulation time | 46739021 ps |
| CPU time | 6.55 seconds |
| Started | Jul 31 08:02:06 PM PDT 24 |
| Finished | Jul 31 08:02:13 PM PDT 24 |
| Peak memory | 573812 kb |
| Host | smart-4f94ba7a-8e7f-4fa6-b61a-21e65065ca39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454913377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_zero_delay s.3454913377 |
| Directory | /workspace/81.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all.612286330 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 440533735 ps |
| CPU time | 27.91 seconds |
| Started | Jul 31 08:02:20 PM PDT 24 |
| Finished | Jul 31 08:02:48 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-0f79897e-7b0e-46ad-8dc2-14d5ca900c80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612286330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all.612286330 |
| Directory | /workspace/81.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.1614493031 |
| Short name | T1570 |
| Test name | |
| Test status | |
| Simulation time | 6442375751 ps |
| CPU time | 220.68 seconds |
| Started | Jul 31 08:02:23 PM PDT 24 |
| Finished | Jul 31 08:06:04 PM PDT 24 |
| Peak memory | 576124 kb |
| Host | smart-903162b2-0a6f-441a-8b48-8c0c54492cde |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614493031 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_error.1614493031 |
| Directory | /workspace/81.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.1043910610 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 5864558474 ps |
| CPU time | 547.38 seconds |
| Started | Jul 31 08:02:19 PM PDT 24 |
| Finished | Jul 31 08:11:27 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-e9aa4284-c3c0-435b-a329-ec25c62496ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043910610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all _with_rand_reset.1043910610 |
| Directory | /workspace/81.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.1909053045 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 2614107868 ps |
| CPU time | 206.56 seconds |
| Started | Jul 31 08:02:21 PM PDT 24 |
| Finished | Jul 31 08:05:48 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-8be7d074-8600-4f2d-bc60-b01e6b219dcd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909053045 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_al l_with_reset_error.1909053045 |
| Directory | /workspace/81.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_unmapped_addr.2333411838 |
| Short name | T1862 |
| Test name | |
| Test status | |
| Simulation time | 1119820316 ps |
| CPU time | 44.9 seconds |
| Started | Jul 31 08:02:13 PM PDT 24 |
| Finished | Jul 31 08:02:58 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-0dfe5dff-6837-45b3-8826-2f2eb781f469 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333411838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_unmapped_addr.2333411838 |
| Directory | /workspace/81.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device.3617752199 |
| Short name | T1733 |
| Test name | |
| Test status | |
| Simulation time | 3088354296 ps |
| CPU time | 110.94 seconds |
| Started | Jul 31 08:02:30 PM PDT 24 |
| Finished | Jul 31 08:04:21 PM PDT 24 |
| Peak memory | 576084 kb |
| Host | smart-41716463-5383-4ebe-9ac6-8ece324c197b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617752199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device .3617752199 |
| Directory | /workspace/82.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.4009687693 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 107867164213 ps |
| CPU time | 2036.96 seconds |
| Started | Jul 31 08:02:37 PM PDT 24 |
| Finished | Jul 31 08:36:35 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-7481a6c7-ef34-4f19-9550-c00089f1a848 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009687693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_ device_slow_rsp.4009687693 |
| Directory | /workspace/82.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.272520043 |
| Short name | T1578 |
| Test name | |
| Test status | |
| Simulation time | 181256095 ps |
| CPU time | 18.85 seconds |
| Started | Jul 31 08:02:25 PM PDT 24 |
| Finished | Jul 31 08:02:44 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-101f36d4-2ed6-4efd-a71a-cb82f51f6c4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272520043 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_and_unmapped_addr .272520043 |
| Directory | /workspace/82.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_random.211683621 |
| Short name | T2728 |
| Test name | |
| Test status | |
| Simulation time | 581637950 ps |
| CPU time | 49.17 seconds |
| Started | Jul 31 08:02:28 PM PDT 24 |
| Finished | Jul 31 08:03:17 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-93932dd2-f292-4b35-a3d2-9ced1671a539 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211683621 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_random.211683621 |
| Directory | /workspace/82.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random.3302052128 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 745162119 ps |
| CPU time | 29.37 seconds |
| Started | Jul 31 08:02:21 PM PDT 24 |
| Finished | Jul 31 08:02:51 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-90d8a4c4-0861-4dd2-8b40-42d82d176068 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302052128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random.3302052128 |
| Directory | /workspace/82.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_large_delays.1931184777 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 98967201628 ps |
| CPU time | 975.94 seconds |
| Started | Jul 31 08:02:25 PM PDT 24 |
| Finished | Jul 31 08:18:41 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-381d703e-a3fe-4469-8226-8e24f22a4b5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931184777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_large_delays.1931184777 |
| Directory | /workspace/82.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_slow_rsp.4268004580 |
| Short name | T2400 |
| Test name | |
| Test status | |
| Simulation time | 27112889165 ps |
| CPU time | 430.65 seconds |
| Started | Jul 31 08:04:00 PM PDT 24 |
| Finished | Jul 31 08:11:11 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-d92dacde-94ec-4de9-ac54-70fec15424fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268004580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_slow_rsp.4268004580 |
| Directory | /workspace/82.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.2080970364 |
| Short name | T1812 |
| Test name | |
| Test status | |
| Simulation time | 150400464 ps |
| CPU time | 14.44 seconds |
| Started | Jul 31 08:02:28 PM PDT 24 |
| Finished | Jul 31 08:02:42 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-38ac1a2f-6cbd-4171-b6b9-dcf2366edbe1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080970364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_zero_del ays.2080970364 |
| Directory | /workspace/82.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_same_source.1484790660 |
| Short name | T2455 |
| Test name | |
| Test status | |
| Simulation time | 2171985188 ps |
| CPU time | 63.37 seconds |
| Started | Jul 31 08:02:28 PM PDT 24 |
| Finished | Jul 31 08:03:32 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-8504f5d0-740e-4982-9325-77f224acc578 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484790660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_same_source.1484790660 |
| Directory | /workspace/82.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke.4075077999 |
| Short name | T2520 |
| Test name | |
| Test status | |
| Simulation time | 104096684 ps |
| CPU time | 6.31 seconds |
| Started | Jul 31 08:02:21 PM PDT 24 |
| Finished | Jul 31 08:02:28 PM PDT 24 |
| Peak memory | 573792 kb |
| Host | smart-c347b78d-7318-473a-bd3e-cce974e128e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075077999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke.4075077999 |
| Directory | /workspace/82.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_large_delays.3848930149 |
| Short name | T2462 |
| Test name | |
| Test status | |
| Simulation time | 9812811564 ps |
| CPU time | 102.31 seconds |
| Started | Jul 31 08:02:22 PM PDT 24 |
| Finished | Jul 31 08:04:04 PM PDT 24 |
| Peak memory | 574584 kb |
| Host | smart-2e78047e-896e-43e4-81a3-f306a82ecfc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848930149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_large_delays.3848930149 |
| Directory | /workspace/82.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.862867023 |
| Short name | T2508 |
| Test name | |
| Test status | |
| Simulation time | 5462497310 ps |
| CPU time | 95.01 seconds |
| Started | Jul 31 08:02:22 PM PDT 24 |
| Finished | Jul 31 08:03:57 PM PDT 24 |
| Peak memory | 573876 kb |
| Host | smart-0464a65e-0f75-44aa-8b17-4ff273a38553 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862867023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_slow_rsp.862867023 |
| Directory | /workspace/82.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_zero_delays.3200063276 |
| Short name | T1945 |
| Test name | |
| Test status | |
| Simulation time | 43593653 ps |
| CPU time | 6.02 seconds |
| Started | Jul 31 08:02:20 PM PDT 24 |
| Finished | Jul 31 08:02:26 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-814d14e1-0955-45c3-b9de-325267e83e9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200063276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_zero_delay s.3200063276 |
| Directory | /workspace/82.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all.175812016 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 2301667284 ps |
| CPU time | 192.17 seconds |
| Started | Jul 31 08:02:28 PM PDT 24 |
| Finished | Jul 31 08:05:40 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-b8000c81-1531-4218-9bc1-f404d791698a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175812016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all.175812016 |
| Directory | /workspace/82.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.3210319246 |
| Short name | T2410 |
| Test name | |
| Test status | |
| Simulation time | 6648619924 ps |
| CPU time | 204.32 seconds |
| Started | Jul 31 08:02:29 PM PDT 24 |
| Finished | Jul 31 08:05:54 PM PDT 24 |
| Peak memory | 576076 kb |
| Host | smart-13b6461f-eaa4-4804-8fde-ef408788a010 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210319246 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_error.3210319246 |
| Directory | /workspace/82.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.1114440812 |
| Short name | T2316 |
| Test name | |
| Test status | |
| Simulation time | 526985436 ps |
| CPU time | 225.86 seconds |
| Started | Jul 31 08:02:27 PM PDT 24 |
| Finished | Jul 31 08:06:13 PM PDT 24 |
| Peak memory | 576708 kb |
| Host | smart-a08e60e5-c4fe-4166-839d-abbcd32d0b00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114440812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all _with_rand_reset.1114440812 |
| Directory | /workspace/82.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.4122075591 |
| Short name | T2706 |
| Test name | |
| Test status | |
| Simulation time | 2399558075 ps |
| CPU time | 265.16 seconds |
| Started | Jul 31 08:02:37 PM PDT 24 |
| Finished | Jul 31 08:07:03 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-6d89667f-c63f-495b-9e1a-5c05c9ec091f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122075591 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_al l_with_reset_error.4122075591 |
| Directory | /workspace/82.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_unmapped_addr.3176793843 |
| Short name | T2764 |
| Test name | |
| Test status | |
| Simulation time | 1048863973 ps |
| CPU time | 48.26 seconds |
| Started | Jul 31 08:02:26 PM PDT 24 |
| Finished | Jul 31 08:03:15 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-7245264a-684b-4f55-9aa7-a5bb9c2792a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176793843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_unmapped_addr.3176793843 |
| Directory | /workspace/82.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device.1363829662 |
| Short name | T2763 |
| Test name | |
| Test status | |
| Simulation time | 973204605 ps |
| CPU time | 51.07 seconds |
| Started | Jul 31 08:02:27 PM PDT 24 |
| Finished | Jul 31 08:03:18 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-35020613-29da-43ac-b54d-f236057993dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363829662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device .1363829662 |
| Directory | /workspace/83.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.3108296833 |
| Short name | T2343 |
| Test name | |
| Test status | |
| Simulation time | 1006869940 ps |
| CPU time | 40.89 seconds |
| Started | Jul 31 08:02:34 PM PDT 24 |
| Finished | Jul 31 08:03:15 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-4621d09f-7d10-4d59-9f52-9e16312566a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108296833 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_and_unmapped_add r.3108296833 |
| Directory | /workspace/83.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_random.2167069889 |
| Short name | T2804 |
| Test name | |
| Test status | |
| Simulation time | 657726192 ps |
| CPU time | 25.35 seconds |
| Started | Jul 31 08:02:29 PM PDT 24 |
| Finished | Jul 31 08:02:55 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-d475bf0a-ee25-4173-b251-f040abc71a58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167069889 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_random.2167069889 |
| Directory | /workspace/83.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random.1615137496 |
| Short name | T2864 |
| Test name | |
| Test status | |
| Simulation time | 367125507 ps |
| CPU time | 15.98 seconds |
| Started | Jul 31 08:02:29 PM PDT 24 |
| Finished | Jul 31 08:02:45 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-d124e26b-8944-49a3-be7b-87bf88eae281 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615137496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random.1615137496 |
| Directory | /workspace/83.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_large_delays.3967471086 |
| Short name | T2824 |
| Test name | |
| Test status | |
| Simulation time | 101793129447 ps |
| CPU time | 1223.68 seconds |
| Started | Jul 31 08:02:27 PM PDT 24 |
| Finished | Jul 31 08:22:51 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-fc5b34f9-9998-4429-9121-faa97210fccb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967471086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_large_delays.3967471086 |
| Directory | /workspace/83.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_slow_rsp.3400281354 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 30607521058 ps |
| CPU time | 470.72 seconds |
| Started | Jul 31 08:04:00 PM PDT 24 |
| Finished | Jul 31 08:11:51 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-e03ab1ab-bec4-4887-a34e-0bd597c42337 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400281354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_slow_rsp.3400281354 |
| Directory | /workspace/83.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.1892224051 |
| Short name | T2775 |
| Test name | |
| Test status | |
| Simulation time | 525315739 ps |
| CPU time | 47.75 seconds |
| Started | Jul 31 08:02:29 PM PDT 24 |
| Finished | Jul 31 08:03:17 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-03379624-5080-4fc2-9076-1e7abff370fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892224051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_zero_del ays.1892224051 |
| Directory | /workspace/83.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_same_source.1024258117 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 2529044567 ps |
| CPU time | 74.91 seconds |
| Started | Jul 31 08:02:37 PM PDT 24 |
| Finished | Jul 31 08:03:52 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-ce432953-fcdc-44cc-8169-94094c5dd68d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024258117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_same_source.1024258117 |
| Directory | /workspace/83.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke.336632435 |
| Short name | T1742 |
| Test name | |
| Test status | |
| Simulation time | 45189920 ps |
| CPU time | 5.93 seconds |
| Started | Jul 31 08:02:29 PM PDT 24 |
| Finished | Jul 31 08:02:35 PM PDT 24 |
| Peak memory | 573876 kb |
| Host | smart-ef7dc23c-18c0-40e8-b95c-d25ed8ff951e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336632435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke.336632435 |
| Directory | /workspace/83.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.4225829550 |
| Short name | T1775 |
| Test name | |
| Test status | |
| Simulation time | 9185237211 ps |
| CPU time | 99.48 seconds |
| Started | Jul 31 08:02:37 PM PDT 24 |
| Finished | Jul 31 08:04:17 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-2dba127c-abe7-472b-95ee-64ff630e0b8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225829550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_large_delays.4225829550 |
| Directory | /workspace/83.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.3809876968 |
| Short name | T1988 |
| Test name | |
| Test status | |
| Simulation time | 5247619038 ps |
| CPU time | 86.23 seconds |
| Started | Jul 31 08:02:26 PM PDT 24 |
| Finished | Jul 31 08:03:52 PM PDT 24 |
| Peak memory | 573920 kb |
| Host | smart-f2f28d43-e5c4-4219-a5ff-530410f52f05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809876968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_slow_rsp.3809876968 |
| Directory | /workspace/83.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_zero_delays.1145247933 |
| Short name | T2262 |
| Test name | |
| Test status | |
| Simulation time | 35927254 ps |
| CPU time | 5.81 seconds |
| Started | Jul 31 08:02:29 PM PDT 24 |
| Finished | Jul 31 08:02:35 PM PDT 24 |
| Peak memory | 573808 kb |
| Host | smart-fc6f4348-e400-4852-b11d-1e3ff16fae35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145247933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_zero_delay s.1145247933 |
| Directory | /workspace/83.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all.586776136 |
| Short name | T2850 |
| Test name | |
| Test status | |
| Simulation time | 13987862838 ps |
| CPU time | 593.02 seconds |
| Started | Jul 31 08:02:33 PM PDT 24 |
| Finished | Jul 31 08:12:27 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-9cf50133-656e-45f9-9a66-42d8a8bd7412 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586776136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all.586776136 |
| Directory | /workspace/83.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_error.806847142 |
| Short name | T1509 |
| Test name | |
| Test status | |
| Simulation time | 1047671291 ps |
| CPU time | 35.32 seconds |
| Started | Jul 31 08:02:33 PM PDT 24 |
| Finished | Jul 31 08:03:08 PM PDT 24 |
| Peak memory | 576044 kb |
| Host | smart-b1e84f61-84c9-42dd-a953-9f7b22cec03f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806847142 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_error.806847142 |
| Directory | /workspace/83.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.3394213169 |
| Short name | T2280 |
| Test name | |
| Test status | |
| Simulation time | 32367165 ps |
| CPU time | 21.08 seconds |
| Started | Jul 31 08:03:45 PM PDT 24 |
| Finished | Jul 31 08:04:06 PM PDT 24 |
| Peak memory | 573056 kb |
| Host | smart-66845f39-922e-45a8-887f-aa0a81c38faa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394213169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all _with_rand_reset.3394213169 |
| Directory | /workspace/83.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.3170701962 |
| Short name | T2798 |
| Test name | |
| Test status | |
| Simulation time | 2881101571 ps |
| CPU time | 184.83 seconds |
| Started | Jul 31 08:02:35 PM PDT 24 |
| Finished | Jul 31 08:05:40 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-b748758b-df6c-4e04-931e-cc96eb21d3ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170701962 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_al l_with_reset_error.3170701962 |
| Directory | /workspace/83.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_unmapped_addr.3490220668 |
| Short name | T2489 |
| Test name | |
| Test status | |
| Simulation time | 1414977137 ps |
| CPU time | 58.75 seconds |
| Started | Jul 31 08:02:34 PM PDT 24 |
| Finished | Jul 31 08:03:33 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-150da0ac-ab61-4bcc-9b2c-fae633329fce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490220668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_unmapped_addr.3490220668 |
| Directory | /workspace/83.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device.614294763 |
| Short name | T2487 |
| Test name | |
| Test status | |
| Simulation time | 986869805 ps |
| CPU time | 68.38 seconds |
| Started | Jul 31 08:02:36 PM PDT 24 |
| Finished | Jul 31 08:03:44 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-1dd22d3e-cc73-4faa-9107-c95b4ddf55ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614294763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device. 614294763 |
| Directory | /workspace/84.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.877069196 |
| Short name | T1626 |
| Test name | |
| Test status | |
| Simulation time | 1081025499 ps |
| CPU time | 44.21 seconds |
| Started | Jul 31 08:02:42 PM PDT 24 |
| Finished | Jul 31 08:03:26 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-f2dca757-9480-4402-b4d6-34c17714a9b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877069196 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_and_unmapped_addr .877069196 |
| Directory | /workspace/84.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_random.1045441961 |
| Short name | T2882 |
| Test name | |
| Test status | |
| Simulation time | 1315875187 ps |
| CPU time | 40.97 seconds |
| Started | Jul 31 08:02:45 PM PDT 24 |
| Finished | Jul 31 08:03:26 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-b5680201-8781-4c3b-9ce0-c4fb8713b017 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045441961 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_random.1045441961 |
| Directory | /workspace/84.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random.2116633690 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 561265470 ps |
| CPU time | 38.42 seconds |
| Started | Jul 31 08:04:00 PM PDT 24 |
| Finished | Jul 31 08:04:38 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-fe174162-0174-4234-b623-5911cebb135c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116633690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random.2116633690 |
| Directory | /workspace/84.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_large_delays.1951946717 |
| Short name | T2624 |
| Test name | |
| Test status | |
| Simulation time | 33583317445 ps |
| CPU time | 328.22 seconds |
| Started | Jul 31 08:02:33 PM PDT 24 |
| Finished | Jul 31 08:08:02 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-e3ce1118-880c-4ccd-ad0e-ab35080a6b95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951946717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_large_delays.1951946717 |
| Directory | /workspace/84.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_slow_rsp.1544746882 |
| Short name | T2892 |
| Test name | |
| Test status | |
| Simulation time | 21465193191 ps |
| CPU time | 338.93 seconds |
| Started | Jul 31 08:02:34 PM PDT 24 |
| Finished | Jul 31 08:08:13 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-d8f4dedb-3504-48aa-9136-325c997574a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544746882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_slow_rsp.1544746882 |
| Directory | /workspace/84.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_zero_delays.989569574 |
| Short name | T2016 |
| Test name | |
| Test status | |
| Simulation time | 354563230 ps |
| CPU time | 26.16 seconds |
| Started | Jul 31 08:02:33 PM PDT 24 |
| Finished | Jul 31 08:02:59 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-f7318f2f-404b-4475-ab97-beec451d3875 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989569574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_zero_dela ys.989569574 |
| Directory | /workspace/84.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_same_source.1076869633 |
| Short name | T2439 |
| Test name | |
| Test status | |
| Simulation time | 283136478 ps |
| CPU time | 10.54 seconds |
| Started | Jul 31 08:02:41 PM PDT 24 |
| Finished | Jul 31 08:02:52 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-7233efa0-5374-49b6-a259-4ea6d22d2915 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076869633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_same_source.1076869633 |
| Directory | /workspace/84.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke.3445069010 |
| Short name | T1444 |
| Test name | |
| Test status | |
| Simulation time | 241127163 ps |
| CPU time | 8.84 seconds |
| Started | Jul 31 08:03:59 PM PDT 24 |
| Finished | Jul 31 08:04:08 PM PDT 24 |
| Peak memory | 573364 kb |
| Host | smart-e7f9d56f-99a5-44dc-b795-13e9cb31df2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445069010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke.3445069010 |
| Directory | /workspace/84.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.2443149866 |
| Short name | T2229 |
| Test name | |
| Test status | |
| Simulation time | 4841560138 ps |
| CPU time | 53.84 seconds |
| Started | Jul 31 08:02:34 PM PDT 24 |
| Finished | Jul 31 08:03:28 PM PDT 24 |
| Peak memory | 573936 kb |
| Host | smart-8198ae1f-51bc-4321-8a00-affc712a6595 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443149866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_large_delays.2443149866 |
| Directory | /workspace/84.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.2173327839 |
| Short name | T1483 |
| Test name | |
| Test status | |
| Simulation time | 5700831400 ps |
| CPU time | 96.25 seconds |
| Started | Jul 31 08:02:34 PM PDT 24 |
| Finished | Jul 31 08:04:10 PM PDT 24 |
| Peak memory | 574584 kb |
| Host | smart-48a9c05d-707a-4b08-a4f6-fc816d086041 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173327839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_slow_rsp.2173327839 |
| Directory | /workspace/84.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_zero_delays.3377967819 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 54662829 ps |
| CPU time | 6.22 seconds |
| Started | Jul 31 08:02:34 PM PDT 24 |
| Finished | Jul 31 08:02:41 PM PDT 24 |
| Peak memory | 573784 kb |
| Host | smart-2d83cc7a-a962-4171-a83d-9d441bf289cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377967819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_zero_delay s.3377967819 |
| Directory | /workspace/84.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all.982655603 |
| Short name | T1769 |
| Test name | |
| Test status | |
| Simulation time | 1049510707 ps |
| CPU time | 98.65 seconds |
| Started | Jul 31 08:02:42 PM PDT 24 |
| Finished | Jul 31 08:04:21 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-9919bda6-80da-44f5-aadf-b672010a31dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982655603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all.982655603 |
| Directory | /workspace/84.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.4043025109 |
| Short name | T2723 |
| Test name | |
| Test status | |
| Simulation time | 3430908186 ps |
| CPU time | 258.04 seconds |
| Started | Jul 31 08:02:42 PM PDT 24 |
| Finished | Jul 31 08:07:00 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-a1a91b65-9b0f-43a2-a903-3ac5a9492056 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043025109 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_error.4043025109 |
| Directory | /workspace/84.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.436116104 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 400145588 ps |
| CPU time | 178.19 seconds |
| Started | Jul 31 08:02:43 PM PDT 24 |
| Finished | Jul 31 08:05:41 PM PDT 24 |
| Peak memory | 576724 kb |
| Host | smart-27282809-8d95-4b87-b2ad-8c56ffd45488 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436116104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_ with_rand_reset.436116104 |
| Directory | /workspace/84.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.2452078863 |
| Short name | T2839 |
| Test name | |
| Test status | |
| Simulation time | 501348776 ps |
| CPU time | 184.3 seconds |
| Started | Jul 31 08:02:42 PM PDT 24 |
| Finished | Jul 31 08:05:46 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-cd0c7368-80e8-4564-b10a-812b17e2f8fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452078863 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_al l_with_reset_error.2452078863 |
| Directory | /workspace/84.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_unmapped_addr.2855920929 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 798244458 ps |
| CPU time | 33.47 seconds |
| Started | Jul 31 08:02:41 PM PDT 24 |
| Finished | Jul 31 08:03:15 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-f11d742d-f116-462c-9b4b-922dbcc78296 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855920929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_unmapped_addr.2855920929 |
| Directory | /workspace/84.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device.3197910068 |
| Short name | T2236 |
| Test name | |
| Test status | |
| Simulation time | 414991732 ps |
| CPU time | 18.78 seconds |
| Started | Jul 31 08:02:49 PM PDT 24 |
| Finished | Jul 31 08:03:07 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-ffc4329b-de72-45b8-865d-33b6f4c3e0e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197910068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device .3197910068 |
| Directory | /workspace/85.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.1289123382 |
| Short name | T1833 |
| Test name | |
| Test status | |
| Simulation time | 126846307882 ps |
| CPU time | 2357.28 seconds |
| Started | Jul 31 08:02:51 PM PDT 24 |
| Finished | Jul 31 08:42:08 PM PDT 24 |
| Peak memory | 576080 kb |
| Host | smart-24627c96-2ed4-4a08-ae05-9c119b577db0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289123382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_ device_slow_rsp.1289123382 |
| Directory | /workspace/85.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.1368990749 |
| Short name | T2888 |
| Test name | |
| Test status | |
| Simulation time | 962788590 ps |
| CPU time | 38.09 seconds |
| Started | Jul 31 08:02:50 PM PDT 24 |
| Finished | Jul 31 08:03:28 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-adeae689-9a3e-4e7f-84a0-1747205d5b5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368990749 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_and_unmapped_add r.1368990749 |
| Directory | /workspace/85.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_random.3078563262 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 849975309 ps |
| CPU time | 29.3 seconds |
| Started | Jul 31 08:02:49 PM PDT 24 |
| Finished | Jul 31 08:03:19 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-96f56c81-13ff-4951-8edf-6f4ca5ed5b0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078563262 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_random.3078563262 |
| Directory | /workspace/85.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random.3158463530 |
| Short name | T1993 |
| Test name | |
| Test status | |
| Simulation time | 1353646425 ps |
| CPU time | 40.73 seconds |
| Started | Jul 31 08:02:42 PM PDT 24 |
| Finished | Jul 31 08:03:22 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-7a395676-9e2c-48e6-a08b-2726a45ab689 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158463530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random.3158463530 |
| Directory | /workspace/85.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_large_delays.769425675 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 59934425856 ps |
| CPU time | 645.11 seconds |
| Started | Jul 31 08:02:51 PM PDT 24 |
| Finished | Jul 31 08:13:36 PM PDT 24 |
| Peak memory | 576060 kb |
| Host | smart-d3153721-bdba-4391-9ce9-0b05234f8b11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769425675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_large_delays.769425675 |
| Directory | /workspace/85.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_slow_rsp.1211908955 |
| Short name | T2407 |
| Test name | |
| Test status | |
| Simulation time | 25548694772 ps |
| CPU time | 449.21 seconds |
| Started | Jul 31 08:02:48 PM PDT 24 |
| Finished | Jul 31 08:10:18 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-7415554e-ccdc-48ab-baf8-3fafef4e9d9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211908955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_slow_rsp.1211908955 |
| Directory | /workspace/85.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_zero_delays.4057894654 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 118196935 ps |
| CPU time | 12.62 seconds |
| Started | Jul 31 08:02:54 PM PDT 24 |
| Finished | Jul 31 08:03:07 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-249b92f0-cfa9-4ae7-9232-51a0b3905a3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057894654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_zero_del ays.4057894654 |
| Directory | /workspace/85.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_same_source.1350665979 |
| Short name | T2389 |
| Test name | |
| Test status | |
| Simulation time | 207834266 ps |
| CPU time | 18.27 seconds |
| Started | Jul 31 08:02:49 PM PDT 24 |
| Finished | Jul 31 08:03:07 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-b32d68b4-ccd0-4f46-8183-212d193de4cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350665979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_same_source.1350665979 |
| Directory | /workspace/85.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke.651772951 |
| Short name | T2386 |
| Test name | |
| Test status | |
| Simulation time | 202258980 ps |
| CPU time | 9.35 seconds |
| Started | Jul 31 08:02:50 PM PDT 24 |
| Finished | Jul 31 08:03:00 PM PDT 24 |
| Peak memory | 573784 kb |
| Host | smart-42192394-be72-491e-b947-354ed0d4faa0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651772951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke.651772951 |
| Directory | /workspace/85.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.3722380449 |
| Short name | T1716 |
| Test name | |
| Test status | |
| Simulation time | 8132496099 ps |
| CPU time | 91 seconds |
| Started | Jul 31 08:02:42 PM PDT 24 |
| Finished | Jul 31 08:04:13 PM PDT 24 |
| Peak memory | 574580 kb |
| Host | smart-0df4902e-7314-4174-bcde-9b81c5f2568c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722380449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_large_delays.3722380449 |
| Directory | /workspace/85.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.2121587860 |
| Short name | T2013 |
| Test name | |
| Test status | |
| Simulation time | 5176409641 ps |
| CPU time | 89.72 seconds |
| Started | Jul 31 08:02:43 PM PDT 24 |
| Finished | Jul 31 08:04:13 PM PDT 24 |
| Peak memory | 573884 kb |
| Host | smart-aa489316-3654-49f3-9b27-e62f24457a90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121587860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_slow_rsp.2121587860 |
| Directory | /workspace/85.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_zero_delays.625843030 |
| Short name | T1556 |
| Test name | |
| Test status | |
| Simulation time | 45108947 ps |
| CPU time | 5.6 seconds |
| Started | Jul 31 08:02:41 PM PDT 24 |
| Finished | Jul 31 08:02:47 PM PDT 24 |
| Peak memory | 573820 kb |
| Host | smart-cd901ad0-07ab-4495-87e7-83356ed55ef9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625843030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_zero_delays .625843030 |
| Directory | /workspace/85.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all.3448422846 |
| Short name | T1941 |
| Test name | |
| Test status | |
| Simulation time | 5679377759 ps |
| CPU time | 209.28 seconds |
| Started | Jul 31 08:02:52 PM PDT 24 |
| Finished | Jul 31 08:06:21 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-6f84d7aa-62ce-4bfe-8005-4e5b348c4c6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448422846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all.3448422846 |
| Directory | /workspace/85.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.808296753 |
| Short name | T1501 |
| Test name | |
| Test status | |
| Simulation time | 5790157753 ps |
| CPU time | 198.03 seconds |
| Started | Jul 31 08:02:49 PM PDT 24 |
| Finished | Jul 31 08:06:07 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-a424be89-d517-456b-8a52-65fd2a5ac7e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808296753 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_error.808296753 |
| Directory | /workspace/85.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.607326797 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 1476118023 ps |
| CPU time | 148.1 seconds |
| Started | Jul 31 08:02:51 PM PDT 24 |
| Finished | Jul 31 08:05:20 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-b4ee78e8-5d5d-4283-a0fe-09150640caa3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607326797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_ with_rand_reset.607326797 |
| Directory | /workspace/85.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.2568329768 |
| Short name | T1672 |
| Test name | |
| Test status | |
| Simulation time | 43183273 ps |
| CPU time | 9.74 seconds |
| Started | Jul 31 08:02:50 PM PDT 24 |
| Finished | Jul 31 08:03:00 PM PDT 24 |
| Peak memory | 574044 kb |
| Host | smart-a1d10526-6864-4546-aa1a-b81e70d99e44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568329768 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_al l_with_reset_error.2568329768 |
| Directory | /workspace/85.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_unmapped_addr.167828889 |
| Short name | T2131 |
| Test name | |
| Test status | |
| Simulation time | 1361275870 ps |
| CPU time | 50.37 seconds |
| Started | Jul 31 08:02:53 PM PDT 24 |
| Finished | Jul 31 08:03:43 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-905245e5-74bc-4656-a37d-dc95f167867f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167828889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_unmapped_addr.167828889 |
| Directory | /workspace/85.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device.632442489 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 1865809673 ps |
| CPU time | 75.79 seconds |
| Started | Jul 31 08:02:57 PM PDT 24 |
| Finished | Jul 31 08:04:13 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-98527705-96bc-4720-9cb0-1b72df96c3d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632442489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device. 632442489 |
| Directory | /workspace/86.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.340858393 |
| Short name | T2063 |
| Test name | |
| Test status | |
| Simulation time | 124165877750 ps |
| CPU time | 2393.49 seconds |
| Started | Jul 31 08:03:00 PM PDT 24 |
| Finished | Jul 31 08:42:54 PM PDT 24 |
| Peak memory | 576072 kb |
| Host | smart-25b34c54-d7a2-41c7-9daf-a9ba52506d27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340858393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_d evice_slow_rsp.340858393 |
| Directory | /workspace/86.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.3226943811 |
| Short name | T1561 |
| Test name | |
| Test status | |
| Simulation time | 877172596 ps |
| CPU time | 31.09 seconds |
| Started | Jul 31 08:04:28 PM PDT 24 |
| Finished | Jul 31 08:04:59 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-6f6fe0c1-cea1-4939-918b-61f6fe2baf5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226943811 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_and_unmapped_add r.3226943811 |
| Directory | /workspace/86.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_random.2858604177 |
| Short name | T1431 |
| Test name | |
| Test status | |
| Simulation time | 32410202 ps |
| CPU time | 5.63 seconds |
| Started | Jul 31 08:02:57 PM PDT 24 |
| Finished | Jul 31 08:03:03 PM PDT 24 |
| Peak memory | 573848 kb |
| Host | smart-0abd1fa9-cb7b-462b-abb2-ffc10fc3e896 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858604177 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_random.2858604177 |
| Directory | /workspace/86.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random.3194328034 |
| Short name | T2168 |
| Test name | |
| Test status | |
| Simulation time | 162608052 ps |
| CPU time | 16.1 seconds |
| Started | Jul 31 08:02:57 PM PDT 24 |
| Finished | Jul 31 08:03:14 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-d97c05f1-2477-47a9-a7c1-2e8b4f696645 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194328034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random.3194328034 |
| Directory | /workspace/86.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_large_delays.861584103 |
| Short name | T1920 |
| Test name | |
| Test status | |
| Simulation time | 78334283624 ps |
| CPU time | 837.11 seconds |
| Started | Jul 31 08:02:55 PM PDT 24 |
| Finished | Jul 31 08:16:52 PM PDT 24 |
| Peak memory | 576048 kb |
| Host | smart-681a74ff-bd0d-43c2-8234-a398d96bebf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861584103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_large_delays.861584103 |
| Directory | /workspace/86.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_slow_rsp.370521274 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 64760267735 ps |
| CPU time | 1144.86 seconds |
| Started | Jul 31 08:02:58 PM PDT 24 |
| Finished | Jul 31 08:22:03 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-8b2bb869-d055-4423-acf1-ea5ca14e217a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370521274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_slow_rsp.370521274 |
| Directory | /workspace/86.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.3584627720 |
| Short name | T1546 |
| Test name | |
| Test status | |
| Simulation time | 83236871 ps |
| CPU time | 10.2 seconds |
| Started | Jul 31 08:02:56 PM PDT 24 |
| Finished | Jul 31 08:03:06 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-1d050642-bd37-4089-977d-ea3437549e21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584627720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_zero_del ays.3584627720 |
| Directory | /workspace/86.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_same_source.3594791620 |
| Short name | T2004 |
| Test name | |
| Test status | |
| Simulation time | 2536775951 ps |
| CPU time | 78.06 seconds |
| Started | Jul 31 08:02:57 PM PDT 24 |
| Finished | Jul 31 08:04:16 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-a6cc1fc4-57f3-44da-a94b-33b671d681ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594791620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_same_source.3594791620 |
| Directory | /workspace/86.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke.673499295 |
| Short name | T2737 |
| Test name | |
| Test status | |
| Simulation time | 51520419 ps |
| CPU time | 6.39 seconds |
| Started | Jul 31 08:02:52 PM PDT 24 |
| Finished | Jul 31 08:02:59 PM PDT 24 |
| Peak memory | 573860 kb |
| Host | smart-a02c7529-bab9-4964-8503-2da4e6c68e05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673499295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke.673499295 |
| Directory | /workspace/86.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_large_delays.3004639849 |
| Short name | T1482 |
| Test name | |
| Test status | |
| Simulation time | 8469979595 ps |
| CPU time | 85.45 seconds |
| Started | Jul 31 08:02:51 PM PDT 24 |
| Finished | Jul 31 08:04:16 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-392d9c97-bb13-46ab-b7a7-159ad7d48091 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004639849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_large_delays.3004639849 |
| Directory | /workspace/86.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.3510153536 |
| Short name | T1605 |
| Test name | |
| Test status | |
| Simulation time | 5535462215 ps |
| CPU time | 93.94 seconds |
| Started | Jul 31 08:02:58 PM PDT 24 |
| Finished | Jul 31 08:04:32 PM PDT 24 |
| Peak memory | 573912 kb |
| Host | smart-8c8c3722-c1cf-4054-a5f9-f7f47b651cf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510153536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_slow_rsp.3510153536 |
| Directory | /workspace/86.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_zero_delays.631501731 |
| Short name | T1744 |
| Test name | |
| Test status | |
| Simulation time | 42094891 ps |
| CPU time | 6.03 seconds |
| Started | Jul 31 08:02:51 PM PDT 24 |
| Finished | Jul 31 08:02:57 PM PDT 24 |
| Peak memory | 573812 kb |
| Host | smart-87219986-7576-4929-9976-c0c777210980 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631501731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_zero_delays .631501731 |
| Directory | /workspace/86.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all.1042513534 |
| Short name | T2585 |
| Test name | |
| Test status | |
| Simulation time | 8039673411 ps |
| CPU time | 279.47 seconds |
| Started | Jul 31 08:02:57 PM PDT 24 |
| Finished | Jul 31 08:07:36 PM PDT 24 |
| Peak memory | 576040 kb |
| Host | smart-f272be58-7cd6-4563-89ac-77b293563a5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042513534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all.1042513534 |
| Directory | /workspace/86.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.419019737 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 20252869298 ps |
| CPU time | 818.47 seconds |
| Started | Jul 31 08:02:58 PM PDT 24 |
| Finished | Jul 31 08:16:37 PM PDT 24 |
| Peak memory | 576808 kb |
| Host | smart-ff2ff81a-8f27-480a-b2cf-104eeb0f8197 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419019737 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_error.419019737 |
| Directory | /workspace/86.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.2894535897 |
| Short name | T2827 |
| Test name | |
| Test status | |
| Simulation time | 3610454829 ps |
| CPU time | 361.07 seconds |
| Started | Jul 31 08:02:59 PM PDT 24 |
| Finished | Jul 31 08:09:01 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-16bfcafa-37e0-47b8-b5fa-b66dc3fea3bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894535897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all _with_rand_reset.2894535897 |
| Directory | /workspace/86.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.1154801966 |
| Short name | T2224 |
| Test name | |
| Test status | |
| Simulation time | 6033542277 ps |
| CPU time | 431.76 seconds |
| Started | Jul 31 08:02:59 PM PDT 24 |
| Finished | Jul 31 08:10:11 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-6f879ab1-18b3-4911-816f-eebe07d92433 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154801966 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_al l_with_reset_error.1154801966 |
| Directory | /workspace/86.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_unmapped_addr.4044400950 |
| Short name | T2589 |
| Test name | |
| Test status | |
| Simulation time | 111362255 ps |
| CPU time | 14.36 seconds |
| Started | Jul 31 08:04:22 PM PDT 24 |
| Finished | Jul 31 08:04:36 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-d45babf2-f3e7-4907-a734-3fb9e42a893e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044400950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_unmapped_addr.4044400950 |
| Directory | /workspace/86.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device.2867005083 |
| Short name | T2684 |
| Test name | |
| Test status | |
| Simulation time | 155279919 ps |
| CPU time | 10.55 seconds |
| Started | Jul 31 08:03:03 PM PDT 24 |
| Finished | Jul 31 08:03:13 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-ec8470e7-2b2a-4611-b4be-c33e1ae38b05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867005083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device .2867005083 |
| Directory | /workspace/87.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.1599567648 |
| Short name | T2743 |
| Test name | |
| Test status | |
| Simulation time | 118905499287 ps |
| CPU time | 2407.21 seconds |
| Started | Jul 31 08:03:06 PM PDT 24 |
| Finished | Jul 31 08:43:14 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-f59c594e-4c8c-40d7-8a95-71a7be771a9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599567648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_ device_slow_rsp.1599567648 |
| Directory | /workspace/87.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.1847862902 |
| Short name | T1415 |
| Test name | |
| Test status | |
| Simulation time | 870307255 ps |
| CPU time | 33.88 seconds |
| Started | Jul 31 08:03:04 PM PDT 24 |
| Finished | Jul 31 08:03:38 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-5f984218-9cb2-44f3-8008-748b93991b92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847862902 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_and_unmapped_add r.1847862902 |
| Directory | /workspace/87.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_random.3537850306 |
| Short name | T2699 |
| Test name | |
| Test status | |
| Simulation time | 1769562010 ps |
| CPU time | 59.87 seconds |
| Started | Jul 31 08:03:04 PM PDT 24 |
| Finished | Jul 31 08:04:04 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-b4699e3d-5c4e-461f-bc40-c6f18e8d0316 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537850306 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_random.3537850306 |
| Directory | /workspace/87.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random.2459455183 |
| Short name | T2800 |
| Test name | |
| Test status | |
| Simulation time | 264506041 ps |
| CPU time | 21.27 seconds |
| Started | Jul 31 08:03:03 PM PDT 24 |
| Finished | Jul 31 08:03:25 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-21df491c-d4f1-40f1-aec9-f330498b69b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459455183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random.2459455183 |
| Directory | /workspace/87.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_large_delays.1816208574 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 49304976258 ps |
| CPU time | 563.68 seconds |
| Started | Jul 31 08:03:04 PM PDT 24 |
| Finished | Jul 31 08:12:28 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-cdcd9fa2-30b3-40c0-9016-e86ff4fc9849 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816208574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_large_delays.1816208574 |
| Directory | /workspace/87.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_slow_rsp.3236851630 |
| Short name | T2267 |
| Test name | |
| Test status | |
| Simulation time | 25019026829 ps |
| CPU time | 386.67 seconds |
| Started | Jul 31 08:03:06 PM PDT 24 |
| Finished | Jul 31 08:09:33 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-2881b50f-4df3-4d03-a2f3-6cbd062a475d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236851630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_slow_rsp.3236851630 |
| Directory | /workspace/87.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_zero_delays.2660461466 |
| Short name | T2615 |
| Test name | |
| Test status | |
| Simulation time | 137746072 ps |
| CPU time | 15.72 seconds |
| Started | Jul 31 08:03:05 PM PDT 24 |
| Finished | Jul 31 08:03:20 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-a8f44cff-7696-4b8c-8be8-f12468bea426 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660461466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_zero_del ays.2660461466 |
| Directory | /workspace/87.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_same_source.4086003170 |
| Short name | T2757 |
| Test name | |
| Test status | |
| Simulation time | 578060704 ps |
| CPU time | 40.61 seconds |
| Started | Jul 31 08:03:08 PM PDT 24 |
| Finished | Jul 31 08:03:49 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-f06a7cdf-a29d-4358-8c5e-ee706c23dc39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086003170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_same_source.4086003170 |
| Directory | /workspace/87.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke.2954210205 |
| Short name | T1684 |
| Test name | |
| Test status | |
| Simulation time | 46270440 ps |
| CPU time | 6.25 seconds |
| Started | Jul 31 08:03:00 PM PDT 24 |
| Finished | Jul 31 08:03:06 PM PDT 24 |
| Peak memory | 574492 kb |
| Host | smart-fe6e7457-16ac-408f-80b3-4c733021a119 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954210205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke.2954210205 |
| Directory | /workspace/87.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_large_delays.1291669819 |
| Short name | T1565 |
| Test name | |
| Test status | |
| Simulation time | 7339377625 ps |
| CPU time | 74.71 seconds |
| Started | Jul 31 08:02:57 PM PDT 24 |
| Finished | Jul 31 08:04:12 PM PDT 24 |
| Peak memory | 573944 kb |
| Host | smart-b2f9fc97-8d1f-4623-909d-c187f74fa1b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291669819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_large_delays.1291669819 |
| Directory | /workspace/87.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.1363095246 |
| Short name | T1442 |
| Test name | |
| Test status | |
| Simulation time | 4754970005 ps |
| CPU time | 72.88 seconds |
| Started | Jul 31 08:04:22 PM PDT 24 |
| Finished | Jul 31 08:05:35 PM PDT 24 |
| Peak memory | 573696 kb |
| Host | smart-aa54b3fa-8f42-428f-8074-4661045b644a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363095246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_slow_rsp.1363095246 |
| Directory | /workspace/87.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_zero_delays.3993940933 |
| Short name | T1829 |
| Test name | |
| Test status | |
| Simulation time | 51390511 ps |
| CPU time | 6.38 seconds |
| Started | Jul 31 08:02:59 PM PDT 24 |
| Finished | Jul 31 08:03:05 PM PDT 24 |
| Peak memory | 573764 kb |
| Host | smart-54499897-4da6-418a-92dc-9d433ac4fb40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993940933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_zero_delay s.3993940933 |
| Directory | /workspace/87.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all.3278655209 |
| Short name | T2077 |
| Test name | |
| Test status | |
| Simulation time | 7123323779 ps |
| CPU time | 256.23 seconds |
| Started | Jul 31 08:03:07 PM PDT 24 |
| Finished | Jul 31 08:07:23 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-607997ef-b40c-4e48-94e4-509b3e1603e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278655209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all.3278655209 |
| Directory | /workspace/87.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_error.2279088910 |
| Short name | T2542 |
| Test name | |
| Test status | |
| Simulation time | 11651745631 ps |
| CPU time | 430.08 seconds |
| Started | Jul 31 08:03:06 PM PDT 24 |
| Finished | Jul 31 08:10:17 PM PDT 24 |
| Peak memory | 576728 kb |
| Host | smart-151620cc-c184-4ec3-b8f5-160f7eb68bdb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279088910 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_error.2279088910 |
| Directory | /workspace/87.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.190684965 |
| Short name | T2903 |
| Test name | |
| Test status | |
| Simulation time | 1734660979 ps |
| CPU time | 451.05 seconds |
| Started | Jul 31 08:03:06 PM PDT 24 |
| Finished | Jul 31 08:10:38 PM PDT 24 |
| Peak memory | 576740 kb |
| Host | smart-2e27c8f8-ecfc-44e4-bfed-a3d5ee16f612 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190684965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_ with_rand_reset.190684965 |
| Directory | /workspace/87.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.1909381647 |
| Short name | T1965 |
| Test name | |
| Test status | |
| Simulation time | 29278254 ps |
| CPU time | 19.28 seconds |
| Started | Jul 31 08:03:10 PM PDT 24 |
| Finished | Jul 31 08:03:30 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-bc6da849-fd28-48d3-93c2-2fca3326a89f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909381647 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_al l_with_reset_error.1909381647 |
| Directory | /workspace/87.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_unmapped_addr.499847928 |
| Short name | T2338 |
| Test name | |
| Test status | |
| Simulation time | 773533614 ps |
| CPU time | 30.86 seconds |
| Started | Jul 31 08:03:06 PM PDT 24 |
| Finished | Jul 31 08:03:37 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-35e48448-902c-4736-ab8e-e70953bf92f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499847928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_unmapped_addr.499847928 |
| Directory | /workspace/87.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device.1999854894 |
| Short name | T2115 |
| Test name | |
| Test status | |
| Simulation time | 77837126 ps |
| CPU time | 11.37 seconds |
| Started | Jul 31 08:04:22 PM PDT 24 |
| Finished | Jul 31 08:04:33 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-0c275a2a-fe5b-4831-b920-2fd12ed3e5e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999854894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device .1999854894 |
| Directory | /workspace/88.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.1331470964 |
| Short name | T1552 |
| Test name | |
| Test status | |
| Simulation time | 46353952688 ps |
| CPU time | 872.19 seconds |
| Started | Jul 31 08:03:13 PM PDT 24 |
| Finished | Jul 31 08:17:45 PM PDT 24 |
| Peak memory | 576124 kb |
| Host | smart-9c4469f9-fe86-487b-8bfc-4dc1b6b750b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331470964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_ device_slow_rsp.1331470964 |
| Directory | /workspace/88.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.736505174 |
| Short name | T2146 |
| Test name | |
| Test status | |
| Simulation time | 245054963 ps |
| CPU time | 26.27 seconds |
| Started | Jul 31 08:03:12 PM PDT 24 |
| Finished | Jul 31 08:03:38 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-baf9a40f-21f2-4b73-9e01-22717282a28d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736505174 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_and_unmapped_addr .736505174 |
| Directory | /workspace/88.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random.2426204973 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 529140762 ps |
| CPU time | 21.43 seconds |
| Started | Jul 31 08:03:10 PM PDT 24 |
| Finished | Jul 31 08:03:32 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-72c8649c-7edb-4051-a928-cd13edd6bebd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426204973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random.2426204973 |
| Directory | /workspace/88.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_large_delays.1682423505 |
| Short name | T1737 |
| Test name | |
| Test status | |
| Simulation time | 95908884961 ps |
| CPU time | 1142.58 seconds |
| Started | Jul 31 08:03:11 PM PDT 24 |
| Finished | Jul 31 08:22:14 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-c0095ca5-b8e8-4b9c-8123-b13b082494cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682423505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_large_delays.1682423505 |
| Directory | /workspace/88.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.462573827 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 40628888303 ps |
| CPU time | 703.44 seconds |
| Started | Jul 31 08:03:12 PM PDT 24 |
| Finished | Jul 31 08:14:55 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-0e96db14-2fa3-4af2-889d-9466da752263 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462573827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_slow_rsp.462573827 |
| Directory | /workspace/88.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_zero_delays.1444045973 |
| Short name | T2872 |
| Test name | |
| Test status | |
| Simulation time | 441435237 ps |
| CPU time | 36.46 seconds |
| Started | Jul 31 08:03:10 PM PDT 24 |
| Finished | Jul 31 08:03:47 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-eb860f19-ea20-40f2-b941-9514cf510acd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444045973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_zero_del ays.1444045973 |
| Directory | /workspace/88.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_same_source.1279328420 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 2123983889 ps |
| CPU time | 70.53 seconds |
| Started | Jul 31 08:03:11 PM PDT 24 |
| Finished | Jul 31 08:04:21 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-0e5f971b-c77d-4aad-b2fe-71a425788589 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279328420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_same_source.1279328420 |
| Directory | /workspace/88.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke.1691695430 |
| Short name | T2206 |
| Test name | |
| Test status | |
| Simulation time | 249862020 ps |
| CPU time | 9.82 seconds |
| Started | Jul 31 08:03:13 PM PDT 24 |
| Finished | Jul 31 08:03:23 PM PDT 24 |
| Peak memory | 573824 kb |
| Host | smart-5b0d1ab5-1165-4bde-b6b1-d2bc5a2bfb5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691695430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke.1691695430 |
| Directory | /workspace/88.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.632853972 |
| Short name | T1524 |
| Test name | |
| Test status | |
| Simulation time | 9951772749 ps |
| CPU time | 101.46 seconds |
| Started | Jul 31 08:03:09 PM PDT 24 |
| Finished | Jul 31 08:04:50 PM PDT 24 |
| Peak memory | 574584 kb |
| Host | smart-827e1dc3-5c1e-4c9f-87d7-4f848d57504d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632853972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_large_delays.632853972 |
| Directory | /workspace/88.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.3755216494 |
| Short name | T1606 |
| Test name | |
| Test status | |
| Simulation time | 5674010635 ps |
| CPU time | 87.14 seconds |
| Started | Jul 31 08:03:10 PM PDT 24 |
| Finished | Jul 31 08:04:38 PM PDT 24 |
| Peak memory | 574012 kb |
| Host | smart-3ff328fa-5c6b-46dc-90fe-e647354e622c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755216494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_slow_rsp.3755216494 |
| Directory | /workspace/88.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_zero_delays.4191102970 |
| Short name | T2559 |
| Test name | |
| Test status | |
| Simulation time | 40849109 ps |
| CPU time | 5.85 seconds |
| Started | Jul 31 08:03:10 PM PDT 24 |
| Finished | Jul 31 08:03:16 PM PDT 24 |
| Peak memory | 573736 kb |
| Host | smart-10c59694-1a15-4919-b773-1a5ea1887f9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191102970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_zero_delay s.4191102970 |
| Directory | /workspace/88.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all.3499561555 |
| Short name | T2330 |
| Test name | |
| Test status | |
| Simulation time | 15123089530 ps |
| CPU time | 618.4 seconds |
| Started | Jul 31 08:03:11 PM PDT 24 |
| Finished | Jul 31 08:13:30 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-3ec3fb4e-3c67-494f-a0cb-71ac560534e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499561555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all.3499561555 |
| Directory | /workspace/88.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.3314986428 |
| Short name | T1582 |
| Test name | |
| Test status | |
| Simulation time | 3704002813 ps |
| CPU time | 123.52 seconds |
| Started | Jul 31 08:04:22 PM PDT 24 |
| Finished | Jul 31 08:06:26 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-0cf197e0-334e-456c-b0db-acd503724175 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314986428 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_error.3314986428 |
| Directory | /workspace/88.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.1860029485 |
| Short name | T2529 |
| Test name | |
| Test status | |
| Simulation time | 271921560 ps |
| CPU time | 93.76 seconds |
| Started | Jul 31 08:03:09 PM PDT 24 |
| Finished | Jul 31 08:04:43 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-777f8f7b-30c3-494b-bcd5-15de73bce922 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860029485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all _with_rand_reset.1860029485 |
| Directory | /workspace/88.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.3237307366 |
| Short name | T1975 |
| Test name | |
| Test status | |
| Simulation time | 334846355 ps |
| CPU time | 123.68 seconds |
| Started | Jul 31 08:03:29 PM PDT 24 |
| Finished | Jul 31 08:05:33 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-da2fc4ee-7240-4bf7-990e-142c5b8f7dd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237307366 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_al l_with_reset_error.3237307366 |
| Directory | /workspace/88.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_unmapped_addr.3127341212 |
| Short name | T1868 |
| Test name | |
| Test status | |
| Simulation time | 644648158 ps |
| CPU time | 30.65 seconds |
| Started | Jul 31 08:03:09 PM PDT 24 |
| Finished | Jul 31 08:03:40 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-0c401c6b-fc8b-472d-8e62-7f768d4272a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127341212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_unmapped_addr.3127341212 |
| Directory | /workspace/88.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device.564334542 |
| Short name | T1784 |
| Test name | |
| Test status | |
| Simulation time | 351244882 ps |
| CPU time | 27.08 seconds |
| Started | Jul 31 08:03:25 PM PDT 24 |
| Finished | Jul 31 08:03:52 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-fd93c013-3c1b-4b0e-9332-20ccd17069ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564334542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device. 564334542 |
| Directory | /workspace/89.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.1418413049 |
| Short name | T1931 |
| Test name | |
| Test status | |
| Simulation time | 4509825562 ps |
| CPU time | 69.38 seconds |
| Started | Jul 31 08:03:24 PM PDT 24 |
| Finished | Jul 31 08:04:33 PM PDT 24 |
| Peak memory | 573924 kb |
| Host | smart-12a00af0-9407-4857-b780-636045044681 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418413049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_ device_slow_rsp.1418413049 |
| Directory | /workspace/89.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.139660970 |
| Short name | T2381 |
| Test name | |
| Test status | |
| Simulation time | 874690966 ps |
| CPU time | 34.76 seconds |
| Started | Jul 31 08:03:24 PM PDT 24 |
| Finished | Jul 31 08:03:59 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-6eaf628e-ce40-433a-9483-47f93760d4bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139660970 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_and_unmapped_addr .139660970 |
| Directory | /workspace/89.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_random.1785033458 |
| Short name | T2060 |
| Test name | |
| Test status | |
| Simulation time | 2582562872 ps |
| CPU time | 91.26 seconds |
| Started | Jul 31 08:03:29 PM PDT 24 |
| Finished | Jul 31 08:05:00 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-1384a64a-2841-42ca-ab5e-2e8a277934a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785033458 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_random.1785033458 |
| Directory | /workspace/89.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random.1591279640 |
| Short name | T2006 |
| Test name | |
| Test status | |
| Simulation time | 122274092 ps |
| CPU time | 12.19 seconds |
| Started | Jul 31 08:03:25 PM PDT 24 |
| Finished | Jul 31 08:03:37 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-c03dde63-84a0-4c39-99dc-5a63312f9c8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591279640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random.1591279640 |
| Directory | /workspace/89.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_large_delays.3742722636 |
| Short name | T1414 |
| Test name | |
| Test status | |
| Simulation time | 103056005259 ps |
| CPU time | 1037.89 seconds |
| Started | Jul 31 08:03:24 PM PDT 24 |
| Finished | Jul 31 08:20:42 PM PDT 24 |
| Peak memory | 576084 kb |
| Host | smart-a4f14c17-1734-4190-a1ad-d93752a45114 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742722636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_large_delays.3742722636 |
| Directory | /workspace/89.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_slow_rsp.2939060600 |
| Short name | T1702 |
| Test name | |
| Test status | |
| Simulation time | 41990692433 ps |
| CPU time | 759.11 seconds |
| Started | Jul 31 08:03:29 PM PDT 24 |
| Finished | Jul 31 08:16:08 PM PDT 24 |
| Peak memory | 576040 kb |
| Host | smart-8ded6f30-a662-4df9-8c2e-e9a3124f9cd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939060600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_slow_rsp.2939060600 |
| Directory | /workspace/89.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_zero_delays.3580822584 |
| Short name | T1870 |
| Test name | |
| Test status | |
| Simulation time | 130009573 ps |
| CPU time | 13.23 seconds |
| Started | Jul 31 08:03:24 PM PDT 24 |
| Finished | Jul 31 08:03:37 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-e5359350-0836-4e0c-a952-afae7ad41700 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580822584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_zero_del ays.3580822584 |
| Directory | /workspace/89.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_same_source.1713893167 |
| Short name | T1652 |
| Test name | |
| Test status | |
| Simulation time | 217043915 ps |
| CPU time | 8.86 seconds |
| Started | Jul 31 08:03:25 PM PDT 24 |
| Finished | Jul 31 08:03:34 PM PDT 24 |
| Peak memory | 573816 kb |
| Host | smart-6c0322e9-aef7-4642-a4d1-c250348cbb33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713893167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_same_source.1713893167 |
| Directory | /workspace/89.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke.2186846728 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 164429307 ps |
| CPU time | 7.91 seconds |
| Started | Jul 31 08:03:25 PM PDT 24 |
| Finished | Jul 31 08:03:33 PM PDT 24 |
| Peak memory | 573752 kb |
| Host | smart-8d757451-af02-4b36-a64e-f1a4b66106e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186846728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke.2186846728 |
| Directory | /workspace/89.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_large_delays.1420585104 |
| Short name | T1700 |
| Test name | |
| Test status | |
| Simulation time | 8640499613 ps |
| CPU time | 89.91 seconds |
| Started | Jul 31 08:03:25 PM PDT 24 |
| Finished | Jul 31 08:04:55 PM PDT 24 |
| Peak memory | 573788 kb |
| Host | smart-17dcf2a6-7552-4fa9-a3d1-00403900e352 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420585104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_large_delays.1420585104 |
| Directory | /workspace/89.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.4168507444 |
| Short name | T2530 |
| Test name | |
| Test status | |
| Simulation time | 4809967303 ps |
| CPU time | 77.29 seconds |
| Started | Jul 31 08:03:27 PM PDT 24 |
| Finished | Jul 31 08:04:45 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-c7295c58-6960-4820-b830-2f1d7782772e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168507444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_slow_rsp.4168507444 |
| Directory | /workspace/89.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.4140002441 |
| Short name | T1647 |
| Test name | |
| Test status | |
| Simulation time | 43043004 ps |
| CPU time | 5.93 seconds |
| Started | Jul 31 08:03:24 PM PDT 24 |
| Finished | Jul 31 08:03:30 PM PDT 24 |
| Peak memory | 573732 kb |
| Host | smart-ece39fa8-39dc-41da-90df-e2cef018b831 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140002441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_zero_delay s.4140002441 |
| Directory | /workspace/89.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all.3438783358 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 3002634376 ps |
| CPU time | 253.54 seconds |
| Started | Jul 31 08:03:23 PM PDT 24 |
| Finished | Jul 31 08:07:37 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-5c3a31a8-41c1-43d6-8307-d815571f21d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438783358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all.3438783358 |
| Directory | /workspace/89.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.3961237192 |
| Short name | T1526 |
| Test name | |
| Test status | |
| Simulation time | 1423969327 ps |
| CPU time | 91.9 seconds |
| Started | Jul 31 08:03:23 PM PDT 24 |
| Finished | Jul 31 08:04:55 PM PDT 24 |
| Peak memory | 576088 kb |
| Host | smart-74eb4916-bd78-4253-80c9-dd48afc187e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961237192 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_error.3961237192 |
| Directory | /workspace/89.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.913139673 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 358527539 ps |
| CPU time | 115.75 seconds |
| Started | Jul 31 08:03:25 PM PDT 24 |
| Finished | Jul 31 08:05:21 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-91524c1d-214e-4298-8aed-73c7c585b09b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913139673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_ with_rand_reset.913139673 |
| Directory | /workspace/89.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.961614352 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 13113859848 ps |
| CPU time | 587.07 seconds |
| Started | Jul 31 08:03:23 PM PDT 24 |
| Finished | Jul 31 08:13:10 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-c5b72b27-d0cb-4d49-b4b0-e39fa32e525d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961614352 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all _with_reset_error.961614352 |
| Directory | /workspace/89.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.1738055814 |
| Short name | T2365 |
| Test name | |
| Test status | |
| Simulation time | 333349261 ps |
| CPU time | 40.61 seconds |
| Started | Jul 31 08:03:25 PM PDT 24 |
| Finished | Jul 31 08:04:06 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-b5471c30-2c13-4a45-9210-1c743418b50e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738055814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_unmapped_addr.1738055814 |
| Directory | /workspace/89.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_csr_rw.2343773449 |
| Short name | T2449 |
| Test name | |
| Test status | |
| Simulation time | 5802920364 ps |
| CPU time | 603.59 seconds |
| Started | Jul 31 07:48:04 PM PDT 24 |
| Finished | Jul 31 07:58:08 PM PDT 24 |
| Peak memory | 597664 kb |
| Host | smart-f608f361-439a-4d68-99f1-aae549922e24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343773449 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_rw.2343773449 |
| Directory | /workspace/9.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.2061546692 |
| Short name | T2392 |
| Test name | |
| Test status | |
| Simulation time | 33055736771 ps |
| CPU time | 4669.17 seconds |
| Started | Jul 31 07:47:42 PM PDT 24 |
| Finished | Jul 31 09:05:32 PM PDT 24 |
| Peak memory | 593536 kb |
| Host | smart-9a1b19f4-97b8-4ee0-a87e-0a4c28d3bca7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061546692 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 9.chip_same_csr_outstanding.2061546692 |
| Directory | /workspace/9.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_tl_errors.3247122890 |
| Short name | T2811 |
| Test name | |
| Test status | |
| Simulation time | 3686003330 ps |
| CPU time | 224.33 seconds |
| Started | Jul 31 07:47:45 PM PDT 24 |
| Finished | Jul 31 07:51:29 PM PDT 24 |
| Peak memory | 598652 kb |
| Host | smart-4ed7657c-c4dc-489a-920e-1860b8e19642 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247122890 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_tl_errors.3247122890 |
| Directory | /workspace/9.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device.4153367523 |
| Short name | T1901 |
| Test name | |
| Test status | |
| Simulation time | 116336466 ps |
| CPU time | 12.69 seconds |
| Started | Jul 31 07:47:56 PM PDT 24 |
| Finished | Jul 31 07:48:08 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-6a50c9b7-6822-42d6-a9fa-3c3c204d8a86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153367523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device. 4153367523 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.662834608 |
| Short name | T1670 |
| Test name | |
| Test status | |
| Simulation time | 24087613839 ps |
| CPU time | 402.27 seconds |
| Started | Jul 31 07:47:58 PM PDT 24 |
| Finished | Jul 31 07:54:40 PM PDT 24 |
| Peak memory | 576024 kb |
| Host | smart-dc847f9d-5c4f-4c8c-9c3e-c9d77678a28a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662834608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_de vice_slow_rsp.662834608 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.2433473365 |
| Short name | T1853 |
| Test name | |
| Test status | |
| Simulation time | 879556752 ps |
| CPU time | 31.89 seconds |
| Started | Jul 31 07:47:59 PM PDT 24 |
| Finished | Jul 31 07:48:31 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-a7fb6aa9-8a52-4254-bb9b-411d7a4452d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433473365 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr .2433473365 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_random.1127649809 |
| Short name | T2351 |
| Test name | |
| Test status | |
| Simulation time | 761571442 ps |
| CPU time | 24.19 seconds |
| Started | Jul 31 07:47:57 PM PDT 24 |
| Finished | Jul 31 07:48:22 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-80d9817e-c9ba-48fb-85db-c3f3b4fb240a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127649809 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.1127649809 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random.505541099 |
| Short name | T2670 |
| Test name | |
| Test status | |
| Simulation time | 241884118 ps |
| CPU time | 11.64 seconds |
| Started | Jul 31 07:47:52 PM PDT 24 |
| Finished | Jul 31 07:48:03 PM PDT 24 |
| Peak memory | 574480 kb |
| Host | smart-8b46bcc8-098f-49ec-b5d3-fbb5bec85469 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505541099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random.505541099 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_large_delays.2776826161 |
| Short name | T2897 |
| Test name | |
| Test status | |
| Simulation time | 91862480152 ps |
| CPU time | 942.25 seconds |
| Started | Jul 31 07:47:52 PM PDT 24 |
| Finished | Jul 31 08:03:35 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-a065aecf-bd31-4486-a93c-d852d4fd51b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776826161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.2776826161 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_slow_rsp.1112612740 |
| Short name | T2562 |
| Test name | |
| Test status | |
| Simulation time | 18837582139 ps |
| CPU time | 307.45 seconds |
| Started | Jul 31 07:47:48 PM PDT 24 |
| Finished | Jul 31 07:52:56 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-7bcfb368-a713-4943-ace2-162d7ef4fe21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112612740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.1112612740 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_zero_delays.1715339321 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 493355815 ps |
| CPU time | 38.14 seconds |
| Started | Jul 31 07:47:50 PM PDT 24 |
| Finished | Jul 31 07:48:28 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-72ace745-3a20-4f08-b072-1c27c758bc06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715339321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_dela ys.1715339321 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_same_source.2753187224 |
| Short name | T1796 |
| Test name | |
| Test status | |
| Simulation time | 2595565302 ps |
| CPU time | 80.64 seconds |
| Started | Jul 31 07:47:55 PM PDT 24 |
| Finished | Jul 31 07:49:16 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-9060cc82-f325-43bc-87fb-95351902588f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753187224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.2753187224 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke.2327540280 |
| Short name | T2105 |
| Test name | |
| Test status | |
| Simulation time | 210679073 ps |
| CPU time | 9.54 seconds |
| Started | Jul 31 07:47:52 PM PDT 24 |
| Finished | Jul 31 07:48:02 PM PDT 24 |
| Peak memory | 573852 kb |
| Host | smart-7613caec-9f2d-45da-bb44-eeda3b6d4e62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327540280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.2327540280 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_large_delays.3718985045 |
| Short name | T2544 |
| Test name | |
| Test status | |
| Simulation time | 7303461707 ps |
| CPU time | 74.98 seconds |
| Started | Jul 31 07:47:51 PM PDT 24 |
| Finished | Jul 31 07:49:06 PM PDT 24 |
| Peak memory | 573956 kb |
| Host | smart-2af5214e-7bcd-448f-bdab-65bc71dc4e13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718985045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.3718985045 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.2687565700 |
| Short name | T2087 |
| Test name | |
| Test status | |
| Simulation time | 4768012541 ps |
| CPU time | 76.03 seconds |
| Started | Jul 31 07:47:51 PM PDT 24 |
| Finished | Jul 31 07:49:07 PM PDT 24 |
| Peak memory | 573836 kb |
| Host | smart-f05e1f97-4fe7-4684-8622-f29f980d00bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687565700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.2687565700 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_zero_delays.2050253891 |
| Short name | T1400 |
| Test name | |
| Test status | |
| Simulation time | 59600501 ps |
| CPU time | 7.28 seconds |
| Started | Jul 31 07:47:50 PM PDT 24 |
| Finished | Jul 31 07:47:58 PM PDT 24 |
| Peak memory | 573812 kb |
| Host | smart-fe678d47-9354-44a2-a3dd-d7fd5bc7909c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050253891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays .2050253891 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all.3278888486 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 4925490025 ps |
| CPU time | 216.18 seconds |
| Started | Jul 31 07:47:58 PM PDT 24 |
| Finished | Jul 31 07:51:34 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-21900374-2dbb-4e89-b0df-d1dd3b13207d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278888486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.3278888486 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_error.3868985279 |
| Short name | T2099 |
| Test name | |
| Test status | |
| Simulation time | 10664846414 ps |
| CPU time | 386.92 seconds |
| Started | Jul 31 07:47:56 PM PDT 24 |
| Finished | Jul 31 07:54:23 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-2ae4df23-a0a8-441d-91c5-baa628160bbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868985279 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.3868985279 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.951291081 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 4153793851 ps |
| CPU time | 515.23 seconds |
| Started | Jul 31 07:47:57 PM PDT 24 |
| Finished | Jul 31 07:56:32 PM PDT 24 |
| Peak memory | 576800 kb |
| Host | smart-37ae348b-62b1-433d-8092-172b7256d207 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951291081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_w ith_rand_reset.951291081 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.1681353878 |
| Short name | T2612 |
| Test name | |
| Test status | |
| Simulation time | 7004861187 ps |
| CPU time | 388.54 seconds |
| Started | Jul 31 07:48:03 PM PDT 24 |
| Finished | Jul 31 07:54:31 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-6fee292f-9076-4fc1-981b-1f20b7514ea2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681353878 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all _with_reset_error.1681353878 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.3156652780 |
| Short name | T1530 |
| Test name | |
| Test status | |
| Simulation time | 58005996 ps |
| CPU time | 9.66 seconds |
| Started | Jul 31 07:47:59 PM PDT 24 |
| Finished | Jul 31 07:48:09 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-a0b0d4df-78a8-46da-bd4c-8831afbcac38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156652780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.3156652780 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device.2052860495 |
| Short name | T1614 |
| Test name | |
| Test status | |
| Simulation time | 964547208 ps |
| CPU time | 38.2 seconds |
| Started | Jul 31 08:03:29 PM PDT 24 |
| Finished | Jul 31 08:04:08 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-b90920d3-88be-44fa-b321-91a00bca0c9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052860495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device .2052860495 |
| Directory | /workspace/90.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.1469683633 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 130446288843 ps |
| CPU time | 2191.82 seconds |
| Started | Jul 31 08:03:31 PM PDT 24 |
| Finished | Jul 31 08:40:04 PM PDT 24 |
| Peak memory | 576088 kb |
| Host | smart-fcc3f0a9-ce4e-4f8b-aab1-ba9f00b46fba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469683633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_ device_slow_rsp.1469683633 |
| Directory | /workspace/90.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.2363694681 |
| Short name | T1899 |
| Test name | |
| Test status | |
| Simulation time | 236727757 ps |
| CPU time | 30.18 seconds |
| Started | Jul 31 08:03:33 PM PDT 24 |
| Finished | Jul 31 08:04:03 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-13130de2-f234-4661-940f-1150886ea244 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363694681 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_and_unmapped_add r.2363694681 |
| Directory | /workspace/90.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_random.1667361734 |
| Short name | T2875 |
| Test name | |
| Test status | |
| Simulation time | 238512671 ps |
| CPU time | 19.39 seconds |
| Started | Jul 31 08:03:29 PM PDT 24 |
| Finished | Jul 31 08:03:49 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-4a94d872-b1ca-4e16-9ce6-2c6cce8b900b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667361734 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_random.1667361734 |
| Directory | /workspace/90.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random.948165261 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 198647394 ps |
| CPU time | 20.52 seconds |
| Started | Jul 31 08:03:29 PM PDT 24 |
| Finished | Jul 31 08:03:50 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-88e1a3bc-61b3-4f0e-9536-d6c3324c65c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948165261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random.948165261 |
| Directory | /workspace/90.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_large_delays.3149393808 |
| Short name | T1918 |
| Test name | |
| Test status | |
| Simulation time | 27539179537 ps |
| CPU time | 299.66 seconds |
| Started | Jul 31 08:03:24 PM PDT 24 |
| Finished | Jul 31 08:08:24 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-004976bf-5897-4fed-a781-9b483baeca99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149393808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_large_delays.3149393808 |
| Directory | /workspace/90.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_slow_rsp.581622169 |
| Short name | T1725 |
| Test name | |
| Test status | |
| Simulation time | 56895320130 ps |
| CPU time | 960.75 seconds |
| Started | Jul 31 08:03:29 PM PDT 24 |
| Finished | Jul 31 08:19:30 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-1893dac0-3d8a-4a42-9553-89992c4cc96b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581622169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_slow_rsp.581622169 |
| Directory | /workspace/90.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.1068628298 |
| Short name | T1707 |
| Test name | |
| Test status | |
| Simulation time | 501267349 ps |
| CPU time | 38.87 seconds |
| Started | Jul 31 08:03:24 PM PDT 24 |
| Finished | Jul 31 08:04:03 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-c7200dbe-177a-4e86-80cb-bca792293251 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068628298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_zero_del ays.1068628298 |
| Directory | /workspace/90.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_same_source.2141145754 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 2577687903 ps |
| CPU time | 76.29 seconds |
| Started | Jul 31 08:03:29 PM PDT 24 |
| Finished | Jul 31 08:04:45 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-a286de6d-12a0-48e3-9d05-4b66cc989d5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141145754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_same_source.2141145754 |
| Directory | /workspace/90.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke.2548814393 |
| Short name | T2802 |
| Test name | |
| Test status | |
| Simulation time | 201491933 ps |
| CPU time | 9.21 seconds |
| Started | Jul 31 08:03:24 PM PDT 24 |
| Finished | Jul 31 08:03:33 PM PDT 24 |
| Peak memory | 573772 kb |
| Host | smart-0300433c-4ee6-4ce8-94e5-82ea17db5b48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548814393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke.2548814393 |
| Directory | /workspace/90.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_large_delays.1161949025 |
| Short name | T1475 |
| Test name | |
| Test status | |
| Simulation time | 5404514763 ps |
| CPU time | 57.55 seconds |
| Started | Jul 31 08:03:25 PM PDT 24 |
| Finished | Jul 31 08:04:22 PM PDT 24 |
| Peak memory | 573904 kb |
| Host | smart-eecbc7cf-7c7e-44f5-b4e9-2aa7e5fccb22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161949025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_large_delays.1161949025 |
| Directory | /workspace/90.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.2784853582 |
| Short name | T2779 |
| Test name | |
| Test status | |
| Simulation time | 5670226047 ps |
| CPU time | 97.67 seconds |
| Started | Jul 31 08:03:27 PM PDT 24 |
| Finished | Jul 31 08:05:05 PM PDT 24 |
| Peak memory | 573904 kb |
| Host | smart-5caf3173-f3f0-4ad9-919e-029f9cf553a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784853582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_slow_rsp.2784853582 |
| Directory | /workspace/90.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_zero_delays.2578643830 |
| Short name | T1417 |
| Test name | |
| Test status | |
| Simulation time | 41251248 ps |
| CPU time | 6.37 seconds |
| Started | Jul 31 08:03:23 PM PDT 24 |
| Finished | Jul 31 08:03:30 PM PDT 24 |
| Peak memory | 573816 kb |
| Host | smart-323d7b77-e067-4603-ae1c-869f7857b693 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578643830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_zero_delay s.2578643830 |
| Directory | /workspace/90.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all.2373739446 |
| Short name | T2361 |
| Test name | |
| Test status | |
| Simulation time | 11380556318 ps |
| CPU time | 461.85 seconds |
| Started | Jul 31 08:03:32 PM PDT 24 |
| Finished | Jul 31 08:11:14 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-3281f75c-8a22-4aa5-b7ec-43f2d89472c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373739446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all.2373739446 |
| Directory | /workspace/90.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.1848376016 |
| Short name | T1930 |
| Test name | |
| Test status | |
| Simulation time | 3074478924 ps |
| CPU time | 107.2 seconds |
| Started | Jul 31 08:03:34 PM PDT 24 |
| Finished | Jul 31 08:05:21 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-d74e4a83-f1f7-4d0c-8760-456ae37fa184 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848376016 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_error.1848376016 |
| Directory | /workspace/90.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.4269180805 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 3622672757 ps |
| CPU time | 249.05 seconds |
| Started | Jul 31 08:03:31 PM PDT 24 |
| Finished | Jul 31 08:07:41 PM PDT 24 |
| Peak memory | 576756 kb |
| Host | smart-494a041b-5835-46bb-aaf7-1dd17c734b7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269180805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all _with_rand_reset.4269180805 |
| Directory | /workspace/90.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.2494388925 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 171356397 ps |
| CPU time | 29.11 seconds |
| Started | Jul 31 08:03:29 PM PDT 24 |
| Finished | Jul 31 08:03:58 PM PDT 24 |
| Peak memory | 576228 kb |
| Host | smart-2f1a1ace-ce52-4856-94d6-716b213662e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494388925 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_al l_with_reset_error.2494388925 |
| Directory | /workspace/90.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_unmapped_addr.2054397841 |
| Short name | T2553 |
| Test name | |
| Test status | |
| Simulation time | 18788761 ps |
| CPU time | 4.9 seconds |
| Started | Jul 31 08:03:32 PM PDT 24 |
| Finished | Jul 31 08:03:37 PM PDT 24 |
| Peak memory | 573872 kb |
| Host | smart-e5c512f5-0252-4d2c-96ac-898b14288229 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054397841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_unmapped_addr.2054397841 |
| Directory | /workspace/90.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device.2475818220 |
| Short name | T1580 |
| Test name | |
| Test status | |
| Simulation time | 1934371384 ps |
| CPU time | 77.92 seconds |
| Started | Jul 31 08:03:39 PM PDT 24 |
| Finished | Jul 31 08:04:57 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-c203c9a3-f6d0-4b15-8edf-ac23b7da4fa5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475818220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device .2475818220 |
| Directory | /workspace/91.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.3734593395 |
| Short name | T1503 |
| Test name | |
| Test status | |
| Simulation time | 69476110212 ps |
| CPU time | 1329.35 seconds |
| Started | Jul 31 08:03:37 PM PDT 24 |
| Finished | Jul 31 08:25:46 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-c8aa8f2f-0b38-4852-afdd-20ba0d2798db |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734593395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_ device_slow_rsp.3734593395 |
| Directory | /workspace/91.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.3219584404 |
| Short name | T1396 |
| Test name | |
| Test status | |
| Simulation time | 40145671 ps |
| CPU time | 7.42 seconds |
| Started | Jul 31 08:03:37 PM PDT 24 |
| Finished | Jul 31 08:03:45 PM PDT 24 |
| Peak memory | 573812 kb |
| Host | smart-5ac545ff-5aac-4c8b-a052-7b86695dd985 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219584404 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_and_unmapped_add r.3219584404 |
| Directory | /workspace/91.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_random.3243892736 |
| Short name | T2219 |
| Test name | |
| Test status | |
| Simulation time | 721067100 ps |
| CPU time | 27.5 seconds |
| Started | Jul 31 08:03:35 PM PDT 24 |
| Finished | Jul 31 08:04:03 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-56a64a5a-ae0e-431b-a7f9-a23ed0ae0002 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243892736 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_random.3243892736 |
| Directory | /workspace/91.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random.1824063749 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 257621423 ps |
| CPU time | 22.94 seconds |
| Started | Jul 31 08:03:34 PM PDT 24 |
| Finished | Jul 31 08:03:57 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-f8728e1d-d076-431b-af4e-88648bd9aeeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824063749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random.1824063749 |
| Directory | /workspace/91.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.407334778 |
| Short name | T2528 |
| Test name | |
| Test status | |
| Simulation time | 13686648362 ps |
| CPU time | 141.29 seconds |
| Started | Jul 31 08:03:39 PM PDT 24 |
| Finished | Jul 31 08:06:01 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-887667d2-df15-42a2-b907-c66e207dbeb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407334778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_large_delays.407334778 |
| Directory | /workspace/91.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_slow_rsp.1263789501 |
| Short name | T2047 |
| Test name | |
| Test status | |
| Simulation time | 52450306772 ps |
| CPU time | 903.09 seconds |
| Started | Jul 31 08:03:39 PM PDT 24 |
| Finished | Jul 31 08:18:42 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-a7d00634-53dd-4ecb-ad02-ba2ad8c10db1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263789501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_slow_rsp.1263789501 |
| Directory | /workspace/91.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_zero_delays.1174099265 |
| Short name | T1749 |
| Test name | |
| Test status | |
| Simulation time | 72082705 ps |
| CPU time | 9.11 seconds |
| Started | Jul 31 08:03:37 PM PDT 24 |
| Finished | Jul 31 08:03:46 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-a419202d-ad55-470e-ab07-14593e963dd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174099265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_zero_del ays.1174099265 |
| Directory | /workspace/91.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_same_source.3503925075 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 406307529 ps |
| CPU time | 14.1 seconds |
| Started | Jul 31 08:03:39 PM PDT 24 |
| Finished | Jul 31 08:03:53 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-c34c9c06-6379-4247-8e79-a1435daa809a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503925075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_same_source.3503925075 |
| Directory | /workspace/91.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke.107349157 |
| Short name | T1864 |
| Test name | |
| Test status | |
| Simulation time | 233006398 ps |
| CPU time | 9.34 seconds |
| Started | Jul 31 08:03:29 PM PDT 24 |
| Finished | Jul 31 08:03:39 PM PDT 24 |
| Peak memory | 574496 kb |
| Host | smart-7d9ccb22-2c7f-462a-8ceb-85498c2a5993 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107349157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke.107349157 |
| Directory | /workspace/91.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_large_delays.4090358150 |
| Short name | T1410 |
| Test name | |
| Test status | |
| Simulation time | 6324394283 ps |
| CPU time | 64.64 seconds |
| Started | Jul 31 08:03:29 PM PDT 24 |
| Finished | Jul 31 08:04:34 PM PDT 24 |
| Peak memory | 574512 kb |
| Host | smart-d0f23850-341d-4cbb-ba36-2671cc01ab04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090358150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_large_delays.4090358150 |
| Directory | /workspace/91.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.1435929517 |
| Short name | T1597 |
| Test name | |
| Test status | |
| Simulation time | 6106174810 ps |
| CPU time | 102.43 seconds |
| Started | Jul 31 08:03:29 PM PDT 24 |
| Finished | Jul 31 08:05:11 PM PDT 24 |
| Peak memory | 573992 kb |
| Host | smart-e86a1f22-2f3f-463e-a59c-92f104e2f864 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435929517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_slow_rsp.1435929517 |
| Directory | /workspace/91.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.2575658285 |
| Short name | T2252 |
| Test name | |
| Test status | |
| Simulation time | 54206785 ps |
| CPU time | 6.77 seconds |
| Started | Jul 31 08:03:30 PM PDT 24 |
| Finished | Jul 31 08:03:36 PM PDT 24 |
| Peak memory | 573900 kb |
| Host | smart-2a4da0fb-723f-4e53-b224-9597abea083c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575658285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_zero_delay s.2575658285 |
| Directory | /workspace/91.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all.1763586599 |
| Short name | T2336 |
| Test name | |
| Test status | |
| Simulation time | 3769251583 ps |
| CPU time | 135.67 seconds |
| Started | Jul 31 08:03:37 PM PDT 24 |
| Finished | Jul 31 08:05:52 PM PDT 24 |
| Peak memory | 576220 kb |
| Host | smart-b33a85d6-753e-425c-8d40-52223cef4bdb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763586599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all.1763586599 |
| Directory | /workspace/91.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.3159389160 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 11172846518 ps |
| CPU time | 662.7 seconds |
| Started | Jul 31 08:03:39 PM PDT 24 |
| Finished | Jul 31 08:14:41 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-2366d259-967b-4d3f-8ea0-9b06a5ce1215 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159389160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all _with_rand_reset.3159389160 |
| Directory | /workspace/91.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.1198502666 |
| Short name | T2889 |
| Test name | |
| Test status | |
| Simulation time | 2300003613 ps |
| CPU time | 259.92 seconds |
| Started | Jul 31 08:03:43 PM PDT 24 |
| Finished | Jul 31 08:08:03 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-16847061-b800-4185-8ab7-44e4937b6d31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198502666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_al l_with_reset_error.1198502666 |
| Directory | /workspace/91.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_unmapped_addr.2003678715 |
| Short name | T2679 |
| Test name | |
| Test status | |
| Simulation time | 270006262 ps |
| CPU time | 28.25 seconds |
| Started | Jul 31 08:03:35 PM PDT 24 |
| Finished | Jul 31 08:04:03 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-3381d836-8739-4660-a37b-32c0f4c087e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003678715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_unmapped_addr.2003678715 |
| Directory | /workspace/91.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device.1956369388 |
| Short name | T2510 |
| Test name | |
| Test status | |
| Simulation time | 1433450673 ps |
| CPU time | 96.55 seconds |
| Started | Jul 31 08:03:48 PM PDT 24 |
| Finished | Jul 31 08:05:25 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-55e55a84-98ad-4058-9d04-bb13693720f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956369388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device .1956369388 |
| Directory | /workspace/92.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.4107637777 |
| Short name | T2893 |
| Test name | |
| Test status | |
| Simulation time | 47255438947 ps |
| CPU time | 933.48 seconds |
| Started | Jul 31 08:03:47 PM PDT 24 |
| Finished | Jul 31 08:19:21 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-43d296c1-a2b4-400d-a6ce-5e9adaa7d10c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107637777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_ device_slow_rsp.4107637777 |
| Directory | /workspace/92.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.237520245 |
| Short name | T1905 |
| Test name | |
| Test status | |
| Simulation time | 197293449 ps |
| CPU time | 23.39 seconds |
| Started | Jul 31 08:03:52 PM PDT 24 |
| Finished | Jul 31 08:04:15 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-c940b672-c3c0-4460-b144-df51687aa680 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237520245 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_and_unmapped_addr .237520245 |
| Directory | /workspace/92.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_random.2186908174 |
| Short name | T2452 |
| Test name | |
| Test status | |
| Simulation time | 580061250 ps |
| CPU time | 47.96 seconds |
| Started | Jul 31 08:03:51 PM PDT 24 |
| Finished | Jul 31 08:04:39 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-ccda4a16-4a43-412d-9b15-691e2699ed1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186908174 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_random.2186908174 |
| Directory | /workspace/92.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random.2706134267 |
| Short name | T1682 |
| Test name | |
| Test status | |
| Simulation time | 213991115 ps |
| CPU time | 20.95 seconds |
| Started | Jul 31 08:03:45 PM PDT 24 |
| Finished | Jul 31 08:04:06 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-b0caab60-c1be-40dc-9e34-84eaaa9e075d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706134267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random.2706134267 |
| Directory | /workspace/92.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_large_delays.2481778614 |
| Short name | T1622 |
| Test name | |
| Test status | |
| Simulation time | 34336299706 ps |
| CPU time | 359.01 seconds |
| Started | Jul 31 08:03:43 PM PDT 24 |
| Finished | Jul 31 08:09:42 PM PDT 24 |
| Peak memory | 576032 kb |
| Host | smart-2486b5d6-f7df-4d2c-a5f0-eae1702bd5b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481778614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_large_delays.2481778614 |
| Directory | /workspace/92.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_slow_rsp.2661478160 |
| Short name | T2136 |
| Test name | |
| Test status | |
| Simulation time | 62400936572 ps |
| CPU time | 1087.67 seconds |
| Started | Jul 31 08:03:41 PM PDT 24 |
| Finished | Jul 31 08:21:49 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-80c9bb74-1c35-4982-bc8b-96a404a04822 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661478160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_slow_rsp.2661478160 |
| Directory | /workspace/92.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.1870489377 |
| Short name | T1821 |
| Test name | |
| Test status | |
| Simulation time | 70360556 ps |
| CPU time | 8.7 seconds |
| Started | Jul 31 08:03:42 PM PDT 24 |
| Finished | Jul 31 08:03:50 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-ab7f7399-7068-4724-9468-68b69a6a4604 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870489377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_zero_del ays.1870489377 |
| Directory | /workspace/92.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_same_source.730882791 |
| Short name | T1717 |
| Test name | |
| Test status | |
| Simulation time | 2270793672 ps |
| CPU time | 71.36 seconds |
| Started | Jul 31 08:03:48 PM PDT 24 |
| Finished | Jul 31 08:04:59 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-0342483f-c40e-42ff-b65c-dc03a25192df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730882791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_same_source.730882791 |
| Directory | /workspace/92.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke.40796539 |
| Short name | T2111 |
| Test name | |
| Test status | |
| Simulation time | 49879644 ps |
| CPU time | 6.9 seconds |
| Started | Jul 31 08:03:44 PM PDT 24 |
| Finished | Jul 31 08:03:51 PM PDT 24 |
| Peak memory | 574480 kb |
| Host | smart-f5651164-69e3-4a7a-bcc4-4d8e145211be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40796539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke.40796539 |
| Directory | /workspace/92.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_large_delays.4150022712 |
| Short name | T1504 |
| Test name | |
| Test status | |
| Simulation time | 9912136221 ps |
| CPU time | 101.13 seconds |
| Started | Jul 31 08:03:45 PM PDT 24 |
| Finished | Jul 31 08:05:26 PM PDT 24 |
| Peak memory | 573952 kb |
| Host | smart-9016618c-bc9d-4459-8785-6c39e3928e9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150022712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_large_delays.4150022712 |
| Directory | /workspace/92.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.1735770835 |
| Short name | T1953 |
| Test name | |
| Test status | |
| Simulation time | 5938469502 ps |
| CPU time | 100.23 seconds |
| Started | Jul 31 08:03:42 PM PDT 24 |
| Finished | Jul 31 08:05:22 PM PDT 24 |
| Peak memory | 573900 kb |
| Host | smart-c7e2ca79-7a80-4df4-85d4-153451698dbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735770835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_slow_rsp.1735770835 |
| Directory | /workspace/92.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.2596128018 |
| Short name | T2254 |
| Test name | |
| Test status | |
| Simulation time | 40689682 ps |
| CPU time | 6.24 seconds |
| Started | Jul 31 08:03:43 PM PDT 24 |
| Finished | Jul 31 08:03:49 PM PDT 24 |
| Peak memory | 574488 kb |
| Host | smart-b1386453-57ed-40af-8f2d-3e96e608eaba |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596128018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_zero_delay s.2596128018 |
| Directory | /workspace/92.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all.3978156022 |
| Short name | T2554 |
| Test name | |
| Test status | |
| Simulation time | 12262777473 ps |
| CPU time | 475.42 seconds |
| Started | Jul 31 08:03:46 PM PDT 24 |
| Finished | Jul 31 08:11:41 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-b268b967-c560-4845-a5fc-eff1aa8b0668 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978156022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all.3978156022 |
| Directory | /workspace/92.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_error.2819424858 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 2692821784 ps |
| CPU time | 99.5 seconds |
| Started | Jul 31 08:03:47 PM PDT 24 |
| Finished | Jul 31 08:05:27 PM PDT 24 |
| Peak memory | 576088 kb |
| Host | smart-cba3f87b-f6d3-4631-a04c-1703210b260c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819424858 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_error.2819424858 |
| Directory | /workspace/92.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.3256465055 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 4810636221 ps |
| CPU time | 285.74 seconds |
| Started | Jul 31 08:03:49 PM PDT 24 |
| Finished | Jul 31 08:08:35 PM PDT 24 |
| Peak memory | 576728 kb |
| Host | smart-3615c5e1-9806-4500-bacc-2828eb49133f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256465055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all _with_rand_reset.3256465055 |
| Directory | /workspace/92.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_unmapped_addr.475027298 |
| Short name | T1730 |
| Test name | |
| Test status | |
| Simulation time | 1366051299 ps |
| CPU time | 56.5 seconds |
| Started | Jul 31 08:03:46 PM PDT 24 |
| Finished | Jul 31 08:04:43 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-2b0022fc-d692-47d1-87f0-42701f75d106 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475027298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_unmapped_addr.475027298 |
| Directory | /workspace/92.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device.3437948139 |
| Short name | T2563 |
| Test name | |
| Test status | |
| Simulation time | 777316101 ps |
| CPU time | 68.46 seconds |
| Started | Jul 31 08:03:55 PM PDT 24 |
| Finished | Jul 31 08:05:03 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-dfde0765-a094-4527-8107-1865a6c42dfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437948139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device .3437948139 |
| Directory | /workspace/93.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.1111831451 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 136031910793 ps |
| CPU time | 2578.19 seconds |
| Started | Jul 31 08:03:54 PM PDT 24 |
| Finished | Jul 31 08:46:52 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-de53b16f-5c57-4f0f-80b8-6084ceb7afbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111831451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_ device_slow_rsp.1111831451 |
| Directory | /workspace/93.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.309189322 |
| Short name | T1839 |
| Test name | |
| Test status | |
| Simulation time | 671647730 ps |
| CPU time | 28.48 seconds |
| Started | Jul 31 08:04:01 PM PDT 24 |
| Finished | Jul 31 08:04:30 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-9d10605f-0abe-43d7-94ab-67ed52734adf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309189322 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_and_unmapped_addr .309189322 |
| Directory | /workspace/93.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_random.3039352016 |
| Short name | T1513 |
| Test name | |
| Test status | |
| Simulation time | 237647253 ps |
| CPU time | 17.27 seconds |
| Started | Jul 31 08:04:05 PM PDT 24 |
| Finished | Jul 31 08:04:23 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-0b28b084-e7cf-4cb9-8b93-ac48b0ff16f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039352016 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_random.3039352016 |
| Directory | /workspace/93.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random.813660450 |
| Short name | T1608 |
| Test name | |
| Test status | |
| Simulation time | 470717285 ps |
| CPU time | 19.47 seconds |
| Started | Jul 31 08:03:53 PM PDT 24 |
| Finished | Jul 31 08:04:12 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-7ac95a3a-fe07-4a8c-a511-095838378760 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813660450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random.813660450 |
| Directory | /workspace/93.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_large_delays.1624368483 |
| Short name | T2731 |
| Test name | |
| Test status | |
| Simulation time | 44320597254 ps |
| CPU time | 493.06 seconds |
| Started | Jul 31 08:03:55 PM PDT 24 |
| Finished | Jul 31 08:12:08 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-56f8d6d8-9ea0-4c6c-8b78-576fdada4ba5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624368483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_large_delays.1624368483 |
| Directory | /workspace/93.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.2914797035 |
| Short name | T1669 |
| Test name | |
| Test status | |
| Simulation time | 42869982194 ps |
| CPU time | 718.95 seconds |
| Started | Jul 31 08:03:54 PM PDT 24 |
| Finished | Jul 31 08:15:53 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-bbd7cd91-5081-4a84-80e8-3927766eb931 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914797035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_slow_rsp.2914797035 |
| Directory | /workspace/93.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_zero_delays.2715525552 |
| Short name | T2582 |
| Test name | |
| Test status | |
| Simulation time | 189986418 ps |
| CPU time | 16.58 seconds |
| Started | Jul 31 08:03:55 PM PDT 24 |
| Finished | Jul 31 08:04:12 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-35bd0f56-628d-4f22-946b-29719216af3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715525552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_zero_del ays.2715525552 |
| Directory | /workspace/93.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_same_source.2985180360 |
| Short name | T1644 |
| Test name | |
| Test status | |
| Simulation time | 43225917 ps |
| CPU time | 6.87 seconds |
| Started | Jul 31 08:04:01 PM PDT 24 |
| Finished | Jul 31 08:04:08 PM PDT 24 |
| Peak memory | 574580 kb |
| Host | smart-3edc62a6-0ff3-40ea-9d2e-642cd3af2277 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985180360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_same_source.2985180360 |
| Directory | /workspace/93.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke.3592192459 |
| Short name | T2119 |
| Test name | |
| Test status | |
| Simulation time | 180811870 ps |
| CPU time | 7.87 seconds |
| Started | Jul 31 08:03:48 PM PDT 24 |
| Finished | Jul 31 08:03:56 PM PDT 24 |
| Peak memory | 573796 kb |
| Host | smart-2c4c27cd-cb6d-4436-985e-ca833da59e9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592192459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke.3592192459 |
| Directory | /workspace/93.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_large_delays.2252370983 |
| Short name | T1488 |
| Test name | |
| Test status | |
| Simulation time | 7467171939 ps |
| CPU time | 74.56 seconds |
| Started | Jul 31 08:03:55 PM PDT 24 |
| Finished | Jul 31 08:05:10 PM PDT 24 |
| Peak memory | 573860 kb |
| Host | smart-21f0790e-51f3-43fa-94e9-12de86acb0b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252370983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_large_delays.2252370983 |
| Directory | /workspace/93.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.1320485497 |
| Short name | T1451 |
| Test name | |
| Test status | |
| Simulation time | 5076555564 ps |
| CPU time | 89.14 seconds |
| Started | Jul 31 08:03:54 PM PDT 24 |
| Finished | Jul 31 08:05:23 PM PDT 24 |
| Peak memory | 574588 kb |
| Host | smart-a5e5e659-3008-46e8-86b5-00fe36e9edc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320485497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_slow_rsp.1320485497 |
| Directory | /workspace/93.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_zero_delays.2142443597 |
| Short name | T2750 |
| Test name | |
| Test status | |
| Simulation time | 54001690 ps |
| CPU time | 6.38 seconds |
| Started | Jul 31 08:03:46 PM PDT 24 |
| Finished | Jul 31 08:03:53 PM PDT 24 |
| Peak memory | 574572 kb |
| Host | smart-32162c9b-0f97-4fbc-ba03-43cfacd1a817 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142443597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_zero_delay s.2142443597 |
| Directory | /workspace/93.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all.42026802 |
| Short name | T1857 |
| Test name | |
| Test status | |
| Simulation time | 3049721277 ps |
| CPU time | 295.53 seconds |
| Started | Jul 31 08:04:00 PM PDT 24 |
| Finished | Jul 31 08:08:56 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-aae2768d-4f2b-4a5a-a87e-33ab487c47e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42026802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all.42026802 |
| Directory | /workspace/93.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.3978441013 |
| Short name | T1826 |
| Test name | |
| Test status | |
| Simulation time | 3808707507 ps |
| CPU time | 323.91 seconds |
| Started | Jul 31 08:04:00 PM PDT 24 |
| Finished | Jul 31 08:09:24 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-deed50d2-ffd0-4189-94df-b04ab930c959 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978441013 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_error.3978441013 |
| Directory | /workspace/93.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.2707492303 |
| Short name | T2441 |
| Test name | |
| Test status | |
| Simulation time | 4563313073 ps |
| CPU time | 226.27 seconds |
| Started | Jul 31 08:04:03 PM PDT 24 |
| Finished | Jul 31 08:07:49 PM PDT 24 |
| Peak memory | 576792 kb |
| Host | smart-590838bb-cfc4-4222-9f40-fc2125fdda0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707492303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all _with_rand_reset.2707492303 |
| Directory | /workspace/93.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.20525162 |
| Short name | T2250 |
| Test name | |
| Test status | |
| Simulation time | 10831075138 ps |
| CPU time | 458.66 seconds |
| Started | Jul 31 08:04:02 PM PDT 24 |
| Finished | Jul 31 08:11:41 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-d13519da-ce0e-4f18-8583-dcf9441e86f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20525162 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_ with_reset_error.20525162 |
| Directory | /workspace/93.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_unmapped_addr.2207057282 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 1308549493 ps |
| CPU time | 50.29 seconds |
| Started | Jul 31 08:04:03 PM PDT 24 |
| Finished | Jul 31 08:04:53 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-017a2275-cb47-4830-95b7-132df1d8060e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207057282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_unmapped_addr.2207057282 |
| Directory | /workspace/93.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device.2611448293 |
| Short name | T1976 |
| Test name | |
| Test status | |
| Simulation time | 408019218 ps |
| CPU time | 26.54 seconds |
| Started | Jul 31 08:04:08 PM PDT 24 |
| Finished | Jul 31 08:04:35 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-f9bab976-f434-49f8-8f58-1128841c9f29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611448293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device .2611448293 |
| Directory | /workspace/94.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.2855821115 |
| Short name | T1814 |
| Test name | |
| Test status | |
| Simulation time | 51612422454 ps |
| CPU time | 1004.18 seconds |
| Started | Jul 31 08:04:06 PM PDT 24 |
| Finished | Jul 31 08:20:50 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-5d4a3553-130f-47bc-98fa-74290263efb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855821115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_ device_slow_rsp.2855821115 |
| Directory | /workspace/94.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.3563913463 |
| Short name | T2729 |
| Test name | |
| Test status | |
| Simulation time | 347431220 ps |
| CPU time | 15.07 seconds |
| Started | Jul 31 08:04:07 PM PDT 24 |
| Finished | Jul 31 08:04:22 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-2ad428c3-e216-4ee9-933d-44fba21f272b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563913463 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_and_unmapped_add r.3563913463 |
| Directory | /workspace/94.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_random.202325158 |
| Short name | T1547 |
| Test name | |
| Test status | |
| Simulation time | 839687735 ps |
| CPU time | 28.04 seconds |
| Started | Jul 31 08:04:06 PM PDT 24 |
| Finished | Jul 31 08:04:34 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-5bf6adc3-f4c7-4542-be36-f06f84fce998 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202325158 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_random.202325158 |
| Directory | /workspace/94.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random.1782534407 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 503588459 ps |
| CPU time | 20.64 seconds |
| Started | Jul 31 08:04:01 PM PDT 24 |
| Finished | Jul 31 08:04:22 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-c941bad0-7fe9-4b70-875a-ecf7f276a387 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782534407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random.1782534407 |
| Directory | /workspace/94.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_large_delays.2790121074 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 92346982363 ps |
| CPU time | 984.42 seconds |
| Started | Jul 31 08:04:02 PM PDT 24 |
| Finished | Jul 31 08:20:27 PM PDT 24 |
| Peak memory | 576052 kb |
| Host | smart-99ccf079-8db9-481f-b4c3-d2bd94f200c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790121074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_large_delays.2790121074 |
| Directory | /workspace/94.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_slow_rsp.4257732775 |
| Short name | T2169 |
| Test name | |
| Test status | |
| Simulation time | 3026063607 ps |
| CPU time | 48.83 seconds |
| Started | Jul 31 08:04:12 PM PDT 24 |
| Finished | Jul 31 08:05:01 PM PDT 24 |
| Peak memory | 574640 kb |
| Host | smart-91434da5-32de-4c6c-8917-ffb2483f7f68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257732775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_slow_rsp.4257732775 |
| Directory | /workspace/94.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_zero_delays.2991675221 |
| Short name | T1650 |
| Test name | |
| Test status | |
| Simulation time | 276351495 ps |
| CPU time | 23.73 seconds |
| Started | Jul 31 08:04:02 PM PDT 24 |
| Finished | Jul 31 08:04:26 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-8c4aadc8-bdc1-41d6-990a-1734dd8bdf7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991675221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_zero_del ays.2991675221 |
| Directory | /workspace/94.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_same_source.2428991743 |
| Short name | T2634 |
| Test name | |
| Test status | |
| Simulation time | 168245704 ps |
| CPU time | 15.57 seconds |
| Started | Jul 31 08:04:06 PM PDT 24 |
| Finished | Jul 31 08:04:22 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-4aa242ea-45a7-4649-8819-32879d69cac2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428991743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_same_source.2428991743 |
| Directory | /workspace/94.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke.1605622275 |
| Short name | T1989 |
| Test name | |
| Test status | |
| Simulation time | 198612341 ps |
| CPU time | 8.93 seconds |
| Started | Jul 31 08:04:01 PM PDT 24 |
| Finished | Jul 31 08:04:10 PM PDT 24 |
| Peak memory | 573856 kb |
| Host | smart-0be93cb8-607b-4bcb-a061-5c26ba6f106b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605622275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke.1605622275 |
| Directory | /workspace/94.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_large_delays.3547851065 |
| Short name | T1569 |
| Test name | |
| Test status | |
| Simulation time | 9471611161 ps |
| CPU time | 98.61 seconds |
| Started | Jul 31 08:04:00 PM PDT 24 |
| Finished | Jul 31 08:05:38 PM PDT 24 |
| Peak memory | 573892 kb |
| Host | smart-d3d91c91-4bcd-4d00-a93f-50ae8764bc71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547851065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_large_delays.3547851065 |
| Directory | /workspace/94.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.2879056807 |
| Short name | T1395 |
| Test name | |
| Test status | |
| Simulation time | 4740597310 ps |
| CPU time | 83.8 seconds |
| Started | Jul 31 08:04:04 PM PDT 24 |
| Finished | Jul 31 08:05:28 PM PDT 24 |
| Peak memory | 573888 kb |
| Host | smart-1204f521-f57d-4482-a574-7ccc399535d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879056807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_slow_rsp.2879056807 |
| Directory | /workspace/94.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_zero_delays.1630967052 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 48069595 ps |
| CPU time | 6.72 seconds |
| Started | Jul 31 08:04:02 PM PDT 24 |
| Finished | Jul 31 08:04:08 PM PDT 24 |
| Peak memory | 573912 kb |
| Host | smart-d8c3720b-91b5-435d-ac4a-005786df05ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630967052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_zero_delay s.1630967052 |
| Directory | /workspace/94.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all.3638114235 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 10080496703 ps |
| CPU time | 341.41 seconds |
| Started | Jul 31 08:04:08 PM PDT 24 |
| Finished | Jul 31 08:09:50 PM PDT 24 |
| Peak memory | 576716 kb |
| Host | smart-13c39b39-7537-43fe-ac52-ca55ffd7caa8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638114235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all.3638114235 |
| Directory | /workspace/94.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_error.1874600511 |
| Short name | T2058 |
| Test name | |
| Test status | |
| Simulation time | 2525012697 ps |
| CPU time | 208.29 seconds |
| Started | Jul 31 08:04:13 PM PDT 24 |
| Finished | Jul 31 08:07:42 PM PDT 24 |
| Peak memory | 576728 kb |
| Host | smart-e8e517ac-fb7f-45fb-bfc6-01827291f2f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874600511 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_error.1874600511 |
| Directory | /workspace/94.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.871416042 |
| Short name | T2506 |
| Test name | |
| Test status | |
| Simulation time | 182252051 ps |
| CPU time | 86.52 seconds |
| Started | Jul 31 08:04:14 PM PDT 24 |
| Finished | Jul 31 08:05:40 PM PDT 24 |
| Peak memory | 576740 kb |
| Host | smart-1ae7cda6-991b-4b39-bd41-495bbb00ae1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871416042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all _with_reset_error.871416042 |
| Directory | /workspace/94.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_unmapped_addr.869189880 |
| Short name | T1602 |
| Test name | |
| Test status | |
| Simulation time | 383255690 ps |
| CPU time | 15.85 seconds |
| Started | Jul 31 08:04:12 PM PDT 24 |
| Finished | Jul 31 08:04:28 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-82835077-aa19-451c-8059-beafe6b4bd13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869189880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_unmapped_addr.869189880 |
| Directory | /workspace/94.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device.2457581514 |
| Short name | T1938 |
| Test name | |
| Test status | |
| Simulation time | 1148311297 ps |
| CPU time | 86.81 seconds |
| Started | Jul 31 08:04:14 PM PDT 24 |
| Finished | Jul 31 08:05:41 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-80502d7a-8416-45b1-acb2-d9a419b608e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457581514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device .2457581514 |
| Directory | /workspace/95.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.594473322 |
| Short name | T2159 |
| Test name | |
| Test status | |
| Simulation time | 138048582780 ps |
| CPU time | 2551.4 seconds |
| Started | Jul 31 08:04:26 PM PDT 24 |
| Finished | Jul 31 08:46:58 PM PDT 24 |
| Peak memory | 576104 kb |
| Host | smart-bc2b76da-7373-4a8e-8da4-8008b7698f8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594473322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_d evice_slow_rsp.594473322 |
| Directory | /workspace/95.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.2331946339 |
| Short name | T2803 |
| Test name | |
| Test status | |
| Simulation time | 321784578 ps |
| CPU time | 34.01 seconds |
| Started | Jul 31 08:04:20 PM PDT 24 |
| Finished | Jul 31 08:04:54 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-0cb9044f-c7c6-4d28-9aef-dd60d095a62c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331946339 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_and_unmapped_add r.2331946339 |
| Directory | /workspace/95.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_random.2381080546 |
| Short name | T2742 |
| Test name | |
| Test status | |
| Simulation time | 1403790433 ps |
| CPU time | 45.76 seconds |
| Started | Jul 31 08:04:26 PM PDT 24 |
| Finished | Jul 31 08:05:12 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-71dc3367-804a-4bb4-a831-f3ed088fbb2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381080546 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_random.2381080546 |
| Directory | /workspace/95.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random.1651745109 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 245238629 ps |
| CPU time | 22.74 seconds |
| Started | Jul 31 08:04:13 PM PDT 24 |
| Finished | Jul 31 08:04:36 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-38f8539e-720d-40ba-ba29-f42cdddae648 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651745109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random.1651745109 |
| Directory | /workspace/95.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_large_delays.1523951712 |
| Short name | T1872 |
| Test name | |
| Test status | |
| Simulation time | 41289693283 ps |
| CPU time | 426.87 seconds |
| Started | Jul 31 08:04:15 PM PDT 24 |
| Finished | Jul 31 08:11:22 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-0286668e-c731-44b3-b3a1-4c018716ee82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523951712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_large_delays.1523951712 |
| Directory | /workspace/95.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_slow_rsp.620622557 |
| Short name | T2485 |
| Test name | |
| Test status | |
| Simulation time | 25806007209 ps |
| CPU time | 455.45 seconds |
| Started | Jul 31 08:04:20 PM PDT 24 |
| Finished | Jul 31 08:11:56 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-c9613e69-902a-4137-a300-e602243c788a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620622557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_slow_rsp.620622557 |
| Directory | /workspace/95.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_zero_delays.1057593867 |
| Short name | T1518 |
| Test name | |
| Test status | |
| Simulation time | 314383936 ps |
| CPU time | 26.01 seconds |
| Started | Jul 31 08:04:12 PM PDT 24 |
| Finished | Jul 31 08:04:38 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-d5e38dcb-fc77-4bfd-9f23-3da8117ccc8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057593867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_zero_del ays.1057593867 |
| Directory | /workspace/95.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_same_source.2256001638 |
| Short name | T2558 |
| Test name | |
| Test status | |
| Simulation time | 347260075 ps |
| CPU time | 24.48 seconds |
| Started | Jul 31 08:04:18 PM PDT 24 |
| Finished | Jul 31 08:04:42 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-91dee8e3-efa8-45df-acf4-6095f2867402 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256001638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_same_source.2256001638 |
| Directory | /workspace/95.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke.1905847725 |
| Short name | T2420 |
| Test name | |
| Test status | |
| Simulation time | 179473662 ps |
| CPU time | 7.65 seconds |
| Started | Jul 31 08:04:13 PM PDT 24 |
| Finished | Jul 31 08:04:21 PM PDT 24 |
| Peak memory | 573824 kb |
| Host | smart-05245a54-5e38-4f72-9a68-c698959b5bf3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905847725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke.1905847725 |
| Directory | /workspace/95.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_large_delays.2899427008 |
| Short name | T2240 |
| Test name | |
| Test status | |
| Simulation time | 7596012488 ps |
| CPU time | 80.64 seconds |
| Started | Jul 31 08:04:14 PM PDT 24 |
| Finished | Jul 31 08:05:34 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-9731a662-2a12-494c-82a1-49e56ce951a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899427008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_large_delays.2899427008 |
| Directory | /workspace/95.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.181351277 |
| Short name | T2192 |
| Test name | |
| Test status | |
| Simulation time | 5637655840 ps |
| CPU time | 98.15 seconds |
| Started | Jul 31 08:04:14 PM PDT 24 |
| Finished | Jul 31 08:05:52 PM PDT 24 |
| Peak memory | 573860 kb |
| Host | smart-381d5c8b-d825-477b-a390-c1fc5c1bc5e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181351277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_slow_rsp.181351277 |
| Directory | /workspace/95.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_zero_delays.2699247939 |
| Short name | T1505 |
| Test name | |
| Test status | |
| Simulation time | 54264681 ps |
| CPU time | 6.58 seconds |
| Started | Jul 31 08:04:15 PM PDT 24 |
| Finished | Jul 31 08:04:22 PM PDT 24 |
| Peak memory | 573776 kb |
| Host | smart-fea8f50a-4fdd-4941-8b64-86cb44d95515 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699247939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_zero_delay s.2699247939 |
| Directory | /workspace/95.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all.3466983448 |
| Short name | T1948 |
| Test name | |
| Test status | |
| Simulation time | 2909232349 ps |
| CPU time | 245.47 seconds |
| Started | Jul 31 08:04:21 PM PDT 24 |
| Finished | Jul 31 08:08:26 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-1abeb526-49d5-421f-8a21-b136a938a8e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466983448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all.3466983448 |
| Directory | /workspace/95.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.3187376250 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 1740751632 ps |
| CPU time | 128.32 seconds |
| Started | Jul 31 08:04:22 PM PDT 24 |
| Finished | Jul 31 08:06:30 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-48a89f32-c395-4f7d-918e-857438544b7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187376250 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_error.3187376250 |
| Directory | /workspace/95.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.662117693 |
| Short name | T1534 |
| Test name | |
| Test status | |
| Simulation time | 155328454 ps |
| CPU time | 71.27 seconds |
| Started | Jul 31 08:04:20 PM PDT 24 |
| Finished | Jul 31 08:05:31 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-7c156423-1551-4f45-99fd-ca9436753a09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662117693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_ with_rand_reset.662117693 |
| Directory | /workspace/95.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.3226436397 |
| Short name | T2347 |
| Test name | |
| Test status | |
| Simulation time | 436142441 ps |
| CPU time | 197.66 seconds |
| Started | Jul 31 08:04:19 PM PDT 24 |
| Finished | Jul 31 08:07:37 PM PDT 24 |
| Peak memory | 576708 kb |
| Host | smart-5302e80c-691b-46f9-86cc-41d777e912ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226436397 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_al l_with_reset_error.3226436397 |
| Directory | /workspace/95.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_unmapped_addr.3563041243 |
| Short name | T1645 |
| Test name | |
| Test status | |
| Simulation time | 455005007 ps |
| CPU time | 20.93 seconds |
| Started | Jul 31 08:04:26 PM PDT 24 |
| Finished | Jul 31 08:04:47 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-5df81452-c915-43af-b012-3fb38db2669f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563041243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_unmapped_addr.3563041243 |
| Directory | /workspace/95.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device.3588588607 |
| Short name | T1664 |
| Test name | |
| Test status | |
| Simulation time | 217953476 ps |
| CPU time | 22.59 seconds |
| Started | Jul 31 08:04:25 PM PDT 24 |
| Finished | Jul 31 08:04:48 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-01583366-700b-46c5-bde7-09dcff9f8782 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588588607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device .3588588607 |
| Directory | /workspace/96.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.657950158 |
| Short name | T1898 |
| Test name | |
| Test status | |
| Simulation time | 43044484145 ps |
| CPU time | 768.05 seconds |
| Started | Jul 31 08:04:26 PM PDT 24 |
| Finished | Jul 31 08:17:14 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-19594513-e98f-4b0f-886b-feba5ebd40f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657950158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_d evice_slow_rsp.657950158 |
| Directory | /workspace/96.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.264998736 |
| Short name | T1677 |
| Test name | |
| Test status | |
| Simulation time | 196414385 ps |
| CPU time | 20.54 seconds |
| Started | Jul 31 08:04:32 PM PDT 24 |
| Finished | Jul 31 08:04:52 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-20d217a8-0e90-4944-ad7d-57a007b2419c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264998736 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_and_unmapped_addr .264998736 |
| Directory | /workspace/96.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_random.2417122400 |
| Short name | T2924 |
| Test name | |
| Test status | |
| Simulation time | 2647713855 ps |
| CPU time | 80.02 seconds |
| Started | Jul 31 08:04:30 PM PDT 24 |
| Finished | Jul 31 08:05:50 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-2facd331-464b-4168-a459-c01c1cc66c33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417122400 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_random.2417122400 |
| Directory | /workspace/96.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random.359737004 |
| Short name | T1715 |
| Test name | |
| Test status | |
| Simulation time | 267202670 ps |
| CPU time | 26.49 seconds |
| Started | Jul 31 08:04:24 PM PDT 24 |
| Finished | Jul 31 08:04:50 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-acfa88bb-c32c-45b6-8373-52569b65e343 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359737004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random.359737004 |
| Directory | /workspace/96.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_large_delays.2886906647 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 93978577564 ps |
| CPU time | 1036.29 seconds |
| Started | Jul 31 08:04:26 PM PDT 24 |
| Finished | Jul 31 08:21:42 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-b34006ac-8499-4c95-8e33-dd4a99818687 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886906647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_large_delays.2886906647 |
| Directory | /workspace/96.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_slow_rsp.2093880818 |
| Short name | T2703 |
| Test name | |
| Test status | |
| Simulation time | 7337910665 ps |
| CPU time | 123.82 seconds |
| Started | Jul 31 08:04:26 PM PDT 24 |
| Finished | Jul 31 08:06:30 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-8609ba5a-f59e-42a0-9d37-c2cff46fbce2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093880818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_slow_rsp.2093880818 |
| Directory | /workspace/96.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.1156656400 |
| Short name | T1745 |
| Test name | |
| Test status | |
| Simulation time | 253619959 ps |
| CPU time | 22.1 seconds |
| Started | Jul 31 08:04:25 PM PDT 24 |
| Finished | Jul 31 08:04:47 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-34415214-745c-4ced-be0b-b9508f69978b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156656400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_zero_del ays.1156656400 |
| Directory | /workspace/96.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_same_source.3646962294 |
| Short name | T2591 |
| Test name | |
| Test status | |
| Simulation time | 366420356 ps |
| CPU time | 26.8 seconds |
| Started | Jul 31 08:04:26 PM PDT 24 |
| Finished | Jul 31 08:04:53 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-19e01f06-9699-49d1-93ca-3a480b699bee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646962294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_same_source.3646962294 |
| Directory | /workspace/96.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke.1676854411 |
| Short name | T1407 |
| Test name | |
| Test status | |
| Simulation time | 55749866 ps |
| CPU time | 6.54 seconds |
| Started | Jul 31 08:04:18 PM PDT 24 |
| Finished | Jul 31 08:04:25 PM PDT 24 |
| Peak memory | 574480 kb |
| Host | smart-f8462d98-69f9-4ce1-b35c-1f77a6ac632e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676854411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke.1676854411 |
| Directory | /workspace/96.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.577826761 |
| Short name | T1840 |
| Test name | |
| Test status | |
| Simulation time | 7684388829 ps |
| CPU time | 81.7 seconds |
| Started | Jul 31 08:04:20 PM PDT 24 |
| Finished | Jul 31 08:05:42 PM PDT 24 |
| Peak memory | 573892 kb |
| Host | smart-26188cc7-0edc-4f3a-a035-394fef8f8435 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577826761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_large_delays.577826761 |
| Directory | /workspace/96.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.3035763106 |
| Short name | T2783 |
| Test name | |
| Test status | |
| Simulation time | 4861666283 ps |
| CPU time | 83.44 seconds |
| Started | Jul 31 08:04:17 PM PDT 24 |
| Finished | Jul 31 08:05:41 PM PDT 24 |
| Peak memory | 573560 kb |
| Host | smart-b44ec90b-aa94-4b5e-a8bd-f417c991442e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035763106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_slow_rsp.3035763106 |
| Directory | /workspace/96.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.2313096947 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 48136333 ps |
| CPU time | 6.6 seconds |
| Started | Jul 31 08:04:18 PM PDT 24 |
| Finished | Jul 31 08:04:25 PM PDT 24 |
| Peak memory | 573740 kb |
| Host | smart-815db287-c9ab-4595-9537-20fbc1efe17c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313096947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_zero_delay s.2313096947 |
| Directory | /workspace/96.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all.786406200 |
| Short name | T1984 |
| Test name | |
| Test status | |
| Simulation time | 3574310442 ps |
| CPU time | 140.83 seconds |
| Started | Jul 31 08:04:31 PM PDT 24 |
| Finished | Jul 31 08:06:52 PM PDT 24 |
| Peak memory | 576128 kb |
| Host | smart-d4b2417d-79f1-4c29-9348-25af2baecba6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786406200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all.786406200 |
| Directory | /workspace/96.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.3746357709 |
| Short name | T2397 |
| Test name | |
| Test status | |
| Simulation time | 5123270222 ps |
| CPU time | 184.82 seconds |
| Started | Jul 31 08:04:30 PM PDT 24 |
| Finished | Jul 31 08:07:35 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-0cc7a637-9121-44f2-8a50-6e749801fd09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746357709 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_error.3746357709 |
| Directory | /workspace/96.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.678104756 |
| Short name | T2516 |
| Test name | |
| Test status | |
| Simulation time | 5780691669 ps |
| CPU time | 634.38 seconds |
| Started | Jul 31 08:04:33 PM PDT 24 |
| Finished | Jul 31 08:15:07 PM PDT 24 |
| Peak memory | 576736 kb |
| Host | smart-75778d53-4f97-4c4f-9b58-d020cf9d9c38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678104756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_ with_rand_reset.678104756 |
| Directory | /workspace/96.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.3769003749 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 6259862691 ps |
| CPU time | 559.3 seconds |
| Started | Jul 31 08:04:32 PM PDT 24 |
| Finished | Jul 31 08:13:52 PM PDT 24 |
| Peak memory | 576992 kb |
| Host | smart-ac1c569f-6977-4119-863a-4c7dab15d241 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769003749 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_al l_with_reset_error.3769003749 |
| Directory | /workspace/96.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_unmapped_addr.3223366439 |
| Short name | T2026 |
| Test name | |
| Test status | |
| Simulation time | 1129292953 ps |
| CPU time | 49.31 seconds |
| Started | Jul 31 08:04:31 PM PDT 24 |
| Finished | Jul 31 08:05:21 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-418e2f4f-e0e0-480e-94de-517569b5ccc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223366439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_unmapped_addr.3223366439 |
| Directory | /workspace/96.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device.2342877223 |
| Short name | T1803 |
| Test name | |
| Test status | |
| Simulation time | 3155561293 ps |
| CPU time | 121.71 seconds |
| Started | Jul 31 08:04:38 PM PDT 24 |
| Finished | Jul 31 08:06:40 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-728dff20-c838-4ffd-bb4c-4383c61f8109 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342877223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device .2342877223 |
| Directory | /workspace/97.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.666935154 |
| Short name | T1939 |
| Test name | |
| Test status | |
| Simulation time | 117392306906 ps |
| CPU time | 2216.83 seconds |
| Started | Jul 31 08:04:39 PM PDT 24 |
| Finished | Jul 31 08:41:36 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-1fc82a54-0bda-4a08-a695-a42e6af5d425 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666935154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_d evice_slow_rsp.666935154 |
| Directory | /workspace/97.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.3240595256 |
| Short name | T2788 |
| Test name | |
| Test status | |
| Simulation time | 148197548 ps |
| CPU time | 18.34 seconds |
| Started | Jul 31 08:04:41 PM PDT 24 |
| Finished | Jul 31 08:04:59 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-c084f666-cc35-4326-aa5b-181be1b58083 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240595256 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_and_unmapped_add r.3240595256 |
| Directory | /workspace/97.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_random.494303962 |
| Short name | T1401 |
| Test name | |
| Test status | |
| Simulation time | 565674374 ps |
| CPU time | 45.76 seconds |
| Started | Jul 31 08:04:36 PM PDT 24 |
| Finished | Jul 31 08:05:22 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-cda1f2b1-d4a0-4e80-baf4-9ada6f296d3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494303962 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_random.494303962 |
| Directory | /workspace/97.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random.192642183 |
| Short name | T2052 |
| Test name | |
| Test status | |
| Simulation time | 339082836 ps |
| CPU time | 30.48 seconds |
| Started | Jul 31 08:04:33 PM PDT 24 |
| Finished | Jul 31 08:05:03 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-e0971e0f-f8c9-451e-bbb3-770b993e6c30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192642183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random.192642183 |
| Directory | /workspace/97.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_large_delays.245989404 |
| Short name | T2346 |
| Test name | |
| Test status | |
| Simulation time | 83715625741 ps |
| CPU time | 1009.05 seconds |
| Started | Jul 31 08:04:38 PM PDT 24 |
| Finished | Jul 31 08:21:28 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-7d5ca40a-f64f-4935-a3f5-de6c59338892 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245989404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_large_delays.245989404 |
| Directory | /workspace/97.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_slow_rsp.1805364789 |
| Short name | T1887 |
| Test name | |
| Test status | |
| Simulation time | 24849426584 ps |
| CPU time | 419.46 seconds |
| Started | Jul 31 08:04:38 PM PDT 24 |
| Finished | Jul 31 08:11:37 PM PDT 24 |
| Peak memory | 576044 kb |
| Host | smart-f2b55c7d-03d9-4b75-9fb6-5a4c93531fb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805364789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_slow_rsp.1805364789 |
| Directory | /workspace/97.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.1278792902 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 140708632 ps |
| CPU time | 15.38 seconds |
| Started | Jul 31 08:04:33 PM PDT 24 |
| Finished | Jul 31 08:04:48 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-9f308721-4010-4f1c-956f-432c535f9449 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278792902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_zero_del ays.1278792902 |
| Directory | /workspace/97.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_same_source.2356703406 |
| Short name | T1908 |
| Test name | |
| Test status | |
| Simulation time | 2375305193 ps |
| CPU time | 70.49 seconds |
| Started | Jul 31 08:04:42 PM PDT 24 |
| Finished | Jul 31 08:05:52 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-fee7305e-abab-4117-8dca-ebaa2aca3c32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356703406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_same_source.2356703406 |
| Directory | /workspace/97.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke.3186227274 |
| Short name | T2170 |
| Test name | |
| Test status | |
| Simulation time | 241480790 ps |
| CPU time | 9 seconds |
| Started | Jul 31 08:04:31 PM PDT 24 |
| Finished | Jul 31 08:04:40 PM PDT 24 |
| Peak memory | 573796 kb |
| Host | smart-e494bd9f-c358-41d9-aaac-7d7497bb4b05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186227274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke.3186227274 |
| Directory | /workspace/97.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.3642446327 |
| Short name | T2277 |
| Test name | |
| Test status | |
| Simulation time | 7343893403 ps |
| CPU time | 74.9 seconds |
| Started | Jul 31 08:04:32 PM PDT 24 |
| Finished | Jul 31 08:05:47 PM PDT 24 |
| Peak memory | 573960 kb |
| Host | smart-5eeb9bb1-49a7-4dee-a1a0-bf8958258b4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642446327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_large_delays.3642446327 |
| Directory | /workspace/97.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.1249032328 |
| Short name | T2433 |
| Test name | |
| Test status | |
| Simulation time | 5078240916 ps |
| CPU time | 79.93 seconds |
| Started | Jul 31 08:04:31 PM PDT 24 |
| Finished | Jul 31 08:05:51 PM PDT 24 |
| Peak memory | 573912 kb |
| Host | smart-a049a73a-45a8-4b25-9002-5f973b3ecd33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249032328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_slow_rsp.1249032328 |
| Directory | /workspace/97.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_zero_delays.2125360551 |
| Short name | T2213 |
| Test name | |
| Test status | |
| Simulation time | 45460665 ps |
| CPU time | 6.05 seconds |
| Started | Jul 31 08:04:32 PM PDT 24 |
| Finished | Jul 31 08:04:38 PM PDT 24 |
| Peak memory | 573800 kb |
| Host | smart-bb2dd612-a6db-4765-b4b0-93f662699e86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125360551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_zero_delay s.2125360551 |
| Directory | /workspace/97.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all.325894896 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 4265150786 ps |
| CPU time | 389.06 seconds |
| Started | Jul 31 08:04:37 PM PDT 24 |
| Finished | Jul 31 08:11:06 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-e91e79f8-483c-4beb-a56d-6c7aec535d03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325894896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all.325894896 |
| Directory | /workspace/97.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.1938630610 |
| Short name | T1636 |
| Test name | |
| Test status | |
| Simulation time | 2382738151 ps |
| CPU time | 84.59 seconds |
| Started | Jul 31 08:04:41 PM PDT 24 |
| Finished | Jul 31 08:06:05 PM PDT 24 |
| Peak memory | 576124 kb |
| Host | smart-983dc6a0-ceed-49bf-b52b-9814911acebd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938630610 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_error.1938630610 |
| Directory | /workspace/97.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.3865387453 |
| Short name | T2435 |
| Test name | |
| Test status | |
| Simulation time | 258252914 ps |
| CPU time | 81.04 seconds |
| Started | Jul 31 08:04:38 PM PDT 24 |
| Finished | Jul 31 08:05:59 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-cdb5cfef-0379-4b9d-81d1-d3707ae14bbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865387453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all _with_rand_reset.3865387453 |
| Directory | /workspace/97.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.467861186 |
| Short name | T1891 |
| Test name | |
| Test status | |
| Simulation time | 5127145665 ps |
| CPU time | 636.11 seconds |
| Started | Jul 31 08:04:41 PM PDT 24 |
| Finished | Jul 31 08:15:17 PM PDT 24 |
| Peak memory | 577824 kb |
| Host | smart-d97e4ce6-2784-4dc8-84ec-9943f02a774e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467861186 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all _with_reset_error.467861186 |
| Directory | /workspace/97.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_unmapped_addr.3473679378 |
| Short name | T2707 |
| Test name | |
| Test status | |
| Simulation time | 510262170 ps |
| CPU time | 23.84 seconds |
| Started | Jul 31 08:04:38 PM PDT 24 |
| Finished | Jul 31 08:05:02 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-855c86bf-54a5-402a-b638-9a3e8091defd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473679378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_unmapped_addr.3473679378 |
| Directory | /workspace/97.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device.284256305 |
| Short name | T2921 |
| Test name | |
| Test status | |
| Simulation time | 1481243886 ps |
| CPU time | 53.97 seconds |
| Started | Jul 31 08:04:40 PM PDT 24 |
| Finished | Jul 31 08:05:34 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-2650635b-597a-4cb5-987c-d82b6cafcadd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284256305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device. 284256305 |
| Directory | /workspace/98.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.615189203 |
| Short name | T2071 |
| Test name | |
| Test status | |
| Simulation time | 102931616189 ps |
| CPU time | 1941.93 seconds |
| Started | Jul 31 08:04:46 PM PDT 24 |
| Finished | Jul 31 08:37:08 PM PDT 24 |
| Peak memory | 576056 kb |
| Host | smart-b8c4b6f4-c8c6-4eac-884f-89633734c0c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615189203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_d evice_slow_rsp.615189203 |
| Directory | /workspace/98.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.3630072878 |
| Short name | T2458 |
| Test name | |
| Test status | |
| Simulation time | 93098202 ps |
| CPU time | 13.2 seconds |
| Started | Jul 31 08:04:42 PM PDT 24 |
| Finished | Jul 31 08:04:56 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-d29cc569-bdef-4fe2-9e5a-ca4d1ec90919 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630072878 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_and_unmapped_add r.3630072878 |
| Directory | /workspace/98.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_random.656048081 |
| Short name | T1485 |
| Test name | |
| Test status | |
| Simulation time | 116737702 ps |
| CPU time | 12.21 seconds |
| Started | Jul 31 08:04:46 PM PDT 24 |
| Finished | Jul 31 08:04:58 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-6f1bcadb-d5e0-4a6d-9348-121345f88962 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656048081 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_random.656048081 |
| Directory | /workspace/98.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random.707439471 |
| Short name | T1463 |
| Test name | |
| Test status | |
| Simulation time | 2345188833 ps |
| CPU time | 78.45 seconds |
| Started | Jul 31 08:04:38 PM PDT 24 |
| Finished | Jul 31 08:05:56 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-9e77775c-16eb-4641-9816-0ea48d629ea7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707439471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random.707439471 |
| Directory | /workspace/98.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_large_delays.119156047 |
| Short name | T2681 |
| Test name | |
| Test status | |
| Simulation time | 83258476441 ps |
| CPU time | 958.34 seconds |
| Started | Jul 31 08:04:38 PM PDT 24 |
| Finished | Jul 31 08:20:37 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-885ab711-46a1-49d1-adb9-9875b48f5f92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119156047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_large_delays.119156047 |
| Directory | /workspace/98.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_slow_rsp.2143343212 |
| Short name | T1711 |
| Test name | |
| Test status | |
| Simulation time | 42889309597 ps |
| CPU time | 808.09 seconds |
| Started | Jul 31 08:04:39 PM PDT 24 |
| Finished | Jul 31 08:18:07 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-c5c3ef7a-5a06-489e-a3ed-6145365b3f14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143343212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_slow_rsp.2143343212 |
| Directory | /workspace/98.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_zero_delays.3193462667 |
| Short name | T2233 |
| Test name | |
| Test status | |
| Simulation time | 242864078 ps |
| CPU time | 22.13 seconds |
| Started | Jul 31 08:04:38 PM PDT 24 |
| Finished | Jul 31 08:05:01 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-1d257cf6-2177-4a5c-beee-f577525b40ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193462667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_zero_del ays.3193462667 |
| Directory | /workspace/98.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_same_source.4177211424 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 513674340 ps |
| CPU time | 18.19 seconds |
| Started | Jul 31 08:04:43 PM PDT 24 |
| Finished | Jul 31 08:05:01 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-45ee8537-83b9-48cf-8823-5a9d0abd60df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177211424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_same_source.4177211424 |
| Directory | /workspace/98.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke.2893661327 |
| Short name | T2184 |
| Test name | |
| Test status | |
| Simulation time | 169727756 ps |
| CPU time | 7.62 seconds |
| Started | Jul 31 08:04:38 PM PDT 24 |
| Finished | Jul 31 08:04:45 PM PDT 24 |
| Peak memory | 573828 kb |
| Host | smart-52a76954-08b4-4e47-967e-7ec063fe8110 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893661327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke.2893661327 |
| Directory | /workspace/98.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_large_delays.599660482 |
| Short name | T1558 |
| Test name | |
| Test status | |
| Simulation time | 6152435113 ps |
| CPU time | 62.09 seconds |
| Started | Jul 31 08:04:39 PM PDT 24 |
| Finished | Jul 31 08:05:41 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-39d6192a-6b17-4e19-a4a9-628484852b70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599660482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_large_delays.599660482 |
| Directory | /workspace/98.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.3662895652 |
| Short name | T2034 |
| Test name | |
| Test status | |
| Simulation time | 4889377180 ps |
| CPU time | 79.57 seconds |
| Started | Jul 31 08:04:41 PM PDT 24 |
| Finished | Jul 31 08:06:01 PM PDT 24 |
| Peak memory | 573748 kb |
| Host | smart-5f5e7825-5151-492c-929a-cc7bf1791fe4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662895652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_slow_rsp.3662895652 |
| Directory | /workspace/98.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.569423596 |
| Short name | T2404 |
| Test name | |
| Test status | |
| Simulation time | 48850009 ps |
| CPU time | 6.49 seconds |
| Started | Jul 31 08:04:42 PM PDT 24 |
| Finished | Jul 31 08:04:48 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-d9c6e37c-532d-4888-b9dc-9fdf72941c67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569423596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_zero_delays .569423596 |
| Directory | /workspace/98.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all.3061692367 |
| Short name | T2890 |
| Test name | |
| Test status | |
| Simulation time | 2967471485 ps |
| CPU time | 240.82 seconds |
| Started | Jul 31 08:04:45 PM PDT 24 |
| Finished | Jul 31 08:08:47 PM PDT 24 |
| Peak memory | 576756 kb |
| Host | smart-36b2a757-2c73-4c9e-8b1b-f774c5e2675b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061692367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all.3061692367 |
| Directory | /workspace/98.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.3405850887 |
| Short name | T1695 |
| Test name | |
| Test status | |
| Simulation time | 1984858057 ps |
| CPU time | 141.14 seconds |
| Started | Jul 31 08:04:45 PM PDT 24 |
| Finished | Jul 31 08:07:06 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-749df583-4360-44d7-ad1e-3ec1c473141e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405850887 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_error.3405850887 |
| Directory | /workspace/98.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.1997501478 |
| Short name | T1487 |
| Test name | |
| Test status | |
| Simulation time | 87069965 ps |
| CPU time | 79.85 seconds |
| Started | Jul 31 08:04:44 PM PDT 24 |
| Finished | Jul 31 08:06:04 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-58e930a0-0f72-4130-821f-af230508451a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997501478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all _with_rand_reset.1997501478 |
| Directory | /workspace/98.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.1661870699 |
| Short name | T1704 |
| Test name | |
| Test status | |
| Simulation time | 3582144993 ps |
| CPU time | 399.67 seconds |
| Started | Jul 31 08:04:45 PM PDT 24 |
| Finished | Jul 31 08:11:25 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-efe73a87-d5cf-4351-9b45-abab79ce0372 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661870699 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_al l_with_reset_error.1661870699 |
| Directory | /workspace/98.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_unmapped_addr.427236017 |
| Short name | T1481 |
| Test name | |
| Test status | |
| Simulation time | 476720609 ps |
| CPU time | 19.74 seconds |
| Started | Jul 31 08:04:44 PM PDT 24 |
| Finished | Jul 31 08:05:04 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-3bfbc039-5fd9-4565-9d79-2ed07e4c3d60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427236017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_unmapped_addr.427236017 |
| Directory | /workspace/98.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device.93758042 |
| Short name | T1876 |
| Test name | |
| Test status | |
| Simulation time | 1999165144 ps |
| CPU time | 81.39 seconds |
| Started | Jul 31 08:04:49 PM PDT 24 |
| Finished | Jul 31 08:06:10 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-fb4b1b08-725a-431c-9230-f8521f821ca2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93758042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device.93758042 |
| Directory | /workspace/99.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.930622383 |
| Short name | T2873 |
| Test name | |
| Test status | |
| Simulation time | 78592052 ps |
| CPU time | 6.39 seconds |
| Started | Jul 31 08:04:49 PM PDT 24 |
| Finished | Jul 31 08:04:56 PM PDT 24 |
| Peak memory | 573800 kb |
| Host | smart-51668209-5dbd-4ef2-9026-bacf539d18ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930622383 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_and_unmapped_addr .930622383 |
| Directory | /workspace/99.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_random.1751508088 |
| Short name | T2640 |
| Test name | |
| Test status | |
| Simulation time | 472535799 ps |
| CPU time | 38.39 seconds |
| Started | Jul 31 08:04:48 PM PDT 24 |
| Finished | Jul 31 08:05:26 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-f230d0e7-e517-4537-9133-a7fef7a89d6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751508088 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_random.1751508088 |
| Directory | /workspace/99.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random.1565651322 |
| Short name | T1633 |
| Test name | |
| Test status | |
| Simulation time | 608866239 ps |
| CPU time | 24.78 seconds |
| Started | Jul 31 08:04:45 PM PDT 24 |
| Finished | Jul 31 08:05:10 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-c4cdf120-c9b1-4dad-b114-4a24c2f7511f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565651322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random.1565651322 |
| Directory | /workspace/99.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_large_delays.2022999059 |
| Short name | T2472 |
| Test name | |
| Test status | |
| Simulation time | 83415161854 ps |
| CPU time | 896.77 seconds |
| Started | Jul 31 08:04:51 PM PDT 24 |
| Finished | Jul 31 08:19:48 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-bd461a95-6074-4435-8728-72874a70f42d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022999059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_large_delays.2022999059 |
| Directory | /workspace/99.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.3251561792 |
| Short name | T2887 |
| Test name | |
| Test status | |
| Simulation time | 13815813148 ps |
| CPU time | 233.59 seconds |
| Started | Jul 31 08:04:50 PM PDT 24 |
| Finished | Jul 31 08:08:44 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-af01f960-6fc0-415e-814c-8eb0ebc47e25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251561792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_slow_rsp.3251561792 |
| Directory | /workspace/99.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_zero_delays.422760698 |
| Short name | T2103 |
| Test name | |
| Test status | |
| Simulation time | 316313264 ps |
| CPU time | 25.36 seconds |
| Started | Jul 31 08:04:50 PM PDT 24 |
| Finished | Jul 31 08:05:15 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-d026f533-7807-49a5-a35b-826f93198698 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422760698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_zero_dela ys.422760698 |
| Directory | /workspace/99.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_same_source.1202691988 |
| Short name | T2778 |
| Test name | |
| Test status | |
| Simulation time | 175702750 ps |
| CPU time | 16.15 seconds |
| Started | Jul 31 08:04:50 PM PDT 24 |
| Finished | Jul 31 08:05:06 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-296432cf-96f3-493c-b304-70405ab3bbd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202691988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_same_source.1202691988 |
| Directory | /workspace/99.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke.485601228 |
| Short name | T1946 |
| Test name | |
| Test status | |
| Simulation time | 213116516 ps |
| CPU time | 8.9 seconds |
| Started | Jul 31 08:04:43 PM PDT 24 |
| Finished | Jul 31 08:04:52 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-e7ab3796-7fdd-4486-977c-9b845c45ccea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485601228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke.485601228 |
| Directory | /workspace/99.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.620528406 |
| Short name | T2368 |
| Test name | |
| Test status | |
| Simulation time | 8246766625 ps |
| CPU time | 85.62 seconds |
| Started | Jul 31 08:04:43 PM PDT 24 |
| Finished | Jul 31 08:06:08 PM PDT 24 |
| Peak memory | 574008 kb |
| Host | smart-9cde9158-e615-4556-8801-934e7c4d262c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620528406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_large_delays.620528406 |
| Directory | /workspace/99.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.136490814 |
| Short name | T2009 |
| Test name | |
| Test status | |
| Simulation time | 4992225712 ps |
| CPU time | 86.52 seconds |
| Started | Jul 31 08:04:45 PM PDT 24 |
| Finished | Jul 31 08:06:12 PM PDT 24 |
| Peak memory | 574540 kb |
| Host | smart-62b73d11-0fdd-4602-ba0a-68c33e647a1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136490814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_slow_rsp.136490814 |
| Directory | /workspace/99.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_zero_delays.2488900392 |
| Short name | T1402 |
| Test name | |
| Test status | |
| Simulation time | 46111450 ps |
| CPU time | 5.61 seconds |
| Started | Jul 31 08:04:52 PM PDT 24 |
| Finished | Jul 31 08:04:58 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-aefe47ae-b26f-4f3e-aa2f-121696adfab2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488900392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_zero_delay s.2488900392 |
| Directory | /workspace/99.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all.2076762337 |
| Short name | T2188 |
| Test name | |
| Test status | |
| Simulation time | 1248385110 ps |
| CPU time | 120.5 seconds |
| Started | Jul 31 08:04:49 PM PDT 24 |
| Finished | Jul 31 08:06:50 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-b998fe66-f4f7-440d-84c2-18ac1a196f3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076762337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all.2076762337 |
| Directory | /workspace/99.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.3972226459 |
| Short name | T2327 |
| Test name | |
| Test status | |
| Simulation time | 5455817267 ps |
| CPU time | 176.09 seconds |
| Started | Jul 31 08:04:50 PM PDT 24 |
| Finished | Jul 31 08:07:46 PM PDT 24 |
| Peak memory | 576156 kb |
| Host | smart-7417de1d-203d-4014-997e-4d161aa9c431 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972226459 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_error.3972226459 |
| Directory | /workspace/99.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.2965275422 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 3324624582 ps |
| CPU time | 601.11 seconds |
| Started | Jul 31 08:04:52 PM PDT 24 |
| Finished | Jul 31 08:14:54 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-a946322f-75cc-4fb9-ac46-418bd56ac729 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965275422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all _with_rand_reset.2965275422 |
| Directory | /workspace/99.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.1948995435 |
| Short name | T2476 |
| Test name | |
| Test status | |
| Simulation time | 950768410 ps |
| CPU time | 207.09 seconds |
| Started | Jul 31 08:04:52 PM PDT 24 |
| Finished | Jul 31 08:08:20 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-2cbbb67e-bf7f-4cf8-88e7-c2a2fe6c1d21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948995435 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_al l_with_reset_error.1948995435 |
| Directory | /workspace/99.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_unmapped_addr.1027426675 |
| Short name | T2378 |
| Test name | |
| Test status | |
| Simulation time | 78242201 ps |
| CPU time | 6.61 seconds |
| Started | Jul 31 08:04:54 PM PDT 24 |
| Finished | Jul 31 08:05:00 PM PDT 24 |
| Peak memory | 574484 kb |
| Host | smart-b4d0be13-08d0-4bbe-bd84-abf93eadb2b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027426675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_unmapped_addr.1027426675 |
| Directory | /workspace/99.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_csr_rw.1897816270 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 6609439744 ps |
| CPU time | 559.09 seconds |
| Started | Jul 31 08:06:44 PM PDT 24 |
| Finished | Jul 31 08:16:03 PM PDT 24 |
| Peak memory | 608076 kb |
| Host | smart-6041a671-203a-449d-98a7-71dc7545ee15 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897816270 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_jtag_csr_rw.1897816270 |
| Directory | /workspace/0.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_mem_access.1054455700 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 14185332510 ps |
| CPU time | 1332.92 seconds |
| Started | Jul 31 08:06:48 PM PDT 24 |
| Finished | Jul 31 08:29:02 PM PDT 24 |
| Peak memory | 607904 kb |
| Host | smart-a32d8f6a-1d68-487d-aca1-8fc52a557591 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054455700 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.1 054455700 |
| Directory | /workspace/0.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/0.chip_sival_flash_info_access.1407550664 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 3694499700 ps |
| CPU time | 388.8 seconds |
| Started | Jul 31 08:13:31 PM PDT 24 |
| Finished | Jul 31 08:20:02 PM PDT 24 |
| Peak memory | 609908 kb |
| Host | smart-c7b4cd9b-7793-4ae7-8f6b-7bbfd99ff7e6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1407550664 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.1407550664 |
| Directory | /workspace/0.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc.445066782 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 2965470680 ps |
| CPU time | 302.21 seconds |
| Started | Jul 31 08:16:16 PM PDT 24 |
| Finished | Jul 31 08:21:18 PM PDT 24 |
| Peak memory | 609740 kb |
| Host | smart-f888d31c-4c07-4232-9ab1-7f4a472cf81c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445066782 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.445066782 |
| Directory | /workspace/0.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2995208480 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 2859721412 ps |
| CPU time | 311.41 seconds |
| Started | Jul 31 08:14:22 PM PDT 24 |
| Finished | Jul 31 08:19:34 PM PDT 24 |
| Peak memory | 609728 kb |
| Host | smart-066c2caf-38b2-4c9f-b679-8c7f09c2f738 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995 208480 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.2995208480 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3430201710 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 3437385298 ps |
| CPU time | 291.85 seconds |
| Started | Jul 31 08:17:26 PM PDT 24 |
| Finished | Jul 31 08:22:18 PM PDT 24 |
| Peak memory | 608732 kb |
| Host | smart-06dee43d-1251-443a-8e3e-6f3906da7f6e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430201710 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.3430201710 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_entropy.1604056351 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 2256827380 ps |
| CPU time | 221.48 seconds |
| Started | Jul 31 08:13:28 PM PDT 24 |
| Finished | Jul 31 08:17:09 PM PDT 24 |
| Peak memory | 609780 kb |
| Host | smart-543bb53f-3baa-4b42-808b-037680974aa3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604056351 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_entropy.1604056351 |
| Directory | /workspace/0.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_idle.1413746265 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 3191160792 ps |
| CPU time | 304.95 seconds |
| Started | Jul 31 08:13:37 PM PDT 24 |
| Finished | Jul 31 08:18:42 PM PDT 24 |
| Peak memory | 609784 kb |
| Host | smart-a0d832cf-bf78-4625-b684-611dd8f29b48 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413746265 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.1413746265 |
| Directory | /workspace/0.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_masking_off.3202473259 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 3416022021 ps |
| CPU time | 387 seconds |
| Started | Jul 31 08:14:43 PM PDT 24 |
| Finished | Jul 31 08:21:10 PM PDT 24 |
| Peak memory | 610612 kb |
| Host | smart-53ec593f-9b62-4e62-8414-a4d377a69da8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202473259 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_masking_off.3202473259 |
| Directory | /workspace/0.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_smoketest.1455240986 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 3373717884 ps |
| CPU time | 291.1 seconds |
| Started | Jul 31 08:15:59 PM PDT 24 |
| Finished | Jul 31 08:20:52 PM PDT 24 |
| Peak memory | 609628 kb |
| Host | smart-ecddb21e-e090-4fb2-a11b-027e8d58fb9f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455240986 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_smoketest.1455240986 |
| Directory | /workspace/0.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_entropy.2145574602 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 3161253065 ps |
| CPU time | 277.11 seconds |
| Started | Jul 31 08:12:59 PM PDT 24 |
| Finished | Jul 31 08:17:36 PM PDT 24 |
| Peak memory | 609760 kb |
| Host | smart-760f00d1-e993-4b63-b204-90f11cd7f005 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2145574602 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.2145574602 |
| Directory | /workspace/0.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_escalation.2950937588 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 5707570920 ps |
| CPU time | 645.83 seconds |
| Started | Jul 31 08:17:33 PM PDT 24 |
| Finished | Jul 31 08:28:19 PM PDT 24 |
| Peak memory | 619636 kb |
| Host | smart-dbadf104-bcf3-470c-9acc-b6748b2b3d0b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=2950937588 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.2950937588 |
| Directory | /workspace/0.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.474936865 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 8511002000 ps |
| CPU time | 1842.6 seconds |
| Started | Jul 31 08:13:38 PM PDT 24 |
| Finished | Jul 31 08:44:21 PM PDT 24 |
| Peak memory | 609916 kb |
| Host | smart-cf774055-b125-4eb1-b9d5-af5870869160 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474936865 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_toggle.474936865 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1329812212 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 13128723868 ps |
| CPU time | 1696.68 seconds |
| Started | Jul 31 08:13:41 PM PDT 24 |
| Finished | Jul 31 08:41:58 PM PDT 24 |
| Peak memory | 611056 kb |
| Host | smart-ce4f49f5-655e-4890-8226-2221c44471b4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329812212 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_sleep_mode_pings.1329812212 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.3748896160 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 7820890700 ps |
| CPU time | 1420.9 seconds |
| Started | Jul 31 08:14:52 PM PDT 24 |
| Finished | Jul 31 08:38:34 PM PDT 24 |
| Peak memory | 610104 kb |
| Host | smart-a2a669e6-b763-47ee-bd87-e40fad9b7b89 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3748896160 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_ok.3748896160 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1862375071 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 3287968528 ps |
| CPU time | 303.54 seconds |
| Started | Jul 31 08:15:21 PM PDT 24 |
| Finished | Jul 31 08:20:25 PM PDT 24 |
| Peak memory | 609700 kb |
| Host | smart-8d20e5c4-20fc-4e02-a5de-63995b94d52e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1862375071 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.1862375071 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2548904690 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 255874128080 ps |
| CPU time | 12008.7 seconds |
| Started | Jul 31 08:16:09 PM PDT 24 |
| Finished | Jul 31 11:36:20 PM PDT 24 |
| Peak memory | 610608 kb |
| Host | smart-4e173324-4d58-4f7e-bd50-8cc8887c61fb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2548904690 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2548904690 |
| Directory | /workspace/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_test.692020104 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 3569688476 ps |
| CPU time | 329.76 seconds |
| Started | Jul 31 08:12:28 PM PDT 24 |
| Finished | Jul 31 08:17:58 PM PDT 24 |
| Peak memory | 609984 kb |
| Host | smart-2f9798b8-aecf-4e8f-8231-9108a382eb00 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692020104 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_alert_test.692020104 |
| Directory | /workspace/0.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_irq.425285052 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 4087344000 ps |
| CPU time | 343.03 seconds |
| Started | Jul 31 08:15:57 PM PDT 24 |
| Finished | Jul 31 08:21:41 PM PDT 24 |
| Peak memory | 609572 kb |
| Host | smart-329bc855-1507-4110-a04e-cf1f378dfa60 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425285052 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.425285052 |
| Directory | /workspace/0.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.101874765 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 7856550890 ps |
| CPU time | 611.32 seconds |
| Started | Jul 31 08:13:51 PM PDT 24 |
| Finished | Jul 31 08:24:03 PM PDT 24 |
| Peak memory | 610396 kb |
| Host | smart-88e78a88-a706-44cb-b9e2-537bd7d68bca |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=101874765 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.101874765 |
| Directory | /workspace/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.3656960495 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 3337760420 ps |
| CPU time | 297.79 seconds |
| Started | Jul 31 08:16:54 PM PDT 24 |
| Finished | Jul 31 08:21:52 PM PDT 24 |
| Peak memory | 609692 kb |
| Host | smart-f47d839e-9dda-41a5-9b4b-1ef12ecc7d97 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656960495 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_aon_timer_smoketest.3656960495 |
| Directory | /workspace/0.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2847635712 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 6564758078 ps |
| CPU time | 475.51 seconds |
| Started | Jul 31 08:13:39 PM PDT 24 |
| Finished | Jul 31 08:21:34 PM PDT 24 |
| Peak memory | 610260 kb |
| Host | smart-ced5edd7-cc74-4237-be7e-80a3cb230054 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2847635712 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.2847635712 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3624774444 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 4284888734 ps |
| CPU time | 583.16 seconds |
| Started | Jul 31 08:17:35 PM PDT 24 |
| Finished | Jul 31 08:27:18 PM PDT 24 |
| Peak memory | 609044 kb |
| Host | smart-378325b3-bd79-4c68-89b3-1e886e502871 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3624774444 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.3624774444 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_ast_clk_outputs.2524993086 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 8832749600 ps |
| CPU time | 1076.31 seconds |
| Started | Jul 31 08:16:14 PM PDT 24 |
| Finished | Jul 31 08:34:11 PM PDT 24 |
| Peak memory | 617056 kb |
| Host | smart-aa4c2046-c4c8-447e-840b-f7b5a66a26c8 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524993086 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.2524993086 |
| Directory | /workspace/0.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.1789278237 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 27638217708 ps |
| CPU time | 4740.12 seconds |
| Started | Jul 31 08:15:29 PM PDT 24 |
| Finished | Jul 31 09:34:30 PM PDT 24 |
| Peak memory | 610736 kb |
| Host | smart-f0339a92-7599-4e6e-8d95-cc51ce646f84 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789278237 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_rst_inputs.1789278237 |
| Directory | /workspace/0.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2960250423 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 10254015024 ps |
| CPU time | 841.94 seconds |
| Started | Jul 31 08:14:09 PM PDT 24 |
| Finished | Jul 31 08:28:11 PM PDT 24 |
| Peak memory | 620504 kb |
| Host | smart-1f89508d-4884-4d1d-9c1b-3153ecbc1c51 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2960250423 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.2960250423 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3861906867 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 4288808262 ps |
| CPU time | 642.03 seconds |
| Started | Jul 31 08:15:17 PM PDT 24 |
| Finished | Jul 31 08:25:59 PM PDT 24 |
| Peak memory | 613136 kb |
| Host | smart-92533e80-a4f2-42bb-bdc8-66b10fcf39e3 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861906867 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.3861906867 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.777953559 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 3759652716 ps |
| CPU time | 598.02 seconds |
| Started | Jul 31 08:14:51 PM PDT 24 |
| Finished | Jul 31 08:24:50 PM PDT 24 |
| Peak memory | 612884 kb |
| Host | smart-5f109849-060f-407a-bcad-5de9903ab9f7 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777953559 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0. chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.777953559 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.568468580 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 5219983668 ps |
| CPU time | 758.74 seconds |
| Started | Jul 31 08:18:36 PM PDT 24 |
| Finished | Jul 31 08:31:15 PM PDT 24 |
| Peak memory | 612900 kb |
| Host | smart-3f930be9-df46-4f34-9a14-9d7d88d035b6 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568468580 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_cl kmgr_external_clk_src_for_sw_slow_dev.568468580 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3271481567 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 4905219300 ps |
| CPU time | 779.59 seconds |
| Started | Jul 31 08:13:22 PM PDT 24 |
| Finished | Jul 31 08:26:22 PM PDT 24 |
| Peak memory | 612904 kb |
| Host | smart-065a639e-3eb1-4438-b991-6d883d61ffe5 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271481567 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.3271481567 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1547058769 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 5033989052 ps |
| CPU time | 624.82 seconds |
| Started | Jul 31 08:15:11 PM PDT 24 |
| Finished | Jul 31 08:25:37 PM PDT 24 |
| Peak memory | 613140 kb |
| Host | smart-6e09cb97-67e1-4820-b381-77d35bf8c076 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547058769 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1547058769 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter.3748874509 |
| Short name | T1380 |
| Test name | |
| Test status | |
| Simulation time | 3512022383 ps |
| CPU time | 293.4 seconds |
| Started | Jul 31 08:16:04 PM PDT 24 |
| Finished | Jul 31 08:20:58 PM PDT 24 |
| Peak memory | 609636 kb |
| Host | smart-3521a6c3-8406-4114-b6f3-10535be6f3f6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748874509 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_clkmgr_jitter.3748874509 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.1250094692 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 3149698820 ps |
| CPU time | 442.87 seconds |
| Started | Jul 31 08:16:52 PM PDT 24 |
| Finished | Jul 31 08:24:16 PM PDT 24 |
| Peak memory | 609632 kb |
| Host | smart-e7339b39-2fc9-4207-b65e-d70776d9d3cb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250094692 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_frequency.1250094692 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1269351609 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 3034460087 ps |
| CPU time | 283.79 seconds |
| Started | Jul 31 08:14:30 PM PDT 24 |
| Finished | Jul 31 08:19:14 PM PDT 24 |
| Peak memory | 609676 kb |
| Host | smart-ea01146c-e8e6-4d78-b150-5f529f6fb123 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269351609 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.1269351609 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1774198121 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 4852378962 ps |
| CPU time | 474.4 seconds |
| Started | Jul 31 08:13:42 PM PDT 24 |
| Finished | Jul 31 08:21:37 PM PDT 24 |
| Peak memory | 610468 kb |
| Host | smart-9f35f2b7-5fe8-47d8-8ba4-484b576699ec |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774198121 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.1774198121 |
| Directory | /workspace/0.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2408194094 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 3932780724 ps |
| CPU time | 515.65 seconds |
| Started | Jul 31 08:14:01 PM PDT 24 |
| Finished | Jul 31 08:22:36 PM PDT 24 |
| Peak memory | 610092 kb |
| Host | smart-4bbbd522-4f4e-438b-9376-a409b6f34c8a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408194094 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.2408194094 |
| Directory | /workspace/0.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.122155148 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 5503703680 ps |
| CPU time | 564.87 seconds |
| Started | Jul 31 08:15:33 PM PDT 24 |
| Finished | Jul 31 08:24:59 PM PDT 24 |
| Peak memory | 610440 kb |
| Host | smart-8a0a2dcf-27e2-4637-a30c-a43e78041962 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122155148 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.122155148 |
| Directory | /workspace/0.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2018155045 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 5281387524 ps |
| CPU time | 447.84 seconds |
| Started | Jul 31 08:15:47 PM PDT 24 |
| Finished | Jul 31 08:23:16 PM PDT 24 |
| Peak memory | 610392 kb |
| Host | smart-c137ff96-802a-40c5-a72a-319685e91651 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018155045 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_otbn_trans.2018155045 |
| Directory | /workspace/0.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.2045612335 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 12210763950 ps |
| CPU time | 997.03 seconds |
| Started | Jul 31 08:16:11 PM PDT 24 |
| Finished | Jul 31 08:32:48 PM PDT 24 |
| Peak memory | 610284 kb |
| Host | smart-b1432326-915a-40fd-8d05-30ca0ddbe07c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045612335 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.2045612335 |
| Directory | /workspace/0.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.2779439257 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 3823135804 ps |
| CPU time | 440.93 seconds |
| Started | Jul 31 08:15:53 PM PDT 24 |
| Finished | Jul 31 08:23:14 PM PDT 24 |
| Peak memory | 609888 kb |
| Host | smart-7ec57011-6a3e-4a43-afc8-be73f1f00540 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779439257 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.2779439257 |
| Directory | /workspace/0.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.300921829 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 4463567116 ps |
| CPU time | 591.38 seconds |
| Started | Jul 31 08:14:32 PM PDT 24 |
| Finished | Jul 31 08:24:24 PM PDT 24 |
| Peak memory | 610288 kb |
| Host | smart-b68c556b-ddd5-45a6-94e2-207414929902 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300921829 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.300921829 |
| Directory | /workspace/0.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.3006799843 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 2789853882 ps |
| CPU time | 248.15 seconds |
| Started | Jul 31 08:15:59 PM PDT 24 |
| Finished | Jul 31 08:20:08 PM PDT 24 |
| Peak memory | 608496 kb |
| Host | smart-0af52720-beac-4f45-ab9d-3abb48cfe8d9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006799843 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_clkmgr_smoketest.3006799843 |
| Directory | /workspace/0.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_coremark.274192676 |
| Short name | T1357 |
| Test name | |
| Test status | |
| Simulation time | 71717350680 ps |
| CPU time | 14812.3 seconds |
| Started | Jul 31 08:15:15 PM PDT 24 |
| Finished | Aug 01 12:22:10 AM PDT 24 |
| Peak memory | 609440 kb |
| Host | smart-cb8f10fb-6e2e-476f-b0dc-4b98ba9d33c3 |
| User | root |
| Command | /workspace/default/simv +en_uart_logger=1 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=coremark_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=274192676 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_coremark.274192676 |
| Directory | /workspace/0.chip_sw_coremark/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.3869041061 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 18042698888 ps |
| CPU time | 4492.97 seconds |
| Started | Jul 31 08:19:31 PM PDT 24 |
| Finished | Jul 31 09:34:25 PM PDT 24 |
| Peak memory | 610280 kb |
| Host | smart-0cef0b96-64cf-4f57-a27a-fa9b071c4e98 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869041061 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency.3869041061 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.3469125731 |
| Short name | T1366 |
| Test name | |
| Test status | |
| Simulation time | 18467709518 ps |
| CPU time | 3363.82 seconds |
| Started | Jul 31 08:14:01 PM PDT 24 |
| Finished | Jul 31 09:10:06 PM PDT 24 |
| Peak memory | 610408 kb |
| Host | smart-0d32e700-0c44-42d6-b514-a5ca30bfb75e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3469125731 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency_reduced_freq.3469125731 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1295908692 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 4519058358 ps |
| CPU time | 522.14 seconds |
| Started | Jul 31 08:16:04 PM PDT 24 |
| Finished | Jul 31 08:24:47 PM PDT 24 |
| Peak memory | 609460 kb |
| Host | smart-a65b69c4-2f99-453d-93e5-802c5521e164 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12959 08692 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.1295908692 |
| Directory | /workspace/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_kat_test.129181019 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 2963576712 ps |
| CPU time | 231.66 seconds |
| Started | Jul 31 08:13:43 PM PDT 24 |
| Finished | Jul 31 08:17:35 PM PDT 24 |
| Peak memory | 609616 kb |
| Host | smart-e63d3a51-a009-4ae2-927b-635ac96ca062 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129181019 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.129181019 |
| Directory | /workspace/0.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1670625884 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 5881355176 ps |
| CPU time | 618.26 seconds |
| Started | Jul 31 08:14:50 PM PDT 24 |
| Finished | Jul 31 08:25:10 PM PDT 24 |
| Peak memory | 611084 kb |
| Host | smart-4441bb4d-1ccf-452e-9e88-f024f10456c4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670625884 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csr ng_lc_hw_debug_en_test.1670625884 |
| Directory | /workspace/0.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_smoketest.3283927479 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 2277806800 ps |
| CPU time | 201.37 seconds |
| Started | Jul 31 08:17:21 PM PDT 24 |
| Finished | Jul 31 08:20:42 PM PDT 24 |
| Peak memory | 609644 kb |
| Host | smart-98786d55-81aa-4c61-ae6f-9eeaea1f7ceb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283927479 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_csrng_smoketest.3283927479 |
| Directory | /workspace/0.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_auto_mode.319795081 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 3739169488 ps |
| CPU time | 891.69 seconds |
| Started | Jul 31 08:13:25 PM PDT 24 |
| Finished | Jul 31 08:28:17 PM PDT 24 |
| Peak memory | 610056 kb |
| Host | smart-1b69cc28-0155-42c0-a132-42d5481687d8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319795081 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_a uto_mode.319795081 |
| Directory | /workspace/0.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2008848812 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 6164769900 ps |
| CPU time | 1347.48 seconds |
| Started | Jul 31 08:14:23 PM PDT 24 |
| Finished | Jul 31 08:36:51 PM PDT 24 |
| Peak memory | 610684 kb |
| Host | smart-a1700286-247a-4bac-9a9b-133b0801a260 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2008848812 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.2008848812 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3201015460 |
| Short name | T1320 |
| Test name | |
| Test status | |
| Simulation time | 7098285224 ps |
| CPU time | 1049.11 seconds |
| Started | Jul 31 08:13:08 PM PDT 24 |
| Finished | Jul 31 08:30:37 PM PDT 24 |
| Peak memory | 610936 kb |
| Host | smart-107ddeff-c7c9-4116-b730-3d2f2824d9fe |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201015460 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.3201015460 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_kat.438342059 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 3461083376 ps |
| CPU time | 767.78 seconds |
| Started | Jul 31 08:15:04 PM PDT 24 |
| Finished | Jul 31 08:27:53 PM PDT 24 |
| Peak memory | 615728 kb |
| Host | smart-03b41514-2584-4265-a4e8-b020e171cafa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438342059 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_edn_kat.438342059 |
| Directory | /workspace/0.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_sw_mode.3139576493 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 5663755280 ps |
| CPU time | 1312.46 seconds |
| Started | Jul 31 08:14:39 PM PDT 24 |
| Finished | Jul 31 08:36:32 PM PDT 24 |
| Peak memory | 609960 kb |
| Host | smart-d54afce0-b486-4cdb-92b9-b2bf20c78366 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139576493 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_sw_mode.3139576493 |
| Directory | /workspace/0.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.235379550 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 2527192286 ps |
| CPU time | 185.12 seconds |
| Started | Jul 31 08:17:00 PM PDT 24 |
| Finished | Jul 31 08:20:05 PM PDT 24 |
| Peak memory | 608296 kb |
| Host | smart-79c015b0-fc41-4a6a-ae9b-9c0b49e5ac06 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23 5379550 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.235379550 |
| Directory | /workspace/0.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_csrng.3616360312 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 6180894248 ps |
| CPU time | 1360.88 seconds |
| Started | Jul 31 08:14:01 PM PDT 24 |
| Finished | Jul 31 08:36:42 PM PDT 24 |
| Peak memory | 609308 kb |
| Host | smart-dc32dadd-9d52-437b-add4-d0ad8cf3242c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3616360312 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.3616360312 |
| Directory | /workspace/0.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.24256248 |
| Short name | T1341 |
| Test name | |
| Test status | |
| Simulation time | 2194577992 ps |
| CPU time | 176.95 seconds |
| Started | Jul 31 08:14:43 PM PDT 24 |
| Finished | Jul 31 08:17:41 PM PDT 24 |
| Peak memory | 608520 kb |
| Host | smart-437e5a06-dace-41bd-a581-a311ff6996a3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24256248 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.24256248 |
| Directory | /workspace/0.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.2012284764 |
| Short name | T1332 |
| Test name | |
| Test status | |
| Simulation time | 3347935308 ps |
| CPU time | 564.26 seconds |
| Started | Jul 31 08:15:55 PM PDT 24 |
| Finished | Jul 31 08:25:20 PM PDT 24 |
| Peak memory | 608900 kb |
| Host | smart-790c7216-ba6e-450a-93e6-2a0bece34654 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2012284764 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.2012284764 |
| Directory | /workspace/0.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_concurrency.1404753715 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 2729065646 ps |
| CPU time | 363.82 seconds |
| Started | Jul 31 08:13:27 PM PDT 24 |
| Finished | Jul 31 08:19:32 PM PDT 24 |
| Peak memory | 609500 kb |
| Host | smart-fba3ede7-ebef-41d6-b14d-2b1526d48f38 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404753715 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_example_concurrency.1404753715 |
| Directory | /workspace/0.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_flash.2839350637 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 2803842684 ps |
| CPU time | 249.36 seconds |
| Started | Jul 31 08:11:17 PM PDT 24 |
| Finished | Jul 31 08:15:26 PM PDT 24 |
| Peak memory | 609620 kb |
| Host | smart-f46e8b6f-0576-48f6-8e21-29759bcd6ac8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839350637 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_flash.2839350637 |
| Directory | /workspace/0.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_rom.21488289 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 2499614964 ps |
| CPU time | 112.77 seconds |
| Started | Jul 31 08:12:20 PM PDT 24 |
| Finished | Jul 31 08:14:13 PM PDT 24 |
| Peak memory | 610000 kb |
| Host | smart-c113160b-f5c8-40f6-a531-b29609deec9d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21488289 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_example_rom.21488289 |
| Directory | /workspace/0.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.2798568502 |
| Short name | T1331 |
| Test name | |
| Test status | |
| Simulation time | 58484061744 ps |
| CPU time | 10436.5 seconds |
| Started | Jul 31 08:14:07 PM PDT 24 |
| Finished | Jul 31 11:08:05 PM PDT 24 |
| Peak memory | 624744 kb |
| Host | smart-bbad288f-eccd-49d8-be22-d314bb1c8856 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=2798568502 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_exit_test_unlocked_bootstrap.2798568502 |
| Directory | /workspace/0.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_crash_alert.4146853540 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 5136618522 ps |
| CPU time | 720.59 seconds |
| Started | Jul 31 08:15:27 PM PDT 24 |
| Finished | Jul 31 08:27:28 PM PDT 24 |
| Peak memory | 611300 kb |
| Host | smart-d66427d8-8656-4c81-8b3e-046fe68dcc2f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=4146853540 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.4146853540 |
| Directory | /workspace/0.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access.620853212 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 5389942746 ps |
| CPU time | 1055.43 seconds |
| Started | Jul 31 08:14:01 PM PDT 24 |
| Finished | Jul 31 08:31:37 PM PDT 24 |
| Peak memory | 610096 kb |
| Host | smart-006f6899-cfd0-4935-bd08-f4edf5a3500b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620853212 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_flash_ctrl_access.620853212 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3906268285 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 6260783874 ps |
| CPU time | 1181.72 seconds |
| Started | Jul 31 08:14:01 PM PDT 24 |
| Finished | Jul 31 08:33:44 PM PDT 24 |
| Peak memory | 610056 kb |
| Host | smart-63e44de6-2d95-410f-90d0-d97dad6d94ea |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906268285 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en.3906268285 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.573541975 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 7990413959 ps |
| CPU time | 1336.89 seconds |
| Started | Jul 31 08:14:50 PM PDT 24 |
| Finished | Jul 31 08:37:07 PM PDT 24 |
| Peak memory | 610196 kb |
| Host | smart-a1171c1b-d809-4aa5-82da-fae325b4c3ac |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573541975 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.573541975 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.1893361957 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 6017567296 ps |
| CPU time | 1351.45 seconds |
| Started | Jul 31 08:12:35 PM PDT 24 |
| Finished | Jul 31 08:35:07 PM PDT 24 |
| Peak memory | 610096 kb |
| Host | smart-34c9bc4e-d50b-4aa9-be03-370f0d5741d8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893361957 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_flash_ctrl_clock_freqs.1893361957 |
| Directory | /workspace/0.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.1953907956 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 3531689056 ps |
| CPU time | 342.26 seconds |
| Started | Jul 31 08:13:37 PM PDT 24 |
| Finished | Jul 31 08:19:19 PM PDT 24 |
| Peak memory | 609680 kb |
| Host | smart-a8ea87b9-0bb5-47b2-936a-e983eb6ef5e3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953907956 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_idle_low_power.1953907956 |
| Directory | /workspace/0.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.435509977 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 5888998814 ps |
| CPU time | 658.96 seconds |
| Started | Jul 31 08:13:21 PM PDT 24 |
| Finished | Jul 31 08:24:21 PM PDT 24 |
| Peak memory | 610900 kb |
| Host | smart-9ff68175-beb9-4865-b0a6-35905010391f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43 5509977 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_lc_rw_en.435509977 |
| Directory | /workspace/0.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.674395229 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 5969111024 ps |
| CPU time | 1129.08 seconds |
| Started | Jul 31 08:16:46 PM PDT 24 |
| Finished | Jul 31 08:35:36 PM PDT 24 |
| Peak memory | 610088 kb |
| Host | smart-585395f5-da5c-4b98-967f-019f89598272 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674395229 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_mem_protection.674395229 |
| Directory | /workspace/0.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3757221825 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 4969249822 ps |
| CPU time | 831.35 seconds |
| Started | Jul 31 08:20:19 PM PDT 24 |
| Finished | Jul 31 08:34:10 PM PDT 24 |
| Peak memory | 610052 kb |
| Host | smart-23f5459c-61af-4ab5-b0b6-5a10da530188 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3757221825 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3757221825 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.1644338044 |
| Short name | T1343 |
| Test name | |
| Test status | |
| Simulation time | 3586785124 ps |
| CPU time | 325.7 seconds |
| Started | Jul 31 08:16:00 PM PDT 24 |
| Finished | Jul 31 08:21:26 PM PDT 24 |
| Peak memory | 608880 kb |
| Host | smart-bb7a0dd4-aacf-49ee-a2b6-a05a56a20339 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644338 044 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_write_clear.1644338044 |
| Directory | /workspace/0.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init.388120704 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 19149789316 ps |
| CPU time | 2089.29 seconds |
| Started | Jul 31 08:12:53 PM PDT 24 |
| Finished | Jul 31 08:47:43 PM PDT 24 |
| Peak memory | 613120 kb |
| Host | smart-f65dbd6a-2859-46dc-8d3d-61d5f0c298e8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388120704 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init.388120704 |
| Directory | /workspace/0.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.2551324393 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 3001376900 ps |
| CPU time | 158.47 seconds |
| Started | Jul 31 08:21:46 PM PDT 24 |
| Finished | Jul 31 08:24:25 PM PDT 24 |
| Peak memory | 609744 kb |
| Host | smart-31ac3c9f-0d35-4ebc-adb1-5ecded5c92f1 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2551324393 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.2551324393 |
| Directory | /workspace/0.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio_smoketest.2128104828 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 2608052403 ps |
| CPU time | 282.46 seconds |
| Started | Jul 31 08:20:35 PM PDT 24 |
| Finished | Jul 31 08:25:17 PM PDT 24 |
| Peak memory | 608936 kb |
| Host | smart-ce1417ee-ce0a-4441-b32b-03001dfd417a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128104828 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_gpio_smoketest.2128104828 |
| Directory | /workspace/0.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc.3085754195 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 2507770300 ps |
| CPU time | 267.74 seconds |
| Started | Jul 31 08:18:40 PM PDT 24 |
| Finished | Jul 31 08:23:08 PM PDT 24 |
| Peak memory | 609760 kb |
| Host | smart-2731e67b-44bb-4362-8ad9-943fe9cfd328 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085754195 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc.3085754195 |
| Directory | /workspace/0.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_idle.2622378219 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 3303646920 ps |
| CPU time | 248.44 seconds |
| Started | Jul 31 08:15:59 PM PDT 24 |
| Finished | Jul 31 08:20:08 PM PDT 24 |
| Peak memory | 609772 kb |
| Host | smart-dffaf720-af8a-4304-9a8a-a4f44c9cebd3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622378219 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_hmac_enc_idle.2622378219 |
| Directory | /workspace/0.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.3840866196 |
| Short name | T1356 |
| Test name | |
| Test status | |
| Simulation time | 3511861411 ps |
| CPU time | 210.96 seconds |
| Started | Jul 31 08:15:16 PM PDT 24 |
| Finished | Jul 31 08:18:47 PM PDT 24 |
| Peak memory | 609732 kb |
| Host | smart-a563784d-458d-4829-8df4-abc86fec9fc7 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840866196 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en.3840866196 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1840635387 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 3092988392 ps |
| CPU time | 272.67 seconds |
| Started | Jul 31 08:15:54 PM PDT 24 |
| Finished | Jul 31 08:20:27 PM PDT 24 |
| Peak memory | 609876 kb |
| Host | smart-5e63f9d9-2d5c-43fc-930c-5bc5c950120e |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840635387 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.1840635387 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_multistream.3220292062 |
| Short name | T1375 |
| Test name | |
| Test status | |
| Simulation time | 8384737080 ps |
| CPU time | 1945.6 seconds |
| Started | Jul 31 08:17:15 PM PDT 24 |
| Finished | Jul 31 08:49:41 PM PDT 24 |
| Peak memory | 610108 kb |
| Host | smart-7be40889-e743-45ef-b4fb-26a0a296cc4c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220292062 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_hmac_multistream.3220292062 |
| Directory | /workspace/0.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_oneshot.4123674099 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 2605676074 ps |
| CPU time | 277.74 seconds |
| Started | Jul 31 08:12:50 PM PDT 24 |
| Finished | Jul 31 08:17:28 PM PDT 24 |
| Peak memory | 609700 kb |
| Host | smart-4f60d30b-7941-44b4-8b74-2c2b03334673 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123674099 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_oneshot.4123674099 |
| Directory | /workspace/0.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_smoketest.172073207 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 3378430868 ps |
| CPU time | 441.69 seconds |
| Started | Jul 31 08:21:04 PM PDT 24 |
| Finished | Jul 31 08:28:26 PM PDT 24 |
| Peak memory | 608504 kb |
| Host | smart-990aa5be-276c-4c27-a95c-1f04e5b61826 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172073207 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_smoketest.172073207 |
| Directory | /workspace/0.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.1299746788 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 3974402736 ps |
| CPU time | 569.16 seconds |
| Started | Jul 31 08:16:46 PM PDT 24 |
| Finished | Jul 31 08:26:16 PM PDT 24 |
| Peak memory | 610268 kb |
| Host | smart-60734f30-2b5a-466f-b84e-37e8bf5d7d87 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299746788 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_i2c_device_tx_rx.1299746788 |
| Directory | /workspace/0.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.4154019345 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 5440189264 ps |
| CPU time | 894.5 seconds |
| Started | Jul 31 08:15:03 PM PDT 24 |
| Finished | Jul 31 08:29:57 PM PDT 24 |
| Peak memory | 609200 kb |
| Host | smart-64c76666-de28-4e9d-9206-d1a0941b606b |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154019345 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx.4154019345 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.4049181830 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 5126654216 ps |
| CPU time | 938.1 seconds |
| Started | Jul 31 08:15:15 PM PDT 24 |
| Finished | Jul 31 08:30:53 PM PDT 24 |
| Peak memory | 609232 kb |
| Host | smart-2688f652-c1cb-43e7-8e7b-aad8fb161efd |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049181830 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.4049181830 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_inject_scramble_seed.552826284 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 65522268741 ps |
| CPU time | 11304.3 seconds |
| Started | Jul 31 08:15:00 PM PDT 24 |
| Finished | Jul 31 11:23:25 PM PDT 24 |
| Peak memory | 624760 kb |
| Host | smart-d3d0a042-b676-4a6f-a7c4-79a72cc6cb94 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=552826284 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.552826284 |
| Directory | /workspace/0.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.311197230 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 12300739936 ps |
| CPU time | 2938.44 seconds |
| Started | Jul 31 08:13:57 PM PDT 24 |
| Finished | Jul 31 09:02:56 PM PDT 24 |
| Peak memory | 618056 kb |
| Host | smart-e6ce9db2-0f13-401e-b179-307d40b41925 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111 97230 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation.311197230 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.2053177849 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 8032862721 ps |
| CPU time | 1258.83 seconds |
| Started | Jul 31 08:16:28 PM PDT 24 |
| Finished | Jul 31 08:37:28 PM PDT 24 |
| Peak memory | 617968 kb |
| Host | smart-f20f4a00-30b9-416a-8399-22ed296472d1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2053177849 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en.2053177849 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.273185127 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 7368254860 ps |
| CPU time | 863.56 seconds |
| Started | Jul 31 08:15:53 PM PDT 24 |
| Finished | Jul 31 08:30:17 PM PDT 24 |
| Peak memory | 617692 kb |
| Host | smart-d0f18d56-6fff-4091-b6ff-c54c5b826e49 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=273185127 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en_ reduced_freq.273185127 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.2966457713 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 9033349928 ps |
| CPU time | 1631.59 seconds |
| Started | Jul 31 08:14:56 PM PDT 24 |
| Finished | Jul 31 08:42:09 PM PDT 24 |
| Peak memory | 616632 kb |
| Host | smart-b572eb2d-c62d-4efa-898e-49d03df0fc9b |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2966457713 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_prod.2966457713 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.2104978544 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 7287407214 ps |
| CPU time | 1408.45 seconds |
| Started | Jul 31 08:18:44 PM PDT 24 |
| Finished | Jul 31 08:42:14 PM PDT 24 |
| Peak memory | 609896 kb |
| Host | smart-5abae5b7-bd57-4200-8b38-4edc91d6a26a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21049 78544 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.2104978544 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.486820993 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 13257927732 ps |
| CPU time | 3616.4 seconds |
| Started | Jul 31 08:17:33 PM PDT 24 |
| Finished | Jul 31 09:17:50 PM PDT 24 |
| Peak memory | 609648 kb |
| Host | smart-dc1a0fe7-5383-40e0-9d9a-35b0b217e8d8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48682 0993 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.486820993 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_app_rom.3469264704 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 3071118590 ps |
| CPU time | 304.24 seconds |
| Started | Jul 31 08:19:14 PM PDT 24 |
| Finished | Jul 31 08:24:19 PM PDT 24 |
| Peak memory | 609408 kb |
| Host | smart-2f680cb4-6a8a-49e4-a1ad-58eea62d723d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469264704 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_kmac_app_rom.3469264704 |
| Directory | /workspace/0.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_entropy.1369907370 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 2657791536 ps |
| CPU time | 243.54 seconds |
| Started | Jul 31 08:12:30 PM PDT 24 |
| Finished | Jul 31 08:16:35 PM PDT 24 |
| Peak memory | 609680 kb |
| Host | smart-c598343a-2a8b-4175-a839-53c1f53aa07b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369907370 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_kmac_entropy.1369907370 |
| Directory | /workspace/0.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_idle.2424446325 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 2873126788 ps |
| CPU time | 245 seconds |
| Started | Jul 31 08:13:59 PM PDT 24 |
| Finished | Jul 31 08:18:04 PM PDT 24 |
| Peak memory | 609584 kb |
| Host | smart-3c91f767-7208-4e1a-a3c2-e9533f8074a6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424446325 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_idle.2424446325 |
| Directory | /workspace/0.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.715988788 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 3103787674 ps |
| CPU time | 217.48 seconds |
| Started | Jul 31 08:15:29 PM PDT 24 |
| Finished | Jul 31 08:19:08 PM PDT 24 |
| Peak memory | 609720 kb |
| Host | smart-173e6f27-f15a-45ab-a6b4-cb6974c28a6b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715988788 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_kmac_mode_cshake.715988788 |
| Directory | /workspace/0.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.531302788 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 2969953476 ps |
| CPU time | 403.23 seconds |
| Started | Jul 31 08:15:40 PM PDT 24 |
| Finished | Jul 31 08:22:24 PM PDT 24 |
| Peak memory | 609584 kb |
| Host | smart-889b0557-a491-4640-8300-d27644dbfbf2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531302788 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_kmac_mode_kmac.531302788 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.3422927142 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 3381863869 ps |
| CPU time | 268.11 seconds |
| Started | Jul 31 08:16:33 PM PDT 24 |
| Finished | Jul 31 08:21:01 PM PDT 24 |
| Peak memory | 609704 kb |
| Host | smart-9c6c37ef-79df-47ed-8010-f0347b53c10a |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422927142 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.3422927142 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1766157152 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 2824188192 ps |
| CPU time | 293.64 seconds |
| Started | Jul 31 08:14:54 PM PDT 24 |
| Finished | Jul 31 08:19:48 PM PDT 24 |
| Peak memory | 608656 kb |
| Host | smart-3a025e8e-09df-4080-a69b-8b2abdef12d3 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17661571 52 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1766157152 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_smoketest.2775214597 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 3201914804 ps |
| CPU time | 275.67 seconds |
| Started | Jul 31 08:17:39 PM PDT 24 |
| Finished | Jul 31 08:22:15 PM PDT 24 |
| Peak memory | 608488 kb |
| Host | smart-979610d5-e0b0-4848-887f-1fee437219d1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775214597 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_smoketest.2775214597 |
| Directory | /workspace/0.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.2870787496 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 3335476164 ps |
| CPU time | 407.15 seconds |
| Started | Jul 31 08:15:03 PM PDT 24 |
| Finished | Jul 31 08:21:51 PM PDT 24 |
| Peak memory | 609492 kb |
| Host | smart-d0f6c8ef-93ab-4215-8814-194fb47c709e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870787496 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_lc_ctrl_otp_hw_cfg0.2870787496 |
| Directory | /workspace/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.1384040712 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 3047103083 ps |
| CPU time | 168.05 seconds |
| Started | Jul 31 08:12:46 PM PDT 24 |
| Finished | Jul 31 08:15:35 PM PDT 24 |
| Peak memory | 620140 kb |
| Host | smart-fc640913-b279-4906-a3e5-28ee546cef00 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384040712 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.1384040712 |
| Directory | /workspace/0.chip_sw_lc_ctrl_raw_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1572643345 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 3120529398 ps |
| CPU time | 327.52 seconds |
| Started | Jul 31 08:13:01 PM PDT 24 |
| Finished | Jul 31 08:18:29 PM PDT 24 |
| Peak memory | 621632 kb |
| Host | smart-c5b470db-1df1-4144-b090-db3981fbfaa6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572643345 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.1572643345 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rma_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.280674041 |
| Short name | T1367 |
| Test name | |
| Test status | |
| Simulation time | 3158684045 ps |
| CPU time | 160.55 seconds |
| Started | Jul 31 08:13:25 PM PDT 24 |
| Finished | Jul 31 08:16:06 PM PDT 24 |
| Peak memory | 620104 kb |
| Host | smart-b7c58980-4f56-4256-8adc-a4d938ccc724 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTestLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=280674041 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.280674041 |
| Directory | /workspace/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2465514975 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 9575799104 ps |
| CPU time | 740.12 seconds |
| Started | Jul 31 08:16:01 PM PDT 24 |
| Finished | Jul 31 08:28:22 PM PDT 24 |
| Peak memory | 624692 kb |
| Host | smart-aaa422dd-7fcb-4c9b-af04-c99a2847fe32 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465514975 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_transition.2465514975 |
| Directory | /workspace/0.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.1780411666 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 2925477984 ps |
| CPU time | 116.55 seconds |
| Started | Jul 31 08:11:47 PM PDT 24 |
| Finished | Jul 31 08:13:44 PM PDT 24 |
| Peak memory | 618028 kb |
| Host | smart-4f7f90c8-45ec-4996-9bf1-6fe2b09e2433 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1780411666 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.1780411666 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.8557916 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 1968898390 ps |
| CPU time | 108.68 seconds |
| Started | Jul 31 08:14:08 PM PDT 24 |
| Finished | Jul 31 08:15:57 PM PDT 24 |
| Peak memory | 617620 kb |
| Host | smart-9a35ebb8-e5d0-4f26-92e8-cf486aa0340d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8557916 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.8557916 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.1544706217 |
| Short name | T1328 |
| Test name | |
| Test status | |
| Simulation time | 8530907996 ps |
| CPU time | 831.8 seconds |
| Started | Jul 31 08:13:29 PM PDT 24 |
| Finished | Jul 31 08:27:21 PM PDT 24 |
| Peak memory | 619340 kb |
| Host | smart-cb98024e-d7d1-4bbb-9211-d6776d80b642 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544706217 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.1544706217 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.500947711 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 47295816297 ps |
| CPU time | 6610.72 seconds |
| Started | Jul 31 08:12:59 PM PDT 24 |
| Finished | Jul 31 10:03:11 PM PDT 24 |
| Peak memory | 620660 kb |
| Host | smart-ec526d0f-f1ec-4a0d-8991-d61c8e667b15 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500947711 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_ sw_lc_walkthrough_rma.500947711 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.1915439969 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 26483833600 ps |
| CPU time | 2195.07 seconds |
| Started | Jul 31 08:15:08 PM PDT 24 |
| Finished | Jul 31 08:51:44 PM PDT 24 |
| Peak memory | 621420 kb |
| Host | smart-80a12ecf-84f3-41ff-8a46-4665c1b2c3ce |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1915439969 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_testun locks.1915439969 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2613008145 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 17246621200 ps |
| CPU time | 3581.56 seconds |
| Started | Jul 31 08:14:32 PM PDT 24 |
| Finished | Jul 31 09:14:14 PM PDT 24 |
| Peak memory | 609996 kb |
| Host | smart-d5db25b6-9a6d-4ab3-b44e-f6c7bfa1f8e4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=2613008145 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.2613008145 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.4252838411 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 18668838876 ps |
| CPU time | 4145.64 seconds |
| Started | Jul 31 08:15:56 PM PDT 24 |
| Finished | Jul 31 09:25:02 PM PDT 24 |
| Peak memory | 610380 kb |
| Host | smart-bb9cd9e4-c3d7-4487-ba03-7cc6e4776fb1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=4252838411 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.4252838411 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.4057968406 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 3639038840 ps |
| CPU time | 479.22 seconds |
| Started | Jul 31 08:14:05 PM PDT 24 |
| Finished | Jul 31 08:22:05 PM PDT 24 |
| Peak memory | 609784 kb |
| Host | smart-f43697ab-3c87-44ab-ace3-f244ad9df1aa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057968406 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.4057968406 |
| Directory | /workspace/0.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_randomness.10463514 |
| Short name | T1381 |
| Test name | |
| Test status | |
| Simulation time | 6369856092 ps |
| CPU time | 960.67 seconds |
| Started | Jul 31 08:16:19 PM PDT 24 |
| Finished | Jul 31 08:32:20 PM PDT 24 |
| Peak memory | 608812 kb |
| Host | smart-52528f6d-bd06-49b0-97e9-667916db9967 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=10463514 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.10463514 |
| Directory | /workspace/0.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_smoketest.359482255 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 10074797494 ps |
| CPU time | 2365.69 seconds |
| Started | Jul 31 08:19:33 PM PDT 24 |
| Finished | Jul 31 08:58:59 PM PDT 24 |
| Peak memory | 610128 kb |
| Host | smart-e7dfc243-8608-4205-904c-b1ae9edc9cad |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359482255 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_smoketest.359482255 |
| Directory | /workspace/0.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.1493023575 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 27228967026 ps |
| CPU time | 5340.62 seconds |
| Started | Jul 31 08:15:14 PM PDT 24 |
| Finished | Jul 31 09:44:16 PM PDT 24 |
| Peak memory | 610416 kb |
| Host | smart-9f3ce40b-8edb-400b-a3f4-1d62274de939 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=otp_ctrl_mem_access_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149302 3575 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_dai_lock.1493023575 |
| Directory | /workspace/0.chip_sw_otp_ctrl_dai_lock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.3245027463 |
| Short name | T1316 |
| Test name | |
| Test status | |
| Simulation time | 3032209459 ps |
| CPU time | 254.94 seconds |
| Started | Jul 31 08:12:52 PM PDT 24 |
| Finished | Jul 31 08:17:07 PM PDT 24 |
| Peak memory | 609940 kb |
| Host | smart-af679a39-23e2-4ad2-91b5-6ad22c1db4b2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245027463 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_ecc_error_vendor_test.3245027463 |
| Directory | /workspace/0.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.2894017906 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 4450103928 ps |
| CPU time | 577.49 seconds |
| Started | Jul 31 08:12:32 PM PDT 24 |
| Finished | Jul 31 08:22:10 PM PDT 24 |
| Peak memory | 611096 kb |
| Host | smart-4ddc42eb-f43c-41cb-baaf-e6eea2f1ebb7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2894017906 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.2894017906 |
| Directory | /workspace/0.chip_sw_otp_ctrl_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.605483310 |
| Short name | T1344 |
| Test name | |
| Test status | |
| Simulation time | 8367361056 ps |
| CPU time | 1252.41 seconds |
| Started | Jul 31 08:15:17 PM PDT 24 |
| Finished | Jul 31 08:36:09 PM PDT 24 |
| Peak memory | 610680 kb |
| Host | smart-4fbf531c-e77b-4a18-b3f0-4ec05949639a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=605483310 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.605483310 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.864830021 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 9023490180 ps |
| CPU time | 1417.68 seconds |
| Started | Jul 31 08:13:53 PM PDT 24 |
| Finished | Jul 31 08:37:31 PM PDT 24 |
| Peak memory | 610540 kb |
| Host | smart-d24df398-4d7d-4f54-a005-1b97f21c628b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=864830021 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.864830021 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.2192695283 |
| Short name | T1368 |
| Test name | |
| Test status | |
| Simulation time | 7939540384 ps |
| CPU time | 1211.16 seconds |
| Started | Jul 31 08:13:10 PM PDT 24 |
| Finished | Jul 31 08:33:21 PM PDT 24 |
| Peak memory | 610600 kb |
| Host | smart-e9fd9c5b-2211-4e8a-9ccc-0d1a542937e5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2192695283 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.2192695283 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3912989379 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 3999317840 ps |
| CPU time | 672.48 seconds |
| Started | Jul 31 08:14:23 PM PDT 24 |
| Finished | Jul 31 08:25:35 PM PDT 24 |
| Peak memory | 609824 kb |
| Host | smart-5884af3e-b586-4321-a70f-ceadc133abbc |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3912989379 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3912989379 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.2311316384 |
| Short name | T1338 |
| Test name | |
| Test status | |
| Simulation time | 2636555600 ps |
| CPU time | 294.31 seconds |
| Started | Jul 31 08:18:12 PM PDT 24 |
| Finished | Jul 31 08:23:07 PM PDT 24 |
| Peak memory | 608468 kb |
| Host | smart-a37b7907-c8c1-45c5-9576-09d833538abf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311316384 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_otp_ctrl_smoketest.2311316384 |
| Directory | /workspace/0.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pattgen_ios.593386107 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 2877477064 ps |
| CPU time | 250.91 seconds |
| Started | Jul 31 08:14:05 PM PDT 24 |
| Finished | Jul 31 08:18:18 PM PDT 24 |
| Peak memory | 612500 kb |
| Host | smart-1656cb20-f973-4d62-83f8-f630273fb8df |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593386107 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.593386107 |
| Directory | /workspace/0.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_idle_load.1542520999 |
| Short name | T1335 |
| Test name | |
| Test status | |
| Simulation time | 3597083390 ps |
| CPU time | 578.44 seconds |
| Started | Jul 31 08:13:24 PM PDT 24 |
| Finished | Jul 31 08:23:03 PM PDT 24 |
| Peak memory | 608948 kb |
| Host | smart-bc938baf-4dbd-4788-8ae5-2b244b67e397 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542520999 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_idle_load.1542520999 |
| Directory | /workspace/0.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_sleep_load.2663086203 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 4717571852 ps |
| CPU time | 306.33 seconds |
| Started | Jul 31 08:14:30 PM PDT 24 |
| Finished | Jul 31 08:19:37 PM PDT 24 |
| Peak memory | 610456 kb |
| Host | smart-4d7706ed-ed68-40d9-9881-0231e460b2a9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663086203 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_power_sleep_load.2663086203 |
| Directory | /workspace/0.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_virus.1745440623 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 5661888084 ps |
| CPU time | 1301 seconds |
| Started | Jul 31 08:22:14 PM PDT 24 |
| Finished | Jul 31 08:43:55 PM PDT 24 |
| Peak memory | 624920 kb |
| Host | smart-ff4188e2-1908-410b-81b5-0fb84414fe3c |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +accelerate_cold_ power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtes t_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=1745440623 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_virus.1745440623 |
| Directory | /workspace/0.chip_sw_power_virus/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.1079964613 |
| Short name | T1372 |
| Test name | |
| Test status | |
| Simulation time | 12166306917 ps |
| CPU time | 1740.47 seconds |
| Started | Jul 31 08:15:26 PM PDT 24 |
| Finished | Jul 31 08:44:27 PM PDT 24 |
| Peak memory | 611296 kb |
| Host | smart-217734a7-cb74-4bab-adef-2dfe2c7fc292 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079 964613 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.1079964613 |
| Directory | /workspace/0.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.4272293816 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 28558416062 ps |
| CPU time | 2964.3 seconds |
| Started | Jul 31 08:16:15 PM PDT 24 |
| Finished | Jul 31 09:05:40 PM PDT 24 |
| Peak memory | 611028 kb |
| Host | smart-9fbbdff4-906e-4f90-a828-61834b501292 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427 2293816 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.4272293816 |
| Directory | /workspace/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1753782912 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 25403853672 ps |
| CPU time | 1395.29 seconds |
| Started | Jul 31 08:16:08 PM PDT 24 |
| Finished | Jul 31 08:39:24 PM PDT 24 |
| Peak memory | 610908 kb |
| Host | smart-ff8fb552-d669-4249-aeef-fe002d52965b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1753782912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1753782912 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.3287681320 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 9551354912 ps |
| CPU time | 728.78 seconds |
| Started | Jul 31 08:15:55 PM PDT 24 |
| Finished | Jul 31 08:28:04 PM PDT 24 |
| Peak memory | 609588 kb |
| Host | smart-bffd9d9c-3bf2-4f62-9d64-8142306733aa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287681320 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.3287681320 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2802150330 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 4261779443 ps |
| CPU time | 353.31 seconds |
| Started | Jul 31 08:12:07 PM PDT 24 |
| Finished | Jul 31 08:18:01 PM PDT 24 |
| Peak memory | 616312 kb |
| Host | smart-b1c64894-dd74-4b7c-b66d-b76ddaa312c8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2802150330 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.2802150330 |
| Directory | /workspace/0.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1925715291 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 10591905297 ps |
| CPU time | 1596.49 seconds |
| Started | Jul 31 08:13:01 PM PDT 24 |
| Finished | Jul 31 08:39:38 PM PDT 24 |
| Peak memory | 611260 kb |
| Host | smart-516a86d7-437c-41ab-8993-5a032900d0be |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925715291 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1925715291 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3091180230 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 6924564864 ps |
| CPU time | 481.23 seconds |
| Started | Jul 31 08:14:20 PM PDT 24 |
| Finished | Jul 31 08:22:22 PM PDT 24 |
| Peak memory | 610416 kb |
| Host | smart-0b3f8f74-9332-42d7-9e13-2fd5a3c16768 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091180230 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3091180230 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.962670980 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 7079483279 ps |
| CPU time | 692.8 seconds |
| Started | Jul 31 08:13:54 PM PDT 24 |
| Finished | Jul 31 08:25:27 PM PDT 24 |
| Peak memory | 610756 kb |
| Host | smart-a9181ed8-b475-4106-9291-3e6666c44426 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962670980 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_por_reset.962670980 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3598026533 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 28622428638 ps |
| CPU time | 2745.26 seconds |
| Started | Jul 31 08:13:51 PM PDT 24 |
| Finished | Jul 31 08:59:37 PM PDT 24 |
| Peak memory | 611516 kb |
| Host | smart-663ab4cc-329d-4840-8aa6-3b070f1c0c50 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3598026533 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3598026533 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.578931635 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 37029883833 ps |
| CPU time | 3708.86 seconds |
| Started | Jul 31 08:14:12 PM PDT 24 |
| Finished | Jul 31 09:16:01 PM PDT 24 |
| Peak memory | 611188 kb |
| Host | smart-97b20a64-dab0-4cbe-8e48-36137e532a4e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578931635 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glitc h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sl eep_power_glitch_reset.578931635 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.1703359705 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 2587055680 ps |
| CPU time | 389.47 seconds |
| Started | Jul 31 08:13:44 PM PDT 24 |
| Finished | Jul 31 08:20:14 PM PDT 24 |
| Peak memory | 609792 kb |
| Host | smart-4a36a6e0-6fcd-4e12-9ff2-ba74ec08d3ee |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703359705 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_disabled.1703359705 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.3893685419 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 6345624022 ps |
| CPU time | 550.06 seconds |
| Started | Jul 31 08:13:31 PM PDT 24 |
| Finished | Jul 31 08:22:42 PM PDT 24 |
| Peak memory | 616816 kb |
| Host | smart-9e0af144-4816-4610-bb3d-1b7a3c90bb6a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3893685419 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_power_glitch_reset.3893685419 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.2383645107 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 6687296840 ps |
| CPU time | 616.36 seconds |
| Started | Jul 31 08:15:59 PM PDT 24 |
| Finished | Jul 31 08:26:16 PM PDT 24 |
| Peak memory | 610740 kb |
| Host | smart-569ada52-78d6-459f-9314-687c024632ee |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2383645107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.2383645107 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.461239072 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 4448286504 ps |
| CPU time | 404.46 seconds |
| Started | Jul 31 08:19:20 PM PDT 24 |
| Finished | Jul 31 08:26:05 PM PDT 24 |
| Peak memory | 610272 kb |
| Host | smart-fbafde93-5345-4eaa-abfd-0b80d513024a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461239072 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.461239072 |
| Directory | /workspace/0.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.457501108 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 7064689864 ps |
| CPU time | 1162.99 seconds |
| Started | Jul 31 08:13:36 PM PDT 24 |
| Finished | Jul 31 08:33:01 PM PDT 24 |
| Peak memory | 609616 kb |
| Host | smart-86561a93-ed9e-4d63-9564-6666aa3b0957 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457501108 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.457501108 |
| Directory | /workspace/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.2692187857 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 4475154712 ps |
| CPU time | 629.74 seconds |
| Started | Jul 31 08:13:24 PM PDT 24 |
| Finished | Jul 31 08:23:55 PM PDT 24 |
| Peak memory | 609236 kb |
| Host | smart-b9216924-e9b9-47c1-9292-452c1107a9d4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692187857 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.2692187857 |
| Directory | /workspace/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.2925905924 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5804111120 ps |
| CPU time | 583.09 seconds |
| Started | Jul 31 08:18:54 PM PDT 24 |
| Finished | Jul 31 08:28:37 PM PDT 24 |
| Peak memory | 610388 kb |
| Host | smart-da60562a-0bb8-42ee-a515-5547a43c42ce |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925905924 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usbdev_smoketest.2925905924 |
| Directory | /workspace/0.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.143637278 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 3880027956 ps |
| CPU time | 427.12 seconds |
| Started | Jul 31 08:13:15 PM PDT 24 |
| Finished | Jul 31 08:20:23 PM PDT 24 |
| Peak memory | 610084 kb |
| Host | smart-56de1d89-8b0f-489d-8014-d8a6abf1be96 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143 637278 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.143637278 |
| Directory | /workspace/0.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.3635838803 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 9475693103 ps |
| CPU time | 470.9 seconds |
| Started | Jul 31 08:18:47 PM PDT 24 |
| Finished | Jul 31 08:26:38 PM PDT 24 |
| Peak memory | 624684 kb |
| Host | smart-ff52b55d-00f4-4bdf-935a-9c18628bdc6c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635838803 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.3635838803 |
| Directory | /workspace/0.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.638046600 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 5872050516 ps |
| CPU time | 749.52 seconds |
| Started | Jul 31 08:11:53 PM PDT 24 |
| Finished | Jul 31 08:24:23 PM PDT 24 |
| Peak memory | 641680 kb |
| Host | smart-469cec5c-888d-4f4b-951f-d7a7a4b9e73a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 638046600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.638046600 |
| Directory | /workspace/0.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.2499934537 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 2790569852 ps |
| CPU time | 214.78 seconds |
| Started | Jul 31 08:17:48 PM PDT 24 |
| Finished | Jul 31 08:21:23 PM PDT 24 |
| Peak memory | 609644 kb |
| Host | smart-d927cb36-1c06-4d07-8467-f2d1e7b1a06a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499934537 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_rstmgr_smoketest.2499934537 |
| Directory | /workspace/0.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.768814138 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 4972116386 ps |
| CPU time | 461.73 seconds |
| Started | Jul 31 08:14:20 PM PDT 24 |
| Finished | Jul 31 08:22:02 PM PDT 24 |
| Peak memory | 610448 kb |
| Host | smart-c3ad6e4e-e938-4238-bf87-baed08460160 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768814138 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rstmgr_sw_req.768814138 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.447912122 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 2898614420 ps |
| CPU time | 278.79 seconds |
| Started | Jul 31 08:13:21 PM PDT 24 |
| Finished | Jul 31 08:18:01 PM PDT 24 |
| Peak memory | 609704 kb |
| Host | smart-4b8530e0-f917-4bdd-b30f-ee45e6b16750 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447912122 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_sw_rst.447912122 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.3483704131 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 2910100413 ps |
| CPU time | 260.35 seconds |
| Started | Jul 31 08:16:49 PM PDT 24 |
| Finished | Jul 31 08:21:10 PM PDT 24 |
| Peak memory | 608984 kb |
| Host | smart-1d790725-dce4-43b0-8d6c-b9cae26aeeef |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483704131 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.3483704131 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.1740779553 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 5099537608 ps |
| CPU time | 1155.79 seconds |
| Started | Jul 31 08:14:19 PM PDT 24 |
| Finished | Jul 31 08:33:36 PM PDT 24 |
| Peak memory | 608820 kb |
| Host | smart-22f81aec-e991-468c-83ae-9f471d666f05 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1740779553 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.1740779553 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.3216683601 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 5252111198 ps |
| CPU time | 465.34 seconds |
| Started | Jul 31 08:17:27 PM PDT 24 |
| Finished | Jul 31 08:25:13 PM PDT 24 |
| Peak memory | 624384 kb |
| Host | smart-8850d7a3-7009-4440-827f-296e7556e139 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216683601 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.3216683601 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.2003931047 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 5830112520 ps |
| CPU time | 700.99 seconds |
| Started | Jul 31 08:15:02 PM PDT 24 |
| Finished | Jul 31 08:26:44 PM PDT 24 |
| Peak memory | 621528 kb |
| Host | smart-08ac3486-02cb-4495-8b7e-8f037fb8c8d2 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003931047 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_wakeup.2003931047 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.3561354576 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 2497475242 ps |
| CPU time | 195.59 seconds |
| Started | Jul 31 08:17:33 PM PDT 24 |
| Finished | Jul 31 08:20:48 PM PDT 24 |
| Peak memory | 609580 kb |
| Host | smart-6391faad-bac9-4650-be2f-c37a07c7d7d3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561354576 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rv_plic_smoketest.3561354576 |
| Directory | /workspace/0.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_irq.2549238098 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 2700351500 ps |
| CPU time | 265.23 seconds |
| Started | Jul 31 08:13:02 PM PDT 24 |
| Finished | Jul 31 08:17:28 PM PDT 24 |
| Peak memory | 609672 kb |
| Host | smart-d57c1e46-aece-4c23-9ef8-e9cbae70f101 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549238098 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_irq.2549238098 |
| Directory | /workspace/0.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.3450187955 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 3550957656 ps |
| CPU time | 266.14 seconds |
| Started | Jul 31 08:16:04 PM PDT 24 |
| Finished | Jul 31 08:20:31 PM PDT 24 |
| Peak memory | 609684 kb |
| Host | smart-71ef1b75-5293-449c-8847-24549d2f06d4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450187955 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_smoketest.3450187955 |
| Directory | /workspace/0.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.3543553233 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 3167413362 ps |
| CPU time | 239.77 seconds |
| Started | Jul 31 08:17:25 PM PDT 24 |
| Finished | Jul 31 08:21:25 PM PDT 24 |
| Peak memory | 609792 kb |
| Host | smart-d435658e-ad0f-49ad-9900-7fc748a6be24 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543553 233 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.3543553233 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_wake.1119210695 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 3102390088 ps |
| CPU time | 269.11 seconds |
| Started | Jul 31 08:12:06 PM PDT 24 |
| Finished | Jul 31 08:16:35 PM PDT 24 |
| Peak memory | 609392 kb |
| Host | smart-059f7596-457d-4b00-8642-05738fa3db9f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119210695 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.1119210695 |
| Directory | /workspace/0.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.1611917990 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 9356320224 ps |
| CPU time | 1555.66 seconds |
| Started | Jul 31 08:11:47 PM PDT 24 |
| Finished | Jul 31 08:37:43 PM PDT 24 |
| Peak memory | 609556 kb |
| Host | smart-5ed58646-b378-4121-8e33-3d7f4f2b765a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611917990 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_sleep_pwm_pulses.1611917990 |
| Directory | /workspace/0.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1328511072 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 8034770186 ps |
| CPU time | 461.47 seconds |
| Started | Jul 31 08:16:36 PM PDT 24 |
| Finished | Jul 31 08:24:18 PM PDT 24 |
| Peak memory | 610696 kb |
| Host | smart-1be648e4-3525-4fee-85d2-fc82870d0f91 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328511072 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sl eep_sram_ret_contents_no_scramble.1328511072 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.67549186 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 7785231944 ps |
| CPU time | 710.18 seconds |
| Started | Jul 31 08:15:30 PM PDT 24 |
| Finished | Jul 31 08:27:21 PM PDT 24 |
| Peak memory | 610664 kb |
| Host | smart-c42e95ed-c647-4024-aa59-5cce0d7e94a9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67549186 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_s ram_ret_contents_scramble.67549186 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through.2443610154 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 5328945226 ps |
| CPU time | 543.56 seconds |
| Started | Jul 31 08:12:32 PM PDT 24 |
| Finished | Jul 31 08:21:36 PM PDT 24 |
| Peak memory | 624744 kb |
| Host | smart-bf140856-ce1a-47a7-b9fe-33ce514dec8d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443610154 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through.2443610154 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_tpm.3643062141 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 3256088992 ps |
| CPU time | 354.56 seconds |
| Started | Jul 31 08:14:05 PM PDT 24 |
| Finished | Jul 31 08:20:00 PM PDT 24 |
| Peak memory | 618316 kb |
| Host | smart-c24fe3ad-5057-445e-877a-442253a15293 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643062141 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_tpm.3643062141 |
| Directory | /workspace/0.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.202731021 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 2473511810 ps |
| CPU time | 242.06 seconds |
| Started | Jul 31 08:13:29 PM PDT 24 |
| Finished | Jul 31 08:17:31 PM PDT 24 |
| Peak memory | 610176 kb |
| Host | smart-9e56fa3a-36d2-4f8c-a0e6-75c5c0d21b0e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202731021 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_spi_host_tx_rx.202731021 |
| Directory | /workspace/0.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.778902730 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 7683096959 ps |
| CPU time | 958.36 seconds |
| Started | Jul 31 08:15:24 PM PDT 24 |
| Finished | Jul 31 08:31:23 PM PDT 24 |
| Peak memory | 610708 kb |
| Host | smart-048708ef-6600-4a95-9c28-080eddaf3547 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778902730 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.778902730 |
| Directory | /workspace/0.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.302848727 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 4733218400 ps |
| CPU time | 733.52 seconds |
| Started | Jul 31 08:14:31 PM PDT 24 |
| Finished | Jul 31 08:26:45 PM PDT 24 |
| Peak memory | 611092 kb |
| Host | smart-1beade1b-1901-4401-a503-b8c7afc7c3ec |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302848727 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl _scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ sram_ctrl_scrambled_access.302848727 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1235044445 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 3416652785 ps |
| CPU time | 525.82 seconds |
| Started | Jul 31 08:13:45 PM PDT 24 |
| Finished | Jul 31 08:22:32 PM PDT 24 |
| Peak memory | 610576 kb |
| Host | smart-5918358c-c66e-4da4-8621-ecfc2aea6d36 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235044445 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1235044445 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.478521153 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 5111331658 ps |
| CPU time | 562.31 seconds |
| Started | Jul 31 08:17:05 PM PDT 24 |
| Finished | Jul 31 08:26:28 PM PDT 24 |
| Peak memory | 610096 kb |
| Host | smart-70d53281-fc65-49d0-b466-c98f1df6cf1a |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478521153 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.478521153 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.1030851637 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 2298129334 ps |
| CPU time | 241.14 seconds |
| Started | Jul 31 08:19:34 PM PDT 24 |
| Finished | Jul 31 08:23:36 PM PDT 24 |
| Peak memory | 609508 kb |
| Host | smart-7ed9caaf-f238-499f-a0cc-2d18bb0febd3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030851637 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_sram_ctrl_smoketest.1030851637 |
| Directory | /workspace/0.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.344491411 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 20005976652 ps |
| CPU time | 3256.88 seconds |
| Started | Jul 31 08:15:45 PM PDT 24 |
| Finished | Jul 31 09:10:03 PM PDT 24 |
| Peak memory | 610500 kb |
| Host | smart-6dd75658-e217-4fa6-bf84-3b9fa1d28cb4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344491411 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.344491411 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.2908544715 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 4797837004 ps |
| CPU time | 543.74 seconds |
| Started | Jul 31 08:15:00 PM PDT 24 |
| Finished | Jul 31 08:24:06 PM PDT 24 |
| Peak memory | 613520 kb |
| Host | smart-36904742-8778-4972-9a34-4a71ee21ae83 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908544715 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_in_irq.2908544715 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.1643470261 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 3201481331 ps |
| CPU time | 282.26 seconds |
| Started | Jul 31 08:15:13 PM PDT 24 |
| Finished | Jul 31 08:19:56 PM PDT 24 |
| Peak memory | 614340 kb |
| Host | smart-edd0145b-56cd-4adf-9d6a-df9c81fe01b2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643470261 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_inputs.1643470261 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.3420798451 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 4114525628 ps |
| CPU time | 462.67 seconds |
| Started | Jul 31 08:16:32 PM PDT 24 |
| Finished | Jul 31 08:24:15 PM PDT 24 |
| Peak memory | 610020 kb |
| Host | smart-6aa0b508-6cb6-49c7-adfc-dbad39e41fe9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420798451 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_outputs.3420798451 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2263221571 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 5100970564 ps |
| CPU time | 506.36 seconds |
| Started | Jul 31 08:14:05 PM PDT 24 |
| Finished | Jul 31 08:22:32 PM PDT 24 |
| Peak memory | 610504 kb |
| Host | smart-414bcdd4-a965-4008-8ad9-6d168eb02b77 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263221571 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2263221571 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.3117900416 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 13678947704 ps |
| CPU time | 3164.12 seconds |
| Started | Jul 31 08:12:20 PM PDT 24 |
| Finished | Jul 31 09:05:05 PM PDT 24 |
| Peak memory | 624468 kb |
| Host | smart-3d448744-ee89-4de1-888f-b9e1e76a7e5c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3117900416 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.3117900416 |
| Directory | /workspace/0.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_smoketest.641059172 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 2698912260 ps |
| CPU time | 230.48 seconds |
| Started | Jul 31 08:17:36 PM PDT 24 |
| Finished | Jul 31 08:21:27 PM PDT 24 |
| Peak memory | 615044 kb |
| Host | smart-80f874bd-3bec-46e2-94db-d65127114708 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641059172 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_uart_smoketest.641059172 |
| Directory | /workspace/0.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx.279757194 |
| Short name | T1361 |
| Test name | |
| Test status | |
| Simulation time | 4276285004 ps |
| CPU time | 646.25 seconds |
| Started | Jul 31 08:12:39 PM PDT 24 |
| Finished | Jul 31 08:23:27 PM PDT 24 |
| Peak memory | 623888 kb |
| Host | smart-45b75aac-46ff-4bd6-b66d-e0048b593c64 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279757194 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.279757194 |
| Directory | /workspace/0.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3266217641 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 13281653956 ps |
| CPU time | 2834.75 seconds |
| Started | Jul 31 08:11:54 PM PDT 24 |
| Finished | Jul 31 08:59:10 PM PDT 24 |
| Peak memory | 624520 kb |
| Host | smart-1f202881-ea1f-4132-a66d-252afbd889fc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266217641 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx _alt_clk_freq.3266217641 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1661575986 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 4374991552 ps |
| CPU time | 480.06 seconds |
| Started | Jul 31 08:13:09 PM PDT 24 |
| Finished | Jul 31 08:21:10 PM PDT 24 |
| Peak memory | 619272 kb |
| Host | smart-ff26ec63-05e8-45f8-9f95-0aa04cbe0a16 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661575986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.1661575986 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.3957886819 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 4516919184 ps |
| CPU time | 795.46 seconds |
| Started | Jul 31 08:12:24 PM PDT 24 |
| Finished | Jul 31 08:25:40 PM PDT 24 |
| Peak memory | 623976 kb |
| Host | smart-6352dee3-98d5-4e88-b663-162140874988 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957886819 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.3957886819 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.3008730661 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 4249957170 ps |
| CPU time | 829.15 seconds |
| Started | Jul 31 08:13:26 PM PDT 24 |
| Finished | Jul 31 08:27:16 PM PDT 24 |
| Peak memory | 623648 kb |
| Host | smart-826c8d78-0cab-4f29-9ef8-79d3dcf2a106 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008730661 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.3008730661 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.2923014728 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 4133698360 ps |
| CPU time | 623.02 seconds |
| Started | Jul 31 08:12:01 PM PDT 24 |
| Finished | Jul 31 08:22:24 PM PDT 24 |
| Peak memory | 623644 kb |
| Host | smart-719f8d8a-ee27-4e80-a89c-0d8979eb710f |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923014728 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.2923014728 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.3115025355 |
| Short name | T1354 |
| Test name | |
| Test status | |
| Simulation time | 2765554098 ps |
| CPU time | 338 seconds |
| Started | Jul 31 08:15:55 PM PDT 24 |
| Finished | Jul 31 08:21:33 PM PDT 24 |
| Peak memory | 610148 kb |
| Host | smart-cead55f8-1caf-4b5f-8795-8a3e667eae0e |
| User | root |
| Command | /workspace/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw_images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115025355 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.3115025355 |
| Directory | /workspace/0.chip_sw_usb_ast_clk_calib/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_dpi.3117759431 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 12130306116 ps |
| CPU time | 3264.13 seconds |
| Started | Jul 31 08:13:41 PM PDT 24 |
| Finished | Jul 31 09:08:06 PM PDT 24 |
| Peak memory | 610128 kb |
| Host | smart-46dcd4fa-57fa-4116-a6ca-280cf603a109 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3117759431 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.3117759431 |
| Directory | /workspace/0.chip_sw_usbdev_dpi/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pincfg.1884067119 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 31512081720 ps |
| CPU time | 6777.36 seconds |
| Started | Jul 31 08:13:45 PM PDT 24 |
| Finished | Jul 31 10:06:44 PM PDT 24 |
| Peak memory | 610192 kb |
| Host | smart-f1ae09de-bf7a-4dab-9fde-3c94354c9440 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=1884067119 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.1884067119 |
| Directory | /workspace/0.chip_sw_usbdev_pincfg/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pullup.2385347688 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 2892108072 ps |
| CPU time | 255.71 seconds |
| Started | Jul 31 08:13:36 PM PDT 24 |
| Finished | Jul 31 08:17:52 PM PDT 24 |
| Peak memory | 609780 kb |
| Host | smart-4a9f1696-e410-48c6-ade8-5d94e74e4e4f |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385347688 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.2385347688 |
| Directory | /workspace/0.chip_sw_usbdev_pullup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_setuprx.2056563221 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 4010109456 ps |
| CPU time | 531.35 seconds |
| Started | Jul 31 08:12:18 PM PDT 24 |
| Finished | Jul 31 08:21:10 PM PDT 24 |
| Peak memory | 609796 kb |
| Host | smart-af86c0a4-9c9f-4bbc-a5f3-8896e0adea5d |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205656322 1 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.2056563221 |
| Directory | /workspace/0.chip_sw_usbdev_setuprx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_stream.3357050262 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 18459343656 ps |
| CPU time | 4907.26 seconds |
| Started | Jul 31 08:14:47 PM PDT 24 |
| Finished | Jul 31 09:36:35 PM PDT 24 |
| Peak memory | 609404 kb |
| Host | smart-e29037ae-538d-40d5-bf2e-759b17789d8f |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=3357050262 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.3357050262 |
| Directory | /workspace/0.chip_sw_usbdev_stream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_vbus.3692223875 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 3149587760 ps |
| CPU time | 263.12 seconds |
| Started | Jul 31 08:12:03 PM PDT 24 |
| Finished | Jul 31 08:16:27 PM PDT 24 |
| Peak memory | 608472 kb |
| Host | smart-e176e801-5659-47f3-a41b-b4b3acca24c3 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692223875 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.3692223875 |
| Directory | /workspace/0.chip_sw_usbdev_vbus/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_dev.2400567761 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 2435882444 ps |
| CPU time | 169.03 seconds |
| Started | Jul 31 08:13:41 PM PDT 24 |
| Finished | Jul 31 08:16:30 PM PDT 24 |
| Peak memory | 623876 kb |
| Host | smart-909d06de-daac-4eac-ba21-d95974e8b07d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2400567761 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_dev.2400567761 |
| Directory | /workspace/0.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_prod.1787023552 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 2921610042 ps |
| CPU time | 184.16 seconds |
| Started | Jul 31 08:15:28 PM PDT 24 |
| Finished | Jul 31 08:18:32 PM PDT 24 |
| Peak memory | 623776 kb |
| Host | smart-b9ae2597-a9e7-4be8-9afc-c6b500b5dbdb |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787023552 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.1787023552 |
| Directory | /workspace/0.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_testunlock0.502032810 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 3400572681 ps |
| CPU time | 273.63 seconds |
| Started | Jul 31 08:15:53 PM PDT 24 |
| Finished | Jul 31 08:20:27 PM PDT 24 |
| Peak memory | 633120 kb |
| Host | smart-a466e514-d065-4b0c-8527-92f3251f15ab |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=502032810 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_testunlock0.502032810 |
| Directory | /workspace/0.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_dev.2776858067 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 15264730271 ps |
| CPU time | 4424.8 seconds |
| Started | Jul 31 08:22:38 PM PDT 24 |
| Finished | Jul 31 09:36:24 PM PDT 24 |
| Peak memory | 610100 kb |
| Host | smart-a44aa4cd-1a1d-495f-a13b-3a3da3dd22f8 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776858067 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_dev.2776858067 |
| Directory | /workspace/0.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod.1806800119 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 15671209618 ps |
| CPU time | 4190.48 seconds |
| Started | Jul 31 08:21:46 PM PDT 24 |
| Finished | Jul 31 09:31:37 PM PDT 24 |
| Peak memory | 610236 kb |
| Host | smart-8a70abca-1b74-4fe0-b509-ab064b61550f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806800119 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_prod.1806800119 |
| Directory | /workspace/0.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.2713153465 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 15787370216 ps |
| CPU time | 3833.02 seconds |
| Started | Jul 31 08:21:42 PM PDT 24 |
| Finished | Jul 31 09:25:35 PM PDT 24 |
| Peak memory | 610256 kb |
| Host | smart-e38f2835-e020-485c-85f3-485f71184575 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713153465 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.rom_e2e_asm_init_prod_end.2713153465 |
| Directory | /workspace/0.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_rma.2778155373 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 14470582851 ps |
| CPU time | 3791.96 seconds |
| Started | Jul 31 08:24:33 PM PDT 24 |
| Finished | Jul 31 09:27:45 PM PDT 24 |
| Peak memory | 610332 kb |
| Host | smart-17b7ad13-2742-470a-bc34-d335d4d07e3a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778155373 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_rma.2778155373 |
| Directory | /workspace/0.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.2465706992 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 10877658912 ps |
| CPU time | 2771.94 seconds |
| Started | Jul 31 08:20:39 PM PDT 24 |
| Finished | Jul 31 09:06:51 PM PDT 24 |
| Peak memory | 610608 kb |
| Host | smart-7092ab27-5088-458e-be54-a1c28cd32744 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465706992 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.rom_e2e_asm_init_test_unlocked0.2465706992 |
| Directory | /workspace/0.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.232899659 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 24558390680 ps |
| CPU time | 5658.1 seconds |
| Started | Jul 31 08:22:13 PM PDT 24 |
| Finished | Jul 31 09:56:31 PM PDT 24 |
| Peak memory | 609856 kb |
| Host | smart-18806292-331b-4a9e-a261-bd71e3ef4529 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=232899659 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.232899659 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.3925834663 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 24323123286 ps |
| CPU time | 5877.95 seconds |
| Started | Jul 31 08:21:49 PM PDT 24 |
| Finished | Jul 31 09:59:48 PM PDT 24 |
| Peak memory | 609564 kb |
| Host | smart-05f4824d-e6bf-4cf3-b0fe-b14fc482bfb1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3925834663 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.3925834663 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2007025192 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 23078283480 ps |
| CPU time | 5583.38 seconds |
| Started | Jul 31 08:21:52 PM PDT 24 |
| Finished | Jul 31 09:54:57 PM PDT 24 |
| Peak memory | 610176 kb |
| Host | smart-608a1944-ae3f-4920-915f-7f32a1a1152a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2007025192 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2007025192 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2952491862 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 18346539672 ps |
| CPU time | 4946.89 seconds |
| Started | Jul 31 08:21:41 PM PDT 24 |
| Finished | Jul 31 09:44:08 PM PDT 24 |
| Peak memory | 609576 kb |
| Host | smart-6cb3b6fd-9f73-42e4-af4f-5fedd5cb220c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952491862 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2952491862 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3102961950 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 15297634248 ps |
| CPU time | 4285.44 seconds |
| Started | Jul 31 08:21:35 PM PDT 24 |
| Finished | Jul 31 09:33:01 PM PDT 24 |
| Peak memory | 610100 kb |
| Host | smart-8a42e02a-b2ab-4af0-9bcd-cc2ab7b4900a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3102961950 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3102961950 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.312250712 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 15127632132 ps |
| CPU time | 4471.63 seconds |
| Started | Jul 31 08:22:42 PM PDT 24 |
| Finished | Jul 31 09:37:14 PM PDT 24 |
| Peak memory | 610100 kb |
| Host | smart-c2d8a03f-2a69-4694-ae60-cfa9d65775a8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=312250712 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.312250712 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3411629112 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 15035000150 ps |
| CPU time | 4059.18 seconds |
| Started | Jul 31 08:22:32 PM PDT 24 |
| Finished | Jul 31 09:30:12 PM PDT 24 |
| Peak memory | 610144 kb |
| Host | smart-9101b8f1-e55f-4d87-85b5-66f3c293cad3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3411629112 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3411629112 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2029546630 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 14751281432 ps |
| CPU time | 4429.61 seconds |
| Started | Jul 31 08:23:00 PM PDT 24 |
| Finished | Jul 31 09:36:50 PM PDT 24 |
| Peak memory | 609132 kb |
| Host | smart-eeab29c9-3885-46df-9176-7e4d1f18107a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2029546630 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2029546630 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2093392054 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 12109634488 ps |
| CPU time | 3337.93 seconds |
| Started | Jul 31 08:23:09 PM PDT 24 |
| Finished | Jul 31 09:18:47 PM PDT 24 |
| Peak memory | 609944 kb |
| Host | smart-409b9177-cd5c-4c27-ab42-e0e070d4d805 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093392054 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2093392054 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3094369968 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 15342579336 ps |
| CPU time | 4527.08 seconds |
| Started | Jul 31 08:22:36 PM PDT 24 |
| Finished | Jul 31 09:38:04 PM PDT 24 |
| Peak memory | 610136 kb |
| Host | smart-43147013-ec3a-4d0d-99df-e67fa6d89e84 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094369968 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3094369968 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1324061997 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 15868004760 ps |
| CPU time | 4179.08 seconds |
| Started | Jul 31 08:21:19 PM PDT 24 |
| Finished | Jul 31 09:30:59 PM PDT 24 |
| Peak memory | 610052 kb |
| Host | smart-725794d3-96ce-4381-9728-3c19505cc5e2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132406 1997 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1324061997 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1242322521 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 14986125264 ps |
| CPU time | 3661.45 seconds |
| Started | Jul 31 08:20:37 PM PDT 24 |
| Finished | Jul 31 09:21:39 PM PDT 24 |
| Peak memory | 610184 kb |
| Host | smart-4b677a06-6a14-4697-b6af-65a054fe825c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242322521 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1242322521 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.2398905665 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 11468065360 ps |
| CPU time | 3014.5 seconds |
| Started | Jul 31 08:22:42 PM PDT 24 |
| Finished | Jul 31 09:12:57 PM PDT 24 |
| Peak memory | 609232 kb |
| Host | smart-13f7005b-59a7-4aeb-8e5f-92d0e71c5799 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2398905665 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.2398905665 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_dev.2919614188 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 10486650582 ps |
| CPU time | 1934.53 seconds |
| Started | Jul 31 08:17:58 PM PDT 24 |
| Finished | Jul 31 08:50:13 PM PDT 24 |
| Peak memory | 624632 kb |
| Host | smart-8d7f9347-178d-4981-9600-4dbef9c5f706 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_disabled:4,mask_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29196 14188 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_dev.2919614188 |
| Directory | /workspace/0.rom_e2e_jtag_debug_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_rma.2523930537 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 11134943925 ps |
| CPU time | 2436.37 seconds |
| Started | Jul 31 08:16:12 PM PDT 24 |
| Finished | Jul 31 08:56:50 PM PDT 24 |
| Peak memory | 624560 kb |
| Host | smart-0c35521b-49d4-4ed5-af99-7469294f5ec4 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_disabled:4,mask_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25239 30537 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_rma.2523930537 |
| Directory | /workspace/0.rom_e2e_jtag_debug_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.2441958001 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 11149695184 ps |
| CPU time | 2095.35 seconds |
| Started | Jul 31 08:17:45 PM PDT 24 |
| Finished | Jul 31 08:52:41 PM PDT 24 |
| Peak memory | 624396 kb |
| Host | smart-ddac6464-6b5b-45f2-bf80-07365e7a45b6 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlocked0_exec_disabled:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2441958001 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_test_unlocked0.2441958001 |
| Directory | /workspace/0.rom_e2e_jtag_debug_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.2469231100 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 32195436377 ps |
| CPU time | 3118.47 seconds |
| Started | Jul 31 08:19:33 PM PDT 24 |
| Finished | Jul 31 09:11:33 PM PDT 24 |
| Peak memory | 623864 kb |
| Host | smart-2a62c1e4-f7df-46fd-b7b2-78aed8dc1bcd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2469231100 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_dev.2469231100 |
| Directory | /workspace/0.rom_e2e_jtag_inject_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.1089216976 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 25360001056 ps |
| CPU time | 2761.37 seconds |
| Started | Jul 31 08:19:02 PM PDT 24 |
| Finished | Jul 31 09:05:04 PM PDT 24 |
| Peak memory | 620888 kb |
| Host | smart-f0e89ab8-00eb-4d6d-be2d-a100f9e9b797 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1089216976 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_rma.1089216976 |
| Directory | /workspace/0.rom_e2e_jtag_inject_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.3539367470 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 32302042110 ps |
| CPU time | 2330.66 seconds |
| Started | Jul 31 08:19:04 PM PDT 24 |
| Finished | Jul 31 08:57:55 PM PDT 24 |
| Peak memory | 621312 kb |
| Host | smart-bed9302d-d969-4337-9a3c-2d3882c4a77c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlock ed0_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539367470 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_ inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject _test_unlocked0.3539367470 |
| Directory | /workspace/0.rom_e2e_jtag_inject_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.3927074985 |
| Short name | T1314 |
| Test name | |
| Test status | |
| Simulation time | 14988119560 ps |
| CPU time | 4016.81 seconds |
| Started | Jul 31 08:20:46 PM PDT 24 |
| Finished | Jul 31 09:27:43 PM PDT 24 |
| Peak memory | 610076 kb |
| Host | smart-5d14e845-a4a1-47ae-a3ec-494e9e0c23c0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927074985 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_in it_rom_ext_invalid_meas.3927074985 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.153912521 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 14629302028 ps |
| CPU time | 3789.89 seconds |
| Started | Jul 31 08:24:01 PM PDT 24 |
| Finished | Jul 31 09:27:11 PM PDT 24 |
| Peak memory | 610068 kb |
| Host | smart-9d4a460b-c0f8-4e35-8a55-211377345a54 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153912521 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_meas.153912521 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.250529498 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 15426173370 ps |
| CPU time | 4030 seconds |
| Started | Jul 31 08:22:42 PM PDT 24 |
| Finished | Jul 31 09:29:52 PM PDT 24 |
| Peak memory | 610264 kb |
| Host | smart-9cf472c2-cb97-4cf6-be65-591825225802 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250529498 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_ no_meas.250529498 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_self_hash.1250199152 |
| Short name | T1337 |
| Test name | |
| Test status | |
| Simulation time | 25846015836 ps |
| CPU time | 6305.49 seconds |
| Started | Jul 31 08:21:47 PM PDT 24 |
| Finished | Jul 31 10:06:53 PM PDT 24 |
| Peak memory | 610180 kb |
| Host | smart-c7013a8a-a951-48c3-8c63-06e3552e20d5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250199152 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_self_hash.1250199152 |
| Directory | /workspace/0.rom_e2e_self_hash/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.1696584510 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 14672187167 ps |
| CPU time | 3380.77 seconds |
| Started | Jul 31 08:17:32 PM PDT 24 |
| Finished | Jul 31 09:13:54 PM PDT 24 |
| Peak memory | 610340 kb |
| Host | smart-424fbf83-8e82-44c1-8e5a-6779f8e7915a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696584510 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_ shutdown_exception_c.1696584510 |
| Directory | /workspace/0.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_output.242801953 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 29610998972 ps |
| CPU time | 3306.36 seconds |
| Started | Jul 31 08:22:18 PM PDT 24 |
| Finished | Jul 31 09:17:25 PM PDT 24 |
| Peak memory | 611448 kb |
| Host | smart-4298edd6-4fd3-440a-bdf0-716a9881f3ec |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242801953 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_shutdown_output.242801953 |
| Directory | /workspace/0.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.1435320309 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 23845384464 ps |
| CPU time | 6099.94 seconds |
| Started | Jul 31 08:19:51 PM PDT 24 |
| Finished | Jul 31 10:01:32 PM PDT 24 |
| Peak memory | 609392 kb |
| Host | smart-3efde626-001a-4a8f-aabe-b05c2c2949ce |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev :4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1435320309 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_b ad_dev.1435320309 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.12925662 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 23989376620 ps |
| CPU time | 5614.83 seconds |
| Started | Jul 31 08:21:59 PM PDT 24 |
| Finished | Jul 31 09:55:35 PM PDT 24 |
| Peak memory | 609376 kb |
| Host | smart-545cc39a-ec86-4912-a64a-b800d8a44b72 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=12925662 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_ bad_prod.12925662 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.4196773509 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 23736678350 ps |
| CPU time | 5952.94 seconds |
| Started | Jul 31 08:21:47 PM PDT 24 |
| Finished | Jul 31 10:01:01 PM PDT 24 |
| Peak memory | 609412 kb |
| Host | smart-823f31aa-b064-43b1-916e-818aaf574801 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=4196773509 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_ bad_b_bad_prod_end.4196773509 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.3357839903 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 22748450650 ps |
| CPU time | 5018.69 seconds |
| Started | Jul 31 08:26:01 PM PDT 24 |
| Finished | Jul 31 09:49:40 PM PDT 24 |
| Peak memory | 610456 kb |
| Host | smart-36b4eff5-824d-4c3e-af31-0a058c9b6990 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_r ma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=3357839903 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b _bad_rma.3357839903 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.3500921365 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 17996420152 ps |
| CPU time | 4607.39 seconds |
| Started | Jul 31 08:21:37 PM PDT 24 |
| Finished | Jul 31 09:38:25 PM PDT 24 |
| Peak memory | 610724 kb |
| Host | smart-62dc0c7f-0957-49b9-87cc-12c9be47eac9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=600_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_t est_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=3500921365 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b _bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_alw ays_a_bad_b_bad_test_unlocked0.3500921365 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.978152479 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 14549715972 ps |
| CPU time | 4029.23 seconds |
| Started | Jul 31 08:25:22 PM PDT 24 |
| Finished | Jul 31 09:32:32 PM PDT 24 |
| Peak memory | 610248 kb |
| Host | smart-f3248069-ca5a-4bbc-804f-eae43decc682 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978152479 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.978152479 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3869846067 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 14268744886 ps |
| CPU time | 3860.5 seconds |
| Started | Jul 31 08:20:54 PM PDT 24 |
| Finished | Jul 31 09:25:15 PM PDT 24 |
| Peak memory | 610156 kb |
| Host | smart-176038a8-fb61-41a7-933e-ea08784dfe62 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869846067 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3869846067 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2972312530 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 15354153700 ps |
| CPU time | 3359.11 seconds |
| Started | Jul 31 08:21:06 PM PDT 24 |
| Finished | Jul 31 09:17:06 PM PDT 24 |
| Peak memory | 609468 kb |
| Host | smart-de7a8b04-0a39-48da-8415-69a68c1ab840 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972312530 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2972312530 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.3118882396 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 13746924391 ps |
| CPU time | 4619.54 seconds |
| Started | Jul 31 08:22:25 PM PDT 24 |
| Finished | Jul 31 09:39:25 PM PDT 24 |
| Peak memory | 610772 kb |
| Host | smart-0a0d2337-ff6c-415d-8f95-4778890d7016 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118882396 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.3118882396 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3819789438 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 11332087000 ps |
| CPU time | 2443.3 seconds |
| Started | Jul 31 08:25:19 PM PDT 24 |
| Finished | Jul 31 09:06:03 PM PDT 24 |
| Peak memory | 611348 kb |
| Host | smart-abfd0ac0-a5cb-404b-974d-9ac67a4817e8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0:new_rules,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819789438 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3819789438 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.793518008 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 15300960375 ps |
| CPU time | 3912.34 seconds |
| Started | Jul 31 08:24:33 PM PDT 24 |
| Finished | Jul 31 09:29:45 PM PDT 24 |
| Peak memory | 610444 kb |
| Host | smart-65ba7285-7d89-47c4-a500-64fa7538db30 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793518008 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.793518008 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.3404799678 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 14733890452 ps |
| CPU time | 3342.45 seconds |
| Started | Jul 31 08:19:26 PM PDT 24 |
| Finished | Jul 31 09:15:09 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-d883e163-c5a3-4b4a-96a3-804baa3923d5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404799678 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.3404799678 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1820644889 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 14212045416 ps |
| CPU time | 3495.16 seconds |
| Started | Jul 31 08:24:32 PM PDT 24 |
| Finished | Jul 31 09:22:48 PM PDT 24 |
| Peak memory | 610408 kb |
| Host | smart-c1030e83-f34c-4ee3-ae6c-5b9176ac058c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820644889 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1820644889 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2397283226 |
| Short name | T1340 |
| Test name | |
| Test status | |
| Simulation time | 14558970508 ps |
| CPU time | 3624.55 seconds |
| Started | Jul 31 08:23:16 PM PDT 24 |
| Finished | Jul 31 09:23:42 PM PDT 24 |
| Peak memory | 610424 kb |
| Host | smart-6181ed28-facc-498d-9e79-3cf2aa00ac89 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397283226 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2397283226 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2599967122 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 10435679288 ps |
| CPU time | 2722.81 seconds |
| Started | Jul 31 08:19:23 PM PDT 24 |
| Finished | Jul 31 09:04:47 PM PDT 24 |
| Peak memory | 611432 kb |
| Host | smart-31a41963-5b1b-4a62-a14c-968313d7d696 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599967122 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2599967122 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_smoke.3613485836 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 14364129526 ps |
| CPU time | 4000.17 seconds |
| Started | Jul 31 08:19:33 PM PDT 24 |
| Finished | Jul 31 09:26:14 PM PDT 24 |
| Peak memory | 610180 kb |
| Host | smart-7113627e-11d3-4bda-a52a-a410d2ce2655 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=3613485836 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.3613485836 |
| Directory | /workspace/0.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_static_critical.2914073616 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 17207835224 ps |
| CPU time | 4461.04 seconds |
| Started | Jul 31 08:24:47 PM PDT 24 |
| Finished | Jul 31 09:39:09 PM PDT 24 |
| Peak memory | 610160 kb |
| Host | smart-ea55f776-c1f5-4a69-b47b-ed4e2f34ae7b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914073616 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_static_critical.2914073616 |
| Directory | /workspace/0.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/0.rom_keymgr_functest.2876519461 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 4961843100 ps |
| CPU time | 407.97 seconds |
| Started | Jul 31 08:15:53 PM PDT 24 |
| Finished | Jul 31 08:22:41 PM PDT 24 |
| Peak memory | 610532 kb |
| Host | smart-ab1ed98d-e539-4d7d-90fc-65aa8bbc75b7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876519461 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_keymgr_functest.2876519461 |
| Directory | /workspace/0.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/0.rom_raw_unlock.578559595 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 6033491972 ps |
| CPU time | 243.12 seconds |
| Started | Jul 31 08:18:48 PM PDT 24 |
| Finished | Jul 31 08:22:51 PM PDT 24 |
| Peak memory | 623796 kb |
| Host | smart-3ed69a8e-7270-473a-a145-22777c5fca93 |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=578559595 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_raw_unlock.578559595 |
| Directory | /workspace/0.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.rom_volatile_raw_unlock.2339163091 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 2493922088 ps |
| CPU time | 105.97 seconds |
| Started | Jul 31 08:15:28 PM PDT 24 |
| Finished | Jul 31 08:17:14 PM PDT 24 |
| Peak memory | 616972 kb |
| Host | smart-76771101-1d35-437e-a97e-600a1904a7a0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339163091 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.2339163091 |
| Directory | /workspace/0.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_mem_access.3890376473 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 14381869490 ps |
| CPU time | 1683.45 seconds |
| Started | Jul 31 08:17:03 PM PDT 24 |
| Finished | Jul 31 08:45:06 PM PDT 24 |
| Peak memory | 607948 kb |
| Host | smart-7ec13e12-e438-4faa-9a5c-b72986a2bb93 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890376473 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.3 890376473 |
| Directory | /workspace/1.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.333826902 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 3777795078 ps |
| CPU time | 433.27 seconds |
| Started | Jul 31 08:25:51 PM PDT 24 |
| Finished | Jul 31 08:33:04 PM PDT 24 |
| Peak memory | 619908 kb |
| Host | smart-08cc5175-8cdd-4251-850e-220317429b8d |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3 33826902 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.333826902 |
| Directory | /workspace/1.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sival_flash_info_access.3631175276 |
| Short name | T1352 |
| Test name | |
| Test status | |
| Simulation time | 3180138820 ps |
| CPU time | 476.64 seconds |
| Started | Jul 31 08:21:33 PM PDT 24 |
| Finished | Jul 31 08:29:30 PM PDT 24 |
| Peak memory | 609960 kb |
| Host | smart-ee8287e0-9b08-4485-acff-53314363cabb |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3631175276 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.3631175276 |
| Directory | /workspace/1.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3446917322 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 18119790328 ps |
| CPU time | 631.97 seconds |
| Started | Jul 31 08:21:49 PM PDT 24 |
| Finished | Jul 31 08:32:22 PM PDT 24 |
| Peak memory | 619424 kb |
| Host | smart-24d31884-616b-4215-b870-f49259fa1250 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3446917322 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3446917322 |
| Directory | /workspace/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc.2878965433 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 2077966896 ps |
| CPU time | 284.35 seconds |
| Started | Jul 31 08:21:32 PM PDT 24 |
| Finished | Jul 31 08:26:17 PM PDT 24 |
| Peak memory | 609728 kb |
| Host | smart-f16b317c-327a-4333-8fed-2de86ec45a29 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878965433 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.2878965433 |
| Directory | /workspace/1.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.3866496857 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 3376639841 ps |
| CPU time | 290.36 seconds |
| Started | Jul 31 08:21:51 PM PDT 24 |
| Finished | Jul 31 08:26:41 PM PDT 24 |
| Peak memory | 609696 kb |
| Host | smart-c7a4f218-7001-4112-9e7c-6c94944e6af8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866 496857 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.3866496857 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2273990827 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 3063746528 ps |
| CPU time | 269.87 seconds |
| Started | Jul 31 08:27:30 PM PDT 24 |
| Finished | Jul 31 08:32:00 PM PDT 24 |
| Peak memory | 608680 kb |
| Host | smart-be098567-dbb9-433f-a1e2-9440641a9882 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273990827 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.2273990827 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_entropy.2712869135 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 3073861416 ps |
| CPU time | 274.1 seconds |
| Started | Jul 31 08:21:16 PM PDT 24 |
| Finished | Jul 31 08:25:51 PM PDT 24 |
| Peak memory | 609684 kb |
| Host | smart-715bc884-07be-4c7c-84ea-67c5ce20d107 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712869135 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_entropy.2712869135 |
| Directory | /workspace/1.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_idle.3288819844 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 2555389248 ps |
| CPU time | 285.26 seconds |
| Started | Jul 31 08:23:26 PM PDT 24 |
| Finished | Jul 31 08:28:12 PM PDT 24 |
| Peak memory | 609644 kb |
| Host | smart-5fec3f6c-83ad-4686-b5f0-13a312ed4f0c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288819844 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.3288819844 |
| Directory | /workspace/1.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_masking_off.685488530 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 3484343733 ps |
| CPU time | 381.79 seconds |
| Started | Jul 31 08:22:51 PM PDT 24 |
| Finished | Jul 31 08:29:13 PM PDT 24 |
| Peak memory | 610524 kb |
| Host | smart-ad1c79ed-9c43-44a8-a95a-cb88ae68afbf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685488530 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_masking_off.685488530 |
| Directory | /workspace/1.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_smoketest.822789066 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 3152322798 ps |
| CPU time | 307.74 seconds |
| Started | Jul 31 08:27:22 PM PDT 24 |
| Finished | Jul 31 08:32:31 PM PDT 24 |
| Peak memory | 609752 kb |
| Host | smart-ca83b3cf-e40b-4fff-af4f-596b55c9298b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822789066 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_smoketest.822789066 |
| Directory | /workspace/1.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_entropy.2288150994 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 2557955709 ps |
| CPU time | 282.44 seconds |
| Started | Jul 31 08:22:32 PM PDT 24 |
| Finished | Jul 31 08:27:15 PM PDT 24 |
| Peak memory | 609756 kb |
| Host | smart-b219d8cb-71c0-413e-9ed6-ac9cdbe93cbe |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2288150994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.2288150994 |
| Directory | /workspace/1.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_escalation.2176292795 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 5876245000 ps |
| CPU time | 787.67 seconds |
| Started | Jul 31 08:21:49 PM PDT 24 |
| Finished | Jul 31 08:34:57 PM PDT 24 |
| Peak memory | 619616 kb |
| Host | smart-d0c283db-091a-47fc-9c20-dd9cc6245fd7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=2176292795 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.2176292795 |
| Directory | /workspace/1.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.1231273623 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 9107582520 ps |
| CPU time | 2019.69 seconds |
| Started | Jul 31 08:21:25 PM PDT 24 |
| Finished | Jul 31 08:55:05 PM PDT 24 |
| Peak memory | 610072 kb |
| Host | smart-0d1e32a5-f395-4f43-a71b-2cee2e09c6da |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1231273623 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.1231273623 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.3952722912 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 8838317744 ps |
| CPU time | 2053.96 seconds |
| Started | Jul 31 08:24:09 PM PDT 24 |
| Finished | Jul 31 08:58:23 PM PDT 24 |
| Peak memory | 610048 kb |
| Host | smart-a47f3dda-9e41-4383-8083-f10fdeebf62a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952722912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_togg le.3952722912 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.2559097192 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 7535945528 ps |
| CPU time | 1707.95 seconds |
| Started | Jul 31 08:22:38 PM PDT 24 |
| Finished | Jul 31 08:51:06 PM PDT 24 |
| Peak memory | 610000 kb |
| Host | smart-d8656dc0-58f1-4f8d-8955-b1762a4059b4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2559097192 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_ok.2559097192 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.459191816 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 3353897454 ps |
| CPU time | 377.83 seconds |
| Started | Jul 31 08:22:59 PM PDT 24 |
| Finished | Jul 31 08:29:17 PM PDT 24 |
| Peak memory | 609820 kb |
| Host | smart-f0268692-50f7-4016-bdba-22cba8c10dec |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=459191816 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.459191816 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1071797528 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 255051355736 ps |
| CPU time | 11092.1 seconds |
| Started | Jul 31 08:21:39 PM PDT 24 |
| Finished | Jul 31 11:26:33 PM PDT 24 |
| Peak memory | 610568 kb |
| Host | smart-8b51932c-b2ec-47e3-989f-99d44cb4471d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1071797528 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1071797528 |
| Directory | /workspace/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/1.chip_sw_all_escalation_resets.2711618313 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 5096698116 ps |
| CPU time | 657.2 seconds |
| Started | Jul 31 08:17:50 PM PDT 24 |
| Finished | Jul 31 08:28:47 PM PDT 24 |
| Peak memory | 650524 kb |
| Host | smart-96934cb4-20ec-407d-b7f9-2eb0ebc35ada |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2711618313 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.2711618313 |
| Directory | /workspace/1.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_irq.3121549127 |
| Short name | T1333 |
| Test name | |
| Test status | |
| Simulation time | 3836823434 ps |
| CPU time | 344.31 seconds |
| Started | Jul 31 08:21:17 PM PDT 24 |
| Finished | Jul 31 08:27:02 PM PDT 24 |
| Peak memory | 609696 kb |
| Host | smart-f60e735f-ad6f-4e27-8618-488a6cdf4ab7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121549127 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.3121549127 |
| Directory | /workspace/1.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.847511202 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 6111292312 ps |
| CPU time | 403.7 seconds |
| Started | Jul 31 08:21:02 PM PDT 24 |
| Finished | Jul 31 08:27:46 PM PDT 24 |
| Peak memory | 610536 kb |
| Host | smart-efc658c6-3b8c-4740-b183-81a072757cbc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=847511202 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.847511202 |
| Directory | /workspace/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.3853885999 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 3638148152 ps |
| CPU time | 346.31 seconds |
| Started | Jul 31 08:26:28 PM PDT 24 |
| Finished | Jul 31 08:32:15 PM PDT 24 |
| Peak memory | 609592 kb |
| Host | smart-dd0ed0e0-21a4-4128-9006-17a7c4e88ae8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853885999 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_aon_timer_smoketest.3853885999 |
| Directory | /workspace/1.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.1778069392 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 9190091250 ps |
| CPU time | 937.09 seconds |
| Started | Jul 31 08:20:18 PM PDT 24 |
| Finished | Jul 31 08:35:56 PM PDT 24 |
| Peak memory | 609232 kb |
| Host | smart-2af45f9a-0e88-4495-a991-615511de47f1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1778069392 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.1778069392 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.3566443491 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 5479815880 ps |
| CPU time | 815.34 seconds |
| Started | Jul 31 08:23:20 PM PDT 24 |
| Finished | Jul 31 08:36:56 PM PDT 24 |
| Peak memory | 610440 kb |
| Host | smart-3c582bde-0f65-4734-b340-130b6bb10d42 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3566443491 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.3566443491 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_outputs.324082987 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 7939900554 ps |
| CPU time | 1225.32 seconds |
| Started | Jul 31 08:26:33 PM PDT 24 |
| Finished | Jul 31 08:46:59 PM PDT 24 |
| Peak memory | 617300 kb |
| Host | smart-f7ff8d09-9730-499b-a486-9a1f0442c632 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324082987 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.324082987 |
| Directory | /workspace/1.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.3823998176 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 23209129199 ps |
| CPU time | 3623.64 seconds |
| Started | Jul 31 08:27:10 PM PDT 24 |
| Finished | Jul 31 09:27:34 PM PDT 24 |
| Peak memory | 610600 kb |
| Host | smart-eb4d8ee6-88f9-48ea-8d2c-91e986b4773e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823998176 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_rst_inputs.3823998176 |
| Directory | /workspace/1.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1104462819 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 11722474437 ps |
| CPU time | 996 seconds |
| Started | Jul 31 08:23:23 PM PDT 24 |
| Finished | Jul 31 08:39:59 PM PDT 24 |
| Peak memory | 621244 kb |
| Host | smart-723b7757-6ba8-43c9-9b5c-715cb3b04c84 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=1104462819 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.1104462819 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1741598822 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 3942425280 ps |
| CPU time | 675.35 seconds |
| Started | Jul 31 08:24:17 PM PDT 24 |
| Finished | Jul 31 08:35:32 PM PDT 24 |
| Peak memory | 612860 kb |
| Host | smart-1ba38d43-a2f4-45cf-8f5c-7ae5a6203ea7 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741598822 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.1741598822 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.280521899 |
| Short name | T1336 |
| Test name | |
| Test status | |
| Simulation time | 3613569942 ps |
| CPU time | 569.76 seconds |
| Started | Jul 31 08:24:12 PM PDT 24 |
| Finished | Jul 31 08:33:42 PM PDT 24 |
| Peak memory | 613136 kb |
| Host | smart-8dcda737-dfb7-4141-a262-f67ae1766ca6 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280521899 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_cl kmgr_external_clk_src_for_sw_fast_rma.280521899 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1735867452 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 3884033746 ps |
| CPU time | 670.31 seconds |
| Started | Jul 31 08:23:07 PM PDT 24 |
| Finished | Jul 31 08:34:18 PM PDT 24 |
| Peak memory | 612936 kb |
| Host | smart-55ff3252-2ff3-4456-a034-d5896ebbe31f |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735867452 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1735867452 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.864797874 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 4838861656 ps |
| CPU time | 793.36 seconds |
| Started | Jul 31 08:24:31 PM PDT 24 |
| Finished | Jul 31 08:37:44 PM PDT 24 |
| Peak memory | 613132 kb |
| Host | smart-ba6ae8e1-9657-4f8f-8c24-27feb4d39097 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864797874 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_cl kmgr_external_clk_src_for_sw_slow_dev.864797874 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3557845453 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 4008613776 ps |
| CPU time | 576.34 seconds |
| Started | Jul 31 08:23:34 PM PDT 24 |
| Finished | Jul 31 08:33:11 PM PDT 24 |
| Peak memory | 612912 kb |
| Host | smart-8c87cb63-3518-42db-a767-33cae9f944e0 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557845453 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.3557845453 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.116599915 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 4243481160 ps |
| CPU time | 582.59 seconds |
| Started | Jul 31 08:24:27 PM PDT 24 |
| Finished | Jul 31 08:34:09 PM PDT 24 |
| Peak memory | 613156 kb |
| Host | smart-217bbbba-1554-455f-a739-6e7570d99c68 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116599915 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1. chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.116599915 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter.3123653360 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 2837976785 ps |
| CPU time | 294.52 seconds |
| Started | Jul 31 08:24:33 PM PDT 24 |
| Finished | Jul 31 08:29:28 PM PDT 24 |
| Peak memory | 609812 kb |
| Host | smart-989244db-16fb-4eeb-8186-b0701c0b9e34 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123653360 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_clkmgr_jitter.3123653360 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.4278729473 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 4070810320 ps |
| CPU time | 545.44 seconds |
| Started | Jul 31 08:24:10 PM PDT 24 |
| Finished | Jul 31 08:33:16 PM PDT 24 |
| Peak memory | 609428 kb |
| Host | smart-e1209b48-2acc-45cd-8399-a9a219922505 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278729473 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_frequency.4278729473 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.4201252078 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 3016842743 ps |
| CPU time | 238.47 seconds |
| Started | Jul 31 08:25:30 PM PDT 24 |
| Finished | Jul 31 08:29:29 PM PDT 24 |
| Peak memory | 609708 kb |
| Host | smart-2e1d4537-b5ac-40ec-8bd9-c7a9023df062 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201252078 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.4201252078 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.1404971358 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 4614002856 ps |
| CPU time | 526.44 seconds |
| Started | Jul 31 08:24:40 PM PDT 24 |
| Finished | Jul 31 08:33:26 PM PDT 24 |
| Peak memory | 610396 kb |
| Host | smart-53c0ec8f-a416-4cdc-8af1-8196e3ecccc6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404971358 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.1404971358 |
| Directory | /workspace/1.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.1609196997 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 4701382076 ps |
| CPU time | 531.19 seconds |
| Started | Jul 31 08:23:24 PM PDT 24 |
| Finished | Jul 31 08:32:16 PM PDT 24 |
| Peak memory | 610168 kb |
| Host | smart-46033319-5f65-4c4f-8054-538b56e17ea6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609196997 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_hmac_trans.1609196997 |
| Directory | /workspace/1.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.2363210105 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 4143942264 ps |
| CPU time | 443.73 seconds |
| Started | Jul 31 08:23:43 PM PDT 24 |
| Finished | Jul 31 08:31:07 PM PDT 24 |
| Peak memory | 610124 kb |
| Host | smart-f7846dc9-699b-42cd-a955-6b49e6d9f8e4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363210105 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_kmac_trans.2363210105 |
| Directory | /workspace/1.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.1748943471 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 5330966180 ps |
| CPU time | 537.55 seconds |
| Started | Jul 31 08:24:05 PM PDT 24 |
| Finished | Jul 31 08:33:03 PM PDT 24 |
| Peak memory | 610376 kb |
| Host | smart-1c1cf904-bc85-4900-8d5a-237aec0055a9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748943471 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_otbn_trans.1748943471 |
| Directory | /workspace/1.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3153238526 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 10802577896 ps |
| CPU time | 1638.06 seconds |
| Started | Jul 31 08:23:11 PM PDT 24 |
| Finished | Jul 31 08:50:29 PM PDT 24 |
| Peak memory | 610524 kb |
| Host | smart-54136f02-d65d-4f7d-9c10-5f283ee5f7a3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153238526 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.3153238526 |
| Directory | /workspace/1.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.4152442084 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 3141385912 ps |
| CPU time | 445.35 seconds |
| Started | Jul 31 08:24:24 PM PDT 24 |
| Finished | Jul 31 08:31:50 PM PDT 24 |
| Peak memory | 609988 kb |
| Host | smart-bcdbc4de-0d9a-42aa-9950-aea09113edd3 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152442084 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.4152442084 |
| Directory | /workspace/1.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.4209334232 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 4160886744 ps |
| CPU time | 661.6 seconds |
| Started | Jul 31 08:23:34 PM PDT 24 |
| Finished | Jul 31 08:34:35 PM PDT 24 |
| Peak memory | 609996 kb |
| Host | smart-30bb8200-d4b0-4f68-9350-dafd63e6ad9a |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209334232 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.4209334232 |
| Directory | /workspace/1.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.934408516 |
| Short name | T1317 |
| Test name | |
| Test status | |
| Simulation time | 3249089932 ps |
| CPU time | 254.89 seconds |
| Started | Jul 31 08:32:48 PM PDT 24 |
| Finished | Jul 31 08:37:04 PM PDT 24 |
| Peak memory | 609224 kb |
| Host | smart-c75913e2-8aea-4204-a3f9-08da58a8f0c1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934408516 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_clkmgr_smoketest.934408516 |
| Directory | /workspace/1.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.4271064845 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 13395304700 ps |
| CPU time | 3183.16 seconds |
| Started | Jul 31 08:22:53 PM PDT 24 |
| Finished | Jul 31 09:15:57 PM PDT 24 |
| Peak memory | 610504 kb |
| Host | smart-fba56592-85d7-433c-888c-79d637d521da |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271064845 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency.4271064845 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.3607666048 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 3788322900 ps |
| CPU time | 496.92 seconds |
| Started | Jul 31 08:26:13 PM PDT 24 |
| Finished | Jul 31 08:34:30 PM PDT 24 |
| Peak memory | 609488 kb |
| Host | smart-3eff1c1b-a51b-44a6-9c07-a42ea9414cb0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36076 66048 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.3607666048 |
| Directory | /workspace/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_kat_test.4244717267 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 2866658754 ps |
| CPU time | 249.2 seconds |
| Started | Jul 31 08:21:59 PM PDT 24 |
| Finished | Jul 31 08:26:08 PM PDT 24 |
| Peak memory | 609716 kb |
| Host | smart-a2206c87-e22e-4310-9b45-de804202b05f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244717267 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_kat_test.4244717267 |
| Directory | /workspace/1.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.4257115752 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 8130188137 ps |
| CPU time | 673.34 seconds |
| Started | Jul 31 08:22:01 PM PDT 24 |
| Finished | Jul 31 08:33:15 PM PDT 24 |
| Peak memory | 610032 kb |
| Host | smart-419aafe1-7d9d-4561-b4d5-f728c4aed4af |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257115752 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csr ng_lc_hw_debug_en_test.4257115752 |
| Directory | /workspace/1.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_smoketest.69228200 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 2286105284 ps |
| CPU time | 247.15 seconds |
| Started | Jul 31 08:28:32 PM PDT 24 |
| Finished | Jul 31 08:32:40 PM PDT 24 |
| Peak memory | 608424 kb |
| Host | smart-27997a49-3ca2-4405-b39e-c0fb075bc016 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69228200 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_smoketest.69228200 |
| Directory | /workspace/1.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_data_integrity_escalation.4093684284 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 4778118278 ps |
| CPU time | 687.14 seconds |
| Started | Jul 31 08:17:53 PM PDT 24 |
| Finished | Jul 31 08:29:21 PM PDT 24 |
| Peak memory | 611116 kb |
| Host | smart-e773c108-1bba-4a16-800e-81fd6f0c1d7d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4093684284 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.4093684284 |
| Directory | /workspace/1.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_boot_mode.380577379 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 3232368950 ps |
| CPU time | 789.81 seconds |
| Started | Jul 31 08:22:21 PM PDT 24 |
| Finished | Jul 31 08:35:32 PM PDT 24 |
| Peak memory | 610108 kb |
| Host | smart-cab49e59-7d4f-40e9-bdbe-98d9e3a2072f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380577379 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_b oot_mode.380577379 |
| Directory | /workspace/1.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.686546914 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 7205692615 ps |
| CPU time | 1080.68 seconds |
| Started | Jul 31 08:21:53 PM PDT 24 |
| Finished | Jul 31 08:39:54 PM PDT 24 |
| Peak memory | 611036 kb |
| Host | smart-19234205-bf9c-4e00-ab51-c9f4e4fdad5c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686546914 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.686546914 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_kat.604122756 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 3564782120 ps |
| CPU time | 667.76 seconds |
| Started | Jul 31 08:21:39 PM PDT 24 |
| Finished | Jul 31 08:32:47 PM PDT 24 |
| Peak memory | 615380 kb |
| Host | smart-99351854-2318-47c2-83fd-fc320a26f732 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604122756 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_edn_kat.604122756 |
| Directory | /workspace/1.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_sw_mode.850176844 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 9291662748 ps |
| CPU time | 2116 seconds |
| Started | Jul 31 08:22:50 PM PDT 24 |
| Finished | Jul 31 08:58:06 PM PDT 24 |
| Peak memory | 610020 kb |
| Host | smart-86a1fbca-2947-4aa8-ab0a-888706821771 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850176844 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_sw_mode.850176844 |
| Directory | /workspace/1.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.3159129769 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 2537842794 ps |
| CPU time | 161.97 seconds |
| Started | Jul 31 08:21:02 PM PDT 24 |
| Finished | Jul 31 08:23:44 PM PDT 24 |
| Peak memory | 608684 kb |
| Host | smart-833ec753-7d35-4f34-8c13-7e33834a425a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31 59129769 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.3159129769 |
| Directory | /workspace/1.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.3857988297 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 3446773300 ps |
| CPU time | 254.67 seconds |
| Started | Jul 31 08:21:25 PM PDT 24 |
| Finished | Jul 31 08:25:41 PM PDT 24 |
| Peak memory | 608812 kb |
| Host | smart-d3185ddd-934a-4738-81e1-6a8420935ed4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857988297 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.3857988297 |
| Directory | /workspace/1.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.3863124318 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 4198706000 ps |
| CPU time | 575.34 seconds |
| Started | Jul 31 08:33:52 PM PDT 24 |
| Finished | Jul 31 08:43:28 PM PDT 24 |
| Peak memory | 609368 kb |
| Host | smart-ff3e4bff-9c68-42e7-b4ae-663885f60583 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3863124318 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.3863124318 |
| Directory | /workspace/1.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_concurrency.1153151685 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 3036171448 ps |
| CPU time | 187.3 seconds |
| Started | Jul 31 08:15:23 PM PDT 24 |
| Finished | Jul 31 08:18:30 PM PDT 24 |
| Peak memory | 609760 kb |
| Host | smart-9979e793-16b8-4df0-8409-7bf04ba73e87 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153151685 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_example_concurrency.1153151685 |
| Directory | /workspace/1.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_flash.1373543516 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 2804540140 ps |
| CPU time | 230.75 seconds |
| Started | Jul 31 08:17:44 PM PDT 24 |
| Finished | Jul 31 08:21:35 PM PDT 24 |
| Peak memory | 609672 kb |
| Host | smart-c3b01bc7-649a-4815-97f1-b0a8e604611f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373543516 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_flash.1373543516 |
| Directory | /workspace/1.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_manufacturer.3423997766 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 3134281972 ps |
| CPU time | 203.06 seconds |
| Started | Jul 31 08:18:13 PM PDT 24 |
| Finished | Jul 31 08:21:37 PM PDT 24 |
| Peak memory | 609684 kb |
| Host | smart-01208a2b-6b0e-4cb5-afc1-14dade570428 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423997766 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_manufacturer.3423997766 |
| Directory | /workspace/1.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_rom.3699977381 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 2506410270 ps |
| CPU time | 144.8 seconds |
| Started | Jul 31 08:18:19 PM PDT 24 |
| Finished | Jul 31 08:20:44 PM PDT 24 |
| Peak memory | 609096 kb |
| Host | smart-5a833bf3-4db9-4449-b8ff-52a1d23d07cc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699977381 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_rom.3699977381 |
| Directory | /workspace/1.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.3936759280 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 59007383797 ps |
| CPU time | 10730 seconds |
| Started | Jul 31 08:17:18 PM PDT 24 |
| Finished | Jul 31 11:16:09 PM PDT 24 |
| Peak memory | 624780 kb |
| Host | smart-7f5c3848-d4ba-4e4f-95c6-8bae7b9dd0d2 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3936759280 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_exit_test_unlocked_bootstrap.3936759280 |
| Directory | /workspace/1.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_crash_alert.3628588049 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 4693994760 ps |
| CPU time | 840.12 seconds |
| Started | Jul 31 08:26:21 PM PDT 24 |
| Finished | Jul 31 08:40:22 PM PDT 24 |
| Peak memory | 611256 kb |
| Host | smart-4c47aa20-e326-45bf-a209-e3a2fbcc3cba |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=3628588049 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.3628588049 |
| Directory | /workspace/1.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access.4201391473 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 5329779864 ps |
| CPU time | 927.08 seconds |
| Started | Jul 31 08:18:01 PM PDT 24 |
| Finished | Jul 31 08:33:28 PM PDT 24 |
| Peak memory | 610068 kb |
| Host | smart-3625e860-d989-4c3c-83b3-e64eb4961e0a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201391473 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_flash_ctrl_access.4201391473 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1772580662 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 6719161956 ps |
| CPU time | 742.97 seconds |
| Started | Jul 31 08:18:00 PM PDT 24 |
| Finished | Jul 31 08:30:23 PM PDT 24 |
| Peak memory | 609584 kb |
| Host | smart-6c009727-fc5f-4112-aaba-5ca438dfed93 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772580662 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en.1772580662 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4219154354 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 7232161167 ps |
| CPU time | 1205.2 seconds |
| Started | Jul 31 08:26:58 PM PDT 24 |
| Finished | Jul 31 08:47:04 PM PDT 24 |
| Peak memory | 610112 kb |
| Host | smart-7f8a2dd4-d880-47b8-84f7-6341fa8fe776 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219154354 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4219154354 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.487232869 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 5301554775 ps |
| CPU time | 1004.77 seconds |
| Started | Jul 31 08:18:28 PM PDT 24 |
| Finished | Jul 31 08:35:13 PM PDT 24 |
| Peak memory | 609912 kb |
| Host | smart-de070204-9de0-4f06-92ee-9ca760babb71 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487232869 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_flash_ctrl_clock_freqs.487232869 |
| Directory | /workspace/1.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1980433057 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 3615849176 ps |
| CPU time | 347.24 seconds |
| Started | Jul 31 08:19:15 PM PDT 24 |
| Finished | Jul 31 08:25:03 PM PDT 24 |
| Peak memory | 609628 kb |
| Host | smart-364ef6f8-b54c-4c5b-ba21-c785d630a3e3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980433057 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_idle_low_power.1980433057 |
| Directory | /workspace/1.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.94745689 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 5658414668 ps |
| CPU time | 747.77 seconds |
| Started | Jul 31 08:19:28 PM PDT 24 |
| Finished | Jul 31 08:31:57 PM PDT 24 |
| Peak memory | 609600 kb |
| Host | smart-ca29db94-68a9-4da6-8781-efe7d3c08dc7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94 745689 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_lc_rw_en.94745689 |
| Directory | /workspace/1.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.751082165 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 5368071800 ps |
| CPU time | 1396.4 seconds |
| Started | Jul 31 08:25:44 PM PDT 24 |
| Finished | Jul 31 08:49:00 PM PDT 24 |
| Peak memory | 609820 kb |
| Host | smart-c5d3e9c3-fa1f-42f7-b4ec-b220c07276d3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751082165 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_mem_protection.751082165 |
| Directory | /workspace/1.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.3574978078 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 3895598014 ps |
| CPU time | 750.18 seconds |
| Started | Jul 31 08:21:28 PM PDT 24 |
| Finished | Jul 31 08:33:58 PM PDT 24 |
| Peak memory | 609856 kb |
| Host | smart-01d61290-a986-45c0-92e5-00b6ed4a30be |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574978078 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.3574978078 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.2252535982 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 4396220686 ps |
| CPU time | 509.62 seconds |
| Started | Jul 31 08:18:19 PM PDT 24 |
| Finished | Jul 31 08:26:49 PM PDT 24 |
| Peak memory | 609748 kb |
| Host | smart-fae985c5-45c2-49c6-ae94-1e65e4b1e30a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2252535982 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.2252535982 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3121843608 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 4258853184 ps |
| CPU time | 884.02 seconds |
| Started | Jul 31 08:27:07 PM PDT 24 |
| Finished | Jul 31 08:41:51 PM PDT 24 |
| Peak memory | 609912 kb |
| Host | smart-0f6a3ca6-9351-4257-8464-172b7c7ea5e8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3121843608 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3121843608 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.3171791572 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 3869007112 ps |
| CPU time | 451.91 seconds |
| Started | Jul 31 08:24:54 PM PDT 24 |
| Finished | Jul 31 08:32:26 PM PDT 24 |
| Peak memory | 609664 kb |
| Host | smart-d74d0ea7-81c5-4cbd-b23c-b2c00e286dd7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171791 572 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_write_clear.3171791572 |
| Directory | /workspace/1.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init.1030289663 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 19383796945 ps |
| CPU time | 2064.69 seconds |
| Started | Jul 31 08:17:36 PM PDT 24 |
| Finished | Jul 31 08:52:01 PM PDT 24 |
| Peak memory | 613516 kb |
| Host | smart-c7bee5b6-f874-4342-91da-27bda69b7f3f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030289663 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init.1030289663 |
| Directory | /workspace/1.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.1599209604 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 17023551841 ps |
| CPU time | 1819.32 seconds |
| Started | Jul 31 08:25:21 PM PDT 24 |
| Finished | Jul 31 08:55:41 PM PDT 24 |
| Peak memory | 612496 kb |
| Host | smart-cb6baff0-daf9-4526-8c3e-1d375dab3581 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1599209604 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.1599209604 |
| Directory | /workspace/1.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.3521728193 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 2585216304 ps |
| CPU time | 198.4 seconds |
| Started | Jul 31 08:30:30 PM PDT 24 |
| Finished | Jul 31 08:33:49 PM PDT 24 |
| Peak memory | 609876 kb |
| Host | smart-11d9afb0-7340-4c51-aeac-dc45ce191f22 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3521728193 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.3521728193 |
| Directory | /workspace/1.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio_smoketest.412627464 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 3594716919 ps |
| CPU time | 343.51 seconds |
| Started | Jul 31 08:28:01 PM PDT 24 |
| Finished | Jul 31 08:33:45 PM PDT 24 |
| Peak memory | 609072 kb |
| Host | smart-185d1b4b-2004-44ef-bcd6-e13d21f1ca84 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412627464 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_gpio_smoketest.412627464 |
| Directory | /workspace/1.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc.2635276650 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 2570550250 ps |
| CPU time | 289.26 seconds |
| Started | Jul 31 08:22:56 PM PDT 24 |
| Finished | Jul 31 08:27:46 PM PDT 24 |
| Peak memory | 608504 kb |
| Host | smart-df19ea24-0f45-46f7-a830-5d630513863a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635276650 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc.2635276650 |
| Directory | /workspace/1.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_idle.1975463343 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 2868334072 ps |
| CPU time | 291.63 seconds |
| Started | Jul 31 08:22:53 PM PDT 24 |
| Finished | Jul 31 08:27:45 PM PDT 24 |
| Peak memory | 609700 kb |
| Host | smart-d30156ca-fca8-439f-a51b-2a7e98a556e8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975463343 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_hmac_enc_idle.1975463343 |
| Directory | /workspace/1.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.2742823463 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 2663826920 ps |
| CPU time | 263.67 seconds |
| Started | Jul 31 08:24:05 PM PDT 24 |
| Finished | Jul 31 08:28:29 PM PDT 24 |
| Peak memory | 609704 kb |
| Host | smart-1f35a78a-cd09-4033-81fb-80c0b8758f07 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742823463 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en.2742823463 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1533950861 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 2730054494 ps |
| CPU time | 286.47 seconds |
| Started | Jul 31 08:26:48 PM PDT 24 |
| Finished | Jul 31 08:31:35 PM PDT 24 |
| Peak memory | 608548 kb |
| Host | smart-352ab4e4-e74c-499c-9e37-fd0b2d57b9dc |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533950861 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.1533950861 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_multistream.1200548903 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 8276653026 ps |
| CPU time | 2031.82 seconds |
| Started | Jul 31 08:21:57 PM PDT 24 |
| Finished | Jul 31 08:55:49 PM PDT 24 |
| Peak memory | 610136 kb |
| Host | smart-d97874d1-fa6f-4f7e-908b-ca1c4328c133 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200548903 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_hmac_multistream.1200548903 |
| Directory | /workspace/1.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_oneshot.2037784219 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 2820944506 ps |
| CPU time | 360.34 seconds |
| Started | Jul 31 08:22:22 PM PDT 24 |
| Finished | Jul 31 08:28:23 PM PDT 24 |
| Peak memory | 609740 kb |
| Host | smart-f0625395-7d0a-4ad8-8443-8448109448dc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037784219 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_oneshot.2037784219 |
| Directory | /workspace/1.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_smoketest.2298590169 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 3365929740 ps |
| CPU time | 325.8 seconds |
| Started | Jul 31 08:27:21 PM PDT 24 |
| Finished | Jul 31 08:32:47 PM PDT 24 |
| Peak memory | 609664 kb |
| Host | smart-8f50e9c0-2e79-4bcd-b82e-0ab552514325 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298590169 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_hmac_smoketest.2298590169 |
| Directory | /workspace/1.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.805576990 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 4049261450 ps |
| CPU time | 541.9 seconds |
| Started | Jul 31 08:20:31 PM PDT 24 |
| Finished | Jul 31 08:29:34 PM PDT 24 |
| Peak memory | 610528 kb |
| Host | smart-25e220a1-e9d9-4cb5-9a36-ac015b0bfad9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805576990 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.805576990 |
| Directory | /workspace/1.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.2997622121 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 4664036416 ps |
| CPU time | 647.62 seconds |
| Started | Jul 31 08:17:53 PM PDT 24 |
| Finished | Jul 31 08:28:41 PM PDT 24 |
| Peak memory | 609224 kb |
| Host | smart-499a0311-173e-4fd3-923d-897147006c6d |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997622121 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx.2997622121 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.574880454 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 5307911352 ps |
| CPU time | 792.61 seconds |
| Started | Jul 31 08:17:56 PM PDT 24 |
| Finished | Jul 31 08:31:09 PM PDT 24 |
| Peak memory | 610236 kb |
| Host | smart-19aa1e59-ecd6-40f9-8e12-072568050a89 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574880454 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.574880454 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.4264414519 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 4867807620 ps |
| CPU time | 858.97 seconds |
| Started | Jul 31 08:17:02 PM PDT 24 |
| Finished | Jul 31 08:31:22 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-8fcaf6c8-7c6d-49da-ba15-b6116de40857 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264414519 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.4264414519 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_inject_scramble_seed.548024194 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 64823692410 ps |
| CPU time | 12875 seconds |
| Started | Jul 31 08:18:23 PM PDT 24 |
| Finished | Jul 31 11:52:59 PM PDT 24 |
| Peak memory | 624800 kb |
| Host | smart-07fd22da-5826-4fee-b135-ebbfe0aeb841 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=548024194 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.548024194 |
| Directory | /workspace/1.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.1609197100 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 8170575400 ps |
| CPU time | 1780.39 seconds |
| Started | Jul 31 08:22:56 PM PDT 24 |
| Finished | Jul 31 08:52:37 PM PDT 24 |
| Peak memory | 616860 kb |
| Host | smart-ee3656d6-bf49-413b-a24d-53ee404fa7eb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609 197100 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation.1609197100 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.1442597948 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 9164530607 ps |
| CPU time | 1530.71 seconds |
| Started | Jul 31 08:21:19 PM PDT 24 |
| Finished | Jul 31 08:46:50 PM PDT 24 |
| Peak memory | 617652 kb |
| Host | smart-6ce0c5d5-2a18-4fc7-9f9e-edde07d2119a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1442597948 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en.1442597948 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.257951861 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 8228859848 ps |
| CPU time | 1433.44 seconds |
| Started | Jul 31 08:26:26 PM PDT 24 |
| Finished | Jul 31 08:50:19 PM PDT 24 |
| Peak memory | 618028 kb |
| Host | smart-9adf6e91-faee-4c83-87fa-eba8674d1fd3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=257951861 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en_ reduced_freq.257951861 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.2185346936 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 6875944712 ps |
| CPU time | 1302.66 seconds |
| Started | Jul 31 08:22:29 PM PDT 24 |
| Finished | Jul 31 08:44:12 PM PDT 24 |
| Peak memory | 617892 kb |
| Host | smart-6f3b8386-2151-4684-bc3a-2a68df611b67 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2185346936 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.2185346936 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.1659659841 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 12841820380 ps |
| CPU time | 2578.85 seconds |
| Started | Jul 31 08:23:22 PM PDT 24 |
| Finished | Jul 31 09:06:22 PM PDT 24 |
| Peak memory | 611248 kb |
| Host | smart-31245d87-31ae-4377-aec9-ebba9767d8f3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165965 9841 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_aes.1659659841 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.2721166295 |
| Short name | T1370 |
| Test name | |
| Test status | |
| Simulation time | 11803888040 ps |
| CPU time | 2346.46 seconds |
| Started | Jul 31 08:24:04 PM PDT 24 |
| Finished | Jul 31 09:03:11 PM PDT 24 |
| Peak memory | 610284 kb |
| Host | smart-701d2519-b2bf-41e6-8345-5578d31b5524 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27211 66295 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.2721166295 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_app_rom.2693724229 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 3254646616 ps |
| CPU time | 219.85 seconds |
| Started | Jul 31 08:24:33 PM PDT 24 |
| Finished | Jul 31 08:28:13 PM PDT 24 |
| Peak memory | 609616 kb |
| Host | smart-f9ea329a-dc0e-44fd-b03b-392a8d8d0c8c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693724229 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_app_rom.2693724229 |
| Directory | /workspace/1.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_entropy.2374924749 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 2966855372 ps |
| CPU time | 259.45 seconds |
| Started | Jul 31 08:18:50 PM PDT 24 |
| Finished | Jul 31 08:23:10 PM PDT 24 |
| Peak memory | 608548 kb |
| Host | smart-94b0b84c-790b-4198-adf8-13f4031522f5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374924749 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_entropy.2374924749 |
| Directory | /workspace/1.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_idle.2535184473 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 2266146168 ps |
| CPU time | 184.05 seconds |
| Started | Jul 31 08:22:23 PM PDT 24 |
| Finished | Jul 31 08:25:27 PM PDT 24 |
| Peak memory | 609704 kb |
| Host | smart-c4cacf71-057c-4cd3-a37a-e21482233d5f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535184473 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_idle.2535184473 |
| Directory | /workspace/1.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.482957626 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 3403370384 ps |
| CPU time | 304.15 seconds |
| Started | Jul 31 08:23:32 PM PDT 24 |
| Finished | Jul 31 08:28:36 PM PDT 24 |
| Peak memory | 609680 kb |
| Host | smart-ddbf3765-41d4-4222-af47-e78c06be28e4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482957626 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_kmac_mode_cshake.482957626 |
| Directory | /workspace/1.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.3154215142 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 2448272746 ps |
| CPU time | 264.71 seconds |
| Started | Jul 31 08:22:30 PM PDT 24 |
| Finished | Jul 31 08:26:55 PM PDT 24 |
| Peak memory | 608464 kb |
| Host | smart-aea30993-6673-43cd-a302-5224ee43cc6f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154215142 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_kmac_mode_kmac.3154215142 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.467201741 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 2663268882 ps |
| CPU time | 251.72 seconds |
| Started | Jul 31 08:23:19 PM PDT 24 |
| Finished | Jul 31 08:27:31 PM PDT 24 |
| Peak memory | 609644 kb |
| Host | smart-1a12c87f-b6a2-4542-a4d1-adb7830d9be7 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467201741 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.467201741 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2178483134 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 3323363840 ps |
| CPU time | 363.35 seconds |
| Started | Jul 31 08:25:45 PM PDT 24 |
| Finished | Jul 31 08:31:48 PM PDT 24 |
| Peak memory | 608828 kb |
| Host | smart-1b3f71e3-e8fe-4735-8ca6-b8b56cf2e550 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21784831 34 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2178483134 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_smoketest.1014445399 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 2593288326 ps |
| CPU time | 319.42 seconds |
| Started | Jul 31 08:27:24 PM PDT 24 |
| Finished | Jul 31 08:32:44 PM PDT 24 |
| Peak memory | 609720 kb |
| Host | smart-08e51987-f83a-4944-ac13-a503d253225f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014445399 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_smoketest.1014445399 |
| Directory | /workspace/1.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.3662231425 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 2833343464 ps |
| CPU time | 253.99 seconds |
| Started | Jul 31 08:17:34 PM PDT 24 |
| Finished | Jul 31 08:21:48 PM PDT 24 |
| Peak memory | 609672 kb |
| Host | smart-28c93db0-f092-4320-aa53-b67d9cdcf98b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662231425 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg0.3662231425 |
| Directory | /workspace/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.2406208248 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 4367455704 ps |
| CPU time | 682.86 seconds |
| Started | Jul 31 08:25:37 PM PDT 24 |
| Finished | Jul 31 08:37:01 PM PDT 24 |
| Peak memory | 611224 kb |
| Host | smart-00ead536-7885-4c30-b12c-2199113d0b47 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2406208248 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_program_error.2406208248 |
| Directory | /workspace/1.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.412686612 |
| Short name | T1373 |
| Test name | |
| Test status | |
| Simulation time | 5168914341 ps |
| CPU time | 346.29 seconds |
| Started | Jul 31 08:19:43 PM PDT 24 |
| Finished | Jul 31 08:25:31 PM PDT 24 |
| Peak memory | 624720 kb |
| Host | smart-47eb59cf-c497-4e7a-b2c7-2082e4f4f9d0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412686612 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_transition.412686612 |
| Directory | /workspace/1.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.945592754 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 2389398485 ps |
| CPU time | 134.88 seconds |
| Started | Jul 31 08:21:44 PM PDT 24 |
| Finished | Jul 31 08:23:59 PM PDT 24 |
| Peak memory | 617064 kb |
| Host | smart-a372b5c2-57d4-47ff-b145-73fb527db891 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=945592754 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.945592754 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1218785414 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 2491275473 ps |
| CPU time | 114.62 seconds |
| Started | Jul 31 08:21:14 PM PDT 24 |
| Finished | Jul 31 08:23:09 PM PDT 24 |
| Peak memory | 617044 kb |
| Host | smart-eaeaa798-aab2-49d9-899b-29e6d105a853 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218785414 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1218785414 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.2086513928 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 46915461785 ps |
| CPU time | 5336.67 seconds |
| Started | Jul 31 08:19:37 PM PDT 24 |
| Finished | Jul 31 09:48:34 PM PDT 24 |
| Peak memory | 620616 kb |
| Host | smart-5d27b18c-28c3-4396-a136-43e6d9ed4ec4 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086513928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_dev.2086513928 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.2658782994 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 51112590774 ps |
| CPU time | 5464.12 seconds |
| Started | Jul 31 08:19:42 PM PDT 24 |
| Finished | Jul 31 09:50:48 PM PDT 24 |
| Peak memory | 620572 kb |
| Host | smart-ab358ec1-81a5-4da7-b2f6-1404a1235fff |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658782994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chi p_sw_lc_walkthrough_prod.2658782994 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.1008259620 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 10060067200 ps |
| CPU time | 776.2 seconds |
| Started | Jul 31 08:18:49 PM PDT 24 |
| Finished | Jul 31 08:31:46 PM PDT 24 |
| Peak memory | 620384 kb |
| Host | smart-f3deca20-61e8-4d58-914f-d47f6672a2ee |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008259620 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.1008259620 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.555248065 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 49058159222 ps |
| CPU time | 5144.95 seconds |
| Started | Jul 31 08:21:52 PM PDT 24 |
| Finished | Jul 31 09:47:39 PM PDT 24 |
| Peak memory | 620304 kb |
| Host | smart-7314b20d-6257-4b76-b959-1453483f028b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555248065 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_ sw_lc_walkthrough_rma.555248065 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.4042625925 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 16445577568 ps |
| CPU time | 3563.02 seconds |
| Started | Jul 31 08:21:20 PM PDT 24 |
| Finished | Jul 31 09:20:44 PM PDT 24 |
| Peak memory | 610224 kb |
| Host | smart-d08d071d-a6cd-4345-b6b5-9592b7571970 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=4042625925 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.4042625925 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.3612743437 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 18820629591 ps |
| CPU time | 3595.89 seconds |
| Started | Jul 31 08:21:06 PM PDT 24 |
| Finished | Jul 31 09:21:03 PM PDT 24 |
| Peak memory | 610272 kb |
| Host | smart-bfca42e8-2d18-4228-81ac-c7aadd44d7ed |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3612743437 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.3612743437 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.889107981 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 24941544537 ps |
| CPU time | 3473.07 seconds |
| Started | Jul 31 08:27:40 PM PDT 24 |
| Finished | Jul 31 09:25:33 PM PDT 24 |
| Peak memory | 610360 kb |
| Host | smart-10351ead-9b0b-44c6-b441-22a42c4020cd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889107981 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduc ed_freq.889107981 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.2205629940 |
| Short name | T1376 |
| Test name | |
| Test status | |
| Simulation time | 3449523372 ps |
| CPU time | 521.08 seconds |
| Started | Jul 31 08:21:30 PM PDT 24 |
| Finished | Jul 31 08:30:12 PM PDT 24 |
| Peak memory | 609856 kb |
| Host | smart-af763942-58a9-4058-b4cd-feac3054d96c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205629940 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.2205629940 |
| Directory | /workspace/1.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_randomness.2232734499 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 5801337800 ps |
| CPU time | 679.05 seconds |
| Started | Jul 31 08:19:57 PM PDT 24 |
| Finished | Jul 31 08:31:16 PM PDT 24 |
| Peak memory | 609032 kb |
| Host | smart-73cdd371-3ab0-4d3f-a423-ff91de99597a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2232734499 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.2232734499 |
| Directory | /workspace/1.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_smoketest.1290001049 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 7420994380 ps |
| CPU time | 1918.76 seconds |
| Started | Jul 31 08:26:47 PM PDT 24 |
| Finished | Jul 31 08:58:46 PM PDT 24 |
| Peak memory | 610376 kb |
| Host | smart-be4d7274-f51a-405f-a02a-e3da4ddc0ba7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290001049 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_otbn_smoketest.1290001049 |
| Directory | /workspace/1.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.2269155731 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 3006725021 ps |
| CPU time | 197.88 seconds |
| Started | Jul 31 08:19:16 PM PDT 24 |
| Finished | Jul 31 08:22:34 PM PDT 24 |
| Peak memory | 609356 kb |
| Host | smart-5a54fdea-8755-4173-800a-975357d61c2b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269155731 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_ecc_error_vendor_test.2269155731 |
| Directory | /workspace/1.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3614547481 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 7394173612 ps |
| CPU time | 1298.45 seconds |
| Started | Jul 31 08:22:23 PM PDT 24 |
| Finished | Jul 31 08:44:02 PM PDT 24 |
| Peak memory | 610688 kb |
| Host | smart-2d4cbe08-4e3b-4019-a674-644c71ab565c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3614547481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.3614547481 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.886551429 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 8461192660 ps |
| CPU time | 1516.69 seconds |
| Started | Jul 31 08:19:15 PM PDT 24 |
| Finished | Jul 31 08:44:32 PM PDT 24 |
| Peak memory | 610656 kb |
| Host | smart-437d9408-0632-4bdd-8942-21724c8fa87c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=886551429 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.886551429 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.1031852652 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 8057271948 ps |
| CPU time | 1153.54 seconds |
| Started | Jul 31 08:20:51 PM PDT 24 |
| Finished | Jul 31 08:40:05 PM PDT 24 |
| Peak memory | 610692 kb |
| Host | smart-930bae35-139c-4797-b061-2db530e67ec9 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1031852652 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.1031852652 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.386119243 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 4077982954 ps |
| CPU time | 765.95 seconds |
| Started | Jul 31 08:19:13 PM PDT 24 |
| Finished | Jul 31 08:31:59 PM PDT 24 |
| Peak memory | 609820 kb |
| Host | smart-b7dd2cc2-ac8b-47a6-91d7-d2e8703b02ae |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=386119243 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.386119243 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.2149650585 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 3439022388 ps |
| CPU time | 341.05 seconds |
| Started | Jul 31 08:26:32 PM PDT 24 |
| Finished | Jul 31 08:32:13 PM PDT 24 |
| Peak memory | 608436 kb |
| Host | smart-c8c600ca-c85e-4a7d-bd8f-a8d3fd79cc7a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149650585 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_otp_ctrl_smoketest.2149650585 |
| Directory | /workspace/1.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pattgen_ios.322626330 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 3715753010 ps |
| CPU time | 271.65 seconds |
| Started | Jul 31 08:19:31 PM PDT 24 |
| Finished | Jul 31 08:24:03 PM PDT 24 |
| Peak memory | 612372 kb |
| Host | smart-65c398aa-7ad7-4143-b1e2-3005ef70e97b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322626330 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.322626330 |
| Directory | /workspace/1.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/1.chip_sw_plic_sw_irq.1167026615 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 2783009524 ps |
| CPU time | 275.02 seconds |
| Started | Jul 31 08:25:32 PM PDT 24 |
| Finished | Jul 31 08:30:08 PM PDT 24 |
| Peak memory | 609620 kb |
| Host | smart-23f14d6a-19a6-49ca-ab33-2e0c2b2c24b4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167026615 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_plic_sw_irq.1167026615 |
| Directory | /workspace/1.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_idle_load.1045916760 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 3734413422 ps |
| CPU time | 693.56 seconds |
| Started | Jul 31 08:30:24 PM PDT 24 |
| Finished | Jul 31 08:41:59 PM PDT 24 |
| Peak memory | 608044 kb |
| Host | smart-29723be2-28c0-4ef0-9263-cbfb999132a9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045916760 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_idle_load.1045916760 |
| Directory | /workspace/1.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_sleep_load.1636573773 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 4698990712 ps |
| CPU time | 419.57 seconds |
| Started | Jul 31 08:25:52 PM PDT 24 |
| Finished | Jul 31 08:32:52 PM PDT 24 |
| Peak memory | 610312 kb |
| Host | smart-b1b03df4-d2d8-4780-9497-f41c33e5228c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636573773 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_power_sleep_load.1636573773 |
| Directory | /workspace/1.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_virus.566132688 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5944848344 ps |
| CPU time | 1614.78 seconds |
| Started | Jul 31 08:31:56 PM PDT 24 |
| Finished | Jul 31 08:58:51 PM PDT 24 |
| Peak memory | 625116 kb |
| Host | smart-a92a383e-b142-43b2-8584-44befe01af7b |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +accelerate_cold_ power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtes t_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=566132688 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_virus.566132688 |
| Directory | /workspace/1.chip_sw_power_virus/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2455958657 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 13382782996 ps |
| CPU time | 1727.57 seconds |
| Started | Jul 31 08:21:16 PM PDT 24 |
| Finished | Jul 31 08:50:04 PM PDT 24 |
| Peak memory | 611484 kb |
| Host | smart-97b3e7fa-f70c-4ab3-9987-c6c1ab672427 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455 958657 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.2455958657 |
| Directory | /workspace/1.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.907329896 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 27082836684 ps |
| CPU time | 1880.25 seconds |
| Started | Jul 31 08:25:47 PM PDT 24 |
| Finished | Jul 31 08:57:07 PM PDT 24 |
| Peak memory | 610848 kb |
| Host | smart-2634bfd5-5696-4585-9c90-1e325a3e9628 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907 329896 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.907329896 |
| Directory | /workspace/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1460137493 |
| Short name | T1353 |
| Test name | |
| Test status | |
| Simulation time | 16104302247 ps |
| CPU time | 1496.96 seconds |
| Started | Jul 31 08:19:33 PM PDT 24 |
| Finished | Jul 31 08:44:31 PM PDT 24 |
| Peak memory | 611284 kb |
| Host | smart-b353685c-fc26-47ee-97e2-99193d97a4f9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1460137493 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1460137493 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3542176951 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 25842861306 ps |
| CPU time | 1504.09 seconds |
| Started | Jul 31 08:23:47 PM PDT 24 |
| Finished | Jul 31 08:48:51 PM PDT 24 |
| Peak memory | 611928 kb |
| Host | smart-96f997c4-b146-4ed2-8118-0fa8b6610a9a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3542176951 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3542176951 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.4163267636 |
| Short name | T1385 |
| Test name | |
| Test status | |
| Simulation time | 7626011408 ps |
| CPU time | 860.34 seconds |
| Started | Jul 31 08:19:11 PM PDT 24 |
| Finished | Jul 31 08:33:31 PM PDT 24 |
| Peak memory | 610788 kb |
| Host | smart-9c83bd1b-82ed-4a29-b556-6b6627cceca0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163267636 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_por_reset.4163267636 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.820911172 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 6191338260 ps |
| CPU time | 498.06 seconds |
| Started | Jul 31 08:20:54 PM PDT 24 |
| Finished | Jul 31 08:29:13 PM PDT 24 |
| Peak memory | 616120 kb |
| Host | smart-55edf986-49ca-43fd-ae7b-4818d6b073f0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=820911172 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.820911172 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.36024989 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 7715807728 ps |
| CPU time | 550.4 seconds |
| Started | Jul 31 08:21:12 PM PDT 24 |
| Finished | Jul 31 08:30:23 PM PDT 24 |
| Peak memory | 610816 kb |
| Host | smart-afe30e48-5f45-4aa1-8bec-8f0fcc89483b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36024989 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_pwrmgr_full_aon_reset.36024989 |
| Directory | /workspace/1.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.221726364 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 3507089928 ps |
| CPU time | 378.61 seconds |
| Started | Jul 31 08:23:54 PM PDT 24 |
| Finished | Jul 31 08:30:13 PM PDT 24 |
| Peak memory | 609620 kb |
| Host | smart-5d2f4bde-fa76-4a89-9b8d-61cc386380e5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221726364 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_lowpower_cancel.221726364 |
| Directory | /workspace/1.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.3438432020 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 5182400471 ps |
| CPU time | 468.8 seconds |
| Started | Jul 31 08:19:59 PM PDT 24 |
| Finished | Jul 31 08:27:48 PM PDT 24 |
| Peak memory | 617636 kb |
| Host | smart-de5ba46c-2e90-4738-b91f-d5f46b2b80fc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3438432020 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.3438432020 |
| Directory | /workspace/1.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.679305587 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 11364363666 ps |
| CPU time | 1508.49 seconds |
| Started | Jul 31 08:20:28 PM PDT 24 |
| Finished | Jul 31 08:45:37 PM PDT 24 |
| Peak memory | 611256 kb |
| Host | smart-6e109e36-4e37-4dcb-b2cd-548ce11b4e59 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679305587 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.679305587 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2183321780 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 7922053828 ps |
| CPU time | 545.24 seconds |
| Started | Jul 31 08:26:33 PM PDT 24 |
| Finished | Jul 31 08:35:38 PM PDT 24 |
| Peak memory | 610700 kb |
| Host | smart-a63567b8-d717-4500-bdd5-eff21ebf437a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183321780 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2183321780 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.632520337 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 7241560056 ps |
| CPU time | 567.31 seconds |
| Started | Jul 31 08:20:28 PM PDT 24 |
| Finished | Jul 31 08:29:56 PM PDT 24 |
| Peak memory | 610908 kb |
| Host | smart-aee1fca1-0596-4a28-a539-d18ce8d5f310 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632520337 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.632520337 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1462741057 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 21917766822 ps |
| CPU time | 2000.77 seconds |
| Started | Jul 31 08:20:48 PM PDT 24 |
| Finished | Jul 31 08:54:09 PM PDT 24 |
| Peak memory | 611588 kb |
| Host | smart-ca088420-cbcd-45b7-82ae-48d53602f2b0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1462741057 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1462741057 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2059432169 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 22894810440 ps |
| CPU time | 1164.8 seconds |
| Started | Jul 31 08:25:24 PM PDT 24 |
| Finished | Jul 31 08:44:49 PM PDT 24 |
| Peak memory | 610876 kb |
| Host | smart-c21f0166-6355-4f7b-ad25-f98499094683 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2059432169 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2059432169 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.806369015 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 39166693768 ps |
| CPU time | 3211.17 seconds |
| Started | Jul 31 08:21:51 PM PDT 24 |
| Finished | Jul 31 09:15:22 PM PDT 24 |
| Peak memory | 611632 kb |
| Host | smart-a4f26769-5e4e-4c5d-bf12-dfd7f01d86eb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806369015 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glitc h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sl eep_power_glitch_reset.806369015 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2895905793 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 6103873068 ps |
| CPU time | 538.36 seconds |
| Started | Jul 31 08:25:36 PM PDT 24 |
| Finished | Jul 31 08:34:35 PM PDT 24 |
| Peak memory | 611196 kb |
| Host | smart-2d78058e-7691-4581-90ce-985168aec7c4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2895905793 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.2895905793 |
| Directory | /workspace/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.2102228607 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 3461672460 ps |
| CPU time | 242.08 seconds |
| Started | Jul 31 08:19:24 PM PDT 24 |
| Finished | Jul 31 08:23:27 PM PDT 24 |
| Peak memory | 609240 kb |
| Host | smart-5e57fd6c-62db-470e-b060-1cf76a5e8704 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102228607 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_disabled.2102228607 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.3156331868 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 4803475615 ps |
| CPU time | 450.67 seconds |
| Started | Jul 31 08:20:20 PM PDT 24 |
| Finished | Jul 31 08:27:51 PM PDT 24 |
| Peak memory | 617236 kb |
| Host | smart-22ed0d8f-7a89-49f4-b528-94ed3719eaf3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3156331868 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_power_glitch_reset.3156331868 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.286435145 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 5916013560 ps |
| CPU time | 420.68 seconds |
| Started | Jul 31 08:25:02 PM PDT 24 |
| Finished | Jul 31 08:32:03 PM PDT 24 |
| Peak memory | 608668 kb |
| Host | smart-2ae7fb99-9fcc-48ba-bd07-716a241d15e5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28643514 5 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.286435145 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.614458627 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 5893512606 ps |
| CPU time | 448.43 seconds |
| Started | Jul 31 08:25:49 PM PDT 24 |
| Finished | Jul 31 08:33:17 PM PDT 24 |
| Peak memory | 610776 kb |
| Host | smart-f40e2f0a-0ef7-4657-b4aa-da2559aea72d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=614458627 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.614458627 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.1282608273 |
| Short name | T1339 |
| Test name | |
| Test status | |
| Simulation time | 5471829168 ps |
| CPU time | 537.38 seconds |
| Started | Jul 31 08:27:10 PM PDT 24 |
| Finished | Jul 31 08:36:08 PM PDT 24 |
| Peak memory | 610452 kb |
| Host | smart-3e8e7c10-004b-4f1e-a9be-4498c8d71eaa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282608273 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.1282608273 |
| Directory | /workspace/1.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.1343829396 |
| Short name | T1342 |
| Test name | |
| Test status | |
| Simulation time | 8849245464 ps |
| CPU time | 1311.74 seconds |
| Started | Jul 31 08:19:12 PM PDT 24 |
| Finished | Jul 31 08:41:04 PM PDT 24 |
| Peak memory | 609896 kb |
| Host | smart-7976209d-0d94-477c-a98a-96c8bda3409f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343829396 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.1343829396 |
| Directory | /workspace/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.3606372817 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 5426740118 ps |
| CPU time | 475.52 seconds |
| Started | Jul 31 08:20:46 PM PDT 24 |
| Finished | Jul 31 08:28:42 PM PDT 24 |
| Peak memory | 610484 kb |
| Host | smart-48115782-d557-41f9-a159-604bf5a715f7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606372817 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.3606372817 |
| Directory | /workspace/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.3784589850 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 5373612904 ps |
| CPU time | 436.42 seconds |
| Started | Jul 31 08:26:26 PM PDT 24 |
| Finished | Jul 31 08:33:43 PM PDT 24 |
| Peak memory | 610360 kb |
| Host | smart-6194e31d-b4ca-41dd-980d-921bb452fef9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784589850 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usbdev_smoketest.3784589850 |
| Directory | /workspace/1.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1158107527 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 4303413994 ps |
| CPU time | 565.34 seconds |
| Started | Jul 31 08:22:03 PM PDT 24 |
| Finished | Jul 31 08:31:29 PM PDT 24 |
| Peak memory | 610228 kb |
| Host | smart-18d16078-eaad-448e-8e0a-b98ec7d0266e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115 8107527 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.1158107527 |
| Directory | /workspace/1.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.4011157118 |
| Short name | T1377 |
| Test name | |
| Test status | |
| Simulation time | 8943545668 ps |
| CPU time | 660.73 seconds |
| Started | Jul 31 08:23:40 PM PDT 24 |
| Finished | Jul 31 08:34:41 PM PDT 24 |
| Peak memory | 624768 kb |
| Host | smart-0804afb8-dfb9-405d-afdd-a68207894dab |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011157118 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.4011157118 |
| Directory | /workspace/1.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.631633783 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 5345688800 ps |
| CPU time | 608.84 seconds |
| Started | Jul 31 08:20:55 PM PDT 24 |
| Finished | Jul 31 08:31:04 PM PDT 24 |
| Peak memory | 610476 kb |
| Host | smart-1a173e0e-027c-4d11-b411-71f738522be4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631633783 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_rstmgr_cpu_info.631633783 |
| Directory | /workspace/1.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.3886416899 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 5768531292 ps |
| CPU time | 858.44 seconds |
| Started | Jul 31 08:21:07 PM PDT 24 |
| Finished | Jul 31 08:35:27 PM PDT 24 |
| Peak memory | 641744 kb |
| Host | smart-f15606f5-5244-4568-b546-7cea276b075b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3886416899 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.3886416899 |
| Directory | /workspace/1.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.2627807537 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 2137186054 ps |
| CPU time | 189.62 seconds |
| Started | Jul 31 08:26:42 PM PDT 24 |
| Finished | Jul 31 08:29:52 PM PDT 24 |
| Peak memory | 609600 kb |
| Host | smart-c897b6af-fd0c-4994-b43d-be85853a00dc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627807537 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_rstmgr_smoketest.2627807537 |
| Directory | /workspace/1.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.695276411 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 5191232000 ps |
| CPU time | 416.32 seconds |
| Started | Jul 31 08:20:09 PM PDT 24 |
| Finished | Jul 31 08:27:05 PM PDT 24 |
| Peak memory | 610420 kb |
| Host | smart-5a7d0c6b-d593-4b26-8ea5-67e9021c9afd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695276411 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rstmgr_sw_req.695276411 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.1844515613 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 3067841996 ps |
| CPU time | 257.51 seconds |
| Started | Jul 31 08:21:18 PM PDT 24 |
| Finished | Jul 31 08:25:36 PM PDT 24 |
| Peak memory | 609672 kb |
| Host | smart-ad5440cf-7ed8-47c3-a46d-4e25048c37a3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844515613 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_sw_rst.1844515613 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1806880609 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 2194407112 ps |
| CPU time | 210.23 seconds |
| Started | Jul 31 08:26:07 PM PDT 24 |
| Finished | Jul 31 08:29:37 PM PDT 24 |
| Peak memory | 609808 kb |
| Host | smart-5832e670-b93b-43ab-ba91-77333f9be0ff |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1806880609 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.1806880609 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.3605496226 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 3613387391 ps |
| CPU time | 340.71 seconds |
| Started | Jul 31 08:25:48 PM PDT 24 |
| Finished | Jul 31 08:31:30 PM PDT 24 |
| Peak memory | 609008 kb |
| Host | smart-4a52bcbd-cbf8-408b-997f-8f16f7104448 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605496226 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.3605496226 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.1545971089 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 2934547052 ps |
| CPU time | 328.88 seconds |
| Started | Jul 31 08:26:23 PM PDT 24 |
| Finished | Jul 31 08:31:52 PM PDT 24 |
| Peak memory | 617624 kb |
| Host | smart-aacf44a2-9525-424b-b615-f1922976e41a |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545971089 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_lockstep_glitch.1545971089 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2978843404 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 4608114560 ps |
| CPU time | 834.94 seconds |
| Started | Jul 31 08:21:42 PM PDT 24 |
| Finished | Jul 31 08:35:38 PM PDT 24 |
| Peak memory | 608888 kb |
| Host | smart-2a4e79b5-12b5-45ea-ba96-686be642f9a8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29788 43404 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.2978843404 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.376577433 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 5036954692 ps |
| CPU time | 1005.99 seconds |
| Started | Jul 31 08:21:01 PM PDT 24 |
| Finished | Jul 31 08:37:48 PM PDT 24 |
| Peak memory | 610152 kb |
| Host | smart-87a9c3c0-726a-4419-8261-2a04733e0362 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=376577433 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.376577433 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.2750264762 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 5722251488 ps |
| CPU time | 625.31 seconds |
| Started | Jul 31 08:25:36 PM PDT 24 |
| Finished | Jul 31 08:36:01 PM PDT 24 |
| Peak memory | 621220 kb |
| Host | smart-4ad66e10-5feb-4d3c-b7e0-b600ed2faf89 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750264762 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_wakeup.2750264762 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3170335470 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 4762823720 ps |
| CPU time | 633.29 seconds |
| Started | Jul 31 08:24:34 PM PDT 24 |
| Finished | Jul 31 08:35:08 PM PDT 24 |
| Peak memory | 621364 kb |
| Host | smart-96432895-472e-47b6-8923-6b9eaa8c3117 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317033 5470 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3170335470 |
| Directory | /workspace/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.1674352295 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 2906972600 ps |
| CPU time | 278.85 seconds |
| Started | Jul 31 08:26:52 PM PDT 24 |
| Finished | Jul 31 08:31:31 PM PDT 24 |
| Peak memory | 608528 kb |
| Host | smart-9e38e013-3113-45d7-807c-c60805f003c5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674352295 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rv_plic_smoketest.1674352295 |
| Directory | /workspace/1.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_irq.3205081371 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 3208970336 ps |
| CPU time | 303.65 seconds |
| Started | Jul 31 08:20:32 PM PDT 24 |
| Finished | Jul 31 08:25:36 PM PDT 24 |
| Peak memory | 609604 kb |
| Host | smart-e2dc18e9-5015-49b1-8a66-bc77b568504d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205081371 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_irq.3205081371 |
| Directory | /workspace/1.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.15056808 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 2533207000 ps |
| CPU time | 262.59 seconds |
| Started | Jul 31 08:27:20 PM PDT 24 |
| Finished | Jul 31 08:31:43 PM PDT 24 |
| Peak memory | 608360 kb |
| Host | smart-950fe88c-e160-4350-b9c7-0e452fc313c9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15056808 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_rv_timer_smoketest.15056808 |
| Directory | /workspace/1.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.2433116832 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 2786527122 ps |
| CPU time | 225 seconds |
| Started | Jul 31 08:25:56 PM PDT 24 |
| Finished | Jul 31 08:29:41 PM PDT 24 |
| Peak memory | 609400 kb |
| Host | smart-5e5b1689-4241-4f59-9466-da21069c9c35 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433116 832 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.2433116832 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_retention.532607692 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 3888594510 ps |
| CPU time | 262.18 seconds |
| Started | Jul 31 08:18:19 PM PDT 24 |
| Finished | Jul 31 08:22:42 PM PDT 24 |
| Peak memory | 608912 kb |
| Host | smart-af3cbcb6-2c4b-46b3-b476-806d1a2918af |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532607692 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_retention.532607692 |
| Directory | /workspace/1.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.668122249 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 8723951250 ps |
| CPU time | 1181.07 seconds |
| Started | Jul 31 08:16:38 PM PDT 24 |
| Finished | Jul 31 08:36:19 PM PDT 24 |
| Peak memory | 610484 kb |
| Host | smart-53868d89-8314-413f-a9c0-092c78eb53a4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668122249 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_sleep_pwm_pulses.668122249 |
| Directory | /workspace/1.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.203982360 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 7416267634 ps |
| CPU time | 913.18 seconds |
| Started | Jul 31 08:23:04 PM PDT 24 |
| Finished | Jul 31 08:38:18 PM PDT 24 |
| Peak memory | 610668 kb |
| Host | smart-273781ff-ab73-4e0d-868d-e7846dbd50ff |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203982360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sle ep_sram_ret_contents_no_scramble.203982360 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.2222567339 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 7854066020 ps |
| CPU time | 716.58 seconds |
| Started | Jul 31 08:25:47 PM PDT 24 |
| Finished | Jul 31 08:37:43 PM PDT 24 |
| Peak memory | 610312 kb |
| Host | smart-c56b4c7e-ee13-4b81-bed6-731976ef37a4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222567339 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep _sram_ret_contents_scramble.2222567339 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through.2547867127 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 6912613981 ps |
| CPU time | 890.85 seconds |
| Started | Jul 31 08:18:34 PM PDT 24 |
| Finished | Jul 31 08:33:25 PM PDT 24 |
| Peak memory | 624932 kb |
| Host | smart-33ce0025-d9ef-4591-9082-c173bcdf4c03 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547867127 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through.2547867127 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.2417185821 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 4454877761 ps |
| CPU time | 373.84 seconds |
| Started | Jul 31 08:17:01 PM PDT 24 |
| Finished | Jul 31 08:23:15 PM PDT 24 |
| Peak memory | 624360 kb |
| Host | smart-6024b6ff-b813-402e-b5ab-039409a2dfde |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417185821 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.2417185821 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.3730860108 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 3562843550 ps |
| CPU time | 265.78 seconds |
| Started | Jul 31 08:19:06 PM PDT 24 |
| Finished | Jul 31 08:23:32 PM PDT 24 |
| Peak memory | 617848 kb |
| Host | smart-d81768d0-c848-4a2c-a019-4ea5040e3ea7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730860108 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pinmux_sleep_retention.3730860108 |
| Directory | /workspace/1.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_tpm.4088147024 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 3748308814 ps |
| CPU time | 393.96 seconds |
| Started | Jul 31 08:20:23 PM PDT 24 |
| Finished | Jul 31 08:26:58 PM PDT 24 |
| Peak memory | 619596 kb |
| Host | smart-a1808961-c4eb-4180-aa7b-5ab9a2dc0fd9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088147024 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_tpm.4088147024 |
| Directory | /workspace/1.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.1321494918 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 2918681640 ps |
| CPU time | 269.46 seconds |
| Started | Jul 31 08:19:45 PM PDT 24 |
| Finished | Jul 31 08:24:14 PM PDT 24 |
| Peak memory | 608964 kb |
| Host | smart-da62ca91-1cfd-49b3-a427-935d23b62465 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321494918 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_spi_host_tx_rx.1321494918 |
| Directory | /workspace/1.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.990345216 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 5269759500 ps |
| CPU time | 618.61 seconds |
| Started | Jul 31 08:23:45 PM PDT 24 |
| Finished | Jul 31 08:34:04 PM PDT 24 |
| Peak memory | 611320 kb |
| Host | smart-1981a4d5-bd8a-4487-9d04-157890d99158 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990345216 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl _scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ sram_ctrl_scrambled_access.990345216 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.3594567242 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 5075232026 ps |
| CPU time | 557.01 seconds |
| Started | Jul 31 08:24:37 PM PDT 24 |
| Finished | Jul 31 08:33:55 PM PDT 24 |
| Peak memory | 609964 kb |
| Host | smart-3bb0198d-fdec-4573-a270-89a259e51619 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594567242 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.chip_sw_sram_ctrl_scrambled_access_jitter_en.3594567242 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2816234839 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 5293898360 ps |
| CPU time | 601.69 seconds |
| Started | Jul 31 08:26:38 PM PDT 24 |
| Finished | Jul 31 08:36:41 PM PDT 24 |
| Peak memory | 611120 kb |
| Host | smart-d9c9a13a-3f82-49e7-805a-99c60ee4287c |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816234839 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2816234839 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.757492433 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 3099592978 ps |
| CPU time | 192.46 seconds |
| Started | Jul 31 08:27:45 PM PDT 24 |
| Finished | Jul 31 08:30:58 PM PDT 24 |
| Peak memory | 608532 kb |
| Host | smart-fd614433-4974-4132-a2e0-8dc669b2a28c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757492433 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_sram_ctrl_smoketest.757492433 |
| Directory | /workspace/1.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.1645854641 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 20800714506 ps |
| CPU time | 3283.16 seconds |
| Started | Jul 31 08:22:22 PM PDT 24 |
| Finished | Jul 31 09:17:06 PM PDT 24 |
| Peak memory | 610784 kb |
| Host | smart-92889d05-4c8d-401e-b6b7-a06b892c40ce |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645854641 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.1645854641 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1680356148 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 5290691791 ps |
| CPU time | 738.38 seconds |
| Started | Jul 31 08:21:40 PM PDT 24 |
| Finished | Jul 31 08:34:00 PM PDT 24 |
| Peak memory | 613628 kb |
| Host | smart-1a679651-85c8-41e1-8673-ae8674018cca |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680356148 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_in_irq.1680356148 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.2745342408 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 3670895039 ps |
| CPU time | 348.75 seconds |
| Started | Jul 31 08:21:02 PM PDT 24 |
| Finished | Jul 31 08:26:52 PM PDT 24 |
| Peak memory | 613092 kb |
| Host | smart-8179f35f-9e80-4717-9eff-ffb88dff2aa2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745342408 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_inputs.2745342408 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.2171638971 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 3567843140 ps |
| CPU time | 386.13 seconds |
| Started | Jul 31 08:21:17 PM PDT 24 |
| Finished | Jul 31 08:27:44 PM PDT 24 |
| Peak memory | 610196 kb |
| Host | smart-bcb53dec-9257-4875-92fb-229c1a1472c1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171638971 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_outputs.2171638971 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.768916934 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 22612363610 ps |
| CPU time | 1821.1 seconds |
| Started | Jul 31 08:22:28 PM PDT 24 |
| Finished | Jul 31 08:52:50 PM PDT 24 |
| Peak memory | 614848 kb |
| Host | smart-96489c81-08cb-4fa9-bd64-1f94867bd1bc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76891693 4 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.768916934 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3387372439 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 6299818426 ps |
| CPU time | 513.51 seconds |
| Started | Jul 31 08:20:48 PM PDT 24 |
| Finished | Jul 31 08:29:22 PM PDT 24 |
| Peak memory | 610512 kb |
| Host | smart-d64d33b0-dc86-47d6-90b8-3bfd534f5997 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387372439 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3387372439 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_smoketest.3130658641 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 2557507668 ps |
| CPU time | 291.97 seconds |
| Started | Jul 31 08:27:38 PM PDT 24 |
| Finished | Jul 31 08:32:31 PM PDT 24 |
| Peak memory | 615128 kb |
| Host | smart-4514550f-77b1-43e2-bf9c-cd2e3a0e9018 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130658641 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_uart_smoketest.3130658641 |
| Directory | /workspace/1.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx.3405228041 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 4238630128 ps |
| CPU time | 762.52 seconds |
| Started | Jul 31 08:22:30 PM PDT 24 |
| Finished | Jul 31 08:35:13 PM PDT 24 |
| Peak memory | 623896 kb |
| Host | smart-6b470299-5c2e-46f0-ae77-6f132ad2d2fb |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405228041 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.3405228041 |
| Directory | /workspace/1.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.3774117214 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 8005428727 ps |
| CPU time | 1820.89 seconds |
| Started | Jul 31 08:17:10 PM PDT 24 |
| Finished | Jul 31 08:47:32 PM PDT 24 |
| Peak memory | 624524 kb |
| Host | smart-6c86703c-9253-4b3c-8390-a023a191f75d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774117214 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq.3774117214 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4025365148 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 8623127287 ps |
| CPU time | 1200.64 seconds |
| Started | Jul 31 08:22:02 PM PDT 24 |
| Finished | Jul 31 08:42:03 PM PDT 24 |
| Peak memory | 619716 kb |
| Host | smart-d85d2c16-e3fa-4496-81d0-8558ea50ff31 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025365148 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.4025365148 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.3739964891 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 77583256200 ps |
| CPU time | 14101.2 seconds |
| Started | Jul 31 08:22:36 PM PDT 24 |
| Finished | Aug 01 12:17:39 AM PDT 24 |
| Peak memory | 636064 kb |
| Host | smart-c380c1c4-c3a4-4c29-9bd7-1cd6eed8f89e |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3739964891 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.3739964891 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.3341168245 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 4399367652 ps |
| CPU time | 764.16 seconds |
| Started | Jul 31 08:18:02 PM PDT 24 |
| Finished | Jul 31 08:30:46 PM PDT 24 |
| Peak memory | 623972 kb |
| Host | smart-3184a097-04f9-4978-9a71-2cd059604fe1 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341168245 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.3341168245 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.2460346482 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 4584135798 ps |
| CPU time | 625.98 seconds |
| Started | Jul 31 08:19:20 PM PDT 24 |
| Finished | Jul 31 08:29:46 PM PDT 24 |
| Peak memory | 623976 kb |
| Host | smart-01856ed0-6413-4622-b9db-07ab71f122d9 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460346482 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.2460346482 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.1868165743 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4470003800 ps |
| CPU time | 620.05 seconds |
| Started | Jul 31 08:17:13 PM PDT 24 |
| Finished | Jul 31 08:27:33 PM PDT 24 |
| Peak memory | 623996 kb |
| Host | smart-df21ed1d-66db-4fdd-b660-d86f44b19014 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868165743 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.1868165743 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_prod.3355818715 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 12675459751 ps |
| CPU time | 1405.76 seconds |
| Started | Jul 31 08:24:13 PM PDT 24 |
| Finished | Jul 31 08:47:39 PM PDT 24 |
| Peak memory | 624480 kb |
| Host | smart-23ede858-60a7-4464-9010-654e0b382698 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355818715 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.3355818715 |
| Directory | /workspace/1.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_rma.13816774 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 3387679734 ps |
| CPU time | 328.57 seconds |
| Started | Jul 31 08:24:34 PM PDT 24 |
| Finished | Jul 31 08:30:03 PM PDT 24 |
| Peak memory | 624664 kb |
| Host | smart-95d7899b-54f1-4dde-8e93-8f2753057608 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13816774 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_rma.13816774 |
| Directory | /workspace/1.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_dev.4204057056 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 15602563234 ps |
| CPU time | 3808.61 seconds |
| Started | Jul 31 08:32:49 PM PDT 24 |
| Finished | Jul 31 09:36:18 PM PDT 24 |
| Peak memory | 610056 kb |
| Host | smart-339fe5d1-687e-46b4-baf3-853ab543554c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204057056 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_dev.4204057056 |
| Directory | /workspace/1.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod.1269269235 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 15390339304 ps |
| CPU time | 4187.05 seconds |
| Started | Jul 31 08:31:09 PM PDT 24 |
| Finished | Jul 31 09:40:57 PM PDT 24 |
| Peak memory | 610300 kb |
| Host | smart-e4cacab3-2b47-490a-ad75-1f483340bf88 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269269235 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_prod.1269269235 |
| Directory | /workspace/1.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.3071719500 |
| Short name | T1322 |
| Test name | |
| Test status | |
| Simulation time | 15574915166 ps |
| CPU time | 3394.11 seconds |
| Started | Jul 31 08:38:33 PM PDT 24 |
| Finished | Jul 31 09:35:07 PM PDT 24 |
| Peak memory | 609844 kb |
| Host | smart-9bff8de0-5f47-4577-968f-754cb86076db |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071719500 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.rom_e2e_asm_init_prod_end.3071719500 |
| Directory | /workspace/1.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_rma.1120610084 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 14678539382 ps |
| CPU time | 3264.17 seconds |
| Started | Jul 31 08:36:40 PM PDT 24 |
| Finished | Jul 31 09:31:05 PM PDT 24 |
| Peak memory | 609596 kb |
| Host | smart-d3108951-4dc0-4233-aaed-5d0edb27eff6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120610084 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_rma.1120610084 |
| Directory | /workspace/1.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.251786343 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 12266935900 ps |
| CPU time | 2642.12 seconds |
| Started | Jul 31 08:31:16 PM PDT 24 |
| Finished | Jul 31 09:15:19 PM PDT 24 |
| Peak memory | 610392 kb |
| Host | smart-433c8733-01ad-416f-a9a6-cf12087a3888 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251786343 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.rom_e2e_asm_init_test_unlocked0.251786343 |
| Directory | /workspace/1.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.1729258121 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 14906172408 ps |
| CPU time | 3708.9 seconds |
| Started | Jul 31 08:33:40 PM PDT 24 |
| Finished | Jul 31 09:35:29 PM PDT 24 |
| Peak memory | 610100 kb |
| Host | smart-e19591b3-0508-481f-a1d5-30a2ca7aecc0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729258121 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_in it_rom_ext_invalid_meas.1729258121 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.173951024 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 14649269776 ps |
| CPU time | 3781.96 seconds |
| Started | Jul 31 08:31:51 PM PDT 24 |
| Finished | Jul 31 09:34:53 PM PDT 24 |
| Peak memory | 609924 kb |
| Host | smart-d79f7bab-5cbf-4832-9b26-de91b2932c26 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173951024 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_meas.173951024 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.1410602951 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 14813978314 ps |
| CPU time | 3187.85 seconds |
| Started | Jul 31 08:32:09 PM PDT 24 |
| Finished | Jul 31 09:25:17 PM PDT 24 |
| Peak memory | 610184 kb |
| Host | smart-10bf38da-60ad-4498-8d81-2ab5882fbf99 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410602951 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext _no_meas.1410602951 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_self_hash.1736406890 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 26198308276 ps |
| CPU time | 5761.39 seconds |
| Started | Jul 31 08:31:15 PM PDT 24 |
| Finished | Jul 31 10:07:17 PM PDT 24 |
| Peak memory | 610112 kb |
| Host | smart-a4d93c21-3f85-4cb9-9a52-95c05fd17a66 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736406890 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_self_hash.1736406890 |
| Directory | /workspace/1.rom_e2e_self_hash/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_output.242797102 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 26375628732 ps |
| CPU time | 3759.26 seconds |
| Started | Jul 31 08:31:27 PM PDT 24 |
| Finished | Jul 31 09:34:07 PM PDT 24 |
| Peak memory | 611480 kb |
| Host | smart-416c0c7f-367c-4b15-9252-b4e95d19b9a0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242797102 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_output.242797102 |
| Directory | /workspace/1.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_smoke.800308340 |
| Short name | T1347 |
| Test name | |
| Test status | |
| Simulation time | 15595962136 ps |
| CPU time | 3314.2 seconds |
| Started | Jul 31 08:39:02 PM PDT 24 |
| Finished | Jul 31 09:34:17 PM PDT 24 |
| Peak memory | 609840 kb |
| Host | smart-7d152206-bc3f-4c67-84cc-cc471c2ad72c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=800308340 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.800308340 |
| Directory | /workspace/1.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_static_critical.1869010529 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 17231593244 ps |
| CPU time | 4298.19 seconds |
| Started | Jul 31 08:33:32 PM PDT 24 |
| Finished | Jul 31 09:45:11 PM PDT 24 |
| Peak memory | 610136 kb |
| Host | smart-dea7ee9e-e6e8-49fc-b53c-91a40404e972 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869010529 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_static_critical.1869010529 |
| Directory | /workspace/1.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/1.rom_keymgr_functest.2177389790 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 4826292196 ps |
| CPU time | 466.52 seconds |
| Started | Jul 31 08:27:03 PM PDT 24 |
| Finished | Jul 31 08:34:50 PM PDT 24 |
| Peak memory | 609456 kb |
| Host | smart-595be413-02a0-4611-9fe0-18e72734cbc0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177389790 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.rom_keymgr_functest.2177389790 |
| Directory | /workspace/1.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/1.rom_raw_unlock.252402572 |
| Short name | T1348 |
| Test name | |
| Test status | |
| Simulation time | 6483432890 ps |
| CPU time | 239.84 seconds |
| Started | Jul 31 08:27:23 PM PDT 24 |
| Finished | Jul 31 08:31:23 PM PDT 24 |
| Peak memory | 619860 kb |
| Host | smart-e03651b9-65e5-458d-b088-eec35d5acabe |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=252402572 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_raw_unlock.252402572 |
| Directory | /workspace/1.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.rom_volatile_raw_unlock.1328642917 |
| Short name | T1369 |
| Test name | |
| Test status | |
| Simulation time | 2298798574 ps |
| CPU time | 148.41 seconds |
| Started | Jul 31 08:34:23 PM PDT 24 |
| Finished | Jul 31 08:36:53 PM PDT 24 |
| Peak memory | 617128 kb |
| Host | smart-168d94de-a4b7-4918-9b42-c4d58083db20 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328642917 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.1328642917 |
| Directory | /workspace/1.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/10.chip_sw_all_escalation_resets.4186683550 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 6346476968 ps |
| CPU time | 749.03 seconds |
| Started | Jul 31 08:40:53 PM PDT 24 |
| Finished | Jul 31 08:53:23 PM PDT 24 |
| Peak memory | 650136 kb |
| Host | smart-fcd2562e-f13f-4e0e-bb38-52fa0ee1ee75 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4186683550 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.4186683550 |
| Directory | /workspace/10.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.2263163368 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 9089864702 ps |
| CPU time | 902.64 seconds |
| Started | Jul 31 08:39:33 PM PDT 24 |
| Finished | Jul 31 08:54:36 PM PDT 24 |
| Peak memory | 620396 kb |
| Host | smart-9e8fcc13-1c1d-4820-b175-2837283820fe |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263163368 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 10.chip_sw_lc_ctrl_transition.2263163368 |
| Directory | /workspace/10.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.2743233544 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 13104903800 ps |
| CPU time | 2302.07 seconds |
| Started | Jul 31 08:39:10 PM PDT 24 |
| Finished | Jul 31 09:17:33 PM PDT 24 |
| Peak memory | 624484 kb |
| Host | smart-e9c691be-bd2e-4679-9c8d-699fd287062a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2743233544 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.2743233544 |
| Directory | /workspace/10.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.2199849553 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 6730494717 ps |
| CPU time | 669.59 seconds |
| Started | Jul 31 08:39:10 PM PDT 24 |
| Finished | Jul 31 08:50:20 PM PDT 24 |
| Peak memory | 621328 kb |
| Host | smart-aff10bbe-7fa3-4fef-a583-2a641b217763 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199849553 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 11.chip_sw_lc_ctrl_transition.2199849553 |
| Directory | /workspace/11.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.2237182307 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 12946961296 ps |
| CPU time | 2713.72 seconds |
| Started | Jul 31 08:45:35 PM PDT 24 |
| Finished | Jul 31 09:30:49 PM PDT 24 |
| Peak memory | 624548 kb |
| Host | smart-74e99dba-969a-49c1-a193-fd8e869be414 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2237182307 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.2237182307 |
| Directory | /workspace/11.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2255696754 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 3829027280 ps |
| CPU time | 358.41 seconds |
| Started | Jul 31 08:41:49 PM PDT 24 |
| Finished | Jul 31 08:47:47 PM PDT 24 |
| Peak memory | 649072 kb |
| Host | smart-0ab7ffb4-93b7-4839-94f5-bc01655aedec |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255696754 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2255696754 |
| Directory | /workspace/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/12.chip_sw_all_escalation_resets.912216124 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 5795470556 ps |
| CPU time | 614.73 seconds |
| Started | Jul 31 08:41:16 PM PDT 24 |
| Finished | Jul 31 08:51:31 PM PDT 24 |
| Peak memory | 650236 kb |
| Host | smart-8df410bf-b95e-43d2-95b6-8f32787b3f9c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 912216124 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.912216124 |
| Directory | /workspace/12.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.4038221335 |
| Short name | T1360 |
| Test name | |
| Test status | |
| Simulation time | 9694061221 ps |
| CPU time | 951.28 seconds |
| Started | Jul 31 08:40:49 PM PDT 24 |
| Finished | Jul 31 08:56:41 PM PDT 24 |
| Peak memory | 621224 kb |
| Host | smart-d66f9455-5115-4798-a778-c0378d49b843 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038221335 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 12.chip_sw_lc_ctrl_transition.4038221335 |
| Directory | /workspace/12.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.3808634508 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 4089518248 ps |
| CPU time | 501.84 seconds |
| Started | Jul 31 08:42:36 PM PDT 24 |
| Finished | Jul 31 08:50:58 PM PDT 24 |
| Peak memory | 624448 kb |
| Host | smart-2714f1a1-52bb-45bf-ba03-16e47fea665f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3808634508 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.3808634508 |
| Directory | /workspace/12.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/13.chip_sw_all_escalation_resets.3212308424 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 4387779080 ps |
| CPU time | 519.37 seconds |
| Started | Jul 31 08:42:14 PM PDT 24 |
| Finished | Jul 31 08:50:54 PM PDT 24 |
| Peak memory | 650300 kb |
| Host | smart-797cc183-b955-41db-960c-33d712c1c461 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3212308424 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.3212308424 |
| Directory | /workspace/13.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.952876417 |
| Short name | T1355 |
| Test name | |
| Test status | |
| Simulation time | 13567374996 ps |
| CPU time | 1036.3 seconds |
| Started | Jul 31 08:42:01 PM PDT 24 |
| Finished | Jul 31 08:59:18 PM PDT 24 |
| Peak memory | 620700 kb |
| Host | smart-aee92443-bd4c-4ffb-a8b4-8cbe2ec8c5da |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952876417 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 13.chip_sw_lc_ctrl_transition.952876417 |
| Directory | /workspace/13.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.447549680 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 12933032376 ps |
| CPU time | 2927.93 seconds |
| Started | Jul 31 08:43:16 PM PDT 24 |
| Finished | Jul 31 09:32:04 PM PDT 24 |
| Peak memory | 623220 kb |
| Host | smart-e6076efc-d7ad-46b2-917b-5706fd169c0d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=447549680 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.447549680 |
| Directory | /workspace/13.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.1412776777 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 10728650472 ps |
| CPU time | 717.86 seconds |
| Started | Jul 31 08:41:11 PM PDT 24 |
| Finished | Jul 31 08:53:09 PM PDT 24 |
| Peak memory | 620444 kb |
| Host | smart-12ede1cc-40f5-4983-b805-f5e62fceb50b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412776777 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 14.chip_sw_lc_ctrl_transition.1412776777 |
| Directory | /workspace/14.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.606476272 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 4600104676 ps |
| CPU time | 532.3 seconds |
| Started | Jul 31 08:41:38 PM PDT 24 |
| Finished | Jul 31 08:50:31 PM PDT 24 |
| Peak memory | 624408 kb |
| Host | smart-4128d15c-1203-4b56-8edd-68d710384cd7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=606476272 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.606476272 |
| Directory | /workspace/14.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.1751789822 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 8200451708 ps |
| CPU time | 1562.79 seconds |
| Started | Jul 31 08:41:37 PM PDT 24 |
| Finished | Jul 31 09:07:41 PM PDT 24 |
| Peak memory | 623148 kb |
| Host | smart-96f26482-29c4-4669-8adc-4212e01b06f2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1751789822 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.1751789822 |
| Directory | /workspace/15.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.3622026664 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 4108421656 ps |
| CPU time | 550.01 seconds |
| Started | Jul 31 08:42:04 PM PDT 24 |
| Finished | Jul 31 08:51:15 PM PDT 24 |
| Peak memory | 624444 kb |
| Host | smart-514abc55-cfb6-4be8-a63a-56a3aeb5e235 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3622026664 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.3622026664 |
| Directory | /workspace/16.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/17.chip_sw_all_escalation_resets.1333411069 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 4811061336 ps |
| CPU time | 824.66 seconds |
| Started | Jul 31 08:42:11 PM PDT 24 |
| Finished | Jul 31 08:55:56 PM PDT 24 |
| Peak memory | 650292 kb |
| Host | smart-4af4bd72-8aa5-46ba-aa6a-ff4908396660 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1333411069 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.1333411069 |
| Directory | /workspace/17.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.3670088881 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 4330458208 ps |
| CPU time | 590.77 seconds |
| Started | Jul 31 08:41:35 PM PDT 24 |
| Finished | Jul 31 08:51:26 PM PDT 24 |
| Peak memory | 624680 kb |
| Host | smart-7d9ba42b-832e-4b2a-b54e-59412c66898e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3670088881 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.3670088881 |
| Directory | /workspace/17.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3759806351 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 4062718720 ps |
| CPU time | 485.98 seconds |
| Started | Jul 31 08:41:36 PM PDT 24 |
| Finished | Jul 31 08:49:42 PM PDT 24 |
| Peak memory | 649328 kb |
| Host | smart-b78ea2c2-8dfc-4cac-a586-afee4a5e18cc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759806351 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3759806351 |
| Directory | /workspace/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.3155799639 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 7841449228 ps |
| CPU time | 1466.1 seconds |
| Started | Jul 31 08:41:24 PM PDT 24 |
| Finished | Jul 31 09:05:50 PM PDT 24 |
| Peak memory | 624408 kb |
| Host | smart-d97463c7-11d0-422f-bd43-5e449b5bd63b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3155799639 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.3155799639 |
| Directory | /workspace/18.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.323855789 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 3800369376 ps |
| CPU time | 511.33 seconds |
| Started | Jul 31 08:41:55 PM PDT 24 |
| Finished | Jul 31 08:50:27 PM PDT 24 |
| Peak memory | 624548 kb |
| Host | smart-86297d8d-db7b-4848-a66e-adc5781690b3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=323855789 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.323855789 |
| Directory | /workspace/19.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.4039014290 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 3509429360 ps |
| CPU time | 381.47 seconds |
| Started | Jul 31 08:34:16 PM PDT 24 |
| Finished | Jul 31 08:40:38 PM PDT 24 |
| Peak memory | 620140 kb |
| Host | smart-4d4cce97-219f-46fb-926a-d4d193331bfb |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4 039014290 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.4039014290 |
| Directory | /workspace/2.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sival_flash_info_access.1946568201 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 2670692544 ps |
| CPU time | 250.55 seconds |
| Started | Jul 31 08:26:37 PM PDT 24 |
| Finished | Jul 31 08:30:48 PM PDT 24 |
| Peak memory | 610040 kb |
| Host | smart-1f920607-4cb8-4efb-91e7-e2c9b7ec7e34 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1946568201 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.1946568201 |
| Directory | /workspace/2.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3809171939 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 18466373374 ps |
| CPU time | 506.02 seconds |
| Started | Jul 31 08:30:22 PM PDT 24 |
| Finished | Jul 31 08:38:48 PM PDT 24 |
| Peak memory | 619116 kb |
| Host | smart-30f5b67d-72ce-4f4a-8e21-728f46823519 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3809171939 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3809171939 |
| Directory | /workspace/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc.2022377837 |
| Short name | T1323 |
| Test name | |
| Test status | |
| Simulation time | 2956402552 ps |
| CPU time | 359.55 seconds |
| Started | Jul 31 08:34:11 PM PDT 24 |
| Finished | Jul 31 08:40:11 PM PDT 24 |
| Peak memory | 609604 kb |
| Host | smart-a10bea8d-acfe-4dea-ae2a-656a44e19d9e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022377837 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.2022377837 |
| Directory | /workspace/2.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.636547164 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 2676588592 ps |
| CPU time | 297.61 seconds |
| Started | Jul 31 08:32:48 PM PDT 24 |
| Finished | Jul 31 08:37:53 PM PDT 24 |
| Peak memory | 608440 kb |
| Host | smart-8b56142a-74d9-4c0f-bff0-fa8644ece1cf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6365 47164 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.636547164 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3615138785 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 3231399994 ps |
| CPU time | 260.92 seconds |
| Started | Jul 31 08:33:53 PM PDT 24 |
| Finished | Jul 31 08:38:15 PM PDT 24 |
| Peak memory | 608444 kb |
| Host | smart-31ca0db6-960d-42a6-aab5-8a14564044ad |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615138785 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.3615138785 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_entropy.3231004124 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 3626790666 ps |
| CPU time | 283.3 seconds |
| Started | Jul 31 08:32:22 PM PDT 24 |
| Finished | Jul 31 08:37:06 PM PDT 24 |
| Peak memory | 609488 kb |
| Host | smart-9ebd2c64-bd36-45f5-b2da-74f986b42486 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231004124 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_entropy.3231004124 |
| Directory | /workspace/2.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_idle.3877609533 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 2854339714 ps |
| CPU time | 213.75 seconds |
| Started | Jul 31 08:32:02 PM PDT 24 |
| Finished | Jul 31 08:35:36 PM PDT 24 |
| Peak memory | 609596 kb |
| Host | smart-03b9e296-833a-46fa-98a7-b18325f07017 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877609533 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.3877609533 |
| Directory | /workspace/2.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_masking_off.1458709228 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 2432068036 ps |
| CPU time | 258.91 seconds |
| Started | Jul 31 08:32:03 PM PDT 24 |
| Finished | Jul 31 08:36:22 PM PDT 24 |
| Peak memory | 609396 kb |
| Host | smart-26a883d2-75c1-4a88-9240-bbb07e90a3e3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458709228 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_masking_off.1458709228 |
| Directory | /workspace/2.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_smoketest.3546399588 |
| Short name | T1315 |
| Test name | |
| Test status | |
| Simulation time | 2358618776 ps |
| CPU time | 303.5 seconds |
| Started | Jul 31 08:34:53 PM PDT 24 |
| Finished | Jul 31 08:39:58 PM PDT 24 |
| Peak memory | 609612 kb |
| Host | smart-dc26960a-78a7-455a-bf26-b020ce0d0f10 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546399588 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_smoketest.3546399588 |
| Directory | /workspace/2.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_entropy.3653325495 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 3777182011 ps |
| CPU time | 263.29 seconds |
| Started | Jul 31 08:31:43 PM PDT 24 |
| Finished | Jul 31 08:36:07 PM PDT 24 |
| Peak memory | 609428 kb |
| Host | smart-764fbde5-9319-4a4b-ba50-7055fe82302b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3653325495 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.3653325495 |
| Directory | /workspace/2.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_escalation.3427336211 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 4850521878 ps |
| CPU time | 493.25 seconds |
| Started | Jul 31 08:31:06 PM PDT 24 |
| Finished | Jul 31 08:39:19 PM PDT 24 |
| Peak memory | 619404 kb |
| Host | smart-45e58308-a38c-42e7-ba29-a722d2dcac9e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=3427336211 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.3427336211 |
| Directory | /workspace/2.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.1169178261 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 7002571208 ps |
| CPU time | 1351.76 seconds |
| Started | Jul 31 08:32:20 PM PDT 24 |
| Finished | Jul 31 08:54:53 PM PDT 24 |
| Peak memory | 610296 kb |
| Host | smart-d1db836a-e780-445d-af21-0b48fd7f105f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1169178261 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.1169178261 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.2109804993 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 9317670296 ps |
| CPU time | 1781.66 seconds |
| Started | Jul 31 08:32:06 PM PDT 24 |
| Finished | Jul 31 09:01:48 PM PDT 24 |
| Peak memory | 610140 kb |
| Host | smart-bb6b41f4-8a4d-4a14-8ee8-cf228e6958c3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109804993 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_togg le.2109804993 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2816047586 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 12660688616 ps |
| CPU time | 1585.25 seconds |
| Started | Jul 31 08:33:32 PM PDT 24 |
| Finished | Jul 31 08:59:57 PM PDT 24 |
| Peak memory | 611040 kb |
| Host | smart-b825c49f-b8fc-44fc-91eb-92ad4fdc138c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816047586 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_sleep_mode_pings.2816047586 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.2803868552 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 8627981250 ps |
| CPU time | 1757.25 seconds |
| Started | Jul 31 08:32:24 PM PDT 24 |
| Finished | Jul 31 09:01:42 PM PDT 24 |
| Peak memory | 610116 kb |
| Host | smart-a439776f-ad29-4bb1-9015-c2f52cecb059 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2803868552 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_ok.2803868552 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.228825101 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 3568302548 ps |
| CPU time | 295.19 seconds |
| Started | Jul 31 08:31:20 PM PDT 24 |
| Finished | Jul 31 08:36:15 PM PDT 24 |
| Peak memory | 609916 kb |
| Host | smart-5d0a10a5-3bc5-4d70-9519-500d88ca85e5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=228825101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.228825101 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3528077914 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 255332411774 ps |
| CPU time | 12599.2 seconds |
| Started | Jul 31 08:32:12 PM PDT 24 |
| Finished | Aug 01 12:02:13 AM PDT 24 |
| Peak memory | 610876 kb |
| Host | smart-7693cd1e-3206-4ba0-a2e3-d033ad28b87f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3528077914 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3528077914 |
| Directory | /workspace/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_test.4110780505 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 3550023696 ps |
| CPU time | 332.06 seconds |
| Started | Jul 31 08:33:15 PM PDT 24 |
| Finished | Jul 31 08:38:48 PM PDT 24 |
| Peak memory | 609944 kb |
| Host | smart-efdc0099-219e-4431-8adb-730444d90732 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110780505 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_alert_test.4110780505 |
| Directory | /workspace/2.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_all_escalation_resets.1579985861 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 4696787296 ps |
| CPU time | 636.95 seconds |
| Started | Jul 31 08:29:09 PM PDT 24 |
| Finished | Jul 31 08:39:46 PM PDT 24 |
| Peak memory | 650364 kb |
| Host | smart-5bfd2f94-0288-44f0-be1e-3626eec2aa4f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1579985861 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.1579985861 |
| Directory | /workspace/2.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_irq.1725336630 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 3919967572 ps |
| CPU time | 520.24 seconds |
| Started | Jul 31 08:31:08 PM PDT 24 |
| Finished | Jul 31 08:39:49 PM PDT 24 |
| Peak memory | 609752 kb |
| Host | smart-49563bb0-627c-431a-a54a-2ac67222dd10 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725336630 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.1725336630 |
| Directory | /workspace/2.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.4252461419 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 6775400000 ps |
| CPU time | 322.9 seconds |
| Started | Jul 31 08:31:44 PM PDT 24 |
| Finished | Jul 31 08:37:07 PM PDT 24 |
| Peak memory | 610560 kb |
| Host | smart-e36a3fa5-0b4f-4403-b8cb-c65f6858bb01 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4252461419 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.4252461419 |
| Directory | /workspace/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.3719157068 |
| Short name | T1319 |
| Test name | |
| Test status | |
| Simulation time | 2867102572 ps |
| CPU time | 256.42 seconds |
| Started | Jul 31 08:38:02 PM PDT 24 |
| Finished | Jul 31 08:42:19 PM PDT 24 |
| Peak memory | 609712 kb |
| Host | smart-d69e6250-9ba4-4659-9278-eb0475acd8fa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719157068 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_aon_timer_smoketest.3719157068 |
| Directory | /workspace/2.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.1212553968 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 6481951768 ps |
| CPU time | 698.64 seconds |
| Started | Jul 31 08:33:37 PM PDT 24 |
| Finished | Jul 31 08:45:16 PM PDT 24 |
| Peak memory | 610196 kb |
| Host | smart-d3eaea7c-8ca6-488e-abbe-79483303b067 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1212553968 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.1212553968 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.2478188693 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 4486057448 ps |
| CPU time | 517.14 seconds |
| Started | Jul 31 08:29:55 PM PDT 24 |
| Finished | Jul 31 08:38:32 PM PDT 24 |
| Peak memory | 610408 kb |
| Host | smart-6885c3fd-057b-47a9-8c5b-4a3d42cf4661 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2478188693 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.2478188693 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_outputs.3922591306 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 7519730468 ps |
| CPU time | 953.79 seconds |
| Started | Jul 31 08:34:15 PM PDT 24 |
| Finished | Jul 31 08:50:09 PM PDT 24 |
| Peak memory | 616980 kb |
| Host | smart-84837769-9f02-432d-a42d-8b71057918a4 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922591306 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.3922591306 |
| Directory | /workspace/2.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.4175898527 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 7356569490 ps |
| CPU time | 397.2 seconds |
| Started | Jul 31 08:32:40 PM PDT 24 |
| Finished | Jul 31 08:39:18 PM PDT 24 |
| Peak memory | 621276 kb |
| Host | smart-f39bbb69-de1a-4736-8456-b01f66f28283 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=4175898527 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.4175898527 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.324280965 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 3335834500 ps |
| CPU time | 719.4 seconds |
| Started | Jul 31 08:34:07 PM PDT 24 |
| Finished | Jul 31 08:46:06 PM PDT 24 |
| Peak memory | 612916 kb |
| Host | smart-047d2d09-3d9b-4e06-af3d-d0fde9f4828e |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324280965 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_cl kmgr_external_clk_src_for_sw_fast_dev.324280965 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1164556158 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 3663982416 ps |
| CPU time | 631.78 seconds |
| Started | Jul 31 08:35:50 PM PDT 24 |
| Finished | Jul 31 08:46:22 PM PDT 24 |
| Peak memory | 613148 kb |
| Host | smart-55e6c938-5fa7-47fc-8461-42ab2839b459 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164556158 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.1164556158 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2321973122 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 4350593832 ps |
| CPU time | 790.9 seconds |
| Started | Jul 31 08:32:25 PM PDT 24 |
| Finished | Jul 31 08:45:36 PM PDT 24 |
| Peak memory | 613144 kb |
| Host | smart-68720173-73df-4b8d-8b88-fa9efffd78d8 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321973122 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2321973122 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1497268010 |
| Short name | T1324 |
| Test name | |
| Test status | |
| Simulation time | 4596921350 ps |
| CPU time | 689.95 seconds |
| Started | Jul 31 08:33:28 PM PDT 24 |
| Finished | Jul 31 08:44:58 PM PDT 24 |
| Peak memory | 612904 kb |
| Host | smart-33227291-b01e-44f7-9565-057636ad2f35 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497268010 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.1497268010 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.6169965 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 4466901000 ps |
| CPU time | 594.35 seconds |
| Started | Jul 31 08:34:49 PM PDT 24 |
| Finished | Jul 31 08:44:44 PM PDT 24 |
| Peak memory | 613092 kb |
| Host | smart-bac54920-1bdb-4faa-9124-dc632a5914cc |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6169965 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkm gr_external_clk_src_for_sw_slow_rma.6169965 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.823022816 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 4827672552 ps |
| CPU time | 682.87 seconds |
| Started | Jul 31 08:33:25 PM PDT 24 |
| Finished | Jul 31 08:44:48 PM PDT 24 |
| Peak memory | 613232 kb |
| Host | smart-34b0958a-0639-4747-8957-719c01b2e7ed |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823022816 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2. chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.823022816 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter.3826871958 |
| Short name | T1371 |
| Test name | |
| Test status | |
| Simulation time | 3285432752 ps |
| CPU time | 184.53 seconds |
| Started | Jul 31 08:33:46 PM PDT 24 |
| Finished | Jul 31 08:36:51 PM PDT 24 |
| Peak memory | 609620 kb |
| Host | smart-5e43d558-fc3f-45a3-9b9e-82522c7f39fc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826871958 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_clkmgr_jitter.3826871958 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.247691781 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 3298462280 ps |
| CPU time | 461.12 seconds |
| Started | Jul 31 08:33:53 PM PDT 24 |
| Finished | Jul 31 08:41:34 PM PDT 24 |
| Peak memory | 609560 kb |
| Host | smart-fd0f1c99-f21d-4014-bd93-fa585685cd91 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247691781 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_frequency.247691781 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3725007336 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 2492727956 ps |
| CPU time | 183.22 seconds |
| Started | Jul 31 08:36:31 PM PDT 24 |
| Finished | Jul 31 08:39:35 PM PDT 24 |
| Peak memory | 609656 kb |
| Host | smart-bad25b0f-45f9-422c-9f85-b14d8d477169 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725007336 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.3725007336 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.1535629867 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 4214374692 ps |
| CPU time | 526.31 seconds |
| Started | Jul 31 08:34:10 PM PDT 24 |
| Finished | Jul 31 08:42:56 PM PDT 24 |
| Peak memory | 609780 kb |
| Host | smart-d30b9bdb-0100-46ad-8fa8-b3beacb3febe |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535629867 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.1535629867 |
| Directory | /workspace/2.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.2353997953 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 5327560952 ps |
| CPU time | 569.34 seconds |
| Started | Jul 31 08:32:36 PM PDT 24 |
| Finished | Jul 31 08:42:06 PM PDT 24 |
| Peak memory | 609304 kb |
| Host | smart-a63b0d34-87ed-4181-a760-ff8b61c91078 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353997953 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_hmac_trans.2353997953 |
| Directory | /workspace/2.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.934508866 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 4068899926 ps |
| CPU time | 522.05 seconds |
| Started | Jul 31 08:33:34 PM PDT 24 |
| Finished | Jul 31 08:42:17 PM PDT 24 |
| Peak memory | 610108 kb |
| Host | smart-dc4740fd-8434-4122-8b19-8ef478693e09 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934508866 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_kmac_trans.934508866 |
| Directory | /workspace/2.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3109930019 |
| Short name | T1365 |
| Test name | |
| Test status | |
| Simulation time | 4012395952 ps |
| CPU time | 452.48 seconds |
| Started | Jul 31 08:34:06 PM PDT 24 |
| Finished | Jul 31 08:41:39 PM PDT 24 |
| Peak memory | 610192 kb |
| Host | smart-ed4ea6fc-d74f-4a93-a93e-a4693f937619 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109930019 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_otbn_trans.3109930019 |
| Directory | /workspace/2.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.4189568309 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 8844724828 ps |
| CPU time | 1393.76 seconds |
| Started | Jul 31 08:32:37 PM PDT 24 |
| Finished | Jul 31 08:55:51 PM PDT 24 |
| Peak memory | 610260 kb |
| Host | smart-7b230cb9-5e21-4ec2-915e-919ab15c5d9a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189568309 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.4189568309 |
| Directory | /workspace/2.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.2813829237 |
| Short name | T1345 |
| Test name | |
| Test status | |
| Simulation time | 3980547252 ps |
| CPU time | 476.09 seconds |
| Started | Jul 31 08:33:49 PM PDT 24 |
| Finished | Jul 31 08:41:45 PM PDT 24 |
| Peak memory | 608720 kb |
| Host | smart-85e1f852-f9b3-484d-874e-ce725430a41e |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813829237 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.2813829237 |
| Directory | /workspace/2.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.1994237463 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 3894157652 ps |
| CPU time | 691.7 seconds |
| Started | Jul 31 08:34:37 PM PDT 24 |
| Finished | Jul 31 08:46:10 PM PDT 24 |
| Peak memory | 609968 kb |
| Host | smart-4f902225-72d6-45a8-9c1c-479cc2439f5d |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994237463 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.1994237463 |
| Directory | /workspace/2.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.2396843268 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 3235340050 ps |
| CPU time | 319.86 seconds |
| Started | Jul 31 08:35:32 PM PDT 24 |
| Finished | Jul 31 08:40:52 PM PDT 24 |
| Peak memory | 608636 kb |
| Host | smart-8ffafda2-c457-455e-b5ff-55912349ff91 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396843268 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_clkmgr_smoketest.2396843268 |
| Directory | /workspace/2.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.3023000428 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 22173528418 ps |
| CPU time | 5427.23 seconds |
| Started | Jul 31 08:31:54 PM PDT 24 |
| Finished | Jul 31 10:02:22 PM PDT 24 |
| Peak memory | 610504 kb |
| Host | smart-2632ed9d-4b97-4a50-b340-29d23c5a3a0d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023000428 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency.3023000428 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3185555602 |
| Short name | T1330 |
| Test name | |
| Test status | |
| Simulation time | 10022632678 ps |
| CPU time | 1383.38 seconds |
| Started | Jul 31 08:36:32 PM PDT 24 |
| Finished | Jul 31 08:59:36 PM PDT 24 |
| Peak memory | 610140 kb |
| Host | smart-9f477ae3-29f8-474a-9be8-576a551ba293 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3185555602 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency_reduced_freq.3185555602 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.3565969528 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 5101061192 ps |
| CPU time | 409.22 seconds |
| Started | Jul 31 08:31:37 PM PDT 24 |
| Finished | Jul 31 08:38:27 PM PDT 24 |
| Peak memory | 610960 kb |
| Host | smart-db89d84c-9995-4f47-b122-1b9fe9c0fc9b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35659 69528 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.3565969528 |
| Directory | /workspace/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_kat_test.1148243613 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 3000155700 ps |
| CPU time | 244.51 seconds |
| Started | Jul 31 08:34:49 PM PDT 24 |
| Finished | Jul 31 08:38:54 PM PDT 24 |
| Peak memory | 609696 kb |
| Host | smart-297a6040-da15-494d-8e6b-9471c55e4076 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148243613 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.1148243613 |
| Directory | /workspace/2.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.1894716039 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 8161178064 ps |
| CPU time | 940.98 seconds |
| Started | Jul 31 08:31:47 PM PDT 24 |
| Finished | Jul 31 08:47:29 PM PDT 24 |
| Peak memory | 611128 kb |
| Host | smart-3554e5c3-434b-434e-b984-4f6461365b32 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894716039 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csr ng_lc_hw_debug_en_test.1894716039 |
| Directory | /workspace/2.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_smoketest.1337298946 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 2861921884 ps |
| CPU time | 267.36 seconds |
| Started | Jul 31 08:37:09 PM PDT 24 |
| Finished | Jul 31 08:41:37 PM PDT 24 |
| Peak memory | 609588 kb |
| Host | smart-8baf7d12-2f51-44cd-a10d-379c7d5799ac |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337298946 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_csrng_smoketest.1337298946 |
| Directory | /workspace/2.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_data_integrity_escalation.4014290993 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 5293388784 ps |
| CPU time | 868.42 seconds |
| Started | Jul 31 08:28:21 PM PDT 24 |
| Finished | Jul 31 08:42:50 PM PDT 24 |
| Peak memory | 611172 kb |
| Host | smart-cfd89586-b832-4260-93f0-c3f5c3f65d84 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4014290993 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.4014290993 |
| Directory | /workspace/2.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_auto_mode.57748830 |
| Short name | T1325 |
| Test name | |
| Test status | |
| Simulation time | 5573575768 ps |
| CPU time | 1610.71 seconds |
| Started | Jul 31 08:33:28 PM PDT 24 |
| Finished | Jul 31 09:00:19 PM PDT 24 |
| Peak memory | 610252 kb |
| Host | smart-aefcd707-0a4f-44f9-ad53-0e98bb02a070 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57748830 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_au to_mode.57748830 |
| Directory | /workspace/2.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_boot_mode.2188277304 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 2718615994 ps |
| CPU time | 662.43 seconds |
| Started | Jul 31 08:31:56 PM PDT 24 |
| Finished | Jul 31 08:42:59 PM PDT 24 |
| Peak memory | 610068 kb |
| Host | smart-7af94a32-c36a-4ad5-b118-367a19dde525 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188277304 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ boot_mode.2188277304 |
| Directory | /workspace/2.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.4195064672 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 6421985256 ps |
| CPU time | 1257.81 seconds |
| Started | Jul 31 08:32:30 PM PDT 24 |
| Finished | Jul 31 08:53:28 PM PDT 24 |
| Peak memory | 610640 kb |
| Host | smart-ffbcb32f-a32d-4a9c-8ce4-fd0fa99a84d5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4195064672 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.4195064672 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.2943832790 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 6844931785 ps |
| CPU time | 990.76 seconds |
| Started | Jul 31 08:31:29 PM PDT 24 |
| Finished | Jul 31 08:48:00 PM PDT 24 |
| Peak memory | 610940 kb |
| Host | smart-5371a276-4ee0-4bbf-84a4-b7a1a6d4da75 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943832790 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.2943832790 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_kat.1858635855 |
| Short name | T1382 |
| Test name | |
| Test status | |
| Simulation time | 3888887256 ps |
| CPU time | 586.66 seconds |
| Started | Jul 31 08:31:49 PM PDT 24 |
| Finished | Jul 31 08:41:35 PM PDT 24 |
| Peak memory | 615528 kb |
| Host | smart-1e22f514-8550-496b-bb78-220f98a612bf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858635855 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_edn_kat.1858635855 |
| Directory | /workspace/2.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_sw_mode.1670158529 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 8939761988 ps |
| CPU time | 1753.11 seconds |
| Started | Jul 31 08:31:51 PM PDT 24 |
| Finished | Jul 31 09:01:05 PM PDT 24 |
| Peak memory | 609976 kb |
| Host | smart-67b30c14-2aec-4508-81f4-b4887e3bca26 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670158529 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_sw_mode.1670158529 |
| Directory | /workspace/2.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.2994374485 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 2910711956 ps |
| CPU time | 266.08 seconds |
| Started | Jul 31 08:31:58 PM PDT 24 |
| Finished | Jul 31 08:36:24 PM PDT 24 |
| Peak memory | 609476 kb |
| Host | smart-87bf551f-ea5f-4e50-bfa1-bbec4a64d617 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29 94374485 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.2994374485 |
| Directory | /workspace/2.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_csrng.597776588 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 7517127496 ps |
| CPU time | 2175.82 seconds |
| Started | Jul 31 08:32:09 PM PDT 24 |
| Finished | Jul 31 09:08:26 PM PDT 24 |
| Peak memory | 609284 kb |
| Host | smart-9ce812d6-0c42-49f7-bc64-32fb1b4d4ba5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=597776588 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.597776588 |
| Directory | /workspace/2.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.3424808638 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 2903075444 ps |
| CPU time | 238.27 seconds |
| Started | Jul 31 08:31:21 PM PDT 24 |
| Finished | Jul 31 08:35:20 PM PDT 24 |
| Peak memory | 609800 kb |
| Host | smart-0ac83f55-b51f-4f48-9cac-d9234f393cd0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424808638 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.3424808638 |
| Directory | /workspace/2.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.177716662 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 3870492178 ps |
| CPU time | 745.14 seconds |
| Started | Jul 31 08:36:13 PM PDT 24 |
| Finished | Jul 31 08:48:39 PM PDT 24 |
| Peak memory | 608632 kb |
| Host | smart-e8c1875a-bd53-4337-9715-15f4c8be9a93 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=177716662 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.177716662 |
| Directory | /workspace/2.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_concurrency.3942329780 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 2811376766 ps |
| CPU time | 295.75 seconds |
| Started | Jul 31 08:27:53 PM PDT 24 |
| Finished | Jul 31 08:32:49 PM PDT 24 |
| Peak memory | 609552 kb |
| Host | smart-640e626c-32a9-4812-b374-40433a6c3b26 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942329780 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_example_concurrency.3942329780 |
| Directory | /workspace/2.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_flash.4183058849 |
| Short name | T1362 |
| Test name | |
| Test status | |
| Simulation time | 2955035120 ps |
| CPU time | 242.26 seconds |
| Started | Jul 31 08:26:32 PM PDT 24 |
| Finished | Jul 31 08:30:34 PM PDT 24 |
| Peak memory | 608440 kb |
| Host | smart-a13e2a44-764b-446f-94dc-77d10101b02f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183058849 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_flash.4183058849 |
| Directory | /workspace/2.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_manufacturer.2923654050 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 2298580144 ps |
| CPU time | 214.24 seconds |
| Started | Jul 31 08:28:03 PM PDT 24 |
| Finished | Jul 31 08:31:38 PM PDT 24 |
| Peak memory | 609492 kb |
| Host | smart-2259195e-d2ef-4dcf-9eb4-45344c482913 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923654050 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_manufacturer.2923654050 |
| Directory | /workspace/2.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_rom.762491523 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 2161010812 ps |
| CPU time | 141.34 seconds |
| Started | Jul 31 08:25:59 PM PDT 24 |
| Finished | Jul 31 08:28:21 PM PDT 24 |
| Peak memory | 607876 kb |
| Host | smart-71972530-b364-4092-b35e-a720e652c68a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762491523 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_sw_example_rom.762491523 |
| Directory | /workspace/2.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_crash_alert.2060092654 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 5262558684 ps |
| CPU time | 582.72 seconds |
| Started | Jul 31 08:35:36 PM PDT 24 |
| Finished | Jul 31 08:45:19 PM PDT 24 |
| Peak memory | 610948 kb |
| Host | smart-1b95d862-94c4-455d-88e6-598ed82b3e52 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=2060092654 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.2060092654 |
| Directory | /workspace/2.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access.769627518 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 5313402266 ps |
| CPU time | 1181.35 seconds |
| Started | Jul 31 08:30:30 PM PDT 24 |
| Finished | Jul 31 08:50:12 PM PDT 24 |
| Peak memory | 608812 kb |
| Host | smart-5814b72f-3270-4896-8127-68bfd9ef062f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769627518 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_flash_ctrl_access.769627518 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.309259369 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 5751710017 ps |
| CPU time | 1212.98 seconds |
| Started | Jul 31 08:29:10 PM PDT 24 |
| Finished | Jul 31 08:49:24 PM PDT 24 |
| Peak memory | 610200 kb |
| Host | smart-91f60bd1-ad07-41de-a504-20c480168385 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309259369 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en.309259369 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1680194206 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 7167240807 ps |
| CPU time | 1148.11 seconds |
| Started | Jul 31 08:33:53 PM PDT 24 |
| Finished | Jul 31 08:53:01 PM PDT 24 |
| Peak memory | 610208 kb |
| Host | smart-faa14df8-4cfd-4159-8a87-8c123abc5719 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680194206 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1680194206 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.4026745099 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 5704490221 ps |
| CPU time | 1053.2 seconds |
| Started | Jul 31 08:29:30 PM PDT 24 |
| Finished | Jul 31 08:47:03 PM PDT 24 |
| Peak memory | 610060 kb |
| Host | smart-88e98c44-ef84-4a6c-b03a-6286a0e9a71d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026745099 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_flash_ctrl_clock_freqs.4026745099 |
| Directory | /workspace/2.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.2926139148 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 3828906900 ps |
| CPU time | 371.38 seconds |
| Started | Jul 31 08:28:01 PM PDT 24 |
| Finished | Jul 31 08:34:12 PM PDT 24 |
| Peak memory | 609876 kb |
| Host | smart-fe968b6a-13f0-4ace-9906-444fa73fe5c9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926139148 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_idle_low_power.2926139148 |
| Directory | /workspace/2.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.1679361888 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 5506252648 ps |
| CPU time | 1339.93 seconds |
| Started | Jul 31 08:35:34 PM PDT 24 |
| Finished | Jul 31 08:57:54 PM PDT 24 |
| Peak memory | 610036 kb |
| Host | smart-3c5b789f-327f-4d06-88a9-2c8ce7c9ce65 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679361888 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_mem_protection.1679361888 |
| Directory | /workspace/2.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.3219906853 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 4669406312 ps |
| CPU time | 719.91 seconds |
| Started | Jul 31 08:29:31 PM PDT 24 |
| Finished | Jul 31 08:41:31 PM PDT 24 |
| Peak memory | 610144 kb |
| Host | smart-391c5a3a-80f2-46f8-a8f8-c05d12c11d0a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219906853 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.3219906853 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2831269471 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 3895913887 ps |
| CPU time | 730.42 seconds |
| Started | Jul 31 08:29:15 PM PDT 24 |
| Finished | Jul 31 08:41:25 PM PDT 24 |
| Peak memory | 609936 kb |
| Host | smart-746f049a-439e-41c5-b37a-c793e55862ba |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2831269471 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.2831269471 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2777944314 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 4974354759 ps |
| CPU time | 581.51 seconds |
| Started | Jul 31 08:35:46 PM PDT 24 |
| Finished | Jul 31 08:45:27 PM PDT 24 |
| Peak memory | 609220 kb |
| Host | smart-9f19d538-9b06-4250-a390-80e0b1ba5d4b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=2777944314 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2777944314 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.4293556644 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 2869594000 ps |
| CPU time | 427.84 seconds |
| Started | Jul 31 08:34:40 PM PDT 24 |
| Finished | Jul 31 08:41:48 PM PDT 24 |
| Peak memory | 609800 kb |
| Host | smart-ff5893db-c23b-43c8-9c5d-75b97c1abbfb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293556 644 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_write_clear.4293556644 |
| Directory | /workspace/2.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init.2431794803 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 17510042344 ps |
| CPU time | 1749.78 seconds |
| Started | Jul 31 08:28:22 PM PDT 24 |
| Finished | Jul 31 08:57:33 PM PDT 24 |
| Peak memory | 612796 kb |
| Host | smart-3619b8a0-6b0d-40da-8080-59f73e4f6f5b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431794803 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init.2431794803 |
| Directory | /workspace/2.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.753367233 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 24921357109 ps |
| CPU time | 1632.49 seconds |
| Started | Jul 31 08:35:12 PM PDT 24 |
| Finished | Jul 31 09:02:25 PM PDT 24 |
| Peak memory | 615476 kb |
| Host | smart-214aff39-d163-4409-9f80-5db46fe4bbc1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=753367233 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.753367233 |
| Directory | /workspace/2.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.1867910532 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 3100854410 ps |
| CPU time | 187.57 seconds |
| Started | Jul 31 08:39:09 PM PDT 24 |
| Finished | Jul 31 08:42:17 PM PDT 24 |
| Peak memory | 609724 kb |
| Host | smart-bff151b3-1ae7-47f4-8867-32ea0177b6d1 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1867910532 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.1867910532 |
| Directory | /workspace/2.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio.867989341 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 4275026030 ps |
| CPU time | 577.8 seconds |
| Started | Jul 31 08:29:55 PM PDT 24 |
| Finished | Jul 31 08:39:34 PM PDT 24 |
| Peak memory | 610040 kb |
| Host | smart-2925003e-225b-4630-ac7a-50b706f397ce |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867989341 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.chip_sw_gpio.867989341 |
| Directory | /workspace/2.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio_smoketest.3757828773 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 2873572394 ps |
| CPU time | 250.18 seconds |
| Started | Jul 31 08:35:35 PM PDT 24 |
| Finished | Jul 31 08:39:46 PM PDT 24 |
| Peak memory | 609028 kb |
| Host | smart-cc641f97-c65b-4c61-bee8-d0f7b1adcdcd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757828773 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_gpio_smoketest.3757828773 |
| Directory | /workspace/2.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc.3359688927 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 3358002044 ps |
| CPU time | 355.1 seconds |
| Started | Jul 31 08:32:08 PM PDT 24 |
| Finished | Jul 31 08:38:04 PM PDT 24 |
| Peak memory | 609824 kb |
| Host | smart-a7950cfd-b72e-498c-93b1-b2a1cdfdd302 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359688927 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc.3359688927 |
| Directory | /workspace/2.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_idle.1301728934 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 3618817200 ps |
| CPU time | 335.03 seconds |
| Started | Jul 31 08:32:08 PM PDT 24 |
| Finished | Jul 31 08:37:43 PM PDT 24 |
| Peak memory | 608548 kb |
| Host | smart-817ea0b9-bd59-45c7-a151-c48bf373914a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301728934 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_hmac_enc_idle.1301728934 |
| Directory | /workspace/2.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.3814370585 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 3529614095 ps |
| CPU time | 343.95 seconds |
| Started | Jul 31 08:31:25 PM PDT 24 |
| Finished | Jul 31 08:37:09 PM PDT 24 |
| Peak memory | 609760 kb |
| Host | smart-f36826cf-5773-4f10-84f2-2503e8f1e6d7 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814370585 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en.3814370585 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.2959921173 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 3425738768 ps |
| CPU time | 226.21 seconds |
| Started | Jul 31 08:39:56 PM PDT 24 |
| Finished | Jul 31 08:43:42 PM PDT 24 |
| Peak memory | 609624 kb |
| Host | smart-39d272bf-74cb-4c2b-9df1-d567633f4a71 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959921173 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.2959921173 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_multistream.4074939087 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 7261380854 ps |
| CPU time | 1487.55 seconds |
| Started | Jul 31 08:32:12 PM PDT 24 |
| Finished | Jul 31 08:57:00 PM PDT 24 |
| Peak memory | 610212 kb |
| Host | smart-5650460a-c440-4606-b491-62903ad1d507 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074939087 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_hmac_multistream.4074939087 |
| Directory | /workspace/2.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_oneshot.2278998420 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 3487437544 ps |
| CPU time | 449.59 seconds |
| Started | Jul 31 08:33:06 PM PDT 24 |
| Finished | Jul 31 08:40:37 PM PDT 24 |
| Peak memory | 608496 kb |
| Host | smart-64345a75-279c-4d3c-b7cd-fd29bf4c77ef |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278998420 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_oneshot.2278998420 |
| Directory | /workspace/2.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_smoketest.1470146936 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 4180813110 ps |
| CPU time | 395.76 seconds |
| Started | Jul 31 08:36:35 PM PDT 24 |
| Finished | Jul 31 08:43:11 PM PDT 24 |
| Peak memory | 609692 kb |
| Host | smart-acb761de-9d63-4fe0-8081-4b8903143313 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470146936 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_hmac_smoketest.1470146936 |
| Directory | /workspace/2.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.1725428875 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 3346005756 ps |
| CPU time | 436.52 seconds |
| Started | Jul 31 08:31:48 PM PDT 24 |
| Finished | Jul 31 08:39:05 PM PDT 24 |
| Peak memory | 610524 kb |
| Host | smart-d04a1394-86ed-4abb-96b0-95034748ae69 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725428875 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.1725428875 |
| Directory | /workspace/2.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.804776849 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 4665624580 ps |
| CPU time | 916.79 seconds |
| Started | Jul 31 08:28:30 PM PDT 24 |
| Finished | Jul 31 08:43:47 PM PDT 24 |
| Peak memory | 609232 kb |
| Host | smart-54ceadb3-ba8b-4153-ac7d-5ac3f4329f2e |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804776849 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx.804776849 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.1416470227 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 5475424332 ps |
| CPU time | 948.32 seconds |
| Started | Jul 31 08:28:37 PM PDT 24 |
| Finished | Jul 31 08:44:26 PM PDT 24 |
| Peak memory | 609276 kb |
| Host | smart-edb94c1b-16e3-4228-a13d-04dce04705fb |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416470227 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.1416470227 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.1699651681 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 5202123260 ps |
| CPU time | 912.61 seconds |
| Started | Jul 31 08:31:48 PM PDT 24 |
| Finished | Jul 31 08:47:01 PM PDT 24 |
| Peak memory | 609168 kb |
| Host | smart-53659060-a40c-4fae-98aa-7ea4b05099b4 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699651681 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.1699651681 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_inject_scramble_seed.435653470 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 63257616981 ps |
| CPU time | 11285 seconds |
| Started | Jul 31 08:28:30 PM PDT 24 |
| Finished | Jul 31 11:36:37 PM PDT 24 |
| Peak memory | 624728 kb |
| Host | smart-0babcf1f-bba1-45df-9b5a-c3add371567d |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=435653470 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.435653470 |
| Directory | /workspace/2.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1805729028 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 7960603428 ps |
| CPU time | 1573.14 seconds |
| Started | Jul 31 08:33:13 PM PDT 24 |
| Finished | Jul 31 08:59:27 PM PDT 24 |
| Peak memory | 617920 kb |
| Host | smart-41f4e25e-ab00-4892-8907-ec222bc4ae03 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805 729028 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation.1805729028 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.2966528231 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 11107150567 ps |
| CPU time | 1532.33 seconds |
| Started | Jul 31 08:36:17 PM PDT 24 |
| Finished | Jul 31 09:01:50 PM PDT 24 |
| Peak memory | 617948 kb |
| Host | smart-413331e1-3154-4a3a-87e0-714cb591beea |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2966528231 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.2966528231 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.472775920 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 13154969044 ps |
| CPU time | 1633.59 seconds |
| Started | Jul 31 08:39:32 PM PDT 24 |
| Finished | Jul 31 09:06:46 PM PDT 24 |
| Peak memory | 617792 kb |
| Host | smart-6cdaea92-00c0-40b1-b0db-f01b3bc3df2c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=472775920 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en_ reduced_freq.472775920 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.1109961837 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 7746690644 ps |
| CPU time | 1458.31 seconds |
| Started | Jul 31 08:32:15 PM PDT 24 |
| Finished | Jul 31 08:56:34 PM PDT 24 |
| Peak memory | 616908 kb |
| Host | smart-18b25ea9-3d1c-44c7-bfff-9fafecab0570 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1109961837 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.1109961837 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.4102839858 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 7940903530 ps |
| CPU time | 1468.74 seconds |
| Started | Jul 31 08:32:07 PM PDT 24 |
| Finished | Jul 31 08:56:36 PM PDT 24 |
| Peak memory | 611104 kb |
| Host | smart-c307860d-24df-443f-9f11-a4806eecf9fb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410283 9858 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.4102839858 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3085787974 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 9216015506 ps |
| CPU time | 1704.43 seconds |
| Started | Jul 31 08:36:58 PM PDT 24 |
| Finished | Jul 31 09:05:23 PM PDT 24 |
| Peak memory | 611120 kb |
| Host | smart-31073186-48ba-4baa-a707-2db541eae10b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30857 87974 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.3085787974 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.2722687715 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 12416924492 ps |
| CPU time | 3551.49 seconds |
| Started | Jul 31 08:31:31 PM PDT 24 |
| Finished | Jul 31 09:30:43 PM PDT 24 |
| Peak memory | 610916 kb |
| Host | smart-efae433c-2c43-45df-8c5d-3e18565c25b9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27226 87715 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.2722687715 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_app_rom.351012987 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 2960934812 ps |
| CPU time | 181.4 seconds |
| Started | Jul 31 08:36:57 PM PDT 24 |
| Finished | Jul 31 08:39:58 PM PDT 24 |
| Peak memory | 609692 kb |
| Host | smart-78f9e2bb-0eca-4571-b879-ca4930cef058 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351012987 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_kmac_app_rom.351012987 |
| Directory | /workspace/2.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_entropy.1157201478 |
| Short name | T1378 |
| Test name | |
| Test status | |
| Simulation time | 2628971500 ps |
| CPU time | 238.5 seconds |
| Started | Jul 31 08:29:39 PM PDT 24 |
| Finished | Jul 31 08:33:39 PM PDT 24 |
| Peak memory | 608468 kb |
| Host | smart-e45cef14-7a3b-4ee5-a4e5-e5c902064e43 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157201478 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_entropy.1157201478 |
| Directory | /workspace/2.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_idle.2568925346 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 3496911344 ps |
| CPU time | 344.12 seconds |
| Started | Jul 31 08:31:55 PM PDT 24 |
| Finished | Jul 31 08:37:40 PM PDT 24 |
| Peak memory | 608412 kb |
| Host | smart-deca8542-dd95-4dcf-8992-2724ada05ae6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568925346 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_idle.2568925346 |
| Directory | /workspace/2.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.4176474416 |
| Short name | T1329 |
| Test name | |
| Test status | |
| Simulation time | 2810282728 ps |
| CPU time | 305.24 seconds |
| Started | Jul 31 08:33:57 PM PDT 24 |
| Finished | Jul 31 08:39:02 PM PDT 24 |
| Peak memory | 609620 kb |
| Host | smart-ca6212db-0a81-4ff6-a0c8-d144e89c3723 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176474416 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_sw_kmac_mode_cshake.4176474416 |
| Directory | /workspace/2.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.4139587444 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 3735051608 ps |
| CPU time | 372.3 seconds |
| Started | Jul 31 08:36:37 PM PDT 24 |
| Finished | Jul 31 08:42:50 PM PDT 24 |
| Peak memory | 608516 kb |
| Host | smart-284bf19f-9252-4dfd-b896-1ef6bc7a7a0e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139587444 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_kmac_mode_kmac.4139587444 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.268762505 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 2961354686 ps |
| CPU time | 307.06 seconds |
| Started | Jul 31 08:33:20 PM PDT 24 |
| Finished | Jul 31 08:38:28 PM PDT 24 |
| Peak memory | 609644 kb |
| Host | smart-0451ba94-7225-4a0f-8be6-38b0b9c9af10 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268762505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.268762505 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.553086638 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 3738852878 ps |
| CPU time | 324.14 seconds |
| Started | Jul 31 08:34:40 PM PDT 24 |
| Finished | Jul 31 08:40:04 PM PDT 24 |
| Peak memory | 609808 kb |
| Host | smart-c432c1ac-530c-43dd-afc6-c470fdaad71d |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55308663 8 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.553086638 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_smoketest.2341525762 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 2248301880 ps |
| CPU time | 300.86 seconds |
| Started | Jul 31 08:36:44 PM PDT 24 |
| Finished | Jul 31 08:41:46 PM PDT 24 |
| Peak memory | 609680 kb |
| Host | smart-137ca2ec-8115-466c-9b85-b491a0a04273 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341525762 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_smoketest.2341525762 |
| Directory | /workspace/2.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.4162564142 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 3594543504 ps |
| CPU time | 369.24 seconds |
| Started | Jul 31 08:28:10 PM PDT 24 |
| Finished | Jul 31 08:34:19 PM PDT 24 |
| Peak memory | 609376 kb |
| Host | smart-81612d56-1f49-4890-b8a7-3684f8bcce92 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162564142 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_lc_ctrl_otp_hw_cfg0.4162564142 |
| Directory | /workspace/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.1700341714 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 4899421302 ps |
| CPU time | 572.99 seconds |
| Started | Jul 31 08:36:52 PM PDT 24 |
| Finished | Jul 31 08:46:25 PM PDT 24 |
| Peak memory | 611020 kb |
| Host | smart-6ba53ca0-af14-455b-8123-d6fb56b4134a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1700341714 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_program_error.1700341714 |
| Directory | /workspace/2.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.571096304 |
| Short name | T1379 |
| Test name | |
| Test status | |
| Simulation time | 3535213302 ps |
| CPU time | 168.21 seconds |
| Started | Jul 31 08:29:13 PM PDT 24 |
| Finished | Jul 31 08:32:01 PM PDT 24 |
| Peak memory | 620164 kb |
| Host | smart-6dae3a52-aacb-4f50-a1fc-e5dc2c62e9de |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57109630 4 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_rand_to_scrap.571096304 |
| Directory | /workspace/2.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.2871388226 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 6781980339 ps |
| CPU time | 640.42 seconds |
| Started | Jul 31 08:29:55 PM PDT 24 |
| Finished | Jul 31 08:40:35 PM PDT 24 |
| Peak memory | 620400 kb |
| Host | smart-bd6a816e-f577-452e-ab97-2a3513ae1d99 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871388226 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_transition.2871388226 |
| Directory | /workspace/2.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.3014157173 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 2909609943 ps |
| CPU time | 111.28 seconds |
| Started | Jul 31 08:30:15 PM PDT 24 |
| Finished | Jul 31 08:32:07 PM PDT 24 |
| Peak memory | 617736 kb |
| Host | smart-09ff5b42-5939-457b-bb7a-779a07251d3f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3014157173 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.3014157173 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3956825374 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 2460875159 ps |
| CPU time | 121.53 seconds |
| Started | Jul 31 08:30:23 PM PDT 24 |
| Finished | Jul 31 08:32:25 PM PDT 24 |
| Peak memory | 617692 kb |
| Host | smart-97ff471c-874c-4e4e-a211-d7ce19cc7217 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956825374 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3956825374 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.1573698185 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 50547948893 ps |
| CPU time | 5497.65 seconds |
| Started | Jul 31 08:30:02 PM PDT 24 |
| Finished | Jul 31 10:01:41 PM PDT 24 |
| Peak memory | 619860 kb |
| Host | smart-e7bd4499-7d4c-4561-8150-3c2a84fed003 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573698185 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chi p_sw_lc_walkthrough_prod.1573698185 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.590056496 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 8255849729 ps |
| CPU time | 1144.34 seconds |
| Started | Jul 31 08:31:31 PM PDT 24 |
| Finished | Jul 31 08:50:36 PM PDT 24 |
| Peak memory | 620272 kb |
| Host | smart-940ebcd6-824f-4500-8c85-b9b31a4e5154 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=590056496 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.590056496 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.2060025499 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 46134494992 ps |
| CPU time | 5366.36 seconds |
| Started | Jul 31 08:30:27 PM PDT 24 |
| Finished | Jul 31 09:59:55 PM PDT 24 |
| Peak memory | 616800 kb |
| Host | smart-aee315ce-f99e-480e-af30-d2be0ed7d058 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060025499 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_rma.2060025499 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.3824440462 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 36527468810 ps |
| CPU time | 2303.47 seconds |
| Started | Jul 31 08:30:02 PM PDT 24 |
| Finished | Jul 31 09:08:26 PM PDT 24 |
| Peak memory | 622080 kb |
| Host | smart-2a63f66a-bb55-44d2-8f8e-5ab9148f395e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3824440462 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testun locks.3824440462 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1551707604 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 17499590622 ps |
| CPU time | 3372.17 seconds |
| Started | Jul 31 08:33:11 PM PDT 24 |
| Finished | Jul 31 09:29:24 PM PDT 24 |
| Peak memory | 610236 kb |
| Host | smart-0ffecd9f-042f-43dc-b695-98deade5bb7e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=1551707604 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.1551707604 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.2472398798 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 18921365389 ps |
| CPU time | 3416.01 seconds |
| Started | Jul 31 08:33:27 PM PDT 24 |
| Finished | Jul 31 09:30:23 PM PDT 24 |
| Peak memory | 610116 kb |
| Host | smart-2f616d1f-cbbe-4562-a2a0-175f9f50365a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2472398798 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.2472398798 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2397419941 |
| Short name | T1359 |
| Test name | |
| Test status | |
| Simulation time | 24782072316 ps |
| CPU time | 3359.98 seconds |
| Started | Jul 31 08:35:04 PM PDT 24 |
| Finished | Jul 31 09:31:04 PM PDT 24 |
| Peak memory | 610152 kb |
| Host | smart-334432f6-c4e6-4761-9fe8-33e92e1537c9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397419941 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.2397419941 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.3193818854 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 3185309388 ps |
| CPU time | 541.08 seconds |
| Started | Jul 31 08:31:45 PM PDT 24 |
| Finished | Jul 31 08:40:47 PM PDT 24 |
| Peak memory | 609784 kb |
| Host | smart-2bd27b7d-6f6e-4482-aa9f-ccebe0dfc589 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193818854 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.3193818854 |
| Directory | /workspace/2.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_randomness.2975686400 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 6533953730 ps |
| CPU time | 918.21 seconds |
| Started | Jul 31 08:32:19 PM PDT 24 |
| Finished | Jul 31 08:47:38 PM PDT 24 |
| Peak memory | 610240 kb |
| Host | smart-eb2015fd-7e15-47b8-b365-ccaa6d94cdf4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2975686400 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.2975686400 |
| Directory | /workspace/2.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_smoketest.3062035814 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 8003768424 ps |
| CPU time | 1359.52 seconds |
| Started | Jul 31 08:35:32 PM PDT 24 |
| Finished | Jul 31 08:58:12 PM PDT 24 |
| Peak memory | 609048 kb |
| Host | smart-511fd15c-b761-486e-823b-5b187e0584cc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062035814 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_otbn_smoketest.3062035814 |
| Directory | /workspace/2.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.2689484810 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 2884183027 ps |
| CPU time | 341.49 seconds |
| Started | Jul 31 08:29:45 PM PDT 24 |
| Finished | Jul 31 08:35:27 PM PDT 24 |
| Peak memory | 608712 kb |
| Host | smart-b41f4c94-149d-4f59-b525-42c471f1a47c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689484810 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_ecc_error_vendor_test.2689484810 |
| Directory | /workspace/2.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.607686914 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 8720723474 ps |
| CPU time | 1390.79 seconds |
| Started | Jul 31 08:29:03 PM PDT 24 |
| Finished | Jul 31 08:52:14 PM PDT 24 |
| Peak memory | 610684 kb |
| Host | smart-b2b38187-2731-4ec0-8859-fbc6869a0ae5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=607686914 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.607686914 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.673683934 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 7934558260 ps |
| CPU time | 1457.56 seconds |
| Started | Jul 31 08:31:32 PM PDT 24 |
| Finished | Jul 31 08:55:50 PM PDT 24 |
| Peak memory | 610632 kb |
| Host | smart-03db4bd8-20b3-4893-aa04-a15eefa613d6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=673683934 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.673683934 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.166190195 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 7789950804 ps |
| CPU time | 1201.49 seconds |
| Started | Jul 31 08:31:14 PM PDT 24 |
| Finished | Jul 31 08:51:16 PM PDT 24 |
| Peak memory | 610660 kb |
| Host | smart-5ee0bb35-283a-4e02-b244-989e660d95f1 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=166190195 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.166190195 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.669206380 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 4787276840 ps |
| CPU time | 757.89 seconds |
| Started | Jul 31 08:28:47 PM PDT 24 |
| Finished | Jul 31 08:41:25 PM PDT 24 |
| Peak memory | 609144 kb |
| Host | smart-c76006ca-ef85-4df3-86c2-cc179b574058 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=669206380 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.669206380 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.1019204314 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 2233545192 ps |
| CPU time | 259.21 seconds |
| Started | Jul 31 08:37:28 PM PDT 24 |
| Finished | Jul 31 08:41:47 PM PDT 24 |
| Peak memory | 609612 kb |
| Host | smart-298584e3-b96c-403b-a7c7-7834218ba560 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019204314 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_otp_ctrl_smoketest.1019204314 |
| Directory | /workspace/2.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pattgen_ios.1674501340 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 2809556648 ps |
| CPU time | 189.89 seconds |
| Started | Jul 31 08:27:59 PM PDT 24 |
| Finished | Jul 31 08:31:09 PM PDT 24 |
| Peak memory | 612404 kb |
| Host | smart-70f5531d-3462-47cf-9fef-a1c953c32b39 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674501340 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.1674501340 |
| Directory | /workspace/2.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/2.chip_sw_plic_sw_irq.3899018002 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 3399515076 ps |
| CPU time | 294.07 seconds |
| Started | Jul 31 08:35:38 PM PDT 24 |
| Finished | Jul 31 08:40:33 PM PDT 24 |
| Peak memory | 609680 kb |
| Host | smart-1c2bdee9-de07-4fdb-8bfa-bea2c96200c0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899018002 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_plic_sw_irq.3899018002 |
| Directory | /workspace/2.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_idle_load.2916162760 |
| Short name | T1351 |
| Test name | |
| Test status | |
| Simulation time | 4378304200 ps |
| CPU time | 730.54 seconds |
| Started | Jul 31 08:36:33 PM PDT 24 |
| Finished | Jul 31 08:48:44 PM PDT 24 |
| Peak memory | 610328 kb |
| Host | smart-54317731-9aeb-4c3f-bcbf-163300358a9b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916162760 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_idle_load.2916162760 |
| Directory | /workspace/2.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_sleep_load.413306769 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 11238089286 ps |
| CPU time | 658.61 seconds |
| Started | Jul 31 08:39:47 PM PDT 24 |
| Finished | Jul 31 08:50:46 PM PDT 24 |
| Peak memory | 609700 kb |
| Host | smart-220b9507-e3b2-4938-bd9f-a9a5578592c1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413306769 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.413306769 |
| Directory | /workspace/2.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.3382492525 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 11109571882 ps |
| CPU time | 1630.2 seconds |
| Started | Jul 31 08:29:32 PM PDT 24 |
| Finished | Jul 31 08:56:43 PM PDT 24 |
| Peak memory | 611444 kb |
| Host | smart-da6e3eae-372c-426c-a605-8f7a00174a38 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382 492525 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.3382492525 |
| Directory | /workspace/2.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.3005347784 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 30579286800 ps |
| CPU time | 2144.44 seconds |
| Started | Jul 31 08:35:07 PM PDT 24 |
| Finished | Jul 31 09:10:52 PM PDT 24 |
| Peak memory | 610912 kb |
| Host | smart-5b5f87a6-1bb2-45dc-9835-a7a509fbc914 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300 5347784 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.3005347784 |
| Directory | /workspace/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2136084800 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 15154797940 ps |
| CPU time | 1555.12 seconds |
| Started | Jul 31 08:30:20 PM PDT 24 |
| Finished | Jul 31 08:56:16 PM PDT 24 |
| Peak memory | 611328 kb |
| Host | smart-c00fe694-842b-4230-9fbd-adfc3458ba89 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2136084800 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2136084800 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.1782920131 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 9552789104 ps |
| CPU time | 720.75 seconds |
| Started | Jul 31 08:30:17 PM PDT 24 |
| Finished | Jul 31 08:42:18 PM PDT 24 |
| Peak memory | 610924 kb |
| Host | smart-1493dd00-8d41-4e0b-958c-6aa71a1671db |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782920131 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_por_reset.1782920131 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1899727308 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 6119058618 ps |
| CPU time | 569.12 seconds |
| Started | Jul 31 08:30:22 PM PDT 24 |
| Finished | Jul 31 08:39:52 PM PDT 24 |
| Peak memory | 616392 kb |
| Host | smart-7bbecae3-32bd-4e8f-ac47-026f647235a4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1899727308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1899727308 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.466202820 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 9672440778 ps |
| CPU time | 574.12 seconds |
| Started | Jul 31 08:29:45 PM PDT 24 |
| Finished | Jul 31 08:39:20 PM PDT 24 |
| Peak memory | 610716 kb |
| Host | smart-ab6e8038-78a7-4fdb-92b8-98a7e54ce0e7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466202820 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_pwrmgr_full_aon_reset.466202820 |
| Directory | /workspace/2.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.3707856255 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 3211926274 ps |
| CPU time | 391.87 seconds |
| Started | Jul 31 08:29:54 PM PDT 24 |
| Finished | Jul 31 08:36:26 PM PDT 24 |
| Peak memory | 617280 kb |
| Host | smart-b15cb733-5bb2-48ea-9246-a85da7ee513e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3707856255 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.3707856255 |
| Directory | /workspace/2.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.351039280 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 12355685046 ps |
| CPU time | 1691.31 seconds |
| Started | Jul 31 08:29:30 PM PDT 24 |
| Finished | Jul 31 08:57:42 PM PDT 24 |
| Peak memory | 611228 kb |
| Host | smart-64bf2089-27fb-4017-815b-b7a555342aed |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351039280 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.351039280 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3034546195 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 7912764198 ps |
| CPU time | 526.26 seconds |
| Started | Jul 31 08:33:25 PM PDT 24 |
| Finished | Jul 31 08:42:12 PM PDT 24 |
| Peak memory | 610380 kb |
| Host | smart-4540caa8-f31f-403c-aa4e-1f1a314e2c74 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034546195 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3034546195 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.2764030514 |
| Short name | T1384 |
| Test name | |
| Test status | |
| Simulation time | 7177244080 ps |
| CPU time | 763.71 seconds |
| Started | Jul 31 08:30:19 PM PDT 24 |
| Finished | Jul 31 08:43:03 PM PDT 24 |
| Peak memory | 610872 kb |
| Host | smart-53fcef35-9a2c-4343-a7b0-4e58173ac0dc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764030514 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.2764030514 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.64011398 |
| Short name | T1363 |
| Test name | |
| Test status | |
| Simulation time | 28292712536 ps |
| CPU time | 2566.37 seconds |
| Started | Jul 31 08:30:44 PM PDT 24 |
| Finished | Jul 31 09:13:31 PM PDT 24 |
| Peak memory | 611340 kb |
| Host | smart-f21c2087-33b0-4814-9a66-f1adba0c0bc9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=64011398 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.64011398 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.502983543 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 24681732416 ps |
| CPU time | 1467.57 seconds |
| Started | Jul 31 08:34:08 PM PDT 24 |
| Finished | Jul 31 08:58:36 PM PDT 24 |
| Peak memory | 610872 kb |
| Host | smart-2ef668a5-f52f-43b1-944d-8368f8d92ade |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=502983543 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.502983543 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3901083187 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 23653120497 ps |
| CPU time | 2568 seconds |
| Started | Jul 31 08:29:07 PM PDT 24 |
| Finished | Jul 31 09:11:55 PM PDT 24 |
| Peak memory | 612008 kb |
| Host | smart-4201395f-97b4-497e-9b8b-60e4b10d37d6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901083187 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_s leep_power_glitch_reset.3901083187 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3363519087 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 5573276120 ps |
| CPU time | 509.09 seconds |
| Started | Jul 31 08:36:10 PM PDT 24 |
| Finished | Jul 31 08:44:40 PM PDT 24 |
| Peak memory | 610732 kb |
| Host | smart-1bb9da12-11d0-48f4-8e5d-b08a8e5652c7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3363519087 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.3363519087 |
| Directory | /workspace/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.114150503 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 3155925424 ps |
| CPU time | 305.33 seconds |
| Started | Jul 31 08:30:05 PM PDT 24 |
| Finished | Jul 31 08:35:11 PM PDT 24 |
| Peak memory | 609796 kb |
| Host | smart-57481d57-c1bf-488b-a4d8-23627d01f032 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114150503 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_disabled.114150503 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.2473992045 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 5879349146 ps |
| CPU time | 653.29 seconds |
| Started | Jul 31 08:30:25 PM PDT 24 |
| Finished | Jul 31 08:41:18 PM PDT 24 |
| Peak memory | 617880 kb |
| Host | smart-be2e8002-4505-44b9-aa4a-8c1fba002332 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2473992045 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_power_glitch_reset.2473992045 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.763364254 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 5463593568 ps |
| CPU time | 526.66 seconds |
| Started | Jul 31 08:33:48 PM PDT 24 |
| Finished | Jul 31 08:42:35 PM PDT 24 |
| Peak memory | 610012 kb |
| Host | smart-2bd27ed4-1dc9-44a8-ae71-95264e5abf61 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76336425 4 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.763364254 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.1165566721 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 6196564234 ps |
| CPU time | 676.99 seconds |
| Started | Jul 31 08:33:50 PM PDT 24 |
| Finished | Jul 31 08:45:07 PM PDT 24 |
| Peak memory | 610592 kb |
| Host | smart-ce258f27-6c0e-411c-a041-18c891280700 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1165566721 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.1165566721 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1471437373 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 5379305800 ps |
| CPU time | 361.57 seconds |
| Started | Jul 31 08:36:30 PM PDT 24 |
| Finished | Jul 31 08:42:32 PM PDT 24 |
| Peak memory | 610472 kb |
| Host | smart-fdd04d18-7b5c-4a35-9ab3-6070ea6802a5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471437373 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.1471437373 |
| Directory | /workspace/2.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.840877224 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 5627887288 ps |
| CPU time | 971.94 seconds |
| Started | Jul 31 08:32:11 PM PDT 24 |
| Finished | Jul 31 08:48:24 PM PDT 24 |
| Peak memory | 609796 kb |
| Host | smart-42cde1f2-70da-4a55-8858-73acd9959e30 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840877224 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.840877224 |
| Directory | /workspace/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2589790745 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 5349659400 ps |
| CPU time | 671.39 seconds |
| Started | Jul 31 08:30:23 PM PDT 24 |
| Finished | Jul 31 08:41:35 PM PDT 24 |
| Peak memory | 610268 kb |
| Host | smart-b78571aa-6fe2-4cb8-b377-736f102f1eb5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589790745 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2589790745 |
| Directory | /workspace/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.47293374 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 6056541144 ps |
| CPU time | 371.98 seconds |
| Started | Jul 31 08:35:50 PM PDT 24 |
| Finished | Jul 31 08:42:02 PM PDT 24 |
| Peak memory | 610456 kb |
| Host | smart-3082320b-ef34-4c78-8333-e93389f652c6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47293374 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_sw_pwrmgr_usbdev_smoketest.47293374 |
| Directory | /workspace/2.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.1407530960 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 4647674948 ps |
| CPU time | 850.42 seconds |
| Started | Jul 31 08:31:04 PM PDT 24 |
| Finished | Jul 31 08:45:16 PM PDT 24 |
| Peak memory | 610348 kb |
| Host | smart-c4c08565-0e53-4a62-829a-ad907f8aa4f6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140 7530960 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.1407530960 |
| Directory | /workspace/2.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2922217145 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 9555703334 ps |
| CPU time | 520.95 seconds |
| Started | Jul 31 08:33:52 PM PDT 24 |
| Finished | Jul 31 08:42:34 PM PDT 24 |
| Peak memory | 624752 kb |
| Host | smart-d54cad4a-10a5-4240-83ad-af172fe52e06 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922217145 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.2922217145 |
| Directory | /workspace/2.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1738007981 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 12418998628 ps |
| CPU time | 1509.17 seconds |
| Started | Jul 31 08:30:12 PM PDT 24 |
| Finished | Jul 31 08:55:21 PM PDT 24 |
| Peak memory | 610988 kb |
| Host | smart-1995ad73-a566-4800-bf2d-1c34a71e4ad0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1738007981 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.1738007981 |
| Directory | /workspace/2.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.1389234562 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 6476659680 ps |
| CPU time | 751.35 seconds |
| Started | Jul 31 08:30:31 PM PDT 24 |
| Finished | Jul 31 08:43:02 PM PDT 24 |
| Peak memory | 610524 kb |
| Host | smart-974e4972-fc21-4f62-8ce9-9d4d817076e4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389234562 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_rstmgr_cpu_info.1389234562 |
| Directory | /workspace/2.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.1002724327 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 5533915400 ps |
| CPU time | 545.08 seconds |
| Started | Jul 31 08:28:40 PM PDT 24 |
| Finished | Jul 31 08:37:45 PM PDT 24 |
| Peak memory | 641668 kb |
| Host | smart-7315b1df-6274-494d-a014-687d43043f29 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1002724327 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.1002724327 |
| Directory | /workspace/2.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.1775573209 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 2678055608 ps |
| CPU time | 203.08 seconds |
| Started | Jul 31 08:35:58 PM PDT 24 |
| Finished | Jul 31 08:39:22 PM PDT 24 |
| Peak memory | 609636 kb |
| Host | smart-5084cda6-3550-48b6-9730-a97fa9aaf4a3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775573209 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_rstmgr_smoketest.1775573209 |
| Directory | /workspace/2.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.3852063471 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 4133834714 ps |
| CPU time | 513.21 seconds |
| Started | Jul 31 08:30:41 PM PDT 24 |
| Finished | Jul 31 08:39:14 PM PDT 24 |
| Peak memory | 610020 kb |
| Host | smart-4d3fb3ef-2bf2-464e-b747-580d8952492a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852063471 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rstmgr_sw_req.3852063471 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.381964417 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 2522068632 ps |
| CPU time | 218.17 seconds |
| Started | Jul 31 08:30:51 PM PDT 24 |
| Finished | Jul 31 08:34:29 PM PDT 24 |
| Peak memory | 608500 kb |
| Host | smart-d612cb6e-edba-4932-8885-7296ee085394 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381964417 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_sw_rst.381964417 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.1990777828 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 2848652816 ps |
| CPU time | 268.22 seconds |
| Started | Jul 31 08:34:15 PM PDT 24 |
| Finished | Jul 31 08:38:43 PM PDT 24 |
| Peak memory | 608568 kb |
| Host | smart-6376233a-1826-4324-8f26-92b5ccafd4a9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1990777828 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.1990777828 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.486796761 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 2726694243 ps |
| CPU time | 321.04 seconds |
| Started | Jul 31 08:34:59 PM PDT 24 |
| Finished | Jul 31 08:40:20 PM PDT 24 |
| Peak memory | 609648 kb |
| Host | smart-829ece42-e81d-4557-9f26-f16d2c4e90f6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486796761 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.486796761 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.4193515472 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 4626984056 ps |
| CPU time | 862.68 seconds |
| Started | Jul 31 08:31:52 PM PDT 24 |
| Finished | Jul 31 08:46:15 PM PDT 24 |
| Peak memory | 608868 kb |
| Host | smart-addd0c5b-a5d0-4ca4-bf38-f89162554562 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41935 15472 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.4193515472 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.4272687653 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 5858251442 ps |
| CPU time | 969.52 seconds |
| Started | Jul 31 08:32:19 PM PDT 24 |
| Finished | Jul 31 08:48:29 PM PDT 24 |
| Peak memory | 610096 kb |
| Host | smart-e18cdb2a-b6e9-49f9-9709-065ff43d70b5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=4272687653 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.4272687653 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.1065351362 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 4767491838 ps |
| CPU time | 666.48 seconds |
| Started | Jul 31 08:33:40 PM PDT 24 |
| Finished | Jul 31 08:44:47 PM PDT 24 |
| Peak memory | 621684 kb |
| Host | smart-83088e20-681a-450e-8386-3b85b8fe8420 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065351362 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.1065351362 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.2294664638 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 6808125656 ps |
| CPU time | 481.67 seconds |
| Started | Jul 31 08:36:34 PM PDT 24 |
| Finished | Jul 31 08:44:36 PM PDT 24 |
| Peak memory | 620276 kb |
| Host | smart-8d5f3d77-b1f5-4c3e-84ad-9638dcb42559 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294664638 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_wakeup.2294664638 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3055524859 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 5066585180 ps |
| CPU time | 493.95 seconds |
| Started | Jul 31 08:34:23 PM PDT 24 |
| Finished | Jul 31 08:42:37 PM PDT 24 |
| Peak memory | 620028 kb |
| Host | smart-8ba5ead6-e5ec-4d9b-bd31-332130011da6 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305552 4859 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3055524859 |
| Directory | /workspace/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.3654926586 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 2787836500 ps |
| CPU time | 215.51 seconds |
| Started | Jul 31 08:36:41 PM PDT 24 |
| Finished | Jul 31 08:40:16 PM PDT 24 |
| Peak memory | 608424 kb |
| Host | smart-6c21b585-9512-4451-8938-48121758d569 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654926586 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_rv_plic_smoketest.3654926586 |
| Directory | /workspace/2.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_irq.2198596573 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 3395902690 ps |
| CPU time | 325.69 seconds |
| Started | Jul 31 08:29:17 PM PDT 24 |
| Finished | Jul 31 08:34:43 PM PDT 24 |
| Peak memory | 609616 kb |
| Host | smart-f81e14aa-b548-4988-8e1c-fde1f48cd271 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198596573 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_irq.2198596573 |
| Directory | /workspace/2.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.307413469 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 2438411232 ps |
| CPU time | 237.87 seconds |
| Started | Jul 31 08:37:30 PM PDT 24 |
| Finished | Jul 31 08:41:28 PM PDT 24 |
| Peak memory | 609620 kb |
| Host | smart-adc4950a-874e-44b3-9a45-aa6b7bde3ac1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307413469 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_rv_timer_smoketest.307413469 |
| Directory | /workspace/2.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3170027247 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 8463725108 ps |
| CPU time | 992.33 seconds |
| Started | Jul 31 08:34:28 PM PDT 24 |
| Finished | Jul 31 08:51:00 PM PDT 24 |
| Peak memory | 610576 kb |
| Host | smart-040163f7-9614-49db-b9dd-7851f1ba6fa2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31700272 47 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.3170027247 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.210239278 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 2947695372 ps |
| CPU time | 251.12 seconds |
| Started | Jul 31 08:32:37 PM PDT 24 |
| Finished | Jul 31 08:36:48 PM PDT 24 |
| Peak memory | 609548 kb |
| Host | smart-0bc0abed-6add-4481-b3fa-f42cbb2f3907 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102392 78 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.210239278 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_retention.3597955300 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 3032577780 ps |
| CPU time | 353 seconds |
| Started | Jul 31 08:28:28 PM PDT 24 |
| Finished | Jul 31 08:34:22 PM PDT 24 |
| Peak memory | 610136 kb |
| Host | smart-8dee24f1-f08c-429d-b9e3-64cfd5d5e9e8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597955300 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_retention.3597955300 |
| Directory | /workspace/2.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.3024000698 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 9633163404 ps |
| CPU time | 1664.43 seconds |
| Started | Jul 31 08:28:03 PM PDT 24 |
| Finished | Jul 31 08:55:48 PM PDT 24 |
| Peak memory | 610748 kb |
| Host | smart-5ad2c08a-c940-4ba6-9606-be37661b71c8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024000698 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_sleep_pwm_pulses.3024000698 |
| Directory | /workspace/2.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.2059830649 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 6884689128 ps |
| CPU time | 625.4 seconds |
| Started | Jul 31 08:35:49 PM PDT 24 |
| Finished | Jul 31 08:46:14 PM PDT 24 |
| Peak memory | 610400 kb |
| Host | smart-90026632-30a2-40c0-a5fa-df6b93100dbd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059830649 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sl eep_sram_ret_contents_no_scramble.2059830649 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.3781530123 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 8530795832 ps |
| CPU time | 689 seconds |
| Started | Jul 31 08:34:28 PM PDT 24 |
| Finished | Jul 31 08:45:57 PM PDT 24 |
| Peak memory | 610380 kb |
| Host | smart-a5403e03-2ea1-4668-96d3-f2605385859e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781530123 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep _sram_ret_contents_scramble.3781530123 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through.2329369464 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 5980783389 ps |
| CPU time | 790.4 seconds |
| Started | Jul 31 08:28:38 PM PDT 24 |
| Finished | Jul 31 08:41:49 PM PDT 24 |
| Peak memory | 624756 kb |
| Host | smart-6b48498a-caa7-4e63-9755-987d8e083d1d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329369464 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through.2329369464 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.4025721925 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 4413329830 ps |
| CPU time | 708.71 seconds |
| Started | Jul 31 08:31:43 PM PDT 24 |
| Finished | Jul 31 08:43:33 PM PDT 24 |
| Peak memory | 624764 kb |
| Host | smart-5e716604-0ab3-4b62-b6b0-a88c75a5fc2a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025721925 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.4025721925 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.3624825305 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 3396982344 ps |
| CPU time | 285.52 seconds |
| Started | Jul 31 08:29:20 PM PDT 24 |
| Finished | Jul 31 08:34:06 PM PDT 24 |
| Peak memory | 617848 kb |
| Host | smart-54473a41-9cbb-477a-a36e-17a27211ee26 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624825305 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pinmux_sleep_retention.3624825305 |
| Directory | /workspace/2.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_tpm.678650524 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 3417106001 ps |
| CPU time | 436.66 seconds |
| Started | Jul 31 08:29:03 PM PDT 24 |
| Finished | Jul 31 08:36:20 PM PDT 24 |
| Peak memory | 618488 kb |
| Host | smart-c6db37c8-a9a6-42ea-b91e-1b5d24688b03 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678650524 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_tpm.678650524 |
| Directory | /workspace/2.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.2279361443 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 8595831557 ps |
| CPU time | 627.82 seconds |
| Started | Jul 31 08:32:29 PM PDT 24 |
| Finished | Jul 31 08:42:57 PM PDT 24 |
| Peak memory | 610632 kb |
| Host | smart-0d4bca6a-7a92-4fa4-8cad-d88f0acfc6fc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279361443 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.2279361443 |
| Directory | /workspace/2.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.2734297721 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 4813334508 ps |
| CPU time | 820.79 seconds |
| Started | Jul 31 08:33:26 PM PDT 24 |
| Finished | Jul 31 08:47:07 PM PDT 24 |
| Peak memory | 611152 kb |
| Host | smart-ad115a7d-a12e-4fa1-b386-a757bcfa304d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734297721 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _sram_ctrl_scrambled_access.2734297721 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.961443759 |
| Short name | T1358 |
| Test name | |
| Test status | |
| Simulation time | 4557219554 ps |
| CPU time | 493.28 seconds |
| Started | Jul 31 08:35:42 PM PDT 24 |
| Finished | Jul 31 08:43:55 PM PDT 24 |
| Peak memory | 610856 kb |
| Host | smart-7fa50d09-9793-4206-9045-aa217743aa51 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961443759 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.961443759 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.3371759201 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 3258060800 ps |
| CPU time | 228.97 seconds |
| Started | Jul 31 08:36:01 PM PDT 24 |
| Finished | Jul 31 08:39:50 PM PDT 24 |
| Peak memory | 609660 kb |
| Host | smart-d553833c-bf56-4dc4-9fd2-bec772606c03 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371759201 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_sram_ctrl_smoketest.3371759201 |
| Directory | /workspace/2.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3833539504 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 20536182268 ps |
| CPU time | 2776.4 seconds |
| Started | Jul 31 08:30:42 PM PDT 24 |
| Finished | Jul 31 09:16:59 PM PDT 24 |
| Peak memory | 610800 kb |
| Host | smart-10adff80-e0ce-47c3-9f70-73fef6640701 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833539504 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.3833539504 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.2076081178 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 4030306947 ps |
| CPU time | 681.66 seconds |
| Started | Jul 31 08:30:40 PM PDT 24 |
| Finished | Jul 31 08:42:04 PM PDT 24 |
| Peak memory | 613464 kb |
| Host | smart-3dedddb5-52fb-447c-a98a-ee1d7f88db09 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076081178 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_in_irq.2076081178 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.2104138896 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 3755456243 ps |
| CPU time | 401.41 seconds |
| Started | Jul 31 08:32:32 PM PDT 24 |
| Finished | Jul 31 08:39:16 PM PDT 24 |
| Peak memory | 613344 kb |
| Host | smart-2bba7bbd-ee3d-40fd-af50-0a2d33fda8bc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104138896 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_inputs.2104138896 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.1071907094 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 3321573160 ps |
| CPU time | 340.69 seconds |
| Started | Jul 31 08:29:45 PM PDT 24 |
| Finished | Jul 31 08:35:26 PM PDT 24 |
| Peak memory | 610032 kb |
| Host | smart-1d6ddaf9-d15c-4b55-9e00-a2526a8dea53 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071907094 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_outputs.1071907094 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.2477462067 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 23951403240 ps |
| CPU time | 1834.98 seconds |
| Started | Jul 31 08:31:36 PM PDT 24 |
| Finished | Jul 31 09:02:12 PM PDT 24 |
| Peak memory | 614840 kb |
| Host | smart-db61a6e2-db11-4049-a860-6d8a492ed55f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24774620 67 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.2477462067 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1100504440 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 6403917388 ps |
| CPU time | 454.25 seconds |
| Started | Jul 31 08:30:37 PM PDT 24 |
| Finished | Jul 31 08:38:11 PM PDT 24 |
| Peak memory | 610588 kb |
| Host | smart-12f9b55e-e6b6-4403-a45c-da51ad53fd19 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100504440 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1100504440 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.2974298626 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 4240938628 ps |
| CPU time | 521.2 seconds |
| Started | Jul 31 08:28:36 PM PDT 24 |
| Finished | Jul 31 08:37:18 PM PDT 24 |
| Peak memory | 623200 kb |
| Host | smart-04ac4149-bf5c-450e-a2a2-5cc43afa966e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2974298626 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.2974298626 |
| Directory | /workspace/2.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_smoketest.37198961 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 3079448520 ps |
| CPU time | 289.04 seconds |
| Started | Jul 31 08:35:30 PM PDT 24 |
| Finished | Jul 31 08:40:19 PM PDT 24 |
| Peak memory | 615000 kb |
| Host | smart-8e86d5ba-6e08-4f84-b366-243005d4b483 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37198961 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_uart_smoketest.37198961 |
| Directory | /workspace/2.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx.2040085943 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 3708135540 ps |
| CPU time | 815.68 seconds |
| Started | Jul 31 08:27:49 PM PDT 24 |
| Finished | Jul 31 08:41:25 PM PDT 24 |
| Peak memory | 623700 kb |
| Host | smart-c871430e-6d6e-4d23-b99a-6ffd34a164de |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040085943 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.2040085943 |
| Directory | /workspace/2.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1636282453 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 8463782426 ps |
| CPU time | 1580.33 seconds |
| Started | Jul 31 08:27:56 PM PDT 24 |
| Finished | Jul 31 08:54:17 PM PDT 24 |
| Peak memory | 624512 kb |
| Host | smart-8a37fd29-e9d3-4298-a950-bce33657f5f2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636282453 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq.1636282453 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4220378234 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 8497864378 ps |
| CPU time | 1290.93 seconds |
| Started | Jul 31 08:28:39 PM PDT 24 |
| Finished | Jul 31 08:50:11 PM PDT 24 |
| Peak memory | 619756 kb |
| Host | smart-bf39d0c2-eb81-401e-926a-85545deda140 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220378234 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.4220378234 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.3968995239 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 77888304360 ps |
| CPU time | 13995.1 seconds |
| Started | Jul 31 08:28:03 PM PDT 24 |
| Finished | Aug 01 12:21:20 AM PDT 24 |
| Peak memory | 635192 kb |
| Host | smart-a4aacd3c-3d0d-4674-ad95-2b83820cab09 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3968995239 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_bootstrap.3968995239 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.1877998986 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 4146032288 ps |
| CPU time | 635.89 seconds |
| Started | Jul 31 08:30:03 PM PDT 24 |
| Finished | Jul 31 08:40:40 PM PDT 24 |
| Peak memory | 623640 kb |
| Host | smart-e19c4e45-82ae-402e-a932-725a812f5a50 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877998986 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.1877998986 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.2325220929 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 4160215400 ps |
| CPU time | 675.72 seconds |
| Started | Jul 31 08:29:15 PM PDT 24 |
| Finished | Jul 31 08:40:31 PM PDT 24 |
| Peak memory | 623712 kb |
| Host | smart-8cd559e4-3339-451a-8964-9c240608b862 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325220929 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.2325220929 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_dev.4046352421 |
| Short name | T1349 |
| Test name | |
| Test status | |
| Simulation time | 2854124668 ps |
| CPU time | 202.23 seconds |
| Started | Jul 31 08:34:48 PM PDT 24 |
| Finished | Jul 31 08:38:10 PM PDT 24 |
| Peak memory | 623720 kb |
| Host | smart-4aa6392f-d0e5-4ef0-87ed-a8df816db0f7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4046352421 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.4046352421 |
| Directory | /workspace/2.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_prod.3966535275 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 2524558997 ps |
| CPU time | 182.86 seconds |
| Started | Jul 31 08:34:54 PM PDT 24 |
| Finished | Jul 31 08:37:58 PM PDT 24 |
| Peak memory | 623832 kb |
| Host | smart-a8e9a013-088a-4ee0-a08e-eb40f24d00a5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966535275 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.3966535275 |
| Directory | /workspace/2.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_rma.322176062 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 6316389372 ps |
| CPU time | 662.27 seconds |
| Started | Jul 31 08:33:21 PM PDT 24 |
| Finished | Jul 31 08:44:24 PM PDT 24 |
| Peak memory | 632792 kb |
| Host | smart-516821cb-5886-4977-b586-0df19d57f359 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322176062 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_rma.322176062 |
| Directory | /workspace/2.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_dev.1914251462 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 15761386003 ps |
| CPU time | 3610.02 seconds |
| Started | Jul 31 08:40:40 PM PDT 24 |
| Finished | Jul 31 09:40:51 PM PDT 24 |
| Peak memory | 610232 kb |
| Host | smart-333aace5-e450-45c1-9837-55d17ff40aa3 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914251462 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_dev.1914251462 |
| Directory | /workspace/2.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod.4240827979 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 15446157249 ps |
| CPU time | 3012.61 seconds |
| Started | Jul 31 08:40:50 PM PDT 24 |
| Finished | Jul 31 09:31:03 PM PDT 24 |
| Peak memory | 610296 kb |
| Host | smart-f87bfdf3-5ede-4080-8b09-02fa39d0493e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240827979 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_prod.4240827979 |
| Directory | /workspace/2.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.4006217074 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 15370650424 ps |
| CPU time | 3267.91 seconds |
| Started | Jul 31 08:39:40 PM PDT 24 |
| Finished | Jul 31 09:34:08 PM PDT 24 |
| Peak memory | 609996 kb |
| Host | smart-780f7ab5-f996-43b4-b35a-18c868b3507a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006217074 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.rom_e2e_asm_init_prod_end.4006217074 |
| Directory | /workspace/2.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_rma.2951380815 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 15195392963 ps |
| CPU time | 2902.53 seconds |
| Started | Jul 31 08:40:27 PM PDT 24 |
| Finished | Jul 31 09:28:50 PM PDT 24 |
| Peak memory | 610276 kb |
| Host | smart-245827f7-0a66-4b36-8fe2-88eb1f1e3c85 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951380815 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_rma.2951380815 |
| Directory | /workspace/2.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.4132587122 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 11308979381 ps |
| CPU time | 2883.56 seconds |
| Started | Jul 31 08:39:37 PM PDT 24 |
| Finished | Jul 31 09:27:41 PM PDT 24 |
| Peak memory | 610372 kb |
| Host | smart-1a434028-c0ed-4d2a-9f7b-8cf41797e2d7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132587122 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.rom_e2e_asm_init_test_unlocked0.4132587122 |
| Directory | /workspace/2.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.2918773804 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 14518408200 ps |
| CPU time | 3482.91 seconds |
| Started | Jul 31 08:39:13 PM PDT 24 |
| Finished | Jul 31 09:37:16 PM PDT 24 |
| Peak memory | 610244 kb |
| Host | smart-b84183f9-e14d-4009-a460-8668164e0c2a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918773804 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_in it_rom_ext_invalid_meas.2918773804 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.1160854828 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 15048055080 ps |
| CPU time | 3397.42 seconds |
| Started | Jul 31 08:40:33 PM PDT 24 |
| Finished | Jul 31 09:37:10 PM PDT 24 |
| Peak memory | 610096 kb |
| Host | smart-432082eb-545e-4abf-845b-69040ea3db4a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160854828 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_meas.1160854828 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.4235428798 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 15591441438 ps |
| CPU time | 3462.15 seconds |
| Started | Jul 31 08:39:04 PM PDT 24 |
| Finished | Jul 31 09:36:46 PM PDT 24 |
| Peak memory | 609916 kb |
| Host | smart-10b1d0d5-1f18-4c13-8a76-62730ce6f896 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235428798 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext _no_meas.4235428798 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_self_hash.3739405997 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 27340564242 ps |
| CPU time | 6159.67 seconds |
| Started | Jul 31 08:39:33 PM PDT 24 |
| Finished | Jul 31 10:22:14 PM PDT 24 |
| Peak memory | 610072 kb |
| Host | smart-1c19e628-dbcb-4947-8776-d1e34ba3212a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739405997 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_self_hash.3739405997 |
| Directory | /workspace/2.rom_e2e_self_hash/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.1174193887 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 13963633893 ps |
| CPU time | 3910.62 seconds |
| Started | Jul 31 08:38:56 PM PDT 24 |
| Finished | Jul 31 09:44:07 PM PDT 24 |
| Peak memory | 610664 kb |
| Host | smart-b6751f2b-303f-4774-855d-178849c99677 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174193887 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_ shutdown_exception_c.1174193887 |
| Directory | /workspace/2.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_output.679709769 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 30895568885 ps |
| CPU time | 3029.76 seconds |
| Started | Jul 31 08:40:20 PM PDT 24 |
| Finished | Jul 31 09:30:50 PM PDT 24 |
| Peak memory | 611480 kb |
| Host | smart-348eee96-9bc4-4cbb-949b-1faf1fc0d9fd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679709769 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_output.679709769 |
| Directory | /workspace/2.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_smoke.4086114847 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 14571826152 ps |
| CPU time | 2920.08 seconds |
| Started | Jul 31 08:39:48 PM PDT 24 |
| Finished | Jul 31 09:28:29 PM PDT 24 |
| Peak memory | 610080 kb |
| Host | smart-a14ce1bf-a977-4986-b673-0917bdc3aab9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=4086114847 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.4086114847 |
| Directory | /workspace/2.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_static_critical.4113416531 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 16559387944 ps |
| CPU time | 4813.1 seconds |
| Started | Jul 31 08:41:03 PM PDT 24 |
| Finished | Jul 31 10:01:18 PM PDT 24 |
| Peak memory | 610144 kb |
| Host | smart-e04f7620-683e-469c-ba88-2867930c17bf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113416531 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_static_critical.4113416531 |
| Directory | /workspace/2.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/2.rom_keymgr_functest.3256492093 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 4790125500 ps |
| CPU time | 673.22 seconds |
| Started | Jul 31 08:37:15 PM PDT 24 |
| Finished | Jul 31 08:48:29 PM PDT 24 |
| Peak memory | 609396 kb |
| Host | smart-bde67eac-9638-48e3-830b-f2b31a1788db |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256492093 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.rom_keymgr_functest.3256492093 |
| Directory | /workspace/2.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/2.rom_raw_unlock.1250734957 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 6303828991 ps |
| CPU time | 346.52 seconds |
| Started | Jul 31 08:36:00 PM PDT 24 |
| Finished | Jul 31 08:41:47 PM PDT 24 |
| Peak memory | 619848 kb |
| Host | smart-96c87249-ca19-4873-8cc1-424062f8fe9c |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1250734957 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_raw_unlock.1250734957 |
| Directory | /workspace/2.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.rom_volatile_raw_unlock.260782962 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 1923157461 ps |
| CPU time | 122.23 seconds |
| Started | Jul 31 08:36:53 PM PDT 24 |
| Finished | Jul 31 08:38:56 PM PDT 24 |
| Peak memory | 616900 kb |
| Host | smart-f18b5fd1-c387-4565-a483-d3631641dc38 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260782962 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.260782962 |
| Directory | /workspace/2.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/21.chip_sw_all_escalation_resets.3029948548 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 5025856200 ps |
| CPU time | 479.53 seconds |
| Started | Jul 31 08:41:58 PM PDT 24 |
| Finished | Jul 31 08:49:58 PM PDT 24 |
| Peak memory | 650308 kb |
| Host | smart-b01fad82-7ac7-4497-9045-b30753d5f16f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3029948548 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.3029948548 |
| Directory | /workspace/21.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/22.chip_sw_all_escalation_resets.1342855229 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 4769006604 ps |
| CPU time | 480.12 seconds |
| Started | Jul 31 08:42:19 PM PDT 24 |
| Finished | Jul 31 08:50:19 PM PDT 24 |
| Peak memory | 650276 kb |
| Host | smart-2283c267-9030-4e06-a84d-493bb84b67c0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1342855229 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.1342855229 |
| Directory | /workspace/22.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.561070750 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 4151765108 ps |
| CPU time | 418.2 seconds |
| Started | Jul 31 08:43:33 PM PDT 24 |
| Finished | Jul 31 08:50:31 PM PDT 24 |
| Peak memory | 618736 kb |
| Host | smart-d93cff65-4df0-42e2-9dfa-07957b066453 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561070750 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_s w_alert_handler_lpg_sleep_mode_alerts.561070750 |
| Directory | /workspace/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.502140653 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 3675658480 ps |
| CPU time | 374.11 seconds |
| Started | Jul 31 08:43:39 PM PDT 24 |
| Finished | Jul 31 08:49:53 PM PDT 24 |
| Peak memory | 649672 kb |
| Host | smart-8c85fb49-c756-4449-9eb8-46190129dadf |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502140653 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_s w_alert_handler_lpg_sleep_mode_alerts.502140653 |
| Directory | /workspace/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2981926629 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 3421006328 ps |
| CPU time | 440.74 seconds |
| Started | Jul 31 08:42:12 PM PDT 24 |
| Finished | Jul 31 08:49:33 PM PDT 24 |
| Peak memory | 648772 kb |
| Host | smart-1541e2f7-9505-4b44-9777-7a2b2dc5b612 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981926629 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2981926629 |
| Directory | /workspace/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3543855737 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 8090769600 ps |
| CPU time | 596.85 seconds |
| Started | Jul 31 08:36:06 PM PDT 24 |
| Finished | Jul 31 08:46:04 PM PDT 24 |
| Peak memory | 610644 kb |
| Host | smart-f7fdc7dc-2a9d-4c61-82b2-5a416d493de0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3543855737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3543855737 |
| Directory | /workspace/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.2546814246 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 20690251310 ps |
| CPU time | 4902.11 seconds |
| Started | Jul 31 08:38:12 PM PDT 24 |
| Finished | Jul 31 09:59:56 PM PDT 24 |
| Peak memory | 610080 kb |
| Host | smart-44a89d52-5f51-41c6-b0d7-79233323311b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546814246 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 3.chip_sw_csrng_edn_concurrency.2546814246 |
| Directory | /workspace/3.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/3.chip_sw_data_integrity_escalation.757247821 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 6644186270 ps |
| CPU time | 1015.63 seconds |
| Started | Jul 31 08:36:12 PM PDT 24 |
| Finished | Jul 31 08:53:08 PM PDT 24 |
| Peak memory | 611108 kb |
| Host | smart-6a3930bd-af57-4a0c-805d-bc3ad5226d31 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=757247821 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.757247821 |
| Directory | /workspace/3.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.2026676754 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 12567796282 ps |
| CPU time | 973.53 seconds |
| Started | Jul 31 08:37:49 PM PDT 24 |
| Finished | Jul 31 08:54:03 PM PDT 24 |
| Peak memory | 620412 kb |
| Host | smart-e2e1b1ed-7666-4d70-ac1d-1d4dcd104a68 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026676754 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 3.chip_sw_lc_ctrl_transition.2026676754 |
| Directory | /workspace/3.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1773514402 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 5863175170 ps |
| CPU time | 751.72 seconds |
| Started | Jul 31 08:36:24 PM PDT 24 |
| Finished | Jul 31 08:48:56 PM PDT 24 |
| Peak memory | 610564 kb |
| Host | smart-bdd08933-8d41-4e36-abff-d769f826d0f1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17735144 02 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.1773514402 |
| Directory | /workspace/3.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.2980937016 |
| Short name | T1383 |
| Test name | |
| Test status | |
| Simulation time | 13686674016 ps |
| CPU time | 2241.54 seconds |
| Started | Jul 31 08:37:54 PM PDT 24 |
| Finished | Jul 31 09:15:16 PM PDT 24 |
| Peak memory | 624488 kb |
| Host | smart-102d9623-c3c3-4402-99a3-5cf9cb97db31 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2980937016 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.2980937016 |
| Directory | /workspace/3.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx.1954097813 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 3891696550 ps |
| CPU time | 590.07 seconds |
| Started | Jul 31 08:35:32 PM PDT 24 |
| Finished | Jul 31 08:45:22 PM PDT 24 |
| Peak memory | 623948 kb |
| Host | smart-7a05362a-b0d1-4e4e-a2d2-83cf60023dbc |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954097813 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.1954097813 |
| Directory | /workspace/3.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3403818690 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 4509581055 ps |
| CPU time | 492.6 seconds |
| Started | Jul 31 08:36:33 PM PDT 24 |
| Finished | Jul 31 08:44:46 PM PDT 24 |
| Peak memory | 623308 kb |
| Host | smart-604b5846-4cd6-47da-990b-014961b9257b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403818690 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq.3403818690 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.481103516 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 4812178174 ps |
| CPU time | 573.03 seconds |
| Started | Jul 31 08:37:52 PM PDT 24 |
| Finished | Jul 31 08:47:25 PM PDT 24 |
| Peak memory | 624160 kb |
| Host | smart-393a9d20-7ed5-450d-9326-fd143709580a |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481103516 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.481103516 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2930505844 |
| Short name | T1350 |
| Test name | |
| Test status | |
| Simulation time | 4459760900 ps |
| CPU time | 694.18 seconds |
| Started | Jul 31 08:38:53 PM PDT 24 |
| Finished | Jul 31 08:50:28 PM PDT 24 |
| Peak memory | 623948 kb |
| Host | smart-2c400855-eb25-45a2-baa5-7a8d812bd8b0 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930505844 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.2930505844 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.1980231882 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 3797029604 ps |
| CPU time | 596.43 seconds |
| Started | Jul 31 08:39:31 PM PDT 24 |
| Finished | Jul 31 08:49:28 PM PDT 24 |
| Peak memory | 623904 kb |
| Host | smart-e9c7f3ba-5a3a-4138-ae88-f243c4924e34 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980231882 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.1980231882 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_dev.1674209211 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 18455049113 ps |
| CPU time | 1789.64 seconds |
| Started | Jul 31 08:36:03 PM PDT 24 |
| Finished | Jul 31 09:05:53 PM PDT 24 |
| Peak memory | 624592 kb |
| Host | smart-dc3984bc-cf26-4ff7-aef7-f7c7171894a5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1674209211 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.1674209211 |
| Directory | /workspace/3.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_prod.3504111267 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 2701064153 ps |
| CPU time | 164.34 seconds |
| Started | Jul 31 08:37:55 PM PDT 24 |
| Finished | Jul 31 08:40:39 PM PDT 24 |
| Peak memory | 623360 kb |
| Host | smart-59d8b56d-3ae3-49bb-9373-abb1f90f3ee0 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504111267 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.3504111267 |
| Directory | /workspace/3.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/30.chip_sw_all_escalation_resets.745054143 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 4477650522 ps |
| CPU time | 598.3 seconds |
| Started | Jul 31 08:41:42 PM PDT 24 |
| Finished | Jul 31 08:51:41 PM PDT 24 |
| Peak memory | 650232 kb |
| Host | smart-bb430ebc-2daa-4d06-861f-67b80048cd47 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 745054143 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.745054143 |
| Directory | /workspace/30.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/31.chip_sw_all_escalation_resets.3473643844 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 6162395860 ps |
| CPU time | 736.82 seconds |
| Started | Jul 31 08:42:50 PM PDT 24 |
| Finished | Jul 31 08:55:08 PM PDT 24 |
| Peak memory | 649844 kb |
| Host | smart-7e947f17-6ddd-4271-a728-55320d735858 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3473643844 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_all_escalation_resets.3473643844 |
| Directory | /workspace/31.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1238172409 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 3980903904 ps |
| CPU time | 402.4 seconds |
| Started | Jul 31 08:44:08 PM PDT 24 |
| Finished | Jul 31 08:50:51 PM PDT 24 |
| Peak memory | 649040 kb |
| Host | smart-976d81bb-e170-45ba-a633-47474647f111 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238172409 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1238172409 |
| Directory | /workspace/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/32.chip_sw_all_escalation_resets.3064770435 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 5392761232 ps |
| CPU time | 681.27 seconds |
| Started | Jul 31 08:42:26 PM PDT 24 |
| Finished | Jul 31 08:53:48 PM PDT 24 |
| Peak memory | 650616 kb |
| Host | smart-e2a8ccf3-628f-40b0-91b6-f8d6cb142e4c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3064770435 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_all_escalation_resets.3064770435 |
| Directory | /workspace/32.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.95144779 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 4412406112 ps |
| CPU time | 499.78 seconds |
| Started | Jul 31 08:44:20 PM PDT 24 |
| Finished | Jul 31 08:52:40 PM PDT 24 |
| Peak memory | 649464 kb |
| Host | smart-e5afbc25-4f6a-45a5-8432-2ef86e22ca37 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95144779 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw _alert_handler_lpg_sleep_mode_alerts.95144779 |
| Directory | /workspace/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/34.chip_sw_all_escalation_resets.2859420497 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 4631946066 ps |
| CPU time | 702.69 seconds |
| Started | Jul 31 08:42:56 PM PDT 24 |
| Finished | Jul 31 08:54:39 PM PDT 24 |
| Peak memory | 650180 kb |
| Host | smart-ea319b3d-381c-486d-91c1-2108f7078a35 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2859420497 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.2859420497 |
| Directory | /workspace/34.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2248105388 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 4063191944 ps |
| CPU time | 340.19 seconds |
| Started | Jul 31 08:43:43 PM PDT 24 |
| Finished | Jul 31 08:49:23 PM PDT 24 |
| Peak memory | 649096 kb |
| Host | smart-e74ee063-18cd-423f-ae22-caa5d2ed7ad9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248105388 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2248105388 |
| Directory | /workspace/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/36.chip_sw_all_escalation_resets.83941260 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 6214950640 ps |
| CPU time | 606.43 seconds |
| Started | Jul 31 08:41:47 PM PDT 24 |
| Finished | Jul 31 08:51:54 PM PDT 24 |
| Peak memory | 619884 kb |
| Host | smart-0c048c50-8dbb-4fb7-b519-88eb6294ad27 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 83941260 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.83941260 |
| Directory | /workspace/36.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/37.chip_sw_all_escalation_resets.2217868385 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 4341230638 ps |
| CPU time | 593.01 seconds |
| Started | Jul 31 08:43:56 PM PDT 24 |
| Finished | Jul 31 08:53:49 PM PDT 24 |
| Peak memory | 650180 kb |
| Host | smart-c8e63f51-3b38-4b60-aa4e-261c8380d44b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2217868385 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.2217868385 |
| Directory | /workspace/37.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.906695063 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 3077700320 ps |
| CPU time | 365 seconds |
| Started | Jul 31 08:41:08 PM PDT 24 |
| Finished | Jul 31 08:47:13 PM PDT 24 |
| Peak memory | 648776 kb |
| Host | smart-92b71150-aa95-48c5-8fd2-e3c7e7fe6a41 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906695063 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_s w_alert_handler_lpg_sleep_mode_alerts.906695063 |
| Directory | /workspace/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/38.chip_sw_all_escalation_resets.4080337605 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 5622923576 ps |
| CPU time | 552.83 seconds |
| Started | Jul 31 08:42:32 PM PDT 24 |
| Finished | Jul 31 08:51:45 PM PDT 24 |
| Peak memory | 650324 kb |
| Host | smart-a3f7c5ba-168a-4592-a4b9-fc5cb8d4c83b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4080337605 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.4080337605 |
| Directory | /workspace/38.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/39.chip_sw_all_escalation_resets.3822976889 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 4812088954 ps |
| CPU time | 570.35 seconds |
| Started | Jul 31 08:42:05 PM PDT 24 |
| Finished | Jul 31 08:51:35 PM PDT 24 |
| Peak memory | 649964 kb |
| Host | smart-dd6b0f26-062e-4d5d-9705-f586f90f6705 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3822976889 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.3822976889 |
| Directory | /workspace/39.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.138191705 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 4410973560 ps |
| CPU time | 378.39 seconds |
| Started | Jul 31 08:39:46 PM PDT 24 |
| Finished | Jul 31 08:46:05 PM PDT 24 |
| Peak memory | 649136 kb |
| Host | smart-d0ed1742-5ea4-4ee0-b87a-b0874e6e4499 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138191705 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw _alert_handler_lpg_sleep_mode_alerts.138191705 |
| Directory | /workspace/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2510518878 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 6642866760 ps |
| CPU time | 386.04 seconds |
| Started | Jul 31 08:37:40 PM PDT 24 |
| Finished | Jul 31 08:44:07 PM PDT 24 |
| Peak memory | 610600 kb |
| Host | smart-2fcfa286-3ded-466f-9ca0-f79d08b7744e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2510518878 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2510518878 |
| Directory | /workspace/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.3059480888 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 17627131640 ps |
| CPU time | 3784.22 seconds |
| Started | Jul 31 08:38:03 PM PDT 24 |
| Finished | Jul 31 09:41:08 PM PDT 24 |
| Peak memory | 610416 kb |
| Host | smart-d5b0f278-b890-4da0-9baa-75035312ed29 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059480888 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 4.chip_sw_csrng_edn_concurrency.3059480888 |
| Directory | /workspace/4.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/4.chip_sw_data_integrity_escalation.2327024296 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 5383095112 ps |
| CPU time | 734.53 seconds |
| Started | Jul 31 08:37:15 PM PDT 24 |
| Finished | Jul 31 08:49:30 PM PDT 24 |
| Peak memory | 610728 kb |
| Host | smart-76216ccb-ddd2-4042-8851-29ee0cb2db56 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2327024296 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.2327024296 |
| Directory | /workspace/4.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.4277473240 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 10831685745 ps |
| CPU time | 795.13 seconds |
| Started | Jul 31 08:39:19 PM PDT 24 |
| Finished | Jul 31 08:52:35 PM PDT 24 |
| Peak memory | 620408 kb |
| Host | smart-c5d4d210-c080-40a8-a967-12c2aced1cf1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277473240 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 4.chip_sw_lc_ctrl_transition.4277473240 |
| Directory | /workspace/4.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.1119502384 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 8668999316 ps |
| CPU time | 1039 seconds |
| Started | Jul 31 08:39:36 PM PDT 24 |
| Finished | Jul 31 08:56:55 PM PDT 24 |
| Peak memory | 610568 kb |
| Host | smart-39c4dea2-3404-403f-b37c-81b7cac24eeb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11195023 84 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.1119502384 |
| Directory | /workspace/4.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.3013315819 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 4536471016 ps |
| CPU time | 759.39 seconds |
| Started | Jul 31 08:37:24 PM PDT 24 |
| Finished | Jul 31 08:50:04 PM PDT 24 |
| Peak memory | 624496 kb |
| Host | smart-d6d0f15f-d492-4897-bedb-87ed83003854 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3013315819 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.3013315819 |
| Directory | /workspace/4.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx.4062554304 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 4231737644 ps |
| CPU time | 665.64 seconds |
| Started | Jul 31 08:36:17 PM PDT 24 |
| Finished | Jul 31 08:47:23 PM PDT 24 |
| Peak memory | 623700 kb |
| Host | smart-c2f327c9-cc5f-4171-93c0-3f67097a960c |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062554304 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.4062554304 |
| Directory | /workspace/4.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3251038420 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 3882827569 ps |
| CPU time | 569.17 seconds |
| Started | Jul 31 08:38:00 PM PDT 24 |
| Finished | Jul 31 08:47:31 PM PDT 24 |
| Peak memory | 624548 kb |
| Host | smart-7c32206e-a6ed-433c-967e-fc9355183b15 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251038420 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq.3251038420 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3638323590 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 13439768153 ps |
| CPU time | 1367.36 seconds |
| Started | Jul 31 08:37:11 PM PDT 24 |
| Finished | Jul 31 08:59:59 PM PDT 24 |
| Peak memory | 624488 kb |
| Host | smart-762bd4c8-4082-4c72-a01e-b1a598e50566 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638323590 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.3638323590 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.1863519091 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 4740927920 ps |
| CPU time | 655.15 seconds |
| Started | Jul 31 08:38:17 PM PDT 24 |
| Finished | Jul 31 08:49:13 PM PDT 24 |
| Peak memory | 624216 kb |
| Host | smart-4ec17f06-181b-45ff-93cf-28f0cdcaa033 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863519091 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.1863519091 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.2027603808 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 4596768958 ps |
| CPU time | 719.19 seconds |
| Started | Jul 31 08:38:44 PM PDT 24 |
| Finished | Jul 31 08:50:43 PM PDT 24 |
| Peak memory | 623956 kb |
| Host | smart-43b12e3f-725f-4e0c-8706-c02d6a2b597a |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027603808 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.2027603808 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1372127813 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 4022108110 ps |
| CPU time | 644.75 seconds |
| Started | Jul 31 08:37:59 PM PDT 24 |
| Finished | Jul 31 08:48:45 PM PDT 24 |
| Peak memory | 623680 kb |
| Host | smart-5facad4c-e483-4fbf-9e31-478e88fff452 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372127813 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.1372127813 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_dev.3168420591 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 4043782806 ps |
| CPU time | 221.54 seconds |
| Started | Jul 31 08:37:21 PM PDT 24 |
| Finished | Jul 31 08:41:02 PM PDT 24 |
| Peak memory | 624272 kb |
| Host | smart-5eda02a7-5ef7-489f-b3c5-32da79b7ae9a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3168420591 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.3168420591 |
| Directory | /workspace/4.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_prod.1976982765 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 2934699110 ps |
| CPU time | 180.79 seconds |
| Started | Jul 31 08:37:04 PM PDT 24 |
| Finished | Jul 31 08:40:04 PM PDT 24 |
| Peak memory | 624468 kb |
| Host | smart-028feb92-b228-4283-a535-ab56fd49f483 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976982765 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.1976982765 |
| Directory | /workspace/4.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_testunlock0.2717972162 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 6041040885 ps |
| CPU time | 653.06 seconds |
| Started | Jul 31 08:37:32 PM PDT 24 |
| Finished | Jul 31 08:48:25 PM PDT 24 |
| Peak memory | 624908 kb |
| Host | smart-142a176a-829a-4956-8b7d-59b80304a862 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2717972162 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_testunlock0.2717972162 |
| Directory | /workspace/4.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.825946438 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 4452658588 ps |
| CPU time | 387.68 seconds |
| Started | Jul 31 08:44:56 PM PDT 24 |
| Finished | Jul 31 08:51:24 PM PDT 24 |
| Peak memory | 649396 kb |
| Host | smart-ecf7b7c8-0e16-45fe-9982-efeab9777119 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825946438 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_s w_alert_handler_lpg_sleep_mode_alerts.825946438 |
| Directory | /workspace/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/40.chip_sw_all_escalation_resets.3478128520 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 4931702024 ps |
| CPU time | 627.85 seconds |
| Started | Jul 31 08:44:14 PM PDT 24 |
| Finished | Jul 31 08:54:42 PM PDT 24 |
| Peak memory | 650148 kb |
| Host | smart-7e073895-4fc4-44b3-817f-e16ab5bf922f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3478128520 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.3478128520 |
| Directory | /workspace/40.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1867176741 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 3809369248 ps |
| CPU time | 403.31 seconds |
| Started | Jul 31 08:41:54 PM PDT 24 |
| Finished | Jul 31 08:48:38 PM PDT 24 |
| Peak memory | 648704 kb |
| Host | smart-eb6922f3-2bb1-4e70-b6a0-9f1c9fd958c4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867176741 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1867176741 |
| Directory | /workspace/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3689095752 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 3938521120 ps |
| CPU time | 349.86 seconds |
| Started | Jul 31 08:43:01 PM PDT 24 |
| Finished | Jul 31 08:48:51 PM PDT 24 |
| Peak memory | 649216 kb |
| Host | smart-ea473d50-b8cb-46ba-917e-a8535d71404c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689095752 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3689095752 |
| Directory | /workspace/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2927499801 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 4186141152 ps |
| CPU time | 421.02 seconds |
| Started | Jul 31 08:43:08 PM PDT 24 |
| Finished | Jul 31 08:50:09 PM PDT 24 |
| Peak memory | 648888 kb |
| Host | smart-f9bab54c-4ae2-41fb-b949-f52584dba169 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927499801 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2927499801 |
| Directory | /workspace/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/43.chip_sw_all_escalation_resets.3169871057 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 4564097690 ps |
| CPU time | 604.13 seconds |
| Started | Jul 31 08:42:41 PM PDT 24 |
| Finished | Jul 31 08:52:45 PM PDT 24 |
| Peak memory | 650388 kb |
| Host | smart-3eeced55-02dc-4836-a127-a0248ab6b7e4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3169871057 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.3169871057 |
| Directory | /workspace/43.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.599548293 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 3972051344 ps |
| CPU time | 342.27 seconds |
| Started | Jul 31 08:45:03 PM PDT 24 |
| Finished | Jul 31 08:50:45 PM PDT 24 |
| Peak memory | 649080 kb |
| Host | smart-1941fb33-8485-4afd-9168-b9dc4ef97334 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599548293 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_s w_alert_handler_lpg_sleep_mode_alerts.599548293 |
| Directory | /workspace/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/45.chip_sw_all_escalation_resets.3164371461 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 5513230880 ps |
| CPU time | 734.75 seconds |
| Started | Jul 31 08:42:12 PM PDT 24 |
| Finished | Jul 31 08:54:27 PM PDT 24 |
| Peak memory | 650640 kb |
| Host | smart-e8547984-1b7e-4df0-8b15-3692ec757735 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3164371461 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.3164371461 |
| Directory | /workspace/45.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2858792245 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 3765910088 ps |
| CPU time | 383.55 seconds |
| Started | Jul 31 08:43:29 PM PDT 24 |
| Finished | Jul 31 08:49:53 PM PDT 24 |
| Peak memory | 649392 kb |
| Host | smart-11249e76-8d7a-42f4-8351-f3774a6ee856 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858792245 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2858792245 |
| Directory | /workspace/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/46.chip_sw_all_escalation_resets.2145132658 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 4291970934 ps |
| CPU time | 552 seconds |
| Started | Jul 31 08:42:51 PM PDT 24 |
| Finished | Jul 31 08:52:03 PM PDT 24 |
| Peak memory | 650056 kb |
| Host | smart-21f9cf2e-b4ce-4563-9a0a-6ebb421323cf |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2145132658 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_all_escalation_resets.2145132658 |
| Directory | /workspace/46.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.944560690 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 4261357776 ps |
| CPU time | 471.36 seconds |
| Started | Jul 31 08:43:14 PM PDT 24 |
| Finished | Jul 31 08:51:05 PM PDT 24 |
| Peak memory | 649356 kb |
| Host | smart-1cda8313-f644-403f-9ba0-8ed420d83a87 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944560690 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_s w_alert_handler_lpg_sleep_mode_alerts.944560690 |
| Directory | /workspace/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1105739412 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 3921618284 ps |
| CPU time | 595.95 seconds |
| Started | Jul 31 08:43:21 PM PDT 24 |
| Finished | Jul 31 08:53:17 PM PDT 24 |
| Peak memory | 649248 kb |
| Host | smart-82d1c28d-04fe-4771-bc4c-81a58381424f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105739412 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1105739412 |
| Directory | /workspace/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/49.chip_sw_all_escalation_resets.3369236669 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 4312273744 ps |
| CPU time | 752.45 seconds |
| Started | Jul 31 08:44:08 PM PDT 24 |
| Finished | Jul 31 08:56:41 PM PDT 24 |
| Peak memory | 619688 kb |
| Host | smart-90a0b1f5-2130-4b7f-b33f-81ee79527845 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3369236669 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.3369236669 |
| Directory | /workspace/49.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.753999878 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 3576987004 ps |
| CPU time | 370.73 seconds |
| Started | Jul 31 08:37:32 PM PDT 24 |
| Finished | Jul 31 08:43:43 PM PDT 24 |
| Peak memory | 649036 kb |
| Host | smart-282524cb-5a76-4ed3-8ed1-0bce8d3ddd98 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753999878 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw _alert_handler_lpg_sleep_mode_alerts.753999878 |
| Directory | /workspace/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.477503748 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 17457623016 ps |
| CPU time | 3712.63 seconds |
| Started | Jul 31 08:38:26 PM PDT 24 |
| Finished | Jul 31 09:40:19 PM PDT 24 |
| Peak memory | 610480 kb |
| Host | smart-15929fae-0078-4d4d-a6f9-de9fcd8cf801 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477503748 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_csrng_edn_concurrency.477503748 |
| Directory | /workspace/5.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/5.chip_sw_data_integrity_escalation.3023686840 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 5876805156 ps |
| CPU time | 686.49 seconds |
| Started | Jul 31 08:40:15 PM PDT 24 |
| Finished | Jul 31 08:51:42 PM PDT 24 |
| Peak memory | 611060 kb |
| Host | smart-b776f3f4-9520-4f4c-8016-b93e9ce56d73 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3023686840 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.3023686840 |
| Directory | /workspace/5.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1208718472 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 9029589313 ps |
| CPU time | 817.27 seconds |
| Started | Jul 31 08:39:19 PM PDT 24 |
| Finished | Jul 31 08:52:57 PM PDT 24 |
| Peak memory | 620836 kb |
| Host | smart-f87abe13-07f6-40a3-88e7-d210b905dd1f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208718472 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 5.chip_sw_lc_ctrl_transition.1208718472 |
| Directory | /workspace/5.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3511060355 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 13241600676 ps |
| CPU time | 2164.26 seconds |
| Started | Jul 31 08:38:14 PM PDT 24 |
| Finished | Jul 31 09:14:18 PM PDT 24 |
| Peak memory | 624456 kb |
| Host | smart-b5174693-e665-458d-b4b4-b2eb58785a83 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3511060355 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.3511060355 |
| Directory | /workspace/5.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3777796749 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 3654521480 ps |
| CPU time | 556.08 seconds |
| Started | Jul 31 08:42:37 PM PDT 24 |
| Finished | Jul 31 08:51:54 PM PDT 24 |
| Peak memory | 648784 kb |
| Host | smart-71468c54-5188-4970-bdb3-45ed8529ec5b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777796749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3777796749 |
| Directory | /workspace/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/50.chip_sw_all_escalation_resets.4084246373 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 5304602026 ps |
| CPU time | 687.36 seconds |
| Started | Jul 31 08:42:36 PM PDT 24 |
| Finished | Jul 31 08:54:04 PM PDT 24 |
| Peak memory | 650220 kb |
| Host | smart-c7483057-4cf9-4b01-97ca-8867c7c1df51 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4084246373 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.4084246373 |
| Directory | /workspace/50.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2954691970 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 3640920442 ps |
| CPU time | 412.7 seconds |
| Started | Jul 31 08:43:04 PM PDT 24 |
| Finished | Jul 31 08:49:56 PM PDT 24 |
| Peak memory | 649128 kb |
| Host | smart-85a44978-f6a7-468d-89ce-51d18cc34ebb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954691970 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2954691970 |
| Directory | /workspace/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/52.chip_sw_all_escalation_resets.4151196059 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 4916243704 ps |
| CPU time | 595.83 seconds |
| Started | Jul 31 08:46:02 PM PDT 24 |
| Finished | Jul 31 08:55:58 PM PDT 24 |
| Peak memory | 650216 kb |
| Host | smart-c144b602-3fe6-40fd-875f-7e8d8d413b02 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4151196059 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.4151196059 |
| Directory | /workspace/52.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.620666174 |
| Short name | T1346 |
| Test name | |
| Test status | |
| Simulation time | 4222906476 ps |
| CPU time | 382.77 seconds |
| Started | Jul 31 08:42:48 PM PDT 24 |
| Finished | Jul 31 08:49:11 PM PDT 24 |
| Peak memory | 649104 kb |
| Host | smart-9743e389-3f80-4336-a96c-8b31bb4265de |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620666174 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_s w_alert_handler_lpg_sleep_mode_alerts.620666174 |
| Directory | /workspace/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/53.chip_sw_all_escalation_resets.3102336739 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 4371120904 ps |
| CPU time | 609.32 seconds |
| Started | Jul 31 08:44:43 PM PDT 24 |
| Finished | Jul 31 08:54:53 PM PDT 24 |
| Peak memory | 650228 kb |
| Host | smart-94036d42-0105-49b9-b180-1e298969a2ed |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3102336739 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.3102336739 |
| Directory | /workspace/53.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3172609701 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 3550771754 ps |
| CPU time | 497.44 seconds |
| Started | Jul 31 08:46:23 PM PDT 24 |
| Finished | Jul 31 08:54:41 PM PDT 24 |
| Peak memory | 649036 kb |
| Host | smart-f943b425-0401-4598-a6dc-c88a132349ce |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172609701 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3172609701 |
| Directory | /workspace/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.212996985 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 3772141310 ps |
| CPU time | 429.59 seconds |
| Started | Jul 31 08:43:07 PM PDT 24 |
| Finished | Jul 31 08:50:16 PM PDT 24 |
| Peak memory | 649268 kb |
| Host | smart-1233ac4f-274e-498c-8182-96784ff39a8e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212996985 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_s w_alert_handler_lpg_sleep_mode_alerts.212996985 |
| Directory | /workspace/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3850578288 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 3663393400 ps |
| CPU time | 370.75 seconds |
| Started | Jul 31 08:45:56 PM PDT 24 |
| Finished | Jul 31 08:52:07 PM PDT 24 |
| Peak memory | 649044 kb |
| Host | smart-d6c98c2d-0a35-40aa-b3f4-5fac7d530b22 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850578288 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3850578288 |
| Directory | /workspace/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/58.chip_sw_all_escalation_resets.1270464150 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 5971080760 ps |
| CPU time | 560.36 seconds |
| Started | Jul 31 08:42:28 PM PDT 24 |
| Finished | Jul 31 08:51:49 PM PDT 24 |
| Peak memory | 650336 kb |
| Host | smart-bb6133c2-a3af-46ad-8a9f-066ee4961c50 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1270464150 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.1270464150 |
| Directory | /workspace/58.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2933191101 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 3942560342 ps |
| CPU time | 354.41 seconds |
| Started | Jul 31 08:42:54 PM PDT 24 |
| Finished | Jul 31 08:48:49 PM PDT 24 |
| Peak memory | 649200 kb |
| Host | smart-2a13c609-437a-496e-b478-5ef519e7b121 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933191101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2933191101 |
| Directory | /workspace/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/6.chip_sw_all_escalation_resets.2432957315 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 5775306064 ps |
| CPU time | 818.07 seconds |
| Started | Jul 31 08:38:05 PM PDT 24 |
| Finished | Jul 31 08:51:44 PM PDT 24 |
| Peak memory | 649864 kb |
| Host | smart-2d85d2bf-9e52-40a4-862c-0675a725b181 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2432957315 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.2432957315 |
| Directory | /workspace/6.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.1963474907 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 13549701548 ps |
| CPU time | 2860.49 seconds |
| Started | Jul 31 08:42:49 PM PDT 24 |
| Finished | Jul 31 09:30:31 PM PDT 24 |
| Peak memory | 609436 kb |
| Host | smart-78023516-9675-47cc-8a94-596cfad8f1b3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963474907 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 6.chip_sw_csrng_edn_concurrency.1963474907 |
| Directory | /workspace/6.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.227306218 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 12719615560 ps |
| CPU time | 1107.65 seconds |
| Started | Jul 31 08:38:19 PM PDT 24 |
| Finished | Jul 31 08:56:48 PM PDT 24 |
| Peak memory | 620416 kb |
| Host | smart-3fb93bd9-c73e-4d58-9f98-4c869089608c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227306218 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 6.chip_sw_lc_ctrl_transition.227306218 |
| Directory | /workspace/6.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1952400336 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 8386735270 ps |
| CPU time | 1287.4 seconds |
| Started | Jul 31 08:38:51 PM PDT 24 |
| Finished | Jul 31 09:00:19 PM PDT 24 |
| Peak memory | 624448 kb |
| Host | smart-8080d6ed-854d-4e99-9145-a9d096dbf743 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1952400336 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.1952400336 |
| Directory | /workspace/6.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3578502206 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 3261563390 ps |
| CPU time | 433.77 seconds |
| Started | Jul 31 08:46:25 PM PDT 24 |
| Finished | Jul 31 08:53:39 PM PDT 24 |
| Peak memory | 649044 kb |
| Host | smart-eaa83e94-122c-496a-8a67-8f702538e32d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578502206 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3578502206 |
| Directory | /workspace/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/60.chip_sw_all_escalation_resets.1195759941 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 5678832840 ps |
| CPU time | 763.69 seconds |
| Started | Jul 31 08:42:35 PM PDT 24 |
| Finished | Jul 31 08:55:18 PM PDT 24 |
| Peak memory | 650316 kb |
| Host | smart-72500120-f2b9-4ede-a50e-9773297cc34c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1195759941 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.1195759941 |
| Directory | /workspace/60.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.151732297 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 4097584030 ps |
| CPU time | 397.26 seconds |
| Started | Jul 31 08:43:43 PM PDT 24 |
| Finished | Jul 31 08:50:21 PM PDT 24 |
| Peak memory | 649100 kb |
| Host | smart-f3d485fc-f16e-4ede-bbb9-3136eeb93663 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151732297 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_s w_alert_handler_lpg_sleep_mode_alerts.151732297 |
| Directory | /workspace/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3776877100 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 4291526516 ps |
| CPU time | 363.46 seconds |
| Started | Jul 31 08:44:00 PM PDT 24 |
| Finished | Jul 31 08:50:04 PM PDT 24 |
| Peak memory | 649092 kb |
| Host | smart-8c77f415-de09-4ee0-9414-d766a56533bc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776877100 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3776877100 |
| Directory | /workspace/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/62.chip_sw_all_escalation_resets.2440131374 |
| Short name | T1318 |
| Test name | |
| Test status | |
| Simulation time | 5733390522 ps |
| CPU time | 700.59 seconds |
| Started | Jul 31 08:44:28 PM PDT 24 |
| Finished | Jul 31 08:56:09 PM PDT 24 |
| Peak memory | 650384 kb |
| Host | smart-abd054a0-6b5e-4615-bcc3-1851d9521bf8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2440131374 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.2440131374 |
| Directory | /workspace/62.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1134911335 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 3878218276 ps |
| CPU time | 386.09 seconds |
| Started | Jul 31 08:43:03 PM PDT 24 |
| Finished | Jul 31 08:49:29 PM PDT 24 |
| Peak memory | 648772 kb |
| Host | smart-f6008048-916f-49bc-a068-5304688682ed |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134911335 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1134911335 |
| Directory | /workspace/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/63.chip_sw_all_escalation_resets.693437987 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 5870290584 ps |
| CPU time | 680.13 seconds |
| Started | Jul 31 08:44:01 PM PDT 24 |
| Finished | Jul 31 08:55:22 PM PDT 24 |
| Peak memory | 650412 kb |
| Host | smart-0073db21-8cb2-4657-9b8d-fe040ae9ebca |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 693437987 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.693437987 |
| Directory | /workspace/63.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.4227354596 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 3483830300 ps |
| CPU time | 352.46 seconds |
| Started | Jul 31 08:43:22 PM PDT 24 |
| Finished | Jul 31 08:49:15 PM PDT 24 |
| Peak memory | 649108 kb |
| Host | smart-57430cdf-6ff6-4a3c-aaec-8ce00278d2a3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227354596 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4227354596 |
| Directory | /workspace/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/64.chip_sw_all_escalation_resets.3810976769 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 4190316680 ps |
| CPU time | 547.33 seconds |
| Started | Jul 31 08:44:14 PM PDT 24 |
| Finished | Jul 31 08:53:21 PM PDT 24 |
| Peak memory | 649632 kb |
| Host | smart-0dbffd37-d065-457b-baa8-050f170d1645 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3810976769 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.3810976769 |
| Directory | /workspace/64.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/65.chip_sw_all_escalation_resets.3752240179 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 5906961340 ps |
| CPU time | 585.06 seconds |
| Started | Jul 31 08:43:22 PM PDT 24 |
| Finished | Jul 31 08:53:08 PM PDT 24 |
| Peak memory | 650260 kb |
| Host | smart-985f61c4-1a73-4f4c-8710-acbe41903179 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3752240179 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.3752240179 |
| Directory | /workspace/65.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2808437494 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 3684852420 ps |
| CPU time | 415.76 seconds |
| Started | Jul 31 08:42:50 PM PDT 24 |
| Finished | Jul 31 08:49:45 PM PDT 24 |
| Peak memory | 649560 kb |
| Host | smart-9bb4960b-d803-4e18-adee-7daabac1db7d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808437494 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2808437494 |
| Directory | /workspace/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/67.chip_sw_all_escalation_resets.1305302576 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 5104437570 ps |
| CPU time | 536.36 seconds |
| Started | Jul 31 08:43:32 PM PDT 24 |
| Finished | Jul 31 08:52:28 PM PDT 24 |
| Peak memory | 650680 kb |
| Host | smart-a92245e0-b08c-4227-938b-5b42096df8ad |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1305302576 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.1305302576 |
| Directory | /workspace/67.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.4032655569 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 4005003618 ps |
| CPU time | 411.42 seconds |
| Started | Jul 31 08:44:23 PM PDT 24 |
| Finished | Jul 31 08:51:14 PM PDT 24 |
| Peak memory | 649020 kb |
| Host | smart-ed5f10f0-1060-495a-92f1-08526f3f4f6b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032655569 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4032655569 |
| Directory | /workspace/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/68.chip_sw_all_escalation_resets.3553066846 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 5112800908 ps |
| CPU time | 520.5 seconds |
| Started | Jul 31 08:43:48 PM PDT 24 |
| Finished | Jul 31 08:52:29 PM PDT 24 |
| Peak memory | 650136 kb |
| Host | smart-c9741939-64a8-47d9-ab51-9dca291965fa |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3553066846 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.3553066846 |
| Directory | /workspace/68.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/69.chip_sw_all_escalation_resets.397909870 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 4704854820 ps |
| CPU time | 530.96 seconds |
| Started | Jul 31 08:44:20 PM PDT 24 |
| Finished | Jul 31 08:53:11 PM PDT 24 |
| Peak memory | 650032 kb |
| Host | smart-3482b0cd-21a4-44cb-8314-5f6fe4083465 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 397909870 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.397909870 |
| Directory | /workspace/69.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3863947681 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 4256529990 ps |
| CPU time | 577.38 seconds |
| Started | Jul 31 08:44:02 PM PDT 24 |
| Finished | Jul 31 08:53:40 PM PDT 24 |
| Peak memory | 649112 kb |
| Host | smart-b1bee042-f75f-4cd1-8a88-86c8dc4e417d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863947681 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_s w_alert_handler_lpg_sleep_mode_alerts.3863947681 |
| Directory | /workspace/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/7.chip_sw_all_escalation_resets.2055508083 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 5173875102 ps |
| CPU time | 629.27 seconds |
| Started | Jul 31 08:40:18 PM PDT 24 |
| Finished | Jul 31 08:50:48 PM PDT 24 |
| Peak memory | 619676 kb |
| Host | smart-478e00e7-afbb-453b-b1e8-4e03e300bb44 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2055508083 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.2055508083 |
| Directory | /workspace/7.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2420049045 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 27013173546 ps |
| CPU time | 6296.59 seconds |
| Started | Jul 31 08:38:31 PM PDT 24 |
| Finished | Jul 31 10:23:28 PM PDT 24 |
| Peak memory | 610228 kb |
| Host | smart-56cca663-adbd-4efa-ad4e-ab05f8dd2ee9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420049045 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 7.chip_sw_csrng_edn_concurrency.2420049045 |
| Directory | /workspace/7.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2145716474 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 10178135474 ps |
| CPU time | 813.11 seconds |
| Started | Jul 31 08:37:51 PM PDT 24 |
| Finished | Jul 31 08:51:24 PM PDT 24 |
| Peak memory | 620340 kb |
| Host | smart-674e0e42-862a-4b1c-92e3-e20f73608c6a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145716474 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 7.chip_sw_lc_ctrl_transition.2145716474 |
| Directory | /workspace/7.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2718656058 |
| Short name | T1364 |
| Test name | |
| Test status | |
| Simulation time | 3688474470 ps |
| CPU time | 531.67 seconds |
| Started | Jul 31 08:39:48 PM PDT 24 |
| Finished | Jul 31 08:48:40 PM PDT 24 |
| Peak memory | 622136 kb |
| Host | smart-ae131968-a736-40ff-827a-89fcdd391721 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2718656058 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.2718656058 |
| Directory | /workspace/7.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.350210132 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 4351995176 ps |
| CPU time | 464.33 seconds |
| Started | Jul 31 08:45:43 PM PDT 24 |
| Finished | Jul 31 08:53:28 PM PDT 24 |
| Peak memory | 649016 kb |
| Host | smart-2461ad23-b556-426a-9ad9-2dd8b5c6b374 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350210132 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_s w_alert_handler_lpg_sleep_mode_alerts.350210132 |
| Directory | /workspace/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/70.chip_sw_all_escalation_resets.848971623 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 5181061260 ps |
| CPU time | 478.77 seconds |
| Started | Jul 31 08:43:40 PM PDT 24 |
| Finished | Jul 31 08:51:39 PM PDT 24 |
| Peak memory | 650104 kb |
| Host | smart-a821bd24-05a0-4b89-b006-8be8d005131b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 848971623 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.848971623 |
| Directory | /workspace/70.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/71.chip_sw_all_escalation_resets.3899844883 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 4604017032 ps |
| CPU time | 530.53 seconds |
| Started | Jul 31 08:45:08 PM PDT 24 |
| Finished | Jul 31 08:53:59 PM PDT 24 |
| Peak memory | 650288 kb |
| Host | smart-c8c7ce88-104e-4254-8bdc-d71f942dcaec |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3899844883 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.3899844883 |
| Directory | /workspace/71.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3287970108 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 3419139152 ps |
| CPU time | 262.99 seconds |
| Started | Jul 31 08:42:54 PM PDT 24 |
| Finished | Jul 31 08:47:17 PM PDT 24 |
| Peak memory | 648972 kb |
| Host | smart-7044ef55-26f1-4dd2-9c30-85c63685c9c4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287970108 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3287970108 |
| Directory | /workspace/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/72.chip_sw_all_escalation_resets.2760559688 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 5747233026 ps |
| CPU time | 545.92 seconds |
| Started | Jul 31 08:43:40 PM PDT 24 |
| Finished | Jul 31 08:52:46 PM PDT 24 |
| Peak memory | 650440 kb |
| Host | smart-c1d51ccb-aaed-457d-9570-bfbe9bada113 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2760559688 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.2760559688 |
| Directory | /workspace/72.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1672461936 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 3588355240 ps |
| CPU time | 455.21 seconds |
| Started | Jul 31 08:43:56 PM PDT 24 |
| Finished | Jul 31 08:51:32 PM PDT 24 |
| Peak memory | 649328 kb |
| Host | smart-454a07f4-42f1-435d-9ebf-bc2ba4decbae |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672461936 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1672461936 |
| Directory | /workspace/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/73.chip_sw_all_escalation_resets.1131086348 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 5198330232 ps |
| CPU time | 739.2 seconds |
| Started | Jul 31 08:43:49 PM PDT 24 |
| Finished | Jul 31 08:56:08 PM PDT 24 |
| Peak memory | 650012 kb |
| Host | smart-f474a05f-1602-46da-a935-cbe0dd4bfa08 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1131086348 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.1131086348 |
| Directory | /workspace/73.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2390656360 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 3612547884 ps |
| CPU time | 533.46 seconds |
| Started | Jul 31 08:45:54 PM PDT 24 |
| Finished | Jul 31 08:54:47 PM PDT 24 |
| Peak memory | 649012 kb |
| Host | smart-320ec715-bffc-4b1a-9231-be74d074f69b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390656360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2390656360 |
| Directory | /workspace/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/74.chip_sw_all_escalation_resets.1427747674 |
| Short name | T1334 |
| Test name | |
| Test status | |
| Simulation time | 4652780656 ps |
| CPU time | 654.85 seconds |
| Started | Jul 31 08:46:26 PM PDT 24 |
| Finished | Jul 31 08:57:21 PM PDT 24 |
| Peak memory | 650168 kb |
| Host | smart-c3b6ba94-995f-4a9b-be6a-974bd6be0dea |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1427747674 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.1427747674 |
| Directory | /workspace/74.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2387157202 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 3576774112 ps |
| CPU time | 352.2 seconds |
| Started | Jul 31 08:46:04 PM PDT 24 |
| Finished | Jul 31 08:51:56 PM PDT 24 |
| Peak memory | 649616 kb |
| Host | smart-209913d1-179c-448b-a447-73c98b3137f8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387157202 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2387157202 |
| Directory | /workspace/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.377673070 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 3503077562 ps |
| CPU time | 319.31 seconds |
| Started | Jul 31 08:46:06 PM PDT 24 |
| Finished | Jul 31 08:51:26 PM PDT 24 |
| Peak memory | 649088 kb |
| Host | smart-1523fd22-e529-4f4a-bf99-dffd7a294b1d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377673070 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_s w_alert_handler_lpg_sleep_mode_alerts.377673070 |
| Directory | /workspace/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/76.chip_sw_all_escalation_resets.2510516749 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 5867360520 ps |
| CPU time | 745.05 seconds |
| Started | Jul 31 08:45:40 PM PDT 24 |
| Finished | Jul 31 08:58:05 PM PDT 24 |
| Peak memory | 650544 kb |
| Host | smart-bcf4062b-4bb0-4872-961d-26ae6e8d0f63 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2510516749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.2510516749 |
| Directory | /workspace/76.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3706886741 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 4255899960 ps |
| CPU time | 429.13 seconds |
| Started | Jul 31 08:46:45 PM PDT 24 |
| Finished | Jul 31 08:53:55 PM PDT 24 |
| Peak memory | 648684 kb |
| Host | smart-1de98f1d-3935-4f91-bfa7-9223c5a6cfa2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706886741 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3706886741 |
| Directory | /workspace/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/77.chip_sw_all_escalation_resets.3380016512 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 4694483528 ps |
| CPU time | 572.11 seconds |
| Started | Jul 31 08:44:49 PM PDT 24 |
| Finished | Jul 31 08:54:22 PM PDT 24 |
| Peak memory | 650256 kb |
| Host | smart-9168de97-7558-446d-b71c-36c2ec27cd35 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3380016512 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.3380016512 |
| Directory | /workspace/77.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2478716525 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 4017256520 ps |
| CPU time | 362.08 seconds |
| Started | Jul 31 08:45:17 PM PDT 24 |
| Finished | Jul 31 08:51:19 PM PDT 24 |
| Peak memory | 649252 kb |
| Host | smart-b1f2240b-155f-4781-a39f-4cb369a9a187 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478716525 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2478716525 |
| Directory | /workspace/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2578245234 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 3414542060 ps |
| CPU time | 324.37 seconds |
| Started | Jul 31 08:46:38 PM PDT 24 |
| Finished | Jul 31 08:52:03 PM PDT 24 |
| Peak memory | 649136 kb |
| Host | smart-c53108cd-a0b3-4015-8b59-46320887a91f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578245234 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2578245234 |
| Directory | /workspace/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/79.chip_sw_all_escalation_resets.99813477 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 5882209244 ps |
| CPU time | 565.17 seconds |
| Started | Jul 31 08:47:01 PM PDT 24 |
| Finished | Jul 31 08:56:27 PM PDT 24 |
| Peak memory | 650164 kb |
| Host | smart-4328fdb0-58c5-4277-bce0-8be149bdc1bc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 99813477 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_all_escalation_resets.99813477 |
| Directory | /workspace/79.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2655817738 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 3895465070 ps |
| CPU time | 574.21 seconds |
| Started | Jul 31 08:39:00 PM PDT 24 |
| Finished | Jul 31 08:48:34 PM PDT 24 |
| Peak memory | 648900 kb |
| Host | smart-20dc53af-7a43-4b41-aa0c-3b443e7302b1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655817738 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_s w_alert_handler_lpg_sleep_mode_alerts.2655817738 |
| Directory | /workspace/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/8.chip_sw_all_escalation_resets.1681378871 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 5891035120 ps |
| CPU time | 729.04 seconds |
| Started | Jul 31 08:38:37 PM PDT 24 |
| Finished | Jul 31 08:50:47 PM PDT 24 |
| Peak memory | 650180 kb |
| Host | smart-c25058d5-b58c-407b-a9e8-16730650ee59 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1681378871 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.1681378871 |
| Directory | /workspace/8.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.3738600181 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 24622702996 ps |
| CPU time | 5872.9 seconds |
| Started | Jul 31 08:40:14 PM PDT 24 |
| Finished | Jul 31 10:18:08 PM PDT 24 |
| Peak memory | 610344 kb |
| Host | smart-3b1306c2-2a64-4aea-a02e-e014608cbd32 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738600181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 8.chip_sw_csrng_edn_concurrency.3738600181 |
| Directory | /workspace/8.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3109378311 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 7539335585 ps |
| CPU time | 599.67 seconds |
| Started | Jul 31 08:44:34 PM PDT 24 |
| Finished | Jul 31 08:54:35 PM PDT 24 |
| Peak memory | 624708 kb |
| Host | smart-68be0dcb-7fc0-4cbe-9540-a49ed1b789cb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109378311 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 8.chip_sw_lc_ctrl_transition.3109378311 |
| Directory | /workspace/8.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2912942393 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 8023476816 ps |
| CPU time | 1351.49 seconds |
| Started | Jul 31 08:44:24 PM PDT 24 |
| Finished | Jul 31 09:06:56 PM PDT 24 |
| Peak memory | 624548 kb |
| Host | smart-5ac5026e-015d-4b59-a8e5-4831f580db28 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2912942393 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.2912942393 |
| Directory | /workspace/8.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2673682533 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 3856334260 ps |
| CPU time | 314.13 seconds |
| Started | Jul 31 08:46:46 PM PDT 24 |
| Finished | Jul 31 08:52:01 PM PDT 24 |
| Peak memory | 649096 kb |
| Host | smart-4cfcade4-6571-47ed-9718-5e079d297fed |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673682533 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2673682533 |
| Directory | /workspace/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/80.chip_sw_all_escalation_resets.1341940106 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 4401402520 ps |
| CPU time | 460.86 seconds |
| Started | Jul 31 08:47:33 PM PDT 24 |
| Finished | Jul 31 08:55:14 PM PDT 24 |
| Peak memory | 649896 kb |
| Host | smart-ad18fa8c-cbe3-4530-9be6-e779b3ddb8c2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1341940106 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.1341940106 |
| Directory | /workspace/80.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3739510688 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 4177714402 ps |
| CPU time | 384.15 seconds |
| Started | Jul 31 08:44:51 PM PDT 24 |
| Finished | Jul 31 08:51:15 PM PDT 24 |
| Peak memory | 618988 kb |
| Host | smart-195a82a9-5b68-4b2a-bb1c-da7750966d82 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739510688 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3739510688 |
| Directory | /workspace/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/81.chip_sw_all_escalation_resets.2452329445 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 6432162840 ps |
| CPU time | 641.49 seconds |
| Started | Jul 31 08:47:32 PM PDT 24 |
| Finished | Jul 31 08:58:14 PM PDT 24 |
| Peak memory | 649992 kb |
| Host | smart-4e4b2ec3-4ad8-4cf3-b157-9015f100539e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2452329445 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.2452329445 |
| Directory | /workspace/81.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/82.chip_sw_all_escalation_resets.1122924244 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 4914831580 ps |
| CPU time | 568.01 seconds |
| Started | Jul 31 08:44:59 PM PDT 24 |
| Finished | Jul 31 08:54:27 PM PDT 24 |
| Peak memory | 650260 kb |
| Host | smart-f6e2733f-74f2-45ed-ae87-7aec239b9cf3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1122924244 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.1122924244 |
| Directory | /workspace/82.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/83.chip_sw_all_escalation_resets.902426827 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 5197969876 ps |
| CPU time | 621.22 seconds |
| Started | Jul 31 08:45:18 PM PDT 24 |
| Finished | Jul 31 08:55:40 PM PDT 24 |
| Peak memory | 650264 kb |
| Host | smart-9828b922-5552-40d5-b10e-5bce3fe1475e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 902426827 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.902426827 |
| Directory | /workspace/83.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2393857682 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 3266291540 ps |
| CPU time | 350.93 seconds |
| Started | Jul 31 08:45:49 PM PDT 24 |
| Finished | Jul 31 08:51:40 PM PDT 24 |
| Peak memory | 648804 kb |
| Host | smart-a17b9f85-a0b4-455c-962c-86c91d4f056b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393857682 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2393857682 |
| Directory | /workspace/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/85.chip_sw_all_escalation_resets.947520207 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 4447124918 ps |
| CPU time | 601.11 seconds |
| Started | Jul 31 08:45:17 PM PDT 24 |
| Finished | Jul 31 08:55:18 PM PDT 24 |
| Peak memory | 649964 kb |
| Host | smart-85015f73-2bf5-45cb-9459-a44a615bbd8e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 947520207 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.947520207 |
| Directory | /workspace/85.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2264549285 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 3493356080 ps |
| CPU time | 431.2 seconds |
| Started | Jul 31 08:45:36 PM PDT 24 |
| Finished | Jul 31 08:52:47 PM PDT 24 |
| Peak memory | 649468 kb |
| Host | smart-53028d71-503d-436d-a408-b58f344c93e4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264549285 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2264549285 |
| Directory | /workspace/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/86.chip_sw_all_escalation_resets.570483357 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 5207252716 ps |
| CPU time | 771.41 seconds |
| Started | Jul 31 08:46:13 PM PDT 24 |
| Finished | Jul 31 08:59:05 PM PDT 24 |
| Peak memory | 650144 kb |
| Host | smart-0bec150d-d9a3-46ec-9195-985f56b5cb69 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 570483357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.570483357 |
| Directory | /workspace/86.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.2782357324 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 3855471432 ps |
| CPU time | 416.76 seconds |
| Started | Jul 31 08:46:35 PM PDT 24 |
| Finished | Jul 31 08:53:32 PM PDT 24 |
| Peak memory | 649064 kb |
| Host | smart-5a57c5e7-74e1-4ec2-a9df-bba37f6b169e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782357324 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2782357324 |
| Directory | /workspace/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/87.chip_sw_all_escalation_resets.1321743693 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 4318376608 ps |
| CPU time | 497.92 seconds |
| Started | Jul 31 08:47:25 PM PDT 24 |
| Finished | Jul 31 08:55:43 PM PDT 24 |
| Peak memory | 649956 kb |
| Host | smart-1533d6f0-28e2-45bc-b76a-87f5bd9b4033 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1321743693 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.1321743693 |
| Directory | /workspace/87.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/88.chip_sw_all_escalation_resets.856580303 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 5412450640 ps |
| CPU time | 429.83 seconds |
| Started | Jul 31 08:46:52 PM PDT 24 |
| Finished | Jul 31 08:54:02 PM PDT 24 |
| Peak memory | 650288 kb |
| Host | smart-18b72045-61a3-4c4c-80a1-9a84a4c693d8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 856580303 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.856580303 |
| Directory | /workspace/88.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2353107219 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 3382361674 ps |
| CPU time | 448.97 seconds |
| Started | Jul 31 08:45:23 PM PDT 24 |
| Finished | Jul 31 08:52:52 PM PDT 24 |
| Peak memory | 649176 kb |
| Host | smart-7a45cba2-c9e5-43ed-b480-cca05d214430 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353107219 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2353107219 |
| Directory | /workspace/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/89.chip_sw_all_escalation_resets.515309020 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 5348600304 ps |
| CPU time | 616.97 seconds |
| Started | Jul 31 08:45:20 PM PDT 24 |
| Finished | Jul 31 08:55:37 PM PDT 24 |
| Peak memory | 650304 kb |
| Host | smart-abcd3f8a-9ad4-464e-a9fb-35de645bbca4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 515309020 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.515309020 |
| Directory | /workspace/89.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.264619649 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 3417655072 ps |
| CPU time | 357.96 seconds |
| Started | Jul 31 08:45:25 PM PDT 24 |
| Finished | Jul 31 08:51:23 PM PDT 24 |
| Peak memory | 649276 kb |
| Host | smart-50177c49-ab22-477a-8df9-41934fda032c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264619649 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw _alert_handler_lpg_sleep_mode_alerts.264619649 |
| Directory | /workspace/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/9.chip_sw_all_escalation_resets.3201472595 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 5014545088 ps |
| CPU time | 695.2 seconds |
| Started | Jul 31 08:37:57 PM PDT 24 |
| Finished | Jul 31 08:49:32 PM PDT 24 |
| Peak memory | 650900 kb |
| Host | smart-f231e255-4513-4e14-8b8f-f27227547d7f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3201472595 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.3201472595 |
| Directory | /workspace/9.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.1489214666 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 21692075216 ps |
| CPU time | 4310.38 seconds |
| Started | Jul 31 08:37:52 PM PDT 24 |
| Finished | Jul 31 09:49:43 PM PDT 24 |
| Peak memory | 609904 kb |
| Host | smart-5be9df80-11c3-4027-88fd-5512ebb81591 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489214666 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 9.chip_sw_csrng_edn_concurrency.1489214666 |
| Directory | /workspace/9.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.827920573 |
| Short name | T1321 |
| Test name | |
| Test status | |
| Simulation time | 5419286440 ps |
| CPU time | 439.76 seconds |
| Started | Jul 31 08:44:52 PM PDT 24 |
| Finished | Jul 31 08:52:12 PM PDT 24 |
| Peak memory | 620464 kb |
| Host | smart-fd243554-f8bf-4b45-be95-682bee893883 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827920573 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 9.chip_sw_lc_ctrl_transition.827920573 |
| Directory | /workspace/9.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.4271265619 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 13312856208 ps |
| CPU time | 2470.55 seconds |
| Started | Jul 31 08:45:04 PM PDT 24 |
| Finished | Jul 31 09:26:15 PM PDT 24 |
| Peak memory | 623296 kb |
| Host | smart-7c965c79-1c6d-4f38-a6f0-7e1254b02e10 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4271265619 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.4271265619 |
| Directory | /workspace/9.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/91.chip_sw_all_escalation_resets.2722670358 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 5158371726 ps |
| CPU time | 539.96 seconds |
| Started | Jul 31 08:46:01 PM PDT 24 |
| Finished | Jul 31 08:55:01 PM PDT 24 |
| Peak memory | 650344 kb |
| Host | smart-bf97c28c-7f1d-4ad7-a3bf-da4f5c707ff8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2722670358 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.2722670358 |
| Directory | /workspace/91.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/92.chip_sw_all_escalation_resets.2565912760 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 5745597380 ps |
| CPU time | 633.15 seconds |
| Started | Jul 31 08:48:30 PM PDT 24 |
| Finished | Jul 31 08:59:03 PM PDT 24 |
| Peak memory | 650516 kb |
| Host | smart-e8499523-fa7f-4c43-96f2-6fadec02386f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2565912760 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.2565912760 |
| Directory | /workspace/92.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/93.chip_sw_all_escalation_resets.3106195202 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 5881136784 ps |
| CPU time | 604.86 seconds |
| Started | Jul 31 08:46:07 PM PDT 24 |
| Finished | Jul 31 08:56:12 PM PDT 24 |
| Peak memory | 620092 kb |
| Host | smart-dde0aaa9-c044-4901-a52a-956d5db23bb6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3106195202 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.3106195202 |
| Directory | /workspace/93.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/94.chip_sw_all_escalation_resets.1899689871 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 5843979606 ps |
| CPU time | 674.69 seconds |
| Started | Jul 31 08:46:56 PM PDT 24 |
| Finished | Jul 31 08:58:11 PM PDT 24 |
| Peak memory | 650456 kb |
| Host | smart-38a4f417-7f9c-4bba-82ca-ba396523cb07 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1899689871 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.1899689871 |
| Directory | /workspace/94.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/96.chip_sw_all_escalation_resets.1403811820 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 4757658170 ps |
| CPU time | 657.67 seconds |
| Started | Jul 31 08:46:21 PM PDT 24 |
| Finished | Jul 31 08:57:19 PM PDT 24 |
| Peak memory | 650164 kb |
| Host | smart-2d3baa60-082c-483d-8bbe-2969d6992b79 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1403811820 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.1403811820 |
| Directory | /workspace/96.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/97.chip_sw_all_escalation_resets.3632301908 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 5000656470 ps |
| CPU time | 508.88 seconds |
| Started | Jul 31 08:47:24 PM PDT 24 |
| Finished | Jul 31 08:55:53 PM PDT 24 |
| Peak memory | 650420 kb |
| Host | smart-fbfcd522-3bc6-4127-8dea-9a8c58a24410 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3632301908 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.3632301908 |
| Directory | /workspace/97.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/98.chip_sw_all_escalation_resets.3164430661 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 4253639974 ps |
| CPU time | 547.14 seconds |
| Started | Jul 31 08:47:16 PM PDT 24 |
| Finished | Jul 31 08:56:23 PM PDT 24 |
| Peak memory | 650512 kb |
| Host | smart-bb5d8e1a-3218-40e9-baf5-01f02803aa90 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3164430661 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.3164430661 |
| Directory | /workspace/98.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2248588599 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 4049497374 ps |
| CPU time | 210.97 seconds |
| Started | Jul 31 07:45:00 PM PDT 24 |
| Finished | Jul 31 07:48:32 PM PDT 24 |
| Peak memory | 649168 kb |
| Host | smart-7cffab57-4718-4a81-b44c-bb207dd2c1bc |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248588599 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 3.chip_padctrl_attributes.2248588599 |
| Directory | /workspace/3.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1077677341 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 5275185952 ps |
| CPU time | 323.6 seconds |
| Started | Jul 31 07:45:00 PM PDT 24 |
| Finished | Jul 31 07:50:24 PM PDT 24 |
| Peak memory | 652976 kb |
| Host | smart-87acf00e-319e-4113-8831-6b936d5d6efd |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077677341 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 4.chip_padctrl_attributes.1077677341 |
| Directory | /workspace/4.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.421526056 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 4574767240 ps |
| CPU time | 235.48 seconds |
| Started | Jul 31 07:45:02 PM PDT 24 |
| Finished | Jul 31 07:48:58 PM PDT 24 |
| Peak memory | 649164 kb |
| Host | smart-8f825a29-c05b-4407-b2e1-31159d02ab8c |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421526056 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 5.chip_padctrl_attributes.421526056 |
| Directory | /workspace/5.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2045240816 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 3717727280 ps |
| CPU time | 180.03 seconds |
| Started | Jul 31 07:44:59 PM PDT 24 |
| Finished | Jul 31 07:47:59 PM PDT 24 |
| Peak memory | 641264 kb |
| Host | smart-fd367d87-f506-486d-b510-8e50a2da8404 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045240816 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 6.chip_padctrl_attributes.2045240816 |
| Directory | /workspace/6.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2425787393 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 5005822944 ps |
| CPU time | 252.54 seconds |
| Started | Jul 31 07:45:03 PM PDT 24 |
| Finished | Jul 31 07:49:16 PM PDT 24 |
| Peak memory | 655564 kb |
| Host | smart-4f647d9d-a0be-47a2-b8c3-ff035178e31b |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425787393 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 7.chip_padctrl_attributes.2425787393 |
| Directory | /workspace/7.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3909217737 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 3839139275 ps |
| CPU time | 222.06 seconds |
| Started | Jul 31 07:45:03 PM PDT 24 |
| Finished | Jul 31 07:48:45 PM PDT 24 |
| Peak memory | 640900 kb |
| Host | smart-6dc9426b-3ffa-41e5-b75e-2f9900f51701 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909217737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 8.chip_padctrl_attributes.3909217737 |
| Directory | /workspace/8.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1538960740 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 5436411328 ps |
| CPU time | 261.13 seconds |
| Started | Jul 31 07:45:00 PM PDT 24 |
| Finished | Jul 31 07:49:21 PM PDT 24 |
| Peak memory | 657316 kb |
| Host | smart-5f153a35-1608-457b-a916-3cc1dd4d88fb |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538960740 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 9.chip_padctrl_attributes.1538960740 |
| Directory | /workspace/9.chip_padctrl_attributes/latest |
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