| T1197 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.114150503 |
|
|
Jul 31 08:30:05 PM PDT 24 |
Jul 31 08:35:11 PM PDT 24 |
3155925424 ps |
| T1198 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3833539504 |
|
|
Jul 31 08:30:42 PM PDT 24 |
Jul 31 09:16:59 PM PDT 24 |
20536182268 ps |
| T1199 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3624774444 |
|
|
Jul 31 08:17:35 PM PDT 24 |
Jul 31 08:27:18 PM PDT 24 |
4284888734 ps |
| T1200 |
/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.927204541 |
|
|
Jul 31 08:17:18 PM PDT 24 |
Jul 31 08:48:36 PM PDT 24 |
8177631516 ps |
| T1201 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.4272687653 |
|
|
Jul 31 08:32:19 PM PDT 24 |
Jul 31 08:48:29 PM PDT 24 |
5858251442 ps |
| T1202 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.3156331868 |
|
|
Jul 31 08:20:20 PM PDT 24 |
Jul 31 08:27:51 PM PDT 24 |
4803475615 ps |
| T1203 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.3500921365 |
|
|
Jul 31 08:21:37 PM PDT 24 |
Jul 31 09:38:25 PM PDT 24 |
17996420152 ps |
| T1204 |
/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.1775573209 |
|
|
Jul 31 08:35:58 PM PDT 24 |
Jul 31 08:39:22 PM PDT 24 |
2678055608 ps |
| T1205 |
/workspace/coverage/default/1.chip_sw_csrng_kat_test.4244717267 |
|
|
Jul 31 08:21:59 PM PDT 24 |
Jul 31 08:26:08 PM PDT 24 |
2866658754 ps |
| T1206 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.3748896160 |
|
|
Jul 31 08:14:52 PM PDT 24 |
Jul 31 08:38:34 PM PDT 24 |
7820890700 ps |
| T785 |
/workspace/coverage/default/64.chip_sw_all_escalation_resets.3810976769 |
|
|
Jul 31 08:44:14 PM PDT 24 |
Jul 31 08:53:21 PM PDT 24 |
4190316680 ps |
| T1207 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1735867452 |
|
|
Jul 31 08:23:07 PM PDT 24 |
Jul 31 08:34:18 PM PDT 24 |
3884033746 ps |
| T794 |
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1073060558 |
|
|
Jul 31 08:42:48 PM PDT 24 |
Jul 31 08:49:12 PM PDT 24 |
3599629852 ps |
| T1208 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.886551429 |
|
|
Jul 31 08:19:15 PM PDT 24 |
Jul 31 08:44:32 PM PDT 24 |
8461192660 ps |
| T42 |
/workspace/coverage/default/1.chip_sw_spi_device_tpm.4088147024 |
|
|
Jul 31 08:20:23 PM PDT 24 |
Jul 31 08:26:58 PM PDT 24 |
3748308814 ps |
| T1209 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.2966528231 |
|
|
Jul 31 08:36:17 PM PDT 24 |
Jul 31 09:01:50 PM PDT 24 |
11107150567 ps |
| T1210 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1680194206 |
|
|
Jul 31 08:33:53 PM PDT 24 |
Jul 31 08:53:01 PM PDT 24 |
7167240807 ps |
| T1211 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.6169965 |
|
|
Jul 31 08:34:49 PM PDT 24 |
Jul 31 08:44:44 PM PDT 24 |
4466901000 ps |
| T1212 |
/workspace/coverage/default/2.rom_keymgr_functest.3256492093 |
|
|
Jul 31 08:37:15 PM PDT 24 |
Jul 31 08:48:29 PM PDT 24 |
4790125500 ps |
| T268 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.963271349 |
|
|
Jul 31 08:38:14 PM PDT 24 |
Jul 31 08:48:17 PM PDT 24 |
4277898140 ps |
| T1213 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.3925834663 |
|
|
Jul 31 08:21:49 PM PDT 24 |
Jul 31 09:59:48 PM PDT 24 |
24323123286 ps |
| T1214 |
/workspace/coverage/default/1.rom_e2e_self_hash.1736406890 |
|
|
Jul 31 08:31:15 PM PDT 24 |
Jul 31 10:07:17 PM PDT 24 |
26198308276 ps |
| T1215 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.351039280 |
|
|
Jul 31 08:29:30 PM PDT 24 |
Jul 31 08:57:42 PM PDT 24 |
12355685046 ps |
| T1216 |
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.599548293 |
|
|
Jul 31 08:45:03 PM PDT 24 |
Jul 31 08:50:45 PM PDT 24 |
3972051344 ps |
| T1217 |
/workspace/coverage/default/0.chip_tap_straps_testunlock0.502032810 |
|
|
Jul 31 08:15:53 PM PDT 24 |
Jul 31 08:20:27 PM PDT 24 |
3400572681 ps |
| T1218 |
/workspace/coverage/default/1.chip_sw_hmac_oneshot.2037784219 |
|
|
Jul 31 08:22:22 PM PDT 24 |
Jul 31 08:28:23 PM PDT 24 |
2820944506 ps |
| T1219 |
/workspace/coverage/default/0.chip_sw_csrng_kat_test.129181019 |
|
|
Jul 31 08:13:43 PM PDT 24 |
Jul 31 08:17:35 PM PDT 24 |
2963576712 ps |
| T1220 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.67549186 |
|
|
Jul 31 08:15:30 PM PDT 24 |
Jul 31 08:27:21 PM PDT 24 |
7785231944 ps |
| T813 |
/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.994274759 |
|
|
Jul 31 08:42:11 PM PDT 24 |
Jul 31 08:49:44 PM PDT 24 |
3263197256 ps |
| T208 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through.2443610154 |
|
|
Jul 31 08:12:32 PM PDT 24 |
Jul 31 08:21:36 PM PDT 24 |
5328945226 ps |
| T1221 |
/workspace/coverage/default/2.chip_tap_straps_rma.322176062 |
|
|
Jul 31 08:33:21 PM PDT 24 |
Jul 31 08:44:24 PM PDT 24 |
6316389372 ps |
| T1222 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.1740779553 |
|
|
Jul 31 08:14:19 PM PDT 24 |
Jul 31 08:33:36 PM PDT 24 |
5099537608 ps |
| T1223 |
/workspace/coverage/default/2.chip_sw_csrng_kat_test.1148243613 |
|
|
Jul 31 08:34:49 PM PDT 24 |
Jul 31 08:38:54 PM PDT 24 |
3000155700 ps |
| T1224 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.607686914 |
|
|
Jul 31 08:29:03 PM PDT 24 |
Jul 31 08:52:14 PM PDT 24 |
8720723474 ps |
| T1225 |
/workspace/coverage/default/1.chip_sw_flash_init.1030289663 |
|
|
Jul 31 08:17:36 PM PDT 24 |
Jul 31 08:52:01 PM PDT 24 |
19383796945 ps |
| T1226 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.864830021 |
|
|
Jul 31 08:13:53 PM PDT 24 |
Jul 31 08:37:31 PM PDT 24 |
9023490180 ps |
| T1227 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.2269155731 |
|
|
Jul 31 08:19:16 PM PDT 24 |
Jul 31 08:22:34 PM PDT 24 |
3006725021 ps |
| T1228 |
/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.2237182307 |
|
|
Jul 31 08:45:35 PM PDT 24 |
Jul 31 09:30:49 PM PDT 24 |
12946961296 ps |
| T1229 |
/workspace/coverage/default/1.chip_sw_kmac_entropy.2374924749 |
|
|
Jul 31 08:18:50 PM PDT 24 |
Jul 31 08:23:10 PM PDT 24 |
2966855372 ps |
| T1230 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1372127813 |
|
|
Jul 31 08:37:59 PM PDT 24 |
Jul 31 08:48:45 PM PDT 24 |
4022108110 ps |
| T1231 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.447912122 |
|
|
Jul 31 08:13:21 PM PDT 24 |
Jul 31 08:18:01 PM PDT 24 |
2898614420 ps |
| T1232 |
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.1963474907 |
|
|
Jul 31 08:42:49 PM PDT 24 |
Jul 31 09:30:31 PM PDT 24 |
13549701548 ps |
| T298 |
/workspace/coverage/default/77.chip_sw_all_escalation_resets.3380016512 |
|
|
Jul 31 08:44:49 PM PDT 24 |
Jul 31 08:54:22 PM PDT 24 |
4694483528 ps |
| T1233 |
/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.3635838803 |
|
|
Jul 31 08:18:47 PM PDT 24 |
Jul 31 08:26:38 PM PDT 24 |
9475693103 ps |
| T1234 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.2745342408 |
|
|
Jul 31 08:21:02 PM PDT 24 |
Jul 31 08:26:52 PM PDT 24 |
3670895039 ps |
| T791 |
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2393857682 |
|
|
Jul 31 08:45:49 PM PDT 24 |
Jul 31 08:51:40 PM PDT 24 |
3266291540 ps |
| T1235 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.257951861 |
|
|
Jul 31 08:26:26 PM PDT 24 |
Jul 31 08:50:19 PM PDT 24 |
8228859848 ps |
| T1236 |
/workspace/coverage/default/1.chip_sw_ast_clk_outputs.324082987 |
|
|
Jul 31 08:26:33 PM PDT 24 |
Jul 31 08:46:59 PM PDT 24 |
7939900554 ps |
| T1237 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.228825101 |
|
|
Jul 31 08:31:20 PM PDT 24 |
Jul 31 08:36:15 PM PDT 24 |
3568302548 ps |
| T161 |
/workspace/coverage/default/0.chip_sw_usbdev_config_host.3738432441 |
|
|
Jul 31 08:13:05 PM PDT 24 |
Jul 31 08:48:35 PM PDT 24 |
8157210240 ps |
| T29 |
/workspace/coverage/default/1.chip_sw_gpio.3882128054 |
|
|
Jul 31 08:17:51 PM PDT 24 |
Jul 31 08:26:07 PM PDT 24 |
3660373776 ps |
| T1238 |
/workspace/coverage/default/0.chip_tap_straps_prod.1787023552 |
|
|
Jul 31 08:15:28 PM PDT 24 |
Jul 31 08:18:32 PM PDT 24 |
2921610042 ps |
| T1239 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.3008730661 |
|
|
Jul 31 08:13:26 PM PDT 24 |
Jul 31 08:27:16 PM PDT 24 |
4249957170 ps |
| T1240 |
/workspace/coverage/default/2.chip_sw_hmac_enc_idle.1301728934 |
|
|
Jul 31 08:32:08 PM PDT 24 |
Jul 31 08:37:43 PM PDT 24 |
3618817200 ps |
| T1241 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.823022816 |
|
|
Jul 31 08:33:25 PM PDT 24 |
Jul 31 08:44:48 PM PDT 24 |
4827672552 ps |
| T1242 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.804776849 |
|
|
Jul 31 08:28:30 PM PDT 24 |
Jul 31 08:43:47 PM PDT 24 |
4665624580 ps |
| T1243 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.962670980 |
|
|
Jul 31 08:13:54 PM PDT 24 |
Jul 31 08:25:27 PM PDT 24 |
7079483279 ps |
| T1244 |
/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.2551324393 |
|
|
Jul 31 08:21:46 PM PDT 24 |
Jul 31 08:24:25 PM PDT 24 |
3001376900 ps |
| T211 |
/workspace/coverage/default/0.chip_jtag_mem_access.1054455700 |
|
|
Jul 31 08:06:48 PM PDT 24 |
Jul 31 08:29:02 PM PDT 24 |
14185332510 ps |
| T1245 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.2472398798 |
|
|
Jul 31 08:33:27 PM PDT 24 |
Jul 31 09:30:23 PM PDT 24 |
18921365389 ps |
| T1246 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.2027603808 |
|
|
Jul 31 08:38:44 PM PDT 24 |
Jul 31 08:50:43 PM PDT 24 |
4596768958 ps |
| T1247 |
/workspace/coverage/default/1.chip_sw_all_escalation_resets.2711618313 |
|
|
Jul 31 08:17:50 PM PDT 24 |
Jul 31 08:28:47 PM PDT 24 |
5096698116 ps |
| T69 |
/workspace/coverage/default/4.chip_tap_straps_rma.3299114853 |
|
|
Jul 31 08:37:44 PM PDT 24 |
Jul 31 08:47:47 PM PDT 24 |
5369029418 ps |
| T1248 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.2918773804 |
|
|
Jul 31 08:39:13 PM PDT 24 |
Jul 31 09:37:16 PM PDT 24 |
14518408200 ps |
| T731 |
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.971067825 |
|
|
Jul 31 08:43:44 PM PDT 24 |
Jul 31 08:50:48 PM PDT 24 |
3911851272 ps |
| T1249 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1551707604 |
|
|
Jul 31 08:33:11 PM PDT 24 |
Jul 31 09:29:24 PM PDT 24 |
17499590622 ps |
| T1250 |
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.561070750 |
|
|
Jul 31 08:43:33 PM PDT 24 |
Jul 31 08:50:31 PM PDT 24 |
4151765108 ps |
| T831 |
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.604568801 |
|
|
Jul 31 08:43:20 PM PDT 24 |
Jul 31 08:49:08 PM PDT 24 |
3446570118 ps |
| T1251 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx.2040085943 |
|
|
Jul 31 08:27:49 PM PDT 24 |
Jul 31 08:41:25 PM PDT 24 |
3708135540 ps |
| T1252 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.47293374 |
|
|
Jul 31 08:35:50 PM PDT 24 |
Jul 31 08:42:02 PM PDT 24 |
6056541144 ps |
| T1253 |
/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.2546814246 |
|
|
Jul 31 08:38:12 PM PDT 24 |
Jul 31 09:59:56 PM PDT 24 |
20690251310 ps |
| T691 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.3216683601 |
|
|
Jul 31 08:17:27 PM PDT 24 |
Jul 31 08:25:13 PM PDT 24 |
5252111198 ps |
| T1254 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.203982360 |
|
|
Jul 31 08:23:04 PM PDT 24 |
Jul 31 08:38:18 PM PDT 24 |
7416267634 ps |
| T1255 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.3774117214 |
|
|
Jul 31 08:17:10 PM PDT 24 |
Jul 31 08:47:32 PM PDT 24 |
8005428727 ps |
| T1256 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.3404799678 |
|
|
Jul 31 08:19:26 PM PDT 24 |
Jul 31 09:15:09 PM PDT 24 |
14733890452 ps |
| T1257 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.4189568309 |
|
|
Jul 31 08:32:37 PM PDT 24 |
Jul 31 08:55:51 PM PDT 24 |
8844724828 ps |
| T1258 |
/workspace/coverage/default/1.chip_sw_otbn_smoketest.1290001049 |
|
|
Jul 31 08:26:47 PM PDT 24 |
Jul 31 08:58:46 PM PDT 24 |
7420994380 ps |
| T209 |
/workspace/coverage/default/0.chip_sw_power_virus.1745440623 |
|
|
Jul 31 08:22:14 PM PDT 24 |
Jul 31 08:43:55 PM PDT 24 |
5661888084 ps |
| T1259 |
/workspace/coverage/default/0.chip_sw_kmac_entropy.1369907370 |
|
|
Jul 31 08:12:30 PM PDT 24 |
Jul 31 08:16:35 PM PDT 24 |
2657791536 ps |
| T1260 |
/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.668122249 |
|
|
Jul 31 08:16:38 PM PDT 24 |
Jul 31 08:36:19 PM PDT 24 |
8723951250 ps |
| T1261 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.2923014728 |
|
|
Jul 31 08:12:01 PM PDT 24 |
Jul 31 08:22:24 PM PDT 24 |
4133698360 ps |
| T1262 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.1573698185 |
|
|
Jul 31 08:30:02 PM PDT 24 |
Jul 31 10:01:41 PM PDT 24 |
50547948893 ps |
| T1263 |
/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.447549680 |
|
|
Jul 31 08:43:16 PM PDT 24 |
Jul 31 09:32:04 PM PDT 24 |
12933032376 ps |
| T57 |
/workspace/coverage/default/1.chip_sw_sleep_pin_retention.532607692 |
|
|
Jul 31 08:18:19 PM PDT 24 |
Jul 31 08:22:42 PM PDT 24 |
3888594510 ps |
| T1264 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.2478188693 |
|
|
Jul 31 08:29:55 PM PDT 24 |
Jul 31 08:38:32 PM PDT 24 |
4486057448 ps |
| T1265 |
/workspace/coverage/default/1.chip_sw_alert_handler_escalation.2176292795 |
|
|
Jul 31 08:21:49 PM PDT 24 |
Jul 31 08:34:57 PM PDT 24 |
5876245000 ps |
| T1266 |
/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.3450187955 |
|
|
Jul 31 08:16:04 PM PDT 24 |
Jul 31 08:20:31 PM PDT 24 |
3550957656 ps |
| T734 |
/workspace/coverage/default/48.chip_sw_all_escalation_resets.820205214 |
|
|
Jul 31 08:43:40 PM PDT 24 |
Jul 31 08:54:06 PM PDT 24 |
6160172810 ps |
| T1267 |
/workspace/coverage/default/0.chip_sw_ast_clk_outputs.2524993086 |
|
|
Jul 31 08:16:14 PM PDT 24 |
Jul 31 08:34:11 PM PDT 24 |
8832749600 ps |
| T1268 |
/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2202979942 |
|
|
Jul 31 08:13:48 PM PDT 24 |
Jul 31 08:49:22 PM PDT 24 |
26269292819 ps |
| T817 |
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3706886741 |
|
|
Jul 31 08:46:45 PM PDT 24 |
Jul 31 08:53:55 PM PDT 24 |
4255899960 ps |
| T1269 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.2060025499 |
|
|
Jul 31 08:30:27 PM PDT 24 |
Jul 31 09:59:55 PM PDT 24 |
46134494992 ps |
| T1270 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3725007336 |
|
|
Jul 31 08:36:31 PM PDT 24 |
Jul 31 08:39:35 PM PDT 24 |
2492727956 ps |
| T1271 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3085787974 |
|
|
Jul 31 08:36:58 PM PDT 24 |
Jul 31 09:05:23 PM PDT 24 |
9216015506 ps |
| T1272 |
/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.3656960495 |
|
|
Jul 31 08:16:54 PM PDT 24 |
Jul 31 08:21:52 PM PDT 24 |
3337760420 ps |
| T1273 |
/workspace/coverage/default/41.chip_sw_all_escalation_resets.3581410070 |
|
|
Jul 31 08:43:36 PM PDT 24 |
Jul 31 08:52:00 PM PDT 24 |
4541804182 ps |
| T351 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3121843608 |
|
|
Jul 31 08:27:07 PM PDT 24 |
Jul 31 08:41:51 PM PDT 24 |
4258853184 ps |
| T1274 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.3371759201 |
|
|
Jul 31 08:36:01 PM PDT 24 |
Jul 31 08:39:50 PM PDT 24 |
3258060800 ps |
| T60 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.1092605514 |
|
|
Jul 31 08:16:00 PM PDT 24 |
Jul 31 08:19:40 PM PDT 24 |
2789916130 ps |
| T414 |
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.3059480888 |
|
|
Jul 31 08:38:03 PM PDT 24 |
Jul 31 09:41:08 PM PDT 24 |
17627131640 ps |
| T415 |
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.350210132 |
|
|
Jul 31 08:45:43 PM PDT 24 |
Jul 31 08:53:28 PM PDT 24 |
4351995176 ps |
| T416 |
/workspace/coverage/default/2.chip_sw_inject_scramble_seed.435653470 |
|
|
Jul 31 08:28:30 PM PDT 24 |
Jul 31 11:36:37 PM PDT 24 |
63257616981 ps |
| T417 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.3893685419 |
|
|
Jul 31 08:13:31 PM PDT 24 |
Jul 31 08:22:42 PM PDT 24 |
6345624022 ps |
| T418 |
/workspace/coverage/default/0.chip_sw_usbdev_setuprx.2056563221 |
|
|
Jul 31 08:12:18 PM PDT 24 |
Jul 31 08:21:10 PM PDT 24 |
4010109456 ps |
| T419 |
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.4227354596 |
|
|
Jul 31 08:43:22 PM PDT 24 |
Jul 31 08:49:15 PM PDT 24 |
3483830300 ps |
| T420 |
/workspace/coverage/default/1.chip_sw_aes_enc.2878965433 |
|
|
Jul 31 08:21:32 PM PDT 24 |
Jul 31 08:26:17 PM PDT 24 |
2077966896 ps |
| T145 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.286435145 |
|
|
Jul 31 08:25:02 PM PDT 24 |
Jul 31 08:32:03 PM PDT 24 |
5916013560 ps |
| T421 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.2997622121 |
|
|
Jul 31 08:17:53 PM PDT 24 |
Jul 31 08:28:41 PM PDT 24 |
4664036416 ps |
| T1275 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2029546630 |
|
|
Jul 31 08:23:00 PM PDT 24 |
Jul 31 09:36:50 PM PDT 24 |
14751281432 ps |
| T210 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through.2329369464 |
|
|
Jul 31 08:28:38 PM PDT 24 |
Jul 31 08:41:49 PM PDT 24 |
5980783389 ps |
| T798 |
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.212996985 |
|
|
Jul 31 08:43:07 PM PDT 24 |
Jul 31 08:50:16 PM PDT 24 |
3772141310 ps |
| T1276 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1680356148 |
|
|
Jul 31 08:21:40 PM PDT 24 |
Jul 31 08:34:00 PM PDT 24 |
5290691791 ps |
| T1277 |
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1773514402 |
|
|
Jul 31 08:36:24 PM PDT 24 |
Jul 31 08:48:56 PM PDT 24 |
5863175170 ps |
| T1278 |
/workspace/coverage/default/2.chip_sw_otbn_randomness.2975686400 |
|
|
Jul 31 08:32:19 PM PDT 24 |
Jul 31 08:47:38 PM PDT 24 |
6533953730 ps |
| T1279 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx.1954097813 |
|
|
Jul 31 08:35:32 PM PDT 24 |
Jul 31 08:45:22 PM PDT 24 |
3891696550 ps |
| T1280 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3271481567 |
|
|
Jul 31 08:13:22 PM PDT 24 |
Jul 31 08:26:22 PM PDT 24 |
4905219300 ps |
| T1281 |
/workspace/coverage/default/1.chip_sw_kmac_smoketest.1014445399 |
|
|
Jul 31 08:27:24 PM PDT 24 |
Jul 31 08:32:44 PM PDT 24 |
2593288326 ps |
| T53 |
/workspace/coverage/default/0.chip_sw_alert_test.692020104 |
|
|
Jul 31 08:12:28 PM PDT 24 |
Jul 31 08:17:58 PM PDT 24 |
3569688476 ps |
| T1282 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2321973122 |
|
|
Jul 31 08:32:25 PM PDT 24 |
Jul 31 08:45:36 PM PDT 24 |
4350593832 ps |
| T1283 |
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.1489214666 |
|
|
Jul 31 08:37:52 PM PDT 24 |
Jul 31 09:49:43 PM PDT 24 |
21692075216 ps |
| T1284 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.2692187857 |
|
|
Jul 31 08:13:24 PM PDT 24 |
Jul 31 08:23:55 PM PDT 24 |
4475154712 ps |
| T190 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.1384040712 |
|
|
Jul 31 08:12:46 PM PDT 24 |
Jul 31 08:15:35 PM PDT 24 |
3047103083 ps |
| T352 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.3534312237 |
|
|
Jul 31 08:14:13 PM PDT 24 |
Jul 31 08:26:20 PM PDT 24 |
4062203898 ps |
| T304 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1806880609 |
|
|
Jul 31 08:26:07 PM PDT 24 |
Jul 31 08:29:37 PM PDT 24 |
2194407112 ps |
| T1285 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3757221825 |
|
|
Jul 31 08:20:19 PM PDT 24 |
Jul 31 08:34:10 PM PDT 24 |
4969249822 ps |
| T1286 |
/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.3024000698 |
|
|
Jul 31 08:28:03 PM PDT 24 |
Jul 31 08:55:48 PM PDT 24 |
9633163404 ps |
| T1287 |
/workspace/coverage/default/1.rom_e2e_static_critical.1869010529 |
|
|
Jul 31 08:33:32 PM PDT 24 |
Jul 31 09:45:11 PM PDT 24 |
17231593244 ps |
| T1288 |
/workspace/coverage/default/0.chip_sw_aes_smoketest.1455240986 |
|
|
Jul 31 08:15:59 PM PDT 24 |
Jul 31 08:20:52 PM PDT 24 |
3373717884 ps |
| T1289 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.1609197100 |
|
|
Jul 31 08:22:56 PM PDT 24 |
Jul 31 08:52:37 PM PDT 24 |
8170575400 ps |
| T54 |
/workspace/coverage/default/2.chip_sw_alert_test.4110780505 |
|
|
Jul 31 08:33:15 PM PDT 24 |
Jul 31 08:38:48 PM PDT 24 |
3550023696 ps |
| T710 |
/workspace/coverage/default/1.chip_sw_power_sleep_load.1636573773 |
|
|
Jul 31 08:25:52 PM PDT 24 |
Jul 31 08:32:52 PM PDT 24 |
4698990712 ps |
| T778 |
/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.4217043783 |
|
|
Jul 31 08:43:30 PM PDT 24 |
Jul 31 08:50:28 PM PDT 24 |
4041485922 ps |
| T1290 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3906268285 |
|
|
Jul 31 08:14:01 PM PDT 24 |
Jul 31 08:33:44 PM PDT 24 |
6260783874 ps |
| T1291 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access.769627518 |
|
|
Jul 31 08:30:30 PM PDT 24 |
Jul 31 08:50:12 PM PDT 24 |
5313402266 ps |
| T1292 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.386119243 |
|
|
Jul 31 08:19:13 PM PDT 24 |
Jul 31 08:31:59 PM PDT 24 |
4077982954 ps |
| T1293 |
/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.4252461419 |
|
|
Jul 31 08:31:44 PM PDT 24 |
Jul 31 08:37:07 PM PDT 24 |
6775400000 ps |
| T1294 |
/workspace/coverage/default/1.rom_e2e_shutdown_output.242797102 |
|
|
Jul 31 08:31:27 PM PDT 24 |
Jul 31 09:34:07 PM PDT 24 |
26375628732 ps |
| T1295 |
/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.3607666048 |
|
|
Jul 31 08:26:13 PM PDT 24 |
Jul 31 08:34:30 PM PDT 24 |
3788322900 ps |
| T771 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2376397670 |
|
|
Jul 31 08:42:12 PM PDT 24 |
Jul 31 08:49:38 PM PDT 24 |
4031694760 ps |
| T1296 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2145716474 |
|
|
Jul 31 08:37:51 PM PDT 24 |
Jul 31 08:51:24 PM PDT 24 |
10178135474 ps |
| T1297 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.12925662 |
|
|
Jul 31 08:21:59 PM PDT 24 |
Jul 31 09:55:35 PM PDT 24 |
23989376620 ps |
| T820 |
/workspace/coverage/default/87.chip_sw_all_escalation_resets.1321743693 |
|
|
Jul 31 08:47:25 PM PDT 24 |
Jul 31 08:55:43 PM PDT 24 |
4318376608 ps |
| T1298 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2613008145 |
|
|
Jul 31 08:14:32 PM PDT 24 |
Jul 31 09:14:14 PM PDT 24 |
17246621200 ps |
| T1299 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1661575986 |
|
|
Jul 31 08:13:09 PM PDT 24 |
Jul 31 08:21:10 PM PDT 24 |
4374991552 ps |
| T1300 |
/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.3521728193 |
|
|
Jul 31 08:30:30 PM PDT 24 |
Jul 31 08:33:49 PM PDT 24 |
2585216304 ps |
| T1301 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.122155148 |
|
|
Jul 31 08:15:33 PM PDT 24 |
Jul 31 08:24:59 PM PDT 24 |
5503703680 ps |
| T51 |
/workspace/coverage/default/2.chip_jtag_csr_rw.3526945129 |
|
|
Jul 31 08:26:21 PM PDT 24 |
Jul 31 08:59:55 PM PDT 24 |
17538132144 ps |
| T1302 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2674517698 |
|
|
Jul 31 08:16:14 PM PDT 24 |
Jul 31 08:28:03 PM PDT 24 |
3936915937 ps |
| T37 |
/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.202731021 |
|
|
Jul 31 08:13:29 PM PDT 24 |
Jul 31 08:17:31 PM PDT 24 |
2473511810 ps |
| T1303 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3808393568 |
|
|
Jul 31 08:17:37 PM PDT 24 |
Jul 31 08:29:19 PM PDT 24 |
18867208092 ps |
| T1304 |
/workspace/coverage/default/2.chip_sw_otbn_smoketest.3062035814 |
|
|
Jul 31 08:35:32 PM PDT 24 |
Jul 31 08:58:12 PM PDT 24 |
8003768424 ps |
| T814 |
/workspace/coverage/default/63.chip_sw_all_escalation_resets.693437987 |
|
|
Jul 31 08:44:01 PM PDT 24 |
Jul 31 08:55:22 PM PDT 24 |
5870290584 ps |
| T1305 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.3866496857 |
|
|
Jul 31 08:21:51 PM PDT 24 |
Jul 31 08:26:41 PM PDT 24 |
3376639841 ps |
| T1306 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2777944314 |
|
|
Jul 31 08:35:46 PM PDT 24 |
Jul 31 08:45:27 PM PDT 24 |
4974354759 ps |
| T422 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2183321780 |
|
|
Jul 31 08:26:33 PM PDT 24 |
Jul 31 08:35:38 PM PDT 24 |
7922053828 ps |
| T825 |
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2954691970 |
|
|
Jul 31 08:43:04 PM PDT 24 |
Jul 31 08:49:56 PM PDT 24 |
3640920442 ps |
| T1307 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.472775920 |
|
|
Jul 31 08:39:32 PM PDT 24 |
Jul 31 09:06:46 PM PDT 24 |
13154969044 ps |
| T58 |
/workspace/coverage/default/0.chip_sw_sleep_pin_retention.2496495989 |
|
|
Jul 31 08:11:59 PM PDT 24 |
Jul 31 08:17:33 PM PDT 24 |
4337500546 ps |
| T1308 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.311197230 |
|
|
Jul 31 08:13:57 PM PDT 24 |
Jul 31 09:02:56 PM PDT 24 |
12300739936 ps |
| T1309 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3266217641 |
|
|
Jul 31 08:11:54 PM PDT 24 |
Jul 31 08:59:10 PM PDT 24 |
13281653956 ps |
| T1310 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.1782920131 |
|
|
Jul 31 08:30:17 PM PDT 24 |
Jul 31 08:42:18 PM PDT 24 |
9552789104 ps |
| T767 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.339205105 |
|
|
Jul 31 08:21:27 PM PDT 24 |
Jul 31 08:29:17 PM PDT 24 |
4445239928 ps |
| T1311 |
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3511060355 |
|
|
Jul 31 08:38:14 PM PDT 24 |
Jul 31 09:14:18 PM PDT 24 |
13241600676 ps |
| T1312 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.3420798451 |
|
|
Jul 31 08:16:32 PM PDT 24 |
Jul 31 08:24:15 PM PDT 24 |
4114525628 ps |
| T39 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3387372439 |
|
|
Jul 31 08:20:48 PM PDT 24 |
Jul 31 08:29:22 PM PDT 24 |
6299818426 ps |
| T1313 |
/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.3654926586 |
|
|
Jul 31 08:36:41 PM PDT 24 |
Jul 31 08:40:16 PM PDT 24 |
2787836500 ps |
| T677 |
/workspace/coverage/default/1.chip_sw_edn_boot_mode.380577379 |
|
|
Jul 31 08:22:21 PM PDT 24 |
Jul 31 08:35:32 PM PDT 24 |
3232368950 ps |
| T1314 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.3927074985 |
|
|
Jul 31 08:20:46 PM PDT 24 |
Jul 31 09:27:43 PM PDT 24 |
14988119560 ps |
| T269 |
/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.1389234562 |
|
|
Jul 31 08:30:31 PM PDT 24 |
Jul 31 08:43:02 PM PDT 24 |
6476659680 ps |
| T1315 |
/workspace/coverage/default/2.chip_sw_aes_smoketest.3546399588 |
|
|
Jul 31 08:34:53 PM PDT 24 |
Jul 31 08:39:58 PM PDT 24 |
2358618776 ps |
| T1316 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.3245027463 |
|
|
Jul 31 08:12:52 PM PDT 24 |
Jul 31 08:17:07 PM PDT 24 |
3032209459 ps |
| T1317 |
/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.934408516 |
|
|
Jul 31 08:32:48 PM PDT 24 |
Jul 31 08:37:04 PM PDT 24 |
3249089932 ps |
| T792 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.4099307073 |
|
|
Jul 31 08:42:15 PM PDT 24 |
Jul 31 08:48:51 PM PDT 24 |
3147171016 ps |
| T1318 |
/workspace/coverage/default/62.chip_sw_all_escalation_resets.2440131374 |
|
|
Jul 31 08:44:28 PM PDT 24 |
Jul 31 08:56:09 PM PDT 24 |
5733390522 ps |
| T799 |
/workspace/coverage/default/29.chip_sw_all_escalation_resets.3972970017 |
|
|
Jul 31 08:42:46 PM PDT 24 |
Jul 31 08:54:01 PM PDT 24 |
5382824390 ps |
| T1319 |
/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.3719157068 |
|
|
Jul 31 08:38:02 PM PDT 24 |
Jul 31 08:42:19 PM PDT 24 |
2867102572 ps |
| T1320 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3201015460 |
|
|
Jul 31 08:13:08 PM PDT 24 |
Jul 31 08:30:37 PM PDT 24 |
7098285224 ps |
| T1321 |
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.827920573 |
|
|
Jul 31 08:44:52 PM PDT 24 |
Jul 31 08:52:12 PM PDT 24 |
5419286440 ps |
| T1322 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.3071719500 |
|
|
Jul 31 08:38:33 PM PDT 24 |
Jul 31 09:35:07 PM PDT 24 |
15574915166 ps |
| T795 |
/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.811983468 |
|
|
Jul 31 08:39:27 PM PDT 24 |
Jul 31 08:46:19 PM PDT 24 |
3197699736 ps |
| T1323 |
/workspace/coverage/default/2.chip_sw_aes_enc.2022377837 |
|
|
Jul 31 08:34:11 PM PDT 24 |
Jul 31 08:40:11 PM PDT 24 |
2956402552 ps |
| T146 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.763364254 |
|
|
Jul 31 08:33:48 PM PDT 24 |
Jul 31 08:42:35 PM PDT 24 |
5463593568 ps |
| T1324 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1497268010 |
|
|
Jul 31 08:33:28 PM PDT 24 |
Jul 31 08:44:58 PM PDT 24 |
4596921350 ps |
| T1325 |
/workspace/coverage/default/2.chip_sw_edn_auto_mode.57748830 |
|
|
Jul 31 08:33:28 PM PDT 24 |
Jul 31 09:00:19 PM PDT 24 |
5573575768 ps |
| T1326 |
/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.1389866201 |
|
|
Jul 31 08:27:53 PM PDT 24 |
Jul 31 09:52:47 PM PDT 24 |
43295734120 ps |
| T1327 |
/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1093741110 |
|
|
Jul 31 08:14:36 PM PDT 24 |
Jul 31 09:38:49 PM PDT 24 |
43630537525 ps |
| T1328 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.1544706217 |
|
|
Jul 31 08:13:29 PM PDT 24 |
Jul 31 08:27:21 PM PDT 24 |
8530907996 ps |
| T1329 |
/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.4176474416 |
|
|
Jul 31 08:33:57 PM PDT 24 |
Jul 31 08:39:02 PM PDT 24 |
2810282728 ps |
| T1330 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3185555602 |
|
|
Jul 31 08:36:32 PM PDT 24 |
Jul 31 08:59:36 PM PDT 24 |
10022632678 ps |
| T1331 |
/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.2798568502 |
|
|
Jul 31 08:14:07 PM PDT 24 |
Jul 31 11:08:05 PM PDT 24 |
58484061744 ps |
| T1332 |
/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.2012284764 |
|
|
Jul 31 08:15:55 PM PDT 24 |
Jul 31 08:25:20 PM PDT 24 |
3347935308 ps |
| T692 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.1065351362 |
|
|
Jul 31 08:33:40 PM PDT 24 |
Jul 31 08:44:47 PM PDT 24 |
4767491838 ps |
| T1333 |
/workspace/coverage/default/1.chip_sw_aon_timer_irq.3121549127 |
|
|
Jul 31 08:21:17 PM PDT 24 |
Jul 31 08:27:02 PM PDT 24 |
3836823434 ps |
| T693 |
/workspace/coverage/default/3.chip_tap_straps_dev.1674209211 |
|
|
Jul 31 08:36:03 PM PDT 24 |
Jul 31 09:05:53 PM PDT 24 |
18455049113 ps |
| T1334 |
/workspace/coverage/default/74.chip_sw_all_escalation_resets.1427747674 |
|
|
Jul 31 08:46:26 PM PDT 24 |
Jul 31 08:57:21 PM PDT 24 |
4652780656 ps |
| T59 |
/workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.3730860108 |
|
|
Jul 31 08:19:06 PM PDT 24 |
Jul 31 08:23:32 PM PDT 24 |
3562843550 ps |
| T1335 |
/workspace/coverage/default/0.chip_sw_power_idle_load.1542520999 |
|
|
Jul 31 08:13:24 PM PDT 24 |
Jul 31 08:23:03 PM PDT 24 |
3597083390 ps |
| T1336 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.280521899 |
|
|
Jul 31 08:24:12 PM PDT 24 |
Jul 31 08:33:42 PM PDT 24 |
3613569942 ps |
| T786 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.2102955488 |
|
|
Jul 31 08:44:10 PM PDT 24 |
Jul 31 08:53:58 PM PDT 24 |
5681435066 ps |
| T800 |
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2264549285 |
|
|
Jul 31 08:45:36 PM PDT 24 |
Jul 31 08:52:47 PM PDT 24 |
3493356080 ps |
| T1337 |
/workspace/coverage/default/0.rom_e2e_self_hash.1250199152 |
|
|
Jul 31 08:21:47 PM PDT 24 |
Jul 31 10:06:53 PM PDT 24 |
25846015836 ps |
| T1338 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.2311316384 |
|
|
Jul 31 08:18:12 PM PDT 24 |
Jul 31 08:23:07 PM PDT 24 |
2636555600 ps |
| T1339 |
/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.1282608273 |
|
|
Jul 31 08:27:10 PM PDT 24 |
Jul 31 08:36:08 PM PDT 24 |
5471829168 ps |
| T779 |
/workspace/coverage/default/98.chip_sw_all_escalation_resets.3164430661 |
|
|
Jul 31 08:47:16 PM PDT 24 |
Jul 31 08:56:23 PM PDT 24 |
4253639974 ps |
| T1340 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2397283226 |
|
|
Jul 31 08:23:16 PM PDT 24 |
Jul 31 09:23:42 PM PDT 24 |
14558970508 ps |
| T781 |
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3776877100 |
|
|
Jul 31 08:44:00 PM PDT 24 |
Jul 31 08:50:04 PM PDT 24 |
4291526516 ps |
| T1341 |
/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.24256248 |
|
|
Jul 31 08:14:43 PM PDT 24 |
Jul 31 08:17:41 PM PDT 24 |
2194577992 ps |
| T1342 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.1343829396 |
|
|
Jul 31 08:19:12 PM PDT 24 |
Jul 31 08:41:04 PM PDT 24 |
8849245464 ps |
| T1343 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.1644338044 |
|
|
Jul 31 08:16:00 PM PDT 24 |
Jul 31 08:21:26 PM PDT 24 |
3586785124 ps |
| T1344 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.605483310 |
|
|
Jul 31 08:15:17 PM PDT 24 |
Jul 31 08:36:09 PM PDT 24 |
8367361056 ps |
| T1345 |
/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.2813829237 |
|
|
Jul 31 08:33:49 PM PDT 24 |
Jul 31 08:41:45 PM PDT 24 |
3980547252 ps |
| T1346 |
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.620666174 |
|
|
Jul 31 08:42:48 PM PDT 24 |
Jul 31 08:49:11 PM PDT 24 |
4222906476 ps |
| T122 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2059432169 |
|
|
Jul 31 08:25:24 PM PDT 24 |
Jul 31 08:44:49 PM PDT 24 |
22894810440 ps |
| T1347 |
/workspace/coverage/default/1.rom_e2e_smoke.800308340 |
|
|
Jul 31 08:39:02 PM PDT 24 |
Jul 31 09:34:17 PM PDT 24 |
15595962136 ps |
| T1348 |
/workspace/coverage/default/1.rom_raw_unlock.252402572 |
|
|
Jul 31 08:27:23 PM PDT 24 |
Jul 31 08:31:23 PM PDT 24 |
6483432890 ps |
| T1349 |
/workspace/coverage/default/2.chip_tap_straps_dev.4046352421 |
|
|
Jul 31 08:34:48 PM PDT 24 |
Jul 31 08:38:10 PM PDT 24 |
2854124668 ps |
| T1350 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2930505844 |
|
|
Jul 31 08:38:53 PM PDT 24 |
Jul 31 08:50:28 PM PDT 24 |
4459760900 ps |
| T373 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.3029948548 |
|
|
Jul 31 08:41:58 PM PDT 24 |
Jul 31 08:49:58 PM PDT 24 |
5025856200 ps |
| T1351 |
/workspace/coverage/default/2.chip_sw_power_idle_load.2916162760 |
|
|
Jul 31 08:36:33 PM PDT 24 |
Jul 31 08:48:44 PM PDT 24 |
4378304200 ps |
| T1352 |
/workspace/coverage/default/1.chip_sival_flash_info_access.3631175276 |
|
|
Jul 31 08:21:33 PM PDT 24 |
Jul 31 08:29:30 PM PDT 24 |
3180138820 ps |
| T99 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2387157202 |
|
|
Jul 31 08:46:04 PM PDT 24 |
Jul 31 08:51:56 PM PDT 24 |
3576774112 ps |
| T1353 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1460137493 |
|
|
Jul 31 08:19:33 PM PDT 24 |
Jul 31 08:44:31 PM PDT 24 |
16104302247 ps |
| T797 |
/workspace/coverage/default/14.chip_sw_all_escalation_resets.834732795 |
|
|
Jul 31 08:42:57 PM PDT 24 |
Jul 31 08:51:28 PM PDT 24 |
5477756826 ps |
| T1354 |
/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.3115025355 |
|
|
Jul 31 08:15:55 PM PDT 24 |
Jul 31 08:21:33 PM PDT 24 |
2765554098 ps |
| T374 |
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.130299021 |
|
|
Jul 31 08:46:56 PM PDT 24 |
Jul 31 08:51:49 PM PDT 24 |
3665947240 ps |
| T1355 |
/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.952876417 |
|
|
Jul 31 08:42:01 PM PDT 24 |
Jul 31 08:59:18 PM PDT 24 |
13567374996 ps |
| T1356 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.3840866196 |
|
|
Jul 31 08:15:16 PM PDT 24 |
Jul 31 08:18:47 PM PDT 24 |
3511861411 ps |
| T1357 |
/workspace/coverage/default/0.chip_sw_coremark.274192676 |
|
|
Jul 31 08:15:15 PM PDT 24 |
Aug 01 12:22:10 AM PDT 24 |
71717350680 ps |
| T1358 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.961443759 |
|
|
Jul 31 08:35:42 PM PDT 24 |
Jul 31 08:43:55 PM PDT 24 |
4557219554 ps |
| T809 |
/workspace/coverage/default/22.chip_sw_all_escalation_resets.1342855229 |
|
|
Jul 31 08:42:19 PM PDT 24 |
Jul 31 08:50:19 PM PDT 24 |
4769006604 ps |
| T1359 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2397419941 |
|
|
Jul 31 08:35:04 PM PDT 24 |
Jul 31 09:31:04 PM PDT 24 |
24782072316 ps |
| T237 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.486820993 |
|
|
Jul 31 08:17:33 PM PDT 24 |
Jul 31 09:17:50 PM PDT 24 |
13257927732 ps |
| T1360 |
/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.4038221335 |
|
|
Jul 31 08:40:49 PM PDT 24 |
Jul 31 08:56:41 PM PDT 24 |
9694061221 ps |
| T1361 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx.279757194 |
|
|
Jul 31 08:12:39 PM PDT 24 |
Jul 31 08:23:27 PM PDT 24 |
4276285004 ps |
| T1362 |
/workspace/coverage/default/2.chip_sw_example_flash.4183058849 |
|
|
Jul 31 08:26:32 PM PDT 24 |
Jul 31 08:30:34 PM PDT 24 |
2955035120 ps |
| T1363 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.64011398 |
|
|
Jul 31 08:30:44 PM PDT 24 |
Jul 31 09:13:31 PM PDT 24 |
28292712536 ps |
| T1364 |
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2718656058 |
|
|
Jul 31 08:39:48 PM PDT 24 |
Jul 31 08:48:40 PM PDT 24 |
3688474470 ps |
| T1365 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3109930019 |
|
|
Jul 31 08:34:06 PM PDT 24 |
Jul 31 08:41:39 PM PDT 24 |
4012395952 ps |
| T1366 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.3469125731 |
|
|
Jul 31 08:14:01 PM PDT 24 |
Jul 31 09:10:06 PM PDT 24 |
18467709518 ps |
| T1367 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.280674041 |
|
|
Jul 31 08:13:25 PM PDT 24 |
Jul 31 08:16:06 PM PDT 24 |
3158684045 ps |
| T784 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.4003131851 |
|
|
Jul 31 08:41:40 PM PDT 24 |
Jul 31 08:48:38 PM PDT 24 |
3859788390 ps |
| T1368 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.2192695283 |
|
|
Jul 31 08:13:10 PM PDT 24 |
Jul 31 08:33:21 PM PDT 24 |
7939540384 ps |
| T30 |
/workspace/coverage/default/2.chip_sw_gpio.867989341 |
|
|
Jul 31 08:29:55 PM PDT 24 |
Jul 31 08:39:34 PM PDT 24 |
4275026030 ps |
| T1369 |
/workspace/coverage/default/1.rom_volatile_raw_unlock.1328642917 |
|
|
Jul 31 08:34:23 PM PDT 24 |
Jul 31 08:36:53 PM PDT 24 |
2298798574 ps |
| T1370 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.2721166295 |
|
|
Jul 31 08:24:04 PM PDT 24 |
Jul 31 09:03:11 PM PDT 24 |
11803888040 ps |
| T1371 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter.3826871958 |
|
|
Jul 31 08:33:46 PM PDT 24 |
Jul 31 08:36:51 PM PDT 24 |
3285432752 ps |
| T774 |
/workspace/coverage/default/32.chip_sw_all_escalation_resets.3064770435 |
|
|
Jul 31 08:42:26 PM PDT 24 |
Jul 31 08:53:48 PM PDT 24 |
5392761232 ps |
| T1372 |
/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.1079964613 |
|
|
Jul 31 08:15:26 PM PDT 24 |
Jul 31 08:44:27 PM PDT 24 |
12166306917 ps |
| T1373 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.412686612 |
|
|
Jul 31 08:19:43 PM PDT 24 |
Jul 31 08:25:31 PM PDT 24 |
5168914341 ps |
| T1374 |
/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.135102393 |
|
|
Jul 31 08:42:32 PM PDT 24 |
Jul 31 08:49:49 PM PDT 24 |
3863943224 ps |