Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 95.47 93.78 95.32 94.52 97.53 99.61


Total test records in report: 2936
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html | tests60.html | tests61.html | tests62.html
T1039 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.300921829 Jul 31 08:14:32 PM PDT 24 Jul 31 08:24:24 PM PDT 24 4463567116 ps
T126 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3029886778 Jul 31 08:27:15 PM PDT 24 Aug 01 02:14:20 AM PDT 24 151482611384 ps
T220 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.1071907094 Jul 31 08:29:45 PM PDT 24 Jul 31 08:35:26 PM PDT 24 3321573160 ps
T742 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.2894017906 Jul 31 08:12:32 PM PDT 24 Jul 31 08:22:10 PM PDT 24 4450103928 ps
T1040 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.777953559 Jul 31 08:14:51 PM PDT 24 Jul 31 08:24:50 PM PDT 24 3759652716 ps
T1041 /workspace/coverage/default/6.chip_sw_all_escalation_resets.2432957315 Jul 31 08:38:05 PM PDT 24 Jul 31 08:51:44 PM PDT 24 5775306064 ps
T407 /workspace/coverage/default/1.chip_sw_kmac_app_rom.2693724229 Jul 31 08:24:33 PM PDT 24 Jul 31 08:28:13 PM PDT 24 3254646616 ps
T782 /workspace/coverage/default/39.chip_sw_all_escalation_resets.3822976889 Jul 31 08:42:05 PM PDT 24 Jul 31 08:51:35 PM PDT 24 4812088954 ps
T1042 /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2589790745 Jul 31 08:30:23 PM PDT 24 Jul 31 08:41:35 PM PDT 24 5349659400 ps
T805 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.1972288118 Jul 31 08:36:53 PM PDT 24 Jul 31 08:43:46 PM PDT 24 3553086138 ps
T96 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.502140653 Jul 31 08:43:39 PM PDT 24 Jul 31 08:49:53 PM PDT 24 3675658480 ps
T1043 /workspace/coverage/default/1.chip_sw_uart_smoketest.3130658641 Jul 31 08:27:38 PM PDT 24 Jul 31 08:32:31 PM PDT 24 2557507668 ps
T1044 /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.2469231100 Jul 31 08:19:33 PM PDT 24 Jul 31 09:11:33 PM PDT 24 32195436377 ps
T292 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.2734297721 Jul 31 08:33:26 PM PDT 24 Jul 31 08:47:07 PM PDT 24 4813334508 ps
T1045 /workspace/coverage/default/2.chip_sw_example_concurrency.3942329780 Jul 31 08:27:53 PM PDT 24 Jul 31 08:32:49 PM PDT 24 2811376766 ps
T1046 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.590056496 Jul 31 08:31:31 PM PDT 24 Jul 31 08:50:36 PM PDT 24 8255849729 ps
T1047 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.459191816 Jul 31 08:22:59 PM PDT 24 Jul 31 08:29:17 PM PDT 24 3353897454 ps
T1048 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.673683934 Jul 31 08:31:32 PM PDT 24 Jul 31 08:55:50 PM PDT 24 7934558260 ps
T1049 /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.381964417 Jul 31 08:30:51 PM PDT 24 Jul 31 08:34:29 PM PDT 24 2522068632 ps
T350 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.3219906853 Jul 31 08:29:31 PM PDT 24 Jul 31 08:41:31 PM PDT 24 4669406312 ps
T1050 /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.1407530960 Jul 31 08:31:04 PM PDT 24 Jul 31 08:45:16 PM PDT 24 4647674948 ps
T390 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1116995895 Jul 31 08:22:25 PM PDT 24 Jul 31 10:11:57 PM PDT 24 24089765602 ps
T1051 /workspace/coverage/default/1.chip_sw_flash_ctrl_access.4201391473 Jul 31 08:18:01 PM PDT 24 Jul 31 08:33:28 PM PDT 24 5329779864 ps
T1052 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.1160854828 Jul 31 08:40:33 PM PDT 24 Jul 31 09:37:10 PM PDT 24 15048055080 ps
T1053 /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.3155799639 Jul 31 08:41:24 PM PDT 24 Jul 31 09:05:50 PM PDT 24 7841449228 ps
T824 /workspace/coverage/default/28.chip_sw_all_escalation_resets.1930242679 Jul 31 08:41:06 PM PDT 24 Jul 31 08:53:11 PM PDT 24 5550334002 ps
T1054 /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1208718472 Jul 31 08:39:19 PM PDT 24 Jul 31 08:52:57 PM PDT 24 9029589313 ps
T330 /workspace/coverage/default/1.chip_plic_all_irqs_20.1642092287 Jul 31 08:24:27 PM PDT 24 Jul 31 08:37:42 PM PDT 24 4628823000 ps
T1055 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.376577433 Jul 31 08:21:01 PM PDT 24 Jul 31 08:37:48 PM PDT 24 5036954692 ps
T1056 /workspace/coverage/default/2.rom_e2e_smoke.4086114847 Jul 31 08:39:48 PM PDT 24 Jul 31 09:28:29 PM PDT 24 14571826152 ps
T1057 /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.2803868552 Jul 31 08:32:24 PM PDT 24 Jul 31 09:01:42 PM PDT 24 8627981250 ps
T1058 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3430201710 Jul 31 08:17:26 PM PDT 24 Jul 31 08:22:18 PM PDT 24 3437385298 ps
T1059 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1105739412 Jul 31 08:43:21 PM PDT 24 Jul 31 08:53:17 PM PDT 24 3921618284 ps
T1060 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.1645854641 Jul 31 08:22:22 PM PDT 24 Jul 31 09:17:06 PM PDT 24 20800714506 ps
T1061 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.309259369 Jul 31 08:29:10 PM PDT 24 Jul 31 08:49:24 PM PDT 24 5751710017 ps
T1062 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.482957626 Jul 31 08:23:32 PM PDT 24 Jul 31 08:28:36 PM PDT 24 3403370384 ps
T678 /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.3738600181 Jul 31 08:40:14 PM PDT 24 Jul 31 10:18:08 PM PDT 24 24622702996 ps
T787 /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3117256430 Jul 31 08:41:52 PM PDT 24 Jul 31 08:49:30 PM PDT 24 4008610032 ps
T266 /workspace/coverage/default/92.chip_sw_all_escalation_resets.2565912760 Jul 31 08:48:30 PM PDT 24 Jul 31 08:59:03 PM PDT 24 5745597380 ps
T1063 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.153912521 Jul 31 08:24:01 PM PDT 24 Jul 31 09:27:11 PM PDT 24 14629302028 ps
T1064 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.1412776777 Jul 31 08:41:11 PM PDT 24 Jul 31 08:53:09 PM PDT 24 10728650472 ps
T1065 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.4014290993 Jul 31 08:28:21 PM PDT 24 Jul 31 08:42:50 PM PDT 24 5293388784 ps
T10 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.555306540 Jul 31 08:13:18 PM PDT 24 Jul 31 08:18:47 PM PDT 24 3661106073 ps
T1066 /workspace/coverage/default/0.rom_e2e_shutdown_output.242801953 Jul 31 08:22:18 PM PDT 24 Jul 31 09:17:25 PM PDT 24 29610998972 ps
T1067 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.632520337 Jul 31 08:20:28 PM PDT 24 Jul 31 08:29:56 PM PDT 24 7241560056 ps
T1068 /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.1748943471 Jul 31 08:24:05 PM PDT 24 Jul 31 08:33:03 PM PDT 24 5330966180 ps
T746 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3578502206 Jul 31 08:46:25 PM PDT 24 Jul 31 08:53:39 PM PDT 24 3261563390 ps
T1069 /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3543855737 Jul 31 08:36:06 PM PDT 24 Jul 31 08:46:04 PM PDT 24 8090769600 ps
T111 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3034546195 Jul 31 08:33:25 PM PDT 24 Jul 31 08:42:12 PM PDT 24 7912764198 ps
T1070 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1840635387 Jul 31 08:15:54 PM PDT 24 Jul 31 08:20:27 PM PDT 24 3092988392 ps
T1071 /workspace/coverage/default/0.rom_e2e_asm_init_prod.1806800119 Jul 31 08:21:46 PM PDT 24 Jul 31 09:31:37 PM PDT 24 15671209618 ps
T368 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.3574978078 Jul 31 08:21:28 PM PDT 24 Jul 31 08:33:58 PM PDT 24 3895598014 ps
T182 /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.1700341714 Jul 31 08:36:52 PM PDT 24 Jul 31 08:46:25 PM PDT 24 4899421302 ps
T1072 /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.1030851637 Jul 31 08:19:34 PM PDT 24 Jul 31 08:23:36 PM PDT 24 2298129334 ps
T1073 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1899727308 Jul 31 08:30:22 PM PDT 24 Jul 31 08:39:52 PM PDT 24 6119058618 ps
T1074 /workspace/coverage/default/1.chip_sw_power_idle_load.1045916760 Jul 31 08:30:24 PM PDT 24 Jul 31 08:41:59 PM PDT 24 3734413422 ps
T1075 /workspace/coverage/default/0.chip_sw_hmac_enc.3085754195 Jul 31 08:18:40 PM PDT 24 Jul 31 08:23:08 PM PDT 24 2507770300 ps
T1076 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.3606372817 Jul 31 08:20:46 PM PDT 24 Jul 31 08:28:42 PM PDT 24 5426740118 ps
T1077 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.3013315819 Jul 31 08:37:24 PM PDT 24 Jul 31 08:50:04 PM PDT 24 4536471016 ps
T372 /workspace/coverage/default/10.chip_sw_all_escalation_resets.4186683550 Jul 31 08:40:53 PM PDT 24 Jul 31 08:53:23 PM PDT 24 6346476968 ps
T1078 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.4195064672 Jul 31 08:32:30 PM PDT 24 Jul 31 08:53:28 PM PDT 24 6421985256 ps
T151 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2154426327 Jul 31 08:16:38 PM PDT 24 Jul 31 08:33:33 PM PDT 24 7186128120 ps
T245 /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.555248065 Jul 31 08:21:52 PM PDT 24 Jul 31 09:47:39 PM PDT 24 49058159222 ps
T735 /workspace/coverage/default/8.chip_sw_all_escalation_resets.1681378871 Jul 31 08:38:37 PM PDT 24 Jul 31 08:50:47 PM PDT 24 5891035120 ps
T1079 /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.3968995239 Jul 31 08:28:03 PM PDT 24 Aug 01 12:21:20 AM PDT 24 77888304360 ps
T164 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3202049026 Jul 31 08:14:30 PM PDT 24 Jul 31 09:21:48 PM PDT 24 24480977202 ps
T1080 /workspace/coverage/default/1.chip_sw_otbn_randomness.2232734499 Jul 31 08:19:57 PM PDT 24 Jul 31 08:31:16 PM PDT 24 5801337800 ps
T1081 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3982854122 Jul 31 08:12:45 PM PDT 24 Jul 31 08:20:20 PM PDT 24 7243526614 ps
T776 /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.944560690 Jul 31 08:43:14 PM PDT 24 Jul 31 08:51:05 PM PDT 24 4261357776 ps
T696 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.3014157173 Jul 31 08:30:15 PM PDT 24 Jul 31 08:32:07 PM PDT 24 2909609943 ps
T1082 /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.2559097192 Jul 31 08:22:38 PM PDT 24 Jul 31 08:51:06 PM PDT 24 7535945528 ps
T1083 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.2053177849 Jul 31 08:16:28 PM PDT 24 Jul 31 08:37:28 PM PDT 24 8032862721 ps
T788 /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3287970108 Jul 31 08:42:54 PM PDT 24 Jul 31 08:47:17 PM PDT 24 3419139152 ps
T1084 /workspace/coverage/default/0.chip_sw_kmac_app_rom.3469264704 Jul 31 08:19:14 PM PDT 24 Jul 31 08:24:19 PM PDT 24 3071118590 ps
T1085 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.4175898527 Jul 31 08:32:40 PM PDT 24 Jul 31 08:39:18 PM PDT 24 7356569490 ps
T1086 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.531302788 Jul 31 08:15:40 PM PDT 24 Jul 31 08:22:24 PM PDT 24 2969953476 ps
T1087 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.4271064845 Jul 31 08:22:53 PM PDT 24 Jul 31 09:15:57 PM PDT 24 13395304700 ps
T333 /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3481125463 Jul 31 08:21:41 PM PDT 24 Jul 31 08:54:41 PM PDT 24 13688344024 ps
T766 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.151732297 Jul 31 08:43:43 PM PDT 24 Jul 31 08:50:21 PM PDT 24 4097584030 ps
T1088 /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.2104978544 Jul 31 08:18:44 PM PDT 24 Jul 31 08:42:14 PM PDT 24 7287407214 ps
T175 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.2945186956 Jul 31 08:19:38 PM PDT 24 Jul 31 08:21:26 PM PDT 24 2321252315 ps
T26 /workspace/coverage/default/0.chip_sw_usbdev_stream.3357050262 Jul 31 08:14:47 PM PDT 24 Jul 31 09:36:35 PM PDT 24 18459343656 ps
T1089 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.3781530123 Jul 31 08:34:28 PM PDT 24 Jul 31 08:45:57 PM PDT 24 8530795832 ps
T156 /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.1789278237 Jul 31 08:15:29 PM PDT 24 Jul 31 09:34:30 PM PDT 24 27638217708 ps
T1090 /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.2779439257 Jul 31 08:15:53 PM PDT 24 Jul 31 08:23:14 PM PDT 24 3823135804 ps
T1091 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4220378234 Jul 31 08:28:39 PM PDT 24 Jul 31 08:50:11 PM PDT 24 8497864378 ps
T764 /workspace/coverage/default/60.chip_sw_all_escalation_resets.1195759941 Jul 31 08:42:35 PM PDT 24 Jul 31 08:55:18 PM PDT 24 5678832840 ps
T1092 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.4042625925 Jul 31 08:21:20 PM PDT 24 Jul 31 09:20:44 PM PDT 24 16445577568 ps
T1093 /workspace/coverage/default/2.chip_sw_kmac_smoketest.2341525762 Jul 31 08:36:44 PM PDT 24 Jul 31 08:41:46 PM PDT 24 2248301880 ps
T1094 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1741598822 Jul 31 08:24:17 PM PDT 24 Jul 31 08:35:32 PM PDT 24 3942425280 ps
T793 /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1270725740 Jul 31 08:46:34 PM PDT 24 Jul 31 08:52:08 PM PDT 24 3689015044 ps
T1095 /workspace/coverage/default/25.chip_sw_all_escalation_resets.3225792241 Jul 31 08:41:57 PM PDT 24 Jul 31 08:51:39 PM PDT 24 4938965500 ps
T40 /workspace/coverage/default/0.chip_sw_spi_device_tpm.3643062141 Jul 31 08:14:05 PM PDT 24 Jul 31 08:20:00 PM PDT 24 3256088992 ps
T1096 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.3493899357 Jul 31 08:15:34 PM PDT 24 Jul 31 08:48:17 PM PDT 24 8387601772 ps
T1097 /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.3424808638 Jul 31 08:31:21 PM PDT 24 Jul 31 08:35:20 PM PDT 24 2903075444 ps
T267 /workspace/coverage/default/44.chip_sw_all_escalation_resets.837002635 Jul 31 08:43:11 PM PDT 24 Jul 31 08:56:09 PM PDT 24 6649855734 ps
T1098 /workspace/coverage/default/1.chip_sw_pattgen_ios.322626330 Jul 31 08:19:31 PM PDT 24 Jul 31 08:24:03 PM PDT 24 3715753010 ps
T1099 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.2076081178 Jul 31 08:30:40 PM PDT 24 Jul 31 08:42:04 PM PDT 24 4030306947 ps
T1100 /workspace/coverage/default/0.chip_sw_kmac_smoketest.2775214597 Jul 31 08:17:39 PM PDT 24 Jul 31 08:22:15 PM PDT 24 3201914804 ps
T97 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2808437494 Jul 31 08:42:50 PM PDT 24 Jul 31 08:49:45 PM PDT 24 3684852420 ps
T829 /workspace/coverage/default/15.chip_sw_all_escalation_resets.561797616 Jul 31 08:41:55 PM PDT 24 Jul 31 08:52:34 PM PDT 24 5200661300 ps
T1101 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.1442597948 Jul 31 08:21:19 PM PDT 24 Jul 31 08:46:50 PM PDT 24 9164530607 ps
T1102 /workspace/coverage/default/2.chip_sw_flash_crash_alert.2060092654 Jul 31 08:35:36 PM PDT 24 Jul 31 08:45:19 PM PDT 24 5262558684 ps
T1103 /workspace/coverage/default/96.chip_sw_all_escalation_resets.1403811820 Jul 31 08:46:21 PM PDT 24 Jul 31 08:57:19 PM PDT 24 4757658170 ps
T1104 /workspace/coverage/default/5.chip_sw_data_integrity_escalation.3023686840 Jul 31 08:40:15 PM PDT 24 Jul 31 08:51:42 PM PDT 24 5876805156 ps
T334 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1216983792 Jul 31 08:13:06 PM PDT 24 Jul 31 08:46:58 PM PDT 24 11991415720 ps
T1105 /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.323855789 Jul 31 08:41:55 PM PDT 24 Jul 31 08:50:27 PM PDT 24 3800369376 ps
T806 /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.906695063 Jul 31 08:41:08 PM PDT 24 Jul 31 08:47:13 PM PDT 24 3077700320 ps
T1106 /workspace/coverage/default/2.chip_sw_aes_masking_off.1458709228 Jul 31 08:32:03 PM PDT 24 Jul 31 08:36:22 PM PDT 24 2432068036 ps
T697 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.8557916 Jul 31 08:14:08 PM PDT 24 Jul 31 08:15:57 PM PDT 24 1968898390 ps
T1107 /workspace/coverage/default/0.chip_sw_aes_enc.445066782 Jul 31 08:16:16 PM PDT 24 Jul 31 08:21:18 PM PDT 24 2965470680 ps
T1108 /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.1493023575 Jul 31 08:15:14 PM PDT 24 Jul 31 09:44:16 PM PDT 24 27228967026 ps
T1109 /workspace/coverage/default/1.chip_sw_example_flash.1373543516 Jul 31 08:17:44 PM PDT 24 Jul 31 08:21:35 PM PDT 24 2804540140 ps
T1110 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.268762505 Jul 31 08:33:20 PM PDT 24 Jul 31 08:38:28 PM PDT 24 2961354686 ps
T1111 /workspace/coverage/default/4.chip_sw_data_integrity_escalation.2327024296 Jul 31 08:37:15 PM PDT 24 Jul 31 08:49:30 PM PDT 24 5383095112 ps
T810 /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3850578288 Jul 31 08:45:56 PM PDT 24 Jul 31 08:52:07 PM PDT 24 3663393400 ps
T1112 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.4049181830 Jul 31 08:15:15 PM PDT 24 Jul 31 08:30:53 PM PDT 24 5126654216 ps
T1113 /workspace/coverage/default/2.chip_sw_uart_smoketest.37198961 Jul 31 08:35:30 PM PDT 24 Jul 31 08:40:19 PM PDT 24 3079448520 ps
T783 /workspace/coverage/default/17.chip_sw_all_escalation_resets.1333411069 Jul 31 08:42:11 PM PDT 24 Jul 31 08:55:56 PM PDT 24 4811061336 ps
T1114 /workspace/coverage/default/2.chip_sw_hmac_multistream.4074939087 Jul 31 08:32:12 PM PDT 24 Jul 31 08:57:00 PM PDT 24 7261380854 ps
T1115 /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.2870787496 Jul 31 08:15:03 PM PDT 24 Jul 31 08:21:51 PM PDT 24 3335476164 ps
T1116 /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.251786343 Jul 31 08:31:16 PM PDT 24 Jul 31 09:15:19 PM PDT 24 12266935900 ps
T1117 /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.3006799843 Jul 31 08:15:59 PM PDT 24 Jul 31 08:20:08 PM PDT 24 2789853882 ps
T1118 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.2145574602 Jul 31 08:12:59 PM PDT 24 Jul 31 08:17:36 PM PDT 24 3161253065 ps
T345 /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.1725428875 Jul 31 08:31:48 PM PDT 24 Jul 31 08:39:05 PM PDT 24 3346005756 ps
T1119 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.1535629867 Jul 31 08:34:10 PM PDT 24 Jul 31 08:42:56 PM PDT 24 4214374692 ps
T1120 /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.1696584510 Jul 31 08:17:32 PM PDT 24 Jul 31 09:13:54 PM PDT 24 14672187167 ps
T769 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3878149451 Jul 31 08:45:18 PM PDT 24 Jul 31 08:52:19 PM PDT 24 3512267700 ps
T1121 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.3287681320 Jul 31 08:15:55 PM PDT 24 Jul 31 08:28:04 PM PDT 24 9551354912 ps
T1122 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2007025192 Jul 31 08:21:52 PM PDT 24 Jul 31 09:54:57 PM PDT 24 23078283480 ps
T1123 /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.1894716039 Jul 31 08:31:47 PM PDT 24 Jul 31 08:47:29 PM PDT 24 8161178064 ps
T1124 /workspace/coverage/default/2.chip_sival_flash_info_access.1946568201 Jul 31 08:26:37 PM PDT 24 Jul 31 08:30:48 PM PDT 24 2670692544 ps
T1125 /workspace/coverage/default/0.chip_sival_flash_info_access.1407550664 Jul 31 08:13:31 PM PDT 24 Jul 31 08:20:02 PM PDT 24 3694499700 ps
T1126 /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1471437373 Jul 31 08:36:30 PM PDT 24 Jul 31 08:42:32 PM PDT 24 5379305800 ps
T1127 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.1844515613 Jul 31 08:21:18 PM PDT 24 Jul 31 08:25:36 PM PDT 24 3067841996 ps
T1128 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.481103516 Jul 31 08:37:52 PM PDT 24 Jul 31 08:47:25 PM PDT 24 4812178174 ps
T1129 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.1679361888 Jul 31 08:35:34 PM PDT 24 Jul 31 08:57:54 PM PDT 24 5506252648 ps
T1130 /workspace/coverage/default/0.chip_sw_edn_sw_mode.3139576493 Jul 31 08:14:39 PM PDT 24 Jul 31 08:36:32 PM PDT 24 5663755280 ps
T1131 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4025365148 Jul 31 08:22:02 PM PDT 24 Jul 31 08:42:03 PM PDT 24 8623127287 ps
T316 /workspace/coverage/default/91.chip_sw_all_escalation_resets.2722670358 Jul 31 08:46:01 PM PDT 24 Jul 31 08:55:01 PM PDT 24 5158371726 ps
T802 /workspace/coverage/default/3.chip_sw_all_escalation_resets.2278399811 Jul 31 08:36:10 PM PDT 24 Jul 31 08:44:55 PM PDT 24 4808467130 ps
T1132 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.1611917990 Jul 31 08:11:47 PM PDT 24 Jul 31 08:37:43 PM PDT 24 9356320224 ps
T1133 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3638323590 Jul 31 08:37:11 PM PDT 24 Jul 31 08:59:59 PM PDT 24 13439768153 ps
T1134 /workspace/coverage/default/1.chip_sw_hmac_multistream.1200548903 Jul 31 08:21:57 PM PDT 24 Jul 31 08:55:49 PM PDT 24 8276653026 ps
T1135 /workspace/coverage/default/1.chip_sw_csrng_smoketest.69228200 Jul 31 08:28:32 PM PDT 24 Jul 31 08:32:40 PM PDT 24 2286105284 ps
T11 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3679281613 Jul 31 08:27:25 PM PDT 24 Jul 31 08:31:46 PM PDT 24 3081964774 ps
T1136 /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.3857988297 Jul 31 08:21:25 PM PDT 24 Jul 31 08:25:41 PM PDT 24 3446773300 ps
T1137 /workspace/coverage/default/0.chip_sw_flash_crash_alert.4146853540 Jul 31 08:15:27 PM PDT 24 Jul 31 08:27:28 PM PDT 24 5136618522 ps
T1138 /workspace/coverage/default/26.chip_sw_all_escalation_resets.539890698 Jul 31 08:41:02 PM PDT 24 Jul 31 08:52:37 PM PDT 24 4713313700 ps
T1139 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2995208480 Jul 31 08:14:22 PM PDT 24 Jul 31 08:19:34 PM PDT 24 2859721412 ps
T768 /workspace/coverage/default/19.chip_sw_all_escalation_resets.1559494964 Jul 31 08:42:21 PM PDT 24 Jul 31 08:54:21 PM PDT 24 6333586486 ps
T1140 /workspace/coverage/default/1.chip_sw_example_manufacturer.3423997766 Jul 31 08:18:13 PM PDT 24 Jul 31 08:21:37 PM PDT 24 3134281972 ps
T1141 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.552826284 Jul 31 08:15:00 PM PDT 24 Jul 31 11:23:25 PM PDT 24 65522268741 ps
T391 /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.3466807175 Jul 31 08:15:10 PM PDT 24 Jul 31 08:17:09 PM PDT 24 2199224042 ps
T1142 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.3357839903 Jul 31 08:26:01 PM PDT 24 Jul 31 09:49:40 PM PDT 24 22748450650 ps
T1143 /workspace/coverage/default/1.chip_tap_straps_prod.3355818715 Jul 31 08:24:13 PM PDT 24 Jul 31 08:47:39 PM PDT 24 12675459751 ps
T1144 /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.15056808 Jul 31 08:27:20 PM PDT 24 Jul 31 08:31:43 PM PDT 24 2533207000 ps
T1145 /workspace/coverage/default/52.chip_sw_all_escalation_resets.4151196059 Jul 31 08:46:02 PM PDT 24 Jul 31 08:55:58 PM PDT 24 4916243704 ps
T1146 /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2465514975 Jul 31 08:16:01 PM PDT 24 Jul 31 08:28:22 PM PDT 24 9575799104 ps
T1147 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.3863124318 Jul 31 08:33:52 PM PDT 24 Jul 31 08:43:28 PM PDT 24 4198706000 ps
T280 /workspace/coverage/default/1.chip_sw_data_integrity_escalation.4093684284 Jul 31 08:17:53 PM PDT 24 Jul 31 08:29:21 PM PDT 24 4778118278 ps
T1148 /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.907329896 Jul 31 08:25:47 PM PDT 24 Jul 31 08:57:07 PM PDT 24 27082836684 ps
T297 /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3172609701 Jul 31 08:46:23 PM PDT 24 Jul 31 08:54:41 PM PDT 24 3550771754 ps
T1149 /workspace/coverage/default/0.chip_sw_rv_timer_irq.2549238098 Jul 31 08:13:02 PM PDT 24 Jul 31 08:17:28 PM PDT 24 2700351500 ps
T1150 /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.1404971358 Jul 31 08:24:40 PM PDT 24 Jul 31 08:33:26 PM PDT 24 4614002856 ps
T112 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.2274632722 Jul 31 08:27:44 PM PDT 24 Jul 31 08:37:26 PM PDT 24 6689513600 ps
T424 /workspace/coverage/default/2.chip_sw_hmac_oneshot.2278998420 Jul 31 08:33:06 PM PDT 24 Jul 31 08:40:37 PM PDT 24 3487437544 ps
T425 /workspace/coverage/default/20.chip_sw_all_escalation_resets.293756219 Jul 31 08:42:30 PM PDT 24 Jul 31 08:56:37 PM PDT 24 5279373400 ps
T426 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.1751789822 Jul 31 08:41:37 PM PDT 24 Jul 31 09:07:41 PM PDT 24 8200451708 ps
T427 /workspace/coverage/default/0.chip_sw_csrng_smoketest.3283927479 Jul 31 08:17:21 PM PDT 24 Jul 31 08:20:42 PM PDT 24 2277806800 ps
T428 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.247691781 Jul 31 08:33:53 PM PDT 24 Jul 31 08:41:34 PM PDT 24 3298462280 ps
T429 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.235379550 Jul 31 08:17:00 PM PDT 24 Jul 31 08:20:05 PM PDT 24 2527192286 ps
T430 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.4201252078 Jul 31 08:25:30 PM PDT 24 Jul 31 08:29:29 PM PDT 24 3016842743 ps
T431 /workspace/coverage/default/0.chip_sw_example_concurrency.1404753715 Jul 31 08:13:27 PM PDT 24 Jul 31 08:19:32 PM PDT 24 2729065646 ps
T432 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2562114400 Jul 31 08:40:30 PM PDT 24 Jul 31 08:48:17 PM PDT 24 4529296714 ps
T1151 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3403818690 Jul 31 08:36:33 PM PDT 24 Jul 31 08:44:46 PM PDT 24 4509581055 ps
T1152 /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.3382492525 Jul 31 08:29:32 PM PDT 24 Jul 31 08:56:43 PM PDT 24 11109571882 ps
T822 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2579833400 Jul 31 08:42:39 PM PDT 24 Jul 31 08:48:30 PM PDT 24 3382767112 ps
T1153 /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.1674352295 Jul 31 08:26:52 PM PDT 24 Jul 31 08:31:31 PM PDT 24 2906972600 ps
T1154 /workspace/coverage/default/0.chip_sw_kmac_idle.2424446325 Jul 31 08:13:59 PM PDT 24 Jul 31 08:18:04 PM PDT 24 2873126788 ps
T1155 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.889107981 Jul 31 08:27:40 PM PDT 24 Jul 31 09:25:33 PM PDT 24 24941544537 ps
T246 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.2658782994 Jul 31 08:19:42 PM PDT 24 Jul 31 09:50:48 PM PDT 24 51112590774 ps
T409 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3542176951 Jul 31 08:23:47 PM PDT 24 Jul 31 08:48:51 PM PDT 24 25842861306 ps
T408 /workspace/coverage/default/45.chip_sw_all_escalation_resets.3164371461 Jul 31 08:42:12 PM PDT 24 Jul 31 08:54:27 PM PDT 24 5513230880 ps
T98 /workspace/coverage/default/4.chip_sw_all_escalation_resets.1260113759 Jul 31 08:36:46 PM PDT 24 Jul 31 08:46:09 PM PDT 24 4387872292 ps
T1156 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.1109961837 Jul 31 08:32:15 PM PDT 24 Jul 31 08:56:34 PM PDT 24 7746690644 ps
T773 /workspace/coverage/default/67.chip_sw_all_escalation_resets.1305302576 Jul 31 08:43:32 PM PDT 24 Jul 31 08:52:28 PM PDT 24 5104437570 ps
T733 /workspace/coverage/default/69.chip_sw_all_escalation_resets.397909870 Jul 31 08:44:20 PM PDT 24 Jul 31 08:53:11 PM PDT 24 4704854820 ps
T1157 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.3808634508 Jul 31 08:42:36 PM PDT 24 Jul 31 08:50:58 PM PDT 24 4089518248 ps
T1158 /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2548904690 Jul 31 08:16:09 PM PDT 24 Jul 31 11:36:20 PM PDT 24 255874128080 ps
T1159 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.614458627 Jul 31 08:25:49 PM PDT 24 Jul 31 08:33:17 PM PDT 24 5893512606 ps
T1160 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.4139587444 Jul 31 08:36:37 PM PDT 24 Jul 31 08:42:50 PM PDT 24 3735051608 ps
T1161 /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.1174193887 Jul 31 08:38:56 PM PDT 24 Jul 31 09:44:07 PM PDT 24 13963633893 ps
T335 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1738007981 Jul 31 08:30:12 PM PDT 24 Jul 31 08:55:21 PM PDT 24 12418998628 ps
T206 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.2547867127 Jul 31 08:18:34 PM PDT 24 Jul 31 08:33:25 PM PDT 24 6912613981 ps
T1162 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3557845453 Jul 31 08:23:34 PM PDT 24 Jul 31 08:33:11 PM PDT 24 4008613776 ps
T789 /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2578245234 Jul 31 08:46:38 PM PDT 24 Jul 31 08:52:03 PM PDT 24 3414542060 ps
T803 /workspace/coverage/default/84.chip_sw_all_escalation_resets.3126156966 Jul 31 08:46:00 PM PDT 24 Jul 31 08:55:51 PM PDT 24 6029980200 ps
T1163 /workspace/coverage/default/30.chip_sw_all_escalation_resets.745054143 Jul 31 08:41:42 PM PDT 24 Jul 31 08:51:41 PM PDT 24 4477650522 ps
T1164 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2972312530 Jul 31 08:21:06 PM PDT 24 Jul 31 09:17:06 PM PDT 24 15354153700 ps
T1165 /workspace/coverage/default/2.chip_sw_example_rom.762491523 Jul 31 08:25:59 PM PDT 24 Jul 31 08:28:21 PM PDT 24 2161010812 ps
T808 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2981926629 Jul 31 08:42:12 PM PDT 24 Jul 31 08:49:33 PM PDT 24 3421006328 ps
T207 /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.4025721925 Jul 31 08:31:43 PM PDT 24 Jul 31 08:43:33 PM PDT 24 4413329830 ps
T1166 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.3869041061 Jul 31 08:19:31 PM PDT 24 Jul 31 09:34:25 PM PDT 24 18042698888 ps
T1167 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.2294664638 Jul 31 08:36:34 PM PDT 24 Jul 31 08:44:36 PM PDT 24 6808125656 ps
T1168 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.806369015 Jul 31 08:21:51 PM PDT 24 Jul 31 09:15:22 PM PDT 24 39166693768 ps
T1169 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.173951024 Jul 31 08:31:51 PM PDT 24 Jul 31 09:34:53 PM PDT 24 14649269776 ps
T68 /workspace/coverage/default/1.chip_tap_straps_rma.13816774 Jul 31 08:24:34 PM PDT 24 Jul 31 08:30:03 PM PDT 24 3387679734 ps
T1170 /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2408194094 Jul 31 08:14:01 PM PDT 24 Jul 31 08:22:36 PM PDT 24 3932780724 ps
T317 /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3759806351 Jul 31 08:41:36 PM PDT 24 Jul 31 08:49:42 PM PDT 24 4062718720 ps
T1171 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.1953907956 Jul 31 08:13:37 PM PDT 24 Jul 31 08:19:19 PM PDT 24 3531689056 ps
T1172 /workspace/coverage/default/1.rom_e2e_asm_init_prod.1269269235 Jul 31 08:31:09 PM PDT 24 Jul 31 09:40:57 PM PDT 24 15390339304 ps
T41 /workspace/coverage/default/2.chip_sw_spi_device_tpm.678650524 Jul 31 08:29:03 PM PDT 24 Jul 31 08:36:20 PM PDT 24 3417106001 ps
T1173 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1329812212 Jul 31 08:13:41 PM PDT 24 Jul 31 08:41:58 PM PDT 24 13128723868 ps
T1174 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.2473992045 Jul 31 08:30:25 PM PDT 24 Jul 31 08:41:18 PM PDT 24 5879349146 ps
T1175 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.1250094692 Jul 31 08:16:52 PM PDT 24 Jul 31 08:24:16 PM PDT 24 3149698820 ps
T1176 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.250529498 Jul 31 08:22:42 PM PDT 24 Jul 31 09:29:52 PM PDT 24 15426173370 ps
T1177 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.2353997953 Jul 31 08:32:36 PM PDT 24 Jul 31 08:42:06 PM PDT 24 5327560952 ps
T1178 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.4252838411 Jul 31 08:15:56 PM PDT 24 Jul 31 09:25:02 PM PDT 24 18668838876 ps
T1179 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3598026533 Jul 31 08:13:51 PM PDT 24 Jul 31 08:59:37 PM PDT 24 28622428638 ps
T1180 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.1729258121 Jul 31 08:33:40 PM PDT 24 Jul 31 09:35:29 PM PDT 24 14906172408 ps
T1181 /workspace/coverage/default/0.chip_sw_gpio_smoketest.2128104828 Jul 31 08:20:35 PM PDT 24 Jul 31 08:25:17 PM PDT 24 2608052403 ps
T318 /workspace/coverage/default/76.chip_sw_all_escalation_resets.2510516749 Jul 31 08:45:40 PM PDT 24 Jul 31 08:58:05 PM PDT 24 5867360520 ps
T1182 /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.2627807537 Jul 31 08:26:42 PM PDT 24 Jul 31 08:29:52 PM PDT 24 2137186054 ps
T361 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2134860630 Jul 31 08:13:01 PM PDT 24 Jul 31 08:26:37 PM PDT 24 4390197550 ps
T827 /workspace/coverage/default/50.chip_sw_all_escalation_resets.4084246373 Jul 31 08:42:36 PM PDT 24 Jul 31 08:54:04 PM PDT 24 5304602026 ps
T1183 /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1670625884 Jul 31 08:14:50 PM PDT 24 Jul 31 08:25:10 PM PDT 24 5881355176 ps
T780 /workspace/coverage/default/18.chip_sw_all_escalation_resets.2833294281 Jul 31 08:41:15 PM PDT 24 Jul 31 08:52:17 PM PDT 24 6248902816 ps
T1184 /workspace/coverage/default/0.chip_sw_flash_init.388120704 Jul 31 08:12:53 PM PDT 24 Jul 31 08:47:43 PM PDT 24 19149789316 ps
T1185 /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.2396843268 Jul 31 08:35:32 PM PDT 24 Jul 31 08:40:52 PM PDT 24 3235340050 ps
T1186 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.3159129769 Jul 31 08:21:02 PM PDT 24 Jul 31 08:23:44 PM PDT 24 2537842794 ps
T819 /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3169286907 Jul 31 08:43:44 PM PDT 24 Jul 31 08:49:56 PM PDT 24 3700142292 ps
T349 /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.1107550403 Jul 31 08:16:04 PM PDT 24 Jul 31 08:22:12 PM PDT 24 3651496460 ps
T1187 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1295908692 Jul 31 08:16:04 PM PDT 24 Jul 31 08:24:47 PM PDT 24 4519058358 ps
T743 /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3739510688 Jul 31 08:44:51 PM PDT 24 Jul 31 08:51:15 PM PDT 24 4177714402 ps
T698 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.945592754 Jul 31 08:21:44 PM PDT 24 Jul 31 08:23:59 PM PDT 24 2389398485 ps
T308 /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3170335470 Jul 31 08:24:34 PM PDT 24 Jul 31 08:35:08 PM PDT 24 4762823720 ps
T1188 /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.4277473240 Jul 31 08:39:19 PM PDT 24 Jul 31 08:52:35 PM PDT 24 10831685745 ps
T1189 /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2802150330 Jul 31 08:12:07 PM PDT 24 Jul 31 08:18:01 PM PDT 24 4261779443 ps
T1190 /workspace/coverage/default/2.chip_tap_straps_prod.3966535275 Jul 31 08:34:54 PM PDT 24 Jul 31 08:37:58 PM PDT 24 2524558997 ps
T1191 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3861906867 Jul 31 08:15:17 PM PDT 24 Jul 31 08:25:59 PM PDT 24 4288808262 ps
T1192 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2136084800 Jul 31 08:30:20 PM PDT 24 Jul 31 08:56:16 PM PDT 24 15154797940 ps
T168 /workspace/coverage/default/2.chip_plic_all_irqs_10.3646169009 Jul 31 08:38:03 PM PDT 24 Jul 31 08:47:07 PM PDT 24 3677705194 ps
T123 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.1119210695 Jul 31 08:12:06 PM PDT 24 Jul 31 08:16:35 PM PDT 24 3102390088 ps
T1193 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1772580662 Jul 31 08:18:00 PM PDT 24 Jul 31 08:30:23 PM PDT 24 6719161956 ps
T1194 /workspace/coverage/default/1.chip_sw_aes_idle.3288819844 Jul 31 08:23:26 PM PDT 24 Jul 31 08:28:12 PM PDT 24 2555389248 ps
T725 /workspace/coverage/default/0.rom_raw_unlock.578559595 Jul 31 08:18:48 PM PDT 24 Jul 31 08:22:51 PM PDT 24 6033491972 ps
T1195 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.768916934 Jul 31 08:22:28 PM PDT 24 Jul 31 08:52:50 PM PDT 24 22612363610 ps
T362 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.1699651681 Jul 31 08:31:48 PM PDT 24 Jul 31 08:47:01 PM PDT 24 5202123260 ps
T1196 /workspace/coverage/default/2.rom_e2e_shutdown_output.679709769 Jul 31 08:40:20 PM PDT 24 Jul 31 09:30:50 PM PDT 24 30895568885 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%