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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.14 95.47 94.02 95.38 94.92 97.53 99.52


Total test records in report: 2935
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T709 /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.118264877 Aug 02 07:58:36 PM PDT 24 Aug 02 08:19:40 PM PDT 24 30499547912 ps
T2765 /workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.1686139125 Aug 02 07:56:04 PM PDT 24 Aug 02 07:57:17 PM PDT 24 6656784146 ps
T2766 /workspace/coverage/cover_reg_top/98.xbar_unmapped_addr.1208171751 Aug 02 08:09:35 PM PDT 24 Aug 02 08:09:57 PM PDT 24 491808982 ps
T2767 /workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.3528383837 Aug 02 08:07:26 PM PDT 24 Aug 02 08:10:24 PM PDT 24 10227095079 ps
T2768 /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.2230457542 Aug 02 08:03:01 PM PDT 24 Aug 02 08:03:45 PM PDT 24 197676285 ps
T2769 /workspace/coverage/cover_reg_top/31.xbar_smoke.4051041974 Aug 02 07:58:24 PM PDT 24 Aug 02 07:58:30 PM PDT 24 44043332 ps
T2770 /workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.892055498 Aug 02 07:57:31 PM PDT 24 Aug 02 08:05:36 PM PDT 24 27072471782 ps
T2771 /workspace/coverage/cover_reg_top/45.xbar_random.1601263627 Aug 02 08:00:42 PM PDT 24 Aug 02 08:01:15 PM PDT 24 405722660 ps
T2772 /workspace/coverage/cover_reg_top/85.xbar_random_large_delays.608230966 Aug 02 08:07:12 PM PDT 24 Aug 02 08:16:08 PM PDT 24 51639301480 ps
T2773 /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.3429970763 Aug 02 07:53:34 PM PDT 24 Aug 02 08:02:00 PM PDT 24 4467413444 ps
T2774 /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.2504730949 Aug 02 08:02:43 PM PDT 24 Aug 02 08:21:33 PM PDT 24 109518461422 ps
T2775 /workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.1022653680 Aug 02 08:00:35 PM PDT 24 Aug 02 08:34:20 PM PDT 24 110705407590 ps
T2776 /workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.158477201 Aug 02 08:04:40 PM PDT 24 Aug 02 08:05:15 PM PDT 24 942404107 ps
T2777 /workspace/coverage/cover_reg_top/82.xbar_stress_all.2641165712 Aug 02 08:07:01 PM PDT 24 Aug 02 08:16:32 PM PDT 24 15592065357 ps
T2778 /workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.4050236534 Aug 02 08:00:20 PM PDT 24 Aug 02 08:26:21 PM PDT 24 84926323677 ps
T2779 /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.1810804895 Aug 02 08:06:13 PM PDT 24 Aug 02 08:08:21 PM PDT 24 1419882737 ps
T2780 /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.2480591142 Aug 02 07:53:14 PM PDT 24 Aug 02 07:55:05 PM PDT 24 301714257 ps
T2781 /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.285837767 Aug 02 08:06:03 PM PDT 24 Aug 02 08:11:33 PM PDT 24 6636680473 ps
T2782 /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.2791593762 Aug 02 08:09:22 PM PDT 24 Aug 02 08:16:02 PM PDT 24 8735183147 ps
T2783 /workspace/coverage/cover_reg_top/69.xbar_smoke_large_delays.3141315383 Aug 02 08:04:46 PM PDT 24 Aug 02 08:06:22 PM PDT 24 8715610518 ps
T2784 /workspace/coverage/cover_reg_top/67.xbar_same_source.1739910036 Aug 02 08:04:24 PM PDT 24 Aug 02 08:04:32 PM PDT 24 75112950 ps
T2785 /workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.1508756776 Aug 02 08:07:49 PM PDT 24 Aug 02 08:09:07 PM PDT 24 4663568125 ps
T2786 /workspace/coverage/cover_reg_top/60.xbar_access_same_device.668486912 Aug 02 08:03:22 PM PDT 24 Aug 02 08:04:43 PM PDT 24 2421839644 ps
T2787 /workspace/coverage/cover_reg_top/93.xbar_error_random.1147824138 Aug 02 08:09:04 PM PDT 24 Aug 02 08:09:09 PM PDT 24 36667003 ps
T2788 /workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.2153962984 Aug 02 08:07:31 PM PDT 24 Aug 02 08:08:14 PM PDT 24 554431505 ps
T2789 /workspace/coverage/cover_reg_top/62.xbar_access_same_device.1963389323 Aug 02 08:03:40 PM PDT 24 Aug 02 08:04:00 PM PDT 24 186805679 ps
T2790 /workspace/coverage/cover_reg_top/2.chip_tl_errors.4017217199 Aug 02 07:51:53 PM PDT 24 Aug 02 07:53:25 PM PDT 24 2690659348 ps
T2791 /workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.1610489673 Aug 02 07:53:53 PM PDT 24 Aug 02 07:55:14 PM PDT 24 7640875192 ps
T2792 /workspace/coverage/cover_reg_top/55.xbar_smoke.4067673623 Aug 02 08:02:35 PM PDT 24 Aug 02 08:02:47 PM PDT 24 275488833 ps
T2793 /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.2057940033 Aug 02 08:04:07 PM PDT 24 Aug 02 08:07:22 PM PDT 24 836433394 ps
T2794 /workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.4258977537 Aug 02 08:08:40 PM PDT 24 Aug 02 08:09:35 PM PDT 24 633677618 ps
T2795 /workspace/coverage/cover_reg_top/41.xbar_smoke.341722325 Aug 02 08:00:10 PM PDT 24 Aug 02 08:00:18 PM PDT 24 173165575 ps
T2796 /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.3981262953 Aug 02 07:55:48 PM PDT 24 Aug 02 08:05:12 PM PDT 24 15591061833 ps
T2797 /workspace/coverage/cover_reg_top/40.xbar_access_same_device.3946263513 Aug 02 07:59:57 PM PDT 24 Aug 02 08:01:04 PM PDT 24 1698795311 ps
T2798 /workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.3701668838 Aug 02 07:55:21 PM PDT 24 Aug 02 08:18:49 PM PDT 24 13771723177 ps
T2799 /workspace/coverage/cover_reg_top/4.xbar_error_random.84784376 Aug 02 07:52:25 PM PDT 24 Aug 02 07:53:20 PM PDT 24 1623392246 ps
T2800 /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.2498232564 Aug 02 07:59:01 PM PDT 24 Aug 02 08:03:37 PM PDT 24 5500055145 ps
T2801 /workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.527819920 Aug 02 08:03:18 PM PDT 24 Aug 02 08:03:43 PM PDT 24 529627016 ps
T2802 /workspace/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.1009184725 Aug 02 07:58:47 PM PDT 24 Aug 02 07:59:19 PM PDT 24 770014698 ps
T2803 /workspace/coverage/cover_reg_top/82.xbar_unmapped_addr.2977970572 Aug 02 08:07:07 PM PDT 24 Aug 02 08:07:14 PM PDT 24 42491850 ps
T2804 /workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.2103161682 Aug 02 08:02:44 PM PDT 24 Aug 02 08:02:59 PM PDT 24 340190024 ps
T2805 /workspace/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.850951311 Aug 02 08:02:34 PM PDT 24 Aug 02 08:04:05 PM PDT 24 5792319106 ps
T2806 /workspace/coverage/cover_reg_top/81.xbar_access_same_device.1266976262 Aug 02 08:06:45 PM PDT 24 Aug 02 08:07:18 PM PDT 24 921127830 ps
T2807 /workspace/coverage/cover_reg_top/78.xbar_random_large_delays.1069846713 Aug 02 08:05:59 PM PDT 24 Aug 02 08:07:40 PM PDT 24 9975262969 ps
T2808 /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.3373082221 Aug 02 08:05:13 PM PDT 24 Aug 02 08:08:11 PM PDT 24 1634596018 ps
T2809 /workspace/coverage/cover_reg_top/86.xbar_smoke_zero_delays.3315583396 Aug 02 08:07:25 PM PDT 24 Aug 02 08:07:31 PM PDT 24 45267502 ps
T2810 /workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.2915957465 Aug 02 07:55:36 PM PDT 24 Aug 02 07:56:58 PM PDT 24 5132571198 ps
T134 /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.2136244306 Aug 02 07:52:21 PM PDT 24 Aug 02 07:55:57 PM PDT 24 5218415082 ps
T2811 /workspace/coverage/cover_reg_top/6.xbar_same_source.2631671371 Aug 02 07:52:49 PM PDT 24 Aug 02 07:53:32 PM PDT 24 1523590424 ps
T2812 /workspace/coverage/cover_reg_top/50.xbar_same_source.3531222605 Aug 02 08:01:40 PM PDT 24 Aug 02 08:02:16 PM PDT 24 467192589 ps
T2813 /workspace/coverage/cover_reg_top/43.xbar_error_random.2921453314 Aug 02 08:00:31 PM PDT 24 Aug 02 08:00:40 PM PDT 24 74872863 ps
T2814 /workspace/coverage/cover_reg_top/32.xbar_random_large_delays.3785730295 Aug 02 07:58:40 PM PDT 24 Aug 02 08:10:45 PM PDT 24 72402273825 ps
T2815 /workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.36631445 Aug 02 07:54:43 PM PDT 24 Aug 02 07:55:29 PM PDT 24 1226784609 ps
T2816 /workspace/coverage/cover_reg_top/9.xbar_same_source.425606445 Aug 02 07:53:48 PM PDT 24 Aug 02 07:54:39 PM PDT 24 1803345056 ps
T2817 /workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.288704393 Aug 02 08:08:41 PM PDT 24 Aug 02 08:08:47 PM PDT 24 46973349 ps
T2818 /workspace/coverage/cover_reg_top/44.xbar_stress_all.1063681324 Aug 02 08:00:45 PM PDT 24 Aug 02 08:01:10 PM PDT 24 734269057 ps
T2819 /workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.993716651 Aug 02 08:06:03 PM PDT 24 Aug 02 08:06:43 PM PDT 24 480281616 ps
T2820 /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.3739836252 Aug 02 07:59:27 PM PDT 24 Aug 02 08:08:22 PM PDT 24 14343989068 ps
T2821 /workspace/coverage/cover_reg_top/69.xbar_smoke.2651370253 Aug 02 08:04:47 PM PDT 24 Aug 02 08:04:54 PM PDT 24 44076390 ps
T2822 /workspace/coverage/cover_reg_top/36.xbar_same_source.2946701011 Aug 02 07:59:33 PM PDT 24 Aug 02 07:59:45 PM PDT 24 132887837 ps
T2823 /workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.991907424 Aug 02 07:52:23 PM PDT 24 Aug 02 08:28:24 PM PDT 24 15512704532 ps
T2824 /workspace/coverage/cover_reg_top/57.xbar_stress_all.2629354723 Aug 02 08:02:44 PM PDT 24 Aug 02 08:06:05 PM PDT 24 6148119552 ps
T2825 /workspace/coverage/cover_reg_top/5.xbar_random_zero_delays.3562011930 Aug 02 07:52:26 PM PDT 24 Aug 02 07:53:20 PM PDT 24 603024431 ps
T2826 /workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.143731839 Aug 02 08:04:57 PM PDT 24 Aug 02 08:05:08 PM PDT 24 97477733 ps
T2827 /workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.438067803 Aug 02 08:09:24 PM PDT 24 Aug 02 08:10:25 PM PDT 24 6232289310 ps
T2828 /workspace/coverage/cover_reg_top/41.xbar_random_large_delays.2307499403 Aug 02 08:00:09 PM PDT 24 Aug 02 08:09:57 PM PDT 24 51312976682 ps
T2829 /workspace/coverage/cover_reg_top/6.xbar_unmapped_addr.3778542349 Aug 02 07:52:48 PM PDT 24 Aug 02 07:53:29 PM PDT 24 921207688 ps
T648 /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.2868668536 Aug 02 08:05:53 PM PDT 24 Aug 02 08:21:53 PM PDT 24 22667487755 ps
T2830 /workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.1046643275 Aug 02 08:09:48 PM PDT 24 Aug 02 08:09:54 PM PDT 24 39681255 ps
T2831 /workspace/coverage/cover_reg_top/10.xbar_random_large_delays.3623712832 Aug 02 07:53:50 PM PDT 24 Aug 02 07:55:54 PM PDT 24 11472591867 ps
T2832 /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.2070028488 Aug 02 07:54:39 PM PDT 24 Aug 02 08:01:34 PM PDT 24 9274828189 ps
T2833 /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.2318793358 Aug 02 07:52:29 PM PDT 24 Aug 02 07:55:09 PM PDT 24 351458748 ps
T2834 /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.2370517530 Aug 02 08:03:38 PM PDT 24 Aug 02 08:06:08 PM PDT 24 4747216060 ps
T2835 /workspace/coverage/cover_reg_top/27.xbar_random_large_delays.313077715 Aug 02 07:57:33 PM PDT 24 Aug 02 07:58:45 PM PDT 24 6929058480 ps
T2836 /workspace/coverage/cover_reg_top/63.xbar_stress_all.1873324400 Aug 02 08:04:06 PM PDT 24 Aug 02 08:07:35 PM PDT 24 5705717143 ps
T2837 /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.3871641986 Aug 02 08:07:01 PM PDT 24 Aug 02 08:20:05 PM PDT 24 16848641964 ps
T2838 /workspace/coverage/cover_reg_top/88.xbar_stress_all.1191220273 Aug 02 08:07:50 PM PDT 24 Aug 02 08:08:14 PM PDT 24 316628901 ps
T2839 /workspace/coverage/cover_reg_top/34.xbar_smoke_zero_delays.1175751641 Aug 02 07:58:47 PM PDT 24 Aug 02 07:58:53 PM PDT 24 45546994 ps
T2840 /workspace/coverage/cover_reg_top/78.xbar_random_slow_rsp.379704470 Aug 02 08:05:59 PM PDT 24 Aug 02 08:17:05 PM PDT 24 40993989340 ps
T2841 /workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.3285555545 Aug 02 08:03:01 PM PDT 24 Aug 02 08:10:18 PM PDT 24 24801901755 ps
T2842 /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.625243694 Aug 02 07:59:28 PM PDT 24 Aug 02 08:01:07 PM PDT 24 5688620326 ps
T2843 /workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.2391210403 Aug 02 07:54:15 PM PDT 24 Aug 02 07:55:08 PM PDT 24 3548738436 ps
T2844 /workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.1183481790 Aug 02 07:52:23 PM PDT 24 Aug 02 07:53:39 PM PDT 24 7489881932 ps
T2845 /workspace/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.1044167505 Aug 02 08:02:43 PM PDT 24 Aug 02 08:03:14 PM PDT 24 833132083 ps
T2846 /workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.405367348 Aug 02 07:51:50 PM PDT 24 Aug 02 07:52:04 PM PDT 24 335011913 ps
T2847 /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_error.3335690222 Aug 02 07:52:59 PM PDT 24 Aug 02 07:58:33 PM PDT 24 4742091412 ps
T2848 /workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.4278056924 Aug 02 07:58:35 PM PDT 24 Aug 02 08:00:22 PM PDT 24 10606763016 ps
T2849 /workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.2808155973 Aug 02 07:51:46 PM PDT 24 Aug 02 07:52:03 PM PDT 24 131757006 ps
T2850 /workspace/coverage/cover_reg_top/3.xbar_same_source.380485194 Aug 02 07:52:20 PM PDT 24 Aug 02 07:52:59 PM PDT 24 525724863 ps
T2851 /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.4200124825 Aug 02 07:54:04 PM PDT 24 Aug 02 08:02:50 PM PDT 24 9748227383 ps
T2852 /workspace/coverage/cover_reg_top/0.xbar_error_random.2818581831 Aug 02 07:51:48 PM PDT 24 Aug 02 07:51:54 PM PDT 24 41577033 ps
T2853 /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.688904089 Aug 02 08:09:52 PM PDT 24 Aug 02 08:10:39 PM PDT 24 700519981 ps
T2854 /workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.333964057 Aug 02 07:59:57 PM PDT 24 Aug 02 08:04:55 PM PDT 24 19956232572 ps
T2855 /workspace/coverage/cover_reg_top/6.xbar_smoke_large_delays.3934967348 Aug 02 07:52:47 PM PDT 24 Aug 02 07:54:22 PM PDT 24 9048086349 ps
T2856 /workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.4268020364 Aug 02 07:54:40 PM PDT 24 Aug 02 07:56:05 PM PDT 24 5463382947 ps
T2857 /workspace/coverage/cover_reg_top/4.xbar_unmapped_addr.3913200587 Aug 02 07:52:31 PM PDT 24 Aug 02 07:52:42 PM PDT 24 77922165 ps
T2858 /workspace/coverage/cover_reg_top/71.xbar_random_slow_rsp.2944219144 Aug 02 08:04:57 PM PDT 24 Aug 02 08:14:53 PM PDT 24 32926459414 ps
T2859 /workspace/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.587252144 Aug 02 07:52:29 PM PDT 24 Aug 02 08:05:44 PM PDT 24 10523966490 ps
T2860 /workspace/coverage/cover_reg_top/22.xbar_smoke.1048588444 Aug 02 07:56:29 PM PDT 24 Aug 02 07:56:35 PM PDT 24 50328144 ps
T130 /workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.2987112239 Aug 02 07:51:48 PM PDT 24 Aug 02 07:58:47 PM PDT 24 8153921015 ps
T2861 /workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.3817545831 Aug 02 08:04:24 PM PDT 24 Aug 02 08:04:52 PM PDT 24 283983171 ps
T2862 /workspace/coverage/cover_reg_top/58.xbar_smoke.2210029745 Aug 02 08:02:53 PM PDT 24 Aug 02 08:03:02 PM PDT 24 212404612 ps
T2863 /workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.1749546579 Aug 02 07:58:38 PM PDT 24 Aug 02 07:59:15 PM PDT 24 448017487 ps
T2864 /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.2132281022 Aug 02 07:59:53 PM PDT 24 Aug 02 08:05:50 PM PDT 24 10344000723 ps
T2865 /workspace/coverage/cover_reg_top/68.xbar_stress_all.3418779173 Aug 02 08:04:43 PM PDT 24 Aug 02 08:08:08 PM PDT 24 5645680403 ps
T2866 /workspace/coverage/cover_reg_top/82.xbar_access_same_device.719239613 Aug 02 08:07:02 PM PDT 24 Aug 02 08:08:20 PM PDT 24 2015879869 ps
T2867 /workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.2560641758 Aug 02 08:03:41 PM PDT 24 Aug 02 08:03:58 PM PDT 24 383836135 ps
T2868 /workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.4161596709 Aug 02 07:55:48 PM PDT 24 Aug 02 07:55:54 PM PDT 24 41814767 ps
T2869 /workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.2420719566 Aug 02 08:02:49 PM PDT 24 Aug 02 08:02:55 PM PDT 24 41991720 ps
T2870 /workspace/coverage/cover_reg_top/79.xbar_stress_all.1449342925 Aug 02 08:06:31 PM PDT 24 Aug 02 08:09:01 PM PDT 24 1924115816 ps
T2871 /workspace/coverage/cover_reg_top/32.xbar_random.3031948241 Aug 02 07:58:40 PM PDT 24 Aug 02 07:59:36 PM PDT 24 1745421119 ps
T2872 /workspace/coverage/cover_reg_top/52.xbar_access_same_device.1909452915 Aug 02 08:02:04 PM PDT 24 Aug 02 08:03:37 PM PDT 24 1354032979 ps
T2873 /workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.613287604 Aug 02 08:07:51 PM PDT 24 Aug 02 08:40:43 PM PDT 24 111633959170 ps
T2874 /workspace/coverage/cover_reg_top/14.xbar_random_large_delays.3939875790 Aug 02 07:54:30 PM PDT 24 Aug 02 07:58:28 PM PDT 24 22868244507 ps
T2875 /workspace/coverage/cover_reg_top/65.xbar_random.2954886208 Aug 02 08:04:07 PM PDT 24 Aug 02 08:04:14 PM PDT 24 123739089 ps
T2876 /workspace/coverage/cover_reg_top/64.xbar_smoke.2896450748 Aug 02 08:03:55 PM PDT 24 Aug 02 08:04:04 PM PDT 24 212736773 ps
T2877 /workspace/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.3948469261 Aug 02 08:06:03 PM PDT 24 Aug 02 08:06:35 PM PDT 24 846140542 ps
T2878 /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.316291688 Aug 02 07:55:44 PM PDT 24 Aug 02 08:01:34 PM PDT 24 10380117224 ps
T2879 /workspace/coverage/cover_reg_top/29.xbar_random_zero_delays.958752546 Aug 02 07:58:10 PM PDT 24 Aug 02 07:58:28 PM PDT 24 184103509 ps
T2880 /workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.1607662183 Aug 02 07:54:29 PM PDT 24 Aug 02 07:59:04 PM PDT 24 16051134829 ps
T2881 /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.2248984707 Aug 02 07:57:09 PM PDT 24 Aug 02 07:58:24 PM PDT 24 1770225778 ps
T2882 /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.960934597 Aug 02 07:53:31 PM PDT 24 Aug 02 07:58:47 PM PDT 24 4376604040 ps
T2883 /workspace/coverage/cover_reg_top/86.xbar_random_large_delays.1221615484 Aug 02 08:07:26 PM PDT 24 Aug 02 08:12:50 PM PDT 24 31295535973 ps
T2884 /workspace/coverage/cover_reg_top/55.xbar_random.1388697438 Aug 02 08:02:36 PM PDT 24 Aug 02 08:03:59 PM PDT 24 2331946391 ps
T2885 /workspace/coverage/cover_reg_top/25.xbar_access_same_device.3536997202 Aug 02 07:57:10 PM PDT 24 Aug 02 07:59:02 PM PDT 24 2436416276 ps
T2886 /workspace/coverage/cover_reg_top/22.xbar_random.3619052220 Aug 02 07:56:34 PM PDT 24 Aug 02 07:57:00 PM PDT 24 356960831 ps
T2887 /workspace/coverage/cover_reg_top/7.xbar_same_source.1720656288 Aug 02 07:53:13 PM PDT 24 Aug 02 07:53:20 PM PDT 24 55157421 ps
T2888 /workspace/coverage/cover_reg_top/75.xbar_random.1332901551 Aug 02 08:05:39 PM PDT 24 Aug 02 08:05:45 PM PDT 24 77812486 ps
T2889 /workspace/coverage/cover_reg_top/48.xbar_stress_all.1622978942 Aug 02 08:01:28 PM PDT 24 Aug 02 08:01:34 PM PDT 24 49168190 ps
T2890 /workspace/coverage/cover_reg_top/94.xbar_random_slow_rsp.1917384334 Aug 02 08:09:08 PM PDT 24 Aug 02 08:20:30 PM PDT 24 40342541376 ps
T2891 /workspace/coverage/cover_reg_top/13.xbar_error_random.3427382199 Aug 02 07:54:15 PM PDT 24 Aug 02 07:55:22 PM PDT 24 1990453523 ps
T2892 /workspace/coverage/cover_reg_top/54.xbar_access_same_device.3092013704 Aug 02 08:02:19 PM PDT 24 Aug 02 08:03:24 PM PDT 24 1743333307 ps
T2893 /workspace/coverage/cover_reg_top/5.chip_tl_errors.3769904018 Aug 02 07:52:25 PM PDT 24 Aug 02 07:57:13 PM PDT 24 4242960008 ps
T2894 /workspace/coverage/cover_reg_top/56.xbar_access_same_device.3810578770 Aug 02 08:02:45 PM PDT 24 Aug 02 08:03:34 PM PDT 24 654618398 ps
T2895 /workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.2068377322 Aug 02 08:09:12 PM PDT 24 Aug 02 08:31:48 PM PDT 24 69445083486 ps
T2896 /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.3172435690 Aug 02 08:00:22 PM PDT 24 Aug 02 08:03:17 PM PDT 24 610570591 ps
T2897 /workspace/coverage/cover_reg_top/87.xbar_random_large_delays.4197441439 Aug 02 08:07:40 PM PDT 24 Aug 02 08:11:56 PM PDT 24 22477772095 ps
T2898 /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.3051223149 Aug 02 08:07:50 PM PDT 24 Aug 02 08:19:00 PM PDT 24 7646325821 ps
T2899 /workspace/coverage/cover_reg_top/54.xbar_error_random.56645941 Aug 02 08:02:36 PM PDT 24 Aug 02 08:03:10 PM PDT 24 917234243 ps
T2900 /workspace/coverage/cover_reg_top/48.xbar_same_source.1466516124 Aug 02 08:01:36 PM PDT 24 Aug 02 08:02:14 PM PDT 24 1255075103 ps
T2901 /workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.2556777461 Aug 02 07:53:53 PM PDT 24 Aug 02 08:38:55 PM PDT 24 155467023171 ps
T2902 /workspace/coverage/cover_reg_top/60.xbar_random_large_delays.4137825287 Aug 02 08:03:09 PM PDT 24 Aug 02 08:20:08 PM PDT 24 98037951600 ps
T2903 /workspace/coverage/cover_reg_top/34.xbar_smoke_large_delays.1755851489 Aug 02 07:58:44 PM PDT 24 Aug 02 07:59:32 PM PDT 24 4830884577 ps
T2904 /workspace/coverage/cover_reg_top/76.xbar_same_source.252916508 Aug 02 08:05:50 PM PDT 24 Aug 02 08:06:24 PM PDT 24 1095847798 ps
T2905 /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.2726698233 Aug 02 08:02:50 PM PDT 24 Aug 02 08:10:31 PM PDT 24 11628248721 ps
T2906 /workspace/coverage/cover_reg_top/52.xbar_smoke.3912427713 Aug 02 08:01:55 PM PDT 24 Aug 02 08:02:01 PM PDT 24 47202029 ps
T2907 /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.2770112323 Aug 02 08:05:52 PM PDT 24 Aug 02 08:11:03 PM PDT 24 2497364338 ps
T2908 /workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.686500419 Aug 02 07:56:24 PM PDT 24 Aug 02 07:56:51 PM PDT 24 288021939 ps
T2909 /workspace/coverage/cover_reg_top/85.xbar_access_same_device.3287235188 Aug 02 08:07:13 PM PDT 24 Aug 02 08:08:14 PM PDT 24 722445622 ps
T2910 /workspace/coverage/cover_reg_top/18.xbar_smoke.3889165464 Aug 02 07:55:33 PM PDT 24 Aug 02 07:55:40 PM PDT 24 55491758 ps
T2911 /workspace/coverage/cover_reg_top/41.xbar_stress_all.3982336148 Aug 02 08:00:09 PM PDT 24 Aug 02 08:00:13 PM PDT 24 5980156 ps
T2912 /workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.4201256888 Aug 02 07:54:05 PM PDT 24 Aug 02 08:00:28 PM PDT 24 7144664684 ps
T2913 /workspace/coverage/cover_reg_top/36.xbar_random.2537512668 Aug 02 07:59:27 PM PDT 24 Aug 02 08:00:04 PM PDT 24 457287457 ps
T2914 /workspace/coverage/cover_reg_top/34.xbar_error_random.3057939286 Aug 02 07:59:01 PM PDT 24 Aug 02 08:00:19 PM PDT 24 2095573149 ps
T2915 /workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.3808180293 Aug 02 07:52:36 PM PDT 24 Aug 02 08:07:46 PM PDT 24 54937918178 ps
T2916 /workspace/coverage/cover_reg_top/55.xbar_random_large_delays.2134021295 Aug 02 08:02:36 PM PDT 24 Aug 02 08:07:15 PM PDT 24 26823728366 ps
T2917 /workspace/coverage/cover_reg_top/86.xbar_smoke.2450568244 Aug 02 08:07:26 PM PDT 24 Aug 02 08:07:35 PM PDT 24 196657307 ps
T2918 /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.1602713404 Aug 02 07:57:43 PM PDT 24 Aug 02 08:00:07 PM PDT 24 3522514482 ps
T2919 /workspace/coverage/cover_reg_top/91.xbar_random_zero_delays.500042001 Aug 02 08:08:18 PM PDT 24 Aug 02 08:08:30 PM PDT 24 125382837 ps
T2920 /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.617957868 Aug 02 07:56:26 PM PDT 24 Aug 02 07:58:22 PM PDT 24 200337323 ps
T2921 /workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.527963369 Aug 02 07:52:48 PM PDT 24 Aug 02 07:53:10 PM PDT 24 194531069 ps
T2922 /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_error.2360242338 Aug 02 07:53:51 PM PDT 24 Aug 02 07:54:34 PM PDT 24 1371284880 ps
T2923 /workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.2179224132 Aug 02 08:01:55 PM PDT 24 Aug 02 08:02:11 PM PDT 24 130388534 ps
T2924 /workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.3712729947 Aug 02 08:05:04 PM PDT 24 Aug 02 08:18:21 PM PDT 24 43849127838 ps
T2925 /workspace/coverage/cover_reg_top/2.xbar_smoke.1487103593 Aug 02 07:52:03 PM PDT 24 Aug 02 07:52:10 PM PDT 24 57700178 ps
T2926 /workspace/coverage/cover_reg_top/66.xbar_stress_all.1730719240 Aug 02 08:04:23 PM PDT 24 Aug 02 08:09:20 PM PDT 24 3532043613 ps
T2927 /workspace/coverage/cover_reg_top/45.xbar_smoke.36597768 Aug 02 08:00:43 PM PDT 24 Aug 02 08:00:53 PM PDT 24 212100037 ps
T2928 /workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.3239097038 Aug 02 08:09:20 PM PDT 24 Aug 02 08:52:14 PM PDT 24 134060462722 ps
T2929 /workspace/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.351928784 Aug 02 08:09:05 PM PDT 24 Aug 02 08:10:27 PM PDT 24 5043936176 ps
T2930 /workspace/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.2190604271 Aug 02 07:55:47 PM PDT 24 Aug 02 08:09:50 PM PDT 24 9348286669 ps
T2931 /workspace/coverage/cover_reg_top/62.xbar_stress_all.1699168312 Aug 02 08:03:40 PM PDT 24 Aug 02 08:07:07 PM PDT 24 2703573993 ps
T2932 /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.1344265560 Aug 02 07:57:08 PM PDT 24 Aug 02 07:57:25 PM PDT 24 196784117 ps
T2933 /workspace/coverage/cover_reg_top/23.xbar_same_source.2712879880 Aug 02 07:56:46 PM PDT 24 Aug 02 07:57:19 PM PDT 24 420791546 ps
T2934 /workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.1211407629 Aug 02 08:04:57 PM PDT 24 Aug 02 08:05:29 PM PDT 24 287335443 ps
T2935 /workspace/coverage/cover_reg_top/57.xbar_random_large_delays.2345067483 Aug 02 08:02:47 PM PDT 24 Aug 02 08:04:29 PM PDT 24 10508333448 ps
T32 /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.290175009 Aug 02 08:09:54 PM PDT 24 Aug 02 08:15:03 PM PDT 24 5617645142 ps
T33 /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.729425815 Aug 02 08:09:52 PM PDT 24 Aug 02 08:14:18 PM PDT 24 5021239048 ps
T34 /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2781313757 Aug 02 08:09:53 PM PDT 24 Aug 02 08:13:57 PM PDT 24 4426101374 ps
T190 /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3641456681 Aug 02 08:09:54 PM PDT 24 Aug 02 08:14:03 PM PDT 24 5667801603 ps
T191 /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3750462931 Aug 02 08:09:52 PM PDT 24 Aug 02 08:14:01 PM PDT 24 5003813105 ps
T192 /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.4106650320 Aug 02 08:09:51 PM PDT 24 Aug 02 08:14:33 PM PDT 24 4887798180 ps
T193 /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2845217819 Aug 02 08:09:51 PM PDT 24 Aug 02 08:14:30 PM PDT 24 5276247850 ps
T194 /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1122613393 Aug 02 08:09:52 PM PDT 24 Aug 02 08:15:54 PM PDT 24 4840267750 ps
T197 /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1961797458 Aug 02 08:09:51 PM PDT 24 Aug 02 08:13:41 PM PDT 24 4912760560 ps
T195 /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3640869915 Aug 02 08:09:50 PM PDT 24 Aug 02 08:14:46 PM PDT 24 5809033817 ps

Test location /workspace/coverage/default/2.chip_sw_power_virus.4005570263
Short name T11
Test name
Test status
Simulation time 6065749886 ps
CPU time 1340.2 seconds
Started Aug 02 08:46:55 PM PDT 24
Finished Aug 02 09:09:16 PM PDT 24
Peak memory 624952 kb
Host smart-6f23227a-4dee-4c13-8d22-a6cfbd6bc763
User root
Command /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +accelerate_cold_
power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtes
t_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4005570263 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_virus.4005570263
Directory /workspace/2.chip_sw_power_virus/latest

Test location /workspace/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.26735090
Short name T139
Test name
Test status
Simulation time 7543619200 ps
CPU time 458.13 seconds
Started Aug 02 07:56:00 PM PDT 24
Finished Aug 02 08:03:38 PM PDT 24
Peak memory 638632 kb
Host smart-3cfc7ecf-c253-4917-9936-1222415db341
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26735090 -assert nopostproc +UV
M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.chip_csr_mem_rw_with_rand_reset.26735090
Directory /workspace/19.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/2.chip_plic_all_irqs_0.3825285193
Short name T328
Test name
Test status
Simulation time 6030372840 ps
CPU time 1275.79 seconds
Started Aug 02 08:41:28 PM PDT 24
Finished Aug 02 09:02:45 PM PDT 24
Peak memory 609296 kb
Host smart-63f89d7d-034c-411a-8573-6118ff042d2d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825285193 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.chip_plic_all_irqs_0.3825285193
Directory /workspace/2.chip_plic_all_irqs_0/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.2452701167
Short name T254
Test name
Test status
Simulation time 1025372702 ps
CPU time 81.32 seconds
Started Aug 02 08:04:37 PM PDT 24
Finished Aug 02 08:05:59 PM PDT 24
Peak memory 575800 kb
Host smart-1a5f1e9e-088b-4e9a-ba6a-f831d4fa83d7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452701167 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_error.2452701167
Directory /workspace/68.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.4102258687
Short name T832
Test name
Test status
Simulation time 118469977778 ps
CPU time 2152.67 seconds
Started Aug 02 07:58:09 PM PDT 24
Finished Aug 02 08:34:02 PM PDT 24
Peak memory 575952 kb
Host smart-9723bb88-c42e-4822-8923-3fc22e348bcf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102258687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_
device_slow_rsp.4102258687
Directory /workspace/30.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1562532191
Short name T17
Test name
Test status
Simulation time 22944783602 ps
CPU time 1390.19 seconds
Started Aug 02 08:40:04 PM PDT 24
Finished Aug 02 09:03:15 PM PDT 24
Peak memory 610916 kb
Host smart-e1380c11-6418-488c-a931-7b15cd378e82
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1562532191 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1562532191
Directory /workspace/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest

Test location /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.290175009
Short name T32
Test name
Test status
Simulation time 5617645142 ps
CPU time 308.73 seconds
Started Aug 02 08:09:54 PM PDT 24
Finished Aug 02 08:15:03 PM PDT 24
Peak memory 657424 kb
Host smart-4176d934-eb60-49fd-bc21-7f2befe30696
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290175009 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES
T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n
ull -cm_name 0.chip_padctrl_attributes.290175009
Directory /workspace/0.chip_padctrl_attributes/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.2123788845
Short name T555
Test name
Test status
Simulation time 44140696160 ps
CPU time 818.41 seconds
Started Aug 02 08:02:19 PM PDT 24
Finished Aug 02 08:15:58 PM PDT 24
Peak memory 576088 kb
Host smart-af1999e2-d67f-4f9d-9a8a-e20af765b69d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123788845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_
device_slow_rsp.2123788845
Directory /workspace/54.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.4065306851
Short name T848
Test name
Test status
Simulation time 82649046958 ps
CPU time 1422.12 seconds
Started Aug 02 08:05:09 PM PDT 24
Finished Aug 02 08:28:51 PM PDT 24
Peak memory 576040 kb
Host smart-d2503c68-ae53-4039-b036-bcc5557f2610
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065306851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_
device_slow_rsp.4065306851
Directory /workspace/72.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.869654124
Short name T226
Test name
Test status
Simulation time 12917416400 ps
CPU time 2788.33 seconds
Started Aug 02 08:20:20 PM PDT 24
Finished Aug 02 09:06:49 PM PDT 24
Peak memory 611676 kb
Host smart-b56d01e4-8c72-43ab-a34d-1d6ec94ef329
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86965
4124 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.869654124
Directory /workspace/0.chip_sw_keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.3020778275
Short name T3
Test name
Test status
Simulation time 12196272130 ps
CPU time 3091.14 seconds
Started Aug 02 08:27:53 PM PDT 24
Finished Aug 02 09:19:25 PM PDT 24
Peak memory 610164 kb
Host smart-625e029b-1ed7-4e28-a337-a772f469898a
User root
Command /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4,
mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3020778275 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.3020778275
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest

Test location /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3551979010
Short name T8
Test name
Test status
Simulation time 3377723840 ps
CPU time 391.69 seconds
Started Aug 02 08:20:42 PM PDT 24
Finished Aug 02 08:27:14 PM PDT 24
Peak memory 610556 kb
Host smart-691fed68-5640-4241-aba7-44cb0ce84c02
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551
979010 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.3551979010
Directory /workspace/0.chip_sw_sleep_pin_mio_dio_val/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1345116707
Short name T465
Test name
Test status
Simulation time 100416123334 ps
CPU time 1760.14 seconds
Started Aug 02 07:54:19 PM PDT 24
Finished Aug 02 08:23:39 PM PDT 24
Peak memory 576116 kb
Host smart-d1cf3069-383e-4cf9-8412-5f429359d565
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345116707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_
device_slow_rsp.1345116707
Directory /workspace/12.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.1113716050
Short name T836
Test name
Test status
Simulation time 135147369973 ps
CPU time 2616.4 seconds
Started Aug 02 08:02:56 PM PDT 24
Finished Aug 02 08:46:33 PM PDT 24
Peak memory 576760 kb
Host smart-f93b8275-b111-410e-b859-bc9fde5dc2df
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113716050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_
device_slow_rsp.1113716050
Directory /workspace/58.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/default/0.rom_raw_unlock.3659405056
Short name T50
Test name
Test status
Simulation time 6683287521 ps
CPU time 276.71 seconds
Started Aug 02 08:23:16 PM PDT 24
Finished Aug 02 08:27:53 PM PDT 24
Peak memory 619020 kb
Host smart-9b6b5615-e311-444e-8546-b6d45998e130
User root
Command /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE
xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3659405056 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_raw_unlock.3659405056
Directory /workspace/0.rom_raw_unlock/latest

Test location /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.2828918834
Short name T1
Test name
Test status
Simulation time 5174264656 ps
CPU time 671.81 seconds
Started Aug 02 08:37:41 PM PDT 24
Finished Aug 02 08:48:53 PM PDT 24
Peak memory 641492 kb
Host smart-04ce9eef-46f0-40a1-bfe3-baeae776a95b
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2828918834 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.2828918834
Directory /workspace/2.chip_sw_rstmgr_rst_cnsty_escalation/latest

Test location /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2608084843
Short name T180
Test name
Test status
Simulation time 3305231184 ps
CPU time 288.04 seconds
Started Aug 02 08:23:26 PM PDT 24
Finished Aug 02 08:28:14 PM PDT 24
Peak memory 609800 kb
Host smart-45e08757-a216-4fff-86b9-183c7c208ab7
User root
Command /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=2608084843 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.2608084843
Directory /workspace/0.chip_sw_rv_core_ibex_address_translation/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_stress_all.3259766813
Short name T490
Test name
Test status
Simulation time 18296671484 ps
CPU time 619.26 seconds
Started Aug 02 08:05:59 PM PDT 24
Finished Aug 02 08:16:19 PM PDT 24
Peak memory 576068 kb
Host smart-01b2438e-aed3-4bc9-a227-08eb7aac5954
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259766813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all.3259766813
Directory /workspace/77.xbar_stress_all/latest

Test location /workspace/coverage/default/0.chip_plic_all_irqs_20.2909810243
Short name T336
Test name
Test status
Simulation time 4255542984 ps
CPU time 986.5 seconds
Started Aug 02 08:20:35 PM PDT 24
Finished Aug 02 08:37:02 PM PDT 24
Peak memory 609776 kb
Host smart-3b987800-1490-4619-8cb7-a032cc836546
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909810243 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.chip_plic_all_irqs_20.2909810243
Directory /workspace/0.chip_plic_all_irqs_20/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_stress_all.2550451599
Short name T528
Test name
Test status
Simulation time 15021004462 ps
CPU time 513.55 seconds
Started Aug 02 07:52:16 PM PDT 24
Finished Aug 02 08:00:50 PM PDT 24
Peak memory 576776 kb
Host smart-4b3e6497-569c-46b6-840c-b2ff4757f07e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550451599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.2550451599
Directory /workspace/3.xbar_stress_all/latest

Test location /workspace/coverage/default/0.chip_sw_alert_test.2244740157
Short name T52
Test name
Test status
Simulation time 3549847040 ps
CPU time 324.54 seconds
Started Aug 02 08:18:35 PM PDT 24
Finished Aug 02 08:24:00 PM PDT 24
Peak memory 609848 kb
Host smart-a94c90f7-56cf-4527-9aae-8810d117da7c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244740157 -assert nopostproc +UVM_TESTNAME=chip_ba
se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.chip_sw_alert_test.2244740157
Directory /workspace/0.chip_sw_alert_test/latest

Test location /workspace/coverage/default/1.chip_jtag_csr_rw.2982757671
Short name T56
Test name
Test status
Simulation time 13241808250 ps
CPU time 1141.57 seconds
Started Aug 02 08:23:40 PM PDT 24
Finished Aug 02 08:42:41 PM PDT 24
Peak memory 608048 kb
Host smart-5827dbf2-a17b-44f2-af17-6d0a23d5f46f
User root
Command /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982757671 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T
EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.c
hip_jtag_csr_rw.2982757671
Directory /workspace/1.chip_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.849413236
Short name T845
Test name
Test status
Simulation time 88549086215 ps
CPU time 1683.76 seconds
Started Aug 02 08:03:41 PM PDT 24
Finished Aug 02 08:31:46 PM PDT 24
Peak memory 576056 kb
Host smart-62e1aa52-69b7-4935-a07a-a173e798c040
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849413236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_d
evice_slow_rsp.849413236
Directory /workspace/62.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2382730917
Short name T63
Test name
Test status
Simulation time 3160422584 ps
CPU time 335.4 seconds
Started Aug 02 08:46:00 PM PDT 24
Finished Aug 02 08:51:36 PM PDT 24
Peak memory 649284 kb
Host smart-35b74b81-f7e8-42a2-b6b1-66bb6237b6f3
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382730917 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_s
w_alert_handler_lpg_sleep_mode_alerts.2382730917
Directory /workspace/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.3608019666
Short name T703
Test name
Test status
Simulation time 1413987021 ps
CPU time 105.54 seconds
Started Aug 02 08:00:50 PM PDT 24
Finished Aug 02 08:02:35 PM PDT 24
Peak memory 575988 kb
Host smart-cce348fc-adc1-4912-afde-a8b119c49ac6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608019666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.3608019666
Directory /workspace/44.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/26.chip_tl_errors.3876944931
Short name T559
Test name
Test status
Simulation time 4615770104 ps
CPU time 374.88 seconds
Started Aug 02 07:57:30 PM PDT 24
Finished Aug 02 08:03:45 PM PDT 24
Peak memory 603720 kb
Host smart-9052e7d2-fd24-47ff-bb4b-17f5617bf7f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876944931 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.chip_tl_errors.3876944931
Directory /workspace/26.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.794150666
Short name T77
Test name
Test status
Simulation time 3165229683 ps
CPU time 55.01 seconds
Started Aug 02 08:04:23 PM PDT 24
Finished Aug 02 08:05:18 PM PDT 24
Peak memory 573828 kb
Host smart-2ca75431-d037-491f-8a1f-d012b5c7411a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794150666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_slow_rsp.794150666
Directory /workspace/67.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.1835268691
Short name T428
Test name
Test status
Simulation time 28360447909 ps
CPU time 3746 seconds
Started Aug 02 07:55:33 PM PDT 24
Finished Aug 02 08:57:59 PM PDT 24
Peak memory 593712 kb
Host smart-2ac1d1b5-57ed-4abf-9d63-9062463c78f5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835268691 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.chip_same_csr_outstanding.1835268691
Directory /workspace/18.chip_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.chip_plic_all_irqs_10.722480689
Short name T149
Test name
Test status
Simulation time 3529502962 ps
CPU time 726.4 seconds
Started Aug 02 08:19:45 PM PDT 24
Finished Aug 02 08:31:53 PM PDT 24
Peak memory 609828 kb
Host smart-4d8a0e19-be2e-48a8-af6f-02bc20c358bc
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722480689 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.chip_plic_all_irqs_10.722480689
Directory /workspace/0.chip_plic_all_irqs_10/latest

Test location /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.3602600753
Short name T6
Test name
Test status
Simulation time 4161644025 ps
CPU time 512.37 seconds
Started Aug 02 08:28:36 PM PDT 24
Finished Aug 02 08:37:10 PM PDT 24
Peak memory 620428 kb
Host smart-882ee5c0-55ba-414d-8476-0354a96d6abc
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602600753 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_transition.3602600753
Directory /workspace/1.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.1334011776
Short name T877
Test name
Test status
Simulation time 97829174393 ps
CPU time 1711.69 seconds
Started Aug 02 07:56:34 PM PDT 24
Finished Aug 02 08:25:06 PM PDT 24
Peak memory 576036 kb
Host smart-50981fe6-8f53-47aa-bd6d-f2acec99737e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334011776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_
device_slow_rsp.1334011776
Directory /workspace/22.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.3935443298
Short name T166
Test name
Test status
Simulation time 17939584927 ps
CPU time 1734.66 seconds
Started Aug 02 08:41:43 PM PDT 24
Finished Aug 02 09:10:38 PM PDT 24
Peak memory 611544 kb
Host smart-9a5a97db-580e-4565-a923-1ec7d275c6d8
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3935443298 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.3935443298
Directory /workspace/2.chip_sw_flash_init_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_gpio.1488586750
Short name T29
Test name
Test status
Simulation time 3911573904 ps
CPU time 558.98 seconds
Started Aug 02 08:19:19 PM PDT 24
Finished Aug 02 08:28:39 PM PDT 24
Peak memory 610308 kb
Host smart-f0401d5a-f3df-4e1b-8b58-c3d8503d75d1
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488586750 -assert nopostproc +UVM_TESTNAME=chip_bas
e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.chip_sw_gpio.1488586750
Directory /workspace/0.chip_sw_gpio/latest

Test location /workspace/coverage/default/0.rom_e2e_shutdown_output.4066706333
Short name T47
Test name
Test status
Simulation time 24205279108 ps
CPU time 3206.85 seconds
Started Aug 02 08:26:10 PM PDT 24
Finished Aug 02 09:19:38 PM PDT 24
Peak memory 611556 kb
Host smart-68840a4c-5363-4e98-864e-a4d27117238a
User root
Command /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f
lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066706333 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi
p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rom_e2e_shutdown_output.4066706333
Directory /workspace/0.rom_e2e_shutdown_output/latest

Test location /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1326929456
Short name T112
Test name
Test status
Simulation time 27487259430 ps
CPU time 5370.66 seconds
Started Aug 02 08:25:43 PM PDT 24
Finished Aug 02 09:55:15 PM PDT 24
Peak memory 610448 kb
Host smart-ee0dcc46-8c8f-41c3-8280-21b3703c88ce
User root
Command /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_
cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1326929456 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency_reduced_freq.1326929456
Directory /workspace/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2157312214
Short name T127
Test name
Test status
Simulation time 5826907366 ps
CPU time 503.47 seconds
Started Aug 02 08:20:37 PM PDT 24
Finished Aug 02 08:29:01 PM PDT 24
Peak memory 610072 kb
Host smart-5f9997e1-6c15-4722-b661-acde99fca326
User root
Command /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21573122
14 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2157312214
Directory /workspace/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest

Test location /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1349352014
Short name T9
Test name
Test status
Simulation time 3664324750 ps
CPU time 404.39 seconds
Started Aug 02 08:37:38 PM PDT 24
Finished Aug 02 08:44:23 PM PDT 24
Peak memory 609972 kb
Host smart-b50bf047-6e3f-4059-8b2d-4713ad6d2129
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349
352014 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.1349352014
Directory /workspace/2.chip_sw_sleep_pin_mio_dio_val/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.3230437220
Short name T455
Test name
Test status
Simulation time 2114447123 ps
CPU time 394.49 seconds
Started Aug 02 07:53:33 PM PDT 24
Finished Aug 02 08:00:08 PM PDT 24
Peak memory 576708 kb
Host smart-76d0cf6f-92a8-48a4-8dd3-699f5c18855e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230437220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_
with_rand_reset.3230437220
Directory /workspace/8.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.107422174
Short name T850
Test name
Test status
Simulation time 13511060589 ps
CPU time 701.16 seconds
Started Aug 02 07:54:05 PM PDT 24
Finished Aug 02 08:05:46 PM PDT 24
Peak memory 575996 kb
Host smart-2e216cde-a7f4-49fe-b996-cbb4da6e3625
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107422174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_
with_rand_reset.107422174
Directory /workspace/11.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_entropy.2812436424
Short name T85
Test name
Test status
Simulation time 3344384982 ps
CPU time 351.81 seconds
Started Aug 02 08:29:03 PM PDT 24
Finished Aug 02 08:34:55 PM PDT 24
Peak memory 609720 kb
Host smart-13fcdedc-f831-4290-a89e-0e1451a262b9
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2812436424 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.2812436424
Directory /workspace/1.chip_sw_alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.3054503073
Short name T123
Test name
Test status
Simulation time 7468648234 ps
CPU time 73.47 seconds
Started Aug 02 08:06:28 PM PDT 24
Finished Aug 02 08:07:41 PM PDT 24
Peak memory 573900 kb
Host smart-833d3696-e881-4843-a72e-4f3be9db4d18
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054503073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_large_delays.3054503073
Directory /workspace/80.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/16.chip_tl_errors.1619480350
Short name T558
Test name
Test status
Simulation time 3556118510 ps
CPU time 242.49 seconds
Started Aug 02 07:54:58 PM PDT 24
Finished Aug 02 07:59:00 PM PDT 24
Peak memory 598568 kb
Host smart-0ecb41f1-c9d4-490b-abf6-7b6fa8f38f86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619480350 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_tl_errors.1619480350
Directory /workspace/16.chip_tl_errors/latest

Test location /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1204544923
Short name T5
Test name
Test status
Simulation time 10195001738 ps
CPU time 1016.05 seconds
Started Aug 02 08:19:09 PM PDT 24
Finished Aug 02 08:36:06 PM PDT 24
Peak memory 610524 kb
Host smart-820f8075-0376-42b5-9ec6-4a1ed5be13c9
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204544923 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.1204544923
Directory /workspace/0.chip_sw_sram_ctrl_execution_main/latest

Test location /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.985938773
Short name T21
Test name
Test status
Simulation time 25091992700 ps
CPU time 1678.33 seconds
Started Aug 02 08:17:35 PM PDT 24
Finished Aug 02 08:45:34 PM PDT 24
Peak memory 614140 kb
Host smart-b4e18ef5-4e3d-48ac-91e7-996e57ef92a2
User root
Command /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98593877
3 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.985938773
Directory /workspace/0.chip_sw_sysrst_ctrl_reset/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3323729601
Short name T160
Test name
Test status
Simulation time 4954066952 ps
CPU time 526.57 seconds
Started Aug 02 08:20:53 PM PDT 24
Finished Aug 02 08:29:40 PM PDT 24
Peak memory 611204 kb
Host smart-afc44a08-4ad0-429b-83ff-a2d93aa0b368
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3323729601 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.3323729601
Directory /workspace/0.chip_sw_otp_ctrl_escalation/latest

Test location /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1864672827
Short name T172
Test name
Test status
Simulation time 10180168611 ps
CPU time 974.23 seconds
Started Aug 02 08:46:27 PM PDT 24
Finished Aug 02 09:02:42 PM PDT 24
Peak memory 624808 kb
Host smart-562dbb02-911a-4dfb-90cc-2ef7946c67c6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864672827 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.chip_sw_lc_ctrl_transition.1864672827
Directory /workspace/8.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/1.chip_tap_straps_testunlock0.842467600
Short name T69
Test name
Test status
Simulation time 3437383914 ps
CPU time 236.26 seconds
Started Aug 02 08:30:35 PM PDT 24
Finished Aug 02 08:34:33 PM PDT 24
Peak memory 633120 kb
Host smart-624fbdc7-c06c-4bc8-8a69-b68a69d69304
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te
st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842467600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_testunlock0.842467600
Directory /workspace/1.chip_tap_straps_testunlock0/latest

Test location /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.4091393357
Short name T10
Test name
Test status
Simulation time 2828390495 ps
CPU time 259.21 seconds
Started Aug 02 08:23:34 PM PDT 24
Finished Aug 02 08:27:53 PM PDT 24
Peak memory 610052 kb
Host smart-f6c07dff-522e-495c-a508-b98334ef96aa
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091
393357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.4091393357
Directory /workspace/1.chip_sw_sleep_pin_mio_dio_val/latest

Test location /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.3955988987
Short name T245
Test name
Test status
Simulation time 4879691902 ps
CPU time 537.28 seconds
Started Aug 02 08:20:39 PM PDT 24
Finished Aug 02 08:29:37 PM PDT 24
Peak memory 611248 kb
Host smart-f0bebbc1-eabc-4a5b-90a8-85167a3c0b68
User root
Command /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955988987 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr
l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw
_sram_ctrl_scrambled_access.3955988987
Directory /workspace/0.chip_sw_sram_ctrl_scrambled_access/latest

Test location /workspace/coverage/default/1.chip_sw_sleep_pin_retention.4165642272
Short name T16
Test name
Test status
Simulation time 4758477500 ps
CPU time 369.16 seconds
Started Aug 02 08:26:11 PM PDT 24
Finished Aug 02 08:32:21 PM PDT 24
Peak memory 609148 kb
Host smart-1566e11c-3686-4157-91e9-743ad0474042
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165642272 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_retention.4165642272
Directory /workspace/1.chip_sw_sleep_pin_retention/latest

Test location /workspace/coverage/default/29.chip_sw_all_escalation_resets.3852043525
Short name T247
Test name
Test status
Simulation time 6727991382 ps
CPU time 730 seconds
Started Aug 02 08:50:13 PM PDT 24
Finished Aug 02 09:02:23 PM PDT 24
Peak memory 650232 kb
Host smart-b1cafe0e-2e65-4086-8616-58c220542630
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3852043525 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_all_escalation_resets.3852043525
Directory /workspace/29.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/cover_reg_top/7.chip_tl_errors.3071515592
Short name T613
Test name
Test status
Simulation time 4400407506 ps
CPU time 324.43 seconds
Started Aug 02 07:52:56 PM PDT 24
Finished Aug 02 07:58:21 PM PDT 24
Peak memory 603708 kb
Host smart-afbc8a72-424d-433a-80fe-8fde918e9657
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071515592 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_tl_errors.3071515592
Directory /workspace/7.chip_tl_errors/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.121149921
Short name T242
Test name
Test status
Simulation time 4887294644 ps
CPU time 337.31 seconds
Started Aug 02 08:19:24 PM PDT 24
Finished Aug 02 08:25:01 PM PDT 24
Peak memory 610888 kb
Host smart-00b969b3-eb53-4ba6-9a89-148954cd2b61
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12
1149921 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_lc_rw_en.121149921
Directory /workspace/0.chip_sw_flash_ctrl_lc_rw_en/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1288626798
Short name T382
Test name
Test status
Simulation time 4085578620 ps
CPU time 392 seconds
Started Aug 02 08:20:57 PM PDT 24
Finished Aug 02 08:27:30 PM PDT 24
Peak memory 649024 kb
Host smart-9c88bda4-cf9e-4d4a-b384-5f83ca328f55
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288626798 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s
w_alert_handler_lpg_sleep_mode_alerts.1288626798
Directory /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.1652759759
Short name T472
Test name
Test status
Simulation time 8146439382 ps
CPU time 519.81 seconds
Started Aug 02 08:09:04 PM PDT 24
Finished Aug 02 08:17:44 PM PDT 24
Peak memory 576784 kb
Host smart-5fa2fd71-d77c-4427-9697-c1a299f41ec7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652759759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all
_with_rand_reset.1652759759
Directory /workspace/93.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2781313757
Short name T34
Test name
Test status
Simulation time 4426101374 ps
CPU time 244.36 seconds
Started Aug 02 08:09:53 PM PDT 24
Finished Aug 02 08:13:57 PM PDT 24
Peak memory 657392 kb
Host smart-4653ab42-bb68-4188-9cc8-9395133d49be
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781313757 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 1.chip_padctrl_attributes.2781313757
Directory /workspace/1.chip_padctrl_attributes/latest

Test location /workspace/coverage/default/36.chip_sw_all_escalation_resets.299744037
Short name T324
Test name
Test status
Simulation time 5055147700 ps
CPU time 761.26 seconds
Started Aug 02 08:49:24 PM PDT 24
Finished Aug 02 09:02:06 PM PDT 24
Peak memory 650412 kb
Host smart-83726a83-77f0-44f7-9ed3-556324f28966
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
299744037 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.299744037
Directory /workspace/36.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/52.chip_sw_all_escalation_resets.3941522794
Short name T92
Test name
Test status
Simulation time 4997285496 ps
CPU time 748.06 seconds
Started Aug 02 08:52:09 PM PDT 24
Finished Aug 02 09:04:37 PM PDT 24
Peak memory 650980 kb
Host smart-77826ef3-8d16-444e-83b1-d57cc115a611
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3941522794 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.3941522794
Directory /workspace/52.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3657474207
Short name T252
Test name
Test status
Simulation time 4446180500 ps
CPU time 437.48 seconds
Started Aug 02 08:50:21 PM PDT 24
Finished Aug 02 08:57:39 PM PDT 24
Peak memory 649328 kb
Host smart-0ba0cd58-4ce3-498e-b31c-a0a9cc056586
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657474207 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3657474207
Directory /workspace/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.781519201
Short name T1348
Test name
Test status
Simulation time 42761514033 ps
CPU time 4755.72 seconds
Started Aug 02 08:35:21 PM PDT 24
Finished Aug 02 09:54:37 PM PDT 24
Peak memory 623012 kb
Host smart-ac71d841-00a2-4f7f-b8a1-9c8019bebd02
User root
Command /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_
rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=781519201 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_rma_unlocked.781519201
Directory /workspace/2.chip_sw_flash_rma_unlocked/latest

Test location /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.2408719672
Short name T142
Test name
Test status
Simulation time 5570842536 ps
CPU time 274.85 seconds
Started Aug 02 07:51:52 PM PDT 24
Finished Aug 02 07:56:27 PM PDT 24
Peak memory 664028 kb
Host smart-59aecb4f-d926-4fde-9f97-1541c8ec598e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408719672 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_hw_r
eset.2408719672
Directory /workspace/1.chip_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.908997973
Short name T480
Test name
Test status
Simulation time 4437428536 ps
CPU time 494.96 seconds
Started Aug 02 08:02:19 PM PDT 24
Finished Aug 02 08:10:34 PM PDT 24
Peak memory 575972 kb
Host smart-abd7f9f5-9f3b-4831-8ff2-255b9dd7aa00
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908997973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_
with_rand_reset.908997973
Directory /workspace/53.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.chip_sw_data_integrity_escalation.1258522588
Short name T282
Test name
Test status
Simulation time 5202489104 ps
CPU time 850.85 seconds
Started Aug 02 08:21:54 PM PDT 24
Finished Aug 02 08:36:05 PM PDT 24
Peak memory 611056 kb
Host smart-c032c32b-6049-4425-ac5f-b9c86c20644b
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1258522588 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.1258522588
Directory /workspace/1.chip_sw_data_integrity_escalation/latest

Test location /workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.526733151
Short name T450
Test name
Test status
Simulation time 26847350032 ps
CPU time 3561.75 seconds
Started Aug 02 07:53:30 PM PDT 24
Finished Aug 02 08:52:53 PM PDT 24
Peak memory 593372 kb
Host smart-821a3973-3f9b-4abe-ac80-14fb6e10d51c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526733151 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 9.chip_same_csr_outstanding.526733151
Directory /workspace/9.chip_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.3214692192
Short name T173
Test name
Test status
Simulation time 2980713917 ps
CPU time 306.73 seconds
Started Aug 02 08:26:42 PM PDT 24
Finished Aug 02 08:31:49 PM PDT 24
Peak memory 621764 kb
Host smart-47270d5f-149a-4c1e-b51f-db2f97de3c73
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32146921
92 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_rand_to_scrap.3214692192
Directory /workspace/1.chip_sw_lc_ctrl_rand_to_scrap/latest

Test location /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3858407014
Short name T124
Test name
Test status
Simulation time 7564233500 ps
CPU time 1026.47 seconds
Started Aug 02 08:21:25 PM PDT 24
Finished Aug 02 08:38:32 PM PDT 24
Peak memory 610564 kb
Host smart-6eeb5f3d-358e-4a1a-8d8d-75c4f73090e7
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38584070
14 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.3858407014
Directory /workspace/0.chip_sw_sensor_ctrl_alert/latest

Test location /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3253210456
Short name T212
Test name
Test status
Simulation time 8280963470 ps
CPU time 1389.6 seconds
Started Aug 02 08:45:47 PM PDT 24
Finished Aug 02 09:08:57 PM PDT 24
Peak memory 624516 kb
Host smart-b3594e14-59be-4463-b868-8b9730eb8dfc
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3253210456 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.3253210456
Directory /workspace/5.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/1.chip_plic_all_irqs_0.3819137786
Short name T337
Test name
Test status
Simulation time 6047505764 ps
CPU time 1215.53 seconds
Started Aug 02 08:31:01 PM PDT 24
Finished Aug 02 08:51:17 PM PDT 24
Peak memory 608908 kb
Host smart-bcc6aa48-ae4c-4fb8-8b46-d4b629e4ec76
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819137786 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.chip_plic_all_irqs_0.3819137786
Directory /workspace/1.chip_plic_all_irqs_0/latest

Test location /workspace/coverage/cover_reg_top/22.chip_tl_errors.1925252867
Short name T586
Test name
Test status
Simulation time 3166615699 ps
CPU time 189.99 seconds
Started Aug 02 07:56:25 PM PDT 24
Finished Aug 02 07:59:35 PM PDT 24
Peak memory 599080 kb
Host smart-f8ca1391-f1f9-4d2b-9ca5-30bab4e391d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925252867 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.chip_tl_errors.1925252867
Directory /workspace/22.chip_tl_errors/latest

Test location /workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.3649471914
Short name T57
Test name
Test status
Simulation time 3158259811 ps
CPU time 294.37 seconds
Started Aug 02 08:17:55 PM PDT 24
Finished Aug 02 08:22:50 PM PDT 24
Peak memory 619168 kb
Host smart-c398b40f-9349-4993-aa59-9bfa5d2e19f9
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649471914 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pinmux_sleep_retention.3649471914
Directory /workspace/0.chip_sw_spi_device_pinmux_sleep_retention/latest

Test location /workspace/coverage/default/2.chip_sw_sleep_pin_wake.3945699647
Short name T60
Test name
Test status
Simulation time 3862576710 ps
CPU time 280.26 seconds
Started Aug 02 08:34:42 PM PDT 24
Finished Aug 02 08:39:23 PM PDT 24
Peak memory 609508 kb
Host smart-136be823-5673-4a89-ace3-f944cd3f1643
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945699647
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.3945699647
Directory /workspace/2.chip_sw_sleep_pin_wake/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.263282964
Short name T75
Test name
Test status
Simulation time 3836582184 ps
CPU time 392.41 seconds
Started Aug 02 08:18:37 PM PDT 24
Finished Aug 02 08:25:11 PM PDT 24
Peak memory 608508 kb
Host smart-92e64540-8f88-4c76-9083-663789e183dd
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_aon_pullup_test:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263282
964 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_aon_pullup.263282964
Directory /workspace/0.chip_sw_usbdev_aon_pullup/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_stress_all.398869002
Short name T458
Test name
Test status
Simulation time 3139820105 ps
CPU time 217.01 seconds
Started Aug 02 07:55:49 PM PDT 24
Finished Aug 02 07:59:26 PM PDT 24
Peak memory 576020 kb
Host smart-a2bfb92d-bf4d-4dfc-adf4-3038eedace3b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398869002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.398869002
Directory /workspace/18.xbar_stress_all/latest

Test location /workspace/coverage/default/2.chip_plic_all_irqs_20.2761233053
Short name T335
Test name
Test status
Simulation time 4842929384 ps
CPU time 819.21 seconds
Started Aug 02 08:42:18 PM PDT 24
Finished Aug 02 08:55:57 PM PDT 24
Peak memory 610008 kb
Host smart-bdd49fe7-30ae-4669-ae80-6bdf6fa0a172
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761233053 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.chip_plic_all_irqs_20.2761233053
Directory /workspace/2.chip_plic_all_irqs_20/latest

Test location /workspace/coverage/default/0.chip_sw_spi_device_tpm.2443372186
Short name T43
Test name
Test status
Simulation time 3538627721 ps
CPU time 333.45 seconds
Started Aug 02 08:18:34 PM PDT 24
Finished Aug 02 08:24:07 PM PDT 24
Peak memory 618416 kb
Host smart-1bb11f92-36bb-4475-acc6-8abd040f35c3
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443372186 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_tpm.2443372186
Directory /workspace/0.chip_sw_spi_device_tpm/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.1166361615
Short name T849
Test name
Test status
Simulation time 15429132069 ps
CPU time 667.99 seconds
Started Aug 02 07:56:14 PM PDT 24
Finished Aug 02 08:07:22 PM PDT 24
Peak memory 575928 kb
Host smart-67e70e4c-8c92-43ad-8105-87e221b66de2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166361615 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_al
l_with_reset_error.1166361615
Directory /workspace/20.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1809512424
Short name T115
Test name
Test status
Simulation time 11175925229 ps
CPU time 2051.74 seconds
Started Aug 02 08:21:54 PM PDT 24
Finished Aug 02 08:56:06 PM PDT 24
Peak memory 617716 kb
Host smart-ef9419d2-0db4-45ba-ba27-4af59a32ec03
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1809512424 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en
_reduced_freq.1809512424
Directory /workspace/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.563656938
Short name T885
Test name
Test status
Simulation time 1732405703 ps
CPU time 200.6 seconds
Started Aug 02 07:56:38 PM PDT 24
Finished Aug 02 07:59:59 PM PDT 24
Peak memory 575936 kb
Host smart-1bbb76fe-5af2-4ec7-b840-2851aed273a0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563656938 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all
_with_reset_error.563656938
Directory /workspace/22.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/default/0.chip_plic_all_irqs_0.4031907559
Short name T340
Test name
Test status
Simulation time 5738897984 ps
CPU time 1088.66 seconds
Started Aug 02 08:21:34 PM PDT 24
Finished Aug 02 08:39:43 PM PDT 24
Peak memory 610184 kb
Host smart-79152733-d7a4-457c-b278-21fa819e44f3
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031907559 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.chip_plic_all_irqs_0.4031907559
Directory /workspace/0.chip_plic_all_irqs_0/latest

Test location /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.500870249
Short name T186
Test name
Test status
Simulation time 42408279938 ps
CPU time 4578.26 seconds
Started Aug 02 08:20:44 PM PDT 24
Finished Aug 02 09:37:03 PM PDT 24
Peak memory 620852 kb
Host smart-e57a5981-ef28-49cd-a01e-165d9f34a19e
User root
Command /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_
rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=500870249 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_rma_unlocked.500870249
Directory /workspace/0.chip_sw_flash_rma_unlocked/latest

Test location /workspace/coverage/cover_reg_top/12.chip_tl_errors.670191127
Short name T723
Test name
Test status
Simulation time 5241224950 ps
CPU time 439.53 seconds
Started Aug 02 07:54:04 PM PDT 24
Finished Aug 02 08:01:23 PM PDT 24
Peak memory 598636 kb
Host smart-f098f5ed-a902-4231-87e8-89f78cc51c42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670191127 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_tl_errors.670191127
Directory /workspace/12.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.3123080882
Short name T1578
Test name
Test status
Simulation time 9598276348 ps
CPU time 536.4 seconds
Started Aug 02 07:59:56 PM PDT 24
Finished Aug 02 08:08:52 PM PDT 24
Peak memory 577768 kb
Host smart-9a46e5b3-7b6d-40ad-976a-721163f9285d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123080882 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_al
l_with_reset_error.3123080882
Directory /workspace/38.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/default/78.chip_sw_all_escalation_resets.1516600304
Short name T365
Test name
Test status
Simulation time 5615314926 ps
CPU time 499.16 seconds
Started Aug 02 08:54:14 PM PDT 24
Finished Aug 02 09:02:33 PM PDT 24
Peak memory 650444 kb
Host smart-8a84f2dd-b18a-48b2-98b2-a5250f3ff227
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1516600304 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.1516600304
Directory /workspace/78.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/1.chip_sw_sleep_pin_wake.692303723
Short name T110
Test name
Test status
Simulation time 5967655906 ps
CPU time 553.04 seconds
Started Aug 02 08:24:45 PM PDT 24
Finished Aug 02 08:33:58 PM PDT 24
Peak memory 610852 kb
Host smart-35c2ed7b-42b8-4fc3-8753-35eab9e0f132
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692303723 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.692303723
Directory /workspace/1.chip_sw_sleep_pin_wake/latest

Test location /workspace/coverage/default/2.chip_plic_all_irqs_10.4060344544
Short name T150
Test name
Test status
Simulation time 3643511574 ps
CPU time 708.32 seconds
Started Aug 02 08:40:00 PM PDT 24
Finished Aug 02 08:51:48 PM PDT 24
Peak memory 609824 kb
Host smart-0c8e1917-5f01-4e01-b09b-f901e08e581a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060344544 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.chip_plic_all_irqs_10.4060344544
Directory /workspace/2.chip_plic_all_irqs_10/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_random.619015520
Short name T498
Test name
Test status
Simulation time 1822414868 ps
CPU time 61.97 seconds
Started Aug 02 08:00:33 PM PDT 24
Finished Aug 02 08:01:35 PM PDT 24
Peak memory 575852 kb
Host smart-fa9ae63e-8a36-47c9-b6d4-402982b6aa30
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619015520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random.619015520
Directory /workspace/43.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.2987112239
Short name T130
Test name
Test status
Simulation time 8153921015 ps
CPU time 418.57 seconds
Started Aug 02 07:51:48 PM PDT 24
Finished Aug 02 07:58:47 PM PDT 24
Peak memory 658672 kb
Host smart-4ef5348e-8a6f-4415-8529-e2c10028a882
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987112239 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_hw_r
eset.2987112239
Directory /workspace/0.chip_csr_hw_reset/latest

Test location /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.1620319875
Short name T236
Test name
Test status
Simulation time 49555464591 ps
CPU time 5633.17 seconds
Started Aug 02 08:38:10 PM PDT 24
Finished Aug 02 10:12:04 PM PDT 24
Peak memory 620892 kb
Host smart-56a37a80-2473-4add-9bb3-ae8e8f00ed13
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de
vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620319875 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c
hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip
_sw_lc_walkthrough_dev.1620319875
Directory /workspace/2.chip_sw_lc_walkthrough_dev/latest

Test location /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.726908788
Short name T113
Test name
Test status
Simulation time 23208770053 ps
CPU time 3072.19 seconds
Started Aug 02 08:36:36 PM PDT 24
Finished Aug 02 09:27:49 PM PDT 24
Peak memory 610916 kb
Host smart-e952a26d-d8f6-4e48-b06c-838b5b7b6c1c
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726908788 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_rst_inputs.726908788
Directory /workspace/1.chip_sw_ast_clk_rst_inputs/latest

Test location /workspace/coverage/cover_reg_top/3.chip_tl_errors.3625339436
Short name T557
Test name
Test status
Simulation time 3046158901 ps
CPU time 231.1 seconds
Started Aug 02 07:52:04 PM PDT 24
Finished Aug 02 07:55:55 PM PDT 24
Peak memory 599584 kb
Host smart-0e188267-43ef-44f6-b0aa-58eba99cc196
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625339436 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_tl_errors.3625339436
Directory /workspace/3.chip_tl_errors/latest

Test location /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.3046186303
Short name T36
Test name
Test status
Simulation time 3396143188 ps
CPU time 283.19 seconds
Started Aug 02 08:21:23 PM PDT 24
Finished Aug 02 08:26:06 PM PDT 24
Peak memory 609016 kb
Host smart-b0e83395-cb80-4c13-b5f6-f131896086eb
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046186303 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.chip_sw_spi_host_tx_rx.3046186303
Directory /workspace/0.chip_sw_spi_host_tx_rx/latest

Test location /workspace/coverage/default/0.chip_sw_uart_tx_rx.360836061
Short name T301
Test name
Test status
Simulation time 4871116248 ps
CPU time 583.37 seconds
Started Aug 02 08:17:00 PM PDT 24
Finished Aug 02 08:26:44 PM PDT 24
Peak memory 623976 kb
Host smart-cb2ef5fe-1865-4e48-b63f-e2d36134f22f
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360836061 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.360836061
Directory /workspace/0.chip_sw_uart_tx_rx/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_stress_all.2704586590
Short name T2087
Test name
Test status
Simulation time 15585675336 ps
CPU time 559.56 seconds
Started Aug 02 07:55:06 PM PDT 24
Finished Aug 02 08:04:26 PM PDT 24
Peak memory 575944 kb
Host smart-84edadac-9f5e-4711-af08-2fa81105cb70
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704586590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.2704586590
Directory /workspace/16.xbar_stress_all/latest

Test location /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3168536604
Short name T14
Test name
Test status
Simulation time 8575047979 ps
CPU time 1653.5 seconds
Started Aug 02 08:43:44 PM PDT 24
Finished Aug 02 09:11:18 PM PDT 24
Peak memory 619044 kb
Host smart-d9e2cc19-7bee-43ba-90eb-ef4cdc2467b6
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168536604 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx
_alt_clk_freq.3168536604
Directory /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.2345778570
Short name T2320
Test name
Test status
Simulation time 84240313438 ps
CPU time 1518.23 seconds
Started Aug 02 08:09:09 PM PDT 24
Finished Aug 02 08:34:28 PM PDT 24
Peak memory 576068 kb
Host smart-112283f0-9073-46e9-aac7-dbf3bf5309d1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345778570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_
device_slow_rsp.2345778570
Directory /workspace/95.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.3516008965
Short name T1159
Test name
Test status
Simulation time 4428147424 ps
CPU time 671.83 seconds
Started Aug 02 08:17:49 PM PDT 24
Finished Aug 02 08:29:02 PM PDT 24
Peak memory 624228 kb
Host smart-5016c51e-a13f-4a76-90a6-c55c5565dbc2
User root
Command /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516008965 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.3516008965
Directory /workspace/0.chip_sw_uart_tx_rx_idx2/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.2185520970
Short name T894
Test name
Test status
Simulation time 409870249 ps
CPU time 149.99 seconds
Started Aug 02 07:52:13 PM PDT 24
Finished Aug 02 07:54:43 PM PDT 24
Peak memory 576732 kb
Host smart-b648ef76-cce5-4322-b608-7c8702457150
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185520970 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all
_with_reset_error.2185520970
Directory /workspace/1.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.2036628790
Short name T887
Test name
Test status
Simulation time 16336638526 ps
CPU time 734.1 seconds
Started Aug 02 07:55:46 PM PDT 24
Finished Aug 02 08:08:01 PM PDT 24
Peak memory 575972 kb
Host smart-824b8154-cfc1-46f8-b01f-2e8d947cacfc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036628790 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_al
l_with_reset_error.2036628790
Directory /workspace/17.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.4014372249
Short name T87
Test name
Test status
Simulation time 10936561792 ps
CPU time 1404.44 seconds
Started Aug 02 08:30:34 PM PDT 24
Finished Aug 02 08:53:59 PM PDT 24
Peak memory 610996 kb
Host smart-fa20509c-3e49-449f-a5db-b765f218a755
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler
_lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014372249 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han
dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.chip_sw_alert_handler_lpg_sleep_mode_pings.4014372249
Directory /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest

Test location /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2405186539
Short name T35
Test name
Test status
Simulation time 5189270488 ps
CPU time 686.69 seconds
Started Aug 02 08:21:45 PM PDT 24
Finished Aug 02 08:33:13 PM PDT 24
Peak memory 621156 kb
Host smart-1d51caac-5c87-4bcc-8f76-e4cf03b10672
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240518
6539 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2405186539
Directory /workspace/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest

Test location /workspace/coverage/cover_reg_top/0.chip_tl_errors.3315464962
Short name T563
Test name
Test status
Simulation time 2953378072 ps
CPU time 166.05 seconds
Started Aug 02 07:51:47 PM PDT 24
Finished Aug 02 07:54:33 PM PDT 24
Peak memory 598540 kb
Host smart-0cf33e81-336a-438d-a07f-bae9eb3094fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315464962 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_tl_errors.3315464962
Directory /workspace/0.chip_tl_errors/latest

Test location /workspace/coverage/default/1.chip_plic_all_irqs_20.3932470826
Short name T331
Test name
Test status
Simulation time 3956457034 ps
CPU time 766.27 seconds
Started Aug 02 08:31:15 PM PDT 24
Finished Aug 02 08:44:02 PM PDT 24
Peak memory 609740 kb
Host smart-a0db2268-8b2f-492a-a9a6-61ad713c8f0a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932470826 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.chip_plic_all_irqs_20.3932470826
Directory /workspace/1.chip_plic_all_irqs_20/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.419817203
Short name T355
Test name
Test status
Simulation time 4979329115 ps
CPU time 672.61 seconds
Started Aug 02 08:36:24 PM PDT 24
Finished Aug 02 08:47:36 PM PDT 24
Peak memory 610260 kb
Host smart-df335b43-b77b-4ad9-ac4b-816642865b78
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_
rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=419817203 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.419817203
Directory /workspace/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3654143383
Short name T1014
Test name
Test status
Simulation time 4100558652 ps
CPU time 666.95 seconds
Started Aug 02 08:19:59 PM PDT 24
Finished Aug 02 08:31:06 PM PDT 24
Peak memory 612972 kb
Host smart-989b0de2-30b4-4788-978c-9fb15c7fe865
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654143383 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c
lkmgr_external_clk_src_for_sw_fast_dev.3654143383
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2518520771
Short name T155
Test name
Test status
Simulation time 2271180013 ps
CPU time 95.16 seconds
Started Aug 02 08:18:41 PM PDT 24
Finished Aug 02 08:20:18 PM PDT 24
Peak memory 623036 kb
Host smart-cb08e275-ff8e-4886-8f78-bc6c9bee1b98
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518520771 -assert nopost
proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.2518520771
Directory /workspace/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.3026955986
Short name T884
Test name
Test status
Simulation time 5519087877 ps
CPU time 338.82 seconds
Started Aug 02 08:02:57 PM PDT 24
Finished Aug 02 08:08:36 PM PDT 24
Peak memory 576840 kb
Host smart-0f2fa86b-5f72-4dae-979a-57bb6cccc0fe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026955986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all
_with_rand_reset.3026955986
Directory /workspace/58.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.chip_sw_all_escalation_resets.1571313604
Short name T333
Test name
Test status
Simulation time 5399071862 ps
CPU time 655.93 seconds
Started Aug 02 08:50:00 PM PDT 24
Finished Aug 02 09:00:56 PM PDT 24
Peak memory 650228 kb
Host smart-8f200e18-2586-4641-b3dd-4b4b514f10fb
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1571313604 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_all_escalation_resets.1571313604
Directory /workspace/46.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.2612312123
Short name T900
Test name
Test status
Simulation time 262484400 ps
CPU time 194.18 seconds
Started Aug 02 07:55:34 PM PDT 24
Finished Aug 02 07:58:48 PM PDT 24
Peak memory 576676 kb
Host smart-01cc09a9-9072-436e-809c-3f86d249ca74
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612312123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all
_with_rand_reset.2612312123
Directory /workspace/17.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.2264484460
Short name T907
Test name
Test status
Simulation time 3293288585 ps
CPU time 360.44 seconds
Started Aug 02 08:00:21 PM PDT 24
Finished Aug 02 08:06:21 PM PDT 24
Peak memory 576776 kb
Host smart-43bc50a1-aa1a-4397-982c-a635ad400faa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264484460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all
_with_rand_reset.2264484460
Directory /workspace/42.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.493638717
Short name T2486
Test name
Test status
Simulation time 689964475 ps
CPU time 179.24 seconds
Started Aug 02 08:03:55 PM PDT 24
Finished Aug 02 08:06:54 PM PDT 24
Peak memory 576688 kb
Host smart-47ad7dec-2794-4a03-9c57-c3a0d36a67fc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493638717 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all
_with_reset_error.493638717
Directory /workspace/63.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.398800232
Short name T407
Test name
Test status
Simulation time 15005430935 ps
CPU time 1818.52 seconds
Started Aug 02 07:54:15 PM PDT 24
Finished Aug 02 08:24:34 PM PDT 24
Peak memory 593204 kb
Host smart-86dfa0aa-c76d-4b7c-bc6b-3f9dce2cd296
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398800232 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.chip_same_csr_outstanding.398800232
Directory /workspace/13.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.1476536151
Short name T602
Test name
Test status
Simulation time 149935161963 ps
CPU time 2779.33 seconds
Started Aug 02 07:57:09 PM PDT 24
Finished Aug 02 08:43:29 PM PDT 24
Peak memory 576060 kb
Host smart-2e7e7b0d-fd2d-41a1-9f76-aa67462c4c55
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476536151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_
device_slow_rsp.1476536151
Directory /workspace/25.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/default/0.chip_sw_plic_sw_irq.1528603530
Short name T259
Test name
Test status
Simulation time 3125346536 ps
CPU time 242.3 seconds
Started Aug 02 08:19:23 PM PDT 24
Finished Aug 02 08:23:26 PM PDT 24
Peak memory 608436 kb
Host smart-59be2f40-38a5-485f-b7c7-a384044c73c3
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528603530 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.chip_sw_plic_sw_irq.1528603530
Directory /workspace/0.chip_sw_plic_sw_irq/latest

Test location /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.1606355729
Short name T187
Test name
Test status
Simulation time 44491847865 ps
CPU time 4942.46 seconds
Started Aug 02 08:23:05 PM PDT 24
Finished Aug 02 09:45:29 PM PDT 24
Peak memory 621188 kb
Host smart-981d0f08-29dd-4630-b7cc-864cce1f4303
User root
Command /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_
rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1606355729 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_rma_unlocked.1606355729
Directory /workspace/1.chip_sw_flash_rma_unlocked/latest

Test location /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.623219690
Short name T159
Test name
Test status
Simulation time 2270815427 ps
CPU time 110.91 seconds
Started Aug 02 08:26:13 PM PDT 24
Finished Aug 02 08:28:05 PM PDT 24
Peak memory 617072 kb
Host smart-87884010-7abb-4873-ba31-3806a86b7dbc
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes
t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=623219690 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.623219690
Directory /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest

Test location /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.2815949040
Short name T23
Test name
Test status
Simulation time 4069927728 ps
CPU time 384.52 seconds
Started Aug 02 08:20:15 PM PDT 24
Finished Aug 02 08:26:40 PM PDT 24
Peak memory 609236 kb
Host smart-b00233ff-8c6c-42d4-af6b-b50d59cba81b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815949040 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_outputs.2815949040
Directory /workspace/0.chip_sw_sysrst_ctrl_outputs/latest

Test location /workspace/coverage/default/49.chip_sw_all_escalation_resets.76401275
Short name T769
Test name
Test status
Simulation time 4183488732 ps
CPU time 454.85 seconds
Started Aug 02 08:50:19 PM PDT 24
Finished Aug 02 08:57:54 PM PDT 24
Peak memory 650016 kb
Host smart-9bd51736-c111-4002-b90d-ce8ee915fce9
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
76401275 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.76401275
Directory /workspace/49.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.1565164630
Short name T406
Test name
Test status
Simulation time 8815382416 ps
CPU time 786.17 seconds
Started Aug 02 07:55:07 PM PDT 24
Finished Aug 02 08:08:14 PM PDT 24
Peak memory 652944 kb
Host smart-2af4252c-b9e7-4a8d-845f-b02a8da2e2e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565164630 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.chip_csr_mem_rw_with_rand_reset.1565164630
Directory /workspace/16.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.1389229800
Short name T710
Test name
Test status
Simulation time 4471784058 ps
CPU time 558.38 seconds
Started Aug 02 08:32:23 PM PDT 24
Finished Aug 02 08:41:42 PM PDT 24
Peak memory 624452 kb
Host smart-1f237d26-4d87-49a7-84d8-fd92a6a3e402
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389229800 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.1389229800
Directory /workspace/1.chip_sw_rv_dm_access_after_escalation_reset/latest

Test location /workspace/coverage/cover_reg_top/17.chip_tl_errors.3716542875
Short name T725
Test name
Test status
Simulation time 4973252945 ps
CPU time 375.42 seconds
Started Aug 02 07:55:20 PM PDT 24
Finished Aug 02 08:01:35 PM PDT 24
Peak memory 598720 kb
Host smart-2eac6ed9-4f3e-484f-8758-2b1579296223
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716542875 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_tl_errors.3716542875
Directory /workspace/17.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/25.chip_tl_errors.558531879
Short name T575
Test name
Test status
Simulation time 3246378031 ps
CPU time 173.82 seconds
Started Aug 02 07:57:00 PM PDT 24
Finished Aug 02 07:59:54 PM PDT 24
Peak memory 603728 kb
Host smart-3409240e-324c-4b74-8123-a507b2625654
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558531879 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.chip_tl_errors.558531879
Directory /workspace/25.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.3411498044
Short name T2478
Test name
Test status
Simulation time 53216100535 ps
CPU time 898.26 seconds
Started Aug 02 08:06:06 PM PDT 24
Finished Aug 02 08:21:04 PM PDT 24
Peak memory 575916 kb
Host smart-3b42a72b-760c-43c3-8df1-2782011fb458
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411498044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_
device_slow_rsp.3411498044
Directory /workspace/78.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_config_host.4146642336
Short name T25
Test name
Test status
Simulation time 8904332414 ps
CPU time 2048.69 seconds
Started Aug 02 08:18:54 PM PDT 24
Finished Aug 02 08:53:05 PM PDT 24
Peak memory 608984 kb
Host smart-5a58b186-dc03-48cd-ad54-d4c325dc3b8e
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_config_host_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41466
42336 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_config_host.4146642336
Directory /workspace/0.chip_sw_usbdev_config_host/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.842930329
Short name T2677
Test name
Test status
Simulation time 763749046 ps
CPU time 158.27 seconds
Started Aug 02 07:51:45 PM PDT 24
Finished Aug 02 07:54:24 PM PDT 24
Peak memory 576748 kb
Host smart-f281f481-4ec4-4ead-8a6b-01eceedcba36
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842930329 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_
with_reset_error.842930329
Directory /workspace/0.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.1632217793
Short name T881
Test name
Test status
Simulation time 538676024 ps
CPU time 295.91 seconds
Started Aug 02 08:00:09 PM PDT 24
Finished Aug 02 08:05:05 PM PDT 24
Peak memory 576840 kb
Host smart-25ae46d8-31af-4fbe-b5d7-17294c400237
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632217793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all
_with_rand_reset.1632217793
Directory /workspace/41.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2021228706
Short name T822
Test name
Test status
Simulation time 4109986274 ps
CPU time 437.2 seconds
Started Aug 02 08:27:55 PM PDT 24
Finished Aug 02 08:35:13 PM PDT 24
Peak memory 648932 kb
Host smart-1d4859be-b113-4dbf-987f-57afdb36ea89
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021228706 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s
w_alert_handler_lpg_sleep_mode_alerts.2021228706
Directory /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3787772664
Short name T746
Test name
Test status
Simulation time 3579282568 ps
CPU time 358.27 seconds
Started Aug 02 08:46:08 PM PDT 24
Finished Aug 02 08:52:06 PM PDT 24
Peak memory 649112 kb
Host smart-5577d254-9a4f-480f-b1b1-3e474c69cfd0
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787772664 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3787772664
Directory /workspace/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/10.chip_sw_all_escalation_resets.1835700181
Short name T810
Test name
Test status
Simulation time 5007725128 ps
CPU time 558.02 seconds
Started Aug 02 08:47:51 PM PDT 24
Finished Aug 02 08:57:09 PM PDT 24
Peak memory 650284 kb
Host smart-75bec102-4bb0-4c8d-b85c-539bfab915b6
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1835700181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.1835700181
Directory /workspace/10.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.79694806
Short name T277
Test name
Test status
Simulation time 3982533828 ps
CPU time 432.24 seconds
Started Aug 02 08:47:09 PM PDT 24
Finished Aug 02 08:54:22 PM PDT 24
Peak memory 648888 kb
Host smart-67dca6fd-3b51-4daa-8c1b-a9e78ac1ca0f
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79694806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_
escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw
_alert_handler_lpg_sleep_mode_alerts.79694806
Directory /workspace/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.3984646883
Short name T1345
Test name
Test status
Simulation time 3551743352 ps
CPU time 263.75 seconds
Started Aug 02 08:46:08 PM PDT 24
Finished Aug 02 08:50:32 PM PDT 24
Peak memory 648812 kb
Host smart-b3c90980-16c9-441b-93a1-6d37342ac449
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984646883 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3984646883
Directory /workspace/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/12.chip_sw_all_escalation_resets.2766554001
Short name T373
Test name
Test status
Simulation time 4962196724 ps
CPU time 778.11 seconds
Started Aug 02 08:47:09 PM PDT 24
Finished Aug 02 09:00:08 PM PDT 24
Peak memory 649980 kb
Host smart-02e38702-0b43-47f0-a4e9-66984f8633ee
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2766554001 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.2766554001
Directory /workspace/12.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.3634608388
Short name T778
Test name
Test status
Simulation time 4280583560 ps
CPU time 469.17 seconds
Started Aug 02 08:48:38 PM PDT 24
Finished Aug 02 08:56:28 PM PDT 24
Peak memory 649416 kb
Host smart-d627be21-4da1-4116-9758-599881f8336f
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634608388 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3634608388
Directory /workspace/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/14.chip_sw_all_escalation_resets.3213954587
Short name T804
Test name
Test status
Simulation time 5434438740 ps
CPU time 691.44 seconds
Started Aug 02 08:47:49 PM PDT 24
Finished Aug 02 08:59:21 PM PDT 24
Peak memory 650356 kb
Host smart-5b577dd6-97ae-4eb1-a7ab-f6de6acaff5b
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3213954587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.3213954587
Directory /workspace/14.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.3070312936
Short name T285
Test name
Test status
Simulation time 4482352244 ps
CPU time 449.25 seconds
Started Aug 02 08:48:19 PM PDT 24
Finished Aug 02 08:55:48 PM PDT 24
Peak memory 649444 kb
Host smart-5600dad9-e69a-48af-a574-e76ab4d18244
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070312936 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3070312936
Directory /workspace/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3388299753
Short name T812
Test name
Test status
Simulation time 3654388072 ps
CPU time 544.24 seconds
Started Aug 02 08:47:51 PM PDT 24
Finished Aug 02 08:56:55 PM PDT 24
Peak memory 648972 kb
Host smart-d9fbee78-b630-42f7-9b63-fae3b76beaa4
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388299753 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3388299753
Directory /workspace/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/16.chip_sw_all_escalation_resets.2839141301
Short name T747
Test name
Test status
Simulation time 4134541526 ps
CPU time 606.79 seconds
Started Aug 02 08:47:46 PM PDT 24
Finished Aug 02 08:57:53 PM PDT 24
Peak memory 649800 kb
Host smart-df29094c-8117-43ce-b9da-a20a1d02b507
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2839141301 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.2839141301
Directory /workspace/16.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.37515448
Short name T381
Test name
Test status
Simulation time 3587282260 ps
CPU time 398.41 seconds
Started Aug 02 08:47:53 PM PDT 24
Finished Aug 02 08:54:31 PM PDT 24
Peak memory 649108 kb
Host smart-d32f79e8-068f-4cc5-98f6-57b8ee999ec5
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37515448 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_
escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw
_alert_handler_lpg_sleep_mode_alerts.37515448
Directory /workspace/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/18.chip_sw_all_escalation_resets.1019429584
Short name T787
Test name
Test status
Simulation time 5643764812 ps
CPU time 496.59 seconds
Started Aug 02 08:47:46 PM PDT 24
Finished Aug 02 08:56:03 PM PDT 24
Peak memory 650252 kb
Host smart-2fe071cc-0858-4c9e-9d84-307af9a11573
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1019429584 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.1019429584
Directory /workspace/18.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2324189550
Short name T780
Test name
Test status
Simulation time 4079266148 ps
CPU time 475.26 seconds
Started Aug 02 08:39:05 PM PDT 24
Finished Aug 02 08:47:00 PM PDT 24
Peak memory 649048 kb
Host smart-f1a28a4a-5214-4764-873a-ecf2ff74846e
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324189550 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s
w_alert_handler_lpg_sleep_mode_alerts.2324189550
Directory /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/2.chip_sw_all_escalation_resets.3901823225
Short name T273
Test name
Test status
Simulation time 4439410990 ps
CPU time 592.26 seconds
Started Aug 02 08:35:34 PM PDT 24
Finished Aug 02 08:45:26 PM PDT 24
Peak memory 650640 kb
Host smart-11b5f692-5171-47f7-be36-2445db1552ad
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3901823225 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.3901823225
Directory /workspace/2.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1369951425
Short name T784
Test name
Test status
Simulation time 3243406778 ps
CPU time 380.69 seconds
Started Aug 02 08:47:47 PM PDT 24
Finished Aug 02 08:54:08 PM PDT 24
Peak memory 648832 kb
Host smart-cd002f5e-5048-4447-ae96-4329d39cf051
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369951425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1369951425
Directory /workspace/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1401895762
Short name T740
Test name
Test status
Simulation time 3838445484 ps
CPU time 378.26 seconds
Started Aug 02 08:49:22 PM PDT 24
Finished Aug 02 08:55:41 PM PDT 24
Peak memory 649148 kb
Host smart-471aabdb-3d60-4b16-88c7-c0582d3a14e5
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401895762 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1401895762
Directory /workspace/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/21.chip_sw_all_escalation_resets.2702279397
Short name T818
Test name
Test status
Simulation time 4593186988 ps
CPU time 659.73 seconds
Started Aug 02 08:48:03 PM PDT 24
Finished Aug 02 08:59:03 PM PDT 24
Peak memory 650440 kb
Host smart-057822f4-a560-4b95-a016-5cf9b827a775
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2702279397 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.2702279397
Directory /workspace/21.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3757902940
Short name T802
Test name
Test status
Simulation time 3707041400 ps
CPU time 412.19 seconds
Started Aug 02 08:47:45 PM PDT 24
Finished Aug 02 08:54:38 PM PDT 24
Peak memory 649240 kb
Host smart-782676f5-d317-484c-8f34-6230dc8a8822
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757902940 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3757902940
Directory /workspace/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/22.chip_sw_all_escalation_resets.4156748381
Short name T819
Test name
Test status
Simulation time 5430335020 ps
CPU time 641.13 seconds
Started Aug 02 08:49:00 PM PDT 24
Finished Aug 02 08:59:41 PM PDT 24
Peak memory 650036 kb
Host smart-decf9867-6d15-4537-b15c-856eb9e4b35c
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4156748381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.4156748381
Directory /workspace/22.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.364038165
Short name T323
Test name
Test status
Simulation time 3344895140 ps
CPU time 349.1 seconds
Started Aug 02 08:50:00 PM PDT 24
Finished Aug 02 08:55:49 PM PDT 24
Peak memory 649312 kb
Host smart-0add64d6-9c77-42f8-8701-1107facc5ac5
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364038165 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_s
w_alert_handler_lpg_sleep_mode_alerts.364038165
Directory /workspace/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/25.chip_sw_all_escalation_resets.4122659123
Short name T363
Test name
Test status
Simulation time 5915814558 ps
CPU time 600.61 seconds
Started Aug 02 08:48:24 PM PDT 24
Finished Aug 02 08:58:25 PM PDT 24
Peak memory 650624 kb
Host smart-ad3968c3-9ce5-42d9-a8d6-cb3bfbd2f361
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4122659123 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.4122659123
Directory /workspace/25.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.2683361732
Short name T749
Test name
Test status
Simulation time 4127444750 ps
CPU time 398.56 seconds
Started Aug 02 08:48:51 PM PDT 24
Finished Aug 02 08:55:30 PM PDT 24
Peak memory 648740 kb
Host smart-14accc3c-31e6-4574-a1f0-64a302400900
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683361732 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2683361732
Directory /workspace/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1171351215
Short name T827
Test name
Test status
Simulation time 3488791100 ps
CPU time 411.71 seconds
Started Aug 02 08:49:29 PM PDT 24
Finished Aug 02 08:56:21 PM PDT 24
Peak memory 648996 kb
Host smart-92bea410-4559-4364-acee-da234e92623c
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171351215 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1171351215
Directory /workspace/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.4153647520
Short name T816
Test name
Test status
Simulation time 3363035180 ps
CPU time 335.41 seconds
Started Aug 02 08:43:31 PM PDT 24
Finished Aug 02 08:49:07 PM PDT 24
Peak memory 649048 kb
Host smart-214258c7-a9fa-4511-8673-b0c7fd048ac8
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153647520 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_s
w_alert_handler_lpg_sleep_mode_alerts.4153647520
Directory /workspace/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/30.chip_sw_all_escalation_resets.1810206637
Short name T1295
Test name
Test status
Simulation time 5477011934 ps
CPU time 648.52 seconds
Started Aug 02 08:48:14 PM PDT 24
Finished Aug 02 08:59:03 PM PDT 24
Peak memory 650212 kb
Host smart-af1c0494-3255-488e-bb0b-e15df0951927
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1810206637 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.1810206637
Directory /workspace/30.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2299985374
Short name T758
Test name
Test status
Simulation time 3329867368 ps
CPU time 351.19 seconds
Started Aug 02 08:48:29 PM PDT 24
Finished Aug 02 08:54:20 PM PDT 24
Peak memory 649164 kb
Host smart-4ae60bb3-b7d8-4c59-962c-1821696d62ed
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299985374 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2299985374
Directory /workspace/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3218939167
Short name T1292
Test name
Test status
Simulation time 3564859830 ps
CPU time 355.13 seconds
Started Aug 02 08:50:56 PM PDT 24
Finished Aug 02 08:56:51 PM PDT 24
Peak memory 649172 kb
Host smart-21e6415c-36fc-4e55-b0cf-9ab690a03570
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218939167 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3218939167
Directory /workspace/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/32.chip_sw_all_escalation_resets.748685586
Short name T792
Test name
Test status
Simulation time 5421626656 ps
CPU time 594.77 seconds
Started Aug 02 08:48:54 PM PDT 24
Finished Aug 02 08:58:49 PM PDT 24
Peak memory 650180 kb
Host smart-10e7e614-a495-4a58-b742-1fdde64ed687
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
748685586 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_all_escalation_resets.748685586
Directory /workspace/32.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1909042288
Short name T414
Test name
Test status
Simulation time 4035602566 ps
CPU time 382.22 seconds
Started Aug 02 08:51:04 PM PDT 24
Finished Aug 02 08:57:27 PM PDT 24
Peak memory 649056 kb
Host smart-db70f74c-0255-4bca-83a5-7a781a2d567c
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909042288 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1909042288
Directory /workspace/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2825970749
Short name T752
Test name
Test status
Simulation time 3563820392 ps
CPU time 358.57 seconds
Started Aug 02 08:49:51 PM PDT 24
Finished Aug 02 08:55:49 PM PDT 24
Peak memory 649132 kb
Host smart-842d6871-9999-4d2b-a720-4b86c0386782
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825970749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2825970749
Directory /workspace/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/35.chip_sw_all_escalation_resets.2420689377
Short name T272
Test name
Test status
Simulation time 5343432090 ps
CPU time 514.77 seconds
Started Aug 02 08:48:50 PM PDT 24
Finished Aug 02 08:57:25 PM PDT 24
Peak memory 650644 kb
Host smart-1f06304f-56da-427b-ab6e-285f274ac675
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2420689377 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.2420689377
Directory /workspace/35.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.723525722
Short name T545
Test name
Test status
Simulation time 3845924168 ps
CPU time 414.82 seconds
Started Aug 02 08:51:36 PM PDT 24
Finished Aug 02 08:58:31 PM PDT 24
Peak memory 648780 kb
Host smart-4563a1d9-dffa-4e17-8183-ae7aea4e4a27
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723525722 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_s
w_alert_handler_lpg_sleep_mode_alerts.723525722
Directory /workspace/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/38.chip_sw_all_escalation_resets.1092323937
Short name T745
Test name
Test status
Simulation time 4223761112 ps
CPU time 543.61 seconds
Started Aug 02 08:49:25 PM PDT 24
Finished Aug 02 08:58:29 PM PDT 24
Peak memory 650124 kb
Host smart-ca095189-bea9-40b7-ac17-903d6e00c3ea
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1092323937 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.1092323937
Directory /workspace/38.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/39.chip_sw_all_escalation_resets.2247808316
Short name T728
Test name
Test status
Simulation time 5155904852 ps
CPU time 529.59 seconds
Started Aug 02 08:50:55 PM PDT 24
Finished Aug 02 08:59:45 PM PDT 24
Peak memory 650040 kb
Host smart-442fb71e-8401-4390-ac27-f535d028d7cf
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2247808316 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.2247808316
Directory /workspace/39.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/4.chip_sw_all_escalation_resets.2810883399
Short name T770
Test name
Test status
Simulation time 5154296680 ps
CPU time 643.45 seconds
Started Aug 02 08:43:49 PM PDT 24
Finished Aug 02 08:54:33 PM PDT 24
Peak memory 650304 kb
Host smart-569cd4f0-0e6c-4d18-9b37-2ae0085cc65b
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2810883399 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.2810883399
Directory /workspace/4.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/40.chip_sw_all_escalation_resets.446636966
Short name T738
Test name
Test status
Simulation time 5307234252 ps
CPU time 651.61 seconds
Started Aug 02 08:50:02 PM PDT 24
Finished Aug 02 09:00:54 PM PDT 24
Peak memory 650652 kb
Host smart-1787a088-2765-4290-a0fb-c95916547a3a
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
446636966 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.446636966
Directory /workspace/40.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.4034803016
Short name T775
Test name
Test status
Simulation time 3811096000 ps
CPU time 383.65 seconds
Started Aug 02 08:49:36 PM PDT 24
Finished Aug 02 08:56:00 PM PDT 24
Peak memory 649244 kb
Host smart-c7a5b9d8-0fa3-465a-9050-201373045f62
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034803016 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_
sw_alert_handler_lpg_sleep_mode_alerts.4034803016
Directory /workspace/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1106778986
Short name T807
Test name
Test status
Simulation time 3558170408 ps
CPU time 319.98 seconds
Started Aug 02 08:50:31 PM PDT 24
Finished Aug 02 08:55:51 PM PDT 24
Peak memory 649108 kb
Host smart-86218377-01bd-4b66-9ded-d8b50972890b
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106778986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1106778986
Directory /workspace/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/45.chip_sw_all_escalation_resets.2912944854
Short name T210
Test name
Test status
Simulation time 4968375018 ps
CPU time 634.1 seconds
Started Aug 02 08:49:51 PM PDT 24
Finished Aug 02 09:00:26 PM PDT 24
Peak memory 650416 kb
Host smart-14ed0cb6-0c15-4502-a408-7c7b38fb929d
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2912944854 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.2912944854
Directory /workspace/45.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1228381714
Short name T829
Test name
Test status
Simulation time 4102162150 ps
CPU time 426.45 seconds
Started Aug 02 08:50:26 PM PDT 24
Finished Aug 02 08:57:33 PM PDT 24
Peak memory 649176 kb
Host smart-23b3de62-b628-4b71-b512-d437694ae33a
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228381714 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1228381714
Directory /workspace/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1012436192
Short name T801
Test name
Test status
Simulation time 3187359416 ps
CPU time 377.05 seconds
Started Aug 02 08:51:52 PM PDT 24
Finished Aug 02 08:58:09 PM PDT 24
Peak memory 648796 kb
Host smart-4640d095-be80-4b7c-bf6e-769b607c0363
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012436192 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1012436192
Directory /workspace/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2347039454
Short name T825
Test name
Test status
Simulation time 4049867752 ps
CPU time 358.8 seconds
Started Aug 02 08:51:03 PM PDT 24
Finished Aug 02 08:57:02 PM PDT 24
Peak memory 649100 kb
Host smart-901b7034-544f-43c7-859f-a3a5e3f6b979
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347039454 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2347039454
Directory /workspace/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.572243814
Short name T739
Test name
Test status
Simulation time 3231157264 ps
CPU time 379.85 seconds
Started Aug 02 08:52:43 PM PDT 24
Finished Aug 02 08:59:03 PM PDT 24
Peak memory 648724 kb
Host smart-af54b232-d88e-4f69-8c44-0a8f3b6fd75e
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572243814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_s
w_alert_handler_lpg_sleep_mode_alerts.572243814
Directory /workspace/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/6.chip_sw_all_escalation_resets.1374048956
Short name T371
Test name
Test status
Simulation time 5470310478 ps
CPU time 629.22 seconds
Started Aug 02 08:46:54 PM PDT 24
Finished Aug 02 08:57:24 PM PDT 24
Peak memory 650032 kb
Host smart-d23e16dc-0044-4807-aca7-3dea3c00252a
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1374048956 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.1374048956
Directory /workspace/6.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.317281973
Short name T795
Test name
Test status
Simulation time 4279379750 ps
CPU time 487.96 seconds
Started Aug 02 08:53:28 PM PDT 24
Finished Aug 02 09:01:36 PM PDT 24
Peak memory 649224 kb
Host smart-11f06ce9-8547-4338-a953-2e7913536c63
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317281973 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_s
w_alert_handler_lpg_sleep_mode_alerts.317281973
Directory /workspace/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3059082698
Short name T777
Test name
Test status
Simulation time 3669043992 ps
CPU time 427.98 seconds
Started Aug 02 08:53:34 PM PDT 24
Finished Aug 02 09:00:42 PM PDT 24
Peak memory 649140 kb
Host smart-b30173b9-efff-4f9f-b44a-65188c413b01
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059082698 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3059082698
Directory /workspace/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/68.chip_sw_all_escalation_resets.2687964049
Short name T824
Test name
Test status
Simulation time 4985435736 ps
CPU time 466.06 seconds
Started Aug 02 08:52:20 PM PDT 24
Finished Aug 02 09:00:07 PM PDT 24
Peak memory 650284 kb
Host smart-39a0562f-621c-4fed-bbe0-0850476cfa05
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2687964049 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.2687964049
Directory /workspace/68.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.623535567
Short name T731
Test name
Test status
Simulation time 3878267000 ps
CPU time 349.67 seconds
Started Aug 02 08:48:18 PM PDT 24
Finished Aug 02 08:54:08 PM PDT 24
Peak memory 649160 kb
Host smart-9157d943-a2dc-4968-af39-755232eede21
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623535567 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw
_alert_handler_lpg_sleep_mode_alerts.623535567
Directory /workspace/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/70.chip_sw_all_escalation_resets.4177923227
Short name T91
Test name
Test status
Simulation time 5181271720 ps
CPU time 674.14 seconds
Started Aug 02 08:53:31 PM PDT 24
Finished Aug 02 09:04:45 PM PDT 24
Peak memory 650608 kb
Host smart-930f7c3a-efdd-4440-bc0b-530b57551c6c
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4177923227 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.4177923227
Directory /workspace/70.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.498170208
Short name T826
Test name
Test status
Simulation time 4043989548 ps
CPU time 405.33 seconds
Started Aug 02 08:53:35 PM PDT 24
Finished Aug 02 09:00:20 PM PDT 24
Peak memory 649088 kb
Host smart-58ae0b27-4972-4a72-8f6c-9d89971a499e
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498170208 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_s
w_alert_handler_lpg_sleep_mode_alerts.498170208
Directory /workspace/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/75.chip_sw_all_escalation_resets.4021629462
Short name T362
Test name
Test status
Simulation time 5578501200 ps
CPU time 650.32 seconds
Started Aug 02 08:55:45 PM PDT 24
Finished Aug 02 09:06:36 PM PDT 24
Peak memory 650176 kb
Host smart-6200d040-d004-4ac8-9027-3826c130b8df
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4021629462 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.4021629462
Directory /workspace/75.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/79.chip_sw_all_escalation_resets.966808421
Short name T830
Test name
Test status
Simulation time 4711722354 ps
CPU time 761.75 seconds
Started Aug 02 08:55:31 PM PDT 24
Finished Aug 02 09:08:13 PM PDT 24
Peak memory 650280 kb
Host smart-4cde03ef-fb8f-4f66-9919-914951e2edac
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
966808421 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_all_escalation_resets.966808421
Directory /workspace/79.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2182751006
Short name T831
Test name
Test status
Simulation time 3892864616 ps
CPU time 371.45 seconds
Started Aug 02 08:54:03 PM PDT 24
Finished Aug 02 09:00:14 PM PDT 24
Peak memory 648836 kb
Host smart-857301f0-da10-46ac-81ce-c50bb65693a4
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182751006 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2182751006
Directory /workspace/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/81.chip_sw_all_escalation_resets.3901795348
Short name T821
Test name
Test status
Simulation time 4062590600 ps
CPU time 458.6 seconds
Started Aug 02 08:53:51 PM PDT 24
Finished Aug 02 09:01:30 PM PDT 24
Peak memory 649944 kb
Host smart-487417c0-c32f-4f8b-bac9-2507d6f346ee
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3901795348 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.3901795348
Directory /workspace/81.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1190150323
Short name T797
Test name
Test status
Simulation time 3742500094 ps
CPU time 347.57 seconds
Started Aug 02 08:54:36 PM PDT 24
Finished Aug 02 09:00:24 PM PDT 24
Peak memory 649236 kb
Host smart-be2d5ac5-9e77-46b3-bbc6-1463944bfe17
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190150323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1190150323
Directory /workspace/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1685553995
Short name T814
Test name
Test status
Simulation time 3689878784 ps
CPU time 382.74 seconds
Started Aug 02 08:55:06 PM PDT 24
Finished Aug 02 09:01:29 PM PDT 24
Peak memory 648784 kb
Host smart-41fe2ec3-32dd-478c-a6a1-3a7f56d72046
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685553995 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1685553995
Directory /workspace/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.755405162
Short name T798
Test name
Test status
Simulation time 3915552162 ps
CPU time 337.95 seconds
Started Aug 02 08:55:58 PM PDT 24
Finished Aug 02 09:01:36 PM PDT 24
Peak memory 649008 kb
Host smart-806075a6-f295-4e61-945e-e4cb6e4be8f6
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755405162 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_s
w_alert_handler_lpg_sleep_mode_alerts.755405162
Directory /workspace/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/93.chip_sw_all_escalation_resets.1812011381
Short name T372
Test name
Test status
Simulation time 4951503240 ps
CPU time 411.42 seconds
Started Aug 02 08:54:42 PM PDT 24
Finished Aug 02 09:01:33 PM PDT 24
Peak memory 650532 kb
Host smart-a7380340-d817-4821-a8f4-5c4bc0a1c859
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1812011381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.1812011381
Directory /workspace/93.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/0.chip_sw_sleep_pin_wake.3439226336
Short name T61
Test name
Test status
Simulation time 5744303794 ps
CPU time 342.59 seconds
Started Aug 02 08:18:39 PM PDT 24
Finished Aug 02 08:24:22 PM PDT 24
Peak memory 610984 kb
Host smart-211b5f88-cc53-4c50-a83c-056b9b538205
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439226336
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.3439226336
Directory /workspace/0.chip_sw_sleep_pin_wake/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_stress_all.214614757
Short name T467
Test name
Test status
Simulation time 1829407942 ps
CPU time 167.37 seconds
Started Aug 02 07:56:46 PM PDT 24
Finished Aug 02 07:59:33 PM PDT 24
Peak memory 576068 kb
Host smart-9a8b859b-a7a9-4667-aaad-b117c0448c1b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214614757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.214614757
Directory /workspace/23.xbar_stress_all/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2548536299
Short name T380
Test name
Test status
Simulation time 6025049492 ps
CPU time 531.1 seconds
Started Aug 02 08:22:50 PM PDT 24
Finished Aug 02 08:31:42 PM PDT 24
Peak memory 611112 kb
Host smart-08b4299e-7036-4a25-b55b-775b8d7ce9e5
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul
es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2548536299 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sensor_ctrl_deep_s
leep_wake_up.2548536299
Directory /workspace/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest

Test location /workspace/coverage/default/1.chip_plic_all_irqs_10.969047435
Short name T151
Test name
Test status
Simulation time 4681124416 ps
CPU time 544.8 seconds
Started Aug 02 08:31:09 PM PDT 24
Finished Aug 02 08:40:14 PM PDT 24
Peak memory 610148 kb
Host smart-c3128778-8fd0-466e-8df9-5d0030fa1feb
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969047435 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.chip_plic_all_irqs_10.969047435
Directory /workspace/1.chip_plic_all_irqs_10/latest

Test location /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3424711367
Short name T250
Test name
Test status
Simulation time 11084397884 ps
CPU time 1809.27 seconds
Started Aug 02 08:25:19 PM PDT 24
Finished Aug 02 08:55:29 PM PDT 24
Peak memory 610776 kb
Host smart-552eb313-e421-4926-9299-e73d8bc12617
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test
_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb
_random_seed=3424711367 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.3424711367
Directory /workspace/1.chip_sw_rstmgr_alert_info/latest

Test location /workspace/coverage/default/54.chip_sw_all_escalation_resets.3656044467
Short name T268
Test name
Test status
Simulation time 5417267544 ps
CPU time 476.37 seconds
Started Aug 02 08:51:27 PM PDT 24
Finished Aug 02 08:59:23 PM PDT 24
Peak memory 610964 kb
Host smart-a5d1cc8c-2fef-49c6-a727-f764dd867f43
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3656044467 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.3656044467
Directory /workspace/54.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.2148253012
Short name T129
Test name
Test status
Simulation time 4558553040 ps
CPU time 251.26 seconds
Started Aug 02 07:52:35 PM PDT 24
Finished Aug 02 07:56:47 PM PDT 24
Peak memory 661564 kb
Host smart-0f48a3c9-88a2-4f74-b171-75913b39ebf3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148253012 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_hw_r
eset.2148253012
Directory /workspace/4.chip_csr_hw_reset/latest

Test location /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.2814743111
Short name T171
Test name
Test status
Simulation time 46597879361 ps
CPU time 5437.58 seconds
Started Aug 02 08:18:43 PM PDT 24
Finished Aug 02 09:49:22 PM PDT 24
Peak memory 620552 kb
Host smart-d805c933-6c5f-456b-94c1-cb01b8d68be1
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de
vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814743111 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c
hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip
_sw_lc_walkthrough_rma.2814743111
Directory /workspace/0.chip_sw_lc_walkthrough_rma/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1438934343
Short name T138
Test name
Test status
Simulation time 8412953176 ps
CPU time 560.37 seconds
Started Aug 02 08:22:40 PM PDT 24
Finished Aug 02 08:32:00 PM PDT 24
Peak memory 610836 kb
Host smart-7f5b7be3-e0b7-4375-b80a-ef44de883128
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438934343 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.chip_sw_pwrmgr_full_aon_reset.1438934343
Directory /workspace/0.chip_sw_pwrmgr_full_aon_reset/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.591990282
Short name T157
Test name
Test status
Simulation time 2455394096 ps
CPU time 219.72 seconds
Started Aug 02 08:40:24 PM PDT 24
Finished Aug 02 08:44:04 PM PDT 24
Peak memory 623908 kb
Host smart-0ecc285e-9e5f-4466-ade3-3d02d55ba0e5
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591990282 -assert nopostp
roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.591990282
Directory /workspace/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest

Test location /workspace/coverage/default/2.chip_tap_straps_dev.1621858747
Short name T713
Test name
Test status
Simulation time 9609975278 ps
CPU time 941.39 seconds
Started Aug 02 08:39:56 PM PDT 24
Finished Aug 02 08:55:37 PM PDT 24
Peak memory 621072 kb
Host smart-bcab7d51-12df-44e6-959f-8257fdbce2e1
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:
new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1621858747 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.1621858747
Directory /workspace/2.chip_tap_straps_dev/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.1863082977
Short name T2124
Test name
Test status
Simulation time 5791923221 ps
CPU time 457.37 seconds
Started Aug 02 07:54:02 PM PDT 24
Finished Aug 02 08:01:39 PM PDT 24
Peak memory 576840 kb
Host smart-ed229ee2-f3ff-4534-805f-4a2eb921285a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863082977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all
_with_rand_reset.1863082977
Directory /workspace/10.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.chip_tl_errors.1448672495
Short name T566
Test name
Test status
Simulation time 3995204200 ps
CPU time 214.53 seconds
Started Aug 02 07:54:08 PM PDT 24
Finished Aug 02 07:57:42 PM PDT 24
Peak memory 603752 kb
Host smart-93f3d4ad-eba2-4a54-9364-0493df44162e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448672495 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_tl_errors.1448672495
Directory /workspace/11.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.2167349613
Short name T645
Test name
Test status
Simulation time 12684913033 ps
CPU time 435.26 seconds
Started Aug 02 07:54:04 PM PDT 24
Finished Aug 02 08:01:20 PM PDT 24
Peak memory 576196 kb
Host smart-542fbbad-dc8f-4e96-be0d-5e7d327e802e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167349613 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.2167349613
Directory /workspace/11.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.1200139949
Short name T489
Test name
Test status
Simulation time 8690926055 ps
CPU time 83.97 seconds
Started Aug 02 07:54:02 PM PDT 24
Finished Aug 02 07:55:26 PM PDT 24
Peak memory 574684 kb
Host smart-66a83125-5ee3-4186-9dc3-bca52e04d9f7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200139949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.1200139949
Directory /workspace/12.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/8.chip_tl_errors.1500305220
Short name T619
Test name
Test status
Simulation time 3862936492 ps
CPU time 325.53 seconds
Started Aug 02 07:53:13 PM PDT 24
Finished Aug 02 07:58:39 PM PDT 24
Peak memory 603784 kb
Host smart-4862d420-8274-4bd8-8d89-cecd80ad4e34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500305220 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_tl_errors.1500305220
Directory /workspace/8.chip_tl_errors/latest

Test location /workspace/coverage/default/0.chip_sw_entropy_src_csrng.1482731946
Short name T343
Test name
Test status
Simulation time 5682239738 ps
CPU time 1138.43 seconds
Started Aug 02 08:20:20 PM PDT 24
Finished Aug 02 08:39:18 PM PDT 24
Peak memory 609352 kb
Host smart-bf3a7bb3-f00a-414f-b9a4-1d5003b5eac9
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_
csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1482731946 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.1482731946
Directory /workspace/0.chip_sw_entropy_src_csrng/latest

Test location /workspace/coverage/default/0.chip_sw_pattgen_ios.3171708004
Short name T106
Test name
Test status
Simulation time 2835565216 ps
CPU time 247.02 seconds
Started Aug 02 08:17:19 PM PDT 24
Finished Aug 02 08:21:27 PM PDT 24
Peak memory 612452 kb
Host smart-8af05d67-786f-4ad2-9d03-0b66ba0614c4
User root
Command /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171708004 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.3171708004
Directory /workspace/0.chip_sw_pattgen_ios/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.1301143683
Short name T98
Test name
Test status
Simulation time 3301782360 ps
CPU time 306.43 seconds
Started Aug 02 08:23:33 PM PDT 24
Finished Aug 02 08:28:40 PM PDT 24
Peak memory 609836 kb
Host smart-099a55b7-ad23-4381-9ac1-8e789f9626e9
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301143683 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.chip_sw_pwrmgr_lowpower_cancel.1301143683
Directory /workspace/0.chip_sw_pwrmgr_lowpower_cancel/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.3515962630
Short name T356
Test name
Test status
Simulation time 3884075572 ps
CPU time 752.15 seconds
Started Aug 02 08:35:19 PM PDT 24
Finished Aug 02 08:47:52 PM PDT 24
Peak memory 609852 kb
Host smart-f9f8ea72-bbb8-4740-a960-277799b07566
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515962630
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.3515962630
Directory /workspace/2.chip_sw_flash_ctrl_ops/latest

Test location /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.501991608
Short name T942
Test name
Test status
Simulation time 19490508060 ps
CPU time 603.67 seconds
Started Aug 02 08:18:08 PM PDT 24
Finished Aug 02 08:28:13 PM PDT 24
Peak memory 619692 kb
Host smart-e9705dfd-2a1e-4526-a465-09f7778f0e3b
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom:
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=501991608 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.501991608
Directory /workspace/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest

Test location /workspace/coverage/default/0.chip_sw_power_idle_load.3958930235
Short name T219
Test name
Test status
Simulation time 4393426230 ps
CPU time 636.62 seconds
Started Aug 02 08:21:24 PM PDT 24
Finished Aug 02 08:32:01 PM PDT 24
Peak memory 609244 kb
Host smart-f13d4221-f77e-431f-a51e-ab812b20bc77
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958930235 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.chip_sw_power_idle_load.3958930235
Directory /workspace/0.chip_sw_power_idle_load/latest

Test location /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3903316019
Short name T38
Test name
Test status
Simulation time 2603472912 ps
CPU time 254.41 seconds
Started Aug 02 08:34:50 PM PDT 24
Finished Aug 02 08:39:05 PM PDT 24
Peak memory 608940 kb
Host smart-7d6000ce-ba52-497c-b3af-e91a2ef3d0a6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903316019 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.chip_sw_spi_host_tx_rx.3903316019
Directory /workspace/2.chip_sw_spi_host_tx_rx/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2910708501
Short name T319
Test name
Test status
Simulation time 7691331290 ps
CPU time 1711.72 seconds
Started Aug 02 08:19:55 PM PDT 24
Finished Aug 02 08:48:28 PM PDT 24
Peak memory 610232 kb
Host smart-092e664a-ebce-433e-b211-becf520bf75d
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2910708501 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.2910708501
Directory /workspace/0.chip_sw_alert_handler_lpg_clkoff/latest

Test location /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.854186742
Short name T957
Test name
Test status
Simulation time 8157028680 ps
CPU time 1486.45 seconds
Started Aug 02 08:22:23 PM PDT 24
Finished Aug 02 08:47:10 PM PDT 24
Peak memory 610672 kb
Host smart-ec49bb51-8ab8-4b9c-a27b-01df63c65d94
User root
Command /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed
n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=854186742 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.854186742
Directory /workspace/0.chip_sw_edn_entropy_reqs/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.2061496238
Short name T164
Test name
Test status
Simulation time 4333318520 ps
CPU time 360.08 seconds
Started Aug 02 08:21:29 PM PDT 24
Finished Aug 02 08:27:29 PM PDT 24
Peak memory 611032 kb
Host smart-1c00ed82-11c8-4324-9fc0-c7a98278ccf9
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2061496238 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_program_error.2061496238
Directory /workspace/0.chip_sw_lc_ctrl_program_error/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2727572327
Short name T62
Test name
Test status
Simulation time 7707110320 ps
CPU time 533.42 seconds
Started Aug 02 08:18:44 PM PDT 24
Finished Aug 02 08:27:40 PM PDT 24
Peak memory 616732 kb
Host smart-aff063be-8b64-439c-81e0-e2785553946d
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2727572327 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2727572327
Directory /workspace/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest

Test location /workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.3714750373
Short name T544
Test name
Test status
Simulation time 11783196808 ps
CPU time 1124.21 seconds
Started Aug 02 07:54:02 PM PDT 24
Finished Aug 02 08:12:46 PM PDT 24
Peak memory 653028 kb
Host smart-83d785d4-4c31-4a2e-a657-0977a74f301f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714750373 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.chip_csr_mem_rw_with_rand_reset.3714750373
Directory /workspace/11.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.118264877
Short name T709
Test name
Test status
Simulation time 30499547912 ps
CPU time 1263.1 seconds
Started Aug 02 07:58:36 PM PDT 24
Finished Aug 02 08:19:40 PM PDT 24
Peak memory 576816 kb
Host smart-e78877a3-ec32-4663-b24c-8ca841059d53
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118264877 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all
_with_reset_error.118264877
Directory /workspace/32.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.3873586453
Short name T657
Test name
Test status
Simulation time 10812621590 ps
CPU time 605.45 seconds
Started Aug 02 08:00:56 PM PDT 24
Finished Aug 02 08:11:01 PM PDT 24
Peak memory 578396 kb
Host smart-6f91859d-3f39-4c0e-be87-bbc24870c4b5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873586453 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_al
l_with_reset_error.3873586453
Directory /workspace/45.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.2782952630
Short name T650
Test name
Test status
Simulation time 3506437827 ps
CPU time 268.1 seconds
Started Aug 02 08:01:40 PM PDT 24
Finished Aug 02 08:06:08 PM PDT 24
Peak memory 576048 kb
Host smart-cffb93f1-6252-4c7e-b260-110d8453b589
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782952630 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_error.2782952630
Directory /workspace/50.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.2634591455
Short name T649
Test name
Test status
Simulation time 178637105 ps
CPU time 9.8 seconds
Started Aug 02 07:52:59 PM PDT 24
Finished Aug 02 07:53:09 PM PDT 24
Peak memory 576044 kb
Host smart-fbb67227-896b-4fc3-a2a5-c7f23825b980
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634591455 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr
.2634591455
Directory /workspace/6.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.2227135851
Short name T661
Test name
Test status
Simulation time 8643420093 ps
CPU time 336.2 seconds
Started Aug 02 07:53:11 PM PDT 24
Finished Aug 02 07:58:47 PM PDT 24
Peak memory 576016 kb
Host smart-749abbc5-2742-4b22-9c5a-620c0d4a9879
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227135851 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.2227135851
Directory /workspace/7.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.1976054283
Short name T660
Test name
Test status
Simulation time 17865459707 ps
CPU time 601.65 seconds
Started Aug 02 08:04:58 PM PDT 24
Finished Aug 02 08:15:00 PM PDT 24
Peak memory 575960 kb
Host smart-f3069bac-018f-413d-a4c8-093af926e63e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976054283 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_error.1976054283
Directory /workspace/70.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.2868668536
Short name T648
Test name
Test status
Simulation time 22667487755 ps
CPU time 959.59 seconds
Started Aug 02 08:05:53 PM PDT 24
Finished Aug 02 08:21:53 PM PDT 24
Peak memory 576800 kb
Host smart-4a775fef-339d-417a-8c13-5c5afb866f3d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868668536 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_al
l_with_reset_error.2868668536
Directory /workspace/76.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.3045486506
Short name T654
Test name
Test status
Simulation time 9270198899 ps
CPU time 318.77 seconds
Started Aug 02 08:08:43 PM PDT 24
Finished Aug 02 08:14:02 PM PDT 24
Peak memory 576324 kb
Host smart-517e1778-b99e-4d93-9c8f-21a5fa35c30c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045486506 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_error.3045486506
Directory /workspace/91.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.856206380
Short name T646
Test name
Test status
Simulation time 2633737325 ps
CPU time 291.08 seconds
Started Aug 02 08:08:42 PM PDT 24
Finished Aug 02 08:13:33 PM PDT 24
Peak memory 576816 kb
Host smart-ff758a5b-ed0c-428e-85d6-9b6eb8669918
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856206380 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all
_with_reset_error.856206380
Directory /workspace/91.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.213747915
Short name T348
Test name
Test status
Simulation time 4902764592 ps
CPU time 824.77 seconds
Started Aug 02 08:17:18 PM PDT 24
Finished Aug 02 08:31:03 PM PDT 24
Peak memory 609208 kb
Host smart-e8b5dd2b-98b9-4ddb-90eb-45e5b759c36c
User root
Command /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213747915 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx.213747915
Directory /workspace/0.chip_sw_i2c_host_tx_rx/latest

Test location /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.4197483939
Short name T341
Test name
Test status
Simulation time 11029317470 ps
CPU time 1671.25 seconds
Started Aug 02 08:21:57 PM PDT 24
Finished Aug 02 08:49:48 PM PDT 24
Peak memory 610940 kb
Host smart-f9de050d-68b9-4514-a295-13a75fe51cf8
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test
_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb
_random_seed=4197483939 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.4197483939
Directory /workspace/0.chip_sw_rstmgr_alert_info/latest

Test location /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1767049758
Short name T264
Test name
Test status
Simulation time 4611663320 ps
CPU time 945.32 seconds
Started Aug 02 08:19:54 PM PDT 24
Finished Aug 02 08:35:40 PM PDT 24
Peak memory 610076 kb
Host smart-bd1d2039-b8f5-4b6b-8821-e62eb429d577
User root
Command /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17670
49758 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.1767049758
Directory /workspace/0.chip_sw_rv_core_ibex_nmi_irq/latest

Test location /workspace/coverage/default/1.chip_sw_gpio.833843169
Short name T31
Test name
Test status
Simulation time 4314457949 ps
CPU time 375.22 seconds
Started Aug 02 08:21:57 PM PDT 24
Finished Aug 02 08:28:13 PM PDT 24
Peak memory 610032 kb
Host smart-c1ade542-7b89-4c33-a6dc-632b0178454a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833843169 -assert nopostproc +UVM_TESTNAME=chip_base
_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.chip_sw_gpio.833843169
Directory /workspace/1.chip_sw_gpio/latest

Test location /workspace/coverage/default/3.chip_tap_straps_rma.1789483276
Short name T67
Test name
Test status
Simulation time 3690210952 ps
CPU time 360.97 seconds
Started Aug 02 08:43:28 PM PDT 24
Finished Aug 02 08:49:31 PM PDT 24
Peak memory 621032 kb
Host smart-a27d3134-7c28-411d-b643-812f9aea889d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789483276 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_rma.1789483276
Directory /workspace/3.chip_tap_straps_rma/latest

Test location /workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.541042068
Short name T1571
Test name
Test status
Simulation time 13079301475 ps
CPU time 508.32 seconds
Started Aug 02 07:51:42 PM PDT 24
Finished Aug 02 08:00:11 PM PDT 24
Peak memory 598560 kb
Host smart-65949403-d8a1-4ccb-a843-64d703ba65cf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541042068 -assert nopostproc +UVM_TESTNAME=chip_base_te
st +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.chip_rv_dm_lc_disabled.541042068
Directory /workspace/0.chip_rv_dm_lc_disabled/latest

Test location /workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.3832277558
Short name T128
Test name
Test status
Simulation time 6350284270 ps
CPU time 371.38 seconds
Started Aug 02 07:52:03 PM PDT 24
Finished Aug 02 07:58:15 PM PDT 24
Peak memory 662000 kb
Host smart-fd154289-5afe-4030-9f02-67c6e0fa31e0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832277558 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_hw_r
eset.3832277558
Directory /workspace/2.chip_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_random.3561237250
Short name T84
Test name
Test status
Simulation time 71143428 ps
CPU time 8.31 seconds
Started Aug 02 08:02:46 PM PDT 24
Finished Aug 02 08:02:55 PM PDT 24
Peak memory 575876 kb
Host smart-f1960133-78d7-4ab3-b40c-fd1e7584b00f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561237250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random.3561237250
Directory /workspace/58.xbar_random/latest

Test location /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3897020736
Short name T928
Test name
Test status
Simulation time 3251531048 ps
CPU time 220.69 seconds
Started Aug 02 08:22:10 PM PDT 24
Finished Aug 02 08:25:51 PM PDT 24
Peak memory 608396 kb
Host smart-77b34b79-4da4-45df-add5-98e6021ffb5d
User root
Command /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,
test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3897020736 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.3897020736
Directory /workspace/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_edn_boot_mode.1911663591
Short name T687
Test name
Test status
Simulation time 2724018884 ps
CPU time 575.21 seconds
Started Aug 02 08:20:40 PM PDT 24
Finished Aug 02 08:30:16 PM PDT 24
Peak memory 610028 kb
Host smart-fb0b4cb3-b910-442d-983b-5a5cecf30193
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_
build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911663591 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_
boot_mode.1911663591
Directory /workspace/0.chip_sw_edn_boot_mode/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.4252536399
Short name T229
Test name
Test status
Simulation time 10731986064 ps
CPU time 2377.46 seconds
Started Aug 02 08:19:54 PM PDT 24
Finished Aug 02 08:59:32 PM PDT 24
Peak memory 617880 kb
Host smart-0c190a4a-a46a-483f-bc35-25560faca0dc
User root
Command /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4252536399 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_prod.4252536399
Directory /workspace/0.chip_sw_keymgr_key_derivation_prod/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.817793748
Short name T228
Test name
Test status
Simulation time 8770080200 ps
CPU time 1645.34 seconds
Started Aug 02 08:20:01 PM PDT 24
Finished Aug 02 08:47:27 PM PDT 24
Peak memory 611448 kb
Host smart-f3352fa1-e3e2-401e-b793-434bc408ba82
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817793
748 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_aes.817793748
Directory /workspace/0.chip_sw_keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2838386377
Short name T234
Test name
Test status
Simulation time 12846453400 ps
CPU time 3463.04 seconds
Started Aug 02 08:19:45 PM PDT 24
Finished Aug 02 09:17:28 PM PDT 24
Peak memory 610948 kb
Host smart-fb8b64b9-c724-43fa-aa61-2dfd233a5a01
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28383
86377 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.2838386377
Directory /workspace/0.chip_sw_keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1724355444
Short name T965
Test name
Test status
Simulation time 16910508754 ps
CPU time 1413.99 seconds
Started Aug 02 08:17:49 PM PDT 24
Finished Aug 02 08:41:23 PM PDT 24
Peak memory 611544 kb
Host smart-7866f2d6-469f-42ed-831d-35daaaaf347a
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1724355444 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1724355444
Directory /workspace/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3624973593
Short name T690
Test name
Test status
Simulation time 134920551086 ps
CPU time 18066.6 seconds
Started Aug 02 08:32:06 PM PDT 24
Finished Aug 03 01:33:15 AM PDT 24
Peak memory 610452 kb
Host smart-3926e6ca-08c0-4ac9-81ba-8312392fb951
User root
Command /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_
cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3624973593 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency_reduced_freq.3624973593
Directory /workspace/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3547810879
Short name T393
Test name
Test status
Simulation time 24257740298 ps
CPU time 8701.42 seconds
Started Aug 02 08:30:41 PM PDT 24
Finished Aug 02 10:55:43 PM PDT 24
Peak memory 610124 kb
Host smart-dd60b2df-d80f-4253-b50f-42b77be4330f
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3547810879 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3547810879
Directory /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest

Test location /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.1470472564
Short name T402
Test name
Test status
Simulation time 3274703264 ps
CPU time 228.49 seconds
Started Aug 02 08:42:28 PM PDT 24
Finished Aug 02 08:46:17 PM PDT 24
Peak memory 647124 kb
Host smart-e2733cf3-8ae2-487e-8975-398cd05992b3
User root
Command /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470472564 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_lockstep_glitch.1470472564
Directory /workspace/2.chip_sw_rv_core_ibex_lockstep_glitch/latest

Test location /workspace/coverage/cover_reg_top/0.chip_csr_aliasing.3390300472
Short name T706
Test name
Test status
Simulation time 27768568373 ps
CPU time 5592.92 seconds
Started Aug 02 07:51:31 PM PDT 24
Finished Aug 02 09:24:45 PM PDT 24
Peak memory 593772 kb
Host smart-c20b0431-b3e1-4592-9802-bde5d29ce571
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390300472 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 0.chip_csr_aliasing.3390300472
Directory /workspace/0.chip_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.4176299918
Short name T405
Test name
Test status
Simulation time 12040765608 ps
CPU time 1573.13 seconds
Started Aug 02 07:51:31 PM PDT 24
Finished Aug 02 08:17:45 PM PDT 24
Peak memory 592504 kb
Host smart-bd263f1a-225c-4ff6-beb4-e5b499494ac1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176299918 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 0.chip_csr_bit_bash.4176299918
Directory /workspace/0.chip_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.804627162
Short name T2139
Test name
Test status
Simulation time 9541473625 ps
CPU time 833.85 seconds
Started Aug 02 07:51:43 PM PDT 24
Finished Aug 02 08:05:37 PM PDT 24
Peak memory 644788 kb
Host smart-86c8b73b-85ba-4152-86c0-0267839f1885
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804627162 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.chip_csr_mem_rw_with_rand_reset.804627162
Directory /workspace/0.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.chip_csr_rw.3447882184
Short name T442
Test name
Test status
Simulation time 5704266888 ps
CPU time 530.65 seconds
Started Aug 02 07:51:47 PM PDT 24
Finished Aug 02 08:00:37 PM PDT 24
Peak memory 598492 kb
Host smart-b46c3ea9-c47d-46e1-8dc1-7b042384f73a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447882184 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_rw.3447882184
Directory /workspace/0.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.chip_prim_tl_access.965177069
Short name T2594
Test name
Test status
Simulation time 6159016440 ps
CPU time 259.59 seconds
Started Aug 02 07:51:43 PM PDT 24
Finished Aug 02 07:56:02 PM PDT 24
Peak memory 589820 kb
Host smart-d2cbf874-6d27-40c5-ab32-e294dafa4ce8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965177069 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.chip_prim_tl_access.965177069
Directory /workspace/0.chip_prim_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.1180084011
Short name T1937
Test name
Test status
Simulation time 15909544852 ps
CPU time 1748.94 seconds
Started Aug 02 07:51:31 PM PDT 24
Finished Aug 02 08:20:40 PM PDT 24
Peak memory 593356 kb
Host smart-8e1f4965-ecc4-41a5-b9de-81e4b8180af3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180084011 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.chip_same_csr_outstanding.1180084011
Directory /workspace/0.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_access_same_device.2615058378
Short name T1464
Test name
Test status
Simulation time 400394941 ps
CPU time 35.56 seconds
Started Aug 02 07:51:43 PM PDT 24
Finished Aug 02 07:52:19 PM PDT 24
Peak memory 575904 kb
Host smart-4c8251a7-5455-47ea-8fe5-dd8d35a31db9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615058378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.
2615058378
Directory /workspace/0.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.4006055486
Short name T1947
Test name
Test status
Simulation time 89405775468 ps
CPU time 1589.56 seconds
Started Aug 02 07:51:46 PM PDT 24
Finished Aug 02 08:18:16 PM PDT 24
Peak memory 576148 kb
Host smart-bfea08d9-d594-41d8-9653-0e432026e8cb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006055486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_d
evice_slow_rsp.4006055486
Directory /workspace/0.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.405367348
Short name T2846
Test name
Test status
Simulation time 335011913 ps
CPU time 14.58 seconds
Started Aug 02 07:51:50 PM PDT 24
Finished Aug 02 07:52:04 PM PDT 24
Peak memory 575604 kb
Host smart-e4050294-68ba-4109-be15-15b939ceae7b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405367348 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.
405367348
Directory /workspace/0.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_error_random.2818581831
Short name T2852
Test name
Test status
Simulation time 41577033 ps
CPU time 6.15 seconds
Started Aug 02 07:51:48 PM PDT 24
Finished Aug 02 07:51:54 PM PDT 24
Peak memory 573832 kb
Host smart-834d730e-3d3f-4357-9e42-43ebc36d0657
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818581831 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.2818581831
Directory /workspace/0.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_random.3462921636
Short name T2044
Test name
Test status
Simulation time 167702408 ps
CPU time 14.74 seconds
Started Aug 02 07:51:45 PM PDT 24
Finished Aug 02 07:52:00 PM PDT 24
Peak memory 575924 kb
Host smart-7a0360e5-9559-418b-8a3c-dcc3fc1ba0e1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462921636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random.3462921636
Directory /workspace/0.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_random_large_delays.2664766740
Short name T531
Test name
Test status
Simulation time 97920082278 ps
CPU time 931.67 seconds
Started Aug 02 07:51:46 PM PDT 24
Finished Aug 02 08:07:18 PM PDT 24
Peak memory 575996 kb
Host smart-138f8afb-ec30-445b-8336-f3a178d139c5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664766740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.2664766740
Directory /workspace/0.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.3811125433
Short name T2493
Test name
Test status
Simulation time 21124378849 ps
CPU time 357.01 seconds
Started Aug 02 07:51:42 PM PDT 24
Finished Aug 02 07:57:39 PM PDT 24
Peak memory 575816 kb
Host smart-0fe015a8-23de-4ae3-9a5c-e970dbcba5ab
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811125433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.3811125433
Directory /workspace/0.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.2325156331
Short name T1988
Test name
Test status
Simulation time 165572569 ps
CPU time 15.17 seconds
Started Aug 02 07:51:46 PM PDT 24
Finished Aug 02 07:52:02 PM PDT 24
Peak memory 575800 kb
Host smart-b56bf8e3-8b1b-4a00-9118-4cc9da14d22c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325156331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_dela
ys.2325156331
Directory /workspace/0.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_same_source.804274347
Short name T2234
Test name
Test status
Simulation time 872082952 ps
CPU time 27.36 seconds
Started Aug 02 07:51:46 PM PDT 24
Finished Aug 02 07:52:14 PM PDT 24
Peak memory 575872 kb
Host smart-6164d35e-4dd3-4e7c-b534-c5d23468a4f3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804274347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.804274347
Directory /workspace/0.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_smoke.1207192045
Short name T1520
Test name
Test status
Simulation time 38594011 ps
CPU time 5.52 seconds
Started Aug 02 07:51:48 PM PDT 24
Finished Aug 02 07:51:54 PM PDT 24
Peak memory 574428 kb
Host smart-88f0f3c5-66dc-4754-9638-ecef3d80a794
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207192045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.1207192045
Directory /workspace/0.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.1742923726
Short name T1441
Test name
Test status
Simulation time 5944266606 ps
CPU time 58.62 seconds
Started Aug 02 07:51:46 PM PDT 24
Finished Aug 02 07:52:44 PM PDT 24
Peak memory 574648 kb
Host smart-7514a006-6422-4a57-84df-c55baea15657
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742923726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.1742923726
Directory /workspace/0.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.3656950001
Short name T1609
Test name
Test status
Simulation time 4878831085 ps
CPU time 75.56 seconds
Started Aug 02 07:51:45 PM PDT 24
Finished Aug 02 07:53:01 PM PDT 24
Peak memory 573912 kb
Host smart-2aad90e2-b92c-4840-a6d5-2ff02527e56f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656950001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.3656950001
Directory /workspace/0.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.650833371
Short name T1800
Test name
Test status
Simulation time 53021685 ps
CPU time 5.87 seconds
Started Aug 02 07:51:44 PM PDT 24
Finished Aug 02 07:51:50 PM PDT 24
Peak memory 573840 kb
Host smart-39e696bb-9757-47fa-823e-cf8935bea54d
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650833371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.
650833371
Directory /workspace/0.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_stress_all.4207412036
Short name T1862
Test name
Test status
Simulation time 7296427771 ps
CPU time 295.09 seconds
Started Aug 02 07:51:44 PM PDT 24
Finished Aug 02 07:56:39 PM PDT 24
Peak memory 576220 kb
Host smart-76aade31-2b0f-40b0-8211-ec275454bd12
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207412036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.4207412036
Directory /workspace/0.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.3772582177
Short name T1534
Test name
Test status
Simulation time 1690950363 ps
CPU time 144.21 seconds
Started Aug 02 07:51:42 PM PDT 24
Finished Aug 02 07:54:06 PM PDT 24
Peak memory 575900 kb
Host smart-b77eb259-5693-4ae4-9ff2-c794c8973abb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772582177 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.3772582177
Directory /workspace/0.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.1330288650
Short name T2102
Test name
Test status
Simulation time 2308390110 ps
CPU time 221.35 seconds
Started Aug 02 07:51:42 PM PDT 24
Finished Aug 02 07:55:24 PM PDT 24
Peak memory 576476 kb
Host smart-fd0ac581-7096-49f5-893a-b746f95b5b75
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330288650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_
with_rand_reset.1330288650
Directory /workspace/0.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.2808155973
Short name T2849
Test name
Test status
Simulation time 131757006 ps
CPU time 17.35 seconds
Started Aug 02 07:51:46 PM PDT 24
Finished Aug 02 07:52:03 PM PDT 24
Peak memory 575972 kb
Host smart-1069bd4c-c848-4344-8e12-b64a1117881d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808155973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.2808155973
Directory /workspace/0.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.1031724758
Short name T543
Test name
Test status
Simulation time 9149922329 ps
CPU time 862.6 seconds
Started Aug 02 07:51:44 PM PDT 24
Finished Aug 02 08:06:07 PM PDT 24
Peak memory 593224 kb
Host smart-a2897283-59e8-4afb-b0b2-03a7e4c4c902
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031724758 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 1.chip_csr_bit_bash.1031724758
Directory /workspace/1.chip_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.1762009302
Short name T1762
Test name
Test status
Simulation time 10733616437 ps
CPU time 712.2 seconds
Started Aug 02 07:51:53 PM PDT 24
Finished Aug 02 08:03:45 PM PDT 24
Peak memory 647316 kb
Host smart-77706ebb-970c-4888-86e0-03e8669a5528
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762009302 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.chip_csr_mem_rw_with_rand_reset.1762009302
Directory /workspace/1.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.chip_csr_rw.813892530
Short name T2742
Test name
Test status
Simulation time 5571566744 ps
CPU time 643.28 seconds
Started Aug 02 07:51:55 PM PDT 24
Finished Aug 02 08:02:38 PM PDT 24
Peak memory 599232 kb
Host smart-dac9ad83-f919-420c-8e80-b0bb0512155e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813892530 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_rw.813892530
Directory /workspace/1.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.chip_prim_tl_access.324374042
Short name T913
Test name
Test status
Simulation time 5997370408 ps
CPU time 240.36 seconds
Started Aug 02 07:51:44 PM PDT 24
Finished Aug 02 07:55:45 PM PDT 24
Peak memory 589908 kb
Host smart-a7984385-69e0-4bcb-83b0-89fd78067704
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324374042 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.chip_prim_tl_access.324374042
Directory /workspace/1.chip_prim_tl_access/latest

Test location /workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1445438410
Short name T1703
Test name
Test status
Simulation time 13019935350 ps
CPU time 371.62 seconds
Started Aug 02 07:51:44 PM PDT 24
Finished Aug 02 07:57:55 PM PDT 24
Peak memory 590268 kb
Host smart-8fe93852-263c-4136-8ac4-7f34675ac931
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445438410 -assert nopostproc +UVM_TESTNAME=chip_base_t
est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.chip_rv_dm_lc_disabled.1445438410
Directory /workspace/1.chip_rv_dm_lc_disabled/latest

Test location /workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.3987969466
Short name T395
Test name
Test status
Simulation time 16276492685 ps
CPU time 1784.45 seconds
Started Aug 02 07:51:45 PM PDT 24
Finished Aug 02 08:21:30 PM PDT 24
Peak memory 592908 kb
Host smart-a3ad19af-da88-4a72-870c-2f280fff4b39
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987969466 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.chip_same_csr_outstanding.3987969466
Directory /workspace/1.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.chip_tl_errors.1624219871
Short name T2434
Test name
Test status
Simulation time 3003347820 ps
CPU time 78.37 seconds
Started Aug 02 07:51:46 PM PDT 24
Finished Aug 02 07:53:05 PM PDT 24
Peak memory 599992 kb
Host smart-627c9cb1-cc38-42f3-975e-02e257a59a3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624219871 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_tl_errors.1624219871
Directory /workspace/1.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_access_same_device.751995905
Short name T567
Test name
Test status
Simulation time 591602833 ps
CPU time 24.4 seconds
Started Aug 02 07:51:44 PM PDT 24
Finished Aug 02 07:52:09 PM PDT 24
Peak memory 576060 kb
Host smart-e0101917-ef54-4e31-9b90-f7c56c85917b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751995905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.751995905
Directory /workspace/1.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.3196897086
Short name T2457
Test name
Test status
Simulation time 124912525880 ps
CPU time 1980.61 seconds
Started Aug 02 07:51:43 PM PDT 24
Finished Aug 02 08:24:44 PM PDT 24
Peak memory 576056 kb
Host smart-cb0f6d3f-709e-4f5a-8e40-46fbe85957d7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196897086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_d
evice_slow_rsp.3196897086
Directory /workspace/1.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.3656073195
Short name T1775
Test name
Test status
Simulation time 60011551 ps
CPU time 5.88 seconds
Started Aug 02 07:51:47 PM PDT 24
Finished Aug 02 07:51:53 PM PDT 24
Peak memory 574364 kb
Host smart-cd1d5108-03a3-4733-8de4-972d09b1678f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656073195 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr
.3656073195
Directory /workspace/1.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_error_random.23719293
Short name T1749
Test name
Test status
Simulation time 239591470 ps
CPU time 18.54 seconds
Started Aug 02 07:51:41 PM PDT 24
Finished Aug 02 07:52:00 PM PDT 24
Peak memory 575908 kb
Host smart-887cd6f2-2d3d-4188-a28f-52cfbf72334c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23719293 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.23719293
Directory /workspace/1.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_random.128219342
Short name T607
Test name
Test status
Simulation time 201513423 ps
CPU time 16.55 seconds
Started Aug 02 07:51:45 PM PDT 24
Finished Aug 02 07:52:02 PM PDT 24
Peak memory 575772 kb
Host smart-a5d15387-6848-4f7a-b870-5475e723aabf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128219342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random.128219342
Directory /workspace/1.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2472339224
Short name T1965
Test name
Test status
Simulation time 52044658234 ps
CPU time 568.6 seconds
Started Aug 02 07:51:50 PM PDT 24
Finished Aug 02 08:01:18 PM PDT 24
Peak memory 575832 kb
Host smart-84ea35fc-952d-4e88-b6ad-32c2024b4656
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472339224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.2472339224
Directory /workspace/1.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.1283313313
Short name T1468
Test name
Test status
Simulation time 3525337097 ps
CPU time 58.17 seconds
Started Aug 02 07:51:46 PM PDT 24
Finished Aug 02 07:52:45 PM PDT 24
Peak memory 574628 kb
Host smart-ea2ebfff-2716-4c3a-9bc0-1ec5d7330e2a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283313313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.1283313313
Directory /workspace/1.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.2536812195
Short name T1656
Test name
Test status
Simulation time 148578148 ps
CPU time 16.47 seconds
Started Aug 02 07:51:48 PM PDT 24
Finished Aug 02 07:52:04 PM PDT 24
Peak memory 575820 kb
Host smart-41dc01b5-2ab8-4a8c-88d4-ae71173cb4be
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536812195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_dela
ys.2536812195
Directory /workspace/1.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_same_source.2553518552
Short name T2758
Test name
Test status
Simulation time 227508559 ps
CPU time 17.62 seconds
Started Aug 02 07:51:43 PM PDT 24
Finished Aug 02 07:52:01 PM PDT 24
Peak memory 575912 kb
Host smart-6555180f-eaa6-4867-af9d-91b275578c77
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553518552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.2553518552
Directory /workspace/1.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_smoke.440297728
Short name T1951
Test name
Test status
Simulation time 186574830 ps
CPU time 8.38 seconds
Started Aug 02 07:51:44 PM PDT 24
Finished Aug 02 07:51:52 PM PDT 24
Peak memory 573808 kb
Host smart-3a23a928-c076-4450-abce-7c76ffb6b8bd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440297728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.440297728
Directory /workspace/1.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.1774278742
Short name T1533
Test name
Test status
Simulation time 10475943431 ps
CPU time 104.7 seconds
Started Aug 02 07:51:44 PM PDT 24
Finished Aug 02 07:53:29 PM PDT 24
Peak memory 573920 kb
Host smart-8f439628-ccfb-462c-92cc-27c5d135e864
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774278742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.1774278742
Directory /workspace/1.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.2187279479
Short name T2238
Test name
Test status
Simulation time 4006702612 ps
CPU time 70.78 seconds
Started Aug 02 07:51:48 PM PDT 24
Finished Aug 02 07:52:59 PM PDT 24
Peak memory 574560 kb
Host smart-2ea4c890-c2c5-4f3d-b999-168d338ecde3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187279479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.2187279479
Directory /workspace/1.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.2482162671
Short name T1776
Test name
Test status
Simulation time 46815196 ps
CPU time 5.98 seconds
Started Aug 02 07:51:44 PM PDT 24
Finished Aug 02 07:51:51 PM PDT 24
Peak memory 573812 kb
Host smart-7861dcbd-42b1-40a2-8034-fde4553cd981
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482162671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays
.2482162671
Directory /workspace/1.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_stress_all.1571093652
Short name T2068
Test name
Test status
Simulation time 3167020909 ps
CPU time 270.31 seconds
Started Aug 02 07:51:54 PM PDT 24
Finished Aug 02 07:56:24 PM PDT 24
Peak memory 576020 kb
Host smart-d3b82f8f-2488-4c8b-9fea-9861b6c442c8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571093652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.1571093652
Directory /workspace/1.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.341740263
Short name T2417
Test name
Test status
Simulation time 12472705517 ps
CPU time 420.2 seconds
Started Aug 02 07:51:55 PM PDT 24
Finished Aug 02 07:58:56 PM PDT 24
Peak memory 576180 kb
Host smart-62eac882-a8cf-4d83-bc43-7c0cd9ed1677
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341740263 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.341740263
Directory /workspace/1.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.1594954737
Short name T2572
Test name
Test status
Simulation time 11407161860 ps
CPU time 673.05 seconds
Started Aug 02 07:51:57 PM PDT 24
Finished Aug 02 08:03:11 PM PDT 24
Peak memory 576824 kb
Host smart-76d0bbd4-6c56-4023-b198-9504431fa203
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594954737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_
with_rand_reset.1594954737
Directory /workspace/1.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.1376559211
Short name T1765
Test name
Test status
Simulation time 168996195 ps
CPU time 18.54 seconds
Started Aug 02 07:51:49 PM PDT 24
Finished Aug 02 07:52:08 PM PDT 24
Peak memory 575972 kb
Host smart-86aa769f-0642-415a-94f5-b89e8d7d7b1d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376559211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.1376559211
Directory /workspace/1.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.4201256888
Short name T2912
Test name
Test status
Simulation time 7144664684 ps
CPU time 382.9 seconds
Started Aug 02 07:54:05 PM PDT 24
Finished Aug 02 08:00:28 PM PDT 24
Peak memory 640840 kb
Host smart-4a6308eb-6dcd-4f18-9462-c016bdff1ccd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201256888 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.chip_csr_mem_rw_with_rand_reset.4201256888
Directory /workspace/10.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.chip_csr_rw.1038399309
Short name T2259
Test name
Test status
Simulation time 3741821442 ps
CPU time 305.29 seconds
Started Aug 02 07:54:10 PM PDT 24
Finished Aug 02 07:59:15 PM PDT 24
Peak memory 597836 kb
Host smart-c4767ec7-74a9-425c-8b30-51936a499d82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038399309 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_rw.1038399309
Directory /workspace/10.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.1182440837
Short name T140
Test name
Test status
Simulation time 15082799822 ps
CPU time 1690.99 seconds
Started Aug 02 07:53:55 PM PDT 24
Finished Aug 02 08:22:07 PM PDT 24
Peak memory 593296 kb
Host smart-ebe44108-19d1-4f29-90b5-a885457ff1e5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182440837 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.chip_same_csr_outstanding.1182440837
Directory /workspace/10.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.chip_tl_errors.3619109305
Short name T693
Test name
Test status
Simulation time 2584552443 ps
CPU time 77.94 seconds
Started Aug 02 07:53:48 PM PDT 24
Finished Aug 02 07:55:06 PM PDT 24
Peak memory 598664 kb
Host smart-f459a231-050b-4be8-be2b-0583ec4cb1f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619109305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_tl_errors.3619109305
Directory /workspace/10.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_access_same_device.2816080794
Short name T1579
Test name
Test status
Simulation time 947691840 ps
CPU time 44.58 seconds
Started Aug 02 07:53:54 PM PDT 24
Finished Aug 02 07:54:39 PM PDT 24
Peak memory 575796 kb
Host smart-ec0e5acd-efda-461f-a7f6-8b01259ad9ed
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816080794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device
.2816080794
Directory /workspace/10.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.2370207508
Short name T1835
Test name
Test status
Simulation time 108879588852 ps
CPU time 1773.71 seconds
Started Aug 02 07:53:50 PM PDT 24
Finished Aug 02 08:23:24 PM PDT 24
Peak memory 576104 kb
Host smart-195a2e61-5941-409a-a94b-f772b991d6a4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370207508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_
device_slow_rsp.2370207508
Directory /workspace/10.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.3337937504
Short name T2347
Test name
Test status
Simulation time 726385748 ps
CPU time 31.78 seconds
Started Aug 02 07:54:08 PM PDT 24
Finished Aug 02 07:54:40 PM PDT 24
Peak memory 576024 kb
Host smart-3a68bf85-724d-4b8b-b45c-e55dd2a78bad
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337937504 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_add
r.3337937504
Directory /workspace/10.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_error_random.4209638384
Short name T2736
Test name
Test status
Simulation time 2438068301 ps
CPU time 81.95 seconds
Started Aug 02 07:54:10 PM PDT 24
Finished Aug 02 07:55:33 PM PDT 24
Peak memory 575984 kb
Host smart-30b5a3f2-0503-434c-964d-656a933d919a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209638384 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.4209638384
Directory /workspace/10.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_random.1573254387
Short name T2378
Test name
Test status
Simulation time 399850687 ps
CPU time 34.2 seconds
Started Aug 02 07:53:55 PM PDT 24
Finished Aug 02 07:54:29 PM PDT 24
Peak memory 575944 kb
Host smart-ec1951b4-5848-42ba-9761-7c2619b9b60b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573254387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random.1573254387
Directory /workspace/10.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_random_large_delays.3623712832
Short name T2831
Test name
Test status
Simulation time 11472591867 ps
CPU time 123.81 seconds
Started Aug 02 07:53:50 PM PDT 24
Finished Aug 02 07:55:54 PM PDT 24
Peak memory 575872 kb
Host smart-67dedcce-5d12-4359-b35e-b9edbe38914d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623712832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.3623712832
Directory /workspace/10.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.495392024
Short name T1588
Test name
Test status
Simulation time 42366523552 ps
CPU time 699.29 seconds
Started Aug 02 07:53:52 PM PDT 24
Finished Aug 02 08:05:31 PM PDT 24
Peak memory 575904 kb
Host smart-0d6a2a5a-dc4b-4b5d-96bd-eb3946dc491c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495392024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.495392024
Directory /workspace/10.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.1030857195
Short name T1894
Test name
Test status
Simulation time 612432807 ps
CPU time 50.53 seconds
Started Aug 02 07:53:54 PM PDT 24
Finished Aug 02 07:54:45 PM PDT 24
Peak memory 575920 kb
Host smart-f09e0fe7-752f-462d-9406-f83032f2b529
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030857195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_del
ays.1030857195
Directory /workspace/10.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_same_source.1270128730
Short name T1753
Test name
Test status
Simulation time 1911299831 ps
CPU time 52.84 seconds
Started Aug 02 07:53:52 PM PDT 24
Finished Aug 02 07:54:45 PM PDT 24
Peak memory 575944 kb
Host smart-3507a31c-a1de-45c4-b285-eae9a600584a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270128730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.1270128730
Directory /workspace/10.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_smoke.3628241251
Short name T573
Test name
Test status
Simulation time 191034669 ps
CPU time 9.21 seconds
Started Aug 02 07:53:50 PM PDT 24
Finished Aug 02 07:53:59 PM PDT 24
Peak memory 574480 kb
Host smart-43d04287-48f2-4fe5-acbc-403a37775231
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628241251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.3628241251
Directory /workspace/10.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.1610489673
Short name T2791
Test name
Test status
Simulation time 7640875192 ps
CPU time 81.06 seconds
Started Aug 02 07:53:53 PM PDT 24
Finished Aug 02 07:55:14 PM PDT 24
Peak memory 573984 kb
Host smart-be1a5049-12f0-47b7-b726-a1ae9fb2c0ba
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610489673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.1610489673
Directory /workspace/10.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2692321129
Short name T554
Test name
Test status
Simulation time 3024853132 ps
CPU time 47.23 seconds
Started Aug 02 07:53:53 PM PDT 24
Finished Aug 02 07:54:40 PM PDT 24
Peak memory 573876 kb
Host smart-c9f03a85-da3e-49fc-8613-37bdeda38502
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692321129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.2692321129
Directory /workspace/10.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.318082996
Short name T1741
Test name
Test status
Simulation time 49636219 ps
CPU time 5.94 seconds
Started Aug 02 07:53:55 PM PDT 24
Finished Aug 02 07:54:01 PM PDT 24
Peak memory 573824 kb
Host smart-4234b4fe-d796-496e-91b7-9bcbc3679659
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318082996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays
.318082996
Directory /workspace/10.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_stress_all.2246618944
Short name T524
Test name
Test status
Simulation time 4968372528 ps
CPU time 186.25 seconds
Started Aug 02 07:54:04 PM PDT 24
Finished Aug 02 07:57:10 PM PDT 24
Peak memory 576224 kb
Host smart-d0e959e4-5d8b-441e-a435-6e39a99bbde5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246618944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.2246618944
Directory /workspace/10.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.609341095
Short name T1759
Test name
Test status
Simulation time 10876336879 ps
CPU time 353.21 seconds
Started Aug 02 07:54:02 PM PDT 24
Finished Aug 02 07:59:55 PM PDT 24
Peak memory 576152 kb
Host smart-5ee9c9bb-824f-426d-9746-c6e785149e8d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609341095 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.609341095
Directory /workspace/10.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.4200124825
Short name T2851
Test name
Test status
Simulation time 9748227383 ps
CPU time 526.08 seconds
Started Aug 02 07:54:04 PM PDT 24
Finished Aug 02 08:02:50 PM PDT 24
Peak memory 576020 kb
Host smart-85b6bb0a-c4c7-463b-89fa-d7a11d5ae102
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200124825 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_al
l_with_reset_error.4200124825
Directory /workspace/10.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.294971649
Short name T2109
Test name
Test status
Simulation time 389026233 ps
CPU time 17.41 seconds
Started Aug 02 07:54:03 PM PDT 24
Finished Aug 02 07:54:21 PM PDT 24
Peak memory 575964 kb
Host smart-c802e330-8a20-4b50-9044-94d19dc32095
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294971649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.294971649
Directory /workspace/10.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/11.chip_csr_rw.1490077140
Short name T2247
Test name
Test status
Simulation time 5786946616 ps
CPU time 644.61 seconds
Started Aug 02 07:54:09 PM PDT 24
Finished Aug 02 08:04:54 PM PDT 24
Peak memory 598872 kb
Host smart-aa9aee14-f0e0-41b6-9cdc-7792743b6355
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490077140 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_rw.1490077140
Directory /workspace/11.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.81391643
Short name T443
Test name
Test status
Simulation time 28272784282 ps
CPU time 3497.38 seconds
Started Aug 02 07:54:02 PM PDT 24
Finished Aug 02 08:52:20 PM PDT 24
Peak memory 593016 kb
Host smart-86a592c8-1a7b-45a3-8298-929a69a8f2de
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81391643 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.chip_same_csr_outstanding.81391643
Directory /workspace/11.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_access_same_device.2145467360
Short name T2592
Test name
Test status
Simulation time 609333833 ps
CPU time 43.03 seconds
Started Aug 02 07:54:01 PM PDT 24
Finished Aug 02 07:54:44 PM PDT 24
Peak memory 575804 kb
Host smart-1a793031-a7f7-4544-9641-01bce4482f39
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145467360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device
.2145467360
Directory /workspace/11.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.18350911
Short name T2308
Test name
Test status
Simulation time 67228593701 ps
CPU time 1204.12 seconds
Started Aug 02 07:54:08 PM PDT 24
Finished Aug 02 08:14:12 PM PDT 24
Peak memory 576068 kb
Host smart-42f0bb0a-bba8-413f-aa81-a84a95f8328c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18350911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_de
vice_slow_rsp.18350911
Directory /workspace/11.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.2232273680
Short name T734
Test name
Test status
Simulation time 155159940 ps
CPU time 17.69 seconds
Started Aug 02 07:54:02 PM PDT 24
Finished Aug 02 07:54:19 PM PDT 24
Peak memory 576000 kb
Host smart-51c4982a-314a-4f9e-8cac-319042ce1dd3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232273680 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_add
r.2232273680
Directory /workspace/11.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_error_random.513698031
Short name T1685
Test name
Test status
Simulation time 2150776248 ps
CPU time 69.68 seconds
Started Aug 02 07:54:08 PM PDT 24
Finished Aug 02 07:55:18 PM PDT 24
Peak memory 575808 kb
Host smart-db43e673-63be-4451-8eb1-04c6d8525755
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513698031 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.513698031
Directory /workspace/11.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_random.3854354628
Short name T1702
Test name
Test status
Simulation time 1794929013 ps
CPU time 60.96 seconds
Started Aug 02 07:54:09 PM PDT 24
Finished Aug 02 07:55:10 PM PDT 24
Peak memory 575792 kb
Host smart-5651e6d4-a97b-445b-85dc-3f526527b61b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854354628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random.3854354628
Directory /workspace/11.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_random_large_delays.4291860372
Short name T1516
Test name
Test status
Simulation time 29578840686 ps
CPU time 326.53 seconds
Started Aug 02 07:54:03 PM PDT 24
Finished Aug 02 07:59:29 PM PDT 24
Peak memory 575968 kb
Host smart-2cc0818f-0af5-45de-8136-8053f1ca9c09
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291860372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.4291860372
Directory /workspace/11.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.4115325912
Short name T1695
Test name
Test status
Simulation time 59883336781 ps
CPU time 987.32 seconds
Started Aug 02 07:54:02 PM PDT 24
Finished Aug 02 08:10:30 PM PDT 24
Peak memory 576028 kb
Host smart-89583459-661f-4718-8512-54036f51c8fc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115325912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.4115325912
Directory /workspace/11.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.3835470282
Short name T2598
Test name
Test status
Simulation time 197336360 ps
CPU time 18.75 seconds
Started Aug 02 07:54:10 PM PDT 24
Finished Aug 02 07:54:29 PM PDT 24
Peak memory 575808 kb
Host smart-0f32805a-e5bb-4566-90de-d3c826dfeff4
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835470282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_del
ays.3835470282
Directory /workspace/11.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_same_source.63967501
Short name T538
Test name
Test status
Simulation time 513399384 ps
CPU time 33.83 seconds
Started Aug 02 07:54:03 PM PDT 24
Finished Aug 02 07:54:37 PM PDT 24
Peak memory 575864 kb
Host smart-b0b35a32-6a52-482a-a5b6-d4f8c4c3b1b5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63967501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.63967501
Directory /workspace/11.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_smoke.1260086480
Short name T1593
Test name
Test status
Simulation time 48086728 ps
CPU time 5.96 seconds
Started Aug 02 07:54:00 PM PDT 24
Finished Aug 02 07:54:06 PM PDT 24
Peak memory 574468 kb
Host smart-1dff212d-783b-4876-bd1c-31ba934b6366
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260086480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.1260086480
Directory /workspace/11.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.288161178
Short name T2290
Test name
Test status
Simulation time 10270389229 ps
CPU time 108.54 seconds
Started Aug 02 07:54:04 PM PDT 24
Finished Aug 02 07:55:52 PM PDT 24
Peak memory 573876 kb
Host smart-e9834df3-0617-4fbe-8f72-54e3f0af862b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288161178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.288161178
Directory /workspace/11.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.1662552639
Short name T2415
Test name
Test status
Simulation time 5250088954 ps
CPU time 85.22 seconds
Started Aug 02 07:54:08 PM PDT 24
Finished Aug 02 07:55:34 PM PDT 24
Peak memory 574016 kb
Host smart-7bba36e1-ab60-4e36-954b-bd514384f416
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662552639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.1662552639
Directory /workspace/11.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.3144749165
Short name T1508
Test name
Test status
Simulation time 48275262 ps
CPU time 6.6 seconds
Started Aug 02 07:54:06 PM PDT 24
Finished Aug 02 07:54:12 PM PDT 24
Peak memory 573848 kb
Host smart-9769f775-b8cb-4ea4-b662-bb3755fe98b4
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144749165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delay
s.3144749165
Directory /workspace/11.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_stress_all.2013409842
Short name T2672
Test name
Test status
Simulation time 3883149814 ps
CPU time 283.16 seconds
Started Aug 02 07:54:02 PM PDT 24
Finished Aug 02 07:58:45 PM PDT 24
Peak memory 576120 kb
Host smart-4bbb31b9-bb67-45e7-9fd7-648c9f1448ec
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013409842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.2013409842
Directory /workspace/11.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.3252626143
Short name T2734
Test name
Test status
Simulation time 4284754025 ps
CPU time 333.39 seconds
Started Aug 02 07:54:03 PM PDT 24
Finished Aug 02 07:59:36 PM PDT 24
Peak memory 576852 kb
Host smart-969f467a-30dc-4e39-9423-025fdca59d2b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252626143 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_al
l_with_reset_error.3252626143
Directory /workspace/11.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.2349749310
Short name T2030
Test name
Test status
Simulation time 287553706 ps
CPU time 33.82 seconds
Started Aug 02 07:54:08 PM PDT 24
Finished Aug 02 07:54:42 PM PDT 24
Peak memory 576052 kb
Host smart-10164b77-507e-4471-ab03-6c1411b95681
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349749310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.2349749310
Directory /workspace/11.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.200669345
Short name T1953
Test name
Test status
Simulation time 6169336199 ps
CPU time 517.98 seconds
Started Aug 02 07:54:16 PM PDT 24
Finished Aug 02 08:02:54 PM PDT 24
Peak memory 637488 kb
Host smart-b4e21b47-b13e-4733-8828-ad9a248799e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200669345 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.chip_csr_mem_rw_with_rand_reset.200669345
Directory /workspace/12.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.chip_csr_rw.655020284
Short name T1883
Test name
Test status
Simulation time 5014644391 ps
CPU time 348.19 seconds
Started Aug 02 07:54:16 PM PDT 24
Finished Aug 02 08:00:04 PM PDT 24
Peak memory 597784 kb
Host smart-c483d5e0-bdb5-4535-bd3c-9201243a6fc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655020284 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_rw.655020284
Directory /workspace/12.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.2873640267
Short name T1976
Test name
Test status
Simulation time 17397526043 ps
CPU time 1871.89 seconds
Started Aug 02 07:54:04 PM PDT 24
Finished Aug 02 08:25:16 PM PDT 24
Peak memory 593396 kb
Host smart-3571639c-804e-403e-b71c-e68e9ad21bc8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873640267 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.chip_same_csr_outstanding.2873640267
Directory /workspace/12.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_access_same_device.567259941
Short name T2059
Test name
Test status
Simulation time 2257962608 ps
CPU time 97.14 seconds
Started Aug 02 07:54:16 PM PDT 24
Finished Aug 02 07:55:54 PM PDT 24
Peak memory 575880 kb
Host smart-27921466-1e6f-49dc-b2a6-0e8b7aa410ab
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567259941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.
567259941
Directory /workspace/12.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.2001602396
Short name T697
Test name
Test status
Simulation time 808099412 ps
CPU time 32.04 seconds
Started Aug 02 07:54:22 PM PDT 24
Finished Aug 02 07:54:54 PM PDT 24
Peak memory 575836 kb
Host smart-27140d49-5b8a-4a17-8e6a-0911f4802b76
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001602396 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_add
r.2001602396
Directory /workspace/12.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_error_random.2639570431
Short name T1590
Test name
Test status
Simulation time 203217767 ps
CPU time 9.95 seconds
Started Aug 02 07:54:20 PM PDT 24
Finished Aug 02 07:54:30 PM PDT 24
Peak memory 573748 kb
Host smart-4208dd29-9da0-4ac0-931b-71c37f8c3e15
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639570431 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.2639570431
Directory /workspace/12.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_random.1082435171
Short name T2492
Test name
Test status
Simulation time 2179276455 ps
CPU time 79.31 seconds
Started Aug 02 07:54:08 PM PDT 24
Finished Aug 02 07:55:27 PM PDT 24
Peak memory 575988 kb
Host smart-e139eedb-2e38-4a0f-ab25-71a297e36eab
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082435171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random.1082435171
Directory /workspace/12.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_random_large_delays.1922528533
Short name T1787
Test name
Test status
Simulation time 88388201707 ps
CPU time 933.7 seconds
Started Aug 02 07:54:03 PM PDT 24
Finished Aug 02 08:09:37 PM PDT 24
Peak memory 576796 kb
Host smart-bde08ae4-2145-4c44-be83-77ac9c96d707
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922528533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.1922528533
Directory /workspace/12.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.2391210403
Short name T2843
Test name
Test status
Simulation time 3548738436 ps
CPU time 52.67 seconds
Started Aug 02 07:54:15 PM PDT 24
Finished Aug 02 07:55:08 PM PDT 24
Peak memory 574560 kb
Host smart-b1189583-9672-4405-888e-47a22d67a40b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391210403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.2391210403
Directory /workspace/12.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.1864275082
Short name T2716
Test name
Test status
Simulation time 571357205 ps
CPU time 47.23 seconds
Started Aug 02 07:54:04 PM PDT 24
Finished Aug 02 07:54:52 PM PDT 24
Peak memory 575712 kb
Host smart-049cccec-1b33-4d9f-9d81-9778e2639b24
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864275082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_del
ays.1864275082
Directory /workspace/12.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_same_source.2927661345
Short name T2175
Test name
Test status
Simulation time 404072969 ps
CPU time 27.55 seconds
Started Aug 02 07:54:22 PM PDT 24
Finished Aug 02 07:54:49 PM PDT 24
Peak memory 575980 kb
Host smart-424272f4-5f8d-4677-95d7-a96dd31f6780
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927661345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.2927661345
Directory /workspace/12.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_smoke.2238165416
Short name T1469
Test name
Test status
Simulation time 43915545 ps
CPU time 5.99 seconds
Started Aug 02 07:54:10 PM PDT 24
Finished Aug 02 07:54:16 PM PDT 24
Peak memory 573748 kb
Host smart-ee081b46-d052-48ca-ad20-668dcd2395dd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238165416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.2238165416
Directory /workspace/12.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.2245691105
Short name T1459
Test name
Test status
Simulation time 6661352539 ps
CPU time 111.63 seconds
Started Aug 02 07:54:03 PM PDT 24
Finished Aug 02 07:55:54 PM PDT 24
Peak memory 573940 kb
Host smart-49d67065-bdb0-456a-b2ba-0767b059ba48
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245691105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.2245691105
Directory /workspace/12.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.469511607
Short name T1900
Test name
Test status
Simulation time 40560821 ps
CPU time 6.19 seconds
Started Aug 02 07:54:04 PM PDT 24
Finished Aug 02 07:54:10 PM PDT 24
Peak memory 573744 kb
Host smart-ede9db14-2e04-414f-ac85-b48e7e54658f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469511607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays
.469511607
Directory /workspace/12.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_stress_all.2867122471
Short name T2494
Test name
Test status
Simulation time 3305473884 ps
CPU time 116.18 seconds
Started Aug 02 07:54:14 PM PDT 24
Finished Aug 02 07:56:10 PM PDT 24
Peak memory 575940 kb
Host smart-6d381854-8749-413a-8972-a3927ac80ea1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867122471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.2867122471
Directory /workspace/12.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.1975262538
Short name T2217
Test name
Test status
Simulation time 10734546121 ps
CPU time 362.57 seconds
Started Aug 02 07:54:16 PM PDT 24
Finished Aug 02 08:00:18 PM PDT 24
Peak memory 576160 kb
Host smart-f1fa6566-7ff4-4ea3-aaf7-18a2317b2cfd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975262538 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.1975262538
Directory /workspace/12.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.678162736
Short name T905
Test name
Test status
Simulation time 107730802 ps
CPU time 41.09 seconds
Started Aug 02 07:54:15 PM PDT 24
Finished Aug 02 07:54:56 PM PDT 24
Peak memory 575968 kb
Host smart-56346a2a-a582-4a14-96cc-e05c6575a05f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678162736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_
with_rand_reset.678162736
Directory /workspace/12.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.98894946
Short name T2420
Test name
Test status
Simulation time 1363644220 ps
CPU time 264.22 seconds
Started Aug 02 07:54:16 PM PDT 24
Finished Aug 02 07:58:40 PM PDT 24
Peak memory 576756 kb
Host smart-ddaf1a02-41a1-4808-adb2-952fc1396a1a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98894946 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_
with_reset_error.98894946
Directory /workspace/12.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.27715700
Short name T2388
Test name
Test status
Simulation time 26865940 ps
CPU time 5.96 seconds
Started Aug 02 07:54:23 PM PDT 24
Finished Aug 02 07:54:29 PM PDT 24
Peak memory 574544 kb
Host smart-31921b27-e281-477d-910e-4d70f1ba6fac
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27715700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.27715700
Directory /workspace/12.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.1350027911
Short name T440
Test name
Test status
Simulation time 7952135470 ps
CPU time 447.26 seconds
Started Aug 02 07:54:17 PM PDT 24
Finished Aug 02 08:01:44 PM PDT 24
Peak memory 649520 kb
Host smart-3b34f8f9-3636-494d-8270-6bf37582b0d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350027911 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.chip_csr_mem_rw_with_rand_reset.1350027911
Directory /workspace/13.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.chip_csr_rw.985638716
Short name T1981
Test name
Test status
Simulation time 3957778993 ps
CPU time 270.24 seconds
Started Aug 02 07:54:24 PM PDT 24
Finished Aug 02 07:58:54 PM PDT 24
Peak memory 598988 kb
Host smart-88c5deda-7c7a-472d-b12a-c9094b75827a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985638716 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_rw.985638716
Directory /workspace/13.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.chip_tl_errors.1260979563
Short name T2728
Test name
Test status
Simulation time 3233116871 ps
CPU time 169.27 seconds
Started Aug 02 07:54:22 PM PDT 24
Finished Aug 02 07:57:11 PM PDT 24
Peak memory 603768 kb
Host smart-91f2bed8-9db3-40e5-96af-0253377ce2f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260979563 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_tl_errors.1260979563
Directory /workspace/13.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_access_same_device.3507205061
Short name T862
Test name
Test status
Simulation time 898286560 ps
CPU time 35.36 seconds
Started Aug 02 07:54:15 PM PDT 24
Finished Aug 02 07:54:51 PM PDT 24
Peak memory 575956 kb
Host smart-68ba8359-654b-4198-9140-9a33b76e82f4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507205061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device
.3507205061
Directory /workspace/13.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.3035160194
Short name T2168
Test name
Test status
Simulation time 157068599700 ps
CPU time 2855.96 seconds
Started Aug 02 07:54:16 PM PDT 24
Finished Aug 02 08:41:52 PM PDT 24
Peak memory 576792 kb
Host smart-4bc3f62b-0d2e-46c5-8d42-48b50e39004c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035160194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_
device_slow_rsp.3035160194
Directory /workspace/13.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.2344631145
Short name T1425
Test name
Test status
Simulation time 105730279 ps
CPU time 12.68 seconds
Started Aug 02 07:54:16 PM PDT 24
Finished Aug 02 07:54:29 PM PDT 24
Peak memory 575968 kb
Host smart-3b7f8946-e6f2-4150-899e-57367a192628
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344631145 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_add
r.2344631145
Directory /workspace/13.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_error_random.3427382199
Short name T2891
Test name
Test status
Simulation time 1990453523 ps
CPU time 66.84 seconds
Started Aug 02 07:54:15 PM PDT 24
Finished Aug 02 07:55:22 PM PDT 24
Peak memory 575904 kb
Host smart-47bf8f87-51ef-445e-b2e1-a6c9f773df7c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427382199 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.3427382199
Directory /workspace/13.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_random.3215087643
Short name T1476
Test name
Test status
Simulation time 227192331 ps
CPU time 11.28 seconds
Started Aug 02 07:54:15 PM PDT 24
Finished Aug 02 07:54:27 PM PDT 24
Peak memory 575856 kb
Host smart-48959fd8-a90c-4319-80dc-8bd8b4ea4339
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215087643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random.3215087643
Directory /workspace/13.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_random_large_delays.3746410229
Short name T1543
Test name
Test status
Simulation time 31129919448 ps
CPU time 332.52 seconds
Started Aug 02 07:54:15 PM PDT 24
Finished Aug 02 07:59:48 PM PDT 24
Peak memory 576808 kb
Host smart-33c327be-8e43-4366-863c-b321128b80a3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746410229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.3746410229
Directory /workspace/13.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.214625527
Short name T2474
Test name
Test status
Simulation time 65250346952 ps
CPU time 1137.49 seconds
Started Aug 02 07:54:18 PM PDT 24
Finished Aug 02 08:13:15 PM PDT 24
Peak memory 575992 kb
Host smart-23aa4280-ae2f-4768-b580-431fb3815104
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214625527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.214625527
Directory /workspace/13.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.242011207
Short name T1556
Test name
Test status
Simulation time 216195475 ps
CPU time 19.34 seconds
Started Aug 02 07:54:23 PM PDT 24
Finished Aug 02 07:54:43 PM PDT 24
Peak memory 575864 kb
Host smart-bf01ab27-ea3e-41b0-905e-acad07c79753
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242011207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_dela
ys.242011207
Directory /workspace/13.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_same_source.77197888
Short name T491
Test name
Test status
Simulation time 975858838 ps
CPU time 30.09 seconds
Started Aug 02 07:54:14 PM PDT 24
Finished Aug 02 07:54:44 PM PDT 24
Peak memory 575756 kb
Host smart-9dd2d1a0-feb8-4720-8723-8f31bd64b2ae
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77197888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.77197888
Directory /workspace/13.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_smoke.281534710
Short name T2050
Test name
Test status
Simulation time 51600961 ps
CPU time 6.93 seconds
Started Aug 02 07:54:20 PM PDT 24
Finished Aug 02 07:54:27 PM PDT 24
Peak memory 574436 kb
Host smart-6eda4828-7b2f-4be2-adb1-5a6483d0e890
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281534710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.281534710
Directory /workspace/13.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.502459247
Short name T1797
Test name
Test status
Simulation time 8834402280 ps
CPU time 92.51 seconds
Started Aug 02 07:54:17 PM PDT 24
Finished Aug 02 07:55:49 PM PDT 24
Peak memory 573864 kb
Host smart-15796a50-e5ba-4343-b13c-cc3f50d621b9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502459247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.502459247
Directory /workspace/13.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.1658672797
Short name T2500
Test name
Test status
Simulation time 4967095739 ps
CPU time 85.45 seconds
Started Aug 02 07:54:21 PM PDT 24
Finished Aug 02 07:55:47 PM PDT 24
Peak memory 573976 kb
Host smart-7e71f67e-fd90-4b19-b0ff-58cc5ead5c8d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658672797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.1658672797
Directory /workspace/13.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.3191988848
Short name T1985
Test name
Test status
Simulation time 50799801 ps
CPU time 5.84 seconds
Started Aug 02 07:54:16 PM PDT 24
Finished Aug 02 07:54:22 PM PDT 24
Peak memory 574508 kb
Host smart-13be6067-019f-477d-b175-6448e4a9ea62
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191988848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delay
s.3191988848
Directory /workspace/13.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_stress_all.1463845927
Short name T627
Test name
Test status
Simulation time 4274413431 ps
CPU time 147.3 seconds
Started Aug 02 07:54:18 PM PDT 24
Finished Aug 02 07:56:45 PM PDT 24
Peak memory 575956 kb
Host smart-e8dda22d-9f7e-485a-ae48-7944763dbd8d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463845927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.1463845927
Directory /workspace/13.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.2320787237
Short name T1866
Test name
Test status
Simulation time 1551786813 ps
CPU time 122.03 seconds
Started Aug 02 07:54:23 PM PDT 24
Finished Aug 02 07:56:25 PM PDT 24
Peak memory 575864 kb
Host smart-d252ae06-d413-42fb-a340-541197794a4f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320787237 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.2320787237
Directory /workspace/13.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.3862980258
Short name T2374
Test name
Test status
Simulation time 410817978 ps
CPU time 194.57 seconds
Started Aug 02 07:54:23 PM PDT 24
Finished Aug 02 07:57:38 PM PDT 24
Peak memory 575948 kb
Host smart-2373365b-c560-496f-bd6b-24e819d36a98
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862980258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all
_with_rand_reset.3862980258
Directory /workspace/13.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.223917556
Short name T1784
Test name
Test status
Simulation time 2313933487 ps
CPU time 334.72 seconds
Started Aug 02 07:54:19 PM PDT 24
Finished Aug 02 07:59:54 PM PDT 24
Peak memory 576776 kb
Host smart-9fe51405-3aa7-4f12-8694-cac9d6e73c84
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223917556 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all
_with_reset_error.223917556
Directory /workspace/13.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.1993077136
Short name T672
Test name
Test status
Simulation time 808470703 ps
CPU time 33.9 seconds
Started Aug 02 07:54:26 PM PDT 24
Finished Aug 02 07:55:00 PM PDT 24
Peak memory 575980 kb
Host smart-2df6e13a-6c2e-4fe4-94d0-c7b82ba146f8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993077136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.1993077136
Directory /workspace/13.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.451825880
Short name T1618
Test name
Test status
Simulation time 9337279802 ps
CPU time 888.54 seconds
Started Aug 02 07:54:40 PM PDT 24
Finished Aug 02 08:09:29 PM PDT 24
Peak memory 647792 kb
Host smart-0b264439-dc54-4846-bfb6-951f97ac4d45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451825880 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.chip_csr_mem_rw_with_rand_reset.451825880
Directory /workspace/14.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.chip_csr_rw.3497123517
Short name T2458
Test name
Test status
Simulation time 3986106020 ps
CPU time 276.96 seconds
Started Aug 02 07:54:40 PM PDT 24
Finished Aug 02 07:59:17 PM PDT 24
Peak memory 597636 kb
Host smart-7b501bc7-0528-4c86-b4af-d0b7aafe72a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497123517 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_csr_rw.3497123517
Directory /workspace/14.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.3627813995
Short name T2310
Test name
Test status
Simulation time 28507718900 ps
CPU time 3927.81 seconds
Started Aug 02 07:54:29 PM PDT 24
Finished Aug 02 08:59:58 PM PDT 24
Peak memory 593456 kb
Host smart-1bb426b9-ce8c-42c6-b1f9-be7a3498b372
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627813995 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.chip_same_csr_outstanding.3627813995
Directory /workspace/14.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.chip_tl_errors.2095616072
Short name T698
Test name
Test status
Simulation time 3425870172 ps
CPU time 216.47 seconds
Started Aug 02 07:54:26 PM PDT 24
Finished Aug 02 07:58:02 PM PDT 24
Peak memory 603716 kb
Host smart-f4b0bd89-c142-4d9c-beec-89d96e994b49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095616072 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_tl_errors.2095616072
Directory /workspace/14.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_access_same_device.490620656
Short name T844
Test name
Test status
Simulation time 1390584236 ps
CPU time 55.29 seconds
Started Aug 02 07:54:42 PM PDT 24
Finished Aug 02 07:55:38 PM PDT 24
Peak memory 575776 kb
Host smart-90b22899-0cea-4f71-a4df-a12e00cb4ec8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490620656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.
490620656
Directory /workspace/14.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.811583971
Short name T1836
Test name
Test status
Simulation time 24031733445 ps
CPU time 351.77 seconds
Started Aug 02 07:54:44 PM PDT 24
Finished Aug 02 08:00:36 PM PDT 24
Peak memory 576008 kb
Host smart-3be7b578-58e3-425f-a7d9-44b593e4104a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811583971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_d
evice_slow_rsp.811583971
Directory /workspace/14.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.36631445
Short name T2815
Test name
Test status
Simulation time 1226784609 ps
CPU time 46.5 seconds
Started Aug 02 07:54:43 PM PDT 24
Finished Aug 02 07:55:29 PM PDT 24
Peak memory 575956 kb
Host smart-3cc27e92-976f-4abb-8a25-1a1b3e6f7152
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36631445 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.36631445
Directory /workspace/14.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_error_random.238540176
Short name T2079
Test name
Test status
Simulation time 1405504689 ps
CPU time 49.65 seconds
Started Aug 02 07:54:28 PM PDT 24
Finished Aug 02 07:55:18 PM PDT 24
Peak memory 575868 kb
Host smart-a56db02e-e1a8-4598-b7ae-3bd292e269ef
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238540176 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.238540176
Directory /workspace/14.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_random.3427667213
Short name T2080
Test name
Test status
Simulation time 2528970128 ps
CPU time 89.86 seconds
Started Aug 02 07:54:29 PM PDT 24
Finished Aug 02 07:55:59 PM PDT 24
Peak memory 576040 kb
Host smart-4ed8a94f-0e21-4399-b2e7-f3934a1e835e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427667213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random.3427667213
Directory /workspace/14.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_random_large_delays.3939875790
Short name T2874
Test name
Test status
Simulation time 22868244507 ps
CPU time 238.14 seconds
Started Aug 02 07:54:30 PM PDT 24
Finished Aug 02 07:58:28 PM PDT 24
Peak memory 576024 kb
Host smart-db90460b-3f1a-4581-b096-ac33345f6f32
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939875790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.3939875790
Directory /workspace/14.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.1607662183
Short name T2880
Test name
Test status
Simulation time 16051134829 ps
CPU time 275.03 seconds
Started Aug 02 07:54:29 PM PDT 24
Finished Aug 02 07:59:04 PM PDT 24
Peak memory 575848 kb
Host smart-4e654c03-f3c7-4683-b3c3-bb3b26375159
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607662183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.1607662183
Directory /workspace/14.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.3705453545
Short name T651
Test name
Test status
Simulation time 303993904 ps
CPU time 28.01 seconds
Started Aug 02 07:54:43 PM PDT 24
Finished Aug 02 07:55:11 PM PDT 24
Peak memory 575896 kb
Host smart-0dd5a807-af60-4062-8720-f3e334e87ee5
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705453545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_del
ays.3705453545
Directory /workspace/14.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_same_source.616757609
Short name T604
Test name
Test status
Simulation time 395083250 ps
CPU time 25.28 seconds
Started Aug 02 07:54:43 PM PDT 24
Finished Aug 02 07:55:08 PM PDT 24
Peak memory 575744 kb
Host smart-20018111-9ed0-43b7-af86-6d6b7d89db96
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616757609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.616757609
Directory /workspace/14.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_smoke.3316378644
Short name T1433
Test name
Test status
Simulation time 49216355 ps
CPU time 5.85 seconds
Started Aug 02 07:54:29 PM PDT 24
Finished Aug 02 07:54:35 PM PDT 24
Peak memory 573888 kb
Host smart-b6e91dd8-0699-4457-b2bb-131996c110bb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316378644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.3316378644
Directory /workspace/14.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.3510932822
Short name T2606
Test name
Test status
Simulation time 6397899418 ps
CPU time 65.15 seconds
Started Aug 02 07:54:27 PM PDT 24
Finished Aug 02 07:55:32 PM PDT 24
Peak memory 574644 kb
Host smart-cf8b8b9b-9145-4f0f-81b4-f53a20f37523
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510932822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.3510932822
Directory /workspace/14.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.95667077
Short name T1694
Test name
Test status
Simulation time 3405023087 ps
CPU time 54.74 seconds
Started Aug 02 07:54:30 PM PDT 24
Finished Aug 02 07:55:25 PM PDT 24
Peak memory 573844 kb
Host smart-39bc28e9-77bf-4502-a0c9-45475be9ff53
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95667077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.95667077
Directory /workspace/14.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.3588506437
Short name T2688
Test name
Test status
Simulation time 47736777 ps
CPU time 5.9 seconds
Started Aug 02 07:54:30 PM PDT 24
Finished Aug 02 07:54:36 PM PDT 24
Peak memory 574476 kb
Host smart-c96cf336-b746-4584-aaa4-86bb6b192230
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588506437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delay
s.3588506437
Directory /workspace/14.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_stress_all.1142097381
Short name T1915
Test name
Test status
Simulation time 4519285944 ps
CPU time 151.69 seconds
Started Aug 02 07:54:30 PM PDT 24
Finished Aug 02 07:57:01 PM PDT 24
Peak memory 576000 kb
Host smart-aa4bf5e7-9979-47f5-86a0-9b33d827a04f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142097381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.1142097381
Directory /workspace/14.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.4219877935
Short name T2520
Test name
Test status
Simulation time 1985618952 ps
CPU time 159.52 seconds
Started Aug 02 07:54:29 PM PDT 24
Finished Aug 02 07:57:08 PM PDT 24
Peak memory 576000 kb
Host smart-61bb4324-4774-42fa-b490-a5500afcbe50
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219877935 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.4219877935
Directory /workspace/14.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.1877998764
Short name T2174
Test name
Test status
Simulation time 157216161 ps
CPU time 47.08 seconds
Started Aug 02 07:54:28 PM PDT 24
Finished Aug 02 07:55:15 PM PDT 24
Peak memory 576732 kb
Host smart-1b571860-6086-4b30-a827-f202a843f14d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877998764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all
_with_rand_reset.1877998764
Directory /workspace/14.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.2070028488
Short name T2832
Test name
Test status
Simulation time 9274828189 ps
CPU time 414.53 seconds
Started Aug 02 07:54:39 PM PDT 24
Finished Aug 02 08:01:34 PM PDT 24
Peak memory 576892 kb
Host smart-d3553ebb-fc79-484a-9eb3-b4cfc411c9ea
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070028488 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_al
l_with_reset_error.2070028488
Directory /workspace/14.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.3099147586
Short name T1471
Test name
Test status
Simulation time 328836159 ps
CPU time 17.13 seconds
Started Aug 02 07:54:43 PM PDT 24
Finished Aug 02 07:55:00 PM PDT 24
Peak memory 575972 kb
Host smart-894233b4-0fd0-4c1b-ae25-8c7ba96dcf6d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099147586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.3099147586
Directory /workspace/14.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.2833284750
Short name T2152
Test name
Test status
Simulation time 7872947975 ps
CPU time 868.19 seconds
Started Aug 02 07:54:57 PM PDT 24
Finished Aug 02 08:09:26 PM PDT 24
Peak memory 645712 kb
Host smart-29a615eb-0e6b-4fbb-aa40-94f48a4f73a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833284750 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.chip_csr_mem_rw_with_rand_reset.2833284750
Directory /workspace/15.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.chip_csr_rw.228824490
Short name T417
Test name
Test status
Simulation time 3992545044 ps
CPU time 268.94 seconds
Started Aug 02 07:54:56 PM PDT 24
Finished Aug 02 07:59:25 PM PDT 24
Peak memory 597580 kb
Host smart-7ec219ae-865f-4355-ac49-6d140d649bce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228824490 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_rw.228824490
Directory /workspace/15.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.1500477869
Short name T2566
Test name
Test status
Simulation time 17519770436 ps
CPU time 2164.92 seconds
Started Aug 02 07:54:39 PM PDT 24
Finished Aug 02 08:30:44 PM PDT 24
Peak memory 593168 kb
Host smart-f39a9816-aa2a-412f-91a9-3c4e05f8a032
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500477869 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.chip_same_csr_outstanding.1500477869
Directory /workspace/15.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.chip_tl_errors.228280372
Short name T695
Test name
Test status
Simulation time 3931022272 ps
CPU time 248.38 seconds
Started Aug 02 07:54:40 PM PDT 24
Finished Aug 02 07:58:48 PM PDT 24
Peak memory 598624 kb
Host smart-01f75b4d-2466-4594-abc4-ac72a4729c52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228280372 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_tl_errors.228280372
Directory /workspace/15.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_access_same_device.2161048208
Short name T2293
Test name
Test status
Simulation time 114305966 ps
CPU time 8.01 seconds
Started Aug 02 07:54:54 PM PDT 24
Finished Aug 02 07:55:02 PM PDT 24
Peak memory 574480 kb
Host smart-987512a0-7ab7-4cc1-824e-03b9b3821690
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161048208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device
.2161048208
Directory /workspace/15.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.2281617925
Short name T840
Test name
Test status
Simulation time 66314293278 ps
CPU time 1133.78 seconds
Started Aug 02 07:54:54 PM PDT 24
Finished Aug 02 08:13:47 PM PDT 24
Peak memory 576016 kb
Host smart-c54ba602-496b-4e13-8711-a8d61d7cc900
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281617925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_
device_slow_rsp.2281617925
Directory /workspace/15.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.283838946
Short name T448
Test name
Test status
Simulation time 170957812 ps
CPU time 21.47 seconds
Started Aug 02 07:54:55 PM PDT 24
Finished Aug 02 07:55:17 PM PDT 24
Peak memory 575968 kb
Host smart-4da11337-5ee8-4903-8e8a-092d954f8bc8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283838946 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr
.283838946
Directory /workspace/15.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_error_random.2160346589
Short name T2539
Test name
Test status
Simulation time 227416689 ps
CPU time 18.56 seconds
Started Aug 02 07:54:55 PM PDT 24
Finished Aug 02 07:55:14 PM PDT 24
Peak memory 575904 kb
Host smart-47687feb-d0ed-47cf-a425-3b789150a241
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160346589 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.2160346589
Directory /workspace/15.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_random.3986122032
Short name T2006
Test name
Test status
Simulation time 479655011 ps
CPU time 38.55 seconds
Started Aug 02 07:54:41 PM PDT 24
Finished Aug 02 07:55:19 PM PDT 24
Peak memory 575764 kb
Host smart-077ee101-cded-4922-a135-f4cc84291ca6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986122032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random.3986122032
Directory /workspace/15.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_random_large_delays.2081170619
Short name T493
Test name
Test status
Simulation time 72268214817 ps
CPU time 805.78 seconds
Started Aug 02 07:54:56 PM PDT 24
Finished Aug 02 08:08:22 PM PDT 24
Peak memory 576068 kb
Host smart-e3b9d846-d77f-418b-bf9c-ffd37e29c151
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081170619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.2081170619
Directory /workspace/15.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.4174070822
Short name T2408
Test name
Test status
Simulation time 41936751229 ps
CPU time 691.56 seconds
Started Aug 02 07:54:55 PM PDT 24
Finished Aug 02 08:06:27 PM PDT 24
Peak memory 575876 kb
Host smart-45dfc5a1-4f40-4a9f-a238-57a071ccc22c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174070822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.4174070822
Directory /workspace/15.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.1570083360
Short name T2416
Test name
Test status
Simulation time 474053623 ps
CPU time 44.1 seconds
Started Aug 02 07:54:56 PM PDT 24
Finished Aug 02 07:55:40 PM PDT 24
Peak memory 575888 kb
Host smart-881f38f3-b4f9-41cb-a424-008d598733c8
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570083360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_del
ays.1570083360
Directory /workspace/15.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_same_source.1620089601
Short name T667
Test name
Test status
Simulation time 701598736 ps
CPU time 21.78 seconds
Started Aug 02 07:54:56 PM PDT 24
Finished Aug 02 07:55:18 PM PDT 24
Peak memory 575760 kb
Host smart-1255e3ea-2e01-4b4b-9c0c-3e1911f0a70b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620089601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.1620089601
Directory /workspace/15.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_smoke.4130645370
Short name T1575
Test name
Test status
Simulation time 216445856 ps
CPU time 9.29 seconds
Started Aug 02 07:54:39 PM PDT 24
Finished Aug 02 07:54:48 PM PDT 24
Peak memory 573800 kb
Host smart-59f9e121-42e7-42bd-a44e-fa7145d3fd1b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130645370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.4130645370
Directory /workspace/15.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.976170889
Short name T1629
Test name
Test status
Simulation time 8681113682 ps
CPU time 88.22 seconds
Started Aug 02 07:54:39 PM PDT 24
Finished Aug 02 07:56:08 PM PDT 24
Peak memory 573916 kb
Host smart-2e4a584f-ce1e-46be-9e26-9f90746e85ed
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976170889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.976170889
Directory /workspace/15.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.4268020364
Short name T2856
Test name
Test status
Simulation time 5463382947 ps
CPU time 84.85 seconds
Started Aug 02 07:54:40 PM PDT 24
Finished Aug 02 07:56:05 PM PDT 24
Peak memory 573984 kb
Host smart-c13723c7-3829-4c01-8861-14ae2f3f2d64
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268020364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.4268020364
Directory /workspace/15.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.3436319455
Short name T1852
Test name
Test status
Simulation time 51498023 ps
CPU time 6.34 seconds
Started Aug 02 07:54:42 PM PDT 24
Finished Aug 02 07:54:48 PM PDT 24
Peak memory 574588 kb
Host smart-24d704ba-e971-4d10-9186-4392b7b9da3f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436319455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delay
s.3436319455
Directory /workspace/15.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_stress_all.3469566739
Short name T1536
Test name
Test status
Simulation time 1143148631 ps
CPU time 86.02 seconds
Started Aug 02 07:54:55 PM PDT 24
Finished Aug 02 07:56:21 PM PDT 24
Peak memory 575916 kb
Host smart-6de18b54-7bd4-4a56-97f0-83aa9f1dd8ad
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469566739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.3469566739
Directory /workspace/15.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.1253498017
Short name T1832
Test name
Test status
Simulation time 5618942781 ps
CPU time 164.04 seconds
Started Aug 02 07:54:54 PM PDT 24
Finished Aug 02 07:57:38 PM PDT 24
Peak memory 576144 kb
Host smart-ccec48d5-8f04-42d3-9d8a-d7f9a035006f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253498017 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.1253498017
Directory /workspace/15.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.2653777857
Short name T897
Test name
Test status
Simulation time 3327147819 ps
CPU time 359.33 seconds
Started Aug 02 07:54:55 PM PDT 24
Finished Aug 02 08:00:55 PM PDT 24
Peak memory 576792 kb
Host smart-2e8e1e27-3ff5-45db-8623-08b96c93c537
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653777857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all
_with_rand_reset.2653777857
Directory /workspace/15.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.2231375390
Short name T2214
Test name
Test status
Simulation time 4107292043 ps
CPU time 409.46 seconds
Started Aug 02 07:54:54 PM PDT 24
Finished Aug 02 08:01:43 PM PDT 24
Peak memory 575960 kb
Host smart-2dff6658-a860-40e4-bcf4-e2ecb235880f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231375390 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_al
l_with_reset_error.2231375390
Directory /workspace/15.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.2965404313
Short name T2297
Test name
Test status
Simulation time 1062874129 ps
CPU time 42.99 seconds
Started Aug 02 07:54:54 PM PDT 24
Finished Aug 02 07:55:37 PM PDT 24
Peak memory 575840 kb
Host smart-f4f423ec-4d5d-4e50-94f6-97d6024402c9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965404313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.2965404313
Directory /workspace/15.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/16.chip_csr_rw.670305313
Short name T1602
Test name
Test status
Simulation time 5141493930 ps
CPU time 564.2 seconds
Started Aug 02 07:55:08 PM PDT 24
Finished Aug 02 08:04:33 PM PDT 24
Peak memory 598800 kb
Host smart-760bbc3c-7d50-4f69-9f4c-5ea1dff02d95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670305313 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_csr_rw.670305313
Directory /workspace/16.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.3277679446
Short name T141
Test name
Test status
Simulation time 16408211596 ps
CPU time 1901.84 seconds
Started Aug 02 07:54:57 PM PDT 24
Finished Aug 02 08:26:39 PM PDT 24
Peak memory 593448 kb
Host smart-b524c02a-573e-4cd0-aeff-eef84f1528dd
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277679446 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.chip_same_csr_outstanding.3277679446
Directory /workspace/16.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_access_same_device.4264176132
Short name T2114
Test name
Test status
Simulation time 3025001535 ps
CPU time 114.44 seconds
Started Aug 02 07:55:09 PM PDT 24
Finished Aug 02 07:57:04 PM PDT 24
Peak memory 576060 kb
Host smart-b4772fd9-dd82-4967-9719-fcfa8129c945
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264176132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device
.4264176132
Directory /workspace/16.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.2317350741
Short name T1994
Test name
Test status
Simulation time 139948248739 ps
CPU time 2407.35 seconds
Started Aug 02 07:55:07 PM PDT 24
Finished Aug 02 08:35:15 PM PDT 24
Peak memory 575940 kb
Host smart-b308594b-1ed0-464d-855a-ae2d4139d538
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317350741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_
device_slow_rsp.2317350741
Directory /workspace/16.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.1582309901
Short name T1681
Test name
Test status
Simulation time 278876795 ps
CPU time 27.26 seconds
Started Aug 02 07:55:08 PM PDT 24
Finished Aug 02 07:55:35 PM PDT 24
Peak memory 576004 kb
Host smart-35a3550f-6f87-4479-ac13-5b7d0563068b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582309901 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_add
r.1582309901
Directory /workspace/16.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_error_random.1261733642
Short name T1439
Test name
Test status
Simulation time 321713363 ps
CPU time 26.37 seconds
Started Aug 02 07:55:10 PM PDT 24
Finished Aug 02 07:55:36 PM PDT 24
Peak memory 575952 kb
Host smart-c2e6b827-f186-417e-b739-392416071867
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261733642 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.1261733642
Directory /workspace/16.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_random.713480100
Short name T2656
Test name
Test status
Simulation time 1021245759 ps
CPU time 38.03 seconds
Started Aug 02 07:55:10 PM PDT 24
Finished Aug 02 07:55:48 PM PDT 24
Peak memory 575944 kb
Host smart-22f0f22a-7b1c-4bdd-b777-891308addcc2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713480100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random.713480100
Directory /workspace/16.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_random_large_delays.92186404
Short name T2028
Test name
Test status
Simulation time 17966513894 ps
CPU time 179 seconds
Started Aug 02 07:55:04 PM PDT 24
Finished Aug 02 07:58:03 PM PDT 24
Peak memory 575964 kb
Host smart-3675874a-8328-48f5-a2ae-2121df052c1c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92186404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.92186404
Directory /workspace/16.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.3178983370
Short name T2038
Test name
Test status
Simulation time 67720539098 ps
CPU time 1110.32 seconds
Started Aug 02 07:55:10 PM PDT 24
Finished Aug 02 08:13:41 PM PDT 24
Peak memory 576736 kb
Host smart-ce6eb4b0-ac11-4bdc-a8a6-5e6408614e6c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178983370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.3178983370
Directory /workspace/16.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.2907979394
Short name T592
Test name
Test status
Simulation time 293510021 ps
CPU time 25.11 seconds
Started Aug 02 07:55:06 PM PDT 24
Finished Aug 02 07:55:31 PM PDT 24
Peak memory 575708 kb
Host smart-7dbf9fff-bd52-422a-8e3a-b4c5299404c8
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907979394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_del
ays.2907979394
Directory /workspace/16.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_same_source.3959746639
Short name T2422
Test name
Test status
Simulation time 1151627879 ps
CPU time 38.07 seconds
Started Aug 02 07:55:06 PM PDT 24
Finished Aug 02 07:55:44 PM PDT 24
Peak memory 575824 kb
Host smart-8e868d22-d62d-43be-8833-6dabc46cfb4b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959746639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.3959746639
Directory /workspace/16.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_smoke.1223977133
Short name T1990
Test name
Test status
Simulation time 161737006 ps
CPU time 8.74 seconds
Started Aug 02 07:54:59 PM PDT 24
Finished Aug 02 07:55:07 PM PDT 24
Peak memory 574492 kb
Host smart-e5e6274b-6d4f-42f4-b8c8-5eb021c6acde
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223977133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.1223977133
Directory /workspace/16.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.4257295518
Short name T1599
Test name
Test status
Simulation time 10149982024 ps
CPU time 108.25 seconds
Started Aug 02 07:54:58 PM PDT 24
Finished Aug 02 07:56:46 PM PDT 24
Peak memory 574680 kb
Host smart-9642622d-2379-4012-9e31-5dc1069561b0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257295518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.4257295518
Directory /workspace/16.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.242187635
Short name T1987
Test name
Test status
Simulation time 4464228703 ps
CPU time 71.98 seconds
Started Aug 02 07:55:09 PM PDT 24
Finished Aug 02 07:56:21 PM PDT 24
Peak memory 574636 kb
Host smart-8ed14ff7-0841-43e5-a7af-977869e5059a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242187635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.242187635
Directory /workspace/16.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.530953021
Short name T1496
Test name
Test status
Simulation time 41312028 ps
CPU time 6.84 seconds
Started Aug 02 07:54:58 PM PDT 24
Finished Aug 02 07:55:05 PM PDT 24
Peak memory 574520 kb
Host smart-295f3023-d503-4d59-bb25-d6f637eb6de9
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530953021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays
.530953021
Directory /workspace/16.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.2226632772
Short name T2286
Test name
Test status
Simulation time 5768398337 ps
CPU time 166.32 seconds
Started Aug 02 07:55:10 PM PDT 24
Finished Aug 02 07:57:56 PM PDT 24
Peak memory 576232 kb
Host smart-9da574a5-23af-4db8-881e-f6960ba5226c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226632772 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.2226632772
Directory /workspace/16.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.7393610
Short name T2607
Test name
Test status
Simulation time 347431317 ps
CPU time 167.95 seconds
Started Aug 02 07:55:04 PM PDT 24
Finished Aug 02 07:57:52 PM PDT 24
Peak memory 576732 kb
Host smart-f117800d-ae85-4bdc-b69d-014311cccf9e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7393610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_wi
th_rand_reset.7393610
Directory /workspace/16.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.1458256183
Short name T2069
Test name
Test status
Simulation time 1411487586 ps
CPU time 120.88 seconds
Started Aug 02 07:55:07 PM PDT 24
Finished Aug 02 07:57:08 PM PDT 24
Peak memory 576804 kb
Host smart-24296476-b3ba-442a-ae3e-8a19a00569fc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458256183 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_al
l_with_reset_error.1458256183
Directory /workspace/16.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.4216706402
Short name T1427
Test name
Test status
Simulation time 246732430 ps
CPU time 30.52 seconds
Started Aug 02 07:55:07 PM PDT 24
Finished Aug 02 07:55:38 PM PDT 24
Peak memory 575980 kb
Host smart-333dc638-13c0-4339-8903-15cf28ed930e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216706402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.4216706402
Directory /workspace/16.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.3399846718
Short name T1709
Test name
Test status
Simulation time 6716906107 ps
CPU time 439.68 seconds
Started Aug 02 07:55:36 PM PDT 24
Finished Aug 02 08:02:56 PM PDT 24
Peak memory 647268 kb
Host smart-ae6d547b-bbab-48d9-b9ab-1f66d50c5c88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399846718 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.chip_csr_mem_rw_with_rand_reset.3399846718
Directory /workspace/17.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.chip_csr_rw.659218972
Short name T2757
Test name
Test status
Simulation time 4009689200 ps
CPU time 248.77 seconds
Started Aug 02 07:55:36 PM PDT 24
Finished Aug 02 07:59:45 PM PDT 24
Peak memory 597476 kb
Host smart-fc837567-1844-4eaa-a2ac-bce63a8a4212
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659218972 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_rw.659218972
Directory /workspace/17.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.3701668838
Short name T2798
Test name
Test status
Simulation time 13771723177 ps
CPU time 1406.89 seconds
Started Aug 02 07:55:21 PM PDT 24
Finished Aug 02 08:18:49 PM PDT 24
Peak memory 593268 kb
Host smart-415ff594-fcc6-4d68-b01f-ead9d0cb6fc1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701668838 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.chip_same_csr_outstanding.3701668838
Directory /workspace/17.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_access_same_device.871747052
Short name T2215
Test name
Test status
Simulation time 2841630491 ps
CPU time 104.89 seconds
Started Aug 02 07:55:22 PM PDT 24
Finished Aug 02 07:57:07 PM PDT 24
Peak memory 576064 kb
Host smart-12eac403-0658-4464-abca-09b110d31dee
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871747052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.
871747052
Directory /workspace/17.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.1753899144
Short name T2726
Test name
Test status
Simulation time 118090062913 ps
CPU time 2068.13 seconds
Started Aug 02 07:55:34 PM PDT 24
Finished Aug 02 08:30:02 PM PDT 24
Peak memory 576820 kb
Host smart-0a826063-af02-4c36-9d29-2f3c60d80625
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753899144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_
device_slow_rsp.1753899144
Directory /workspace/17.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.1462519058
Short name T1537
Test name
Test status
Simulation time 1372672579 ps
CPU time 49.38 seconds
Started Aug 02 07:55:36 PM PDT 24
Finished Aug 02 07:56:25 PM PDT 24
Peak memory 575980 kb
Host smart-ec3418e8-ac1a-4676-854a-b6057f714c37
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462519058 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_add
r.1462519058
Directory /workspace/17.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_error_random.2782275344
Short name T1565
Test name
Test status
Simulation time 1486532349 ps
CPU time 47.58 seconds
Started Aug 02 07:55:48 PM PDT 24
Finished Aug 02 07:56:35 PM PDT 24
Peak memory 575948 kb
Host smart-96ed2a7e-a657-42f9-ae8d-dd29f23974cf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782275344 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.2782275344
Directory /workspace/17.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_random.3808497643
Short name T2210
Test name
Test status
Simulation time 533949210 ps
CPU time 47.74 seconds
Started Aug 02 07:55:21 PM PDT 24
Finished Aug 02 07:56:09 PM PDT 24
Peak memory 575884 kb
Host smart-e599fd9a-dd67-466e-924e-57a8dafbb85a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808497643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random.3808497643
Directory /workspace/17.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_random_large_delays.3527821801
Short name T2157
Test name
Test status
Simulation time 48434953698 ps
CPU time 503.27 seconds
Started Aug 02 07:55:21 PM PDT 24
Finished Aug 02 08:03:44 PM PDT 24
Peak memory 576008 kb
Host smart-d98c3573-2537-4141-90a3-0bd910ed7dd2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527821801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.3527821801
Directory /workspace/17.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.2231083515
Short name T679
Test name
Test status
Simulation time 53780729777 ps
CPU time 864.56 seconds
Started Aug 02 07:55:20 PM PDT 24
Finished Aug 02 08:09:45 PM PDT 24
Peak memory 576024 kb
Host smart-b272d2ef-a311-4183-86cd-8e2ec1b0fd7f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231083515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.2231083515
Directory /workspace/17.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.898446928
Short name T1487
Test name
Test status
Simulation time 328677245 ps
CPU time 29.01 seconds
Started Aug 02 07:55:20 PM PDT 24
Finished Aug 02 07:55:49 PM PDT 24
Peak memory 575720 kb
Host smart-c170315d-53bd-4901-956b-7c87363b1ab5
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898446928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_dela
ys.898446928
Directory /workspace/17.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_same_source.181143784
Short name T2319
Test name
Test status
Simulation time 1151279127 ps
CPU time 32.74 seconds
Started Aug 02 07:55:35 PM PDT 24
Finished Aug 02 07:56:08 PM PDT 24
Peak memory 575836 kb
Host smart-b6c2b7c7-4bf2-4fc1-9c2c-3c950d6582c3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181143784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.181143784
Directory /workspace/17.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_smoke.1891220947
Short name T1548
Test name
Test status
Simulation time 52782287 ps
CPU time 6.16 seconds
Started Aug 02 07:55:21 PM PDT 24
Finished Aug 02 07:55:27 PM PDT 24
Peak memory 574532 kb
Host smart-8dab5039-4961-4976-bce4-1315515203aa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891220947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.1891220947
Directory /workspace/17.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.1639736475
Short name T1869
Test name
Test status
Simulation time 6374817748 ps
CPU time 66.2 seconds
Started Aug 02 07:55:20 PM PDT 24
Finished Aug 02 07:56:27 PM PDT 24
Peak memory 573956 kb
Host smart-b4b7cc97-bf82-40a6-90be-f9b89cc237d0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639736475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.1639736475
Directory /workspace/17.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.2955100714
Short name T2499
Test name
Test status
Simulation time 5822205138 ps
CPU time 102.17 seconds
Started Aug 02 07:55:20 PM PDT 24
Finished Aug 02 07:57:02 PM PDT 24
Peak memory 573936 kb
Host smart-5c51d910-8aa6-4a02-a849-7b640f9aeeb3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955100714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.2955100714
Directory /workspace/17.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.2573488533
Short name T1473
Test name
Test status
Simulation time 58125468 ps
CPU time 7.08 seconds
Started Aug 02 07:55:20 PM PDT 24
Finished Aug 02 07:55:27 PM PDT 24
Peak memory 574488 kb
Host smart-c5ebe080-e737-49a2-a520-a746842f5f52
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573488533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delay
s.2573488533
Directory /workspace/17.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_stress_all.1342961906
Short name T1926
Test name
Test status
Simulation time 2387954016 ps
CPU time 163.65 seconds
Started Aug 02 07:55:48 PM PDT 24
Finished Aug 02 07:58:32 PM PDT 24
Peak memory 576044 kb
Host smart-d8c19af5-dcbf-4908-836e-699e16a2095b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342961906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.1342961906
Directory /workspace/17.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.2085386821
Short name T1770
Test name
Test status
Simulation time 15843542688 ps
CPU time 558.59 seconds
Started Aug 02 07:55:48 PM PDT 24
Finished Aug 02 08:05:07 PM PDT 24
Peak memory 575968 kb
Host smart-8eb6f9a0-b616-403e-8059-5e6249ff06c9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085386821 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.2085386821
Directory /workspace/17.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.3980283163
Short name T2524
Test name
Test status
Simulation time 345968132 ps
CPU time 15.78 seconds
Started Aug 02 07:55:32 PM PDT 24
Finished Aug 02 07:55:48 PM PDT 24
Peak memory 575936 kb
Host smart-2ca59f12-22dc-4cf5-8ef3-0131a3718ef2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980283163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.3980283163
Directory /workspace/17.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.2190604271
Short name T2930
Test name
Test status
Simulation time 9348286669 ps
CPU time 843.39 seconds
Started Aug 02 07:55:47 PM PDT 24
Finished Aug 02 08:09:50 PM PDT 24
Peak memory 653012 kb
Host smart-81ca7a73-ec88-425d-9838-66ac9b672d1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190604271 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.chip_csr_mem_rw_with_rand_reset.2190604271
Directory /workspace/18.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.chip_csr_rw.489973907
Short name T2533
Test name
Test status
Simulation time 5729687334 ps
CPU time 462.44 seconds
Started Aug 02 07:55:50 PM PDT 24
Finished Aug 02 08:03:33 PM PDT 24
Peak memory 598656 kb
Host smart-f55f0635-31f6-4a7b-9359-b63570416661
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489973907 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_rw.489973907
Directory /workspace/18.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.chip_tl_errors.1117564748
Short name T724
Test name
Test status
Simulation time 4527402950 ps
CPU time 312.91 seconds
Started Aug 02 07:55:36 PM PDT 24
Finished Aug 02 08:00:49 PM PDT 24
Peak memory 598664 kb
Host smart-6a32508a-e237-46f9-a114-b0d14c92f9c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117564748 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_tl_errors.1117564748
Directory /workspace/18.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_access_same_device.1947138452
Short name T857
Test name
Test status
Simulation time 444259322 ps
CPU time 26.28 seconds
Started Aug 02 07:55:47 PM PDT 24
Finished Aug 02 07:56:13 PM PDT 24
Peak memory 575992 kb
Host smart-e8fb5907-eea4-4041-b834-252096432b2e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947138452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device
.1947138452
Directory /workspace/18.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.2359240197
Short name T509
Test name
Test status
Simulation time 63097783809 ps
CPU time 1132.21 seconds
Started Aug 02 07:55:49 PM PDT 24
Finished Aug 02 08:14:42 PM PDT 24
Peak memory 576152 kb
Host smart-1e6dc4f1-e2c5-4e4f-8538-5137ee579745
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359240197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_
device_slow_rsp.2359240197
Directory /workspace/18.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.1169619156
Short name T2135
Test name
Test status
Simulation time 47718753 ps
CPU time 8.4 seconds
Started Aug 02 07:55:47 PM PDT 24
Finished Aug 02 07:55:55 PM PDT 24
Peak memory 575904 kb
Host smart-6eb754d1-9e60-4f54-ba25-6712999295f1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169619156 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_add
r.1169619156
Directory /workspace/18.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_error_random.1364324770
Short name T2462
Test name
Test status
Simulation time 32493515 ps
CPU time 5.59 seconds
Started Aug 02 07:55:48 PM PDT 24
Finished Aug 02 07:55:53 PM PDT 24
Peak memory 573832 kb
Host smart-725b8395-76a7-4b02-b3c7-dd577158779d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364324770 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.1364324770
Directory /workspace/18.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_random.3626884319
Short name T2227
Test name
Test status
Simulation time 1193461945 ps
CPU time 44 seconds
Started Aug 02 07:55:35 PM PDT 24
Finished Aug 02 07:56:19 PM PDT 24
Peak memory 575904 kb
Host smart-9eb609b7-36cf-4642-92de-34df0c908132
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626884319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random.3626884319
Directory /workspace/18.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_random_large_delays.1883422430
Short name T1899
Test name
Test status
Simulation time 44268047747 ps
CPU time 452.44 seconds
Started Aug 02 07:55:36 PM PDT 24
Finished Aug 02 08:03:08 PM PDT 24
Peak memory 576752 kb
Host smart-5ee4c4d9-5530-4ce4-9db9-6dc4d235e808
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883422430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.1883422430
Directory /workspace/18.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.2077473709
Short name T2654
Test name
Test status
Simulation time 28307273769 ps
CPU time 435.02 seconds
Started Aug 02 07:55:47 PM PDT 24
Finished Aug 02 08:03:02 PM PDT 24
Peak memory 576052 kb
Host smart-087147cb-1a7e-4025-a861-be963d3b9990
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077473709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.2077473709
Directory /workspace/18.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.3889651113
Short name T2177
Test name
Test status
Simulation time 387853870 ps
CPU time 31.39 seconds
Started Aug 02 07:55:31 PM PDT 24
Finished Aug 02 07:56:03 PM PDT 24
Peak memory 575848 kb
Host smart-425acba5-4cad-489f-8ec7-15b4164b500f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889651113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_del
ays.3889651113
Directory /workspace/18.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_same_source.773301077
Short name T1813
Test name
Test status
Simulation time 562353831 ps
CPU time 18.57 seconds
Started Aug 02 07:55:49 PM PDT 24
Finished Aug 02 07:56:08 PM PDT 24
Peak memory 575768 kb
Host smart-45dc0b4b-ee90-49b5-b8ba-c1c441ef7c09
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773301077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.773301077
Directory /workspace/18.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_smoke.3889165464
Short name T2910
Test name
Test status
Simulation time 55491758 ps
CPU time 6.31 seconds
Started Aug 02 07:55:33 PM PDT 24
Finished Aug 02 07:55:40 PM PDT 24
Peak memory 574652 kb
Host smart-41746486-3150-4999-a0dd-cff14feae59b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889165464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.3889165464
Directory /workspace/18.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.2955258867
Short name T1573
Test name
Test status
Simulation time 5763016089 ps
CPU time 57.29 seconds
Started Aug 02 07:55:48 PM PDT 24
Finished Aug 02 07:56:45 PM PDT 24
Peak memory 573900 kb
Host smart-aac005b9-d814-403b-9d8c-6a8aa6880295
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955258867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.2955258867
Directory /workspace/18.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.2915957465
Short name T2810
Test name
Test status
Simulation time 5132571198 ps
CPU time 81.83 seconds
Started Aug 02 07:55:36 PM PDT 24
Finished Aug 02 07:56:58 PM PDT 24
Peak memory 573852 kb
Host smart-29c3f591-1cf1-4628-ba02-c658d20814c0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915957465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.2915957465
Directory /workspace/18.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.2260271523
Short name T1636
Test name
Test status
Simulation time 58573969 ps
CPU time 7.02 seconds
Started Aug 02 07:55:33 PM PDT 24
Finished Aug 02 07:55:40 PM PDT 24
Peak memory 574520 kb
Host smart-2cdd687e-5f74-4faa-abd9-c32fec2f5582
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260271523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delay
s.2260271523
Directory /workspace/18.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.316291688
Short name T2878
Test name
Test status
Simulation time 10380117224 ps
CPU time 349.45 seconds
Started Aug 02 07:55:44 PM PDT 24
Finished Aug 02 08:01:34 PM PDT 24
Peak memory 576272 kb
Host smart-65c896ea-c7e7-439f-989d-313f81bd3896
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316291688 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.316291688
Directory /workspace/18.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.3981262953
Short name T2796
Test name
Test status
Simulation time 15591061833 ps
CPU time 563.73 seconds
Started Aug 02 07:55:48 PM PDT 24
Finished Aug 02 08:05:12 PM PDT 24
Peak memory 575928 kb
Host smart-b3ead3f3-eb26-4068-890b-39cfa92d284c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981262953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all
_with_rand_reset.3981262953
Directory /workspace/18.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.3872573839
Short name T2010
Test name
Test status
Simulation time 4572666830 ps
CPU time 194.97 seconds
Started Aug 02 07:55:50 PM PDT 24
Finished Aug 02 07:59:05 PM PDT 24
Peak memory 576700 kb
Host smart-a1006cf1-8bf7-41eb-8f92-0fb855fbc050
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872573839 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_al
l_with_reset_error.3872573839
Directory /workspace/18.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.1207157222
Short name T1412
Test name
Test status
Simulation time 216094128 ps
CPU time 11.69 seconds
Started Aug 02 07:55:50 PM PDT 24
Finished Aug 02 07:56:02 PM PDT 24
Peak memory 576020 kb
Host smart-90febefd-558e-4b8f-90bc-8a6ee92dd0d3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207157222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.1207157222
Directory /workspace/18.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/19.chip_csr_rw.3270781692
Short name T2284
Test name
Test status
Simulation time 4313635549 ps
CPU time 331.51 seconds
Started Aug 02 07:56:03 PM PDT 24
Finished Aug 02 08:01:35 PM PDT 24
Peak memory 597068 kb
Host smart-e08de982-6e5b-4104-a310-dd82943f0ad5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270781692 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_csr_rw.3270781692
Directory /workspace/19.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.2429740474
Short name T1968
Test name
Test status
Simulation time 14905643742 ps
CPU time 1703.88 seconds
Started Aug 02 07:55:49 PM PDT 24
Finished Aug 02 08:24:13 PM PDT 24
Peak memory 593248 kb
Host smart-c2cb1938-78bf-4e04-a62d-e3200fa44d8f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429740474 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.chip_same_csr_outstanding.2429740474
Directory /workspace/19.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.chip_tl_errors.3894663712
Short name T727
Test name
Test status
Simulation time 2983812723 ps
CPU time 243.83 seconds
Started Aug 02 07:55:48 PM PDT 24
Finished Aug 02 07:59:52 PM PDT 24
Peak memory 599920 kb
Host smart-aec7e571-88b0-49fe-bac3-75cd805e1487
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894663712 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_tl_errors.3894663712
Directory /workspace/19.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_access_same_device.3620350270
Short name T1839
Test name
Test status
Simulation time 808016926 ps
CPU time 53.2 seconds
Started Aug 02 07:56:06 PM PDT 24
Finished Aug 02 07:56:59 PM PDT 24
Peak memory 575888 kb
Host smart-f45c3082-cbc8-4b91-a11b-5ec60225ae0c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620350270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device
.3620350270
Directory /workspace/19.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.3713111381
Short name T1868
Test name
Test status
Simulation time 133912077581 ps
CPU time 2315.49 seconds
Started Aug 02 07:56:03 PM PDT 24
Finished Aug 02 08:34:39 PM PDT 24
Peak memory 576004 kb
Host smart-bd79b982-0ca9-4ce7-bf40-50c7e525bfb9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713111381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_
device_slow_rsp.3713111381
Directory /workspace/19.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.4281439003
Short name T1898
Test name
Test status
Simulation time 240979906 ps
CPU time 27.98 seconds
Started Aug 02 07:56:06 PM PDT 24
Finished Aug 02 07:56:34 PM PDT 24
Peak memory 575896 kb
Host smart-76a5343a-cd05-4b11-bb9d-10d5403efedd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281439003 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_add
r.4281439003
Directory /workspace/19.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_error_random.3180974409
Short name T2611
Test name
Test status
Simulation time 61652274 ps
CPU time 8.59 seconds
Started Aug 02 07:56:05 PM PDT 24
Finished Aug 02 07:56:13 PM PDT 24
Peak memory 575780 kb
Host smart-a9ed2a85-7adf-4e47-af3b-b38043dacd8d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180974409 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.3180974409
Directory /workspace/19.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_random.2232972369
Short name T1663
Test name
Test status
Simulation time 125305864 ps
CPU time 16.28 seconds
Started Aug 02 07:56:05 PM PDT 24
Finished Aug 02 07:56:21 PM PDT 24
Peak memory 575964 kb
Host smart-dd338025-62c3-4126-9361-7d152daedf03
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232972369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random.2232972369
Directory /workspace/19.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_random_large_delays.4093370756
Short name T631
Test name
Test status
Simulation time 37218281191 ps
CPU time 405.34 seconds
Started Aug 02 07:56:03 PM PDT 24
Finished Aug 02 08:02:49 PM PDT 24
Peak memory 575952 kb
Host smart-b279b007-fbb8-4373-bb4c-5880ca9e8905
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093370756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.4093370756
Directory /workspace/19.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.2112974907
Short name T2180
Test name
Test status
Simulation time 40905803041 ps
CPU time 700.91 seconds
Started Aug 02 07:56:05 PM PDT 24
Finished Aug 02 08:07:46 PM PDT 24
Peak memory 576724 kb
Host smart-41b79e85-9ec7-48a4-a7a5-dcc8b24ff8df
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112974907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.2112974907
Directory /workspace/19.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.3603590240
Short name T2691
Test name
Test status
Simulation time 361642689 ps
CPU time 29.23 seconds
Started Aug 02 07:56:00 PM PDT 24
Finished Aug 02 07:56:29 PM PDT 24
Peak memory 575740 kb
Host smart-9288a515-9717-4cf6-85fe-e8748d33eb3c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603590240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_del
ays.3603590240
Directory /workspace/19.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_same_source.1063023544
Short name T1846
Test name
Test status
Simulation time 2659703691 ps
CPU time 84.96 seconds
Started Aug 02 07:56:06 PM PDT 24
Finished Aug 02 07:57:31 PM PDT 24
Peak memory 576036 kb
Host smart-eb551097-8f0f-4e2a-a75d-f6e6e668b6e3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063023544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.1063023544
Directory /workspace/19.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_smoke.1792030464
Short name T2064
Test name
Test status
Simulation time 248788071 ps
CPU time 9.74 seconds
Started Aug 02 07:55:48 PM PDT 24
Finished Aug 02 07:55:58 PM PDT 24
Peak memory 574560 kb
Host smart-3b933815-4f71-4d8b-9bf4-6936fd5b3e0f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792030464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.1792030464
Directory /workspace/19.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_smoke_large_delays.387717132
Short name T2424
Test name
Test status
Simulation time 10026921956 ps
CPU time 106.15 seconds
Started Aug 02 07:55:49 PM PDT 24
Finished Aug 02 07:57:35 PM PDT 24
Peak memory 574652 kb
Host smart-71bae48d-fe68-4347-b69f-c32d3c474a50
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387717132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.387717132
Directory /workspace/19.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.873672490
Short name T2435
Test name
Test status
Simulation time 5025657155 ps
CPU time 91.58 seconds
Started Aug 02 07:56:05 PM PDT 24
Finished Aug 02 07:57:36 PM PDT 24
Peak memory 574624 kb
Host smart-b3787b48-be88-4e37-955a-b672ebdf45ab
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873672490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.873672490
Directory /workspace/19.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.4161596709
Short name T2868
Test name
Test status
Simulation time 41814767 ps
CPU time 6.36 seconds
Started Aug 02 07:55:48 PM PDT 24
Finished Aug 02 07:55:54 PM PDT 24
Peak memory 573808 kb
Host smart-bd1d9210-b822-4775-9375-a9ab403f7853
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161596709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delay
s.4161596709
Directory /workspace/19.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_stress_all.814881622
Short name T2385
Test name
Test status
Simulation time 3338367775 ps
CPU time 283.04 seconds
Started Aug 02 07:56:02 PM PDT 24
Finished Aug 02 08:00:45 PM PDT 24
Peak memory 576792 kb
Host smart-4ee8d3c6-6818-4e13-bc1c-45d702a6f519
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814881622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.814881622
Directory /workspace/19.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.3230256755
Short name T1699
Test name
Test status
Simulation time 2134734563 ps
CPU time 149.99 seconds
Started Aug 02 07:56:05 PM PDT 24
Finished Aug 02 07:58:35 PM PDT 24
Peak memory 575904 kb
Host smart-d115f7f3-2ba4-40c0-aabc-01f1f5a5a9a1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230256755 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.3230256755
Directory /workspace/19.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.2454269935
Short name T1842
Test name
Test status
Simulation time 1412665028 ps
CPU time 141.31 seconds
Started Aug 02 07:56:04 PM PDT 24
Finished Aug 02 07:58:25 PM PDT 24
Peak memory 576584 kb
Host smart-29b386d0-6ea0-4f83-a793-4ee66d3ed58e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454269935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all
_with_rand_reset.2454269935
Directory /workspace/19.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.2551765940
Short name T2233
Test name
Test status
Simulation time 5741084249 ps
CPU time 481.12 seconds
Started Aug 02 07:56:04 PM PDT 24
Finished Aug 02 08:04:06 PM PDT 24
Peak memory 576896 kb
Host smart-0dc43860-3886-4c3d-a183-057b3f25d10f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551765940 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_al
l_with_reset_error.2551765940
Directory /workspace/19.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.113767603
Short name T2483
Test name
Test status
Simulation time 748941566 ps
CPU time 29.55 seconds
Started Aug 02 07:56:01 PM PDT 24
Finished Aug 02 07:56:30 PM PDT 24
Peak memory 576012 kb
Host smart-23e107d3-dd86-43d5-8088-32e1aef08a3e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113767603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.113767603
Directory /workspace/19.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/2.chip_csr_aliasing.2854096175
Short name T1983
Test name
Test status
Simulation time 31272382744 ps
CPU time 7622.97 seconds
Started Aug 02 07:52:01 PM PDT 24
Finished Aug 02 09:59:05 PM PDT 24
Peak memory 594024 kb
Host smart-ec6348ae-0f80-403b-9f72-3db6e03ad5bd
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854096175 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 2.chip_csr_aliasing.2854096175
Directory /workspace/2.chip_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.2287533729
Short name T1608
Test name
Test status
Simulation time 5578107082 ps
CPU time 535.57 seconds
Started Aug 02 07:51:55 PM PDT 24
Finished Aug 02 08:00:51 PM PDT 24
Peak memory 592856 kb
Host smart-e98a2f96-71c2-4f56-8efa-0e354e8cb1b8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287533729 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 2.chip_csr_bit_bash.2287533729
Directory /workspace/2.chip_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.3703452188
Short name T2699
Test name
Test status
Simulation time 6992362100 ps
CPU time 473.29 seconds
Started Aug 02 07:52:07 PM PDT 24
Finished Aug 02 08:00:00 PM PDT 24
Peak memory 642752 kb
Host smart-2ffe9b58-4304-473a-acb5-b09d90c63a0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703452188 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.chip_csr_mem_rw_with_rand_reset.3703452188
Directory /workspace/2.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.chip_csr_rw.1117652485
Short name T452
Test name
Test status
Simulation time 3552804225 ps
CPU time 279.57 seconds
Started Aug 02 07:52:07 PM PDT 24
Finished Aug 02 07:56:46 PM PDT 24
Peak memory 598664 kb
Host smart-bf63a417-2a48-42a0-8204-32d5a92c391b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117652485 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_rw.1117652485
Directory /workspace/2.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.chip_prim_tl_access.3248171583
Short name T2134
Test name
Test status
Simulation time 7387142900 ps
CPU time 310.75 seconds
Started Aug 02 07:51:52 PM PDT 24
Finished Aug 02 07:57:03 PM PDT 24
Peak memory 591468 kb
Host smart-a6ab5fbb-8445-4701-95a8-d47e378982f8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248171583 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE
Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.chip_prim_tl_access.3248171583
Directory /workspace/2.chip_prim_tl_access/latest

Test location /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.3456156524
Short name T2017
Test name
Test status
Simulation time 8541080036 ps
CPU time 444.8 seconds
Started Aug 02 07:51:52 PM PDT 24
Finished Aug 02 07:59:17 PM PDT 24
Peak memory 590380 kb
Host smart-daae6f8f-9b8a-4dd8-9d54-08ae254cddd3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456156524 -assert nopostproc +UVM_TESTNAME=chip_base_t
est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.chip_rv_dm_lc_disabled.3456156524
Directory /workspace/2.chip_rv_dm_lc_disabled/latest

Test location /workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.1953061433
Short name T445
Test name
Test status
Simulation time 15150454270 ps
CPU time 2270.23 seconds
Started Aug 02 07:51:53 PM PDT 24
Finished Aug 02 08:29:44 PM PDT 24
Peak memory 592964 kb
Host smart-27671668-598a-4e0d-9f98-4576843d47d4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953061433 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.chip_same_csr_outstanding.1953061433
Directory /workspace/2.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.chip_tl_errors.4017217199
Short name T2790
Test name
Test status
Simulation time 2690659348 ps
CPU time 92.1 seconds
Started Aug 02 07:51:53 PM PDT 24
Finished Aug 02 07:53:25 PM PDT 24
Peak memory 603780 kb
Host smart-f220ac6d-29b6-4b68-b5e3-a902a63d642a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017217199 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_tl_errors.4017217199
Directory /workspace/2.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_access_same_device.3591269112
Short name T1856
Test name
Test status
Simulation time 341084082 ps
CPU time 15.39 seconds
Started Aug 02 07:51:55 PM PDT 24
Finished Aug 02 07:52:11 PM PDT 24
Peak memory 575916 kb
Host smart-83b9e366-b82d-42fd-8988-f7fae00900af
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591269112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.
3591269112
Directory /workspace/2.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.4254845607
Short name T1799
Test name
Test status
Simulation time 107139864587 ps
CPU time 1809.06 seconds
Started Aug 02 07:51:56 PM PDT 24
Finished Aug 02 08:22:06 PM PDT 24
Peak memory 576108 kb
Host smart-e0f7f401-68ea-4cf5-811d-09ad0645a033
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254845607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_d
evice_slow_rsp.4254845607
Directory /workspace/2.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.2508081883
Short name T1810
Test name
Test status
Simulation time 68311708 ps
CPU time 9.6 seconds
Started Aug 02 07:51:52 PM PDT 24
Finished Aug 02 07:52:02 PM PDT 24
Peak memory 575968 kb
Host smart-f0d31a69-f22d-4225-899d-11ebc7749c37
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508081883 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr
.2508081883
Directory /workspace/2.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_error_random.1542445201
Short name T2280
Test name
Test status
Simulation time 293039854 ps
CPU time 25.45 seconds
Started Aug 02 07:51:52 PM PDT 24
Finished Aug 02 07:52:18 PM PDT 24
Peak memory 575940 kb
Host smart-d9ea44a6-8a0b-4613-974f-4667eaa9ca2f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542445201 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.1542445201
Directory /workspace/2.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_random.2328849691
Short name T1818
Test name
Test status
Simulation time 529066301 ps
CPU time 45.9 seconds
Started Aug 02 07:51:54 PM PDT 24
Finished Aug 02 07:52:40 PM PDT 24
Peak memory 575868 kb
Host smart-a42b5fff-edea-4665-ada7-87cfcfe6aa61
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328849691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random.2328849691
Directory /workspace/2.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_random_large_delays.2855758635
Short name T2206
Test name
Test status
Simulation time 112238095416 ps
CPU time 1095.82 seconds
Started Aug 02 07:51:54 PM PDT 24
Finished Aug 02 08:10:10 PM PDT 24
Peak memory 575908 kb
Host smart-35324fca-e5e6-4916-ad16-833b5a1db3b9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855758635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.2855758635
Directory /workspace/2.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_random_slow_rsp.3730555891
Short name T1696
Test name
Test status
Simulation time 26911731119 ps
CPU time 416.3 seconds
Started Aug 02 07:51:55 PM PDT 24
Finished Aug 02 07:58:51 PM PDT 24
Peak memory 575888 kb
Host smart-a2d61205-5b09-4d43-a677-de3cea02a37b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730555891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.3730555891
Directory /workspace/2.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_random_zero_delays.544196419
Short name T1587
Test name
Test status
Simulation time 540037124 ps
CPU time 41.02 seconds
Started Aug 02 07:51:52 PM PDT 24
Finished Aug 02 07:52:33 PM PDT 24
Peak memory 575748 kb
Host smart-6edf0ae5-8895-47d4-a928-ae5a2ce73f14
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544196419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delay
s.544196419
Directory /workspace/2.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_same_source.564880711
Short name T1820
Test name
Test status
Simulation time 1657436123 ps
CPU time 48.75 seconds
Started Aug 02 07:51:56 PM PDT 24
Finished Aug 02 07:52:45 PM PDT 24
Peak memory 575832 kb
Host smart-e9f1b3a0-b1f7-4406-8107-85ea30a2ef94
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564880711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.564880711
Directory /workspace/2.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_smoke.1487103593
Short name T2925
Test name
Test status
Simulation time 57700178 ps
CPU time 6.44 seconds
Started Aug 02 07:52:03 PM PDT 24
Finished Aug 02 07:52:10 PM PDT 24
Peak memory 574528 kb
Host smart-9ef97a2c-4f1a-40cc-88bc-3c104e71be6e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487103593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.1487103593
Directory /workspace/2.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.3528910081
Short name T1955
Test name
Test status
Simulation time 8496859184 ps
CPU time 96.96 seconds
Started Aug 02 07:51:53 PM PDT 24
Finished Aug 02 07:53:30 PM PDT 24
Peak memory 574596 kb
Host smart-eb1a3235-cbce-447b-a511-7d0cb1eac0fa
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528910081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.3528910081
Directory /workspace/2.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.2912244850
Short name T2544
Test name
Test status
Simulation time 5002174134 ps
CPU time 83.7 seconds
Started Aug 02 07:51:53 PM PDT 24
Finished Aug 02 07:53:17 PM PDT 24
Peak memory 574624 kb
Host smart-558bb6d4-dca0-41fe-b842-28256c0da781
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912244850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.2912244850
Directory /workspace/2.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_smoke_zero_delays.1704446058
Short name T2269
Test name
Test status
Simulation time 44274674 ps
CPU time 6.06 seconds
Started Aug 02 07:51:52 PM PDT 24
Finished Aug 02 07:51:58 PM PDT 24
Peak memory 573816 kb
Host smart-84416a80-ac79-45f1-b919-ca698d5d3411
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704446058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays
.1704446058
Directory /workspace/2.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_stress_all.3217891274
Short name T535
Test name
Test status
Simulation time 4895716721 ps
CPU time 165.43 seconds
Started Aug 02 07:52:01 PM PDT 24
Finished Aug 02 07:54:47 PM PDT 24
Peak memory 576584 kb
Host smart-5660b738-6e40-42a5-bde2-b8a1d25ab449
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217891274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.3217891274
Directory /workspace/2.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.3630174366
Short name T1615
Test name
Test status
Simulation time 350250257 ps
CPU time 36.27 seconds
Started Aug 02 07:52:00 PM PDT 24
Finished Aug 02 07:52:37 PM PDT 24
Peak memory 575792 kb
Host smart-ac8e9e41-8a8c-4dfb-92f5-b719e1fbf948
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630174366 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.3630174366
Directory /workspace/2.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.2896277453
Short name T577
Test name
Test status
Simulation time 7503331236 ps
CPU time 342.23 seconds
Started Aug 02 07:52:01 PM PDT 24
Finished Aug 02 07:57:43 PM PDT 24
Peak memory 575948 kb
Host smart-77bfde53-f898-41c2-9faa-d6b7d2247966
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896277453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_
with_rand_reset.2896277453
Directory /workspace/2.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.1812105004
Short name T1555
Test name
Test status
Simulation time 27518728 ps
CPU time 10.06 seconds
Started Aug 02 07:52:02 PM PDT 24
Finished Aug 02 07:52:12 PM PDT 24
Peak memory 573848 kb
Host smart-ba982ecd-1f2c-42f0-9808-989dd7c4bf11
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812105004 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all
_with_reset_error.1812105004
Directory /workspace/2.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_unmapped_addr.3413806558
Short name T2444
Test name
Test status
Simulation time 272130470 ps
CPU time 30.23 seconds
Started Aug 02 07:51:56 PM PDT 24
Finished Aug 02 07:52:26 PM PDT 24
Peak memory 576084 kb
Host smart-bc2f2a55-ee11-4d2d-877b-495fbcb63aa7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413806558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.3413806558
Directory /workspace/2.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/20.chip_tl_errors.2314314803
Short name T726
Test name
Test status
Simulation time 3451895780 ps
CPU time 184.37 seconds
Started Aug 02 07:56:05 PM PDT 24
Finished Aug 02 07:59:09 PM PDT 24
Peak memory 599000 kb
Host smart-42f5dcfa-98eb-4b8c-bde4-cf94b5ebcb12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314314803 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.chip_tl_errors.2314314803
Directory /workspace/20.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_access_same_device.2194786852
Short name T1712
Test name
Test status
Simulation time 3371066033 ps
CPU time 153.39 seconds
Started Aug 02 07:56:01 PM PDT 24
Finished Aug 02 07:58:35 PM PDT 24
Peak memory 575800 kb
Host smart-935f1d73-601e-4dc5-b649-d0a56d573297
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194786852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device
.2194786852
Directory /workspace/20.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.3851951311
Short name T2738
Test name
Test status
Simulation time 70129515115 ps
CPU time 1242.3 seconds
Started Aug 02 07:55:59 PM PDT 24
Finished Aug 02 08:16:42 PM PDT 24
Peak memory 576768 kb
Host smart-3ef605af-7c89-4712-8720-52bf11ca57bb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851951311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_
device_slow_rsp.3851951311
Directory /workspace/20.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.3695110873
Short name T2313
Test name
Test status
Simulation time 1472245188 ps
CPU time 54.53 seconds
Started Aug 02 07:56:13 PM PDT 24
Finished Aug 02 07:57:08 PM PDT 24
Peak memory 575984 kb
Host smart-60a320d0-ed01-45e5-9f50-6897aa68c020
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695110873 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_add
r.3695110873
Directory /workspace/20.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_error_random.4046444973
Short name T2514
Test name
Test status
Simulation time 1553241950 ps
CPU time 59.37 seconds
Started Aug 02 07:56:14 PM PDT 24
Finished Aug 02 07:57:13 PM PDT 24
Peak memory 575928 kb
Host smart-0485d9a6-8569-4d3e-a7b3-8812c8db8d1d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046444973 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.4046444973
Directory /workspace/20.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_random.3737236549
Short name T2550
Test name
Test status
Simulation time 1500039594 ps
CPU time 48 seconds
Started Aug 02 07:56:04 PM PDT 24
Finished Aug 02 07:56:53 PM PDT 24
Peak memory 575988 kb
Host smart-c7cb223d-ed37-4270-b93c-93949a79b6c8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737236549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random.3737236549
Directory /workspace/20.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_random_large_delays.1719405375
Short name T1754
Test name
Test status
Simulation time 53696375823 ps
CPU time 544.42 seconds
Started Aug 02 07:56:04 PM PDT 24
Finished Aug 02 08:05:09 PM PDT 24
Peak memory 575868 kb
Host smart-6627a9fc-20e3-4341-a0f8-1807604ef2c8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719405375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.1719405375
Directory /workspace/20.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_random_slow_rsp.746162915
Short name T2662
Test name
Test status
Simulation time 13974108568 ps
CPU time 251.66 seconds
Started Aug 02 07:56:04 PM PDT 24
Finished Aug 02 08:00:16 PM PDT 24
Peak memory 576032 kb
Host smart-4dc2342c-3fb4-4cd7-9d8d-a2b724a585d5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746162915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.746162915
Directory /workspace/20.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.1378801060
Short name T537
Test name
Test status
Simulation time 436928978 ps
CPU time 37.61 seconds
Started Aug 02 07:56:03 PM PDT 24
Finished Aug 02 07:56:41 PM PDT 24
Peak memory 576024 kb
Host smart-8d270656-2384-4385-9d47-24a20c8eec2c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378801060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_del
ays.1378801060
Directory /workspace/20.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_same_source.3271141697
Short name T1752
Test name
Test status
Simulation time 301441410 ps
CPU time 26.82 seconds
Started Aug 02 07:56:18 PM PDT 24
Finished Aug 02 07:56:45 PM PDT 24
Peak memory 575848 kb
Host smart-f4353b72-b617-4d8b-8693-76fd3f73ffd2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271141697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.3271141697
Directory /workspace/20.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_smoke.3169058367
Short name T2007
Test name
Test status
Simulation time 212658082 ps
CPU time 8.54 seconds
Started Aug 02 07:55:59 PM PDT 24
Finished Aug 02 07:56:08 PM PDT 24
Peak memory 573880 kb
Host smart-dc7a4210-62fa-4e9e-80a8-f9fc19a461e9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169058367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.3169058367
Directory /workspace/20.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.1686139125
Short name T2765
Test name
Test status
Simulation time 6656784146 ps
CPU time 73.18 seconds
Started Aug 02 07:56:04 PM PDT 24
Finished Aug 02 07:57:17 PM PDT 24
Peak memory 573940 kb
Host smart-d4e33bef-018a-435f-8e9c-90e21fef243b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686139125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.1686139125
Directory /workspace/20.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.2276356961
Short name T1958
Test name
Test status
Simulation time 5194259115 ps
CPU time 84.29 seconds
Started Aug 02 07:56:05 PM PDT 24
Finished Aug 02 07:57:29 PM PDT 24
Peak memory 573856 kb
Host smart-99a86265-7a20-4a13-81be-1dd0b8d04938
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276356961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.2276356961
Directory /workspace/20.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_smoke_zero_delays.2108169284
Short name T1607
Test name
Test status
Simulation time 46102385 ps
CPU time 6.19 seconds
Started Aug 02 07:56:00 PM PDT 24
Finished Aug 02 07:56:06 PM PDT 24
Peak memory 573916 kb
Host smart-25257051-0a3f-4b3a-a2b3-94af377e6ac9
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108169284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delay
s.2108169284
Directory /workspace/20.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_stress_all.1644766847
Short name T533
Test name
Test status
Simulation time 10954296570 ps
CPU time 374.47 seconds
Started Aug 02 07:56:14 PM PDT 24
Finished Aug 02 08:02:29 PM PDT 24
Peak memory 576836 kb
Host smart-9a79a414-6db2-43fc-a51e-cee9971e0c52
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644766847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.1644766847
Directory /workspace/20.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.1446996291
Short name T1873
Test name
Test status
Simulation time 4163282206 ps
CPU time 312.36 seconds
Started Aug 02 07:56:14 PM PDT 24
Finished Aug 02 08:01:27 PM PDT 24
Peak memory 576136 kb
Host smart-1dea0897-418e-4068-9cf9-1a880bcb102b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446996291 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.1446996291
Directory /workspace/20.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.1279247251
Short name T2288
Test name
Test status
Simulation time 617336031 ps
CPU time 198.66 seconds
Started Aug 02 07:56:18 PM PDT 24
Finished Aug 02 07:59:37 PM PDT 24
Peak memory 575888 kb
Host smart-167a6450-d0ab-4798-8b77-3cf7cb5e879e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279247251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all
_with_rand_reset.1279247251
Directory /workspace/20.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.4282812983
Short name T2203
Test name
Test status
Simulation time 22371031 ps
CPU time 5.71 seconds
Started Aug 02 07:56:15 PM PDT 24
Finished Aug 02 07:56:21 PM PDT 24
Peak memory 574528 kb
Host smart-cdc3a10e-4910-46b1-aeba-2a5749b7f0c8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282812983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.4282812983
Directory /workspace/20.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/21.chip_tl_errors.1972962688
Short name T570
Test name
Test status
Simulation time 3002006975 ps
CPU time 199.74 seconds
Started Aug 02 07:56:15 PM PDT 24
Finished Aug 02 07:59:35 PM PDT 24
Peak memory 603724 kb
Host smart-44b0e548-3d9d-4fab-bf45-7d86dbc10f4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972962688 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.chip_tl_errors.1972962688
Directory /workspace/21.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_access_same_device.3847660277
Short name T1935
Test name
Test status
Simulation time 2582380238 ps
CPU time 110.91 seconds
Started Aug 02 07:56:25 PM PDT 24
Finished Aug 02 07:58:16 PM PDT 24
Peak memory 575940 kb
Host smart-25f26c19-0652-4cf0-99a9-e3b0475f5245
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847660277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device
.3847660277
Directory /workspace/21.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.3711327807
Short name T843
Test name
Test status
Simulation time 51159763587 ps
CPU time 862.87 seconds
Started Aug 02 07:56:30 PM PDT 24
Finished Aug 02 08:10:53 PM PDT 24
Peak memory 575988 kb
Host smart-ef2042c4-3d3e-4787-9f7c-a79098641c5c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711327807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_
device_slow_rsp.3711327807
Directory /workspace/21.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.686500419
Short name T2908
Test name
Test status
Simulation time 288021939 ps
CPU time 27.35 seconds
Started Aug 02 07:56:24 PM PDT 24
Finished Aug 02 07:56:51 PM PDT 24
Peak memory 575964 kb
Host smart-6ee90e96-71f2-41d2-8457-5a972cbd25d3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686500419 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr
.686500419
Directory /workspace/21.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_error_random.4037393595
Short name T733
Test name
Test status
Simulation time 57688826 ps
CPU time 8.39 seconds
Started Aug 02 07:56:24 PM PDT 24
Finished Aug 02 07:56:33 PM PDT 24
Peak memory 575948 kb
Host smart-283250f9-910a-4cc2-936c-6217830cd046
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037393595 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.4037393595
Directory /workspace/21.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_random.3755548376
Short name T2562
Test name
Test status
Simulation time 367141277 ps
CPU time 34.25 seconds
Started Aug 02 07:56:22 PM PDT 24
Finished Aug 02 07:56:57 PM PDT 24
Peak memory 575888 kb
Host smart-8c015b2f-e41a-40a8-b2f5-36cf1f4437c3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755548376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random.3755548376
Directory /workspace/21.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_random_large_delays.1655888963
Short name T2262
Test name
Test status
Simulation time 77375005389 ps
CPU time 843.49 seconds
Started Aug 02 07:56:24 PM PDT 24
Finished Aug 02 08:10:28 PM PDT 24
Peak memory 575904 kb
Host smart-b6e68063-bf79-45d3-8518-6f820a5dde67
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655888963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.1655888963
Directory /workspace/21.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_random_slow_rsp.4013174065
Short name T2538
Test name
Test status
Simulation time 10360391191 ps
CPU time 180.46 seconds
Started Aug 02 07:56:24 PM PDT 24
Finished Aug 02 07:59:24 PM PDT 24
Peak memory 576732 kb
Host smart-e184ec45-7698-4712-832d-efa297092112
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013174065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.4013174065
Directory /workspace/21.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.2550018844
Short name T2753
Test name
Test status
Simulation time 325762724 ps
CPU time 28.78 seconds
Started Aug 02 07:56:28 PM PDT 24
Finished Aug 02 07:56:56 PM PDT 24
Peak memory 575880 kb
Host smart-0360b707-b145-45a8-a040-082103592452
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550018844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_del
ays.2550018844
Directory /workspace/21.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_same_source.3691725376
Short name T2573
Test name
Test status
Simulation time 347375009 ps
CPU time 26.05 seconds
Started Aug 02 07:56:23 PM PDT 24
Finished Aug 02 07:56:49 PM PDT 24
Peak memory 575764 kb
Host smart-6f87d876-6f9b-406e-b3b0-825568e15cb2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691725376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.3691725376
Directory /workspace/21.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_smoke.2668629194
Short name T2101
Test name
Test status
Simulation time 48181380 ps
CPU time 6.6 seconds
Started Aug 02 07:56:13 PM PDT 24
Finished Aug 02 07:56:20 PM PDT 24
Peak memory 573848 kb
Host smart-74094a4a-2bdb-437c-add4-624381fa7e20
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668629194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.2668629194
Directory /workspace/21.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_smoke_large_delays.2009837091
Short name T2491
Test name
Test status
Simulation time 8282223824 ps
CPU time 85.43 seconds
Started Aug 02 07:56:23 PM PDT 24
Finished Aug 02 07:57:49 PM PDT 24
Peak memory 573960 kb
Host smart-71ca77ed-9bea-44a6-88d0-cb4eb331d9fb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009837091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.2009837091
Directory /workspace/21.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.4208608518
Short name T1804
Test name
Test status
Simulation time 3099350521 ps
CPU time 53.73 seconds
Started Aug 02 07:56:25 PM PDT 24
Finished Aug 02 07:57:18 PM PDT 24
Peak memory 573900 kb
Host smart-46ea7726-1321-457a-b127-4b99155510ce
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208608518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.4208608518
Directory /workspace/21.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.4177990036
Short name T2170
Test name
Test status
Simulation time 46529788 ps
CPU time 6.27 seconds
Started Aug 02 07:56:24 PM PDT 24
Finished Aug 02 07:56:31 PM PDT 24
Peak memory 573744 kb
Host smart-85428bbc-0678-4684-80c4-ccca5fe7d767
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177990036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delay
s.4177990036
Directory /workspace/21.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_stress_all.4206705612
Short name T2471
Test name
Test status
Simulation time 1395303638 ps
CPU time 99.04 seconds
Started Aug 02 07:56:24 PM PDT 24
Finished Aug 02 07:58:03 PM PDT 24
Peak memory 575892 kb
Host smart-9e101ed3-5624-44f0-a928-0a93ca4da182
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206705612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.4206705612
Directory /workspace/21.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.1776282537
Short name T2211
Test name
Test status
Simulation time 1978942100 ps
CPU time 149.93 seconds
Started Aug 02 07:56:28 PM PDT 24
Finished Aug 02 07:58:58 PM PDT 24
Peak memory 575988 kb
Host smart-afcac2de-e9dd-4319-8153-fec5654adbe0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776282537 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.1776282537
Directory /workspace/21.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.617957868
Short name T2920
Test name
Test status
Simulation time 200337323 ps
CPU time 116.01 seconds
Started Aug 02 07:56:26 PM PDT 24
Finished Aug 02 07:58:22 PM PDT 24
Peak memory 576536 kb
Host smart-74001810-92fa-48c8-8654-96db54e78efc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617957868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_
with_rand_reset.617957868
Directory /workspace/21.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.3037276892
Short name T912
Test name
Test status
Simulation time 2001314530 ps
CPU time 391.54 seconds
Started Aug 02 07:56:26 PM PDT 24
Finished Aug 02 08:02:58 PM PDT 24
Peak memory 576928 kb
Host smart-0dc224f6-0179-4f58-8b20-0346aadb8dcd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037276892 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_al
l_with_reset_error.3037276892
Directory /workspace/21.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.915114072
Short name T485
Test name
Test status
Simulation time 221143254 ps
CPU time 27.1 seconds
Started Aug 02 07:56:26 PM PDT 24
Finished Aug 02 07:56:54 PM PDT 24
Peak memory 575932 kb
Host smart-73c002e7-83b4-4bc4-80f9-34c60a48b061
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915114072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.915114072
Directory /workspace/21.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_access_same_device.3777508704
Short name T2179
Test name
Test status
Simulation time 733999595 ps
CPU time 35.43 seconds
Started Aug 02 07:56:36 PM PDT 24
Finished Aug 02 07:57:12 PM PDT 24
Peak memory 575816 kb
Host smart-0a1af9be-e11c-4a4f-bae3-5f6b61cd1588
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777508704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device
.3777508704
Directory /workspace/22.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.364300484
Short name T2589
Test name
Test status
Simulation time 146678026 ps
CPU time 18.74 seconds
Started Aug 02 07:56:35 PM PDT 24
Finished Aug 02 07:56:54 PM PDT 24
Peak memory 576004 kb
Host smart-216c88f7-5551-4ccd-94cf-44d73c5d38d6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364300484 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr
.364300484
Directory /workspace/22.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_error_random.3728797429
Short name T2642
Test name
Test status
Simulation time 337062214 ps
CPU time 32.27 seconds
Started Aug 02 07:56:37 PM PDT 24
Finished Aug 02 07:57:09 PM PDT 24
Peak memory 575888 kb
Host smart-73b96b13-3e65-4d4a-bdc1-13f54bcf3013
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728797429 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.3728797429
Directory /workspace/22.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_random.3619052220
Short name T2886
Test name
Test status
Simulation time 356960831 ps
CPU time 25.9 seconds
Started Aug 02 07:56:34 PM PDT 24
Finished Aug 02 07:57:00 PM PDT 24
Peak memory 575900 kb
Host smart-1c4e21c6-ab6c-4492-8860-f12c2ff990d0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619052220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random.3619052220
Directory /workspace/22.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_random_large_delays.3302782243
Short name T639
Test name
Test status
Simulation time 66527294366 ps
CPU time 684.82 seconds
Started Aug 02 07:56:35 PM PDT 24
Finished Aug 02 08:08:00 PM PDT 24
Peak memory 575848 kb
Host smart-f9ad6289-170d-4ab1-a83f-d74f393577d7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302782243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.3302782243
Directory /workspace/22.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_random_slow_rsp.1823290777
Short name T2274
Test name
Test status
Simulation time 57188581368 ps
CPU time 991.67 seconds
Started Aug 02 07:56:38 PM PDT 24
Finished Aug 02 08:13:10 PM PDT 24
Peak memory 575916 kb
Host smart-f37218cb-5c8f-410f-8002-5e4b64f1f3b2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823290777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.1823290777
Directory /workspace/22.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.292791309
Short name T2508
Test name
Test status
Simulation time 570057932 ps
CPU time 49.84 seconds
Started Aug 02 07:56:38 PM PDT 24
Finished Aug 02 07:57:28 PM PDT 24
Peak memory 575928 kb
Host smart-4fc4567e-5961-4d56-94f6-e45584512f7b
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292791309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_dela
ys.292791309
Directory /workspace/22.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_same_source.3210706108
Short name T2084
Test name
Test status
Simulation time 2125166873 ps
CPU time 63.78 seconds
Started Aug 02 07:56:34 PM PDT 24
Finished Aug 02 07:57:38 PM PDT 24
Peak memory 575900 kb
Host smart-d5cd6e75-60fb-448c-b516-7ffb4f12939a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210706108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.3210706108
Directory /workspace/22.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_smoke.1048588444
Short name T2860
Test name
Test status
Simulation time 50328144 ps
CPU time 6.32 seconds
Started Aug 02 07:56:29 PM PDT 24
Finished Aug 02 07:56:35 PM PDT 24
Peak memory 573792 kb
Host smart-2e43adcb-87ad-40ad-b6db-b092c09cacaa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048588444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.1048588444
Directory /workspace/22.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_smoke_large_delays.2450586841
Short name T1458
Test name
Test status
Simulation time 7855307177 ps
CPU time 82.14 seconds
Started Aug 02 07:56:25 PM PDT 24
Finished Aug 02 07:57:47 PM PDT 24
Peak memory 573920 kb
Host smart-5c3c3f9a-38f7-48e7-85df-e6cea0a4dc4d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450586841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.2450586841
Directory /workspace/22.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.2623841042
Short name T1816
Test name
Test status
Simulation time 4475682592 ps
CPU time 77.02 seconds
Started Aug 02 07:56:24 PM PDT 24
Finished Aug 02 07:57:41 PM PDT 24
Peak memory 574572 kb
Host smart-7eb9d76c-512c-48d6-822d-f4c1cc9663e6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623841042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.2623841042
Directory /workspace/22.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_smoke_zero_delays.616707859
Short name T2679
Test name
Test status
Simulation time 52391915 ps
CPU time 6.42 seconds
Started Aug 02 07:56:30 PM PDT 24
Finished Aug 02 07:56:36 PM PDT 24
Peak memory 574436 kb
Host smart-21b1f79f-14b8-46fb-a9da-71b29dbac45e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616707859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays
.616707859
Directory /workspace/22.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_stress_all.2672440403
Short name T2760
Test name
Test status
Simulation time 11149043278 ps
CPU time 387.12 seconds
Started Aug 02 07:56:38 PM PDT 24
Finished Aug 02 08:03:05 PM PDT 24
Peak memory 575996 kb
Host smart-14220957-6f86-4509-9e39-0f552be6f72c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672440403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.2672440403
Directory /workspace/22.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.1414426360
Short name T1892
Test name
Test status
Simulation time 14125711496 ps
CPU time 438.34 seconds
Started Aug 02 07:56:36 PM PDT 24
Finished Aug 02 08:03:54 PM PDT 24
Peak memory 576164 kb
Host smart-faf398ae-4b64-4758-ac6e-761ed74f2967
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414426360 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.1414426360
Directory /workspace/22.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.2933838284
Short name T1521
Test name
Test status
Simulation time 83955949 ps
CPU time 28.23 seconds
Started Aug 02 07:56:38 PM PDT 24
Finished Aug 02 07:57:06 PM PDT 24
Peak memory 574652 kb
Host smart-cdfa67b3-1e2d-4be2-9f6b-fe41e8ebd070
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933838284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all
_with_rand_reset.2933838284
Directory /workspace/22.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_unmapped_addr.2879644426
Short name T2521
Test name
Test status
Simulation time 337698063 ps
CPU time 41.98 seconds
Started Aug 02 07:56:35 PM PDT 24
Finished Aug 02 07:57:17 PM PDT 24
Peak memory 575792 kb
Host smart-cf40e6d7-1677-42f0-88f6-ccbc4a83d2aa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879644426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.2879644426
Directory /workspace/22.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/23.chip_tl_errors.1694766474
Short name T2712
Test name
Test status
Simulation time 3711004654 ps
CPU time 284.56 seconds
Started Aug 02 07:56:35 PM PDT 24
Finished Aug 02 08:01:19 PM PDT 24
Peak memory 603796 kb
Host smart-9fb11bd4-409a-416b-940a-a68ab0409762
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694766474 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.chip_tl_errors.1694766474
Directory /workspace/23.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_access_same_device.2289774253
Short name T547
Test name
Test status
Simulation time 2598072641 ps
CPU time 87.81 seconds
Started Aug 02 07:56:46 PM PDT 24
Finished Aug 02 07:58:14 PM PDT 24
Peak memory 576044 kb
Host smart-dd3e7f34-02dc-400c-b687-2230e4f12eb8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289774253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device
.2289774253
Directory /workspace/23.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.2277276716
Short name T2178
Test name
Test status
Simulation time 72713172947 ps
CPU time 1266.34 seconds
Started Aug 02 07:56:45 PM PDT 24
Finished Aug 02 08:17:52 PM PDT 24
Peak memory 575856 kb
Host smart-05ebb9c6-e91b-49ae-b41f-39e183027393
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277276716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_
device_slow_rsp.2277276716
Directory /workspace/23.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.384014012
Short name T2346
Test name
Test status
Simulation time 208662193 ps
CPU time 21.03 seconds
Started Aug 02 07:56:48 PM PDT 24
Finished Aug 02 07:57:09 PM PDT 24
Peak memory 575840 kb
Host smart-d7edc254-32b2-4fb8-9c3f-34e3bc19ea2e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384014012 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr
.384014012
Directory /workspace/23.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_error_random.1999823173
Short name T2547
Test name
Test status
Simulation time 124505640 ps
CPU time 7.42 seconds
Started Aug 02 07:56:48 PM PDT 24
Finished Aug 02 07:56:56 PM PDT 24
Peak memory 573968 kb
Host smart-c0ab4e47-58eb-43e6-ab59-e051b2649673
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999823173 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.1999823173
Directory /workspace/23.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_random.1463328336
Short name T1857
Test name
Test status
Simulation time 452800849 ps
CPU time 41.37 seconds
Started Aug 02 07:56:38 PM PDT 24
Finished Aug 02 07:57:19 PM PDT 24
Peak memory 575772 kb
Host smart-0e56c687-9aee-43a1-8855-6f0ed1ef17c8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463328336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random.1463328336
Directory /workspace/23.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_random_large_delays.2492520432
Short name T2098
Test name
Test status
Simulation time 35903990322 ps
CPU time 379.61 seconds
Started Aug 02 07:56:48 PM PDT 24
Finished Aug 02 08:03:08 PM PDT 24
Peak memory 576800 kb
Host smart-8920b301-46e3-44fa-b9d9-e2d55ed15f49
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492520432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.2492520432
Directory /workspace/23.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.1621438269
Short name T2242
Test name
Test status
Simulation time 4490051111 ps
CPU time 74.06 seconds
Started Aug 02 07:56:46 PM PDT 24
Finished Aug 02 07:58:00 PM PDT 24
Peak memory 573936 kb
Host smart-ee0ccaf9-1f73-4c1f-9546-201f45b4c970
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621438269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.1621438269
Directory /workspace/23.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_random_zero_delays.2455518252
Short name T2752
Test name
Test status
Simulation time 158241675 ps
CPU time 17.59 seconds
Started Aug 02 07:56:35 PM PDT 24
Finished Aug 02 07:56:53 PM PDT 24
Peak memory 575824 kb
Host smart-b1a05764-e11f-4f71-98f0-d97f0622ec83
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455518252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_del
ays.2455518252
Directory /workspace/23.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_same_source.2712879880
Short name T2933
Test name
Test status
Simulation time 420791546 ps
CPU time 33.49 seconds
Started Aug 02 07:56:46 PM PDT 24
Finished Aug 02 07:57:19 PM PDT 24
Peak memory 575908 kb
Host smart-ea381891-31b2-4cb1-a1bb-29406cd26c41
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712879880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.2712879880
Directory /workspace/23.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_smoke.615487422
Short name T1436
Test name
Test status
Simulation time 38196810 ps
CPU time 5.97 seconds
Started Aug 02 07:56:37 PM PDT 24
Finished Aug 02 07:56:43 PM PDT 24
Peak memory 574516 kb
Host smart-2676e7f6-36c7-4baf-bb09-5023248a839b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615487422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.615487422
Directory /workspace/23.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_smoke_large_delays.3381236704
Short name T1909
Test name
Test status
Simulation time 8964072756 ps
CPU time 93.17 seconds
Started Aug 02 07:56:39 PM PDT 24
Finished Aug 02 07:58:12 PM PDT 24
Peak memory 573940 kb
Host smart-13f3f345-2110-4985-8748-b32322127ddb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381236704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.3381236704
Directory /workspace/23.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.1819145315
Short name T1631
Test name
Test status
Simulation time 4593574535 ps
CPU time 76.06 seconds
Started Aug 02 07:56:38 PM PDT 24
Finished Aug 02 07:57:54 PM PDT 24
Peak memory 573940 kb
Host smart-56bfd382-4674-48ca-8486-f60d221c0f92
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819145315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.1819145315
Directory /workspace/23.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_smoke_zero_delays.2346789248
Short name T2196
Test name
Test status
Simulation time 55663158 ps
CPU time 6.83 seconds
Started Aug 02 07:56:38 PM PDT 24
Finished Aug 02 07:56:45 PM PDT 24
Peak memory 573748 kb
Host smart-76301858-cb82-4893-83ed-b842b288883e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346789248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delay
s.2346789248
Directory /workspace/23.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.3549893261
Short name T1766
Test name
Test status
Simulation time 3583821572 ps
CPU time 129.55 seconds
Started Aug 02 07:56:45 PM PDT 24
Finished Aug 02 07:58:55 PM PDT 24
Peak memory 576208 kb
Host smart-1633fd38-0e9c-499d-9745-ce328fd716ce
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549893261 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.3549893261
Directory /workspace/23.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.2583379158
Short name T2705
Test name
Test status
Simulation time 8257460909 ps
CPU time 443.74 seconds
Started Aug 02 07:56:46 PM PDT 24
Finished Aug 02 08:04:10 PM PDT 24
Peak memory 576076 kb
Host smart-2d53e04c-6097-402f-b7e3-c6cfa2c78763
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583379158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all
_with_rand_reset.2583379158
Directory /workspace/23.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.3612168942
Short name T2122
Test name
Test status
Simulation time 583028705 ps
CPU time 113.42 seconds
Started Aug 02 07:56:47 PM PDT 24
Finished Aug 02 07:58:41 PM PDT 24
Peak memory 576012 kb
Host smart-254cf23d-a22c-47aa-9f08-606093f41ae3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612168942 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_al
l_with_reset_error.3612168942
Directory /workspace/23.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.2612574928
Short name T2123
Test name
Test status
Simulation time 216627461 ps
CPU time 12.05 seconds
Started Aug 02 07:56:48 PM PDT 24
Finished Aug 02 07:57:00 PM PDT 24
Peak memory 575960 kb
Host smart-a63c71f5-6c47-4eb7-9020-4c9681d75592
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612574928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.2612574928
Directory /workspace/23.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/24.chip_tl_errors.1103709161
Short name T564
Test name
Test status
Simulation time 3981806900 ps
CPU time 164.36 seconds
Started Aug 02 07:56:48 PM PDT 24
Finished Aug 02 07:59:32 PM PDT 24
Peak memory 599588 kb
Host smart-bcf397c9-7804-4e9f-919f-1bb5bd8f2090
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103709161 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.chip_tl_errors.1103709161
Directory /workspace/24.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_access_same_device.140547514
Short name T833
Test name
Test status
Simulation time 920234911 ps
CPU time 34.61 seconds
Started Aug 02 07:57:00 PM PDT 24
Finished Aug 02 07:57:35 PM PDT 24
Peak memory 575908 kb
Host smart-8f7d89fe-5f44-46f7-b147-8ba01f8af1ef
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140547514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.
140547514
Directory /workspace/24.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.1788528186
Short name T861
Test name
Test status
Simulation time 63618242281 ps
CPU time 1110.22 seconds
Started Aug 02 07:56:58 PM PDT 24
Finished Aug 02 08:15:28 PM PDT 24
Peak memory 576040 kb
Host smart-8ffbb879-a8c0-497a-ac58-c56d8b19a529
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788528186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_
device_slow_rsp.1788528186
Directory /workspace/24.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.56199078
Short name T1928
Test name
Test status
Simulation time 402950972 ps
CPU time 16.53 seconds
Started Aug 02 07:56:57 PM PDT 24
Finished Aug 02 07:57:13 PM PDT 24
Peak memory 575976 kb
Host smart-36da1dfb-053c-4e4f-8123-97feffdc520c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56199078 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.56199078
Directory /workspace/24.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_error_random.2535940259
Short name T1411
Test name
Test status
Simulation time 1559932500 ps
CPU time 54.31 seconds
Started Aug 02 07:56:56 PM PDT 24
Finished Aug 02 07:57:51 PM PDT 24
Peak memory 575708 kb
Host smart-74f8fa71-6b06-43ea-8910-2ab8a43fe8bd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535940259 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.2535940259
Directory /workspace/24.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_random.3014329248
Short name T658
Test name
Test status
Simulation time 1036849653 ps
CPU time 37.99 seconds
Started Aug 02 07:56:57 PM PDT 24
Finished Aug 02 07:57:35 PM PDT 24
Peak memory 575784 kb
Host smart-59d15581-6d26-4e4e-ba45-ffdb28df0e4b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014329248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random.3014329248
Directory /workspace/24.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.580068930
Short name T1706
Test name
Test status
Simulation time 59573042007 ps
CPU time 591.55 seconds
Started Aug 02 07:56:57 PM PDT 24
Finished Aug 02 08:06:49 PM PDT 24
Peak memory 576064 kb
Host smart-23450c38-495b-4a69-ad11-eed6b65985dd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580068930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.580068930
Directory /workspace/24.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_random_slow_rsp.2433094745
Short name T579
Test name
Test status
Simulation time 9673479810 ps
CPU time 149.75 seconds
Started Aug 02 07:57:00 PM PDT 24
Finished Aug 02 07:59:30 PM PDT 24
Peak memory 575960 kb
Host smart-884f6b8a-3665-4c7b-9260-4e242194863b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433094745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.2433094745
Directory /workspace/24.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_random_zero_delays.1069703023
Short name T2626
Test name
Test status
Simulation time 404709582 ps
CPU time 30.54 seconds
Started Aug 02 07:56:56 PM PDT 24
Finished Aug 02 07:57:26 PM PDT 24
Peak memory 575788 kb
Host smart-738002b1-6c75-4683-b08d-e704d29b9d94
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069703023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_del
ays.1069703023
Directory /workspace/24.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_same_source.3480367635
Short name T2373
Test name
Test status
Simulation time 273839908 ps
CPU time 18.49 seconds
Started Aug 02 07:56:58 PM PDT 24
Finished Aug 02 07:57:17 PM PDT 24
Peak memory 575832 kb
Host smart-696dd6a5-a75a-46a0-aeac-49bd158a7d7b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480367635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.3480367635
Directory /workspace/24.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_smoke.3913887880
Short name T2132
Test name
Test status
Simulation time 38919365 ps
CPU time 6.19 seconds
Started Aug 02 07:56:47 PM PDT 24
Finished Aug 02 07:56:53 PM PDT 24
Peak memory 573868 kb
Host smart-8acaa31d-ca6f-468a-8493-f6c7491203a9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913887880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.3913887880
Directory /workspace/24.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.242637000
Short name T2472
Test name
Test status
Simulation time 8684077533 ps
CPU time 88.54 seconds
Started Aug 02 07:56:49 PM PDT 24
Finished Aug 02 07:58:18 PM PDT 24
Peak memory 574032 kb
Host smart-95e49db8-44fe-45dc-8c18-b6c431242f1f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242637000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.242637000
Directory /workspace/24.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.1162115780
Short name T2039
Test name
Test status
Simulation time 5703732201 ps
CPU time 101.77 seconds
Started Aug 02 07:56:46 PM PDT 24
Finished Aug 02 07:58:28 PM PDT 24
Peak memory 573948 kb
Host smart-3a2770f2-baa5-4fdb-96b9-11b86eed3174
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162115780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.1162115780
Directory /workspace/24.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_smoke_zero_delays.152105863
Short name T685
Test name
Test status
Simulation time 46209643 ps
CPU time 5.95 seconds
Started Aug 02 07:56:48 PM PDT 24
Finished Aug 02 07:56:54 PM PDT 24
Peak memory 574472 kb
Host smart-b3d94509-5262-4f0e-ab9e-17b847a58247
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152105863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays
.152105863
Directory /workspace/24.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_stress_all.3284784785
Short name T2639
Test name
Test status
Simulation time 11239213779 ps
CPU time 359.45 seconds
Started Aug 02 07:56:58 PM PDT 24
Finished Aug 02 08:02:58 PM PDT 24
Peak memory 576816 kb
Host smart-4bb5f8d2-7feb-4f22-be95-bf6119ec745f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284784785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.3284784785
Directory /workspace/24.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.3206627111
Short name T1531
Test name
Test status
Simulation time 3638837348 ps
CPU time 132.65 seconds
Started Aug 02 07:57:00 PM PDT 24
Finished Aug 02 07:59:12 PM PDT 24
Peak memory 576028 kb
Host smart-3a75323a-c371-4e6b-afae-cc3540928212
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206627111 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.3206627111
Directory /workspace/24.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.4022649434
Short name T2411
Test name
Test status
Simulation time 596733967 ps
CPU time 208 seconds
Started Aug 02 07:57:00 PM PDT 24
Finished Aug 02 08:00:28 PM PDT 24
Peak memory 576720 kb
Host smart-57832719-e268-4c56-bd89-7fc0ffc6a3cf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022649434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all
_with_rand_reset.4022649434
Directory /workspace/24.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.895865045
Short name T883
Test name
Test status
Simulation time 457738029 ps
CPU time 140.86 seconds
Started Aug 02 07:56:57 PM PDT 24
Finished Aug 02 07:59:18 PM PDT 24
Peak memory 575988 kb
Host smart-e9862924-0ff4-469e-916a-7a585b825f8d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895865045 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all
_with_reset_error.895865045
Directory /workspace/24.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_unmapped_addr.2057192454
Short name T2730
Test name
Test status
Simulation time 1373887998 ps
CPU time 57.27 seconds
Started Aug 02 07:56:58 PM PDT 24
Finished Aug 02 07:57:55 PM PDT 24
Peak memory 575944 kb
Host smart-2dc8add8-3605-4ec7-b273-8aa34b7c710f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057192454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.2057192454
Directory /workspace/24.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_access_same_device.3536997202
Short name T2885
Test name
Test status
Simulation time 2436416276 ps
CPU time 112.01 seconds
Started Aug 02 07:57:10 PM PDT 24
Finished Aug 02 07:59:02 PM PDT 24
Peak memory 575988 kb
Host smart-3f94f3fb-36fd-47dc-8368-07dd5b7c248d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536997202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device
.3536997202
Directory /workspace/25.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.957241673
Short name T2302
Test name
Test status
Simulation time 133557313 ps
CPU time 17.53 seconds
Started Aug 02 07:57:09 PM PDT 24
Finished Aug 02 07:57:26 PM PDT 24
Peak memory 576000 kb
Host smart-ddd48d5a-542a-41ee-bce0-34be7811f12e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957241673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr
.957241673
Directory /workspace/25.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_error_random.3452920389
Short name T1668
Test name
Test status
Simulation time 473839495 ps
CPU time 42.07 seconds
Started Aug 02 07:57:10 PM PDT 24
Finished Aug 02 07:57:52 PM PDT 24
Peak memory 575964 kb
Host smart-c30cfe24-4fb5-4ab6-b009-dfb5a2dec28f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452920389 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.3452920389
Directory /workspace/25.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_random.1136009544
Short name T1767
Test name
Test status
Simulation time 1405392419 ps
CPU time 52.56 seconds
Started Aug 02 07:57:09 PM PDT 24
Finished Aug 02 07:58:02 PM PDT 24
Peak memory 575720 kb
Host smart-186192b9-9873-42b1-b1fc-6f3503980614
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136009544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random.1136009544
Directory /workspace/25.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_random_large_delays.2002051528
Short name T1421
Test name
Test status
Simulation time 7805320617 ps
CPU time 81.36 seconds
Started Aug 02 07:57:07 PM PDT 24
Finished Aug 02 07:58:29 PM PDT 24
Peak memory 573948 kb
Host smart-74d8a74c-08c2-4442-b563-6900c9d872ec
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002051528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.2002051528
Directory /workspace/25.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_random_slow_rsp.134526050
Short name T2355
Test name
Test status
Simulation time 55192727142 ps
CPU time 877.71 seconds
Started Aug 02 07:57:10 PM PDT 24
Finished Aug 02 08:11:48 PM PDT 24
Peak memory 575972 kb
Host smart-c0067ad1-86ce-4a5f-95d3-a6e61a26a775
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134526050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.134526050
Directory /workspace/25.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_random_zero_delays.504936299
Short name T2027
Test name
Test status
Simulation time 322004555 ps
CPU time 32.38 seconds
Started Aug 02 07:57:10 PM PDT 24
Finished Aug 02 07:57:42 PM PDT 24
Peak memory 576020 kb
Host smart-ad5ec0cf-21a9-4d4d-8058-a880d204a003
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504936299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_dela
ys.504936299
Directory /workspace/25.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_same_source.587948805
Short name T1999
Test name
Test status
Simulation time 2569229297 ps
CPU time 75.27 seconds
Started Aug 02 07:57:07 PM PDT 24
Finished Aug 02 07:58:22 PM PDT 24
Peak memory 575896 kb
Host smart-9bfe60d8-d63b-4712-b1fa-6be93b1b6ec9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587948805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.587948805
Directory /workspace/25.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_smoke.2044269808
Short name T2322
Test name
Test status
Simulation time 47425771 ps
CPU time 6.42 seconds
Started Aug 02 07:56:57 PM PDT 24
Finished Aug 02 07:57:04 PM PDT 24
Peak memory 574488 kb
Host smart-7758696c-81ea-4ce8-848a-b99f46e5168c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044269808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.2044269808
Directory /workspace/25.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_smoke_large_delays.9936502
Short name T2584
Test name
Test status
Simulation time 9285137690 ps
CPU time 99.72 seconds
Started Aug 02 07:57:08 PM PDT 24
Finished Aug 02 07:58:48 PM PDT 24
Peak memory 573940 kb
Host smart-a08e04f0-4f5c-4ee6-922b-33f87583bdb0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9936502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.9936502
Directory /workspace/25.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.2610666700
Short name T1635
Test name
Test status
Simulation time 5301441064 ps
CPU time 91.12 seconds
Started Aug 02 07:57:08 PM PDT 24
Finished Aug 02 07:58:39 PM PDT 24
Peak memory 574592 kb
Host smart-9bad45d2-caf7-4e3f-ab0a-2db9979601ca
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610666700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.2610666700
Directory /workspace/25.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_smoke_zero_delays.2163736726
Short name T635
Test name
Test status
Simulation time 50520862 ps
CPU time 6.34 seconds
Started Aug 02 07:57:12 PM PDT 24
Finished Aug 02 07:57:18 PM PDT 24
Peak memory 573844 kb
Host smart-87833e1d-477d-41f1-b7c3-fe04467d1637
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163736726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delay
s.2163736726
Directory /workspace/25.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_stress_all.3974719125
Short name T2353
Test name
Test status
Simulation time 7120245126 ps
CPU time 298.96 seconds
Started Aug 02 07:57:11 PM PDT 24
Finished Aug 02 08:02:10 PM PDT 24
Peak memory 576816 kb
Host smart-30fe7e9d-c86e-470e-9fcb-d99f6293623a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974719125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.3974719125
Directory /workspace/25.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.1344265560
Short name T2932
Test name
Test status
Simulation time 196784117 ps
CPU time 17.05 seconds
Started Aug 02 07:57:08 PM PDT 24
Finished Aug 02 07:57:25 PM PDT 24
Peak memory 575732 kb
Host smart-c9999162-c860-453a-82c5-2ce147e710f7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344265560 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.1344265560
Directory /workspace/25.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.2248984707
Short name T2881
Test name
Test status
Simulation time 1770225778 ps
CPU time 74.62 seconds
Started Aug 02 07:57:09 PM PDT 24
Finished Aug 02 07:58:24 PM PDT 24
Peak memory 576516 kb
Host smart-4237c862-d089-4efb-99bc-86d8370c32d2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248984707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all
_with_rand_reset.2248984707
Directory /workspace/25.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.1577336764
Short name T906
Test name
Test status
Simulation time 4052376152 ps
CPU time 359.35 seconds
Started Aug 02 07:57:07 PM PDT 24
Finished Aug 02 08:03:07 PM PDT 24
Peak memory 576808 kb
Host smart-1b6cb5eb-cd12-40c4-b71a-8c00641c1052
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577336764 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_al
l_with_reset_error.1577336764
Directory /workspace/25.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_unmapped_addr.2031595693
Short name T255
Test name
Test status
Simulation time 282252121 ps
CPU time 33.73 seconds
Started Aug 02 07:57:11 PM PDT 24
Finished Aug 02 07:57:44 PM PDT 24
Peak memory 575856 kb
Host smart-10024679-ef81-4c43-b26f-fe68bebc7492
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031595693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.2031595693
Directory /workspace/25.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_access_same_device.330797994
Short name T2097
Test name
Test status
Simulation time 106553956 ps
CPU time 9.5 seconds
Started Aug 02 07:57:29 PM PDT 24
Finished Aug 02 07:57:38 PM PDT 24
Peak memory 574540 kb
Host smart-74e63d53-54a7-4186-9299-a77ada574e8f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330797994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.
330797994
Directory /workspace/26.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.486198005
Short name T1640
Test name
Test status
Simulation time 56185739014 ps
CPU time 1025.07 seconds
Started Aug 02 07:57:21 PM PDT 24
Finished Aug 02 08:14:26 PM PDT 24
Peak memory 575904 kb
Host smart-01e95cbc-a500-45ab-a6ee-1559db472dfb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486198005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_d
evice_slow_rsp.486198005
Directory /workspace/26.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.3472971816
Short name T2120
Test name
Test status
Simulation time 805591062 ps
CPU time 34.02 seconds
Started Aug 02 07:57:33 PM PDT 24
Finished Aug 02 07:58:07 PM PDT 24
Peak memory 575800 kb
Host smart-a61b5bc2-e4cc-480b-9642-1384ec37eb90
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472971816 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_add
r.3472971816
Directory /workspace/26.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_error_random.282943871
Short name T1956
Test name
Test status
Simulation time 273925478 ps
CPU time 23.43 seconds
Started Aug 02 07:57:22 PM PDT 24
Finished Aug 02 07:57:46 PM PDT 24
Peak memory 575768 kb
Host smart-703b7ed7-af26-4033-bdea-0e3127a2c215
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282943871 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.282943871
Directory /workspace/26.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_random.1339647546
Short name T462
Test name
Test status
Simulation time 591903593 ps
CPU time 49.43 seconds
Started Aug 02 07:57:20 PM PDT 24
Finished Aug 02 07:58:09 PM PDT 24
Peak memory 575856 kb
Host smart-3ac888f3-b56b-4e53-a9c8-55ce3129a62e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339647546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random.1339647546
Directory /workspace/26.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_random_large_delays.2940377795
Short name T496
Test name
Test status
Simulation time 25320319464 ps
CPU time 267.97 seconds
Started Aug 02 07:57:20 PM PDT 24
Finished Aug 02 08:01:48 PM PDT 24
Peak memory 575944 kb
Host smart-a33cf375-d3ed-480a-9d47-4bababec3141
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940377795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.2940377795
Directory /workspace/26.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_random_slow_rsp.1697337965
Short name T2240
Test name
Test status
Simulation time 30112630489 ps
CPU time 495.12 seconds
Started Aug 02 07:57:19 PM PDT 24
Finished Aug 02 08:05:35 PM PDT 24
Peak memory 575928 kb
Host smart-60137025-af83-4f27-b488-a9a5043c06c8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697337965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.1697337965
Directory /workspace/26.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.1639061645
Short name T2733
Test name
Test status
Simulation time 614670358 ps
CPU time 47.8 seconds
Started Aug 02 07:57:22 PM PDT 24
Finished Aug 02 07:58:09 PM PDT 24
Peak memory 575768 kb
Host smart-1fb258de-c68b-4d02-825d-b805aa89d08b
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639061645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_del
ays.1639061645
Directory /workspace/26.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_same_source.1343114138
Short name T2618
Test name
Test status
Simulation time 2719341782 ps
CPU time 85.79 seconds
Started Aug 02 07:57:21 PM PDT 24
Finished Aug 02 07:58:47 PM PDT 24
Peak memory 575912 kb
Host smart-d954bd4f-f697-4948-8c4d-f6b6b712c16a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343114138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.1343114138
Directory /workspace/26.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_smoke.2791416579
Short name T2564
Test name
Test status
Simulation time 51478739 ps
CPU time 6.08 seconds
Started Aug 02 07:57:29 PM PDT 24
Finished Aug 02 07:57:36 PM PDT 24
Peak memory 573808 kb
Host smart-fac48b8e-359d-4188-af6e-6df2801bc7ea
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791416579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.2791416579
Directory /workspace/26.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_smoke_large_delays.2823923957
Short name T1738
Test name
Test status
Simulation time 8476780230 ps
CPU time 83.12 seconds
Started Aug 02 07:57:21 PM PDT 24
Finished Aug 02 07:58:44 PM PDT 24
Peak memory 573964 kb
Host smart-a2318ec9-5055-4674-88ac-216df0735ee0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823923957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.2823923957
Directory /workspace/26.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.3501256200
Short name T2495
Test name
Test status
Simulation time 4901846620 ps
CPU time 84.8 seconds
Started Aug 02 07:57:22 PM PDT 24
Finished Aug 02 07:58:47 PM PDT 24
Peak memory 573932 kb
Host smart-992d010d-94c4-4c33-a086-83ba5c2f0b92
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501256200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.3501256200
Directory /workspace/26.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.1865381802
Short name T1711
Test name
Test status
Simulation time 48425117 ps
CPU time 6.47 seconds
Started Aug 02 07:57:22 PM PDT 24
Finished Aug 02 07:57:29 PM PDT 24
Peak memory 574488 kb
Host smart-55467dad-e425-4d71-ac07-209bd2538458
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865381802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delay
s.1865381802
Directory /workspace/26.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_stress_all.3371578366
Short name T486
Test name
Test status
Simulation time 7249609437 ps
CPU time 277.43 seconds
Started Aug 02 07:57:32 PM PDT 24
Finished Aug 02 08:02:10 PM PDT 24
Peak memory 576068 kb
Host smart-90b86b38-bec0-4e0b-a052-659c1303b499
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371578366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.3371578366
Directory /workspace/26.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.2475030411
Short name T878
Test name
Test status
Simulation time 8605771347 ps
CPU time 323.6 seconds
Started Aug 02 07:57:34 PM PDT 24
Finished Aug 02 08:02:57 PM PDT 24
Peak memory 575896 kb
Host smart-f12f0161-1582-44c1-9303-abd863b5b17f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475030411 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.2475030411
Directory /workspace/26.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.4177489108
Short name T1819
Test name
Test status
Simulation time 65363534 ps
CPU time 23.87 seconds
Started Aug 02 07:57:31 PM PDT 24
Finished Aug 02 07:57:55 PM PDT 24
Peak memory 576036 kb
Host smart-d4eb6d74-1347-43ef-8e1c-a4e5f383dcdc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177489108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all
_with_rand_reset.4177489108
Directory /workspace/26.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.3791284844
Short name T842
Test name
Test status
Simulation time 3889766783 ps
CPU time 493.23 seconds
Started Aug 02 07:57:33 PM PDT 24
Finished Aug 02 08:05:47 PM PDT 24
Peak memory 578888 kb
Host smart-ea000fec-6833-4e2a-93f6-6309d88e5fca
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791284844 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_al
l_with_reset_error.3791284844
Directory /workspace/26.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_unmapped_addr.320062572
Short name T1880
Test name
Test status
Simulation time 57875481 ps
CPU time 9.31 seconds
Started Aug 02 07:57:20 PM PDT 24
Finished Aug 02 07:57:29 PM PDT 24
Peak memory 575936 kb
Host smart-224dc4c7-a23d-40a9-962c-076ea12ee981
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320062572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.320062572
Directory /workspace/26.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/27.chip_tl_errors.1154017389
Short name T549
Test name
Test status
Simulation time 3351631240 ps
CPU time 193.97 seconds
Started Aug 02 07:57:35 PM PDT 24
Finished Aug 02 08:00:49 PM PDT 24
Peak memory 603660 kb
Host smart-eabd177f-38f8-4f9a-891b-28df35cfd4bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154017389 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.chip_tl_errors.1154017389
Directory /workspace/27.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_access_same_device.1381031851
Short name T1773
Test name
Test status
Simulation time 195578738 ps
CPU time 24.16 seconds
Started Aug 02 07:57:31 PM PDT 24
Finished Aug 02 07:57:56 PM PDT 24
Peak memory 575936 kb
Host smart-27003292-7765-4cac-a9e8-5f1dfc2cd97d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381031851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device
.1381031851
Directory /workspace/27.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.892055498
Short name T2770
Test name
Test status
Simulation time 27072471782 ps
CPU time 484.38 seconds
Started Aug 02 07:57:31 PM PDT 24
Finished Aug 02 08:05:36 PM PDT 24
Peak memory 575972 kb
Host smart-19329ef1-651f-4766-9aec-3f37500df337
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892055498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_d
evice_slow_rsp.892055498
Directory /workspace/27.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.466326525
Short name T1859
Test name
Test status
Simulation time 314450391 ps
CPU time 29.09 seconds
Started Aug 02 07:57:43 PM PDT 24
Finished Aug 02 07:58:12 PM PDT 24
Peak memory 575864 kb
Host smart-e2ef2fcb-167d-49d9-91c2-b8debf29c27a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466326525 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr
.466326525
Directory /workspace/27.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_error_random.1159061501
Short name T1449
Test name
Test status
Simulation time 789757904 ps
CPU time 28.19 seconds
Started Aug 02 07:57:44 PM PDT 24
Finished Aug 02 07:58:13 PM PDT 24
Peak memory 575800 kb
Host smart-f5516f3e-b64b-41e2-b561-26e0574f6982
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159061501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.1159061501
Directory /workspace/27.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_random.3597974467
Short name T2403
Test name
Test status
Simulation time 1256194727 ps
CPU time 44.08 seconds
Started Aug 02 07:57:30 PM PDT 24
Finished Aug 02 07:58:14 PM PDT 24
Peak memory 575940 kb
Host smart-51bb97db-5edc-4892-8ed2-2bfd7e7e74b7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597974467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random.3597974467
Directory /workspace/27.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_random_large_delays.313077715
Short name T2835
Test name
Test status
Simulation time 6929058480 ps
CPU time 71.68 seconds
Started Aug 02 07:57:33 PM PDT 24
Finished Aug 02 07:58:45 PM PDT 24
Peak memory 574020 kb
Host smart-b8610430-c68a-47df-b947-a0b4a1f7cccb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313077715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.313077715
Directory /workspace/27.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.1023619021
Short name T2052
Test name
Test status
Simulation time 44179842099 ps
CPU time 770.72 seconds
Started Aug 02 07:57:30 PM PDT 24
Finished Aug 02 08:10:21 PM PDT 24
Peak memory 576764 kb
Host smart-e687431f-d503-4479-93bd-3fb28ad27edc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023619021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.1023619021
Directory /workspace/27.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_random_zero_delays.516648651
Short name T2401
Test name
Test status
Simulation time 595774626 ps
CPU time 54.19 seconds
Started Aug 02 07:57:35 PM PDT 24
Finished Aug 02 07:58:29 PM PDT 24
Peak memory 575884 kb
Host smart-785ccc8b-7cf5-4473-b010-53bff82d6418
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516648651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_dela
ys.516648651
Directory /workspace/27.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_same_source.39984206
Short name T2036
Test name
Test status
Simulation time 174516477 ps
CPU time 15.42 seconds
Started Aug 02 07:57:43 PM PDT 24
Finished Aug 02 07:57:59 PM PDT 24
Peak memory 575832 kb
Host smart-8e2e719e-636c-4205-b5bc-56d5ae488a3f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39984206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.39984206
Directory /workspace/27.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_smoke.1205958800
Short name T1890
Test name
Test status
Simulation time 168659605 ps
CPU time 7.6 seconds
Started Aug 02 07:57:32 PM PDT 24
Finished Aug 02 07:57:40 PM PDT 24
Peak memory 573852 kb
Host smart-d446aa56-6df2-4a1d-87fe-538559aa7053
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205958800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.1205958800
Directory /workspace/27.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.4163008825
Short name T2633
Test name
Test status
Simulation time 8924206043 ps
CPU time 93.27 seconds
Started Aug 02 07:57:32 PM PDT 24
Finished Aug 02 07:59:06 PM PDT 24
Peak memory 573956 kb
Host smart-87a63cf6-e1a7-4f07-97ef-1b91bb6a8908
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163008825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.4163008825
Directory /workspace/27.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.1535362228
Short name T1523
Test name
Test status
Simulation time 4547444888 ps
CPU time 75.73 seconds
Started Aug 02 07:57:31 PM PDT 24
Finished Aug 02 07:58:46 PM PDT 24
Peak memory 574580 kb
Host smart-5d4d62a2-e29e-488e-82e7-17409a1fc9bc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535362228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.1535362228
Directory /workspace/27.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.2035543524
Short name T1434
Test name
Test status
Simulation time 51139707 ps
CPU time 6.78 seconds
Started Aug 02 07:57:32 PM PDT 24
Finished Aug 02 07:57:39 PM PDT 24
Peak memory 573820 kb
Host smart-1ba1b87b-1f81-4679-a1bd-55c713d1a7c5
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035543524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delay
s.2035543524
Directory /workspace/27.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_stress_all.190500445
Short name T1661
Test name
Test status
Simulation time 4232144344 ps
CPU time 147.66 seconds
Started Aug 02 07:57:41 PM PDT 24
Finished Aug 02 08:00:09 PM PDT 24
Peak memory 575956 kb
Host smart-8d13e7f2-59ad-45ae-870e-38993556f1f6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190500445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.190500445
Directory /workspace/27.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.3773705282
Short name T1513
Test name
Test status
Simulation time 890336436 ps
CPU time 73.91 seconds
Started Aug 02 07:57:44 PM PDT 24
Finished Aug 02 07:58:58 PM PDT 24
Peak memory 576092 kb
Host smart-8f90df66-0595-4e1e-8ce3-e70c1eb5589e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773705282 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.3773705282
Directory /workspace/27.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.1602713404
Short name T2918
Test name
Test status
Simulation time 3522514482 ps
CPU time 143.83 seconds
Started Aug 02 07:57:43 PM PDT 24
Finished Aug 02 08:00:07 PM PDT 24
Peak memory 576016 kb
Host smart-630b5c17-4857-429b-b2ed-c28292a7a0e7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602713404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all
_with_rand_reset.1602713404
Directory /workspace/27.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.732284550
Short name T1500
Test name
Test status
Simulation time 319364556 ps
CPU time 144.39 seconds
Started Aug 02 07:57:43 PM PDT 24
Finished Aug 02 08:00:08 PM PDT 24
Peak memory 576760 kb
Host smart-db8b47e6-566b-435a-954f-eba94d6165fe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732284550 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all
_with_reset_error.732284550
Directory /workspace/27.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_unmapped_addr.1828325135
Short name T1698
Test name
Test status
Simulation time 223047865 ps
CPU time 28.42 seconds
Started Aug 02 07:57:40 PM PDT 24
Finished Aug 02 07:58:09 PM PDT 24
Peak memory 575836 kb
Host smart-a2d6bd04-8863-4eed-90e5-75250c38a48d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828325135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.1828325135
Directory /workspace/27.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/28.chip_tl_errors.1583011237
Short name T1601
Test name
Test status
Simulation time 2012251857 ps
CPU time 73.36 seconds
Started Aug 02 07:57:44 PM PDT 24
Finished Aug 02 07:58:57 PM PDT 24
Peak memory 598520 kb
Host smart-b419a9cc-8bb0-48c3-882c-c5e6782d040a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583011237 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.chip_tl_errors.1583011237
Directory /workspace/28.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_access_same_device.1256734217
Short name T871
Test name
Test status
Simulation time 182067961 ps
CPU time 14.31 seconds
Started Aug 02 07:57:59 PM PDT 24
Finished Aug 02 07:58:14 PM PDT 24
Peak memory 575900 kb
Host smart-b4302b6a-4a2a-4840-a040-2983548507a0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256734217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device
.1256734217
Directory /workspace/28.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.2229347811
Short name T1889
Test name
Test status
Simulation time 74462895114 ps
CPU time 1274.44 seconds
Started Aug 02 07:57:58 PM PDT 24
Finished Aug 02 08:19:12 PM PDT 24
Peak memory 575900 kb
Host smart-d86840b4-0384-4cac-b95c-854ff942a58c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229347811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_
device_slow_rsp.2229347811
Directory /workspace/28.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.4156242066
Short name T2106
Test name
Test status
Simulation time 856033137 ps
CPU time 35.47 seconds
Started Aug 02 07:57:58 PM PDT 24
Finished Aug 02 07:58:33 PM PDT 24
Peak memory 575960 kb
Host smart-76e61dcd-7da1-49e2-9ff8-cdd146d2e0e5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156242066 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_add
r.4156242066
Directory /workspace/28.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_error_random.649121493
Short name T1972
Test name
Test status
Simulation time 609565046 ps
CPU time 24.99 seconds
Started Aug 02 07:57:57 PM PDT 24
Finished Aug 02 07:58:23 PM PDT 24
Peak memory 575724 kb
Host smart-0e239197-9b65-4f9e-b800-606e441980fa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649121493 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.649121493
Directory /workspace/28.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_random.1809288821
Short name T2254
Test name
Test status
Simulation time 154859345 ps
CPU time 8.78 seconds
Started Aug 02 07:57:58 PM PDT 24
Finished Aug 02 07:58:07 PM PDT 24
Peak memory 573804 kb
Host smart-338c1e21-708b-46e0-8f5d-4071c1b6bfca
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809288821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random.1809288821
Directory /workspace/28.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_random_large_delays.2320985352
Short name T1583
Test name
Test status
Simulation time 33097991537 ps
CPU time 337.05 seconds
Started Aug 02 07:57:58 PM PDT 24
Finished Aug 02 08:03:35 PM PDT 24
Peak memory 575900 kb
Host smart-7b800fa7-9b2a-4b21-8517-f52722a4dc42
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320985352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.2320985352
Directory /workspace/28.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_random_slow_rsp.739837138
Short name T2189
Test name
Test status
Simulation time 38445159883 ps
CPU time 681.48 seconds
Started Aug 02 07:57:58 PM PDT 24
Finished Aug 02 08:09:20 PM PDT 24
Peak memory 575848 kb
Host smart-1574c945-efb1-4e3e-89f7-3e84257f52a3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739837138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.739837138
Directory /workspace/28.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_random_zero_delays.2811334441
Short name T2400
Test name
Test status
Simulation time 314712812 ps
CPU time 29.34 seconds
Started Aug 02 07:57:59 PM PDT 24
Finished Aug 02 07:58:28 PM PDT 24
Peak memory 575752 kb
Host smart-8c84c740-5e6e-4058-b099-afe69374c5af
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811334441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_del
ays.2811334441
Directory /workspace/28.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_same_source.3503752577
Short name T2376
Test name
Test status
Simulation time 2182161209 ps
CPU time 69.89 seconds
Started Aug 02 07:57:59 PM PDT 24
Finished Aug 02 07:59:09 PM PDT 24
Peak memory 575928 kb
Host smart-081bec77-1eb5-4a75-b8de-4d0d0a11ec0b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503752577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.3503752577
Directory /workspace/28.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_smoke.1403863678
Short name T2130
Test name
Test status
Simulation time 184109039 ps
CPU time 7.8 seconds
Started Aug 02 07:57:42 PM PDT 24
Finished Aug 02 07:57:50 PM PDT 24
Peak memory 574468 kb
Host smart-91ea2d28-2440-490c-b0aa-2c8317f5b1f0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403863678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.1403863678
Directory /workspace/28.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_smoke_large_delays.405565616
Short name T1415
Test name
Test status
Simulation time 5069734833 ps
CPU time 53.02 seconds
Started Aug 02 07:57:43 PM PDT 24
Finished Aug 02 07:58:36 PM PDT 24
Peak memory 573944 kb
Host smart-afa9dc52-9f9a-4dd1-9f91-d43a7b73aa52
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405565616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.405565616
Directory /workspace/28.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.4110295890
Short name T1477
Test name
Test status
Simulation time 3843708649 ps
CPU time 63.8 seconds
Started Aug 02 07:57:42 PM PDT 24
Finished Aug 02 07:58:46 PM PDT 24
Peak memory 573896 kb
Host smart-ef8cc02b-f228-4d53-9eea-b2f6ff6a99f0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110295890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.4110295890
Directory /workspace/28.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.1485573815
Short name T1494
Test name
Test status
Simulation time 40506455 ps
CPU time 5.82 seconds
Started Aug 02 07:57:41 PM PDT 24
Finished Aug 02 07:57:47 PM PDT 24
Peak memory 574516 kb
Host smart-078ea88d-6cb7-41d1-8c6b-b8750236d0fd
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485573815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delay
s.1485573815
Directory /workspace/28.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_stress_all.3956921238
Short name T1540
Test name
Test status
Simulation time 268842895 ps
CPU time 25.25 seconds
Started Aug 02 07:57:58 PM PDT 24
Finished Aug 02 07:58:24 PM PDT 24
Peak memory 575824 kb
Host smart-18f47f27-0a00-4d13-be18-802a1d254dd6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956921238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.3956921238
Directory /workspace/28.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.4277271540
Short name T2683
Test name
Test status
Simulation time 3374227047 ps
CPU time 261.35 seconds
Started Aug 02 07:57:59 PM PDT 24
Finished Aug 02 08:02:21 PM PDT 24
Peak memory 576220 kb
Host smart-896510f1-42b1-4f8c-a7b4-7b57940b16f8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277271540 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.4277271540
Directory /workspace/28.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.3164128032
Short name T2703
Test name
Test status
Simulation time 272688489 ps
CPU time 108.28 seconds
Started Aug 02 07:57:58 PM PDT 24
Finished Aug 02 07:59:47 PM PDT 24
Peak memory 576764 kb
Host smart-91b3bf49-40f3-42dd-a634-8ff1c47c5c28
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164128032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all
_with_rand_reset.3164128032
Directory /workspace/28.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.1127327359
Short name T1945
Test name
Test status
Simulation time 68036995 ps
CPU time 27.66 seconds
Started Aug 02 07:57:58 PM PDT 24
Finished Aug 02 07:58:26 PM PDT 24
Peak memory 576064 kb
Host smart-f6a83e2d-c65b-4ba4-a360-5df3577d14bc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127327359 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_al
l_with_reset_error.1127327359
Directory /workspace/28.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_unmapped_addr.2455740807
Short name T2349
Test name
Test status
Simulation time 205632453 ps
CPU time 25.17 seconds
Started Aug 02 07:57:57 PM PDT 24
Finished Aug 02 07:58:22 PM PDT 24
Peak memory 576044 kb
Host smart-5c533594-70db-4fe1-a8e9-fcdf77a5d3eb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455740807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.2455740807
Directory /workspace/28.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/29.chip_tl_errors.1740182179
Short name T722
Test name
Test status
Simulation time 2981261728 ps
CPU time 187.28 seconds
Started Aug 02 07:58:00 PM PDT 24
Finished Aug 02 08:01:07 PM PDT 24
Peak memory 603652 kb
Host smart-eb860518-72fb-4b8b-a176-80e3444f34e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740182179 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.chip_tl_errors.1740182179
Directory /workspace/29.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_access_same_device.2857418506
Short name T2463
Test name
Test status
Simulation time 1988386162 ps
CPU time 71.49 seconds
Started Aug 02 07:58:09 PM PDT 24
Finished Aug 02 07:59:21 PM PDT 24
Peak memory 575992 kb
Host smart-24e917c7-9c92-4dfd-9504-cf2846f3d89a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857418506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device
.2857418506
Directory /workspace/29.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.1995332032
Short name T2631
Test name
Test status
Simulation time 46488247896 ps
CPU time 740.23 seconds
Started Aug 02 07:58:11 PM PDT 24
Finished Aug 02 08:10:32 PM PDT 24
Peak memory 576008 kb
Host smart-7563e723-3631-45aa-bcbf-9869a5aa9937
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995332032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_
device_slow_rsp.1995332032
Directory /workspace/29.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.3535249087
Short name T1701
Test name
Test status
Simulation time 681684612 ps
CPU time 28.59 seconds
Started Aug 02 07:58:11 PM PDT 24
Finished Aug 02 07:58:39 PM PDT 24
Peak memory 575964 kb
Host smart-1839afff-49fd-463d-846b-06e5f250b486
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535249087 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_add
r.3535249087
Directory /workspace/29.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_error_random.1908979090
Short name T1444
Test name
Test status
Simulation time 548130878 ps
CPU time 43.18 seconds
Started Aug 02 07:58:15 PM PDT 24
Finished Aug 02 07:58:58 PM PDT 24
Peak memory 575900 kb
Host smart-0bb4d333-7ea0-4220-9ddd-e6926959e7c5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908979090 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.1908979090
Directory /workspace/29.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_random.2298189490
Short name T2153
Test name
Test status
Simulation time 158112163 ps
CPU time 8.38 seconds
Started Aug 02 07:58:09 PM PDT 24
Finished Aug 02 07:58:18 PM PDT 24
Peak memory 573844 kb
Host smart-992a3234-2776-45b6-887e-3c7acb373d6c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298189490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random.2298189490
Directory /workspace/29.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_random_large_delays.2766391297
Short name T1585
Test name
Test status
Simulation time 99318330316 ps
CPU time 1011.74 seconds
Started Aug 02 07:58:10 PM PDT 24
Finished Aug 02 08:15:02 PM PDT 24
Peak memory 576036 kb
Host smart-8e67aff2-a1b6-440e-8a4e-1a5da07c97db
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766391297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.2766391297
Directory /workspace/29.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.3315348486
Short name T1488
Test name
Test status
Simulation time 1968619358 ps
CPU time 32.47 seconds
Started Aug 02 07:58:11 PM PDT 24
Finished Aug 02 07:58:44 PM PDT 24
Peak memory 574564 kb
Host smart-eb2c3d2f-b90e-4383-968d-1ee65a5c4b46
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315348486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.3315348486
Directory /workspace/29.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_random_zero_delays.958752546
Short name T2879
Test name
Test status
Simulation time 184103509 ps
CPU time 17.18 seconds
Started Aug 02 07:58:10 PM PDT 24
Finished Aug 02 07:58:28 PM PDT 24
Peak memory 575904 kb
Host smart-4be18447-7b8a-4872-8800-cb4b61df48b2
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958752546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_dela
ys.958752546
Directory /workspace/29.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_same_source.1711151924
Short name T523
Test name
Test status
Simulation time 81202298 ps
CPU time 9.33 seconds
Started Aug 02 07:58:08 PM PDT 24
Finished Aug 02 07:58:18 PM PDT 24
Peak memory 575716 kb
Host smart-ae8eb018-2e26-4b6e-b6b3-3ff3cc35eebd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711151924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.1711151924
Directory /workspace/29.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_smoke.1288771643
Short name T2342
Test name
Test status
Simulation time 38825565 ps
CPU time 6.2 seconds
Started Aug 02 07:57:58 PM PDT 24
Finished Aug 02 07:58:04 PM PDT 24
Peak memory 574488 kb
Host smart-d72a4315-66c0-42bd-b7ac-35c661696c62
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288771643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.1288771643
Directory /workspace/29.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_smoke_large_delays.3844137098
Short name T2649
Test name
Test status
Simulation time 7511444670 ps
CPU time 75.7 seconds
Started Aug 02 07:57:57 PM PDT 24
Finished Aug 02 07:59:13 PM PDT 24
Peak memory 574588 kb
Host smart-b34a4183-590b-4fb3-a6ce-57d97315ca02
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844137098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.3844137098
Directory /workspace/29.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.3861686670
Short name T2718
Test name
Test status
Simulation time 4958486758 ps
CPU time 85.29 seconds
Started Aug 02 07:58:09 PM PDT 24
Finished Aug 02 07:59:35 PM PDT 24
Peak memory 573892 kb
Host smart-24789bb3-161a-49ee-8f94-2c142f44adf3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861686670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.3861686670
Directory /workspace/29.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_smoke_zero_delays.3085906634
Short name T2528
Test name
Test status
Simulation time 50004124 ps
CPU time 7.02 seconds
Started Aug 02 07:57:58 PM PDT 24
Finished Aug 02 07:58:05 PM PDT 24
Peak memory 573828 kb
Host smart-1ef4b2f6-ce54-494d-b6ab-e1f051a09410
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085906634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delay
s.3085906634
Directory /workspace/29.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_stress_all.2429379680
Short name T2549
Test name
Test status
Simulation time 775125615 ps
CPU time 60.53 seconds
Started Aug 02 07:58:09 PM PDT 24
Finished Aug 02 07:59:09 PM PDT 24
Peak memory 575944 kb
Host smart-8ff54f1a-b57c-46eb-8194-54b7e33cad81
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429379680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.2429379680
Directory /workspace/29.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.322448011
Short name T1967
Test name
Test status
Simulation time 2384360787 ps
CPU time 208 seconds
Started Aug 02 07:58:10 PM PDT 24
Finished Aug 02 08:01:38 PM PDT 24
Peak memory 576824 kb
Host smart-2e57c1b9-b3bb-494e-b7e2-a3dba01349e2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322448011 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.322448011
Directory /workspace/29.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.113181262
Short name T2484
Test name
Test status
Simulation time 6396793734 ps
CPU time 624.1 seconds
Started Aug 02 07:58:10 PM PDT 24
Finished Aug 02 08:08:34 PM PDT 24
Peak memory 576724 kb
Host smart-cb89a3db-648a-438c-a231-b448b3f2e29b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113181262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_
with_rand_reset.113181262
Directory /workspace/29.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.47708966
Short name T2311
Test name
Test status
Simulation time 1840797358 ps
CPU time 178.96 seconds
Started Aug 02 07:58:11 PM PDT 24
Finished Aug 02 08:01:10 PM PDT 24
Peak memory 575992 kb
Host smart-f432936a-941b-4e57-9a66-378bc2e26778
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47708966 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_
with_reset_error.47708966
Directory /workspace/29.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_unmapped_addr.2728958327
Short name T2565
Test name
Test status
Simulation time 685830814 ps
CPU time 29.1 seconds
Started Aug 02 07:58:09 PM PDT 24
Finished Aug 02 07:58:38 PM PDT 24
Peak memory 576004 kb
Host smart-c905d3bf-e70d-43be-a271-22bfbe7aeefe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728958327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.2728958327
Directory /workspace/29.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/3.chip_csr_bit_bash.3071747459
Short name T1492
Test name
Test status
Simulation time 15383538800 ps
CPU time 1774.99 seconds
Started Aug 02 07:52:04 PM PDT 24
Finished Aug 02 08:21:39 PM PDT 24
Peak memory 592560 kb
Host smart-ec91fa85-e772-4b30-9277-b08567f0a1ea
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071747459 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 3.chip_csr_bit_bash.3071747459
Directory /workspace/3.chip_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.2136244306
Short name T134
Test name
Test status
Simulation time 5218415082 ps
CPU time 215.65 seconds
Started Aug 02 07:52:21 PM PDT 24
Finished Aug 02 07:55:57 PM PDT 24
Peak memory 664092 kb
Host smart-4031bd02-49de-458c-b3f9-33cf50a53765
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136244306 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_hw_r
eset.2136244306
Directory /workspace/3.chip_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.1745176966
Short name T2133
Test name
Test status
Simulation time 9183969200 ps
CPU time 736.08 seconds
Started Aug 02 07:52:16 PM PDT 24
Finished Aug 02 08:04:32 PM PDT 24
Peak memory 653040 kb
Host smart-d5aa8ef3-3061-484a-bd9a-febbd4852269
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745176966 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.chip_csr_mem_rw_with_rand_reset.1745176966
Directory /workspace/3.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.chip_csr_rw.2258981868
Short name T1795
Test name
Test status
Simulation time 6548130604 ps
CPU time 622.59 seconds
Started Aug 02 07:52:23 PM PDT 24
Finished Aug 02 08:02:46 PM PDT 24
Peak memory 598464 kb
Host smart-25b0c558-8307-4994-a23d-e778d86c01c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258981868 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_rw.2258981868
Directory /workspace/3.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.2813415823
Short name T2141
Test name
Test status
Simulation time 15819676762 ps
CPU time 1857.56 seconds
Started Aug 02 07:52:07 PM PDT 24
Finished Aug 02 08:23:04 PM PDT 24
Peak memory 593304 kb
Host smart-bef212bd-b33f-4ed4-8735-512dc188f7b6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813415823 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.chip_same_csr_outstanding.2813415823
Directory /workspace/3.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_access_same_device.3296893404
Short name T2719
Test name
Test status
Simulation time 1230946940 ps
CPU time 83.75 seconds
Started Aug 02 07:52:17 PM PDT 24
Finished Aug 02 07:53:41 PM PDT 24
Peak memory 575792 kb
Host smart-c8a8efbd-48c1-41b7-a4dc-1cabd26ae59c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296893404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.
3296893404
Directory /workspace/3.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.3999453578
Short name T2466
Test name
Test status
Simulation time 11141871857 ps
CPU time 183.9 seconds
Started Aug 02 07:52:17 PM PDT 24
Finished Aug 02 07:55:21 PM PDT 24
Peak memory 575936 kb
Host smart-1fbee5b2-244f-478c-8840-206638ace350
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999453578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_d
evice_slow_rsp.3999453578
Directory /workspace/3.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.1635852654
Short name T1718
Test name
Test status
Simulation time 179030499 ps
CPU time 19.64 seconds
Started Aug 02 07:52:16 PM PDT 24
Finished Aug 02 07:52:35 PM PDT 24
Peak memory 575844 kb
Host smart-9abafc3c-9570-411c-8823-be0d7e01d29a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635852654 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr
.1635852654
Directory /workspace/3.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_error_random.841799838
Short name T1407
Test name
Test status
Simulation time 1599278327 ps
CPU time 48.73 seconds
Started Aug 02 07:52:17 PM PDT 24
Finished Aug 02 07:53:06 PM PDT 24
Peak memory 575688 kb
Host smart-08bac831-ab7e-47a2-bf44-4fb7495cfd6f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841799838 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.841799838
Directory /workspace/3.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_random.1621892243
Short name T1943
Test name
Test status
Simulation time 580187479 ps
CPU time 46.28 seconds
Started Aug 02 07:52:03 PM PDT 24
Finished Aug 02 07:52:50 PM PDT 24
Peak memory 575744 kb
Host smart-5f4d5350-c461-45fd-bb58-fba9379b76db
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621892243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random.1621892243
Directory /workspace/3.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_random_large_delays.4033943236
Short name T1954
Test name
Test status
Simulation time 19713799193 ps
CPU time 214.47 seconds
Started Aug 02 07:52:16 PM PDT 24
Finished Aug 02 07:55:50 PM PDT 24
Peak memory 575852 kb
Host smart-6fbd59d9-253c-4909-b9aa-b3889d195b62
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033943236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.4033943236
Directory /workspace/3.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.3751678824
Short name T1480
Test name
Test status
Simulation time 8460218464 ps
CPU time 139.38 seconds
Started Aug 02 07:52:16 PM PDT 24
Finished Aug 02 07:54:35 PM PDT 24
Peak memory 575860 kb
Host smart-ffa68695-7df3-4e76-87e2-0b00ace5b5b0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751678824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.3751678824
Directory /workspace/3.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_random_zero_delays.1663057872
Short name T629
Test name
Test status
Simulation time 528389295 ps
CPU time 42.66 seconds
Started Aug 02 07:52:03 PM PDT 24
Finished Aug 02 07:52:46 PM PDT 24
Peak memory 575904 kb
Host smart-d173a626-267b-479b-9f14-646a09c1aec5
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663057872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_dela
ys.1663057872
Directory /workspace/3.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_same_source.380485194
Short name T2850
Test name
Test status
Simulation time 525724863 ps
CPU time 38.52 seconds
Started Aug 02 07:52:20 PM PDT 24
Finished Aug 02 07:52:59 PM PDT 24
Peak memory 575756 kb
Host smart-146824c3-cdbd-444e-99cb-bb6147ad3f52
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380485194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.380485194
Directory /workspace/3.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_smoke.3814804112
Short name T652
Test name
Test status
Simulation time 231907693 ps
CPU time 9.78 seconds
Started Aug 02 07:52:01 PM PDT 24
Finished Aug 02 07:52:11 PM PDT 24
Peak memory 574496 kb
Host smart-1ce5f49e-29a7-4187-8d0f-cd09c3db52c1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814804112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.3814804112
Directory /workspace/3.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_smoke_large_delays.2854915776
Short name T2237
Test name
Test status
Simulation time 6807396391 ps
CPU time 65.82 seconds
Started Aug 02 07:52:02 PM PDT 24
Finished Aug 02 07:53:07 PM PDT 24
Peak memory 574600 kb
Host smart-bf598d29-aadc-4f29-b001-74aa6bd03ffa
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854915776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.2854915776
Directory /workspace/3.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.82229879
Short name T2717
Test name
Test status
Simulation time 6233730350 ps
CPU time 101.45 seconds
Started Aug 02 07:52:06 PM PDT 24
Finished Aug 02 07:53:48 PM PDT 24
Peak memory 573916 kb
Host smart-64a41af1-1011-4e30-af6a-4fd3febc95a8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82229879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.82229879
Directory /workspace/3.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.1891849054
Short name T256
Test name
Test status
Simulation time 51040813 ps
CPU time 5.86 seconds
Started Aug 02 07:52:01 PM PDT 24
Finished Aug 02 07:52:07 PM PDT 24
Peak memory 574548 kb
Host smart-3b05c20d-4c2d-435b-8c08-b9bb40ca716f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891849054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays
.1891849054
Directory /workspace/3.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.1260202572
Short name T2710
Test name
Test status
Simulation time 10205388458 ps
CPU time 368.86 seconds
Started Aug 02 07:52:16 PM PDT 24
Finished Aug 02 07:58:25 PM PDT 24
Peak memory 576160 kb
Host smart-bfe2a878-812d-485c-b14b-2b347942bbef
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260202572 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.1260202572
Directory /workspace/3.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.906280911
Short name T542
Test name
Test status
Simulation time 274484180 ps
CPU time 87.07 seconds
Started Aug 02 07:52:17 PM PDT 24
Finished Aug 02 07:53:44 PM PDT 24
Peak memory 576704 kb
Host smart-59e2676a-8462-4f52-b15a-ce6aee5bd3ab
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906280911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_w
ith_rand_reset.906280911
Directory /workspace/3.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.2678949212
Short name T1430
Test name
Test status
Simulation time 261259812 ps
CPU time 42.7 seconds
Started Aug 02 07:52:16 PM PDT 24
Finished Aug 02 07:52:59 PM PDT 24
Peak memory 576048 kb
Host smart-7696d2e6-babb-42d0-b75b-574a6df46e41
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678949212 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all
_with_reset_error.2678949212
Directory /workspace/3.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_unmapped_addr.1555463874
Short name T2231
Test name
Test status
Simulation time 226454664 ps
CPU time 27.19 seconds
Started Aug 02 07:52:14 PM PDT 24
Finished Aug 02 07:52:41 PM PDT 24
Peak memory 575880 kb
Host smart-631b3d2e-17b9-4382-9574-fad7a41fab26
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555463874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.1555463874
Directory /workspace/3.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_access_same_device.2178643543
Short name T2568
Test name
Test status
Simulation time 1024152579 ps
CPU time 71.44 seconds
Started Aug 02 07:58:10 PM PDT 24
Finished Aug 02 07:59:21 PM PDT 24
Peak memory 575964 kb
Host smart-5bbedd2c-633e-498e-aa7f-d2fc52b5b2fb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178643543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device
.2178643543
Directory /workspace/30.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.354918843
Short name T2305
Test name
Test status
Simulation time 142245124 ps
CPU time 15.66 seconds
Started Aug 02 07:58:10 PM PDT 24
Finished Aug 02 07:58:26 PM PDT 24
Peak memory 575948 kb
Host smart-d0e27562-b111-4119-85da-b0b4e52e91da
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354918843 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr
.354918843
Directory /workspace/30.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_error_random.3864190688
Short name T2208
Test name
Test status
Simulation time 1148195765 ps
CPU time 40.14 seconds
Started Aug 02 07:58:14 PM PDT 24
Finished Aug 02 07:58:54 PM PDT 24
Peak memory 575836 kb
Host smart-263f2e3f-3e27-4839-9e6e-468001653fca
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864190688 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.3864190688
Directory /workspace/30.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_random.3842440845
Short name T1938
Test name
Test status
Simulation time 1363216505 ps
CPU time 50.96 seconds
Started Aug 02 07:58:16 PM PDT 24
Finished Aug 02 07:59:07 PM PDT 24
Peak memory 575880 kb
Host smart-def33f7d-70e1-49bb-9c9f-703c82246bbd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842440845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random.3842440845
Directory /workspace/30.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_random_large_delays.2998960401
Short name T529
Test name
Test status
Simulation time 73803985185 ps
CPU time 729.64 seconds
Started Aug 02 07:58:10 PM PDT 24
Finished Aug 02 08:10:20 PM PDT 24
Peak memory 576096 kb
Host smart-23b3996b-0cdd-4dc0-ad94-f03ba793abf6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998960401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.2998960401
Directory /workspace/30.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_random_slow_rsp.282555683
Short name T608
Test name
Test status
Simulation time 19929574983 ps
CPU time 344.95 seconds
Started Aug 02 07:58:13 PM PDT 24
Finished Aug 02 08:03:58 PM PDT 24
Peak memory 575840 kb
Host smart-f101254e-685f-4700-935f-cdc8fc53cc8f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282555683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.282555683
Directory /workspace/30.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_random_zero_delays.801744255
Short name T578
Test name
Test status
Simulation time 147540544 ps
CPU time 15.98 seconds
Started Aug 02 07:58:14 PM PDT 24
Finished Aug 02 07:58:30 PM PDT 24
Peak memory 575740 kb
Host smart-82332df5-4056-4bbc-b12d-f99d9f5ab2e9
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801744255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_dela
ys.801744255
Directory /workspace/30.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_same_source.1026734971
Short name T678
Test name
Test status
Simulation time 165737037 ps
CPU time 14.51 seconds
Started Aug 02 07:58:10 PM PDT 24
Finished Aug 02 07:58:25 PM PDT 24
Peak memory 575780 kb
Host smart-7ae6d421-8feb-4a71-8ebd-e7d49a03141b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026734971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.1026734971
Directory /workspace/30.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_smoke.1652578738
Short name T2183
Test name
Test status
Simulation time 269226555 ps
CPU time 10.82 seconds
Started Aug 02 07:58:08 PM PDT 24
Finished Aug 02 07:58:19 PM PDT 24
Peak memory 573896 kb
Host smart-027dd180-8c15-4d9d-9768-09b9cab169fc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652578738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.1652578738
Directory /workspace/30.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_smoke_large_delays.1259076732
Short name T2085
Test name
Test status
Simulation time 7314765698 ps
CPU time 77.81 seconds
Started Aug 02 07:58:12 PM PDT 24
Finished Aug 02 07:59:30 PM PDT 24
Peak memory 574016 kb
Host smart-541f86fd-dafd-4dcb-b659-9bc43fdb7672
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259076732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.1259076732
Directory /workspace/30.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.3202144861
Short name T1530
Test name
Test status
Simulation time 6078986887 ps
CPU time 96.45 seconds
Started Aug 02 07:58:11 PM PDT 24
Finished Aug 02 07:59:47 PM PDT 24
Peak memory 574564 kb
Host smart-44fdecec-cfe1-4a1c-802d-6f5575c1243a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202144861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.3202144861
Directory /workspace/30.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_smoke_zero_delays.2720583921
Short name T2732
Test name
Test status
Simulation time 42309558 ps
CPU time 5.99 seconds
Started Aug 02 07:58:11 PM PDT 24
Finished Aug 02 07:58:17 PM PDT 24
Peak memory 574492 kb
Host smart-ef8a6de7-4399-42a3-a8a2-0d013894f583
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720583921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delay
s.2720583921
Directory /workspace/30.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_stress_all.1436690328
Short name T473
Test name
Test status
Simulation time 3373664421 ps
CPU time 297.43 seconds
Started Aug 02 07:58:10 PM PDT 24
Finished Aug 02 08:03:07 PM PDT 24
Peak memory 576036 kb
Host smart-a9692691-e12e-4c75-ab81-594708708a78
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436690328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.1436690328
Directory /workspace/30.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.1256721740
Short name T2581
Test name
Test status
Simulation time 4948003059 ps
CPU time 182.62 seconds
Started Aug 02 07:58:12 PM PDT 24
Finished Aug 02 08:01:15 PM PDT 24
Peak memory 576192 kb
Host smart-ed4ac3be-0051-4484-afd9-ce3dae638e82
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256721740 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.1256721740
Directory /workspace/30.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.3443801219
Short name T2605
Test name
Test status
Simulation time 18986243546 ps
CPU time 823.7 seconds
Started Aug 02 07:58:10 PM PDT 24
Finished Aug 02 08:11:54 PM PDT 24
Peak memory 576824 kb
Host smart-085ec75c-15d9-41d4-a157-789cae844cef
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443801219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all
_with_rand_reset.3443801219
Directory /workspace/30.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.3148589276
Short name T1624
Test name
Test status
Simulation time 3066929575 ps
CPU time 388.72 seconds
Started Aug 02 07:58:24 PM PDT 24
Finished Aug 02 08:04:53 PM PDT 24
Peak memory 576812 kb
Host smart-36640728-d120-46ca-9aa2-d7477cb96968
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148589276 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_al
l_with_reset_error.3148589276
Directory /workspace/30.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_unmapped_addr.3909459080
Short name T2382
Test name
Test status
Simulation time 65224111 ps
CPU time 10.16 seconds
Started Aug 02 07:58:11 PM PDT 24
Finished Aug 02 07:58:21 PM PDT 24
Peak memory 575972 kb
Host smart-6355c2b9-e00a-4d42-bf86-059e4e15b72c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909459080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.3909459080
Directory /workspace/30.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_access_same_device.134868577
Short name T2498
Test name
Test status
Simulation time 543786422 ps
CPU time 36.16 seconds
Started Aug 02 07:58:22 PM PDT 24
Finished Aug 02 07:58:58 PM PDT 24
Peak memory 575864 kb
Host smart-86650b2d-4791-4aaa-82cf-8941d63a43ce
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134868577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.
134868577
Directory /workspace/31.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.2241288745
Short name T873
Test name
Test status
Simulation time 12275500078 ps
CPU time 204.15 seconds
Started Aug 02 07:58:25 PM PDT 24
Finished Aug 02 08:01:49 PM PDT 24
Peak memory 575904 kb
Host smart-f3b823ee-5e0e-4891-845e-252ba4249829
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241288745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_
device_slow_rsp.2241288745
Directory /workspace/31.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.1973955331
Short name T2690
Test name
Test status
Simulation time 483581316 ps
CPU time 22.79 seconds
Started Aug 02 07:58:23 PM PDT 24
Finished Aug 02 07:58:46 PM PDT 24
Peak memory 575828 kb
Host smart-b39bc263-8680-4184-bf5b-a0d6535f4e4e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973955331 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_add
r.1973955331
Directory /workspace/31.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_error_random.2521903714
Short name T1522
Test name
Test status
Simulation time 113168036 ps
CPU time 11.74 seconds
Started Aug 02 07:58:21 PM PDT 24
Finished Aug 02 07:58:33 PM PDT 24
Peak memory 575712 kb
Host smart-dd12282b-ceef-441a-b16b-5e97aabc60dd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521903714 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.2521903714
Directory /workspace/31.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_random.1104912139
Short name T2370
Test name
Test status
Simulation time 362030976 ps
CPU time 14.84 seconds
Started Aug 02 07:58:24 PM PDT 24
Finished Aug 02 07:58:38 PM PDT 24
Peak memory 575900 kb
Host smart-58ae1312-d64d-48b4-8048-4c9b09bb4e72
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104912139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random.1104912139
Directory /workspace/31.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_random_large_delays.3261744569
Short name T2253
Test name
Test status
Simulation time 35320993200 ps
CPU time 376.81 seconds
Started Aug 02 07:58:23 PM PDT 24
Finished Aug 02 08:04:40 PM PDT 24
Peak memory 576056 kb
Host smart-5e267266-d5bd-4da6-872d-3fe4f4aed395
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261744569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.3261744569
Directory /workspace/31.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_random_slow_rsp.2309911859
Short name T2328
Test name
Test status
Simulation time 64277281403 ps
CPU time 1142.49 seconds
Started Aug 02 07:58:20 PM PDT 24
Finished Aug 02 08:17:23 PM PDT 24
Peak memory 576052 kb
Host smart-845ba990-61fd-480d-a42c-42acc36d6bab
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309911859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.2309911859
Directory /workspace/31.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_random_zero_delays.1010334748
Short name T2216
Test name
Test status
Simulation time 160791194 ps
CPU time 15.23 seconds
Started Aug 02 07:58:23 PM PDT 24
Finished Aug 02 07:58:38 PM PDT 24
Peak memory 575944 kb
Host smart-784b5860-7e92-4cae-b316-2fc6b4f589b1
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010334748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_del
ays.1010334748
Directory /workspace/31.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_same_source.3817479630
Short name T1650
Test name
Test status
Simulation time 480805452 ps
CPU time 30.94 seconds
Started Aug 02 07:58:23 PM PDT 24
Finished Aug 02 07:58:54 PM PDT 24
Peak memory 575972 kb
Host smart-a730a113-6cb8-4727-9651-8acdddfc6a19
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817479630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.3817479630
Directory /workspace/31.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_smoke.4051041974
Short name T2769
Test name
Test status
Simulation time 44043332 ps
CPU time 6.21 seconds
Started Aug 02 07:58:24 PM PDT 24
Finished Aug 02 07:58:30 PM PDT 24
Peak memory 573832 kb
Host smart-6f43d5bc-9501-40ea-8c23-1671a96cc116
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051041974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.4051041974
Directory /workspace/31.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_smoke_large_delays.2655267160
Short name T1971
Test name
Test status
Simulation time 8676576508 ps
CPU time 87.09 seconds
Started Aug 02 07:58:23 PM PDT 24
Finished Aug 02 07:59:50 PM PDT 24
Peak memory 574640 kb
Host smart-e77de2e8-d969-4f57-bae8-59477f285878
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655267160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.2655267160
Directory /workspace/31.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.3955537849
Short name T2482
Test name
Test status
Simulation time 5261202341 ps
CPU time 85.3 seconds
Started Aug 02 07:58:23 PM PDT 24
Finished Aug 02 07:59:48 PM PDT 24
Peak memory 573944 kb
Host smart-feb10015-1be8-42dd-a98d-0ab139a193c3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955537849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.3955537849
Directory /workspace/31.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.793734746
Short name T1512
Test name
Test status
Simulation time 53380274 ps
CPU time 6.71 seconds
Started Aug 02 07:58:23 PM PDT 24
Finished Aug 02 07:58:30 PM PDT 24
Peak memory 573916 kb
Host smart-19101fd5-5f30-420c-8b49-bec2e36c368b
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793734746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays
.793734746
Directory /workspace/31.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_stress_all.14044651
Short name T2725
Test name
Test status
Simulation time 3379718944 ps
CPU time 137.4 seconds
Started Aug 02 07:58:25 PM PDT 24
Finished Aug 02 08:00:42 PM PDT 24
Peak memory 575924 kb
Host smart-f72d5363-6fc5-4e6b-a8ac-e7d86036b352
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14044651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.14044651
Directory /workspace/31.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_error.3548023894
Short name T2569
Test name
Test status
Simulation time 2229743423 ps
CPU time 79.04 seconds
Started Aug 02 07:58:36 PM PDT 24
Finished Aug 02 07:59:55 PM PDT 24
Peak memory 576012 kb
Host smart-7cb57986-7ae6-48ed-b52b-b05eb951b73c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548023894 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.3548023894
Directory /workspace/31.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.2482009044
Short name T899
Test name
Test status
Simulation time 54580826 ps
CPU time 22.24 seconds
Started Aug 02 07:58:24 PM PDT 24
Finished Aug 02 07:58:46 PM PDT 24
Peak memory 574656 kb
Host smart-ac9da206-7f8c-45f4-8701-d857e3d9996c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482009044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all
_with_rand_reset.2482009044
Directory /workspace/31.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.366623293
Short name T2555
Test name
Test status
Simulation time 10190825099 ps
CPU time 502.78 seconds
Started Aug 02 07:58:37 PM PDT 24
Finished Aug 02 08:07:00 PM PDT 24
Peak memory 576804 kb
Host smart-96d60cc8-d471-4e5d-98c3-995274400f2b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366623293 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all
_with_reset_error.366623293
Directory /workspace/31.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_unmapped_addr.1405950324
Short name T2707
Test name
Test status
Simulation time 751366462 ps
CPU time 36.92 seconds
Started Aug 02 07:58:24 PM PDT 24
Finished Aug 02 07:59:01 PM PDT 24
Peak memory 575776 kb
Host smart-8b0f07ee-67eb-423e-8a32-1f831ea641da
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405950324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.1405950324
Directory /workspace/31.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_access_same_device.323477024
Short name T847
Test name
Test status
Simulation time 1188236072 ps
CPU time 53.25 seconds
Started Aug 02 07:58:37 PM PDT 24
Finished Aug 02 07:59:30 PM PDT 24
Peak memory 575916 kb
Host smart-0f6d7a0a-8e14-4935-85bf-924f88039e96
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323477024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.
323477024
Directory /workspace/32.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.3405209913
Short name T863
Test name
Test status
Simulation time 9190418036 ps
CPU time 147.9 seconds
Started Aug 02 07:58:35 PM PDT 24
Finished Aug 02 08:01:03 PM PDT 24
Peak memory 573904 kb
Host smart-e1c25ec4-7307-4761-82a6-6db8813ae3c4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405209913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_
device_slow_rsp.3405209913
Directory /workspace/32.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.4091853905
Short name T2423
Test name
Test status
Simulation time 96291156 ps
CPU time 11.59 seconds
Started Aug 02 07:58:35 PM PDT 24
Finished Aug 02 07:58:47 PM PDT 24
Peak memory 575984 kb
Host smart-941c7a7d-fa4a-449b-8ee0-b150279e8cf1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091853905 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_add
r.4091853905
Directory /workspace/32.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_error_random.3183605763
Short name T1598
Test name
Test status
Simulation time 2350251385 ps
CPU time 76.14 seconds
Started Aug 02 07:58:39 PM PDT 24
Finished Aug 02 07:59:55 PM PDT 24
Peak memory 575912 kb
Host smart-73bce10a-cee9-4195-9a4a-9b268f341553
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183605763 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.3183605763
Directory /workspace/32.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_random.3031948241
Short name T2871
Test name
Test status
Simulation time 1745421119 ps
CPU time 55.8 seconds
Started Aug 02 07:58:40 PM PDT 24
Finished Aug 02 07:59:36 PM PDT 24
Peak memory 575868 kb
Host smart-739161f5-43c0-491c-8e01-0f0dc3842707
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031948241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random.3031948241
Directory /workspace/32.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_random_large_delays.3785730295
Short name T2814
Test name
Test status
Simulation time 72402273825 ps
CPU time 725.23 seconds
Started Aug 02 07:58:40 PM PDT 24
Finished Aug 02 08:10:45 PM PDT 24
Peak memory 575840 kb
Host smart-56ea8097-4398-4cbf-91e2-db5bfa779902
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785730295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.3785730295
Directory /workspace/32.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.2361738892
Short name T1864
Test name
Test status
Simulation time 9825687721 ps
CPU time 162.85 seconds
Started Aug 02 07:58:35 PM PDT 24
Finished Aug 02 08:01:18 PM PDT 24
Peak memory 575972 kb
Host smart-4a88ef9c-f11a-4793-9802-adfd114d5d62
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361738892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.2361738892
Directory /workspace/32.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.1749546579
Short name T2863
Test name
Test status
Simulation time 448017487 ps
CPU time 36.84 seconds
Started Aug 02 07:58:38 PM PDT 24
Finished Aug 02 07:59:15 PM PDT 24
Peak memory 575912 kb
Host smart-018a8868-0cf8-44da-8cc9-d87792deb6f6
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749546579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_del
ays.1749546579
Directory /workspace/32.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_same_source.1104537895
Short name T2625
Test name
Test status
Simulation time 35022928 ps
CPU time 6.2 seconds
Started Aug 02 07:58:35 PM PDT 24
Finished Aug 02 07:58:42 PM PDT 24
Peak memory 574548 kb
Host smart-9a1544c6-c7da-4df2-9095-1867db53bca6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104537895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.1104537895
Directory /workspace/32.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_smoke.1281402795
Short name T1445
Test name
Test status
Simulation time 47443355 ps
CPU time 6.48 seconds
Started Aug 02 07:58:37 PM PDT 24
Finished Aug 02 07:58:43 PM PDT 24
Peak memory 573848 kb
Host smart-d9de04a3-1630-4b31-8e20-fc681284cd8f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281402795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.1281402795
Directory /workspace/32.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.4278056924
Short name T2848
Test name
Test status
Simulation time 10606763016 ps
CPU time 106.91 seconds
Started Aug 02 07:58:35 PM PDT 24
Finished Aug 02 08:00:22 PM PDT 24
Peak memory 574576 kb
Host smart-6f3b542b-d6b9-4111-bf7d-bd1cb2d00ecb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278056924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.4278056924
Directory /workspace/32.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.1779099517
Short name T1428
Test name
Test status
Simulation time 4428569170 ps
CPU time 73.29 seconds
Started Aug 02 07:58:38 PM PDT 24
Finished Aug 02 07:59:52 PM PDT 24
Peak memory 573884 kb
Host smart-d315303d-d6b6-4f43-bede-ebed86ad009f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779099517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.1779099517
Directory /workspace/32.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.1789356096
Short name T1552
Test name
Test status
Simulation time 50722982 ps
CPU time 6.81 seconds
Started Aug 02 07:58:35 PM PDT 24
Finished Aug 02 07:58:42 PM PDT 24
Peak memory 573844 kb
Host smart-d054980b-a460-4d6c-a8de-76c959c6dd22
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789356096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delay
s.1789356096
Directory /workspace/32.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_stress_all.3805142312
Short name T2469
Test name
Test status
Simulation time 2965888821 ps
CPU time 114.92 seconds
Started Aug 02 07:58:36 PM PDT 24
Finished Aug 02 08:00:31 PM PDT 24
Peak memory 576004 kb
Host smart-dc59d333-5922-4a40-914d-8e2615d1db52
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805142312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.3805142312
Directory /workspace/32.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.2866594358
Short name T1748
Test name
Test status
Simulation time 6575363204 ps
CPU time 253.44 seconds
Started Aug 02 07:58:37 PM PDT 24
Finished Aug 02 08:02:50 PM PDT 24
Peak memory 576092 kb
Host smart-f678018f-5759-4645-8bce-49bd00828339
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866594358 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.2866594358
Directory /workspace/32.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.2660630947
Short name T1544
Test name
Test status
Simulation time 494879636 ps
CPU time 196.95 seconds
Started Aug 02 07:58:38 PM PDT 24
Finished Aug 02 08:01:55 PM PDT 24
Peak memory 575948 kb
Host smart-9200aa98-8178-4cd1-9bb6-67c010ebfaba
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660630947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all
_with_rand_reset.2660630947
Directory /workspace/32.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_unmapped_addr.201631300
Short name T2029
Test name
Test status
Simulation time 1210317923 ps
CPU time 58.69 seconds
Started Aug 02 07:58:35 PM PDT 24
Finished Aug 02 07:59:34 PM PDT 24
Peak memory 575892 kb
Host smart-bd931143-f416-47d4-91df-fe70933b446d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201631300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.201631300
Directory /workspace/32.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_access_same_device.2243432457
Short name T2112
Test name
Test status
Simulation time 16195916 ps
CPU time 6.86 seconds
Started Aug 02 07:58:48 PM PDT 24
Finished Aug 02 07:58:55 PM PDT 24
Peak memory 573908 kb
Host smart-6a8e3926-6bc4-40d3-aefc-2f07885a35e9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243432457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device
.2243432457
Directory /workspace/33.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.2652158849
Short name T868
Test name
Test status
Simulation time 117572138720 ps
CPU time 2299.57 seconds
Started Aug 02 07:58:47 PM PDT 24
Finished Aug 02 08:37:07 PM PDT 24
Peak memory 575992 kb
Host smart-c9e8cf8f-65ed-46c0-8ddc-f0b17e7cef36
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652158849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_
device_slow_rsp.2652158849
Directory /workspace/33.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.1009184725
Short name T2802
Test name
Test status
Simulation time 770014698 ps
CPU time 31.59 seconds
Started Aug 02 07:58:47 PM PDT 24
Finished Aug 02 07:59:19 PM PDT 24
Peak memory 575868 kb
Host smart-59312d28-36d9-4d6a-9187-3d8090cd099e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009184725 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_add
r.1009184725
Directory /workspace/33.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_error_random.990885110
Short name T1828
Test name
Test status
Simulation time 414783197 ps
CPU time 18.21 seconds
Started Aug 02 07:58:46 PM PDT 24
Finished Aug 02 07:59:05 PM PDT 24
Peak memory 575904 kb
Host smart-3288484a-7b1e-43e0-8ac8-aadb106fb2a1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990885110 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.990885110
Directory /workspace/33.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_random.3001924707
Short name T2340
Test name
Test status
Simulation time 127047853 ps
CPU time 13.92 seconds
Started Aug 02 07:58:47 PM PDT 24
Finished Aug 02 07:59:01 PM PDT 24
Peak memory 575948 kb
Host smart-57468975-5481-408d-a306-6a9eb53fcca4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001924707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random.3001924707
Directory /workspace/33.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_random_large_delays.977425496
Short name T1896
Test name
Test status
Simulation time 39169286372 ps
CPU time 416.1 seconds
Started Aug 02 07:58:51 PM PDT 24
Finished Aug 02 08:05:47 PM PDT 24
Peak memory 576828 kb
Host smart-c9770880-09f7-4fa7-ac64-f09724d7bdfd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977425496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.977425496
Directory /workspace/33.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.4228608375
Short name T1993
Test name
Test status
Simulation time 61915597791 ps
CPU time 1109.14 seconds
Started Aug 02 07:58:49 PM PDT 24
Finished Aug 02 08:17:19 PM PDT 24
Peak memory 576040 kb
Host smart-12dc0fa3-2b86-473e-bbae-42e8067b53ce
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228608375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.4228608375
Directory /workspace/33.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.1467044109
Short name T2627
Test name
Test status
Simulation time 553306761 ps
CPU time 53.21 seconds
Started Aug 02 07:58:48 PM PDT 24
Finished Aug 02 07:59:42 PM PDT 24
Peak memory 575992 kb
Host smart-2f38832f-b9b6-4620-9950-63484f62a5bd
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467044109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_del
ays.1467044109
Directory /workspace/33.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_same_source.1611870011
Short name T2200
Test name
Test status
Simulation time 1060088872 ps
CPU time 32.82 seconds
Started Aug 02 07:58:50 PM PDT 24
Finished Aug 02 07:59:23 PM PDT 24
Peak memory 575776 kb
Host smart-c3a6148e-62a9-4060-8900-677efbc1a92a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611870011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.1611870011
Directory /workspace/33.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_smoke.2604864435
Short name T2250
Test name
Test status
Simulation time 42229046 ps
CPU time 6.11 seconds
Started Aug 02 07:58:51 PM PDT 24
Finished Aug 02 07:58:57 PM PDT 24
Peak memory 574528 kb
Host smart-f5db4277-738a-45d9-827e-10b34367537f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604864435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.2604864435
Directory /workspace/33.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_smoke_large_delays.2358423963
Short name T1913
Test name
Test status
Simulation time 5229931232 ps
CPU time 53.85 seconds
Started Aug 02 07:58:48 PM PDT 24
Finished Aug 02 07:59:42 PM PDT 24
Peak memory 573936 kb
Host smart-c74dbb3a-fd72-4fce-ab85-b4a9d8c66ecd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358423963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.2358423963
Directory /workspace/33.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.2811639857
Short name T1408
Test name
Test status
Simulation time 5041034271 ps
CPU time 89.62 seconds
Started Aug 02 07:58:49 PM PDT 24
Finished Aug 02 08:00:19 PM PDT 24
Peak memory 574584 kb
Host smart-dc81c230-5772-4642-a9df-5b26d2bf0acd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811639857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.2811639857
Directory /workspace/33.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_smoke_zero_delays.1944444995
Short name T2439
Test name
Test status
Simulation time 38858238 ps
CPU time 5.73 seconds
Started Aug 02 07:58:51 PM PDT 24
Finished Aug 02 07:58:56 PM PDT 24
Peak memory 573816 kb
Host smart-25c4c88b-1ac9-46d5-8fda-772dd754cc4e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944444995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delay
s.1944444995
Directory /workspace/33.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_stress_all.876527745
Short name T2298
Test name
Test status
Simulation time 3164847562 ps
CPU time 227.02 seconds
Started Aug 02 07:58:49 PM PDT 24
Finished Aug 02 08:02:36 PM PDT 24
Peak memory 576780 kb
Host smart-529cb674-d78f-45a3-b029-78104685a098
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876527745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.876527745
Directory /workspace/33.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.3879320803
Short name T2686
Test name
Test status
Simulation time 3590105952 ps
CPU time 254.71 seconds
Started Aug 02 07:58:51 PM PDT 24
Finished Aug 02 08:03:06 PM PDT 24
Peak memory 575980 kb
Host smart-87e7a78a-17ac-449e-98ed-2a7b2e4bb8bd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879320803 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.3879320803
Directory /workspace/33.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.3439509632
Short name T2670
Test name
Test status
Simulation time 120896102 ps
CPU time 38.71 seconds
Started Aug 02 07:58:47 PM PDT 24
Finished Aug 02 07:59:26 PM PDT 24
Peak memory 576468 kb
Host smart-fcb2a510-9c70-4a47-836f-53108138bbf2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439509632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all
_with_rand_reset.3439509632
Directory /workspace/33.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.2078959106
Short name T2119
Test name
Test status
Simulation time 1735183948 ps
CPU time 238.95 seconds
Started Aug 02 07:58:51 PM PDT 24
Finished Aug 02 08:02:50 PM PDT 24
Peak memory 576824 kb
Host smart-19abb9a2-41f0-4c96-ac52-5ad9ee0771c8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078959106 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_al
l_with_reset_error.2078959106
Directory /workspace/33.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_unmapped_addr.2371203133
Short name T1619
Test name
Test status
Simulation time 72029807 ps
CPU time 9.96 seconds
Started Aug 02 07:58:51 PM PDT 24
Finished Aug 02 07:59:01 PM PDT 24
Peak memory 575824 kb
Host smart-c77d771f-7e74-4897-97a4-7755a3624556
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371203133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.2371203133
Directory /workspace/33.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_access_same_device.1492117156
Short name T835
Test name
Test status
Simulation time 1130447889 ps
CPU time 53.12 seconds
Started Aug 02 07:59:02 PM PDT 24
Finished Aug 02 07:59:55 PM PDT 24
Peak memory 575804 kb
Host smart-2aff6321-7329-4a91-beb6-826faa8616b0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492117156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device
.1492117156
Directory /workspace/34.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.966578809
Short name T2222
Test name
Test status
Simulation time 129441303948 ps
CPU time 2266.63 seconds
Started Aug 02 07:59:00 PM PDT 24
Finished Aug 02 08:36:48 PM PDT 24
Peak memory 575944 kb
Host smart-fe4d54db-f6c6-4158-b0aa-03168f84b7f8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966578809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_d
evice_slow_rsp.966578809
Directory /workspace/34.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.1337762846
Short name T1950
Test name
Test status
Simulation time 183412993 ps
CPU time 10.59 seconds
Started Aug 02 07:59:02 PM PDT 24
Finished Aug 02 07:59:13 PM PDT 24
Peak memory 575772 kb
Host smart-d0e0f0a4-2b75-4ac5-9696-6d8681967c56
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337762846 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_add
r.1337762846
Directory /workspace/34.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_error_random.3057939286
Short name T2914
Test name
Test status
Simulation time 2095573149 ps
CPU time 77.91 seconds
Started Aug 02 07:59:01 PM PDT 24
Finished Aug 02 08:00:19 PM PDT 24
Peak memory 575928 kb
Host smart-5ba812ed-e909-4f7a-ae64-87beae36c9fa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057939286 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.3057939286
Directory /workspace/34.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_random.1161395120
Short name T2070
Test name
Test status
Simulation time 1202693467 ps
CPU time 43.03 seconds
Started Aug 02 07:59:00 PM PDT 24
Finished Aug 02 07:59:44 PM PDT 24
Peak memory 575836 kb
Host smart-7e197f31-20ec-49e5-a716-8bc5031b820c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161395120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random.1161395120
Directory /workspace/34.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_random_large_delays.1274918876
Short name T1669
Test name
Test status
Simulation time 25523540455 ps
CPU time 270.55 seconds
Started Aug 02 07:59:03 PM PDT 24
Finished Aug 02 08:03:34 PM PDT 24
Peak memory 576036 kb
Host smart-3409dd6d-d802-4e49-9c1e-a97af5ee2c27
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274918876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.1274918876
Directory /workspace/34.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_random_slow_rsp.2091968807
Short name T1504
Test name
Test status
Simulation time 52849842192 ps
CPU time 905.28 seconds
Started Aug 02 07:59:01 PM PDT 24
Finished Aug 02 08:14:07 PM PDT 24
Peak memory 576032 kb
Host smart-515829d7-f209-47d2-89fb-25c7eb0775f7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091968807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.2091968807
Directory /workspace/34.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_random_zero_delays.3072041401
Short name T2470
Test name
Test status
Simulation time 360190350 ps
CPU time 33.25 seconds
Started Aug 02 07:59:00 PM PDT 24
Finished Aug 02 07:59:34 PM PDT 24
Peak memory 575800 kb
Host smart-ad9da2b0-308b-41ea-b4be-692811948435
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072041401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_del
ays.3072041401
Directory /workspace/34.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_same_source.3231849906
Short name T2641
Test name
Test status
Simulation time 487017648 ps
CPU time 37.61 seconds
Started Aug 02 07:59:00 PM PDT 24
Finished Aug 02 07:59:38 PM PDT 24
Peak memory 575748 kb
Host smart-6dfa1bc6-da62-4687-8cea-d2ab1d0e2d09
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231849906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.3231849906
Directory /workspace/34.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_smoke.3138856097
Short name T1824
Test name
Test status
Simulation time 210920572 ps
CPU time 9.56 seconds
Started Aug 02 07:58:48 PM PDT 24
Finished Aug 02 07:58:58 PM PDT 24
Peak memory 574644 kb
Host smart-f1bbee41-7085-4a8b-b725-6a88fce0fd09
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138856097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.3138856097
Directory /workspace/34.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_smoke_large_delays.1755851489
Short name T2903
Test name
Test status
Simulation time 4830884577 ps
CPU time 48.25 seconds
Started Aug 02 07:58:44 PM PDT 24
Finished Aug 02 07:59:32 PM PDT 24
Peak memory 573920 kb
Host smart-8f93b4f6-4925-4c60-a01f-f3e0be019daf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755851489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.1755851489
Directory /workspace/34.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.1501248088
Short name T2095
Test name
Test status
Simulation time 5189965779 ps
CPU time 86.97 seconds
Started Aug 02 07:58:48 PM PDT 24
Finished Aug 02 08:00:15 PM PDT 24
Peak memory 574568 kb
Host smart-9d437168-e38d-44a5-88ac-c823187a329a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501248088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.1501248088
Directory /workspace/34.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_smoke_zero_delays.1175751641
Short name T2839
Test name
Test status
Simulation time 45546994 ps
CPU time 6.39 seconds
Started Aug 02 07:58:47 PM PDT 24
Finished Aug 02 07:58:53 PM PDT 24
Peak memory 573800 kb
Host smart-c29bb206-b47e-4168-833a-142e86518e88
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175751641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delay
s.1175751641
Directory /workspace/34.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_stress_all.3960450683
Short name T520
Test name
Test status
Simulation time 2751514443 ps
CPU time 204.28 seconds
Started Aug 02 07:59:01 PM PDT 24
Finished Aug 02 08:02:25 PM PDT 24
Peak memory 575996 kb
Host smart-12c27d06-f342-453e-ab36-c27b06c4640d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960450683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.3960450683
Directory /workspace/34.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.2788240719
Short name T2326
Test name
Test status
Simulation time 3156594028 ps
CPU time 248.39 seconds
Started Aug 02 07:59:01 PM PDT 24
Finished Aug 02 08:03:10 PM PDT 24
Peak memory 576132 kb
Host smart-b21a9116-af23-46ac-b38e-287e4cedc65a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788240719 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.2788240719
Directory /workspace/34.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.2498232564
Short name T2800
Test name
Test status
Simulation time 5500055145 ps
CPU time 275.63 seconds
Started Aug 02 07:59:01 PM PDT 24
Finished Aug 02 08:03:37 PM PDT 24
Peak memory 576720 kb
Host smart-03c2fa69-5269-49f2-a6f6-61c065376d5c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498232564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all
_with_rand_reset.2498232564
Directory /workspace/34.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.2563412399
Short name T1603
Test name
Test status
Simulation time 255621293 ps
CPU time 79.23 seconds
Started Aug 02 07:59:02 PM PDT 24
Finished Aug 02 08:00:21 PM PDT 24
Peak memory 576720 kb
Host smart-f97accac-4eb8-43dd-89da-74fee6773b02
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563412399 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_al
l_with_reset_error.2563412399
Directory /workspace/34.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_unmapped_addr.505790465
Short name T2708
Test name
Test status
Simulation time 934949244 ps
CPU time 39.21 seconds
Started Aug 02 07:59:03 PM PDT 24
Finished Aug 02 07:59:42 PM PDT 24
Peak memory 575840 kb
Host smart-8193d248-b447-4c00-8720-c1e9e3b17865
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505790465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.505790465
Directory /workspace/34.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_access_same_device.793369771
Short name T2475
Test name
Test status
Simulation time 943907050 ps
CPU time 67.25 seconds
Started Aug 02 07:59:15 PM PDT 24
Finished Aug 02 08:00:23 PM PDT 24
Peak memory 575880 kb
Host smart-d9cdd18b-49db-45fb-b072-39f5d46e21bc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793369771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.
793369771
Directory /workspace/35.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.1655812841
Short name T860
Test name
Test status
Simulation time 65926904678 ps
CPU time 1066.98 seconds
Started Aug 02 07:59:14 PM PDT 24
Finished Aug 02 08:17:01 PM PDT 24
Peak memory 575968 kb
Host smart-aca6e6a7-38b3-42d7-ac1d-d1c1b2b1bf6a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655812841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_
device_slow_rsp.1655812841
Directory /workspace/35.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.3853364127
Short name T2749
Test name
Test status
Simulation time 39699952 ps
CPU time 6.86 seconds
Started Aug 02 07:59:16 PM PDT 24
Finished Aug 02 07:59:23 PM PDT 24
Peak memory 573860 kb
Host smart-6edc6219-f2ab-476f-877a-f8c231b616ac
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853364127 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_add
r.3853364127
Directory /workspace/35.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_error_random.1045692902
Short name T1848
Test name
Test status
Simulation time 811526647 ps
CPU time 30.27 seconds
Started Aug 02 07:59:15 PM PDT 24
Finished Aug 02 07:59:45 PM PDT 24
Peak memory 575880 kb
Host smart-07378407-b28b-4377-9447-7fa4ac4f103e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045692902 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.1045692902
Directory /workspace/35.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_random.3947642291
Short name T477
Test name
Test status
Simulation time 2253521646 ps
CPU time 81.82 seconds
Started Aug 02 07:59:16 PM PDT 24
Finished Aug 02 08:00:38 PM PDT 24
Peak memory 576076 kb
Host smart-9f7e2df6-31ec-4f9a-a251-a9d2a6dc9b81
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947642291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random.3947642291
Directory /workspace/35.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_random_large_delays.3659563648
Short name T2745
Test name
Test status
Simulation time 99539039119 ps
CPU time 1112.75 seconds
Started Aug 02 07:59:16 PM PDT 24
Finished Aug 02 08:17:50 PM PDT 24
Peak memory 576016 kb
Host smart-83108c99-102f-4602-b086-3488038657f3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659563648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.3659563648
Directory /workspace/35.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_random_slow_rsp.150436884
Short name T1665
Test name
Test status
Simulation time 62562651180 ps
CPU time 1068.24 seconds
Started Aug 02 07:59:18 PM PDT 24
Finished Aug 02 08:17:06 PM PDT 24
Peak memory 576024 kb
Host smart-823f13b3-7b8d-47f4-8e3c-c1b7d523c07f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150436884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.150436884
Directory /workspace/35.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_random_zero_delays.299535325
Short name T1456
Test name
Test status
Simulation time 40611689 ps
CPU time 6.1 seconds
Started Aug 02 07:59:18 PM PDT 24
Finished Aug 02 07:59:24 PM PDT 24
Peak memory 573832 kb
Host smart-7718324a-b03e-4f49-a72d-3dfd01953794
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299535325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_dela
ys.299535325
Directory /workspace/35.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_same_source.3582220862
Short name T641
Test name
Test status
Simulation time 1815341843 ps
CPU time 47.58 seconds
Started Aug 02 07:59:14 PM PDT 24
Finished Aug 02 08:00:02 PM PDT 24
Peak memory 575800 kb
Host smart-a7629e4e-c1ad-4834-b85c-4d6795925798
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582220862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.3582220862
Directory /workspace/35.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_smoke.1778522911
Short name T2296
Test name
Test status
Simulation time 50459201 ps
CPU time 7.05 seconds
Started Aug 02 07:59:01 PM PDT 24
Finished Aug 02 07:59:08 PM PDT 24
Peak memory 573816 kb
Host smart-85ca259c-84a3-466c-aaca-aab136d1e5ea
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778522911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.1778522911
Directory /workspace/35.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_smoke_large_delays.1150567450
Short name T2449
Test name
Test status
Simulation time 6485107176 ps
CPU time 67.99 seconds
Started Aug 02 07:59:18 PM PDT 24
Finished Aug 02 08:00:26 PM PDT 24
Peak memory 573920 kb
Host smart-22624cfa-b7f1-4e5a-9ffa-91e165ddcdbe
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150567450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.1150567450
Directory /workspace/35.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.1780863003
Short name T2220
Test name
Test status
Simulation time 5736408770 ps
CPU time 103.69 seconds
Started Aug 02 07:59:15 PM PDT 24
Finished Aug 02 08:00:59 PM PDT 24
Peak memory 574676 kb
Host smart-9cca8926-f495-4c89-8af8-17f8b4d8982a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780863003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.1780863003
Directory /workspace/35.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.2758080398
Short name T2031
Test name
Test status
Simulation time 48534479 ps
CPU time 6.36 seconds
Started Aug 02 07:59:16 PM PDT 24
Finished Aug 02 07:59:23 PM PDT 24
Peak memory 573776 kb
Host smart-b96721e2-d9da-4a7e-b1d6-12e6caa651d8
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758080398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delay
s.2758080398
Directory /workspace/35.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_stress_all.2063872261
Short name T512
Test name
Test status
Simulation time 3358285982 ps
CPU time 147.2 seconds
Started Aug 02 07:59:14 PM PDT 24
Finished Aug 02 08:01:41 PM PDT 24
Peak memory 576008 kb
Host smart-b8843bfd-8ec5-49c0-85fd-21310f4e3f08
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063872261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.2063872261
Directory /workspace/35.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.3739836252
Short name T2820
Test name
Test status
Simulation time 14343989068 ps
CPU time 534.78 seconds
Started Aug 02 07:59:27 PM PDT 24
Finished Aug 02 08:08:22 PM PDT 24
Peak memory 576120 kb
Host smart-954e5863-1217-46b3-ba2a-d5727ef600b7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739836252 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.3739836252
Directory /workspace/35.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.1839213921
Short name T1664
Test name
Test status
Simulation time 44858860 ps
CPU time 9.52 seconds
Started Aug 02 07:59:32 PM PDT 24
Finished Aug 02 07:59:41 PM PDT 24
Peak memory 573888 kb
Host smart-b455b57e-c2aa-4985-8c1f-c93723b3a975
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839213921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all
_with_rand_reset.1839213921
Directory /workspace/35.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.515201832
Short name T854
Test name
Test status
Simulation time 7872350906 ps
CPU time 469.82 seconds
Started Aug 02 07:59:26 PM PDT 24
Finished Aug 02 08:07:16 PM PDT 24
Peak memory 576792 kb
Host smart-c1745512-851e-4ec4-a8bb-32b059bd4c74
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515201832 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all
_with_reset_error.515201832
Directory /workspace/35.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_unmapped_addr.1731772176
Short name T1715
Test name
Test status
Simulation time 237776633 ps
CPU time 12.25 seconds
Started Aug 02 07:59:15 PM PDT 24
Finished Aug 02 07:59:28 PM PDT 24
Peak memory 575960 kb
Host smart-0d90d4c0-ed31-4633-8ff1-be6242fe39a8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731772176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.1731772176
Directory /workspace/35.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_access_same_device.2862739884
Short name T550
Test name
Test status
Simulation time 770287893 ps
CPU time 63.49 seconds
Started Aug 02 07:59:29 PM PDT 24
Finished Aug 02 08:00:32 PM PDT 24
Peak memory 575940 kb
Host smart-f11bb657-8951-48bb-bca4-964bbb48ae37
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862739884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device
.2862739884
Directory /workspace/36.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.1080249904
Short name T1963
Test name
Test status
Simulation time 138321963685 ps
CPU time 2414.87 seconds
Started Aug 02 07:59:29 PM PDT 24
Finished Aug 02 08:39:44 PM PDT 24
Peak memory 576020 kb
Host smart-47efdad4-0467-41bd-94be-bfb240feafee
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080249904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_
device_slow_rsp.1080249904
Directory /workspace/36.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.113558380
Short name T2681
Test name
Test status
Simulation time 564445580 ps
CPU time 25.02 seconds
Started Aug 02 07:59:26 PM PDT 24
Finished Aug 02 07:59:51 PM PDT 24
Peak memory 575760 kb
Host smart-a97807aa-6a7d-4a86-82fa-45d23935a135
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113558380 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr
.113558380
Directory /workspace/36.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_error_random.4119980687
Short name T1895
Test name
Test status
Simulation time 1338897020 ps
CPU time 48.68 seconds
Started Aug 02 07:59:28 PM PDT 24
Finished Aug 02 08:00:17 PM PDT 24
Peak memory 575820 kb
Host smart-4fa09c05-d2b7-4a40-82f1-72dcac2213f2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119980687 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.4119980687
Directory /workspace/36.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_random.2537512668
Short name T2913
Test name
Test status
Simulation time 457287457 ps
CPU time 37.63 seconds
Started Aug 02 07:59:27 PM PDT 24
Finished Aug 02 08:00:04 PM PDT 24
Peak memory 575968 kb
Host smart-45c7e9eb-a114-4d88-a17f-0853922edc60
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537512668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random.2537512668
Directory /workspace/36.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_random_large_delays.1270581775
Short name T2173
Test name
Test status
Simulation time 82098522193 ps
CPU time 881.6 seconds
Started Aug 02 07:59:27 PM PDT 24
Finished Aug 02 08:14:08 PM PDT 24
Peak memory 576016 kb
Host smart-a9aa4622-132c-4042-bb0e-6ccd3a1fafc2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270581775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.1270581775
Directory /workspace/36.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.936532048
Short name T1888
Test name
Test status
Simulation time 37061866442 ps
CPU time 646.74 seconds
Started Aug 02 07:59:26 PM PDT 24
Finished Aug 02 08:10:13 PM PDT 24
Peak memory 576008 kb
Host smart-9d27414e-3d81-496a-9658-3f4732bcd32c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936532048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.936532048
Directory /workspace/36.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.3815363861
Short name T2047
Test name
Test status
Simulation time 393309919 ps
CPU time 34.73 seconds
Started Aug 02 07:59:32 PM PDT 24
Finished Aug 02 08:00:06 PM PDT 24
Peak memory 575900 kb
Host smart-8439ab38-7dd0-4cb6-8efe-0a7a9c8aa625
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815363861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_del
ays.3815363861
Directory /workspace/36.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_same_source.2946701011
Short name T2822
Test name
Test status
Simulation time 132887837 ps
CPU time 11.71 seconds
Started Aug 02 07:59:33 PM PDT 24
Finished Aug 02 07:59:45 PM PDT 24
Peak memory 575928 kb
Host smart-ff8dae30-8d03-4d6e-bb8d-679baf552011
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946701011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.2946701011
Directory /workspace/36.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_smoke.373760137
Short name T1419
Test name
Test status
Simulation time 36424987 ps
CPU time 5.76 seconds
Started Aug 02 07:59:28 PM PDT 24
Finished Aug 02 07:59:34 PM PDT 24
Peak memory 574500 kb
Host smart-9ea27d02-26d4-4e9f-af8d-bf0493a22d10
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373760137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.373760137
Directory /workspace/36.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_smoke_large_delays.125757778
Short name T1942
Test name
Test status
Simulation time 6976206756 ps
CPU time 74.53 seconds
Started Aug 02 07:59:29 PM PDT 24
Finished Aug 02 08:00:43 PM PDT 24
Peak memory 573980 kb
Host smart-f559db94-325f-4b14-af95-8fc486ab7346
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125757778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.125757778
Directory /workspace/36.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.534435864
Short name T1713
Test name
Test status
Simulation time 4036270871 ps
CPU time 65.59 seconds
Started Aug 02 07:59:29 PM PDT 24
Finished Aug 02 08:00:34 PM PDT 24
Peak memory 573992 kb
Host smart-251ee779-5d2b-4888-81fd-ba6ce13df7ac
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534435864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.534435864
Directory /workspace/36.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_smoke_zero_delays.997842299
Short name T2019
Test name
Test status
Simulation time 47106338 ps
CPU time 6.04 seconds
Started Aug 02 07:59:29 PM PDT 24
Finished Aug 02 07:59:35 PM PDT 24
Peak memory 573836 kb
Host smart-e29bb271-25a6-4dda-9ee4-350f16e8e3c3
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997842299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays
.997842299
Directory /workspace/36.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_stress_all.3080248632
Short name T1519
Test name
Test status
Simulation time 692060032 ps
CPU time 31.6 seconds
Started Aug 02 07:59:29 PM PDT 24
Finished Aug 02 08:00:00 PM PDT 24
Peak memory 575872 kb
Host smart-d91463ab-2db8-45ad-ad87-8bd2c5b33003
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080248632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.3080248632
Directory /workspace/36.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_error.4130585248
Short name T2307
Test name
Test status
Simulation time 1604151710 ps
CPU time 46.15 seconds
Started Aug 02 07:59:30 PM PDT 24
Finished Aug 02 08:00:16 PM PDT 24
Peak memory 575948 kb
Host smart-6ae10eb8-f2cc-464c-8878-682d41e62e6b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130585248 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.4130585248
Directory /workspace/36.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.2765448765
Short name T2042
Test name
Test status
Simulation time 450902020 ps
CPU time 200.89 seconds
Started Aug 02 07:59:23 PM PDT 24
Finished Aug 02 08:02:44 PM PDT 24
Peak memory 576736 kb
Host smart-87ececcc-3112-4348-a24d-584afd78ada7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765448765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all
_with_rand_reset.2765448765
Directory /workspace/36.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.1735700383
Short name T1924
Test name
Test status
Simulation time 234217705 ps
CPU time 66.62 seconds
Started Aug 02 07:59:27 PM PDT 24
Finished Aug 02 08:00:34 PM PDT 24
Peak memory 576764 kb
Host smart-e571a3e5-48a0-4446-8e44-63503ae4a186
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735700383 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_al
l_with_reset_error.1735700383
Directory /workspace/36.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_unmapped_addr.2457984230
Short name T615
Test name
Test status
Simulation time 1446742891 ps
CPU time 59.66 seconds
Started Aug 02 07:59:27 PM PDT 24
Finished Aug 02 08:00:26 PM PDT 24
Peak memory 575904 kb
Host smart-23384d68-9ded-4bf0-a62d-5502c06e11cc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457984230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.2457984230
Directory /workspace/36.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_access_same_device.3330051712
Short name T2383
Test name
Test status
Simulation time 3258541448 ps
CPU time 133.02 seconds
Started Aug 02 07:59:40 PM PDT 24
Finished Aug 02 08:01:53 PM PDT 24
Peak memory 575860 kb
Host smart-9236233a-7bf3-4f99-b12f-8b7dfdcba468
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330051712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device
.3330051712
Directory /workspace/37.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.470970724
Short name T841
Test name
Test status
Simulation time 35893613893 ps
CPU time 634.63 seconds
Started Aug 02 07:59:42 PM PDT 24
Finished Aug 02 08:10:16 PM PDT 24
Peak memory 576084 kb
Host smart-8dc1541c-2d88-454a-801f-ae20f2cd71d8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470970724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_d
evice_slow_rsp.470970724
Directory /workspace/37.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.2808519780
Short name T2321
Test name
Test status
Simulation time 877522773 ps
CPU time 34.56 seconds
Started Aug 02 07:59:40 PM PDT 24
Finished Aug 02 08:00:15 PM PDT 24
Peak memory 575980 kb
Host smart-5304ca24-e028-4ef6-9300-b4525f808b3a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808519780 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_add
r.2808519780
Directory /workspace/37.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_error_random.801523600
Short name T1867
Test name
Test status
Simulation time 96293609 ps
CPU time 9.75 seconds
Started Aug 02 07:59:40 PM PDT 24
Finished Aug 02 07:59:50 PM PDT 24
Peak memory 575660 kb
Host smart-e71de2eb-a038-4120-b890-37d490899a39
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801523600 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.801523600
Directory /workspace/37.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_random.3779558919
Short name T2138
Test name
Test status
Simulation time 540071686 ps
CPU time 20.11 seconds
Started Aug 02 07:59:33 PM PDT 24
Finished Aug 02 07:59:54 PM PDT 24
Peak memory 575804 kb
Host smart-09bbaaef-d7c1-4eea-b1b0-c867ec7f2dc4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779558919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random.3779558919
Directory /workspace/37.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_random_large_delays.804628648
Short name T671
Test name
Test status
Simulation time 106849093534 ps
CPU time 1122.54 seconds
Started Aug 02 07:59:41 PM PDT 24
Finished Aug 02 08:18:24 PM PDT 24
Peak memory 576056 kb
Host smart-d50707fc-aa48-4102-8977-9ea3b9ac0d61
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804628648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.804628648
Directory /workspace/37.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_random_slow_rsp.148034845
Short name T1653
Test name
Test status
Simulation time 20577021628 ps
CPU time 351.76 seconds
Started Aug 02 07:59:40 PM PDT 24
Finished Aug 02 08:05:32 PM PDT 24
Peak memory 575868 kb
Host smart-bbdd9423-1c4d-4e1c-987d-766710231104
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148034845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.148034845
Directory /workspace/37.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.807186818
Short name T2252
Test name
Test status
Simulation time 545234726 ps
CPU time 42.87 seconds
Started Aug 02 07:59:40 PM PDT 24
Finished Aug 02 08:00:23 PM PDT 24
Peak memory 575960 kb
Host smart-d2f1b8d7-9763-4011-9050-53f3d1195c5f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807186818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_dela
ys.807186818
Directory /workspace/37.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_same_source.2241208609
Short name T476
Test name
Test status
Simulation time 500600593 ps
CPU time 35.63 seconds
Started Aug 02 07:59:44 PM PDT 24
Finished Aug 02 08:00:19 PM PDT 24
Peak memory 575832 kb
Host smart-a97eb654-4344-42b8-95b7-eacdf7918ebe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241208609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.2241208609
Directory /workspace/37.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_smoke.1898565401
Short name T2402
Test name
Test status
Simulation time 226394962 ps
CPU time 10.57 seconds
Started Aug 02 07:59:26 PM PDT 24
Finished Aug 02 07:59:36 PM PDT 24
Peak memory 574508 kb
Host smart-4134ecd0-79c9-4529-ab66-6c2469584ae3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898565401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.1898565401
Directory /workspace/37.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_smoke_large_delays.3048291529
Short name T2640
Test name
Test status
Simulation time 8397920729 ps
CPU time 87.79 seconds
Started Aug 02 07:59:29 PM PDT 24
Finished Aug 02 08:00:57 PM PDT 24
Peak memory 573960 kb
Host smart-f3512346-7d40-45bd-bba2-42f7b110dbcf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048291529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.3048291529
Directory /workspace/37.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.625243694
Short name T2842
Test name
Test status
Simulation time 5688620326 ps
CPU time 98.18 seconds
Started Aug 02 07:59:28 PM PDT 24
Finished Aug 02 08:01:07 PM PDT 24
Peak memory 573868 kb
Host smart-3845c8c7-4481-47d8-a552-6141cd23159f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625243694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.625243694
Directory /workspace/37.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_smoke_zero_delays.1241573982
Short name T2756
Test name
Test status
Simulation time 35698708 ps
CPU time 5.58 seconds
Started Aug 02 07:59:30 PM PDT 24
Finished Aug 02 07:59:35 PM PDT 24
Peak memory 574520 kb
Host smart-cd3c3eb0-8af9-41e0-9eb4-2031830c8d9d
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241573982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delay
s.1241573982
Directory /workspace/37.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_stress_all.2610290212
Short name T519
Test name
Test status
Simulation time 2222436472 ps
CPU time 184.97 seconds
Started Aug 02 07:59:40 PM PDT 24
Finished Aug 02 08:02:45 PM PDT 24
Peak memory 576044 kb
Host smart-c7c532c9-7d6f-46dd-b3b0-238c63a155ba
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610290212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.2610290212
Directory /workspace/37.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.3037993208
Short name T2653
Test name
Test status
Simulation time 13575200463 ps
CPU time 529.82 seconds
Started Aug 02 07:59:39 PM PDT 24
Finished Aug 02 08:08:29 PM PDT 24
Peak memory 576092 kb
Host smart-04cf4f47-3e3f-4d4d-85cb-011ec8413207
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037993208 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.3037993208
Directory /workspace/37.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.2362258776
Short name T2015
Test name
Test status
Simulation time 627011690 ps
CPU time 177.46 seconds
Started Aug 02 07:59:40 PM PDT 24
Finished Aug 02 08:02:38 PM PDT 24
Peak memory 576696 kb
Host smart-3c504074-4472-4287-a4f0-49edd2cd771f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362258776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all
_with_rand_reset.2362258776
Directory /workspace/37.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.2291435295
Short name T893
Test name
Test status
Simulation time 11549433063 ps
CPU time 642.68 seconds
Started Aug 02 07:59:42 PM PDT 24
Finished Aug 02 08:10:25 PM PDT 24
Peak memory 576992 kb
Host smart-ff46dffe-c291-4589-b3c0-a7a8200564e8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291435295 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_al
l_with_reset_error.2291435295
Directory /workspace/37.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_unmapped_addr.1683422105
Short name T2314
Test name
Test status
Simulation time 163202848 ps
CPU time 23.27 seconds
Started Aug 02 07:59:41 PM PDT 24
Finished Aug 02 08:00:04 PM PDT 24
Peak memory 576000 kb
Host smart-f53792b2-ab3f-4597-afa6-4d1344b1da3e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683422105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.1683422105
Directory /workspace/37.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_access_same_device.3004956612
Short name T2345
Test name
Test status
Simulation time 1855086064 ps
CPU time 74.27 seconds
Started Aug 02 07:59:40 PM PDT 24
Finished Aug 02 08:00:55 PM PDT 24
Peak memory 575800 kb
Host smart-11a2b57c-32f1-415c-9c14-a76c510efd9c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004956612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device
.3004956612
Directory /workspace/38.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.3231537634
Short name T2443
Test name
Test status
Simulation time 119116705358 ps
CPU time 2060.52 seconds
Started Aug 02 07:59:44 PM PDT 24
Finished Aug 02 08:34:04 PM PDT 24
Peak memory 575864 kb
Host smart-fffce9cc-8558-41ef-9df4-6fb5f9eb9a76
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231537634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_
device_slow_rsp.3231537634
Directory /workspace/38.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.1753863162
Short name T2143
Test name
Test status
Simulation time 681881835 ps
CPU time 28.6 seconds
Started Aug 02 07:59:41 PM PDT 24
Finished Aug 02 08:00:10 PM PDT 24
Peak memory 575744 kb
Host smart-e4a081fb-3b97-4a50-8796-8f6145838470
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753863162 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_add
r.1753863162
Directory /workspace/38.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_error_random.622503420
Short name T1902
Test name
Test status
Simulation time 670648991 ps
CPU time 25.92 seconds
Started Aug 02 07:59:44 PM PDT 24
Finished Aug 02 08:00:10 PM PDT 24
Peak memory 575936 kb
Host smart-610292c6-4975-4b0b-93de-7a0a10ae4607
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622503420 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.622503420
Directory /workspace/38.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_random.3391436917
Short name T2060
Test name
Test status
Simulation time 968718134 ps
CPU time 31.61 seconds
Started Aug 02 07:59:41 PM PDT 24
Finished Aug 02 08:00:12 PM PDT 24
Peak memory 575748 kb
Host smart-14cda556-4705-4560-b230-8adee5e77aa7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391436917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random.3391436917
Directory /workspace/38.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_random_large_delays.1603493951
Short name T2171
Test name
Test status
Simulation time 12006793347 ps
CPU time 127.69 seconds
Started Aug 02 07:59:41 PM PDT 24
Finished Aug 02 08:01:49 PM PDT 24
Peak memory 576048 kb
Host smart-4a78fd73-039c-44e4-be61-4362970eacbe
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603493951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.1603493951
Directory /workspace/38.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.3614130808
Short name T1672
Test name
Test status
Simulation time 23674672439 ps
CPU time 395.21 seconds
Started Aug 02 07:59:39 PM PDT 24
Finished Aug 02 08:06:15 PM PDT 24
Peak memory 575984 kb
Host smart-e8004590-d8c4-43e3-a438-15baaa507a3b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614130808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.3614130808
Directory /workspace/38.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.2642847110
Short name T2518
Test name
Test status
Simulation time 39328532 ps
CPU time 6.33 seconds
Started Aug 02 07:59:43 PM PDT 24
Finished Aug 02 07:59:50 PM PDT 24
Peak memory 574532 kb
Host smart-b07fd87e-40bf-41e6-9b10-6008ec97c49a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642847110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_del
ays.2642847110
Directory /workspace/38.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_same_source.959443868
Short name T2150
Test name
Test status
Simulation time 62833784 ps
CPU time 8.52 seconds
Started Aug 02 07:59:44 PM PDT 24
Finished Aug 02 07:59:53 PM PDT 24
Peak memory 575828 kb
Host smart-8b9e8770-47e1-44c0-bc5c-60e53e51f8d4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959443868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.959443868
Directory /workspace/38.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_smoke.2990602672
Short name T2159
Test name
Test status
Simulation time 198722019 ps
CPU time 9.52 seconds
Started Aug 02 07:59:42 PM PDT 24
Finished Aug 02 07:59:51 PM PDT 24
Peak memory 574492 kb
Host smart-c8e0838d-ad59-411b-9603-9764a9d4894c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990602672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.2990602672
Directory /workspace/38.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_smoke_large_delays.2006645445
Short name T2190
Test name
Test status
Simulation time 8481838813 ps
CPU time 95.61 seconds
Started Aug 02 07:59:39 PM PDT 24
Finished Aug 02 08:01:15 PM PDT 24
Peak memory 574696 kb
Host smart-09e10758-e041-45b2-a3fd-2a14c31956b6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006645445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.2006645445
Directory /workspace/38.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.2807441143
Short name T505
Test name
Test status
Simulation time 5679533986 ps
CPU time 96.08 seconds
Started Aug 02 07:59:40 PM PDT 24
Finished Aug 02 08:01:16 PM PDT 24
Peak memory 574604 kb
Host smart-35102841-b9b0-40d7-baec-de57d3c17e20
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807441143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.2807441143
Directory /workspace/38.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.1718796018
Short name T2054
Test name
Test status
Simulation time 57083924 ps
CPU time 6.58 seconds
Started Aug 02 07:59:40 PM PDT 24
Finished Aug 02 07:59:47 PM PDT 24
Peak memory 573828 kb
Host smart-62395ee7-38e4-44e2-b608-4e4e823baa3d
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718796018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delay
s.1718796018
Directory /workspace/38.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_stress_all.3327473221
Short name T601
Test name
Test status
Simulation time 9452471739 ps
CPU time 394.95 seconds
Started Aug 02 07:59:42 PM PDT 24
Finished Aug 02 08:06:17 PM PDT 24
Peak memory 576008 kb
Host smart-bfd5f165-a680-4762-970e-099c11e77453
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327473221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.3327473221
Directory /workspace/38.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.1473514785
Short name T2239
Test name
Test status
Simulation time 176657369 ps
CPU time 15.39 seconds
Started Aug 02 07:59:56 PM PDT 24
Finished Aug 02 08:00:12 PM PDT 24
Peak memory 575948 kb
Host smart-3511776d-1eeb-4a7a-a433-2725ad408f67
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473514785 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.1473514785
Directory /workspace/38.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.2284143359
Short name T2697
Test name
Test status
Simulation time 3630291756 ps
CPU time 356 seconds
Started Aug 02 07:59:54 PM PDT 24
Finished Aug 02 08:05:50 PM PDT 24
Peak memory 576016 kb
Host smart-14fdf77c-5748-460f-8402-5869f6962e49
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284143359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all
_with_rand_reset.2284143359
Directory /workspace/38.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_unmapped_addr.2196956021
Short name T2575
Test name
Test status
Simulation time 546309274 ps
CPU time 22.96 seconds
Started Aug 02 07:59:44 PM PDT 24
Finished Aug 02 08:00:07 PM PDT 24
Peak memory 576008 kb
Host smart-5360fe51-fb81-41fe-9360-aca57b54f1e4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196956021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.2196956021
Directory /workspace/38.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_access_same_device.1469082899
Short name T540
Test name
Test status
Simulation time 762008764 ps
CPU time 30.63 seconds
Started Aug 02 07:59:54 PM PDT 24
Finished Aug 02 08:00:25 PM PDT 24
Peak memory 575812 kb
Host smart-f94581d9-20ea-452b-9084-0aed0611181b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469082899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device
.1469082899
Directory /workspace/39.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.881215889
Short name T2648
Test name
Test status
Simulation time 98003547517 ps
CPU time 1808.45 seconds
Started Aug 02 07:59:53 PM PDT 24
Finished Aug 02 08:30:02 PM PDT 24
Peak memory 576060 kb
Host smart-49056a84-48e1-4dce-b16c-049efaa29acc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881215889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_d
evice_slow_rsp.881215889
Directory /workspace/39.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.3519338189
Short name T2535
Test name
Test status
Simulation time 211479405 ps
CPU time 10.37 seconds
Started Aug 02 08:00:04 PM PDT 24
Finished Aug 02 08:00:16 PM PDT 24
Peak memory 575948 kb
Host smart-79e01b95-4844-45a6-8011-45e1e1bae5aa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519338189 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_add
r.3519338189
Directory /workspace/39.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_error_random.2978663479
Short name T1462
Test name
Test status
Simulation time 450765505 ps
CPU time 37.59 seconds
Started Aug 02 07:59:53 PM PDT 24
Finished Aug 02 08:00:31 PM PDT 24
Peak memory 575888 kb
Host smart-de8ea26f-a4e9-4d0e-a4e5-e1258160aaa1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978663479 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.2978663479
Directory /workspace/39.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_random.293788030
Short name T1697
Test name
Test status
Simulation time 541252733 ps
CPU time 44.49 seconds
Started Aug 02 08:00:03 PM PDT 24
Finished Aug 02 08:00:50 PM PDT 24
Peak memory 575840 kb
Host smart-3bf49ad9-5f61-4722-92f5-0e519c56fe57
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293788030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random.293788030
Directory /workspace/39.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_random_large_delays.842818695
Short name T655
Test name
Test status
Simulation time 30559399977 ps
CPU time 336.56 seconds
Started Aug 02 07:59:53 PM PDT 24
Finished Aug 02 08:05:30 PM PDT 24
Peak memory 576820 kb
Host smart-b5a3a7f5-7cc8-4cb2-bc71-0da9fcc034f6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842818695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.842818695
Directory /workspace/39.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_random_slow_rsp.3726621730
Short name T2193
Test name
Test status
Simulation time 34466010278 ps
CPU time 518.57 seconds
Started Aug 02 08:00:03 PM PDT 24
Finished Aug 02 08:08:44 PM PDT 24
Peak memory 575884 kb
Host smart-f90d6440-222a-48a2-b235-cb33d20bcf11
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726621730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.3726621730
Directory /workspace/39.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_random_zero_delays.2237681585
Short name T1586
Test name
Test status
Simulation time 378056517 ps
CPU time 31.16 seconds
Started Aug 02 07:59:52 PM PDT 24
Finished Aug 02 08:00:23 PM PDT 24
Peak memory 575896 kb
Host smart-2fea3e7b-9c34-4b61-b599-16ed493d19b1
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237681585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_del
ays.2237681585
Directory /workspace/39.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_same_source.3585450292
Short name T638
Test name
Test status
Simulation time 961252819 ps
CPU time 28.26 seconds
Started Aug 02 07:59:55 PM PDT 24
Finished Aug 02 08:00:23 PM PDT 24
Peak memory 575768 kb
Host smart-a84f863c-f31c-4945-b138-383caacd7b3a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585450292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.3585450292
Directory /workspace/39.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_smoke.3475682519
Short name T1589
Test name
Test status
Simulation time 55072716 ps
CPU time 6.83 seconds
Started Aug 02 07:59:51 PM PDT 24
Finished Aug 02 07:59:58 PM PDT 24
Peak memory 574508 kb
Host smart-7dca1024-b4de-45df-b508-d746ced97ca6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475682519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.3475682519
Directory /workspace/39.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_smoke_large_delays.2869403046
Short name T2530
Test name
Test status
Simulation time 6818272484 ps
CPU time 70.91 seconds
Started Aug 02 07:59:54 PM PDT 24
Finished Aug 02 08:01:05 PM PDT 24
Peak memory 573968 kb
Host smart-5fdb363c-4ae7-4a71-becc-cc972e996d04
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869403046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.2869403046
Directory /workspace/39.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.3182840429
Short name T1611
Test name
Test status
Simulation time 4587703177 ps
CPU time 81.79 seconds
Started Aug 02 07:59:54 PM PDT 24
Finished Aug 02 08:01:16 PM PDT 24
Peak memory 574648 kb
Host smart-7a1e2125-5e57-41cb-8e8b-5ff8f6d6b555
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182840429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.3182840429
Directory /workspace/39.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_smoke_zero_delays.4047592249
Short name T2700
Test name
Test status
Simulation time 40476270 ps
CPU time 6.15 seconds
Started Aug 02 07:59:53 PM PDT 24
Finished Aug 02 07:59:59 PM PDT 24
Peak memory 573840 kb
Host smart-6a26f58b-9c72-4648-a18f-dc4377896f90
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047592249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delay
s.4047592249
Directory /workspace/39.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_stress_all.3899124202
Short name T2166
Test name
Test status
Simulation time 3574514917 ps
CPU time 267.48 seconds
Started Aug 02 07:59:57 PM PDT 24
Finished Aug 02 08:04:25 PM PDT 24
Peak memory 576764 kb
Host smart-a7eb5b56-6f75-4e4a-ae0c-c49c944345cf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899124202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.3899124202
Directory /workspace/39.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.2132281022
Short name T2864
Test name
Test status
Simulation time 10344000723 ps
CPU time 356.81 seconds
Started Aug 02 07:59:53 PM PDT 24
Finished Aug 02 08:05:50 PM PDT 24
Peak memory 576160 kb
Host smart-627ec6d7-d89b-4471-bf63-131874fd12c1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132281022 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.2132281022
Directory /workspace/39.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.2769060994
Short name T2516
Test name
Test status
Simulation time 228914699 ps
CPU time 107.78 seconds
Started Aug 02 07:59:55 PM PDT 24
Finished Aug 02 08:01:42 PM PDT 24
Peak memory 576628 kb
Host smart-37d9ae81-f377-4d9f-8c06-4c21f4235e56
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769060994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all
_with_rand_reset.2769060994
Directory /workspace/39.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.1695874200
Short name T1646
Test name
Test status
Simulation time 406582025 ps
CPU time 90.82 seconds
Started Aug 02 07:59:56 PM PDT 24
Finished Aug 02 08:01:27 PM PDT 24
Peak memory 576716 kb
Host smart-efa2e26c-4a77-475b-a2e2-a85a8de505a3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695874200 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_al
l_with_reset_error.1695874200
Directory /workspace/39.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_unmapped_addr.3991338285
Short name T2669
Test name
Test status
Simulation time 305453264 ps
CPU time 15.1 seconds
Started Aug 02 07:59:52 PM PDT 24
Finished Aug 02 08:00:08 PM PDT 24
Peak memory 575828 kb
Host smart-4e175a96-ee6a-462d-9595-f6e76794469f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991338285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.3991338285
Directory /workspace/39.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/4.chip_csr_aliasing.656712256
Short name T1768
Test name
Test status
Simulation time 31075194540 ps
CPU time 6822.33 seconds
Started Aug 02 07:52:12 PM PDT 24
Finished Aug 02 09:45:56 PM PDT 24
Peak memory 594024 kb
Host smart-c601d6fc-4f29-4231-b19e-511f672112d9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656712256 -assert nopostproc +UVM_TESTNAME=chip_b
ase_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 4.chip_csr_aliasing.656712256
Directory /workspace/4.chip_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.chip_csr_bit_bash.3172508906
Short name T1475
Test name
Test status
Simulation time 43217447200 ps
CPU time 5442.83 seconds
Started Aug 02 07:52:19 PM PDT 24
Finished Aug 02 09:23:03 PM PDT 24
Peak memory 592688 kb
Host smart-09d4295e-82a0-4a92-970c-2cb161747e68
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172508906 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 4.chip_csr_bit_bash.3172508906
Directory /workspace/4.chip_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.587252144
Short name T2859
Test name
Test status
Simulation time 10523966490 ps
CPU time 795.03 seconds
Started Aug 02 07:52:29 PM PDT 24
Finished Aug 02 08:05:44 PM PDT 24
Peak memory 653020 kb
Host smart-6ea7a747-8eed-4311-85b1-85a43102485f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587252144 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.chip_csr_mem_rw_with_rand_reset.587252144
Directory /workspace/4.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.chip_csr_rw.2769737373
Short name T1803
Test name
Test status
Simulation time 4339136064 ps
CPU time 278.57 seconds
Started Aug 02 07:52:24 PM PDT 24
Finished Aug 02 07:57:03 PM PDT 24
Peak memory 599304 kb
Host smart-d396637b-aaa5-421e-8d95-ef53998da508
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769737373 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_rw.2769737373
Directory /workspace/4.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.991907424
Short name T2823
Test name
Test status
Simulation time 15512704532 ps
CPU time 2159.62 seconds
Started Aug 02 07:52:23 PM PDT 24
Finished Aug 02 08:28:24 PM PDT 24
Peak memory 593368 kb
Host smart-e937e876-4fc5-46f0-8a85-54430b3bb0aa
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991907424 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 4.chip_same_csr_outstanding.991907424
Directory /workspace/4.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.chip_tl_errors.2053722588
Short name T721
Test name
Test status
Simulation time 3578886300 ps
CPU time 207.46 seconds
Started Aug 02 07:52:13 PM PDT 24
Finished Aug 02 07:55:41 PM PDT 24
Peak memory 603672 kb
Host smart-1d8ab634-33db-4413-a050-4b0e2f9409c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053722588 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_tl_errors.2053722588
Directory /workspace/4.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_access_same_device.1707888810
Short name T2675
Test name
Test status
Simulation time 135811377 ps
CPU time 8.45 seconds
Started Aug 02 07:52:34 PM PDT 24
Finished Aug 02 07:52:43 PM PDT 24
Peak memory 573880 kb
Host smart-f13d2ae0-3f27-48cb-804d-b71bd42237ff
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707888810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.
1707888810
Directory /workspace/4.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.4038953967
Short name T2647
Test name
Test status
Simulation time 73245034015 ps
CPU time 1202 seconds
Started Aug 02 07:52:34 PM PDT 24
Finished Aug 02 08:12:36 PM PDT 24
Peak memory 575932 kb
Host smart-472457f1-6bcd-41f5-ab60-da0f7d183196
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038953967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_d
evice_slow_rsp.4038953967
Directory /workspace/4.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.3165503592
Short name T1514
Test name
Test status
Simulation time 85263583 ps
CPU time 11.01 seconds
Started Aug 02 07:52:26 PM PDT 24
Finished Aug 02 07:52:37 PM PDT 24
Peak memory 576056 kb
Host smart-5cfcdab2-7f48-4708-b535-8e1429574f81
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165503592 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr
.3165503592
Directory /workspace/4.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_error_random.84784376
Short name T2799
Test name
Test status
Simulation time 1623392246 ps
CPU time 54.64 seconds
Started Aug 02 07:52:25 PM PDT 24
Finished Aug 02 07:53:20 PM PDT 24
Peak memory 575968 kb
Host smart-6eaf3604-8aa6-4541-90a2-96ff4ec77f16
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84784376 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.84784376
Directory /workspace/4.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_random.3539808450
Short name T1569
Test name
Test status
Simulation time 2038368602 ps
CPU time 78.94 seconds
Started Aug 02 07:52:24 PM PDT 24
Finished Aug 02 07:53:43 PM PDT 24
Peak memory 575984 kb
Host smart-1e343698-c453-4ed1-927a-877fcb518c6e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539808450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random.3539808450
Directory /workspace/4.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_random_large_delays.367564508
Short name T2596
Test name
Test status
Simulation time 93426823062 ps
CPU time 1001.96 seconds
Started Aug 02 07:52:25 PM PDT 24
Finished Aug 02 08:09:07 PM PDT 24
Peak memory 575964 kb
Host smart-22898756-4962-4cf1-b641-48d4c9438990
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367564508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.367564508
Directory /workspace/4.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_random_slow_rsp.1845722874
Short name T1518
Test name
Test status
Simulation time 30924631020 ps
CPU time 462.06 seconds
Started Aug 02 07:52:24 PM PDT 24
Finished Aug 02 08:00:06 PM PDT 24
Peak memory 575824 kb
Host smart-f0e04c85-780e-4a4c-a83e-00f8632603ed
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845722874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.1845722874
Directory /workspace/4.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_random_zero_delays.3733742142
Short name T2337
Test name
Test status
Simulation time 204887427 ps
CPU time 21.71 seconds
Started Aug 02 07:52:24 PM PDT 24
Finished Aug 02 07:52:46 PM PDT 24
Peak memory 575848 kb
Host smart-13356475-70a6-4b42-b7c6-49236fb0adca
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733742142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_dela
ys.3733742142
Directory /workspace/4.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_same_source.549018765
Short name T2379
Test name
Test status
Simulation time 885899475 ps
CPU time 26.12 seconds
Started Aug 02 07:52:24 PM PDT 24
Finished Aug 02 07:52:51 PM PDT 24
Peak memory 575972 kb
Host smart-581575e2-1d7c-4075-aa6e-a1ec095d3a12
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549018765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.549018765
Directory /workspace/4.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_smoke.1535736701
Short name T2040
Test name
Test status
Simulation time 148835846 ps
CPU time 6.92 seconds
Started Aug 02 07:52:19 PM PDT 24
Finished Aug 02 07:52:26 PM PDT 24
Peak memory 573808 kb
Host smart-2db472a8-1a44-46cf-bf5c-cebffc0356cc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535736701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.1535736701
Directory /workspace/4.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.1183481790
Short name T2844
Test name
Test status
Simulation time 7489881932 ps
CPU time 76.17 seconds
Started Aug 02 07:52:23 PM PDT 24
Finished Aug 02 07:53:39 PM PDT 24
Peak memory 573932 kb
Host smart-e0120436-5042-4dac-b304-218b2d63f907
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183481790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.1183481790
Directory /workspace/4.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.2260993342
Short name T874
Test name
Test status
Simulation time 5865898162 ps
CPU time 93.85 seconds
Started Aug 02 07:52:16 PM PDT 24
Finished Aug 02 07:53:50 PM PDT 24
Peak memory 574640 kb
Host smart-5a273873-e56f-431f-8358-61a52efbfa9c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260993342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.2260993342
Directory /workspace/4.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_smoke_zero_delays.977391303
Short name T2597
Test name
Test status
Simulation time 43746538 ps
CPU time 5.74 seconds
Started Aug 02 07:52:17 PM PDT 24
Finished Aug 02 07:52:23 PM PDT 24
Peak memory 573828 kb
Host smart-8210a1e9-38de-4f85-81f1-f71d958340da
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977391303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.
977391303
Directory /workspace/4.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_stress_all.3820540897
Short name T481
Test name
Test status
Simulation time 3982739370 ps
CPU time 157.84 seconds
Started Aug 02 07:52:27 PM PDT 24
Finished Aug 02 07:55:05 PM PDT 24
Peak memory 576076 kb
Host smart-0b5cc881-4eb2-47c5-8a15-684e5c6808a4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820540897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.3820540897
Directory /workspace/4.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.1378224296
Short name T2701
Test name
Test status
Simulation time 5520513734 ps
CPU time 191.17 seconds
Started Aug 02 07:52:28 PM PDT 24
Finished Aug 02 07:55:39 PM PDT 24
Peak memory 576244 kb
Host smart-cf681bae-e977-4c45-85c4-cc26672f0f1a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378224296 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.1378224296
Directory /workspace/4.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.2318793358
Short name T2833
Test name
Test status
Simulation time 351458748 ps
CPU time 160.21 seconds
Started Aug 02 07:52:29 PM PDT 24
Finished Aug 02 07:55:09 PM PDT 24
Peak memory 576796 kb
Host smart-3477dacd-6405-4117-ac5b-91ade5f86c97
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318793358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_
with_rand_reset.2318793358
Directory /workspace/4.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.219333922
Short name T2536
Test name
Test status
Simulation time 524225561 ps
CPU time 169.22 seconds
Started Aug 02 07:52:35 PM PDT 24
Finished Aug 02 07:55:24 PM PDT 24
Peak memory 576748 kb
Host smart-464981cd-227e-46cf-b01a-4b74a6f32617
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219333922 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_
with_reset_error.219333922
Directory /workspace/4.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_unmapped_addr.3913200587
Short name T2857
Test name
Test status
Simulation time 77922165 ps
CPU time 10.51 seconds
Started Aug 02 07:52:31 PM PDT 24
Finished Aug 02 07:52:42 PM PDT 24
Peak memory 575976 kb
Host smart-8a5f9a73-383b-4b62-a2be-1e741f62878c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913200587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.3913200587
Directory /workspace/4.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_access_same_device.3946263513
Short name T2797
Test name
Test status
Simulation time 1698795311 ps
CPU time 67.03 seconds
Started Aug 02 07:59:57 PM PDT 24
Finished Aug 02 08:01:04 PM PDT 24
Peak memory 575776 kb
Host smart-ca72b594-2b44-4e12-9287-fadd525d908a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946263513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device
.3946263513
Directory /workspace/40.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.333964057
Short name T2854
Test name
Test status
Simulation time 19956232572 ps
CPU time 297.76 seconds
Started Aug 02 07:59:57 PM PDT 24
Finished Aug 02 08:04:55 PM PDT 24
Peak memory 576008 kb
Host smart-fe10c668-48d1-4e7d-b02d-d2145ceb9f66
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333964057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_d
evice_slow_rsp.333964057
Directory /workspace/40.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.1976005007
Short name T1483
Test name
Test status
Simulation time 20985310 ps
CPU time 5.13 seconds
Started Aug 02 08:00:08 PM PDT 24
Finished Aug 02 08:00:13 PM PDT 24
Peak memory 574436 kb
Host smart-4b115aaa-2e5b-4e53-9da5-584a8f2c1fec
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976005007 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_add
r.1976005007
Directory /workspace/40.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_error_random.2675222575
Short name T1995
Test name
Test status
Simulation time 612196858 ps
CPU time 48.68 seconds
Started Aug 02 07:59:57 PM PDT 24
Finished Aug 02 08:00:45 PM PDT 24
Peak memory 575760 kb
Host smart-89e6bd7a-7cfb-490d-92da-c30dfe0b93bb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675222575 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.2675222575
Directory /workspace/40.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_random.1882881076
Short name T681
Test name
Test status
Simulation time 364114529 ps
CPU time 31.05 seconds
Started Aug 02 07:59:53 PM PDT 24
Finished Aug 02 08:00:24 PM PDT 24
Peak memory 575768 kb
Host smart-d0e71fc8-b4a5-49e5-8454-d63a9a19bf15
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882881076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random.1882881076
Directory /workspace/40.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_random_large_delays.836550418
Short name T2512
Test name
Test status
Simulation time 42987107882 ps
CPU time 413.36 seconds
Started Aug 02 07:59:55 PM PDT 24
Finished Aug 02 08:06:49 PM PDT 24
Peak memory 576788 kb
Host smart-ea7734b0-4de3-45e3-a0c3-8c4f2fa11eb4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836550418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.836550418
Directory /workspace/40.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_random_slow_rsp.121451515
Short name T591
Test name
Test status
Simulation time 8283446275 ps
CPU time 150.35 seconds
Started Aug 02 07:59:56 PM PDT 24
Finished Aug 02 08:02:27 PM PDT 24
Peak memory 575956 kb
Host smart-da95ec59-26f5-447d-af56-4980dc6c3014
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121451515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.121451515
Directory /workspace/40.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.1046453098
Short name T2399
Test name
Test status
Simulation time 580212869 ps
CPU time 44.1 seconds
Started Aug 02 07:59:52 PM PDT 24
Finished Aug 02 08:00:36 PM PDT 24
Peak memory 575784 kb
Host smart-80ae15c1-4023-4373-9ee6-15d0dca62ce2
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046453098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_del
ays.1046453098
Directory /workspace/40.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_same_source.1257443512
Short name T2343
Test name
Test status
Simulation time 54940833 ps
CPU time 6.37 seconds
Started Aug 02 07:59:56 PM PDT 24
Finished Aug 02 08:00:02 PM PDT 24
Peak memory 574592 kb
Host smart-d55cb3d0-5aea-49b0-930b-9b52e538d44d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257443512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.1257443512
Directory /workspace/40.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_smoke.244241981
Short name T1876
Test name
Test status
Simulation time 207004854 ps
CPU time 9.59 seconds
Started Aug 02 07:59:54 PM PDT 24
Finished Aug 02 08:00:04 PM PDT 24
Peak memory 573828 kb
Host smart-1711a513-d949-4d5f-9d06-269e2559ec96
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244241981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.244241981
Directory /workspace/40.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.735787669
Short name T2362
Test name
Test status
Simulation time 7356032778 ps
CPU time 78.2 seconds
Started Aug 02 07:59:56 PM PDT 24
Finished Aug 02 08:01:14 PM PDT 24
Peak memory 573936 kb
Host smart-e0c8be00-f322-4ec1-9632-a583fcb67d08
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735787669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.735787669
Directory /workspace/40.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.2642193849
Short name T2009
Test name
Test status
Simulation time 5127058949 ps
CPU time 81.58 seconds
Started Aug 02 08:00:04 PM PDT 24
Finished Aug 02 08:01:27 PM PDT 24
Peak memory 574568 kb
Host smart-da8c80f6-b10b-4ece-af00-61694c61e0ae
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642193849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.2642193849
Directory /workspace/40.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_smoke_zero_delays.44674810
Short name T1466
Test name
Test status
Simulation time 46321248 ps
CPU time 6.26 seconds
Started Aug 02 07:59:54 PM PDT 24
Finished Aug 02 08:00:00 PM PDT 24
Peak memory 573848 kb
Host smart-1bde2d17-74e4-4bb6-8ed6-2cd9558f3573
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44674810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.44674810
Directory /workspace/40.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_stress_all.3385735015
Short name T456
Test name
Test status
Simulation time 2247035383 ps
CPU time 193.85 seconds
Started Aug 02 08:00:07 PM PDT 24
Finished Aug 02 08:03:21 PM PDT 24
Peak memory 575992 kb
Host smart-697c6eec-3e42-44cd-850e-d606e65d4665
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385735015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.3385735015
Directory /workspace/40.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.310791922
Short name T2454
Test name
Test status
Simulation time 7144732340 ps
CPU time 255.35 seconds
Started Aug 02 08:00:11 PM PDT 24
Finished Aug 02 08:04:26 PM PDT 24
Peak memory 576204 kb
Host smart-22f5d309-17d8-4df3-a7cb-658f8170753f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310791922 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.310791922
Directory /workspace/40.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.3145937682
Short name T576
Test name
Test status
Simulation time 3570809044 ps
CPU time 466.49 seconds
Started Aug 02 08:00:10 PM PDT 24
Finished Aug 02 08:07:57 PM PDT 24
Peak memory 575964 kb
Host smart-a20e3110-7afd-4848-9751-c4d5a6766cf7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145937682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all
_with_rand_reset.3145937682
Directory /workspace/40.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.3799367466
Short name T2450
Test name
Test status
Simulation time 5818950670 ps
CPU time 288.57 seconds
Started Aug 02 08:00:10 PM PDT 24
Finished Aug 02 08:04:59 PM PDT 24
Peak memory 576800 kb
Host smart-ef891681-d51e-48b3-ab61-5a615eda57f5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799367466 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_al
l_with_reset_error.3799367466
Directory /workspace/40.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_unmapped_addr.3475013959
Short name T2587
Test name
Test status
Simulation time 148157409 ps
CPU time 21.34 seconds
Started Aug 02 08:00:09 PM PDT 24
Finished Aug 02 08:00:30 PM PDT 24
Peak memory 576004 kb
Host smart-9dbd11e8-d3b4-4aa0-99cc-66d4ee348105
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475013959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.3475013959
Directory /workspace/40.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_access_same_device.4106680677
Short name T2256
Test name
Test status
Simulation time 1444952171 ps
CPU time 54.34 seconds
Started Aug 02 08:00:11 PM PDT 24
Finished Aug 02 08:01:05 PM PDT 24
Peak memory 575932 kb
Host smart-55eef5a8-b713-4d64-bb04-8e8c3da870ef
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106680677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device
.4106680677
Directory /workspace/41.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.2138509822
Short name T880
Test name
Test status
Simulation time 4652738533 ps
CPU time 75.3 seconds
Started Aug 02 08:00:08 PM PDT 24
Finished Aug 02 08:01:24 PM PDT 24
Peak memory 575984 kb
Host smart-bb8c3a25-40fc-4d11-b14d-995e89612c11
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138509822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_
device_slow_rsp.2138509822
Directory /workspace/41.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.2344365534
Short name T1558
Test name
Test status
Simulation time 608978788 ps
CPU time 26.2 seconds
Started Aug 02 08:00:12 PM PDT 24
Finished Aug 02 08:00:39 PM PDT 24
Peak memory 575792 kb
Host smart-75ce4ec1-eba0-4d84-9560-4c2287202656
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344365534 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_add
r.2344365534
Directory /workspace/41.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_error_random.4063649545
Short name T2503
Test name
Test status
Simulation time 1279438976 ps
CPU time 44.74 seconds
Started Aug 02 08:00:10 PM PDT 24
Finished Aug 02 08:00:55 PM PDT 24
Peak memory 575992 kb
Host smart-f5f2021f-1328-41b5-bb12-23f509150465
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063649545 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.4063649545
Directory /workspace/41.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_random.2231999180
Short name T2291
Test name
Test status
Simulation time 1226857181 ps
CPU time 50.61 seconds
Started Aug 02 08:00:10 PM PDT 24
Finished Aug 02 08:01:01 PM PDT 24
Peak memory 575784 kb
Host smart-ee5ead04-f33b-438f-95b8-d0384848b968
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231999180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random.2231999180
Directory /workspace/41.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_random_large_delays.2307499403
Short name T2828
Test name
Test status
Simulation time 51312976682 ps
CPU time 588.18 seconds
Started Aug 02 08:00:09 PM PDT 24
Finished Aug 02 08:09:57 PM PDT 24
Peak memory 575956 kb
Host smart-4fa30171-84f1-4c71-8dde-84f88858388d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307499403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.2307499403
Directory /workspace/41.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.3812636786
Short name T851
Test name
Test status
Simulation time 3326865745 ps
CPU time 56.25 seconds
Started Aug 02 08:00:08 PM PDT 24
Finished Aug 02 08:01:04 PM PDT 24
Peak memory 573884 kb
Host smart-2c2387de-ed95-49d4-943a-5b1673015cec
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812636786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.3812636786
Directory /workspace/41.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_random_zero_delays.1915779718
Short name T2156
Test name
Test status
Simulation time 73327267 ps
CPU time 9.29 seconds
Started Aug 02 08:00:09 PM PDT 24
Finished Aug 02 08:00:18 PM PDT 24
Peak memory 575916 kb
Host smart-93a5eb15-93ae-47d0-8da4-b8b8234673ae
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915779718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_del
ays.1915779718
Directory /workspace/41.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_same_source.2062663851
Short name T2525
Test name
Test status
Simulation time 2182693053 ps
CPU time 63.89 seconds
Started Aug 02 08:00:09 PM PDT 24
Finished Aug 02 08:01:13 PM PDT 24
Peak memory 575976 kb
Host smart-aad546dd-aa3d-4739-b981-cf39c68c898d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062663851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.2062663851
Directory /workspace/41.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_smoke.341722325
Short name T2795
Test name
Test status
Simulation time 173165575 ps
CPU time 8.1 seconds
Started Aug 02 08:00:10 PM PDT 24
Finished Aug 02 08:00:18 PM PDT 24
Peak memory 573864 kb
Host smart-bef08dce-d028-4a6c-afdb-861a255205e1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341722325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.341722325
Directory /workspace/41.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.3742886887
Short name T1779
Test name
Test status
Simulation time 8398547610 ps
CPU time 87.95 seconds
Started Aug 02 08:00:09 PM PDT 24
Finished Aug 02 08:01:37 PM PDT 24
Peak memory 574744 kb
Host smart-136c4dca-d17b-423c-9c4f-9b8857301a37
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742886887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.3742886887
Directory /workspace/41.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.1643360683
Short name T1553
Test name
Test status
Simulation time 5194689326 ps
CPU time 85.17 seconds
Started Aug 02 08:00:08 PM PDT 24
Finished Aug 02 08:01:34 PM PDT 24
Peak memory 573900 kb
Host smart-81960ce6-f51f-4474-a10a-77f0be084701
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643360683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.1643360683
Directory /workspace/41.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_smoke_zero_delays.979439387
Short name T2115
Test name
Test status
Simulation time 50746522 ps
CPU time 6.5 seconds
Started Aug 02 08:00:09 PM PDT 24
Finished Aug 02 08:00:15 PM PDT 24
Peak memory 574528 kb
Host smart-cf6373a3-93f8-4d2b-b5b7-e00addfa5f94
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979439387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays
.979439387
Directory /workspace/41.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_stress_all.3982336148
Short name T2911
Test name
Test status
Simulation time 5980156 ps
CPU time 3.71 seconds
Started Aug 02 08:00:09 PM PDT 24
Finished Aug 02 08:00:13 PM PDT 24
Peak memory 565556 kb
Host smart-151e4244-e9a7-4fe0-9412-597d3eb9a0f8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982336148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.3982336148
Directory /workspace/41.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.822021645
Short name T2126
Test name
Test status
Simulation time 9336017590 ps
CPU time 355.31 seconds
Started Aug 02 08:00:28 PM PDT 24
Finished Aug 02 08:06:23 PM PDT 24
Peak memory 576732 kb
Host smart-9be2fdaf-1207-4aa3-bedb-65e2b0a1a0b1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822021645 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.822021645
Directory /workspace/41.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.2747867079
Short name T889
Test name
Test status
Simulation time 598730140 ps
CPU time 156.5 seconds
Started Aug 02 08:00:20 PM PDT 24
Finished Aug 02 08:02:56 PM PDT 24
Peak memory 576824 kb
Host smart-337f8e82-53ae-4c9b-8e6f-3e840baf00e2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747867079 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_al
l_with_reset_error.2747867079
Directory /workspace/41.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_unmapped_addr.2262964664
Short name T2540
Test name
Test status
Simulation time 353755717 ps
CPU time 17.21 seconds
Started Aug 02 08:00:08 PM PDT 24
Finished Aug 02 08:00:26 PM PDT 24
Peak memory 575836 kb
Host smart-6b8b02f5-ccf5-42d0-a089-1f65cd834c63
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262964664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.2262964664
Directory /workspace/41.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_access_same_device.3716442046
Short name T556
Test name
Test status
Simulation time 1220825524 ps
CPU time 94.33 seconds
Started Aug 02 08:00:23 PM PDT 24
Finished Aug 02 08:01:57 PM PDT 24
Peak memory 575924 kb
Host smart-4200df1c-3d33-4488-a150-5abae01ce198
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716442046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device
.3716442046
Directory /workspace/42.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.4050236534
Short name T2778
Test name
Test status
Simulation time 84926323677 ps
CPU time 1561.07 seconds
Started Aug 02 08:00:20 PM PDT 24
Finished Aug 02 08:26:21 PM PDT 24
Peak memory 575996 kb
Host smart-5d20c05b-0c4f-40a9-b7cb-e8f5eaa7a5e3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050236534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_
device_slow_rsp.4050236534
Directory /workspace/42.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.1871187842
Short name T2303
Test name
Test status
Simulation time 438053274 ps
CPU time 15.49 seconds
Started Aug 02 08:00:21 PM PDT 24
Finished Aug 02 08:00:37 PM PDT 24
Peak memory 575904 kb
Host smart-dc0e9552-b06c-4628-84fb-d86933e9e4df
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871187842 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_add
r.1871187842
Directory /workspace/42.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_error_random.1331298747
Short name T1568
Test name
Test status
Simulation time 532495103 ps
CPU time 18.31 seconds
Started Aug 02 08:00:22 PM PDT 24
Finished Aug 02 08:00:41 PM PDT 24
Peak memory 575792 kb
Host smart-aa765788-8b2d-4850-b542-8767937dff0c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331298747 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.1331298747
Directory /workspace/42.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_random.2833501884
Short name T526
Test name
Test status
Simulation time 297213634 ps
CPU time 13.28 seconds
Started Aug 02 08:00:21 PM PDT 24
Finished Aug 02 08:00:34 PM PDT 24
Peak memory 575932 kb
Host smart-c123304f-3869-4cbd-b803-c2e4bc14463a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833501884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random.2833501884
Directory /workspace/42.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_random_large_delays.2816432382
Short name T585
Test name
Test status
Simulation time 68807767489 ps
CPU time 733.28 seconds
Started Aug 02 08:00:22 PM PDT 24
Finished Aug 02 08:12:35 PM PDT 24
Peak memory 575996 kb
Host smart-bf4fd7b9-82ae-4dbc-805f-86bbcc7cc84b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816432382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.2816432382
Directory /workspace/42.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_random_slow_rsp.3734402276
Short name T1952
Test name
Test status
Simulation time 36775539001 ps
CPU time 648.45 seconds
Started Aug 02 08:00:21 PM PDT 24
Finished Aug 02 08:11:10 PM PDT 24
Peak memory 575996 kb
Host smart-0dbac0c7-542b-45df-b11e-865bc11ef764
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734402276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.3734402276
Directory /workspace/42.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_random_zero_delays.2863639904
Short name T541
Test name
Test status
Simulation time 558364941 ps
CPU time 53.18 seconds
Started Aug 02 08:00:25 PM PDT 24
Finished Aug 02 08:01:18 PM PDT 24
Peak memory 575848 kb
Host smart-f7acca76-f50a-43f3-b8e8-75f002031ca0
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863639904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_del
ays.2863639904
Directory /workspace/42.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_same_source.3174126690
Short name T2623
Test name
Test status
Simulation time 1896834401 ps
CPU time 55 seconds
Started Aug 02 08:00:22 PM PDT 24
Finished Aug 02 08:01:17 PM PDT 24
Peak memory 575784 kb
Host smart-51cdf9e9-7518-4571-a8f1-8d36724824a3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174126690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.3174126690
Directory /workspace/42.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_smoke.2762823366
Short name T1782
Test name
Test status
Simulation time 46672269 ps
CPU time 5.81 seconds
Started Aug 02 08:00:25 PM PDT 24
Finished Aug 02 08:00:31 PM PDT 24
Peak memory 574560 kb
Host smart-fbee5418-014a-49ff-94da-5c0590cbcb5c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762823366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.2762823366
Directory /workspace/42.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_smoke_large_delays.804426440
Short name T1604
Test name
Test status
Simulation time 9852642862 ps
CPU time 99.21 seconds
Started Aug 02 08:00:21 PM PDT 24
Finished Aug 02 08:02:00 PM PDT 24
Peak memory 574588 kb
Host smart-c9820e85-0c85-48d2-8144-a3de3058fe4b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804426440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.804426440
Directory /workspace/42.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.449802659
Short name T1450
Test name
Test status
Simulation time 2900654975 ps
CPU time 49.16 seconds
Started Aug 02 08:00:28 PM PDT 24
Finished Aug 02 08:01:17 PM PDT 24
Peak memory 573704 kb
Host smart-9cd9cbdf-844a-4f39-8c75-24d230177eb7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449802659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.449802659
Directory /workspace/42.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_smoke_zero_delays.1255353458
Short name T2655
Test name
Test status
Simulation time 46431636 ps
CPU time 6.37 seconds
Started Aug 02 08:00:22 PM PDT 24
Finished Aug 02 08:00:29 PM PDT 24
Peak memory 573844 kb
Host smart-b24aee70-71d7-4ddd-9685-884bf3ba6cf5
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255353458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delay
s.1255353458
Directory /workspace/42.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_stress_all.2186782612
Short name T622
Test name
Test status
Simulation time 10444669723 ps
CPU time 430.15 seconds
Started Aug 02 08:00:25 PM PDT 24
Finished Aug 02 08:07:35 PM PDT 24
Peak memory 576796 kb
Host smart-8dbe5974-cc0a-4a78-9263-9eb3b88f5cf7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186782612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.2186782612
Directory /workspace/42.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.2119459676
Short name T1705
Test name
Test status
Simulation time 2186428596 ps
CPU time 157.47 seconds
Started Aug 02 08:00:22 PM PDT 24
Finished Aug 02 08:03:00 PM PDT 24
Peak memory 576300 kb
Host smart-99d3d245-01d5-437e-a4f2-c0ff07cfa659
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119459676 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.2119459676
Directory /workspace/42.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.3172435690
Short name T2896
Test name
Test status
Simulation time 610570591 ps
CPU time 174.33 seconds
Started Aug 02 08:00:22 PM PDT 24
Finished Aug 02 08:03:17 PM PDT 24
Peak memory 575904 kb
Host smart-2b97d466-791e-4e8a-a66f-5d557bb00b57
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172435690 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_al
l_with_reset_error.3172435690
Directory /workspace/42.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_unmapped_addr.1717856600
Short name T2048
Test name
Test status
Simulation time 942146665 ps
CPU time 44.48 seconds
Started Aug 02 08:00:25 PM PDT 24
Finished Aug 02 08:01:09 PM PDT 24
Peak memory 575964 kb
Host smart-51e7e19d-6efd-435f-a9bf-e142de10add0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717856600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.1717856600
Directory /workspace/42.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_access_same_device.2725472660
Short name T865
Test name
Test status
Simulation time 416996151 ps
CPU time 37.67 seconds
Started Aug 02 08:00:33 PM PDT 24
Finished Aug 02 08:01:11 PM PDT 24
Peak memory 575856 kb
Host smart-5b4bda63-0d48-4f84-b0fe-534574d94b59
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725472660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device
.2725472660
Directory /workspace/43.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.1022653680
Short name T2775
Test name
Test status
Simulation time 110705407590 ps
CPU time 2024.56 seconds
Started Aug 02 08:00:35 PM PDT 24
Finished Aug 02 08:34:20 PM PDT 24
Peak memory 576032 kb
Host smart-2f4ca706-50c0-433d-bee9-2532f419bc71
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022653680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_
device_slow_rsp.1022653680
Directory /workspace/43.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.1618337166
Short name T2043
Test name
Test status
Simulation time 95369745 ps
CPU time 10.96 seconds
Started Aug 02 08:00:32 PM PDT 24
Finished Aug 02 08:00:43 PM PDT 24
Peak memory 575940 kb
Host smart-b11dff0b-0439-4404-b6d6-a6487ef6645c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618337166 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_add
r.1618337166
Directory /workspace/43.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_error_random.2921453314
Short name T2813
Test name
Test status
Simulation time 74872863 ps
CPU time 8.74 seconds
Started Aug 02 08:00:31 PM PDT 24
Finished Aug 02 08:00:40 PM PDT 24
Peak memory 575924 kb
Host smart-6e335a65-5d7e-48fd-90f1-e35925e415ab
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921453314 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.2921453314
Directory /workspace/43.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_random_large_delays.3435891618
Short name T2341
Test name
Test status
Simulation time 80236941120 ps
CPU time 861.83 seconds
Started Aug 02 08:00:33 PM PDT 24
Finished Aug 02 08:14:55 PM PDT 24
Peak memory 576056 kb
Host smart-be1d36b4-c388-44b8-a796-93952a60f5c1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435891618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.3435891618
Directory /workspace/43.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_random_slow_rsp.752049845
Short name T2155
Test name
Test status
Simulation time 68393387477 ps
CPU time 1193.36 seconds
Started Aug 02 08:00:35 PM PDT 24
Finished Aug 02 08:20:29 PM PDT 24
Peak memory 576040 kb
Host smart-1bc78273-4bf5-446d-a884-ea49b78da0e3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752049845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.752049845
Directory /workspace/43.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_random_zero_delays.46408383
Short name T464
Test name
Test status
Simulation time 580782206 ps
CPU time 50.63 seconds
Started Aug 02 08:00:31 PM PDT 24
Finished Aug 02 08:01:22 PM PDT 24
Peak memory 575880 kb
Host smart-20f75e86-ce9d-499e-bec3-730fad608be4
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46408383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delay
s.46408383
Directory /workspace/43.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_same_source.890235984
Short name T1727
Test name
Test status
Simulation time 2068261656 ps
CPU time 59.18 seconds
Started Aug 02 08:00:33 PM PDT 24
Finished Aug 02 08:01:33 PM PDT 24
Peak memory 575764 kb
Host smart-036ce3fd-34cb-4ce8-8ade-4b84d2e8d0cf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890235984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.890235984
Directory /workspace/43.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_smoke.3350837937
Short name T1493
Test name
Test status
Simulation time 226995436 ps
CPU time 9.83 seconds
Started Aug 02 08:00:28 PM PDT 24
Finished Aug 02 08:00:38 PM PDT 24
Peak memory 574432 kb
Host smart-0e23caad-1efe-40c6-881f-26be86c4fb2c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350837937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.3350837937
Directory /workspace/43.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.378973306
Short name T1805
Test name
Test status
Simulation time 7160944852 ps
CPU time 73.38 seconds
Started Aug 02 08:00:33 PM PDT 24
Finished Aug 02 08:01:47 PM PDT 24
Peak memory 573924 kb
Host smart-939c8dc5-e1c1-484e-b75d-af7e758dacd4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378973306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.378973306
Directory /workspace/43.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.1236603565
Short name T1474
Test name
Test status
Simulation time 5674661438 ps
CPU time 90.06 seconds
Started Aug 02 08:00:33 PM PDT 24
Finished Aug 02 08:02:03 PM PDT 24
Peak memory 574680 kb
Host smart-c5e6f9de-aa17-4158-b850-f3dfed3ec497
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236603565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.1236603565
Directory /workspace/43.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_smoke_zero_delays.1710943854
Short name T2014
Test name
Test status
Simulation time 42408488 ps
CPU time 6.47 seconds
Started Aug 02 08:00:32 PM PDT 24
Finished Aug 02 08:00:39 PM PDT 24
Peak memory 573772 kb
Host smart-a9973cbf-e4bb-4b9b-bde3-aebb2ad99c35
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710943854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delay
s.1710943854
Directory /workspace/43.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_stress_all.2335437942
Short name T611
Test name
Test status
Simulation time 1544598918 ps
CPU time 126.83 seconds
Started Aug 02 08:00:32 PM PDT 24
Finished Aug 02 08:02:39 PM PDT 24
Peak memory 576028 kb
Host smart-dd480218-3961-4707-bfe9-52defc0fbc5b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335437942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.2335437942
Directory /workspace/43.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.2034430177
Short name T1725
Test name
Test status
Simulation time 921222468 ps
CPU time 76.55 seconds
Started Aug 02 08:00:44 PM PDT 24
Finished Aug 02 08:02:00 PM PDT 24
Peak memory 576072 kb
Host smart-dc5578f8-8cc6-4a2a-81df-cdeaf6489401
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034430177 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.2034430177
Directory /workspace/43.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.2565314266
Short name T2368
Test name
Test status
Simulation time 1971985677 ps
CPU time 264.86 seconds
Started Aug 02 08:00:32 PM PDT 24
Finished Aug 02 08:04:57 PM PDT 24
Peak memory 576848 kb
Host smart-2339d013-a8e5-4892-b9cb-935ace3f795a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565314266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all
_with_rand_reset.2565314266
Directory /workspace/43.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.661122153
Short name T2282
Test name
Test status
Simulation time 438463210 ps
CPU time 83.8 seconds
Started Aug 02 08:00:44 PM PDT 24
Finished Aug 02 08:02:08 PM PDT 24
Peak memory 576708 kb
Host smart-7171a6df-57b7-42b2-9db7-2b311b17eb1b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661122153 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all
_with_reset_error.661122153
Directory /workspace/43.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_unmapped_addr.1709809723
Short name T2304
Test name
Test status
Simulation time 94547143 ps
CPU time 13.45 seconds
Started Aug 02 08:00:35 PM PDT 24
Finished Aug 02 08:00:49 PM PDT 24
Peak memory 575880 kb
Host smart-e54a62c7-b451-44f2-aad4-c2b8d68fbc1c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709809723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.1709809723
Directory /workspace/43.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_access_same_device.2697434480
Short name T2127
Test name
Test status
Simulation time 905049860 ps
CPU time 40.97 seconds
Started Aug 02 08:00:43 PM PDT 24
Finished Aug 02 08:01:24 PM PDT 24
Peak memory 575888 kb
Host smart-f9d49675-48d7-4bac-8cfc-72a2d2f27301
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697434480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device
.2697434480
Directory /workspace/44.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.496366199
Short name T1687
Test name
Test status
Simulation time 40690660037 ps
CPU time 686.68 seconds
Started Aug 02 08:00:42 PM PDT 24
Finished Aug 02 08:12:09 PM PDT 24
Peak memory 575836 kb
Host smart-e9b8769c-159a-4099-9f1f-f09f5f12b836
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496366199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_d
evice_slow_rsp.496366199
Directory /workspace/44.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.1854649863
Short name T1442
Test name
Test status
Simulation time 824806010 ps
CPU time 34.16 seconds
Started Aug 02 08:00:47 PM PDT 24
Finished Aug 02 08:01:21 PM PDT 24
Peak memory 575724 kb
Host smart-f08d1cd0-d790-4e4e-95ea-189390d25244
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854649863 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_add
r.1854649863
Directory /workspace/44.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_error_random.826017070
Short name T2058
Test name
Test status
Simulation time 137770916 ps
CPU time 11.66 seconds
Started Aug 02 08:00:43 PM PDT 24
Finished Aug 02 08:00:54 PM PDT 24
Peak memory 575676 kb
Host smart-8a637113-ad53-4bde-9bfe-76655a2463d6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826017070 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.826017070
Directory /workspace/44.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_random.3847622909
Short name T2325
Test name
Test status
Simulation time 547409361 ps
CPU time 46.07 seconds
Started Aug 02 08:00:44 PM PDT 24
Finished Aug 02 08:01:30 PM PDT 24
Peak memory 575872 kb
Host smart-22821b3b-74e7-4548-9d9f-430e425f884c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847622909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random.3847622909
Directory /workspace/44.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_random_large_delays.2423649161
Short name T2072
Test name
Test status
Simulation time 48978024404 ps
CPU time 506.4 seconds
Started Aug 02 08:00:44 PM PDT 24
Finished Aug 02 08:09:11 PM PDT 24
Peak memory 576104 kb
Host smart-b367b608-94b1-439f-97e0-ee99fa26c0b1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423649161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.2423649161
Directory /workspace/44.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_random_slow_rsp.2824169703
Short name T2232
Test name
Test status
Simulation time 26626644333 ps
CPU time 460.53 seconds
Started Aug 02 08:00:49 PM PDT 24
Finished Aug 02 08:08:30 PM PDT 24
Peak memory 576740 kb
Host smart-dff5b3c7-6d10-4740-9ed8-b6aef23b62f3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824169703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.2824169703
Directory /workspace/44.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_random_zero_delays.3915345519
Short name T1526
Test name
Test status
Simulation time 35850991 ps
CPU time 5.88 seconds
Started Aug 02 08:00:51 PM PDT 24
Finished Aug 02 08:00:57 PM PDT 24
Peak memory 574468 kb
Host smart-e3d50c49-ccef-41bd-beb7-436988a0e8bf
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915345519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_del
ays.3915345519
Directory /workspace/44.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_same_source.2145971028
Short name T502
Test name
Test status
Simulation time 1413207849 ps
CPU time 40.17 seconds
Started Aug 02 08:00:50 PM PDT 24
Finished Aug 02 08:01:30 PM PDT 24
Peak memory 575820 kb
Host smart-bab3159d-db3f-497a-aa28-9d4fbb4eee16
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145971028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.2145971028
Directory /workspace/44.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_smoke.3032204344
Short name T1470
Test name
Test status
Simulation time 181505527 ps
CPU time 8.35 seconds
Started Aug 02 08:00:46 PM PDT 24
Finished Aug 02 08:00:55 PM PDT 24
Peak memory 573816 kb
Host smart-e4ed8b2f-246c-4b94-8c47-a92ead61fbbe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032204344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.3032204344
Directory /workspace/44.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_smoke_large_delays.3201589901
Short name T2226
Test name
Test status
Simulation time 6718979912 ps
CPU time 68.97 seconds
Started Aug 02 08:00:44 PM PDT 24
Finished Aug 02 08:01:53 PM PDT 24
Peak memory 574632 kb
Host smart-0242b2d4-03ef-433e-be82-16827630d8f2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201589901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.3201589901
Directory /workspace/44.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.2246365976
Short name T2165
Test name
Test status
Simulation time 4900417963 ps
CPU time 85.97 seconds
Started Aug 02 08:00:43 PM PDT 24
Finished Aug 02 08:02:09 PM PDT 24
Peak memory 573904 kb
Host smart-17dc527c-8cd4-4883-9379-353c5ff3de08
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246365976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.2246365976
Directory /workspace/44.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_smoke_zero_delays.3964856070
Short name T2551
Test name
Test status
Simulation time 52563780 ps
CPU time 6.29 seconds
Started Aug 02 08:00:51 PM PDT 24
Finished Aug 02 08:00:57 PM PDT 24
Peak memory 573812 kb
Host smart-11ae6d53-a990-4d14-9f32-580e93d5cd60
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964856070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delay
s.3964856070
Directory /workspace/44.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_stress_all.1063681324
Short name T2818
Test name
Test status
Simulation time 734269057 ps
CPU time 25.05 seconds
Started Aug 02 08:00:45 PM PDT 24
Finished Aug 02 08:01:10 PM PDT 24
Peak memory 576008 kb
Host smart-182b25a6-75b8-452c-9ea0-0d1d0c81ec3c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063681324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.1063681324
Directory /workspace/44.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.2218722794
Short name T2088
Test name
Test status
Simulation time 63469960 ps
CPU time 41.5 seconds
Started Aug 02 08:00:44 PM PDT 24
Finished Aug 02 08:01:25 PM PDT 24
Peak memory 575848 kb
Host smart-22f88f16-013f-4386-a2a3-d617e1940932
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218722794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all
_with_rand_reset.2218722794
Directory /workspace/44.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.3663958489
Short name T1877
Test name
Test status
Simulation time 5100326668 ps
CPU time 324.19 seconds
Started Aug 02 08:00:44 PM PDT 24
Finished Aug 02 08:06:09 PM PDT 24
Peak memory 576808 kb
Host smart-f90d9fe9-d077-46e2-b1d2-263ffac667cf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663958489 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_al
l_with_reset_error.3663958489
Directory /workspace/44.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_unmapped_addr.3922473100
Short name T1811
Test name
Test status
Simulation time 1285945323 ps
CPU time 51.17 seconds
Started Aug 02 08:00:42 PM PDT 24
Finished Aug 02 08:01:33 PM PDT 24
Peak memory 575884 kb
Host smart-0ffa2270-3fef-4d11-b562-e14f2a295326
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922473100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.3922473100
Directory /workspace/44.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_access_same_device.295224987
Short name T837
Test name
Test status
Simulation time 1077692866 ps
CPU time 42.61 seconds
Started Aug 02 08:00:55 PM PDT 24
Finished Aug 02 08:01:37 PM PDT 24
Peak memory 575940 kb
Host smart-dd4a921d-0101-4d2b-9f58-a9559bf2e501
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295224987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.
295224987
Directory /workspace/45.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.2531344118
Short name T2301
Test name
Test status
Simulation time 109044800203 ps
CPU time 2117.5 seconds
Started Aug 02 08:00:55 PM PDT 24
Finished Aug 02 08:36:13 PM PDT 24
Peak memory 575972 kb
Host smart-1c75d965-4788-491a-a5a6-a56922b0efd7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531344118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_
device_slow_rsp.2531344118
Directory /workspace/45.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.2267163677
Short name T2476
Test name
Test status
Simulation time 1052949358 ps
CPU time 38.36 seconds
Started Aug 02 08:00:54 PM PDT 24
Finished Aug 02 08:01:32 PM PDT 24
Peak memory 575752 kb
Host smart-3a932ac8-fdb5-4adc-82ad-5741757b7bc0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267163677 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_add
r.2267163677
Directory /workspace/45.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_error_random.2040790649
Short name T2020
Test name
Test status
Simulation time 509600249 ps
CPU time 38.02 seconds
Started Aug 02 08:00:55 PM PDT 24
Finished Aug 02 08:01:33 PM PDT 24
Peak memory 575684 kb
Host smart-4eede03c-c7d9-48cf-9abc-53fd7e8620fe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040790649 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.2040790649
Directory /workspace/45.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_random.1601263627
Short name T2771
Test name
Test status
Simulation time 405722660 ps
CPU time 32.94 seconds
Started Aug 02 08:00:42 PM PDT 24
Finished Aug 02 08:01:15 PM PDT 24
Peak memory 575776 kb
Host smart-dcd2d6ea-7ae1-4150-a43b-1943b98adfe2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601263627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random.1601263627
Directory /workspace/45.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_random_large_delays.2340630444
Short name T2090
Test name
Test status
Simulation time 60029960174 ps
CPU time 643.97 seconds
Started Aug 02 08:00:52 PM PDT 24
Finished Aug 02 08:11:36 PM PDT 24
Peak memory 575968 kb
Host smart-552b4251-74c9-4a1f-b882-199a914acd14
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340630444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.2340630444
Directory /workspace/45.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.3738780383
Short name T459
Test name
Test status
Simulation time 39796388812 ps
CPU time 651.9 seconds
Started Aug 02 08:00:57 PM PDT 24
Finished Aug 02 08:11:49 PM PDT 24
Peak memory 576076 kb
Host smart-3bcdada0-8917-4d58-8340-6662204bd457
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738780383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.3738780383
Directory /workspace/45.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_random_zero_delays.848731527
Short name T1577
Test name
Test status
Simulation time 407675671 ps
CPU time 37.28 seconds
Started Aug 02 08:00:51 PM PDT 24
Finished Aug 02 08:01:29 PM PDT 24
Peak memory 575788 kb
Host smart-40df743a-125c-42cd-be70-5b1d53d15dc9
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848731527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_dela
ys.848731527
Directory /workspace/45.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_same_source.1151954255
Short name T2116
Test name
Test status
Simulation time 184577171 ps
CPU time 14.71 seconds
Started Aug 02 08:00:57 PM PDT 24
Finished Aug 02 08:01:11 PM PDT 24
Peak memory 575912 kb
Host smart-ff571498-3209-40e0-a084-5c7785d96513
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151954255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.1151954255
Directory /workspace/45.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_smoke.36597768
Short name T2927
Test name
Test status
Simulation time 212100037 ps
CPU time 9.31 seconds
Started Aug 02 08:00:43 PM PDT 24
Finished Aug 02 08:00:53 PM PDT 24
Peak memory 574548 kb
Host smart-58f3a7c0-4cfb-4a6c-b29a-88246e9ffd9c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36597768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.36597768
Directory /workspace/45.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_smoke_large_delays.3059132072
Short name T2632
Test name
Test status
Simulation time 8723713612 ps
CPU time 90.49 seconds
Started Aug 02 08:00:49 PM PDT 24
Finished Aug 02 08:02:20 PM PDT 24
Peak memory 574532 kb
Host smart-0aa12859-3dae-4c56-a2d9-3da39d71b544
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059132072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.3059132072
Directory /workspace/45.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.54697952
Short name T2504
Test name
Test status
Simulation time 6090065917 ps
CPU time 100.16 seconds
Started Aug 02 08:00:46 PM PDT 24
Finished Aug 02 08:02:27 PM PDT 24
Peak memory 573944 kb
Host smart-9021d74b-d1aa-41c3-8668-2f3f13d6e439
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54697952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.54697952
Directory /workspace/45.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_smoke_zero_delays.962773450
Short name T1406
Test name
Test status
Simulation time 39913206 ps
CPU time 5.72 seconds
Started Aug 02 08:00:51 PM PDT 24
Finished Aug 02 08:00:57 PM PDT 24
Peak memory 574484 kb
Host smart-b8602770-30a3-4cdf-9493-abe0d371e7fc
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962773450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays
.962773450
Directory /workspace/45.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_stress_all.154511205
Short name T548
Test name
Test status
Simulation time 209870983 ps
CPU time 21.37 seconds
Started Aug 02 08:01:01 PM PDT 24
Finished Aug 02 08:01:23 PM PDT 24
Peak memory 575964 kb
Host smart-5f7d70ea-1b4d-431b-bcf2-3558df35e6ed
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154511205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.154511205
Directory /workspace/45.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.3832534663
Short name T2076
Test name
Test status
Simulation time 3871607730 ps
CPU time 146.09 seconds
Started Aug 02 08:00:59 PM PDT 24
Finished Aug 02 08:03:25 PM PDT 24
Peak memory 576064 kb
Host smart-66bacb38-552a-45ce-b712-87f773d7a435
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832534663 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.3832534663
Directory /workspace/45.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.2625394906
Short name T2616
Test name
Test status
Simulation time 410361566 ps
CPU time 176.25 seconds
Started Aug 02 08:00:58 PM PDT 24
Finished Aug 02 08:03:54 PM PDT 24
Peak memory 575940 kb
Host smart-7b9a878d-b18a-4df3-8ac8-efc8a424daa0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625394906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all
_with_rand_reset.2625394906
Directory /workspace/45.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_unmapped_addr.810534488
Short name T1639
Test name
Test status
Simulation time 505363034 ps
CPU time 25.69 seconds
Started Aug 02 08:00:55 PM PDT 24
Finished Aug 02 08:01:21 PM PDT 24
Peak memory 575948 kb
Host smart-da014dc1-ac25-420d-aae6-d7f2f4944b81
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810534488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.810534488
Directory /workspace/45.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_access_same_device.2497503469
Short name T1451
Test name
Test status
Simulation time 186496675 ps
CPU time 13.77 seconds
Started Aug 02 08:01:07 PM PDT 24
Finished Aug 02 08:01:21 PM PDT 24
Peak memory 575784 kb
Host smart-b35f4e47-1858-4689-bbfe-b42d964c740e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497503469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device
.2497503469
Directory /workspace/46.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.281610201
Short name T2614
Test name
Test status
Simulation time 82341116693 ps
CPU time 1619.25 seconds
Started Aug 02 08:01:05 PM PDT 24
Finished Aug 02 08:28:04 PM PDT 24
Peak memory 575980 kb
Host smart-0efc6535-4e87-421e-95db-89fb0b52d783
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281610201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_d
evice_slow_rsp.281610201
Directory /workspace/46.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.1447632045
Short name T1572
Test name
Test status
Simulation time 300291326 ps
CPU time 29.93 seconds
Started Aug 02 08:01:07 PM PDT 24
Finished Aug 02 08:01:37 PM PDT 24
Peak memory 575956 kb
Host smart-882de73e-c64e-4c88-b0cc-c142c2f34660
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447632045 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_add
r.1447632045
Directory /workspace/46.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_error_random.286370288
Short name T2428
Test name
Test status
Simulation time 1841756222 ps
CPU time 55.33 seconds
Started Aug 02 08:01:18 PM PDT 24
Finished Aug 02 08:02:13 PM PDT 24
Peak memory 575700 kb
Host smart-c6fb5fdd-9afa-425e-9218-b9e94f0f8313
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286370288 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.286370288
Directory /workspace/46.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_random.2661005122
Short name T2273
Test name
Test status
Simulation time 1727643588 ps
CPU time 57.18 seconds
Started Aug 02 08:01:01 PM PDT 24
Finished Aug 02 08:01:58 PM PDT 24
Peak memory 575992 kb
Host smart-0c106603-85a4-44cc-a904-b5e8b7b190ad
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661005122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random.2661005122
Directory /workspace/46.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_random_large_delays.178975456
Short name T2560
Test name
Test status
Simulation time 15500519780 ps
CPU time 167.94 seconds
Started Aug 02 08:01:08 PM PDT 24
Finished Aug 02 08:03:56 PM PDT 24
Peak memory 576740 kb
Host smart-a7290825-dc2c-4e54-8496-21cdd27b710e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178975456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.178975456
Directory /workspace/46.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_random_slow_rsp.805901586
Short name T1917
Test name
Test status
Simulation time 18451991008 ps
CPU time 330.21 seconds
Started Aug 02 08:01:09 PM PDT 24
Finished Aug 02 08:06:39 PM PDT 24
Peak memory 575892 kb
Host smart-46df6e4d-ff3d-4383-b0b3-7b909ea34dbf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805901586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.805901586
Directory /workspace/46.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_random_zero_delays.3597923222
Short name T2025
Test name
Test status
Simulation time 122461496 ps
CPU time 13.78 seconds
Started Aug 02 08:01:03 PM PDT 24
Finished Aug 02 08:01:17 PM PDT 24
Peak memory 575740 kb
Host smart-be4be089-2f5d-434a-b296-4f356d0aee3c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597923222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_del
ays.3597923222
Directory /workspace/46.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_same_source.447882908
Short name T590
Test name
Test status
Simulation time 1078459140 ps
CPU time 30.14 seconds
Started Aug 02 08:01:04 PM PDT 24
Finished Aug 02 08:01:35 PM PDT 24
Peak memory 575912 kb
Host smart-3ed8be24-1eb0-42bf-adc4-e9445ab85b9d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447882908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.447882908
Directory /workspace/46.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_smoke.151244478
Short name T1443
Test name
Test status
Simulation time 195937241 ps
CPU time 8.67 seconds
Started Aug 02 08:00:55 PM PDT 24
Finished Aug 02 08:01:04 PM PDT 24
Peak memory 574592 kb
Host smart-e611a833-ad66-453a-abf8-73721f973696
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151244478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.151244478
Directory /workspace/46.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_smoke_large_delays.4273203319
Short name T1438
Test name
Test status
Simulation time 7797493007 ps
CPU time 82.81 seconds
Started Aug 02 08:00:53 PM PDT 24
Finished Aug 02 08:02:16 PM PDT 24
Peak memory 574712 kb
Host smart-94d600dc-f985-4dc6-a422-f7c99a87e508
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273203319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.4273203319
Directory /workspace/46.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.3220108790
Short name T1707
Test name
Test status
Simulation time 4885050442 ps
CPU time 81.53 seconds
Started Aug 02 08:01:00 PM PDT 24
Finished Aug 02 08:02:21 PM PDT 24
Peak memory 573896 kb
Host smart-53971d96-5584-44a6-9b74-d8bfff272b27
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220108790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.3220108790
Directory /workspace/46.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_smoke_zero_delays.1873174461
Short name T2094
Test name
Test status
Simulation time 45271154 ps
CPU time 5.93 seconds
Started Aug 02 08:00:52 PM PDT 24
Finished Aug 02 08:00:58 PM PDT 24
Peak memory 574460 kb
Host smart-4455cea0-6d1c-45c6-a842-23cb5dc5a51b
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873174461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delay
s.1873174461
Directory /workspace/46.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_stress_all.3062145217
Short name T2195
Test name
Test status
Simulation time 4151701626 ps
CPU time 364.03 seconds
Started Aug 02 08:01:06 PM PDT 24
Finished Aug 02 08:07:10 PM PDT 24
Peak memory 575908 kb
Host smart-59dfaa8d-59d9-4157-b147-7a37c1ef31e6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062145217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.3062145217
Directory /workspace/46.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_error.3552634156
Short name T2630
Test name
Test status
Simulation time 556639507 ps
CPU time 40.43 seconds
Started Aug 02 08:01:06 PM PDT 24
Finished Aug 02 08:01:46 PM PDT 24
Peak memory 575756 kb
Host smart-c2825ab3-2293-4bd5-a122-4519b98a2a05
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552634156 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.3552634156
Directory /workspace/46.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.3529603521
Short name T2073
Test name
Test status
Simulation time 4821368456 ps
CPU time 377.13 seconds
Started Aug 02 08:01:04 PM PDT 24
Finished Aug 02 08:07:21 PM PDT 24
Peak memory 576028 kb
Host smart-64cb0e5b-1c49-4f4e-804a-51ed74f79d94
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529603521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all
_with_rand_reset.3529603521
Directory /workspace/46.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.2745883261
Short name T882
Test name
Test status
Simulation time 624635242 ps
CPU time 149.92 seconds
Started Aug 02 08:01:11 PM PDT 24
Finished Aug 02 08:03:41 PM PDT 24
Peak memory 575864 kb
Host smart-1ba9ba54-5ef5-40ca-a780-642a14d441f7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745883261 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_al
l_with_reset_error.2745883261
Directory /workspace/46.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_unmapped_addr.2970260656
Short name T2096
Test name
Test status
Simulation time 122843147 ps
CPU time 16.78 seconds
Started Aug 02 08:01:08 PM PDT 24
Finished Aug 02 08:01:25 PM PDT 24
Peak memory 575912 kb
Host smart-785e8535-863a-45e5-8bd7-7524980bd061
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970260656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.2970260656
Directory /workspace/46.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_access_same_device.2170726610
Short name T2110
Test name
Test status
Simulation time 2185559080 ps
CPU time 81.57 seconds
Started Aug 02 08:01:06 PM PDT 24
Finished Aug 02 08:02:27 PM PDT 24
Peak memory 576012 kb
Host smart-6b7fdc02-ad8f-4588-b0d5-29d8513baf36
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170726610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device
.2170726610
Directory /workspace/47.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.629163713
Short name T2397
Test name
Test status
Simulation time 111954756454 ps
CPU time 1969.65 seconds
Started Aug 02 08:01:16 PM PDT 24
Finished Aug 02 08:34:06 PM PDT 24
Peak memory 576752 kb
Host smart-0a9351f6-d861-4b02-97f0-c6cf1165de5d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629163713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_d
evice_slow_rsp.629163713
Directory /workspace/47.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.1237655042
Short name T2024
Test name
Test status
Simulation time 276899405 ps
CPU time 14.51 seconds
Started Aug 02 08:01:15 PM PDT 24
Finished Aug 02 08:01:29 PM PDT 24
Peak memory 575868 kb
Host smart-fdfc9120-fd19-4461-979c-d072adc2ed53
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237655042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_add
r.1237655042
Directory /workspace/47.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_error_random.2933443822
Short name T1959
Test name
Test status
Simulation time 1034240367 ps
CPU time 35.65 seconds
Started Aug 02 08:01:17 PM PDT 24
Finished Aug 02 08:01:53 PM PDT 24
Peak memory 575852 kb
Host smart-1b6d500d-cf3d-42d2-969d-d864fd2454f4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933443822 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.2933443822
Directory /workspace/47.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_random.1302153291
Short name T2018
Test name
Test status
Simulation time 522453965 ps
CPU time 45.41 seconds
Started Aug 02 08:01:06 PM PDT 24
Finished Aug 02 08:01:52 PM PDT 24
Peak memory 575812 kb
Host smart-61be4fb5-0d44-44a4-a953-b1b8f8b24ec9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302153291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random.1302153291
Directory /workspace/47.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_random_large_delays.3635727069
Short name T633
Test name
Test status
Simulation time 30267276261 ps
CPU time 330.04 seconds
Started Aug 02 08:01:07 PM PDT 24
Finished Aug 02 08:06:37 PM PDT 24
Peak memory 575776 kb
Host smart-af486bd6-64d7-4deb-a592-bbb1cf68cb8d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635727069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.3635727069
Directory /workspace/47.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_random_slow_rsp.3735805838
Short name T2056
Test name
Test status
Simulation time 15808935518 ps
CPU time 275.13 seconds
Started Aug 02 08:01:08 PM PDT 24
Finished Aug 02 08:05:43 PM PDT 24
Peak memory 576008 kb
Host smart-22089738-e9d5-4b7c-9b32-0b3878805b40
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735805838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.3735805838
Directory /workspace/47.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_random_zero_delays.866193538
Short name T515
Test name
Test status
Simulation time 333078767 ps
CPU time 31.59 seconds
Started Aug 02 08:01:05 PM PDT 24
Finished Aug 02 08:01:36 PM PDT 24
Peak memory 575928 kb
Host smart-9e3407c0-5c2c-4383-915b-b88889133453
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866193538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_dela
ys.866193538
Directory /workspace/47.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_same_source.3807878524
Short name T2729
Test name
Test status
Simulation time 1407837504 ps
CPU time 37.29 seconds
Started Aug 02 08:01:18 PM PDT 24
Finished Aug 02 08:01:55 PM PDT 24
Peak memory 575688 kb
Host smart-0428f0c7-6c85-4306-af40-c2b9fe34c6fd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807878524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.3807878524
Directory /workspace/47.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_smoke.3343389609
Short name T2187
Test name
Test status
Simulation time 45514630 ps
CPU time 6.34 seconds
Started Aug 02 08:01:08 PM PDT 24
Finished Aug 02 08:01:14 PM PDT 24
Peak memory 573852 kb
Host smart-f12749b3-3489-4965-a84c-9cd768dc58b4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343389609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.3343389609
Directory /workspace/47.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_smoke_large_delays.2257033940
Short name T1495
Test name
Test status
Simulation time 9703983795 ps
CPU time 102.62 seconds
Started Aug 02 08:01:07 PM PDT 24
Finished Aug 02 08:02:50 PM PDT 24
Peak memory 573956 kb
Host smart-991d229c-ccfc-4a55-81c8-4cae4f9a7665
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257033940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.2257033940
Directory /workspace/47.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.1262155835
Short name T568
Test name
Test status
Simulation time 4835890215 ps
CPU time 85.05 seconds
Started Aug 02 08:01:04 PM PDT 24
Finished Aug 02 08:02:29 PM PDT 24
Peak memory 573868 kb
Host smart-8d4f8c99-1236-4299-b95e-2b760592efd6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262155835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.1262155835
Directory /workspace/47.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_smoke_zero_delays.1843704080
Short name T2567
Test name
Test status
Simulation time 49481665 ps
CPU time 6.24 seconds
Started Aug 02 08:01:04 PM PDT 24
Finished Aug 02 08:01:10 PM PDT 24
Peak memory 574524 kb
Host smart-b22388ae-3e20-4d28-ab2d-809acfe6258c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843704080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delay
s.1843704080
Directory /workspace/47.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_stress_all.2980972364
Short name T1949
Test name
Test status
Simulation time 5803344557 ps
CPU time 202.89 seconds
Started Aug 02 08:01:17 PM PDT 24
Finished Aug 02 08:04:40 PM PDT 24
Peak memory 576104 kb
Host smart-7afab8d7-7021-49ad-8ab7-e1e017f2c57d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980972364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.2980972364
Directory /workspace/47.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_error.3979785525
Short name T2407
Test name
Test status
Simulation time 11752138936 ps
CPU time 407.39 seconds
Started Aug 02 08:01:20 PM PDT 24
Finished Aug 02 08:08:07 PM PDT 24
Peak memory 576800 kb
Host smart-74ecf792-692c-44f5-9bd6-c5a0e981160c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979785525 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.3979785525
Directory /workspace/47.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.2038628879
Short name T2687
Test name
Test status
Simulation time 324168940 ps
CPU time 157.35 seconds
Started Aug 02 08:01:16 PM PDT 24
Finished Aug 02 08:03:54 PM PDT 24
Peak memory 575908 kb
Host smart-1001e217-6d36-449e-bf6c-0ed00f1b7a91
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038628879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all
_with_rand_reset.2038628879
Directory /workspace/47.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.438191150
Short name T896
Test name
Test status
Simulation time 585476383 ps
CPU time 135.5 seconds
Started Aug 02 08:01:20 PM PDT 24
Finished Aug 02 08:03:35 PM PDT 24
Peak memory 576756 kb
Host smart-a531789a-f621-4828-afa8-f042086afbfd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438191150 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all
_with_reset_error.438191150
Directory /workspace/47.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_unmapped_addr.4154502019
Short name T2661
Test name
Test status
Simulation time 480575162 ps
CPU time 21.93 seconds
Started Aug 02 08:01:15 PM PDT 24
Finished Aug 02 08:01:37 PM PDT 24
Peak memory 575840 kb
Host smart-722cdfdd-cf30-42c2-91f8-ddba7b57433a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154502019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.4154502019
Directory /workspace/47.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_access_same_device.2322758879
Short name T484
Test name
Test status
Simulation time 838065910 ps
CPU time 55.55 seconds
Started Aug 02 08:01:15 PM PDT 24
Finished Aug 02 08:02:10 PM PDT 24
Peak memory 575780 kb
Host smart-983b7ac1-7169-4c7c-9da4-214254d789a7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322758879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device
.2322758879
Directory /workspace/48.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.1469145963
Short name T866
Test name
Test status
Simulation time 36958139230 ps
CPU time 651.28 seconds
Started Aug 02 08:01:16 PM PDT 24
Finished Aug 02 08:12:08 PM PDT 24
Peak memory 576152 kb
Host smart-34f14215-a631-4fcc-8a8a-806cbddcc1de
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469145963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_
device_slow_rsp.1469145963
Directory /workspace/48.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.1387645956
Short name T1413
Test name
Test status
Simulation time 1233018621 ps
CPU time 51.75 seconds
Started Aug 02 08:01:29 PM PDT 24
Finished Aug 02 08:02:21 PM PDT 24
Peak memory 575908 kb
Host smart-d9282624-8c89-4c57-88c9-1fcc93e28149
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387645956 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_add
r.1387645956
Directory /workspace/48.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_error_random.2918376213
Short name T1463
Test name
Test status
Simulation time 411153705 ps
CPU time 33.86 seconds
Started Aug 02 08:01:28 PM PDT 24
Finished Aug 02 08:02:02 PM PDT 24
Peak memory 576048 kb
Host smart-13af1b7d-fe59-46c3-89ed-eeef96154139
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918376213 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.2918376213
Directory /workspace/48.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_random.3460666504
Short name T1793
Test name
Test status
Simulation time 129397658 ps
CPU time 14.52 seconds
Started Aug 02 08:01:17 PM PDT 24
Finished Aug 02 08:01:32 PM PDT 24
Peak memory 575896 kb
Host smart-c8efaaf0-b2bc-4edd-994f-81cef7a7bea1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460666504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random.3460666504
Directory /workspace/48.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_random_large_delays.20188796
Short name T1527
Test name
Test status
Simulation time 24004566889 ps
CPU time 246.63 seconds
Started Aug 02 08:01:15 PM PDT 24
Finished Aug 02 08:05:21 PM PDT 24
Peak memory 575864 kb
Host smart-6f45d966-9b67-43b4-a670-5831be026bbe
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20188796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.20188796
Directory /workspace/48.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_random_slow_rsp.3244455261
Short name T2049
Test name
Test status
Simulation time 34677315620 ps
CPU time 625.97 seconds
Started Aug 02 08:01:16 PM PDT 24
Finished Aug 02 08:11:42 PM PDT 24
Peak memory 576004 kb
Host smart-fc7e87ec-df82-4682-84ca-048f8cdaf575
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244455261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.3244455261
Directory /workspace/48.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_random_zero_delays.1455660952
Short name T522
Test name
Test status
Simulation time 410739155 ps
CPU time 36.01 seconds
Started Aug 02 08:01:17 PM PDT 24
Finished Aug 02 08:01:53 PM PDT 24
Peak memory 575900 kb
Host smart-edc5cc1c-0cef-4adc-8fc4-d9179a879bf1
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455660952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_del
ays.1455660952
Directory /workspace/48.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_same_source.1466516124
Short name T2900
Test name
Test status
Simulation time 1255075103 ps
CPU time 37.76 seconds
Started Aug 02 08:01:36 PM PDT 24
Finished Aug 02 08:02:14 PM PDT 24
Peak memory 575904 kb
Host smart-30e9ace7-b553-43bd-a47b-28083ddcf26d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466516124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.1466516124
Directory /workspace/48.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_smoke.2934816034
Short name T2312
Test name
Test status
Simulation time 231107481 ps
CPU time 10.2 seconds
Started Aug 02 08:01:19 PM PDT 24
Finished Aug 02 08:01:29 PM PDT 24
Peak memory 574580 kb
Host smart-8586e5d5-f8e2-4447-b915-2b7fc4625712
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934816034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.2934816034
Directory /workspace/48.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_smoke_large_delays.961431236
Short name T1581
Test name
Test status
Simulation time 7700408815 ps
CPU time 82.16 seconds
Started Aug 02 08:01:19 PM PDT 24
Finished Aug 02 08:02:41 PM PDT 24
Peak memory 573940 kb
Host smart-afa57e73-6319-4647-af63-b4bbcfb131ab
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961431236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.961431236
Directory /workspace/48.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.1489131258
Short name T553
Test name
Test status
Simulation time 4780439224 ps
CPU time 76.6 seconds
Started Aug 02 08:01:16 PM PDT 24
Finished Aug 02 08:02:33 PM PDT 24
Peak memory 574636 kb
Host smart-c115794b-75c9-4395-9917-a13d3284c02b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489131258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.1489131258
Directory /workspace/48.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_smoke_zero_delays.730798977
Short name T1850
Test name
Test status
Simulation time 51762398 ps
CPU time 6.72 seconds
Started Aug 02 08:01:20 PM PDT 24
Finished Aug 02 08:01:26 PM PDT 24
Peak memory 573828 kb
Host smart-78cdf7a5-b400-4059-8979-b5271f2d07ac
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730798977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays
.730798977
Directory /workspace/48.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_stress_all.1622978942
Short name T2889
Test name
Test status
Simulation time 49168190 ps
CPU time 5.81 seconds
Started Aug 02 08:01:28 PM PDT 24
Finished Aug 02 08:01:34 PM PDT 24
Peak memory 574516 kb
Host smart-9a61f042-39d2-466b-85c8-5e9ee4045537
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622978942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.1622978942
Directory /workspace/48.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.3150518311
Short name T1691
Test name
Test status
Simulation time 1412730025 ps
CPU time 51.08 seconds
Started Aug 02 08:01:30 PM PDT 24
Finished Aug 02 08:02:21 PM PDT 24
Peak memory 575836 kb
Host smart-56136b55-81c0-4ede-a2f6-c9257313d662
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150518311 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.3150518311
Directory /workspace/48.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.4294059703
Short name T2283
Test name
Test status
Simulation time 44443591 ps
CPU time 58.65 seconds
Started Aug 02 08:01:31 PM PDT 24
Finished Aug 02 08:02:30 PM PDT 24
Peak memory 575928 kb
Host smart-ebc54efe-a429-44b2-bba4-3b9e99bb0153
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294059703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all
_with_rand_reset.4294059703
Directory /workspace/48.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.3328531136
Short name T1554
Test name
Test status
Simulation time 1372505303 ps
CPU time 205.29 seconds
Started Aug 02 08:01:28 PM PDT 24
Finished Aug 02 08:04:53 PM PDT 24
Peak memory 576752 kb
Host smart-371cc08e-199a-407e-8b58-175a311b2e31
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328531136 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_al
l_with_reset_error.3328531136
Directory /workspace/48.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.3609424862
Short name T2230
Test name
Test status
Simulation time 783260167 ps
CPU time 35.68 seconds
Started Aug 02 08:01:27 PM PDT 24
Finished Aug 02 08:02:03 PM PDT 24
Peak memory 575964 kb
Host smart-4744e010-2ec8-483a-b5d4-2474f257279e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609424862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.3609424862
Directory /workspace/48.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_access_same_device.4037217368
Short name T834
Test name
Test status
Simulation time 2440670062 ps
CPU time 90.75 seconds
Started Aug 02 08:01:27 PM PDT 24
Finished Aug 02 08:02:58 PM PDT 24
Peak memory 576012 kb
Host smart-8fdc4add-b16a-43f8-9e47-46d7f74fc870
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037217368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device
.4037217368
Directory /workspace/49.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.800835509
Short name T2517
Test name
Test status
Simulation time 68154118330 ps
CPU time 1190.78 seconds
Started Aug 02 08:01:28 PM PDT 24
Finished Aug 02 08:21:19 PM PDT 24
Peak memory 576064 kb
Host smart-210cb8e4-4752-4a0d-bc29-2495f235aa60
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800835509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_d
evice_slow_rsp.800835509
Directory /workspace/49.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.3249242537
Short name T2460
Test name
Test status
Simulation time 179042261 ps
CPU time 17.28 seconds
Started Aug 02 08:01:29 PM PDT 24
Finished Aug 02 08:01:46 PM PDT 24
Peak memory 575948 kb
Host smart-61fde849-3c59-4d10-b549-7d127ee4bcb1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249242537 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_add
r.3249242537
Directory /workspace/49.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_error_random.303112923
Short name T1692
Test name
Test status
Simulation time 202856774 ps
CPU time 20.51 seconds
Started Aug 02 08:01:30 PM PDT 24
Finished Aug 02 08:01:50 PM PDT 24
Peak memory 575948 kb
Host smart-741999a4-5788-48e2-8939-e5be65bd2829
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303112923 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.303112923
Directory /workspace/49.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_random.3191709801
Short name T2041
Test name
Test status
Simulation time 2354673432 ps
CPU time 86.21 seconds
Started Aug 02 08:01:33 PM PDT 24
Finished Aug 02 08:02:59 PM PDT 24
Peak memory 575792 kb
Host smart-66db3a82-f9a3-457d-ba3f-5e92632f9f25
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191709801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random.3191709801
Directory /workspace/49.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_random_large_delays.3066832780
Short name T1538
Test name
Test status
Simulation time 37239335427 ps
CPU time 381.2 seconds
Started Aug 02 08:01:27 PM PDT 24
Finished Aug 02 08:07:48 PM PDT 24
Peak memory 575944 kb
Host smart-da39b108-e0b0-410e-b729-c69dff99523c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066832780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.3066832780
Directory /workspace/49.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_random_slow_rsp.3737473084
Short name T1907
Test name
Test status
Simulation time 28892547333 ps
CPU time 477.12 seconds
Started Aug 02 08:01:27 PM PDT 24
Finished Aug 02 08:09:25 PM PDT 24
Peak memory 575952 kb
Host smart-517a52e9-ca42-4bf4-9d52-05ec1d2e8b7d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737473084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.3737473084
Directory /workspace/49.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.464644137
Short name T569
Test name
Test status
Simulation time 315511546 ps
CPU time 26.01 seconds
Started Aug 02 08:01:29 PM PDT 24
Finished Aug 02 08:01:55 PM PDT 24
Peak memory 575880 kb
Host smart-da1679e3-d57e-46c1-a2c3-7ddf23433c01
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464644137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_dela
ys.464644137
Directory /workspace/49.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_same_source.1249178915
Short name T1879
Test name
Test status
Simulation time 455769415 ps
CPU time 30.92 seconds
Started Aug 02 08:01:27 PM PDT 24
Finished Aug 02 08:01:58 PM PDT 24
Peak memory 575748 kb
Host smart-2cfc8cd5-1697-4caf-9351-5236f9fb9a57
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249178915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.1249178915
Directory /workspace/49.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_smoke.2824107939
Short name T2740
Test name
Test status
Simulation time 221782723 ps
CPU time 9.71 seconds
Started Aug 02 08:01:30 PM PDT 24
Finished Aug 02 08:01:40 PM PDT 24
Peak memory 574528 kb
Host smart-5da635f7-ea60-4036-bf5c-81844c8b9dcf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824107939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.2824107939
Directory /workspace/49.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_smoke_large_delays.3555805518
Short name T2548
Test name
Test status
Simulation time 5302587429 ps
CPU time 56.82 seconds
Started Aug 02 08:01:31 PM PDT 24
Finished Aug 02 08:02:28 PM PDT 24
Peak memory 573940 kb
Host smart-91cf07af-5433-41a9-ab47-40d132c3fdb1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555805518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.3555805518
Directory /workspace/49.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.41458943
Short name T1564
Test name
Test status
Simulation time 4412969821 ps
CPU time 73.94 seconds
Started Aug 02 08:01:33 PM PDT 24
Finished Aug 02 08:02:47 PM PDT 24
Peak memory 574544 kb
Host smart-0143d840-5387-4feb-87be-6f54055b2295
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41458943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.41458943
Directory /workspace/49.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_smoke_zero_delays.847796332
Short name T1557
Test name
Test status
Simulation time 38848223 ps
CPU time 5.7 seconds
Started Aug 02 08:01:29 PM PDT 24
Finished Aug 02 08:01:35 PM PDT 24
Peak memory 573848 kb
Host smart-bac5d026-0316-4366-9201-c2d7c4c8cb1d
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847796332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays
.847796332
Directory /workspace/49.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_stress_all.2829270974
Short name T2083
Test name
Test status
Simulation time 2956306155 ps
CPU time 113.19 seconds
Started Aug 02 08:01:32 PM PDT 24
Finished Aug 02 08:03:25 PM PDT 24
Peak memory 575976 kb
Host smart-c656c8dc-d248-4dd5-8da8-1a1766e9f359
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829270974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.2829270974
Directory /workspace/49.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.3269044466
Short name T2295
Test name
Test status
Simulation time 4550548016 ps
CPU time 314.35 seconds
Started Aug 02 08:01:29 PM PDT 24
Finished Aug 02 08:06:44 PM PDT 24
Peak memory 576100 kb
Host smart-c5476fc8-3bec-455f-97df-50240c373833
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269044466 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.3269044466
Directory /workspace/49.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.2464064132
Short name T517
Test name
Test status
Simulation time 9807661137 ps
CPU time 440.07 seconds
Started Aug 02 08:01:27 PM PDT 24
Finished Aug 02 08:08:47 PM PDT 24
Peak memory 575936 kb
Host smart-422956dd-3ed5-4721-a2fa-83c24ce8a156
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464064132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all
_with_rand_reset.2464064132
Directory /workspace/49.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.2450113152
Short name T891
Test name
Test status
Simulation time 2168917562 ps
CPU time 136.7 seconds
Started Aug 02 08:01:27 PM PDT 24
Finished Aug 02 08:03:43 PM PDT 24
Peak memory 576016 kb
Host smart-0a08cc86-e4d5-4931-8477-d000f7b7d9e5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450113152 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_al
l_with_reset_error.2450113152
Directory /workspace/49.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_unmapped_addr.430217697
Short name T2433
Test name
Test status
Simulation time 728935916 ps
CPU time 35.58 seconds
Started Aug 02 08:01:28 PM PDT 24
Finished Aug 02 08:02:04 PM PDT 24
Peak memory 575956 kb
Host smart-c4841f3b-b913-46a1-b75e-5b6869c83aca
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430217697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.430217697
Directory /workspace/49.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.3994650723
Short name T397
Test name
Test status
Simulation time 6183310324 ps
CPU time 547.48 seconds
Started Aug 02 07:52:37 PM PDT 24
Finished Aug 02 08:01:45 PM PDT 24
Peak memory 643152 kb
Host smart-3453a0c7-abef-4d51-85f0-8fdf173adcdf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994650723 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.chip_csr_mem_rw_with_rand_reset.3994650723
Directory /workspace/5.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.chip_csr_rw.500080130
Short name T453
Test name
Test status
Simulation time 4348456428 ps
CPU time 357.76 seconds
Started Aug 02 07:52:35 PM PDT 24
Finished Aug 02 07:58:32 PM PDT 24
Peak memory 597168 kb
Host smart-40f29951-261c-4f11-bba2-33fab484be79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500080130 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_rw.500080130
Directory /workspace/5.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.616934074
Short name T1724
Test name
Test status
Simulation time 28325522146 ps
CPU time 4494.37 seconds
Started Aug 02 07:52:27 PM PDT 24
Finished Aug 02 09:07:22 PM PDT 24
Peak memory 593636 kb
Host smart-d3a8c2a5-ed21-478d-a5b6-42eee0d89dda
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616934074 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.chip_same_csr_outstanding.616934074
Directory /workspace/5.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.chip_tl_errors.3769904018
Short name T2893
Test name
Test status
Simulation time 4242960008 ps
CPU time 288.5 seconds
Started Aug 02 07:52:25 PM PDT 24
Finished Aug 02 07:57:13 PM PDT 24
Peak memory 603732 kb
Host smart-0381faaf-a6dc-453d-ac1f-27387546ab42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769904018 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_tl_errors.3769904018
Directory /workspace/5.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_access_same_device.2268347437
Short name T1638
Test name
Test status
Simulation time 2593442392 ps
CPU time 108.43 seconds
Started Aug 02 07:52:27 PM PDT 24
Finished Aug 02 07:54:16 PM PDT 24
Peak memory 575936 kb
Host smart-6af32ef1-a26e-46d0-90d4-93a1e75e8001
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268347437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.
2268347437
Directory /workspace/5.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.3808180293
Short name T2915
Test name
Test status
Simulation time 54937918178 ps
CPU time 909.81 seconds
Started Aug 02 07:52:36 PM PDT 24
Finished Aug 02 08:07:46 PM PDT 24
Peak memory 575876 kb
Host smart-a6de50d3-e583-4868-9201-51b2e85d8322
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808180293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_d
evice_slow_rsp.3808180293
Directory /workspace/5.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.527963369
Short name T2921
Test name
Test status
Simulation time 194531069 ps
CPU time 22.18 seconds
Started Aug 02 07:52:48 PM PDT 24
Finished Aug 02 07:53:10 PM PDT 24
Peak memory 575980 kb
Host smart-f11fcc7f-60a9-4d37-b85e-1aaf16b3b843
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527963369 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.
527963369
Directory /workspace/5.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_error_random.1161713221
Short name T1651
Test name
Test status
Simulation time 402845039 ps
CPU time 13.87 seconds
Started Aug 02 07:52:38 PM PDT 24
Finished Aug 02 07:52:52 PM PDT 24
Peak memory 575748 kb
Host smart-395f7612-078a-4a6c-a0c5-57f4b807d642
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161713221 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.1161713221
Directory /workspace/5.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_random.1909393374
Short name T1510
Test name
Test status
Simulation time 304632931 ps
CPU time 13.67 seconds
Started Aug 02 07:52:25 PM PDT 24
Finished Aug 02 07:52:39 PM PDT 24
Peak memory 575924 kb
Host smart-b7d66c8c-ba7c-43b2-8ba9-bd87851d3948
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909393374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random.1909393374
Directory /workspace/5.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_random_large_delays.3716108917
Short name T530
Test name
Test status
Simulation time 104148136529 ps
CPU time 1048.86 seconds
Started Aug 02 07:52:27 PM PDT 24
Finished Aug 02 08:09:56 PM PDT 24
Peak memory 576836 kb
Host smart-4b9165bb-efea-4ef2-b0dd-1c315519a49b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716108917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.3716108917
Directory /workspace/5.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.458428272
Short name T2236
Test name
Test status
Simulation time 5156399528 ps
CPU time 82.96 seconds
Started Aug 02 07:52:33 PM PDT 24
Finished Aug 02 07:53:56 PM PDT 24
Peak memory 573952 kb
Host smart-6ab60cb4-3cca-4ef6-a6f9-40be7d8d8c06
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458428272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.458428272
Directory /workspace/5.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_random_zero_delays.3562011930
Short name T2825
Test name
Test status
Simulation time 603024431 ps
CPU time 53.42 seconds
Started Aug 02 07:52:26 PM PDT 24
Finished Aug 02 07:53:20 PM PDT 24
Peak memory 575816 kb
Host smart-7cb3163e-5dde-47ce-bd51-9e581af8baa9
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562011930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_dela
ys.3562011930
Directory /workspace/5.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_same_source.1780063203
Short name T1871
Test name
Test status
Simulation time 54775252 ps
CPU time 6.98 seconds
Started Aug 02 07:52:36 PM PDT 24
Finished Aug 02 07:52:43 PM PDT 24
Peak memory 574516 kb
Host smart-2bbc4b72-2867-4b92-9a3e-6aed13c4e818
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780063203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.1780063203
Directory /workspace/5.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_smoke.3488236916
Short name T1796
Test name
Test status
Simulation time 117088491 ps
CPU time 6.76 seconds
Started Aug 02 07:52:29 PM PDT 24
Finished Aug 02 07:52:36 PM PDT 24
Peak memory 574628 kb
Host smart-25ef465d-f90a-4bbd-a43a-d4682002b4fd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488236916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.3488236916
Directory /workspace/5.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_smoke_large_delays.4079154742
Short name T1440
Test name
Test status
Simulation time 9882325830 ps
CPU time 108.16 seconds
Started Aug 02 07:52:26 PM PDT 24
Finished Aug 02 07:54:14 PM PDT 24
Peak memory 573924 kb
Host smart-23207793-8f68-4a5d-858f-90dfc0b1d586
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079154742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.4079154742
Directory /workspace/5.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.3044316148
Short name T2396
Test name
Test status
Simulation time 3888055889 ps
CPU time 67.69 seconds
Started Aug 02 07:52:31 PM PDT 24
Finished Aug 02 07:53:39 PM PDT 24
Peak memory 573888 kb
Host smart-7ab44e98-d28e-4cb8-aaf5-8aa042158053
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044316148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.3044316148
Directory /workspace/5.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_smoke_zero_delays.4196280951
Short name T2350
Test name
Test status
Simulation time 50173487 ps
CPU time 6.13 seconds
Started Aug 02 07:52:26 PM PDT 24
Finished Aug 02 07:52:32 PM PDT 24
Peak memory 574508 kb
Host smart-cec5beda-4b7a-408b-9c46-abb69798149d
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196280951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays
.4196280951
Directory /workspace/5.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_stress_all.3308318952
Short name T1941
Test name
Test status
Simulation time 3229965740 ps
CPU time 264.67 seconds
Started Aug 02 07:52:48 PM PDT 24
Finished Aug 02 07:57:13 PM PDT 24
Peak memory 576024 kb
Host smart-1ab6f90d-8ed3-4316-aedd-b30129e55e71
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308318952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.3308318952
Directory /workspace/5.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.778243201
Short name T1979
Test name
Test status
Simulation time 3012792894 ps
CPU time 208 seconds
Started Aug 02 07:52:48 PM PDT 24
Finished Aug 02 07:56:16 PM PDT 24
Peak memory 576780 kb
Host smart-2361288f-4f5a-4a7c-b4e6-f797da87f49a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778243201 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.778243201
Directory /workspace/5.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.2788087094
Short name T2204
Test name
Test status
Simulation time 91193145 ps
CPU time 21.73 seconds
Started Aug 02 07:52:38 PM PDT 24
Finished Aug 02 07:53:00 PM PDT 24
Peak memory 576008 kb
Host smart-c2a95b9f-dfd1-4261-981a-322db1d6f3cd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788087094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_
with_rand_reset.2788087094
Directory /workspace/5.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.1814187279
Short name T2186
Test name
Test status
Simulation time 5815830716 ps
CPU time 347.61 seconds
Started Aug 02 07:52:48 PM PDT 24
Finished Aug 02 07:58:36 PM PDT 24
Peak memory 576812 kb
Host smart-0a225949-1a59-479d-87bd-c11a1318c493
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814187279 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all
_with_reset_error.1814187279
Directory /workspace/5.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.1294782568
Short name T2267
Test name
Test status
Simulation time 161188679 ps
CPU time 20.56 seconds
Started Aug 02 07:52:36 PM PDT 24
Finished Aug 02 07:52:57 PM PDT 24
Peak memory 575888 kb
Host smart-008e359f-dba9-4a57-8278-964996ccf40e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294782568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.1294782568
Directory /workspace/5.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_access_same_device.2243840493
Short name T1827
Test name
Test status
Simulation time 1928274913 ps
CPU time 75.63 seconds
Started Aug 02 08:01:39 PM PDT 24
Finished Aug 02 08:02:55 PM PDT 24
Peak memory 575968 kb
Host smart-db004de2-dfb2-49e8-a4bd-389217e1fe00
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243840493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device
.2243840493
Directory /workspace/50.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.4179420072
Short name T869
Test name
Test status
Simulation time 134787219363 ps
CPU time 2357.21 seconds
Started Aug 02 08:01:40 PM PDT 24
Finished Aug 02 08:40:57 PM PDT 24
Peak memory 576832 kb
Host smart-f8585060-3ca2-4b7a-b70d-60a8cc04853c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179420072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_
device_slow_rsp.4179420072
Directory /workspace/50.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.1460674362
Short name T2103
Test name
Test status
Simulation time 370863568 ps
CPU time 14.5 seconds
Started Aug 02 08:01:41 PM PDT 24
Finished Aug 02 08:01:56 PM PDT 24
Peak memory 575844 kb
Host smart-c42bd544-353e-4763-a0ce-c486582f1b1b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460674362 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_and_unmapped_add
r.1460674362
Directory /workspace/50.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_error_random.647053482
Short name T2243
Test name
Test status
Simulation time 1367797734 ps
CPU time 43.04 seconds
Started Aug 02 08:01:40 PM PDT 24
Finished Aug 02 08:02:23 PM PDT 24
Peak memory 575904 kb
Host smart-a0b10c4b-d39e-4dd6-ae54-25497fac38d8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647053482 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_random.647053482
Directory /workspace/50.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_random.521987100
Short name T2125
Test name
Test status
Simulation time 341900652 ps
CPU time 30.01 seconds
Started Aug 02 08:01:39 PM PDT 24
Finished Aug 02 08:02:09 PM PDT 24
Peak memory 575884 kb
Host smart-8e8d0f15-b3ec-4f8b-bd28-b123d2fff9f2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521987100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random.521987100
Directory /workspace/50.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_random_large_delays.1396175396
Short name T1791
Test name
Test status
Simulation time 72163346989 ps
CPU time 750.03 seconds
Started Aug 02 08:01:42 PM PDT 24
Finished Aug 02 08:14:12 PM PDT 24
Peak memory 576084 kb
Host smart-7601977b-61d1-4317-aa78-03cd185b8548
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396175396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_large_delays.1396175396
Directory /workspace/50.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.4106985077
Short name T1997
Test name
Test status
Simulation time 7403859472 ps
CPU time 124.26 seconds
Started Aug 02 08:01:40 PM PDT 24
Finished Aug 02 08:03:44 PM PDT 24
Peak memory 575868 kb
Host smart-a1ef0f0a-cf9b-41d9-ad7c-e68b356915e1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106985077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_slow_rsp.4106985077
Directory /workspace/50.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_random_zero_delays.797007854
Short name T2323
Test name
Test status
Simulation time 182514356 ps
CPU time 19.54 seconds
Started Aug 02 08:01:41 PM PDT 24
Finished Aug 02 08:02:01 PM PDT 24
Peak memory 575892 kb
Host smart-b17d957f-f014-4d8d-85db-bfe11a957a3b
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797007854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_zero_dela
ys.797007854
Directory /workspace/50.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_same_source.3531222605
Short name T2812
Test name
Test status
Simulation time 467192589 ps
CPU time 36.71 seconds
Started Aug 02 08:01:40 PM PDT 24
Finished Aug 02 08:02:16 PM PDT 24
Peak memory 575808 kb
Host smart-ecee6a60-2a47-4881-b1ae-7b4825dbe301
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531222605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_same_source.3531222605
Directory /workspace/50.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_smoke.779126344
Short name T2534
Test name
Test status
Simulation time 48179068 ps
CPU time 5.93 seconds
Started Aug 02 08:01:27 PM PDT 24
Finished Aug 02 08:01:33 PM PDT 24
Peak memory 573932 kb
Host smart-c44c6cd0-d9ec-4ef5-8d9d-1165364b7bc4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779126344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke.779126344
Directory /workspace/50.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_smoke_large_delays.3534681183
Short name T1502
Test name
Test status
Simulation time 7438809216 ps
CPU time 73.64 seconds
Started Aug 02 08:01:27 PM PDT 24
Finished Aug 02 08:02:41 PM PDT 24
Peak memory 574740 kb
Host smart-245460b7-4902-4bb0-8e1e-2e4ad897722c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534681183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_large_delays.3534681183
Directory /workspace/50.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.2978551232
Short name T2075
Test name
Test status
Simulation time 5838810782 ps
CPU time 98.83 seconds
Started Aug 02 08:01:27 PM PDT 24
Finished Aug 02 08:03:06 PM PDT 24
Peak memory 574576 kb
Host smart-3a14c1d4-df02-401b-9ee8-37f28a71afde
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978551232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_slow_rsp.2978551232
Directory /workspace/50.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_smoke_zero_delays.2962969703
Short name T2005
Test name
Test status
Simulation time 47057321 ps
CPU time 6.66 seconds
Started Aug 02 08:01:30 PM PDT 24
Finished Aug 02 08:01:37 PM PDT 24
Peak memory 573752 kb
Host smart-001a35b6-2f6e-40e7-9949-577de984dd49
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962969703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_zero_delay
s.2962969703
Directory /workspace/50.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_stress_all.3307013750
Short name T457
Test name
Test status
Simulation time 5168848088 ps
CPU time 171.07 seconds
Started Aug 02 08:01:40 PM PDT 24
Finished Aug 02 08:04:31 PM PDT 24
Peak memory 576088 kb
Host smart-ea7522f6-099e-40b2-9a38-bf930b35a6f6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307013750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all.3307013750
Directory /workspace/50.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.3761280146
Short name T2213
Test name
Test status
Simulation time 9942475001 ps
CPU time 528.6 seconds
Started Aug 02 08:01:44 PM PDT 24
Finished Aug 02 08:10:33 PM PDT 24
Peak memory 576020 kb
Host smart-dd1a0e99-9f31-4971-8678-0fc53c2ffe2e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761280146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all
_with_rand_reset.3761280146
Directory /workspace/50.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.1604148929
Short name T2577
Test name
Test status
Simulation time 381339296 ps
CPU time 120.79 seconds
Started Aug 02 08:01:39 PM PDT 24
Finished Aug 02 08:03:40 PM PDT 24
Peak memory 576788 kb
Host smart-21b0f3ee-b898-4c4c-af81-9b9ad940e1a0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604148929 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_al
l_with_reset_error.1604148929
Directory /workspace/50.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.740051056
Short name T581
Test name
Test status
Simulation time 177374305 ps
CPU time 21.94 seconds
Started Aug 02 08:01:41 PM PDT 24
Finished Aug 02 08:02:03 PM PDT 24
Peak memory 575928 kb
Host smart-299d69d9-e1ce-4970-8b88-fc9f3ae7e3d5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740051056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_unmapped_addr.740051056
Directory /workspace/50.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_access_same_device.2577772090
Short name T2201
Test name
Test status
Simulation time 351387220 ps
CPU time 16.68 seconds
Started Aug 02 08:01:53 PM PDT 24
Finished Aug 02 08:02:10 PM PDT 24
Peak memory 575712 kb
Host smart-d9655f01-1fb9-4fa9-8725-7f718d4fa24f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577772090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device
.2577772090
Directory /workspace/51.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.170952941
Short name T2590
Test name
Test status
Simulation time 80394413227 ps
CPU time 1405.34 seconds
Started Aug 02 08:01:53 PM PDT 24
Finished Aug 02 08:25:19 PM PDT 24
Peak memory 576016 kb
Host smart-3caf772b-b362-4a5d-89a6-5342adadd7f1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170952941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_d
evice_slow_rsp.170952941
Directory /workspace/51.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.991457409
Short name T2664
Test name
Test status
Simulation time 309358333 ps
CPU time 31.9 seconds
Started Aug 02 08:01:54 PM PDT 24
Finished Aug 02 08:02:25 PM PDT 24
Peak memory 575896 kb
Host smart-4d4e079b-00c0-4c0d-8e24-931f699b5479
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991457409 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_and_unmapped_addr
.991457409
Directory /workspace/51.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_error_random.1875611641
Short name T1761
Test name
Test status
Simulation time 263712918 ps
CPU time 23.8 seconds
Started Aug 02 08:01:54 PM PDT 24
Finished Aug 02 08:02:18 PM PDT 24
Peak memory 575908 kb
Host smart-2bb84d76-d978-4d89-acbe-21d990d30544
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875611641 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_random.1875611641
Directory /workspace/51.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_random.1065204995
Short name T2327
Test name
Test status
Simulation time 872374065 ps
CPU time 34.69 seconds
Started Aug 02 08:01:41 PM PDT 24
Finished Aug 02 08:02:16 PM PDT 24
Peak memory 575868 kb
Host smart-91079c0d-a3b3-40c7-adcd-6a3820ceb1ac
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065204995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random.1065204995
Directory /workspace/51.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_random_large_delays.1554171480
Short name T2169
Test name
Test status
Simulation time 30392420951 ps
CPU time 301.33 seconds
Started Aug 02 08:01:53 PM PDT 24
Finished Aug 02 08:06:54 PM PDT 24
Peak memory 575980 kb
Host smart-5ae1fa79-57e1-4ceb-af2e-be22a0bfd6fe
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554171480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_large_delays.1554171480
Directory /workspace/51.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_random_slow_rsp.1228847051
Short name T2294
Test name
Test status
Simulation time 27943563396 ps
CPU time 477.76 seconds
Started Aug 02 08:02:01 PM PDT 24
Finished Aug 02 08:09:59 PM PDT 24
Peak memory 576100 kb
Host smart-62ec30dd-b08e-486e-bfd6-a980df61cc10
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228847051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_slow_rsp.1228847051
Directory /workspace/51.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_random_zero_delays.1702377073
Short name T1884
Test name
Test status
Simulation time 461282977 ps
CPU time 35.09 seconds
Started Aug 02 08:01:41 PM PDT 24
Finished Aug 02 08:02:16 PM PDT 24
Peak memory 575868 kb
Host smart-57ca55f1-18ec-4036-a56b-3a0ced971d24
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702377073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_zero_del
ays.1702377073
Directory /workspace/51.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_same_source.217646500
Short name T482
Test name
Test status
Simulation time 1577908727 ps
CPU time 50.15 seconds
Started Aug 02 08:01:53 PM PDT 24
Finished Aug 02 08:02:43 PM PDT 24
Peak memory 575812 kb
Host smart-f2e60c14-e447-4ee4-879e-0c9f513c0f37
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217646500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_same_source.217646500
Directory /workspace/51.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_smoke.59822197
Short name T2695
Test name
Test status
Simulation time 215757594 ps
CPU time 9.95 seconds
Started Aug 02 08:01:40 PM PDT 24
Finished Aug 02 08:01:50 PM PDT 24
Peak memory 574492 kb
Host smart-2edd6ff0-4769-4881-b8e2-9dac20289ebc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59822197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke.59822197
Directory /workspace/51.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_smoke_large_delays.4020363391
Short name T1798
Test name
Test status
Simulation time 6105460097 ps
CPU time 62.79 seconds
Started Aug 02 08:01:40 PM PDT 24
Finished Aug 02 08:02:42 PM PDT 24
Peak memory 573908 kb
Host smart-088fd0a4-5038-4599-980e-69960e8c7ca0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020363391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_large_delays.4020363391
Directory /workspace/51.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.1619526103
Short name T2570
Test name
Test status
Simulation time 4414758835 ps
CPU time 74.72 seconds
Started Aug 02 08:01:44 PM PDT 24
Finished Aug 02 08:02:59 PM PDT 24
Peak memory 573920 kb
Host smart-f68c4bdf-f1ce-4610-afc1-053b958aeb50
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619526103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_slow_rsp.1619526103
Directory /workspace/51.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_smoke_zero_delays.3840853039
Short name T2502
Test name
Test status
Simulation time 48971361 ps
CPU time 6.39 seconds
Started Aug 02 08:01:41 PM PDT 24
Finished Aug 02 08:01:47 PM PDT 24
Peak memory 573744 kb
Host smart-e39e6af3-097d-4eb2-9886-32e63faff4e6
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840853039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_zero_delay
s.3840853039
Directory /workspace/51.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_stress_all.1619922120
Short name T2692
Test name
Test status
Simulation time 2618937574 ps
CPU time 166.08 seconds
Started Aug 02 08:01:51 PM PDT 24
Finished Aug 02 08:04:37 PM PDT 24
Peak memory 576788 kb
Host smart-c685cf03-8b1c-4f92-bf73-60f05ee143b7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619922120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all.1619922120
Directory /workspace/51.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.874407401
Short name T2356
Test name
Test status
Simulation time 3897447852 ps
CPU time 137.23 seconds
Started Aug 02 08:02:02 PM PDT 24
Finished Aug 02 08:04:19 PM PDT 24
Peak memory 576096 kb
Host smart-5dad9e34-03a0-46a2-a9c1-3776d0b51931
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874407401 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_error.874407401
Directory /workspace/51.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.1457659287
Short name T886
Test name
Test status
Simulation time 843713388 ps
CPU time 338.09 seconds
Started Aug 02 08:01:52 PM PDT 24
Finished Aug 02 08:07:31 PM PDT 24
Peak memory 575880 kb
Host smart-af7a6060-2ef7-4ce6-900a-0c918790e98b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457659287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all
_with_rand_reset.1457659287
Directory /workspace/51.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.4227495409
Short name T2513
Test name
Test status
Simulation time 22850101 ps
CPU time 10.06 seconds
Started Aug 02 08:01:54 PM PDT 24
Finished Aug 02 08:02:04 PM PDT 24
Peak memory 574012 kb
Host smart-fee710f4-7e15-4f3d-9e37-d44ce8144c73
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227495409 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_al
l_with_reset_error.4227495409
Directory /workspace/51.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.2179224132
Short name T2923
Test name
Test status
Simulation time 130388534 ps
CPU time 16.38 seconds
Started Aug 02 08:01:55 PM PDT 24
Finished Aug 02 08:02:11 PM PDT 24
Peak memory 575944 kb
Host smart-cf26cee0-5ede-4958-aee2-790812f649de
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179224132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_unmapped_addr.2179224132
Directory /workspace/51.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_access_same_device.1909452915
Short name T2872
Test name
Test status
Simulation time 1354032979 ps
CPU time 93.79 seconds
Started Aug 02 08:02:04 PM PDT 24
Finished Aug 02 08:03:37 PM PDT 24
Peak memory 575948 kb
Host smart-8840c0c3-2be7-4b2d-81c2-43d788afdb28
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909452915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device
.1909452915
Directory /workspace/52.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.1998867338
Short name T1637
Test name
Test status
Simulation time 125257947016 ps
CPU time 2287.02 seconds
Started Aug 02 08:02:04 PM PDT 24
Finished Aug 02 08:40:11 PM PDT 24
Peak memory 576096 kb
Host smart-a0bcd762-b452-49cb-acb8-d93a00fa75df
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998867338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_
device_slow_rsp.1998867338
Directory /workspace/52.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.2842298464
Short name T1789
Test name
Test status
Simulation time 37381332 ps
CPU time 6.8 seconds
Started Aug 02 08:02:02 PM PDT 24
Finished Aug 02 08:02:09 PM PDT 24
Peak memory 573888 kb
Host smart-d6b11107-c163-4952-ab3a-a5534e8b8f09
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842298464 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_and_unmapped_add
r.2842298464
Directory /workspace/52.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_error_random.612014186
Short name T2012
Test name
Test status
Simulation time 936980413 ps
CPU time 29.28 seconds
Started Aug 02 08:02:04 PM PDT 24
Finished Aug 02 08:02:34 PM PDT 24
Peak memory 575868 kb
Host smart-7c6f67c6-b7d7-46ef-a038-9585c59ad591
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612014186 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_random.612014186
Directory /workspace/52.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_random.2438800587
Short name T1528
Test name
Test status
Simulation time 35395886 ps
CPU time 6.45 seconds
Started Aug 02 08:01:53 PM PDT 24
Finished Aug 02 08:02:00 PM PDT 24
Peak memory 574508 kb
Host smart-d4492d4e-071b-4573-a0ec-148c5738f896
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438800587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random.2438800587
Directory /workspace/52.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_random_large_delays.3525770284
Short name T2137
Test name
Test status
Simulation time 39124236786 ps
CPU time 391.08 seconds
Started Aug 02 08:01:53 PM PDT 24
Finished Aug 02 08:08:24 PM PDT 24
Peak memory 576008 kb
Host smart-61aa30fa-8803-4742-944b-bd64131725f8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525770284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_large_delays.3525770284
Directory /workspace/52.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.170966159
Short name T2113
Test name
Test status
Simulation time 51449904141 ps
CPU time 912.63 seconds
Started Aug 02 08:02:01 PM PDT 24
Finished Aug 02 08:17:14 PM PDT 24
Peak memory 575920 kb
Host smart-5880b779-6099-4862-be5a-ee2b845d7c47
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170966159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_slow_rsp.170966159
Directory /workspace/52.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_random_zero_delays.2034105585
Short name T1891
Test name
Test status
Simulation time 164171357 ps
CPU time 14.55 seconds
Started Aug 02 08:01:55 PM PDT 24
Finished Aug 02 08:02:09 PM PDT 24
Peak memory 575800 kb
Host smart-430641d3-8b16-4917-85ca-c2bd7e939806
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034105585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_zero_del
ays.2034105585
Directory /workspace/52.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_same_source.3045108762
Short name T488
Test name
Test status
Simulation time 546193014 ps
CPU time 43.71 seconds
Started Aug 02 08:02:04 PM PDT 24
Finished Aug 02 08:02:48 PM PDT 24
Peak memory 575824 kb
Host smart-094e135d-ff37-430b-bf3b-58c2026324b0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045108762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_same_source.3045108762
Directory /workspace/52.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_smoke.3912427713
Short name T2906
Test name
Test status
Simulation time 47202029 ps
CPU time 5.84 seconds
Started Aug 02 08:01:55 PM PDT 24
Finished Aug 02 08:02:01 PM PDT 24
Peak memory 574612 kb
Host smart-48da43cc-31ee-44a4-b580-6833fc3d101e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912427713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke.3912427713
Directory /workspace/52.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.2241240241
Short name T2464
Test name
Test status
Simulation time 7207015940 ps
CPU time 74.01 seconds
Started Aug 02 08:02:01 PM PDT 24
Finished Aug 02 08:03:15 PM PDT 24
Peak memory 573964 kb
Host smart-69aad608-dbc8-4c7c-ba9a-57462ff67b3b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241240241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_large_delays.2241240241
Directory /workspace/52.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.1854246696
Short name T1679
Test name
Test status
Simulation time 4665522994 ps
CPU time 73.83 seconds
Started Aug 02 08:01:51 PM PDT 24
Finished Aug 02 08:03:05 PM PDT 24
Peak memory 573884 kb
Host smart-f825599c-2ef9-4ba7-a3cd-b0fa978e3f55
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854246696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_slow_rsp.1854246696
Directory /workspace/52.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.2915299126
Short name T2676
Test name
Test status
Simulation time 43075170 ps
CPU time 6.54 seconds
Started Aug 02 08:01:53 PM PDT 24
Finished Aug 02 08:02:00 PM PDT 24
Peak memory 574552 kb
Host smart-9152379f-40ab-4456-9fa0-eeca6cd74e69
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915299126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_zero_delay
s.2915299126
Directory /workspace/52.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_stress_all.442760247
Short name T2348
Test name
Test status
Simulation time 4127581464 ps
CPU time 142.06 seconds
Started Aug 02 08:02:05 PM PDT 24
Finished Aug 02 08:04:28 PM PDT 24
Peak memory 576092 kb
Host smart-efd46741-ceaf-4ec6-b970-3ff8bba66ae0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442760247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all.442760247
Directory /workspace/52.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.4097545187
Short name T674
Test name
Test status
Simulation time 2590051990 ps
CPU time 105.35 seconds
Started Aug 02 08:02:05 PM PDT 24
Finished Aug 02 08:03:50 PM PDT 24
Peak memory 576004 kb
Host smart-d9f6be19-0ff4-48ec-a5a9-b24d123699d3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097545187 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_error.4097545187
Directory /workspace/52.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.875420921
Short name T2689
Test name
Test status
Simulation time 423329298 ps
CPU time 198.38 seconds
Started Aug 02 08:02:09 PM PDT 24
Finished Aug 02 08:05:27 PM PDT 24
Peak memory 576564 kb
Host smart-eb262302-873a-465c-987d-87f86cbd9808
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875420921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_
with_rand_reset.875420921
Directory /workspace/52.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.1547165987
Short name T2706
Test name
Test status
Simulation time 295164461 ps
CPU time 95.42 seconds
Started Aug 02 08:02:04 PM PDT 24
Finished Aug 02 08:03:40 PM PDT 24
Peak memory 576648 kb
Host smart-80788e8e-56d3-48e7-a8f1-fd7aca8aba5a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547165987 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_al
l_with_reset_error.1547165987
Directory /workspace/52.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_unmapped_addr.1956192625
Short name T673
Test name
Test status
Simulation time 221807093 ps
CPU time 25.6 seconds
Started Aug 02 08:02:06 PM PDT 24
Finished Aug 02 08:02:32 PM PDT 24
Peak memory 575908 kb
Host smart-99e2173b-04da-4e46-80de-4b87d87b1c59
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956192625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_unmapped_addr.1956192625
Directory /workspace/52.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_access_same_device.3405550572
Short name T2579
Test name
Test status
Simulation time 3017902210 ps
CPU time 111.7 seconds
Started Aug 02 08:02:03 PM PDT 24
Finished Aug 02 08:03:55 PM PDT 24
Peak memory 576048 kb
Host smart-a0af607e-c656-4db3-8827-4d66f84643b7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405550572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device
.3405550572
Directory /workspace/53.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.3954499934
Short name T2246
Test name
Test status
Simulation time 104690477331 ps
CPU time 1745.27 seconds
Started Aug 02 08:02:07 PM PDT 24
Finished Aug 02 08:31:13 PM PDT 24
Peak memory 576080 kb
Host smart-c56f0024-8aad-4c3c-afc4-80aa3e9a42a8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954499934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_
device_slow_rsp.3954499934
Directory /workspace/53.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.1308503415
Short name T1817
Test name
Test status
Simulation time 123485567 ps
CPU time 14.67 seconds
Started Aug 02 08:02:18 PM PDT 24
Finished Aug 02 08:02:33 PM PDT 24
Peak memory 575976 kb
Host smart-d1d8dc66-68c7-496b-bd7e-47cbf10519dd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308503415 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_and_unmapped_add
r.1308503415
Directory /workspace/53.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_error_random.2462589698
Short name T1622
Test name
Test status
Simulation time 42044394 ps
CPU time 5.56 seconds
Started Aug 02 08:02:21 PM PDT 24
Finished Aug 02 08:02:26 PM PDT 24
Peak memory 574488 kb
Host smart-ab52b5df-dd54-45c8-9da4-cc5c0ad044bd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462589698 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_random.2462589698
Directory /workspace/53.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_random.761818443
Short name T1910
Test name
Test status
Simulation time 373769133 ps
CPU time 16.22 seconds
Started Aug 02 08:02:04 PM PDT 24
Finished Aug 02 08:02:20 PM PDT 24
Peak memory 575808 kb
Host smart-3f5c71df-d75d-47f1-aca6-79bf4b4aa52e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761818443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random.761818443
Directory /workspace/53.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_random_large_delays.3887043200
Short name T2501
Test name
Test status
Simulation time 36003308689 ps
CPU time 375.26 seconds
Started Aug 02 08:02:05 PM PDT 24
Finished Aug 02 08:08:20 PM PDT 24
Peak memory 576088 kb
Host smart-23f8ae5e-0cc8-4666-9baa-9bf437ea6121
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887043200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_large_delays.3887043200
Directory /workspace/53.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.1595112018
Short name T2140
Test name
Test status
Simulation time 5939318862 ps
CPU time 103.22 seconds
Started Aug 02 08:02:04 PM PDT 24
Finished Aug 02 08:03:47 PM PDT 24
Peak memory 574728 kb
Host smart-4797abcd-8259-4294-8abc-0ff35c59baba
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595112018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_slow_rsp.1595112018
Directory /workspace/53.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_random_zero_delays.1389186882
Short name T1755
Test name
Test status
Simulation time 379940761 ps
CPU time 32 seconds
Started Aug 02 08:02:04 PM PDT 24
Finished Aug 02 08:02:36 PM PDT 24
Peak memory 575828 kb
Host smart-037b2000-d775-462b-977a-48e4ab18ed94
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389186882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_zero_del
ays.1389186882
Directory /workspace/53.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_same_source.90733546
Short name T620
Test name
Test status
Simulation time 539852804 ps
CPU time 18.44 seconds
Started Aug 02 08:02:19 PM PDT 24
Finished Aug 02 08:02:37 PM PDT 24
Peak memory 575900 kb
Host smart-0cf3529b-e6a5-4c6c-9fec-137288dd9deb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90733546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_same_source.90733546
Directory /workspace/53.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_smoke.1114209953
Short name T1854
Test name
Test status
Simulation time 246707422 ps
CPU time 9.39 seconds
Started Aug 02 08:02:07 PM PDT 24
Finished Aug 02 08:02:17 PM PDT 24
Peak memory 574508 kb
Host smart-2428dc39-bbbc-4a66-827c-08431f85e640
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114209953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke.1114209953
Directory /workspace/53.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_smoke_large_delays.2577663799
Short name T2721
Test name
Test status
Simulation time 9437795082 ps
CPU time 95.02 seconds
Started Aug 02 08:02:03 PM PDT 24
Finished Aug 02 08:03:38 PM PDT 24
Peak memory 573868 kb
Host smart-ceff1b30-8973-46d4-8ea9-e6dc7c437a10
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577663799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_large_delays.2577663799
Directory /workspace/53.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.1914355271
Short name T2759
Test name
Test status
Simulation time 3834998472 ps
CPU time 61.77 seconds
Started Aug 02 08:02:09 PM PDT 24
Finished Aug 02 08:03:11 PM PDT 24
Peak memory 574424 kb
Host smart-1a11f00d-4737-4959-a10f-abac93257279
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914355271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_slow_rsp.1914355271
Directory /workspace/53.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_smoke_zero_delays.792576173
Short name T2034
Test name
Test status
Simulation time 45908440 ps
CPU time 6.51 seconds
Started Aug 02 08:02:04 PM PDT 24
Finished Aug 02 08:02:11 PM PDT 24
Peak memory 574476 kb
Host smart-6f2ef279-0744-4d4b-910a-379a0aa7e4dc
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792576173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_zero_delays
.792576173
Directory /workspace/53.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_stress_all.1201605144
Short name T2270
Test name
Test status
Simulation time 6112363348 ps
CPU time 210.43 seconds
Started Aug 02 08:02:18 PM PDT 24
Finished Aug 02 08:05:48 PM PDT 24
Peak memory 576084 kb
Host smart-a4ff7ba0-6d76-40a0-a033-308a1a9795e6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201605144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all.1201605144
Directory /workspace/53.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.1291995665
Short name T1769
Test name
Test status
Simulation time 8554819953 ps
CPU time 296.79 seconds
Started Aug 02 08:02:21 PM PDT 24
Finished Aug 02 08:07:18 PM PDT 24
Peak memory 576064 kb
Host smart-fdae501f-6767-4ab3-989c-a16acfda0218
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291995665 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_error.1291995665
Directory /workspace/53.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.3745211111
Short name T2389
Test name
Test status
Simulation time 244488537 ps
CPU time 53.21 seconds
Started Aug 02 08:02:18 PM PDT 24
Finished Aug 02 08:03:11 PM PDT 24
Peak memory 576668 kb
Host smart-f5da1648-f9d2-484b-88af-24b2f1aebed8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745211111 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_al
l_with_reset_error.3745211111
Directory /workspace/53.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_unmapped_addr.3793762382
Short name T1704
Test name
Test status
Simulation time 124598655 ps
CPU time 16.51 seconds
Started Aug 02 08:02:19 PM PDT 24
Finished Aug 02 08:02:36 PM PDT 24
Peak memory 576004 kb
Host smart-df4e1e89-f060-486f-a52d-685b3b7c957e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793762382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_unmapped_addr.3793762382
Directory /workspace/53.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_access_same_device.3092013704
Short name T2892
Test name
Test status
Simulation time 1743333307 ps
CPU time 64.73 seconds
Started Aug 02 08:02:19 PM PDT 24
Finished Aug 02 08:03:24 PM PDT 24
Peak memory 575740 kb
Host smart-4541f2b7-695c-46d5-8350-77ed54cee2f5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092013704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device
.3092013704
Directory /workspace/54.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.1044167505
Short name T2845
Test name
Test status
Simulation time 833132083 ps
CPU time 31.65 seconds
Started Aug 02 08:02:43 PM PDT 24
Finished Aug 02 08:03:14 PM PDT 24
Peak memory 575684 kb
Host smart-000241d7-93c9-48c2-abfe-4f57a70e0659
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044167505 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_and_unmapped_add
r.1044167505
Directory /workspace/54.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_error_random.56645941
Short name T2899
Test name
Test status
Simulation time 917234243 ps
CPU time 34.26 seconds
Started Aug 02 08:02:36 PM PDT 24
Finished Aug 02 08:03:10 PM PDT 24
Peak memory 575920 kb
Host smart-d9a7819e-972e-46b4-9608-652b868fad02
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56645941 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_random.56645941
Directory /workspace/54.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_random.494754744
Short name T1837
Test name
Test status
Simulation time 2192549637 ps
CPU time 75.69 seconds
Started Aug 02 08:02:21 PM PDT 24
Finished Aug 02 08:03:37 PM PDT 24
Peak memory 576004 kb
Host smart-bb861abf-9b86-4612-ac5a-10db395e221a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494754744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random.494754744
Directory /workspace/54.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_random_large_delays.3197678904
Short name T665
Test name
Test status
Simulation time 85821621861 ps
CPU time 1010.67 seconds
Started Aug 02 08:02:21 PM PDT 24
Finished Aug 02 08:19:12 PM PDT 24
Peak memory 575992 kb
Host smart-2043321b-4b16-4272-b6af-518aea6da946
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197678904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_large_delays.3197678904
Directory /workspace/54.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.2777226472
Short name T1710
Test name
Test status
Simulation time 64180364516 ps
CPU time 1063.52 seconds
Started Aug 02 08:02:18 PM PDT 24
Finished Aug 02 08:20:02 PM PDT 24
Peak memory 575968 kb
Host smart-99ff9f4c-5ba3-4b27-a44c-7fe61561c40b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777226472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_slow_rsp.2777226472
Directory /workspace/54.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_random_zero_delays.518604780
Short name T2532
Test name
Test status
Simulation time 140461441 ps
CPU time 13.03 seconds
Started Aug 02 08:02:20 PM PDT 24
Finished Aug 02 08:02:33 PM PDT 24
Peak memory 575912 kb
Host smart-ccdc7477-bfbe-45c5-95dd-52538f4b9504
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518604780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_zero_dela
ys.518604780
Directory /workspace/54.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_same_source.4256868011
Short name T508
Test name
Test status
Simulation time 2521303593 ps
CPU time 72.17 seconds
Started Aug 02 08:02:42 PM PDT 24
Finished Aug 02 08:03:55 PM PDT 24
Peak memory 575904 kb
Host smart-f105d83e-516e-4454-8261-c5f86b598256
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256868011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_same_source.4256868011
Directory /workspace/54.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_smoke.1967323806
Short name T2599
Test name
Test status
Simulation time 144452636 ps
CPU time 7.46 seconds
Started Aug 02 08:02:20 PM PDT 24
Finished Aug 02 08:02:27 PM PDT 24
Peak memory 573840 kb
Host smart-7f0ec317-bc89-47db-bcf3-6b5f342d03a3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967323806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke.1967323806
Directory /workspace/54.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_smoke_large_delays.3190208155
Short name T1580
Test name
Test status
Simulation time 7633128782 ps
CPU time 77.25 seconds
Started Aug 02 08:02:18 PM PDT 24
Finished Aug 02 08:03:35 PM PDT 24
Peak memory 574016 kb
Host smart-254f3279-f4fa-4a38-b3d3-a5e4ecbd2369
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190208155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_large_delays.3190208155
Directory /workspace/54.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.182285570
Short name T2093
Test name
Test status
Simulation time 4591861815 ps
CPU time 74.61 seconds
Started Aug 02 08:02:19 PM PDT 24
Finished Aug 02 08:03:34 PM PDT 24
Peak memory 574696 kb
Host smart-54e2795d-83fe-46e5-aac9-ad3882b018a5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182285570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_slow_rsp.182285570
Directory /workspace/54.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_smoke_zero_delays.2458499165
Short name T583
Test name
Test status
Simulation time 51951100 ps
CPU time 6.32 seconds
Started Aug 02 08:02:17 PM PDT 24
Finished Aug 02 08:02:23 PM PDT 24
Peak memory 573888 kb
Host smart-d63ddc62-0377-49bb-bae7-79f7d9b10780
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458499165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_zero_delay
s.2458499165
Directory /workspace/54.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_stress_all.536416310
Short name T2265
Test name
Test status
Simulation time 5121656072 ps
CPU time 403.1 seconds
Started Aug 02 08:02:35 PM PDT 24
Finished Aug 02 08:09:18 PM PDT 24
Peak memory 576108 kb
Host smart-9f8e6cb1-ac3d-4337-90ae-3c3a08245559
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536416310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all.536416310
Directory /workspace/54.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.143006648
Short name T2352
Test name
Test status
Simulation time 4727700609 ps
CPU time 133.73 seconds
Started Aug 02 08:02:34 PM PDT 24
Finished Aug 02 08:04:48 PM PDT 24
Peak memory 576116 kb
Host smart-4df3843e-037d-4686-bc4f-4fa4d49ba9ce
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143006648 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_error.143006648
Directory /workspace/54.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.3910457962
Short name T653
Test name
Test status
Simulation time 691159567 ps
CPU time 296.77 seconds
Started Aug 02 08:02:35 PM PDT 24
Finished Aug 02 08:07:32 PM PDT 24
Peak memory 575932 kb
Host smart-f8ef987e-057f-49d6-a222-8e3c747fc654
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910457962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all
_with_rand_reset.3910457962
Directory /workspace/54.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.4172666443
Short name T1919
Test name
Test status
Simulation time 125180371 ps
CPU time 53.72 seconds
Started Aug 02 08:02:34 PM PDT 24
Finished Aug 02 08:03:28 PM PDT 24
Peak memory 576772 kb
Host smart-0ed2c097-d79d-4a5b-a476-d544f2bc4b81
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172666443 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_al
l_with_reset_error.4172666443
Directory /workspace/54.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_unmapped_addr.1886497444
Short name T2419
Test name
Test status
Simulation time 1273835104 ps
CPU time 54.86 seconds
Started Aug 02 08:02:34 PM PDT 24
Finished Aug 02 08:03:29 PM PDT 24
Peak memory 575932 kb
Host smart-51dd4758-8dac-40fa-9acf-b8c9e92643fd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886497444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_unmapped_addr.1886497444
Directory /workspace/54.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_access_same_device.1258777550
Short name T2384
Test name
Test status
Simulation time 2852180412 ps
CPU time 106.5 seconds
Started Aug 02 08:02:32 PM PDT 24
Finished Aug 02 08:04:18 PM PDT 24
Peak memory 576092 kb
Host smart-94808831-014a-4d2b-bd9f-4244cb7be1f4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258777550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device
.1258777550
Directory /workspace/55.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.1587116815
Short name T2660
Test name
Test status
Simulation time 29321524681 ps
CPU time 458.76 seconds
Started Aug 02 08:02:35 PM PDT 24
Finished Aug 02 08:10:14 PM PDT 24
Peak memory 575896 kb
Host smart-e10ef0e8-5dd6-4b94-b88c-5f3633d44d34
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587116815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_
device_slow_rsp.1587116815
Directory /workspace/55.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.3206223087
Short name T1723
Test name
Test status
Simulation time 120246329 ps
CPU time 14.75 seconds
Started Aug 02 08:02:35 PM PDT 24
Finished Aug 02 08:02:50 PM PDT 24
Peak memory 575956 kb
Host smart-eef26663-d740-45e2-bc0e-34dcc42ede67
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206223087 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_and_unmapped_add
r.3206223087
Directory /workspace/55.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_error_random.576214284
Short name T2318
Test name
Test status
Simulation time 77229409 ps
CPU time 6.01 seconds
Started Aug 02 08:02:35 PM PDT 24
Finished Aug 02 08:02:41 PM PDT 24
Peak memory 574424 kb
Host smart-d2424ada-4168-422a-aab3-4960aeb8d4d7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576214284 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_random.576214284
Directory /workspace/55.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_random.1388697438
Short name T2884
Test name
Test status
Simulation time 2331946391 ps
CPU time 83.72 seconds
Started Aug 02 08:02:36 PM PDT 24
Finished Aug 02 08:03:59 PM PDT 24
Peak memory 575880 kb
Host smart-234dd348-a10c-4b35-ab3d-8714a49f613a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388697438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random.1388697438
Directory /workspace/55.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_random_large_delays.2134021295
Short name T2916
Test name
Test status
Simulation time 26823728366 ps
CPU time 279.05 seconds
Started Aug 02 08:02:36 PM PDT 24
Finished Aug 02 08:07:15 PM PDT 24
Peak memory 576720 kb
Host smart-4b32427f-c450-4c13-aa18-cc408376aef3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134021295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_large_delays.2134021295
Directory /workspace/55.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_random_slow_rsp.1115834428
Short name T1872
Test name
Test status
Simulation time 10302357716 ps
CPU time 182.62 seconds
Started Aug 02 08:02:33 PM PDT 24
Finished Aug 02 08:05:36 PM PDT 24
Peak memory 575968 kb
Host smart-f5f37223-9490-45cf-a2f4-145dc7d1b087
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115834428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_slow_rsp.1115834428
Directory /workspace/55.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.1043686775
Short name T2272
Test name
Test status
Simulation time 492062163 ps
CPU time 37.93 seconds
Started Aug 02 08:02:33 PM PDT 24
Finished Aug 02 08:03:11 PM PDT 24
Peak memory 575816 kb
Host smart-9aff9b69-b2c6-45d5-95c0-122f8d720bbb
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043686775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_zero_del
ays.1043686775
Directory /workspace/55.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_same_source.1194603491
Short name T642
Test name
Test status
Simulation time 641853047 ps
CPU time 22.06 seconds
Started Aug 02 08:02:37 PM PDT 24
Finished Aug 02 08:02:59 PM PDT 24
Peak memory 575756 kb
Host smart-318cf4c0-1897-4535-bb12-18b340240741
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194603491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_same_source.1194603491
Directory /workspace/55.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_smoke.4067673623
Short name T2792
Test name
Test status
Simulation time 275488833 ps
CPU time 11.49 seconds
Started Aug 02 08:02:35 PM PDT 24
Finished Aug 02 08:02:47 PM PDT 24
Peak memory 574532 kb
Host smart-ca7d8872-0904-45c2-9ba5-d0a3ff0304c5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067673623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke.4067673623
Directory /workspace/55.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_smoke_large_delays.1679192812
Short name T1414
Test name
Test status
Simulation time 7693774441 ps
CPU time 76.19 seconds
Started Aug 02 08:02:35 PM PDT 24
Finished Aug 02 08:03:51 PM PDT 24
Peak memory 574588 kb
Host smart-955f12e2-54b7-496b-9585-22b295760254
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679192812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_large_delays.1679192812
Directory /workspace/55.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.1092210606
Short name T2755
Test name
Test status
Simulation time 4813485055 ps
CPU time 79.24 seconds
Started Aug 02 08:02:36 PM PDT 24
Finished Aug 02 08:03:56 PM PDT 24
Peak memory 573896 kb
Host smart-9bff41da-4e44-4a72-9c24-46d68a646ae4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092210606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_slow_rsp.1092210606
Directory /workspace/55.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_smoke_zero_delays.2469858503
Short name T1633
Test name
Test status
Simulation time 40013380 ps
CPU time 5.92 seconds
Started Aug 02 08:02:36 PM PDT 24
Finished Aug 02 08:02:42 PM PDT 24
Peak memory 574472 kb
Host smart-8c3cd4c3-7347-4e72-952c-b85c05678bce
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469858503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_zero_delay
s.2469858503
Directory /workspace/55.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_stress_all.2432367202
Short name T1630
Test name
Test status
Simulation time 1664575611 ps
CPU time 121.05 seconds
Started Aug 02 08:02:35 PM PDT 24
Finished Aug 02 08:04:36 PM PDT 24
Peak memory 576324 kb
Host smart-507165d1-98b7-40cd-bf4d-c67ea9814d4a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432367202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all.2432367202
Directory /workspace/55.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.3542962856
Short name T2129
Test name
Test status
Simulation time 202082747 ps
CPU time 8.57 seconds
Started Aug 02 08:02:36 PM PDT 24
Finished Aug 02 08:02:45 PM PDT 24
Peak memory 573748 kb
Host smart-200c2b5b-eeac-4cf5-8ac9-63ad23429003
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542962856 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_error.3542962856
Directory /workspace/55.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.2332076199
Short name T2192
Test name
Test status
Simulation time 309871241 ps
CPU time 109.73 seconds
Started Aug 02 08:02:36 PM PDT 24
Finished Aug 02 08:04:25 PM PDT 24
Peak memory 576676 kb
Host smart-bc35eaf3-2708-4c55-8414-52677fd919a3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332076199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all
_with_rand_reset.2332076199
Directory /workspace/55.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.2836957280
Short name T2414
Test name
Test status
Simulation time 3457384722 ps
CPU time 412.15 seconds
Started Aug 02 08:02:34 PM PDT 24
Finished Aug 02 08:09:26 PM PDT 24
Peak memory 576788 kb
Host smart-33ac6473-e2d3-4984-99ee-2f1fce5bb250
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836957280 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_al
l_with_reset_error.2836957280
Directory /workspace/55.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_unmapped_addr.2323005579
Short name T2406
Test name
Test status
Simulation time 293989009 ps
CPU time 13.87 seconds
Started Aug 02 08:02:43 PM PDT 24
Finished Aug 02 08:02:57 PM PDT 24
Peak memory 575932 kb
Host smart-dd206d3c-bffc-493d-86f2-5bb05e62a821
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323005579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_unmapped_addr.2323005579
Directory /workspace/55.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_access_same_device.3810578770
Short name T2894
Test name
Test status
Simulation time 654618398 ps
CPU time 49.33 seconds
Started Aug 02 08:02:45 PM PDT 24
Finished Aug 02 08:03:34 PM PDT 24
Peak memory 575764 kb
Host smart-33374480-881c-47d6-a00f-a090aebec844
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810578770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device
.3810578770
Directory /workspace/56.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.2958483621
Short name T2663
Test name
Test status
Simulation time 45436665544 ps
CPU time 775.23 seconds
Started Aug 02 08:02:45 PM PDT 24
Finished Aug 02 08:15:41 PM PDT 24
Peak memory 575928 kb
Host smart-eea43613-6965-454a-ab38-ef0d63562499
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958483621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_
device_slow_rsp.2958483621
Directory /workspace/56.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.2103161682
Short name T2804
Test name
Test status
Simulation time 340190024 ps
CPU time 15.25 seconds
Started Aug 02 08:02:44 PM PDT 24
Finished Aug 02 08:02:59 PM PDT 24
Peak memory 575728 kb
Host smart-ad815fdb-d803-40bf-9c00-d020cb4fd7a2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103161682 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_and_unmapped_add
r.2103161682
Directory /workspace/56.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_error_random.1660856190
Short name T2257
Test name
Test status
Simulation time 1095575847 ps
CPU time 36.14 seconds
Started Aug 02 08:02:45 PM PDT 24
Finished Aug 02 08:03:22 PM PDT 24
Peak memory 575944 kb
Host smart-f68ec248-14a1-4dcc-a252-bf0cac32d6f3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660856190 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_random.1660856190
Directory /workspace/56.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_random.3490419219
Short name T2100
Test name
Test status
Simulation time 217456290 ps
CPU time 21.66 seconds
Started Aug 02 08:02:34 PM PDT 24
Finished Aug 02 08:02:55 PM PDT 24
Peak memory 575756 kb
Host smart-815a6671-344e-4652-8943-530a9df4289b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490419219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random.3490419219
Directory /workspace/56.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.2504730949
Short name T2774
Test name
Test status
Simulation time 109518461422 ps
CPU time 1129.35 seconds
Started Aug 02 08:02:43 PM PDT 24
Finished Aug 02 08:21:33 PM PDT 24
Peak memory 576036 kb
Host smart-53e8d697-a93b-4dc2-83d7-bb1b6bd6831d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504730949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_large_delays.2504730949
Directory /workspace/56.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_random_slow_rsp.3793826867
Short name T469
Test name
Test status
Simulation time 51527804770 ps
CPU time 954.26 seconds
Started Aug 02 08:02:45 PM PDT 24
Finished Aug 02 08:18:39 PM PDT 24
Peak memory 576000 kb
Host smart-43a05013-5ad3-4bdf-abcb-d93deb859da8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793826867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_slow_rsp.3793826867
Directory /workspace/56.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_random_zero_delays.4086882579
Short name T626
Test name
Test status
Simulation time 229221217 ps
CPU time 20.02 seconds
Started Aug 02 08:02:35 PM PDT 24
Finished Aug 02 08:02:55 PM PDT 24
Peak memory 575776 kb
Host smart-30281cd6-b76d-4a45-b027-700c4b7ee33b
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086882579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_zero_del
ays.4086882579
Directory /workspace/56.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_same_source.297372545
Short name T1728
Test name
Test status
Simulation time 599108721 ps
CPU time 19.1 seconds
Started Aug 02 08:02:46 PM PDT 24
Finished Aug 02 08:03:05 PM PDT 24
Peak memory 575796 kb
Host smart-318fb541-9d4b-4275-9cba-69d5f95bfdb7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297372545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_same_source.297372545
Directory /workspace/56.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_smoke.2922043060
Short name T2601
Test name
Test status
Simulation time 230317811 ps
CPU time 8.8 seconds
Started Aug 02 08:02:35 PM PDT 24
Finished Aug 02 08:02:44 PM PDT 24
Peak memory 574484 kb
Host smart-d47f5696-f093-496e-8261-5c92ec08247e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922043060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke.2922043060
Directory /workspace/56.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_smoke_large_delays.2226732939
Short name T2099
Test name
Test status
Simulation time 11558930957 ps
CPU time 118.38 seconds
Started Aug 02 08:02:32 PM PDT 24
Finished Aug 02 08:04:30 PM PDT 24
Peak memory 574688 kb
Host smart-564a96e9-92af-412d-bd03-3ee2ec8a41e8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226732939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_large_delays.2226732939
Directory /workspace/56.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.850951311
Short name T2805
Test name
Test status
Simulation time 5792319106 ps
CPU time 90.75 seconds
Started Aug 02 08:02:34 PM PDT 24
Finished Aug 02 08:04:05 PM PDT 24
Peak memory 574652 kb
Host smart-e9d5e5cd-13a0-4788-976d-a943b1e80def
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850951311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_slow_rsp.850951311
Directory /workspace/56.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_smoke_zero_delays.4036287179
Short name T2176
Test name
Test status
Simulation time 45592421 ps
CPU time 6.67 seconds
Started Aug 02 08:02:37 PM PDT 24
Finished Aug 02 08:02:43 PM PDT 24
Peak memory 574516 kb
Host smart-965a6b88-45e4-4d31-9c51-1f552369771e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036287179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_zero_delay
s.4036287179
Directory /workspace/56.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_stress_all.3524149063
Short name T621
Test name
Test status
Simulation time 3720539679 ps
CPU time 146.19 seconds
Started Aug 02 08:02:44 PM PDT 24
Finished Aug 02 08:05:10 PM PDT 24
Peak memory 576084 kb
Host smart-0a9480ae-750f-4765-8393-24ddd7def227
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524149063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all.3524149063
Directory /workspace/56.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.1975635290
Short name T2557
Test name
Test status
Simulation time 1986318304 ps
CPU time 173.79 seconds
Started Aug 02 08:02:46 PM PDT 24
Finished Aug 02 08:05:40 PM PDT 24
Peak memory 576580 kb
Host smart-9d21a89d-f5b2-4e84-97ef-84a15bc35083
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975635290 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_error.1975635290
Directory /workspace/56.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.3641236696
Short name T494
Test name
Test status
Simulation time 5630768150 ps
CPU time 492.68 seconds
Started Aug 02 08:02:45 PM PDT 24
Finished Aug 02 08:10:58 PM PDT 24
Peak memory 576100 kb
Host smart-94198827-1ddb-4879-849a-3613d1e01741
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641236696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all
_with_rand_reset.3641236696
Directory /workspace/56.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.3708868941
Short name T2459
Test name
Test status
Simulation time 244143254 ps
CPU time 93 seconds
Started Aug 02 08:02:47 PM PDT 24
Finished Aug 02 08:04:20 PM PDT 24
Peak memory 576720 kb
Host smart-9b76fe0e-a473-44e9-a4d6-9ee3223f9443
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708868941 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_al
l_with_reset_error.3708868941
Directory /workspace/56.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_unmapped_addr.4087794392
Short name T2372
Test name
Test status
Simulation time 1101712323 ps
CPU time 44.25 seconds
Started Aug 02 08:02:44 PM PDT 24
Finished Aug 02 08:03:28 PM PDT 24
Peak memory 575820 kb
Host smart-8d397784-42da-4905-a806-e821e1e423ef
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087794392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_unmapped_addr.4087794392
Directory /workspace/56.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_access_same_device.1850220336
Short name T475
Test name
Test status
Simulation time 2693116272 ps
CPU time 108.43 seconds
Started Aug 02 08:02:50 PM PDT 24
Finished Aug 02 08:04:38 PM PDT 24
Peak memory 575968 kb
Host smart-ff2f64a7-368d-477f-950c-d7b2c957e80b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850220336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device
.1850220336
Directory /workspace/57.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.880075725
Short name T2160
Test name
Test status
Simulation time 97718978844 ps
CPU time 1692.08 seconds
Started Aug 02 08:02:52 PM PDT 24
Finished Aug 02 08:31:04 PM PDT 24
Peak memory 576084 kb
Host smart-2687611d-f8e3-4e16-b484-419f8c31dbeb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880075725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_d
evice_slow_rsp.880075725
Directory /workspace/57.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.77403196
Short name T1467
Test name
Test status
Simulation time 110530441 ps
CPU time 13.63 seconds
Started Aug 02 08:02:47 PM PDT 24
Finished Aug 02 08:03:00 PM PDT 24
Peak memory 575960 kb
Host smart-6e9bc42d-665b-4c79-a7aa-aeb046e2d833
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77403196 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_and_unmapped_addr.77403196
Directory /workspace/57.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_error_random.795999714
Short name T1620
Test name
Test status
Simulation time 2470096410 ps
CPU time 82.39 seconds
Started Aug 02 08:02:49 PM PDT 24
Finished Aug 02 08:04:12 PM PDT 24
Peak memory 576056 kb
Host smart-3406f27f-c59d-405c-bda6-36ef260b724d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795999714 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_random.795999714
Directory /workspace/57.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_random.1013225837
Short name T2045
Test name
Test status
Simulation time 608514997 ps
CPU time 57.94 seconds
Started Aug 02 08:02:45 PM PDT 24
Finished Aug 02 08:03:43 PM PDT 24
Peak memory 575876 kb
Host smart-7fe382ef-707b-44f2-aee6-342bd0dbccd9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013225837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random.1013225837
Directory /workspace/57.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_random_large_delays.2345067483
Short name T2935
Test name
Test status
Simulation time 10508333448 ps
CPU time 102.24 seconds
Started Aug 02 08:02:47 PM PDT 24
Finished Aug 02 08:04:29 PM PDT 24
Peak memory 575856 kb
Host smart-f3908bae-e51a-4f9d-832e-f5202b097d9a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345067483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_large_delays.2345067483
Directory /workspace/57.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_random_slow_rsp.2491876256
Short name T1853
Test name
Test status
Simulation time 27221156581 ps
CPU time 469.25 seconds
Started Aug 02 08:02:48 PM PDT 24
Finished Aug 02 08:10:37 PM PDT 24
Peak memory 576016 kb
Host smart-934b5f67-b4a9-4e9c-960f-2f6fba740a68
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491876256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_slow_rsp.2491876256
Directory /workspace/57.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_random_zero_delays.4167127422
Short name T1747
Test name
Test status
Simulation time 260595304 ps
CPU time 26.46 seconds
Started Aug 02 08:02:48 PM PDT 24
Finished Aug 02 08:03:14 PM PDT 24
Peak memory 575840 kb
Host smart-619e82ac-31e7-4b76-abc9-39c34c54ca30
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167127422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_zero_del
ays.4167127422
Directory /workspace/57.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_same_source.1511459423
Short name T1957
Test name
Test status
Simulation time 543285624 ps
CPU time 34.6 seconds
Started Aug 02 08:02:46 PM PDT 24
Finished Aug 02 08:03:20 PM PDT 24
Peak memory 575904 kb
Host smart-2ab01318-1d72-48ac-9008-1527031dbc50
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511459423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_same_source.1511459423
Directory /workspace/57.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_smoke.1656203814
Short name T1560
Test name
Test status
Simulation time 216725336 ps
CPU time 9.29 seconds
Started Aug 02 08:02:45 PM PDT 24
Finished Aug 02 08:02:54 PM PDT 24
Peak memory 573836 kb
Host smart-a40db35f-7602-42a9-9266-ea184f84bce5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656203814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke.1656203814
Directory /workspace/57.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_smoke_large_delays.2536733632
Short name T2249
Test name
Test status
Simulation time 8264217177 ps
CPU time 83.14 seconds
Started Aug 02 08:02:48 PM PDT 24
Finished Aug 02 08:04:11 PM PDT 24
Peak memory 573928 kb
Host smart-93d9fee8-6b25-46f4-a436-782e821ed2fa
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536733632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_large_delays.2536733632
Directory /workspace/57.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.1447399530
Short name T1648
Test name
Test status
Simulation time 5719254368 ps
CPU time 95.51 seconds
Started Aug 02 08:02:50 PM PDT 24
Finished Aug 02 08:04:25 PM PDT 24
Peak memory 573964 kb
Host smart-9c6e3c80-cd52-4a93-9d44-0446c995f9a8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447399530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_slow_rsp.1447399530
Directory /workspace/57.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_smoke_zero_delays.1421209865
Short name T2021
Test name
Test status
Simulation time 46763286 ps
CPU time 6.31 seconds
Started Aug 02 08:02:45 PM PDT 24
Finished Aug 02 08:02:52 PM PDT 24
Peak memory 573844 kb
Host smart-6f8db0a1-b97b-48db-be0a-871899148b59
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421209865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_zero_delay
s.1421209865
Directory /workspace/57.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_stress_all.2629354723
Short name T2824
Test name
Test status
Simulation time 6148119552 ps
CPU time 200.55 seconds
Started Aug 02 08:02:44 PM PDT 24
Finished Aug 02 08:06:05 PM PDT 24
Peak memory 576000 kb
Host smart-c56e6b59-c258-463a-9d31-bdc2cd25ab51
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629354723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all.2629354723
Directory /workspace/57.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.2726698233
Short name T2905
Test name
Test status
Simulation time 11628248721 ps
CPU time 461.01 seconds
Started Aug 02 08:02:50 PM PDT 24
Finished Aug 02 08:10:31 PM PDT 24
Peak memory 576804 kb
Host smart-f4f609db-9b8c-4154-9322-9078a4009e0f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726698233 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_error.2726698233
Directory /workspace/57.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.2609338567
Short name T2241
Test name
Test status
Simulation time 3598821010 ps
CPU time 331.91 seconds
Started Aug 02 08:02:49 PM PDT 24
Finished Aug 02 08:08:21 PM PDT 24
Peak memory 576112 kb
Host smart-cd1d8834-a7fe-436c-b13a-f31ed32ea4bb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609338567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all
_with_rand_reset.2609338567
Directory /workspace/57.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.1065618437
Short name T890
Test name
Test status
Simulation time 927750072 ps
CPU time 252.37 seconds
Started Aug 02 08:02:50 PM PDT 24
Finished Aug 02 08:07:02 PM PDT 24
Peak memory 576748 kb
Host smart-4880b8f4-77ec-425c-a3cf-60717df0eca2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065618437 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_al
l_with_reset_error.1065618437
Directory /workspace/57.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.3228194870
Short name T659
Test name
Test status
Simulation time 861621755 ps
CPU time 35.89 seconds
Started Aug 02 08:02:50 PM PDT 24
Finished Aug 02 08:03:26 PM PDT 24
Peak memory 576000 kb
Host smart-cd078aad-15b2-417b-b2fc-5eee4465c211
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228194870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_unmapped_addr.3228194870
Directory /workspace/57.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_access_same_device.538754076
Short name T2357
Test name
Test status
Simulation time 245448210 ps
CPU time 26.34 seconds
Started Aug 02 08:02:55 PM PDT 24
Finished Aug 02 08:03:22 PM PDT 24
Peak memory 575856 kb
Host smart-90cdc4a7-ef6c-4491-9d10-05da74115943
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538754076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device.
538754076
Directory /workspace/58.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.803930400
Short name T1973
Test name
Test status
Simulation time 281298519 ps
CPU time 26.96 seconds
Started Aug 02 08:02:56 PM PDT 24
Finished Aug 02 08:03:23 PM PDT 24
Peak memory 575760 kb
Host smart-ff6a3eb8-9da3-4d93-b878-e7e5a563bcde
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803930400 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_and_unmapped_addr
.803930400
Directory /workspace/58.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_error_random.1473731888
Short name T1966
Test name
Test status
Simulation time 211745986 ps
CPU time 18.39 seconds
Started Aug 02 08:02:55 PM PDT 24
Finished Aug 02 08:03:13 PM PDT 24
Peak memory 575944 kb
Host smart-d4eff7fb-5d9b-41e6-ad9a-5d06e2c7fdf6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473731888 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_random.1473731888
Directory /workspace/58.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_random_large_delays.1449907631
Short name T527
Test name
Test status
Simulation time 103776973688 ps
CPU time 1122.82 seconds
Started Aug 02 08:02:54 PM PDT 24
Finished Aug 02 08:21:37 PM PDT 24
Peak memory 575896 kb
Host smart-20348ab9-4d7c-4591-8a9e-418e1edc876f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449907631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_large_delays.1449907631
Directory /workspace/58.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.3285555545
Short name T2841
Test name
Test status
Simulation time 24801901755 ps
CPU time 437.05 seconds
Started Aug 02 08:03:01 PM PDT 24
Finished Aug 02 08:10:18 PM PDT 24
Peak memory 576736 kb
Host smart-dd342211-81db-482e-8efc-41672891aba2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285555545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_slow_rsp.3285555545
Directory /workspace/58.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_random_zero_delays.3539252541
Short name T1732
Test name
Test status
Simulation time 521181523 ps
CPU time 49.14 seconds
Started Aug 02 08:02:56 PM PDT 24
Finished Aug 02 08:03:45 PM PDT 24
Peak memory 575816 kb
Host smart-0ff11ecc-0654-453a-92f2-9a4f6589f5c3
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539252541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_zero_del
ays.3539252541
Directory /workspace/58.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_same_source.384536931
Short name T562
Test name
Test status
Simulation time 565216895 ps
CPU time 36.52 seconds
Started Aug 02 08:02:56 PM PDT 24
Finished Aug 02 08:03:32 PM PDT 24
Peak memory 575800 kb
Host smart-b5a040a2-c8c2-43cf-8cf1-183f525f78f5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384536931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_same_source.384536931
Directory /workspace/58.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_smoke.2210029745
Short name T2862
Test name
Test status
Simulation time 212404612 ps
CPU time 9.04 seconds
Started Aug 02 08:02:53 PM PDT 24
Finished Aug 02 08:03:02 PM PDT 24
Peak memory 574540 kb
Host smart-8b95a593-0380-46d7-8780-b07f6e7c4788
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210029745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke.2210029745
Directory /workspace/58.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.201942863
Short name T1567
Test name
Test status
Simulation time 5503931430 ps
CPU time 58.98 seconds
Started Aug 02 08:02:51 PM PDT 24
Finished Aug 02 08:03:50 PM PDT 24
Peak memory 574584 kb
Host smart-e7285811-375c-4959-a46e-9b29b8fc6285
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201942863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_large_delays.201942863
Directory /workspace/58.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.2790672085
Short name T2488
Test name
Test status
Simulation time 4290242048 ps
CPU time 72.55 seconds
Started Aug 02 08:02:53 PM PDT 24
Finished Aug 02 08:04:06 PM PDT 24
Peak memory 573876 kb
Host smart-54e1388e-9050-48b8-b9eb-3ead717bbf52
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790672085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_slow_rsp.2790672085
Directory /workspace/58.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.2420719566
Short name T2869
Test name
Test status
Simulation time 41991720 ps
CPU time 6.25 seconds
Started Aug 02 08:02:49 PM PDT 24
Finished Aug 02 08:02:55 PM PDT 24
Peak memory 573916 kb
Host smart-4c0c1e51-e7b2-496a-a57f-cbade9419953
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420719566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_zero_delay
s.2420719566
Directory /workspace/58.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_stress_all.3678180163
Short name T2754
Test name
Test status
Simulation time 2570067688 ps
CPU time 215.21 seconds
Started Aug 02 08:02:54 PM PDT 24
Finished Aug 02 08:06:29 PM PDT 24
Peak memory 576796 kb
Host smart-fed285e4-4643-4972-8c51-65dacec3b11b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678180163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all.3678180163
Directory /workspace/58.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.2181538123
Short name T1991
Test name
Test status
Simulation time 3665427733 ps
CPU time 132.08 seconds
Started Aug 02 08:03:01 PM PDT 24
Finished Aug 02 08:05:14 PM PDT 24
Peak memory 576088 kb
Host smart-d1180d56-81fd-495c-a750-f6a7586e3e89
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181538123 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_error.2181538123
Directory /workspace/58.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.2230457542
Short name T2768
Test name
Test status
Simulation time 197676285 ps
CPU time 44.03 seconds
Started Aug 02 08:03:01 PM PDT 24
Finished Aug 02 08:03:45 PM PDT 24
Peak memory 575892 kb
Host smart-b60e5474-e9eb-43e4-86f6-838cfbc498fc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230457542 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_al
l_with_reset_error.2230457542
Directory /workspace/58.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_unmapped_addr.3534436168
Short name T2456
Test name
Test status
Simulation time 1250165454 ps
CPU time 48.63 seconds
Started Aug 02 08:02:56 PM PDT 24
Finished Aug 02 08:03:45 PM PDT 24
Peak memory 575844 kb
Host smart-8b3a5541-6372-4b29-a7cf-358233831ed3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534436168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_unmapped_addr.3534436168
Directory /workspace/58.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_access_same_device.3982709641
Short name T867
Test name
Test status
Simulation time 1303546977 ps
CPU time 58.56 seconds
Started Aug 02 08:03:09 PM PDT 24
Finished Aug 02 08:04:07 PM PDT 24
Peak memory 575988 kb
Host smart-87f09e92-9be6-4970-85e0-140fa025a040
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982709641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device
.3982709641
Directory /workspace/59.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.3444761687
Short name T521
Test name
Test status
Simulation time 57963191825 ps
CPU time 1088.94 seconds
Started Aug 02 08:03:10 PM PDT 24
Finished Aug 02 08:21:19 PM PDT 24
Peak memory 576024 kb
Host smart-106f23b6-c836-4d32-9043-0131e3c2933e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444761687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_
device_slow_rsp.3444761687
Directory /workspace/59.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.527819920
Short name T2801
Test name
Test status
Simulation time 529627016 ps
CPU time 24.91 seconds
Started Aug 02 08:03:18 PM PDT 24
Finished Aug 02 08:03:43 PM PDT 24
Peak memory 575904 kb
Host smart-25c36aa2-baa7-40d0-8d5a-5f3d07687bae
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527819920 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_and_unmapped_addr
.527819920
Directory /workspace/59.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_error_random.2312819396
Short name T2431
Test name
Test status
Simulation time 172453588 ps
CPU time 14.84 seconds
Started Aug 02 08:03:10 PM PDT 24
Finished Aug 02 08:03:25 PM PDT 24
Peak memory 576032 kb
Host smart-b9d78319-c41d-41ec-918e-e70b1517280a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312819396 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_random.2312819396
Directory /workspace/59.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_random.2686667516
Short name T2531
Test name
Test status
Simulation time 451065031 ps
CPU time 19.29 seconds
Started Aug 02 08:03:10 PM PDT 24
Finished Aug 02 08:03:30 PM PDT 24
Peak memory 575780 kb
Host smart-c5364c0a-4da7-40b0-a88f-2e15e157163b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686667516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random.2686667516
Directory /workspace/59.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_random_large_delays.1857157954
Short name T1726
Test name
Test status
Simulation time 36947418825 ps
CPU time 389.89 seconds
Started Aug 02 08:03:09 PM PDT 24
Finished Aug 02 08:09:39 PM PDT 24
Peak memory 575932 kb
Host smart-06c358c7-92cf-482e-8842-ac9581e3b523
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857157954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_large_delays.1857157954
Directory /workspace/59.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.699675000
Short name T2467
Test name
Test status
Simulation time 28801144428 ps
CPU time 470.59 seconds
Started Aug 02 08:03:08 PM PDT 24
Finished Aug 02 08:10:59 PM PDT 24
Peak memory 576024 kb
Host smart-b40894ab-e2db-473e-abda-10fd6acee182
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699675000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_slow_rsp.699675000
Directory /workspace/59.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_random_zero_delays.2049070140
Short name T525
Test name
Test status
Simulation time 378390743 ps
CPU time 34.81 seconds
Started Aug 02 08:03:09 PM PDT 24
Finished Aug 02 08:03:44 PM PDT 24
Peak memory 575836 kb
Host smart-f65852a5-a018-4d18-8630-61f8fe2c8b07
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049070140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_zero_del
ays.2049070140
Directory /workspace/59.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_same_source.3348989432
Short name T2608
Test name
Test status
Simulation time 291201257 ps
CPU time 11.21 seconds
Started Aug 02 08:03:11 PM PDT 24
Finished Aug 02 08:03:22 PM PDT 24
Peak memory 576016 kb
Host smart-53dc1bea-d172-4f8e-b382-3cb3853c861d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348989432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_same_source.3348989432
Directory /workspace/59.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_smoke.2579641929
Short name T2421
Test name
Test status
Simulation time 212368305 ps
CPU time 9.24 seconds
Started Aug 02 08:03:01 PM PDT 24
Finished Aug 02 08:03:10 PM PDT 24
Peak memory 573812 kb
Host smart-365411fc-fd6e-46df-a79a-84f75ae03401
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579641929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke.2579641929
Directory /workspace/59.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.4283125151
Short name T1662
Test name
Test status
Simulation time 9010617657 ps
CPU time 99.51 seconds
Started Aug 02 08:03:01 PM PDT 24
Finished Aug 02 08:04:41 PM PDT 24
Peak memory 574532 kb
Host smart-ae3b2c26-08e3-4f86-b3cb-efee614bd74e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283125151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_large_delays.4283125151
Directory /workspace/59.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.427885592
Short name T2465
Test name
Test status
Simulation time 6045324684 ps
CPU time 102.79 seconds
Started Aug 02 08:03:11 PM PDT 24
Finished Aug 02 08:04:54 PM PDT 24
Peak memory 574632 kb
Host smart-19838f9e-0976-4a61-a15c-5fef593c2c5e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427885592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_slow_rsp.427885592
Directory /workspace/59.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_smoke_zero_delays.1842980129
Short name T1688
Test name
Test status
Simulation time 48316402 ps
CPU time 6.34 seconds
Started Aug 02 08:02:53 PM PDT 24
Finished Aug 02 08:02:59 PM PDT 24
Peak memory 574608 kb
Host smart-d25a6887-64ee-4943-af9c-e22a1652c8b5
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842980129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_zero_delay
s.1842980129
Directory /workspace/59.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_stress_all.3921196505
Short name T2394
Test name
Test status
Simulation time 2966481583 ps
CPU time 233.93 seconds
Started Aug 02 08:03:10 PM PDT 24
Finished Aug 02 08:07:04 PM PDT 24
Peak memory 576772 kb
Host smart-21f34bdc-5562-468f-b6b7-391f2c97423f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921196505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all.3921196505
Directory /workspace/59.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.3556613497
Short name T2281
Test name
Test status
Simulation time 3783729419 ps
CPU time 142.98 seconds
Started Aug 02 08:03:09 PM PDT 24
Finished Aug 02 08:05:32 PM PDT 24
Peak memory 575800 kb
Host smart-535200b1-6a85-4d69-8826-93b5f8b3acd5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556613497 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_error.3556613497
Directory /workspace/59.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.2559778522
Short name T2678
Test name
Test status
Simulation time 474257154 ps
CPU time 251.29 seconds
Started Aug 02 08:03:10 PM PDT 24
Finished Aug 02 08:07:21 PM PDT 24
Peak memory 575948 kb
Host smart-0c0fa4ad-c08f-4fb9-8e5a-d364f002ca84
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559778522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all
_with_rand_reset.2559778522
Directory /workspace/59.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.2266661570
Short name T1977
Test name
Test status
Simulation time 410157290 ps
CPU time 122.55 seconds
Started Aug 02 08:03:09 PM PDT 24
Finished Aug 02 08:05:12 PM PDT 24
Peak memory 575928 kb
Host smart-cf41d9c9-0176-4f4f-b66f-026d4ce214cb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266661570 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_al
l_with_reset_error.2266661570
Directory /workspace/59.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_unmapped_addr.2946073760
Short name T1861
Test name
Test status
Simulation time 1421456183 ps
CPU time 57.55 seconds
Started Aug 02 08:03:09 PM PDT 24
Finished Aug 02 08:04:07 PM PDT 24
Peak memory 575940 kb
Host smart-1e55436e-c02c-484c-8eba-76de081ccb36
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946073760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_unmapped_addr.2946073760
Directory /workspace/59.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.184128423
Short name T409
Test name
Test status
Simulation time 12719959416 ps
CPU time 897.3 seconds
Started Aug 02 07:52:59 PM PDT 24
Finished Aug 02 08:07:56 PM PDT 24
Peak memory 646816 kb
Host smart-7a6f2ad1-b54e-424c-8c3b-5da7f784e0f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184128423 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.chip_csr_mem_rw_with_rand_reset.184128423
Directory /workspace/6.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.chip_csr_rw.2241662042
Short name T1763
Test name
Test status
Simulation time 4974461240 ps
CPU time 583.58 seconds
Started Aug 02 07:53:00 PM PDT 24
Finished Aug 02 08:02:43 PM PDT 24
Peak memory 599020 kb
Host smart-a324c381-611a-414b-8ec0-48e19a5447fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241662042 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_csr_rw.2241662042
Directory /workspace/6.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.90607306
Short name T444
Test name
Test status
Simulation time 30665039486 ps
CPU time 4767.78 seconds
Started Aug 02 07:52:49 PM PDT 24
Finished Aug 02 09:12:17 PM PDT 24
Peak memory 593740 kb
Host smart-14d99d63-548d-4353-95fc-973c5868e9f8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90607306 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.chip_same_csr_outstanding.90607306
Directory /workspace/6.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.chip_tl_errors.3467051008
Short name T596
Test name
Test status
Simulation time 3184575742 ps
CPU time 151.36 seconds
Started Aug 02 07:52:35 PM PDT 24
Finished Aug 02 07:55:07 PM PDT 24
Peak memory 598780 kb
Host smart-87510f7e-a9f4-4de3-8547-573b532c168d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467051008 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_tl_errors.3467051008
Directory /workspace/6.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_access_same_device.31788563
Short name T846
Test name
Test status
Simulation time 1500022683 ps
CPU time 66.29 seconds
Started Aug 02 07:52:47 PM PDT 24
Finished Aug 02 07:53:53 PM PDT 24
Peak memory 575932 kb
Host smart-b67a6ea2-af9a-444b-9940-3b4162d78043
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31788563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.31788563
Directory /workspace/6.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.3432796671
Short name T2107
Test name
Test status
Simulation time 115734650279 ps
CPU time 1911.46 seconds
Started Aug 02 07:52:48 PM PDT 24
Finished Aug 02 08:24:40 PM PDT 24
Peak memory 575968 kb
Host smart-50b2d377-89f5-4278-b759-6731abbe9333
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432796671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_d
evice_slow_rsp.3432796671
Directory /workspace/6.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_error_random.1210991050
Short name T1606
Test name
Test status
Simulation time 63961770 ps
CPU time 7.7 seconds
Started Aug 02 07:52:47 PM PDT 24
Finished Aug 02 07:52:55 PM PDT 24
Peak memory 575896 kb
Host smart-8486cee2-1077-49a8-b51d-782ce115d7ad
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210991050 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.1210991050
Directory /workspace/6.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_random.2111413465
Short name T2244
Test name
Test status
Simulation time 1942496937 ps
CPU time 70.57 seconds
Started Aug 02 07:52:47 PM PDT 24
Finished Aug 02 07:53:57 PM PDT 24
Peak memory 575908 kb
Host smart-0fff81c4-4f03-415e-b064-e17626e578cf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111413465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random.2111413465
Directory /workspace/6.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_random_large_delays.3800603046
Short name T2576
Test name
Test status
Simulation time 52133804648 ps
CPU time 519.64 seconds
Started Aug 02 07:52:47 PM PDT 24
Finished Aug 02 08:01:27 PM PDT 24
Peak memory 575904 kb
Host smart-e9e83a96-8c4d-4d81-bdb2-ff96f92f5ad7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800603046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.3800603046
Directory /workspace/6.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_random_slow_rsp.3378987710
Short name T1802
Test name
Test status
Simulation time 57159363108 ps
CPU time 971.55 seconds
Started Aug 02 07:52:47 PM PDT 24
Finished Aug 02 08:08:59 PM PDT 24
Peak memory 575968 kb
Host smart-4347ac22-4b2b-4879-8268-5cbc7f1339cd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378987710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.3378987710
Directory /workspace/6.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_random_zero_delays.3094810941
Short name T2258
Test name
Test status
Simulation time 164505807 ps
CPU time 15.85 seconds
Started Aug 02 07:52:50 PM PDT 24
Finished Aug 02 07:53:06 PM PDT 24
Peak memory 575784 kb
Host smart-b04c9567-679e-41c2-b68c-2dfb99645674
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094810941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_dela
ys.3094810941
Directory /workspace/6.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_same_source.2631671371
Short name T2811
Test name
Test status
Simulation time 1523590424 ps
CPU time 43 seconds
Started Aug 02 07:52:49 PM PDT 24
Finished Aug 02 07:53:32 PM PDT 24
Peak memory 575740 kb
Host smart-8ba207d7-43c1-4d43-9037-dc3a136fa203
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631671371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.2631671371
Directory /workspace/6.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_smoke.2139741835
Short name T1647
Test name
Test status
Simulation time 179141561 ps
CPU time 8.07 seconds
Started Aug 02 07:52:47 PM PDT 24
Finished Aug 02 07:52:55 PM PDT 24
Peak memory 573824 kb
Host smart-97fde9f9-a152-41ab-a22b-94fc9dbe1acc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139741835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.2139741835
Directory /workspace/6.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_smoke_large_delays.3934967348
Short name T2855
Test name
Test status
Simulation time 9048086349 ps
CPU time 94.38 seconds
Started Aug 02 07:52:47 PM PDT 24
Finished Aug 02 07:54:22 PM PDT 24
Peak memory 573956 kb
Host smart-5ae04b02-50dc-42e1-9bc2-1a756848222d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934967348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.3934967348
Directory /workspace/6.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.3846752195
Short name T2574
Test name
Test status
Simulation time 4298223215 ps
CPU time 69.85 seconds
Started Aug 02 07:53:00 PM PDT 24
Finished Aug 02 07:54:10 PM PDT 24
Peak memory 574680 kb
Host smart-3990f3da-de5a-4fb9-8ee9-43f407eebd11
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846752195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.3846752195
Directory /workspace/6.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.2818193703
Short name T1658
Test name
Test status
Simulation time 51023072 ps
CPU time 6.03 seconds
Started Aug 02 07:52:57 PM PDT 24
Finished Aug 02 07:53:03 PM PDT 24
Peak memory 574576 kb
Host smart-e0adbf88-d0fc-4bef-84f2-08a6a8369bc7
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818193703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays
.2818193703
Directory /workspace/6.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_stress_all.4112312244
Short name T2461
Test name
Test status
Simulation time 2325545098 ps
CPU time 178.62 seconds
Started Aug 02 07:52:59 PM PDT 24
Finished Aug 02 07:55:58 PM PDT 24
Peak memory 576000 kb
Host smart-7da538fc-cd7c-4186-9ef6-772fbbe53117
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112312244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.4112312244
Directory /workspace/6.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_error.3335690222
Short name T2847
Test name
Test status
Simulation time 4742091412 ps
CPU time 334.16 seconds
Started Aug 02 07:52:59 PM PDT 24
Finished Aug 02 07:58:33 PM PDT 24
Peak memory 576748 kb
Host smart-20b541fa-b78b-4ff8-bbbf-ee4205ea5e31
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335690222 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.3335690222
Directory /workspace/6.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.1816467809
Short name T2053
Test name
Test status
Simulation time 82104069 ps
CPU time 39.75 seconds
Started Aug 02 07:53:05 PM PDT 24
Finished Aug 02 07:53:45 PM PDT 24
Peak memory 576676 kb
Host smart-f9487ee2-b068-475a-a35a-972178511b98
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816467809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_
with_rand_reset.1816467809
Directory /workspace/6.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.2963659664
Short name T2212
Test name
Test status
Simulation time 8248538567 ps
CPU time 671.13 seconds
Started Aug 02 07:52:57 PM PDT 24
Finished Aug 02 08:04:09 PM PDT 24
Peak memory 581868 kb
Host smart-fe645dad-8230-4ed3-938b-e664ac1d7da0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963659664 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all
_with_reset_error.2963659664
Directory /workspace/6.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_unmapped_addr.3778542349
Short name T2829
Test name
Test status
Simulation time 921207688 ps
CPU time 41.21 seconds
Started Aug 02 07:52:48 PM PDT 24
Finished Aug 02 07:53:29 PM PDT 24
Peak memory 575964 kb
Host smart-9d1ebd43-ae6b-4e45-b8a3-d561ca4d8976
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778542349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.3778542349
Directory /workspace/6.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_access_same_device.668486912
Short name T2786
Test name
Test status
Simulation time 2421839644 ps
CPU time 80.78 seconds
Started Aug 02 08:03:22 PM PDT 24
Finished Aug 02 08:04:43 PM PDT 24
Peak memory 575972 kb
Host smart-83011e71-85ce-427b-b3a9-b1b1aa9656a9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668486912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device.
668486912
Directory /workspace/60.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.2448313982
Short name T2613
Test name
Test status
Simulation time 30514183839 ps
CPU time 548.53 seconds
Started Aug 02 08:03:25 PM PDT 24
Finished Aug 02 08:12:34 PM PDT 24
Peak memory 575816 kb
Host smart-dcd625e1-7fd6-42ad-80ec-9790aef7483f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448313982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_
device_slow_rsp.2448313982
Directory /workspace/60.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.1812606747
Short name T2506
Test name
Test status
Simulation time 140595622 ps
CPU time 8.23 seconds
Started Aug 02 08:03:22 PM PDT 24
Finished Aug 02 08:03:31 PM PDT 24
Peak memory 574484 kb
Host smart-9e72dabb-b255-4025-947d-2d89211e16cf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812606747 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_and_unmapped_add
r.1812606747
Directory /workspace/60.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_error_random.3693176781
Short name T1720
Test name
Test status
Simulation time 343618987 ps
CPU time 26.81 seconds
Started Aug 02 08:03:21 PM PDT 24
Finished Aug 02 08:03:47 PM PDT 24
Peak memory 575872 kb
Host smart-982a3f87-9492-4610-8cdb-63f167681dc0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693176781 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_random.3693176781
Directory /workspace/60.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_random.312050786
Short name T1746
Test name
Test status
Simulation time 2082763110 ps
CPU time 75.03 seconds
Started Aug 02 08:03:10 PM PDT 24
Finished Aug 02 08:04:25 PM PDT 24
Peak memory 575752 kb
Host smart-ea530b6c-5082-4b40-ad86-8d9a646a9888
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312050786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random.312050786
Directory /workspace/60.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_random_large_delays.4137825287
Short name T2902
Test name
Test status
Simulation time 98037951600 ps
CPU time 1018.29 seconds
Started Aug 02 08:03:09 PM PDT 24
Finished Aug 02 08:20:08 PM PDT 24
Peak memory 575976 kb
Host smart-e4d970eb-5a73-4c18-ab72-ce91a24d264b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137825287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_large_delays.4137825287
Directory /workspace/60.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.1881317877
Short name T1721
Test name
Test status
Simulation time 34118726814 ps
CPU time 622.08 seconds
Started Aug 02 08:03:08 PM PDT 24
Finished Aug 02 08:13:31 PM PDT 24
Peak memory 575840 kb
Host smart-98e9d62c-1290-423b-99d3-f6097e53630d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881317877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_slow_rsp.1881317877
Directory /workspace/60.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_random_zero_delays.1388615553
Short name T1716
Test name
Test status
Simulation time 86471119 ps
CPU time 9.9 seconds
Started Aug 02 08:03:11 PM PDT 24
Finished Aug 02 08:03:21 PM PDT 24
Peak memory 575804 kb
Host smart-cf3148b4-3b60-48cb-824e-7498392bd1bf
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388615553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_zero_del
ays.1388615553
Directory /workspace/60.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_same_source.499838807
Short name T2610
Test name
Test status
Simulation time 124218023 ps
CPU time 10.59 seconds
Started Aug 02 08:03:21 PM PDT 24
Finished Aug 02 08:03:32 PM PDT 24
Peak memory 575916 kb
Host smart-21619e90-ccc8-4c20-87a7-a3b544e73634
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499838807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_same_source.499838807
Directory /workspace/60.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_smoke.3650943205
Short name T1911
Test name
Test status
Simulation time 43765902 ps
CPU time 6.57 seconds
Started Aug 02 08:03:09 PM PDT 24
Finished Aug 02 08:03:15 PM PDT 24
Peak memory 573788 kb
Host smart-ba1d5087-130a-418d-843d-110cda791649
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650943205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke.3650943205
Directory /workspace/60.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.2162909628
Short name T1812
Test name
Test status
Simulation time 9822956368 ps
CPU time 103.27 seconds
Started Aug 02 08:03:09 PM PDT 24
Finished Aug 02 08:04:53 PM PDT 24
Peak memory 573884 kb
Host smart-6ab8bba8-5964-4fa6-87a1-73f4b785878e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162909628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_large_delays.2162909628
Directory /workspace/60.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.1294777255
Short name T2451
Test name
Test status
Simulation time 4599342999 ps
CPU time 76.91 seconds
Started Aug 02 08:03:09 PM PDT 24
Finished Aug 02 08:04:26 PM PDT 24
Peak memory 573884 kb
Host smart-01496813-ea79-4c3e-876e-5360fbe1965f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294777255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_slow_rsp.1294777255
Directory /workspace/60.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.1393711810
Short name T2580
Test name
Test status
Simulation time 46470339 ps
CPU time 6.32 seconds
Started Aug 02 08:03:09 PM PDT 24
Finished Aug 02 08:03:16 PM PDT 24
Peak memory 574500 kb
Host smart-ee42c316-98e9-4eaa-83ca-72a949557a32
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393711810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_zero_delay
s.1393711810
Directory /workspace/60.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_stress_all.3600816532
Short name T2622
Test name
Test status
Simulation time 6642578598 ps
CPU time 251.88 seconds
Started Aug 02 08:03:25 PM PDT 24
Finished Aug 02 08:07:37 PM PDT 24
Peak memory 576788 kb
Host smart-15da80bc-85d3-4891-81ed-50f574bd89fd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600816532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all.3600816532
Directory /workspace/60.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.29428805
Short name T1855
Test name
Test status
Simulation time 4134855497 ps
CPU time 283.48 seconds
Started Aug 02 08:03:25 PM PDT 24
Finished Aug 02 08:08:09 PM PDT 24
Peak memory 576728 kb
Host smart-7a42da48-dd25-4604-9de8-1ff88c3d1747
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29428805 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_error.29428805
Directory /workspace/60.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.1300898248
Short name T2161
Test name
Test status
Simulation time 2190507437 ps
CPU time 230.53 seconds
Started Aug 02 08:03:25 PM PDT 24
Finished Aug 02 08:07:15 PM PDT 24
Peak memory 576772 kb
Host smart-415863df-b2f6-456f-b856-b0f59577a73f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300898248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all
_with_rand_reset.1300898248
Directory /workspace/60.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.1906406838
Short name T1930
Test name
Test status
Simulation time 4938985450 ps
CPU time 266.74 seconds
Started Aug 02 08:03:25 PM PDT 24
Finished Aug 02 08:07:52 PM PDT 24
Peak memory 576784 kb
Host smart-abcc1e27-df4b-4342-956f-ed3454a61fee
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906406838 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_al
l_with_reset_error.1906406838
Directory /workspace/60.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_unmapped_addr.845000783
Short name T1790
Test name
Test status
Simulation time 1030298842 ps
CPU time 44.16 seconds
Started Aug 02 08:03:24 PM PDT 24
Finished Aug 02 08:04:08 PM PDT 24
Peak memory 576084 kb
Host smart-c9ce3f6d-5f53-4745-a01d-de9810228bc9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845000783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_unmapped_addr.845000783
Directory /workspace/60.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_access_same_device.1414497486
Short name T1616
Test name
Test status
Simulation time 585458313 ps
CPU time 50.1 seconds
Started Aug 02 08:03:23 PM PDT 24
Finished Aug 02 08:04:13 PM PDT 24
Peak memory 575828 kb
Host smart-d2d12e1f-25c1-4113-a4a1-f70272f33043
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414497486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device
.1414497486
Directory /workspace/61.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.3393103526
Short name T1923
Test name
Test status
Simulation time 118585964104 ps
CPU time 2144.47 seconds
Started Aug 02 08:03:23 PM PDT 24
Finished Aug 02 08:39:08 PM PDT 24
Peak memory 576780 kb
Host smart-91904200-b11d-40b8-9e15-1791ef8652a0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393103526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_
device_slow_rsp.3393103526
Directory /workspace/61.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.3861950423
Short name T2164
Test name
Test status
Simulation time 1132347928 ps
CPU time 44.55 seconds
Started Aug 02 08:03:38 PM PDT 24
Finished Aug 02 08:04:23 PM PDT 24
Peak memory 575684 kb
Host smart-86f95c33-2f4b-4ff9-b2fd-afc305cf4d7f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861950423 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_and_unmapped_add
r.3861950423
Directory /workspace/61.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_error_random.3718125305
Short name T839
Test name
Test status
Simulation time 1613072551 ps
CPU time 57.24 seconds
Started Aug 02 08:03:23 PM PDT 24
Finished Aug 02 08:04:21 PM PDT 24
Peak memory 575748 kb
Host smart-e0dd2aae-416c-4b54-bdb4-2f55e0b22650
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718125305 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_random.3718125305
Directory /workspace/61.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_random.161862557
Short name T682
Test name
Test status
Simulation time 2068307057 ps
CPU time 80.45 seconds
Started Aug 02 08:03:23 PM PDT 24
Finished Aug 02 08:04:44 PM PDT 24
Peak memory 575916 kb
Host smart-b1f22b9a-5ab9-48d3-8dce-d7b95ae6f61d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161862557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random.161862557
Directory /workspace/61.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_random_large_delays.2502460447
Short name T670
Test name
Test status
Simulation time 62365703549 ps
CPU time 643.55 seconds
Started Aug 02 08:03:25 PM PDT 24
Finished Aug 02 08:14:09 PM PDT 24
Peak memory 576828 kb
Host smart-50f17bcf-6957-4079-a944-541d87e47611
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502460447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_large_delays.2502460447
Directory /workspace/61.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_random_slow_rsp.2814862787
Short name T2405
Test name
Test status
Simulation time 74075384008 ps
CPU time 1384.24 seconds
Started Aug 02 08:03:20 PM PDT 24
Finished Aug 02 08:26:25 PM PDT 24
Peak memory 575956 kb
Host smart-0ac2048a-0c02-412b-b060-585e2f7b86ee
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814862787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_slow_rsp.2814862787
Directory /workspace/61.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_random_zero_delays.1037377648
Short name T618
Test name
Test status
Simulation time 297664296 ps
CPU time 24.22 seconds
Started Aug 02 08:03:22 PM PDT 24
Finished Aug 02 08:03:47 PM PDT 24
Peak memory 575856 kb
Host smart-48152bc4-f1b2-4042-984e-fb775a7d4e7b
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037377648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_zero_del
ays.1037377648
Directory /workspace/61.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_same_source.2541592438
Short name T1903
Test name
Test status
Simulation time 503382897 ps
CPU time 32.79 seconds
Started Aug 02 08:03:21 PM PDT 24
Finished Aug 02 08:03:54 PM PDT 24
Peak memory 575740 kb
Host smart-1ee2e18e-841d-4774-98d3-b90d2077c9d6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541592438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_same_source.2541592438
Directory /workspace/61.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_smoke.3762316060
Short name T2016
Test name
Test status
Simulation time 230188398 ps
CPU time 10.02 seconds
Started Aug 02 08:03:25 PM PDT 24
Finished Aug 02 08:03:35 PM PDT 24
Peak memory 573796 kb
Host smart-b5967574-d41a-42bf-84ae-32079e7e5557
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762316060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke.3762316060
Directory /workspace/61.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_smoke_large_delays.2945160774
Short name T1509
Test name
Test status
Simulation time 8267022777 ps
CPU time 83.98 seconds
Started Aug 02 08:03:23 PM PDT 24
Finished Aug 02 08:04:47 PM PDT 24
Peak memory 574652 kb
Host smart-0ce34eda-511b-4bb3-8476-45f57318ea55
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945160774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_large_delays.2945160774
Directory /workspace/61.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.1725567732
Short name T2219
Test name
Test status
Simulation time 5719300238 ps
CPU time 101.01 seconds
Started Aug 02 08:03:25 PM PDT 24
Finished Aug 02 08:05:06 PM PDT 24
Peak memory 574536 kb
Host smart-46c1f55b-5338-4d93-be72-2eb5a136d28b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725567732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_slow_rsp.1725567732
Directory /workspace/61.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_smoke_zero_delays.3988408164
Short name T1591
Test name
Test status
Simulation time 54706431 ps
CPU time 6.65 seconds
Started Aug 02 08:03:23 PM PDT 24
Finished Aug 02 08:03:30 PM PDT 24
Peak memory 574496 kb
Host smart-ce36ec26-0784-4f8d-aade-fa212581400e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988408164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_zero_delay
s.3988408164
Directory /workspace/61.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_stress_all.3627956150
Short name T597
Test name
Test status
Simulation time 8168063972 ps
CPU time 320.82 seconds
Started Aug 02 08:03:37 PM PDT 24
Finished Aug 02 08:08:58 PM PDT 24
Peak memory 575944 kb
Host smart-40980295-e6e7-42c8-a2b9-8765f8e7b035
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627956150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all.3627956150
Directory /workspace/61.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.2370517530
Short name T2834
Test name
Test status
Simulation time 4747216060 ps
CPU time 150.51 seconds
Started Aug 02 08:03:38 PM PDT 24
Finished Aug 02 08:06:08 PM PDT 24
Peak memory 575952 kb
Host smart-74e0476e-78d1-46bc-bf66-17b47520a0a8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370517530 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_error.2370517530
Directory /workspace/61.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.3373935887
Short name T2266
Test name
Test status
Simulation time 3058704181 ps
CPU time 142.97 seconds
Started Aug 02 08:03:38 PM PDT 24
Finished Aug 02 08:06:01 PM PDT 24
Peak memory 575984 kb
Host smart-65d66afc-5978-40ea-ae08-d38484bfbda8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373935887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all
_with_rand_reset.3373935887
Directory /workspace/61.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.2719176581
Short name T2221
Test name
Test status
Simulation time 2551591387 ps
CPU time 468.24 seconds
Started Aug 02 08:03:38 PM PDT 24
Finished Aug 02 08:11:27 PM PDT 24
Peak memory 578948 kb
Host smart-8029df14-2e89-4bdc-a092-383bf1856df2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719176581 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_al
l_with_reset_error.2719176581
Directory /workspace/61.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_unmapped_addr.1772993225
Short name T1562
Test name
Test status
Simulation time 203350923 ps
CPU time 25.26 seconds
Started Aug 02 08:03:38 PM PDT 24
Finished Aug 02 08:04:04 PM PDT 24
Peak memory 575956 kb
Host smart-678339f6-8073-4821-bc23-d7c519ffaaae
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772993225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_unmapped_addr.1772993225
Directory /workspace/61.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_access_same_device.1963389323
Short name T2789
Test name
Test status
Simulation time 186805679 ps
CPU time 20.18 seconds
Started Aug 02 08:03:40 PM PDT 24
Finished Aug 02 08:04:00 PM PDT 24
Peak memory 576016 kb
Host smart-9d32eb8a-e9f5-4792-8703-3e71efa4e260
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963389323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device
.1963389323
Directory /workspace/62.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.207170879
Short name T1780
Test name
Test status
Simulation time 316327396 ps
CPU time 38.57 seconds
Started Aug 02 08:03:39 PM PDT 24
Finished Aug 02 08:04:17 PM PDT 24
Peak memory 575916 kb
Host smart-e48d43ba-f1f2-4902-80d0-fe6800d1a616
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207170879 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_and_unmapped_addr
.207170879
Directory /workspace/62.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_error_random.789066867
Short name T1964
Test name
Test status
Simulation time 1557039347 ps
CPU time 51.48 seconds
Started Aug 02 08:03:37 PM PDT 24
Finished Aug 02 08:04:28 PM PDT 24
Peak memory 575936 kb
Host smart-73748554-58db-422a-81c6-ca2c23b475a6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789066867 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_random.789066867
Directory /workspace/62.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_random.2602051243
Short name T2586
Test name
Test status
Simulation time 413491835 ps
CPU time 35.83 seconds
Started Aug 02 08:03:36 PM PDT 24
Finished Aug 02 08:04:12 PM PDT 24
Peak memory 575932 kb
Host smart-2c170295-643e-4081-b31a-f369911ba31f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602051243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random.2602051243
Directory /workspace/62.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_random_large_delays.2739948145
Short name T2300
Test name
Test status
Simulation time 101946999607 ps
CPU time 1062.14 seconds
Started Aug 02 08:03:41 PM PDT 24
Finished Aug 02 08:21:23 PM PDT 24
Peak memory 576100 kb
Host smart-b530e468-2097-4513-84bc-78cfcca5b1fc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739948145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_large_delays.2739948145
Directory /workspace/62.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_random_slow_rsp.1425625215
Short name T610
Test name
Test status
Simulation time 39394419587 ps
CPU time 707.73 seconds
Started Aug 02 08:03:38 PM PDT 24
Finished Aug 02 08:15:26 PM PDT 24
Peak memory 576060 kb
Host smart-51cbbd8b-a57f-4084-bb1b-b9931eab4675
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425625215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_slow_rsp.1425625215
Directory /workspace/62.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_random_zero_delays.3110241079
Short name T603
Test name
Test status
Simulation time 396038106 ps
CPU time 37.17 seconds
Started Aug 02 08:03:38 PM PDT 24
Finished Aug 02 08:04:15 PM PDT 24
Peak memory 575796 kb
Host smart-3407b2d5-460d-42e4-a4e5-ba84a87bc36a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110241079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_zero_del
ays.3110241079
Directory /workspace/62.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_same_source.2161527021
Short name T2004
Test name
Test status
Simulation time 136214937 ps
CPU time 10.18 seconds
Started Aug 02 08:03:40 PM PDT 24
Finished Aug 02 08:03:50 PM PDT 24
Peak memory 575936 kb
Host smart-f19d41ad-19bb-4a3f-b481-e3bdf2435e72
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161527021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_same_source.2161527021
Directory /workspace/62.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_smoke.1752754154
Short name T2158
Test name
Test status
Simulation time 209181886 ps
CPU time 8.97 seconds
Started Aug 02 08:03:36 PM PDT 24
Finished Aug 02 08:03:45 PM PDT 24
Peak memory 573836 kb
Host smart-fabfbaed-a13f-4909-9efe-bf7708dc5430
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752754154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke.1752754154
Directory /workspace/62.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_smoke_large_delays.2911527449
Short name T2515
Test name
Test status
Simulation time 7899171352 ps
CPU time 84.64 seconds
Started Aug 02 08:03:38 PM PDT 24
Finished Aug 02 08:05:03 PM PDT 24
Peak memory 574672 kb
Host smart-2bc5a876-b6ec-4c22-8195-c43ea38fbfe1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911527449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_large_delays.2911527449
Directory /workspace/62.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.520415350
Short name T1551
Test name
Test status
Simulation time 5577502156 ps
CPU time 91.45 seconds
Started Aug 02 08:03:38 PM PDT 24
Finished Aug 02 08:05:09 PM PDT 24
Peak memory 573952 kb
Host smart-8f20fb65-9e45-4c64-b91c-58e1906db646
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520415350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_slow_rsp.520415350
Directory /workspace/62.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_smoke_zero_delays.2362440925
Short name T2188
Test name
Test status
Simulation time 40078447 ps
CPU time 5.65 seconds
Started Aug 02 08:03:36 PM PDT 24
Finished Aug 02 08:03:41 PM PDT 24
Peak memory 573884 kb
Host smart-4626e4cd-7365-4be0-802a-088a6365528f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362440925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_zero_delay
s.2362440925
Directory /workspace/62.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_stress_all.1699168312
Short name T2931
Test name
Test status
Simulation time 2703573993 ps
CPU time 206.44 seconds
Started Aug 02 08:03:40 PM PDT 24
Finished Aug 02 08:07:07 PM PDT 24
Peak memory 576792 kb
Host smart-467492b9-bed1-40f1-915f-3d7036e2d99b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699168312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all.1699168312
Directory /workspace/62.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.3088596602
Short name T864
Test name
Test status
Simulation time 2891777809 ps
CPU time 213.37 seconds
Started Aug 02 08:03:44 PM PDT 24
Finished Aug 02 08:07:17 PM PDT 24
Peak memory 576724 kb
Host smart-e38e511e-1cc1-4a00-8b2f-2c048661132a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088596602 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_error.3088596602
Directory /workspace/62.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.2414075122
Short name T904
Test name
Test status
Simulation time 394182712 ps
CPU time 168.11 seconds
Started Aug 02 08:03:41 PM PDT 24
Finished Aug 02 08:06:29 PM PDT 24
Peak memory 576708 kb
Host smart-774311a8-9dcd-4063-9e9a-d58c17a91b85
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414075122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all
_with_rand_reset.2414075122
Directory /workspace/62.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.3392150711
Short name T1435
Test name
Test status
Simulation time 1874570043 ps
CPU time 140.61 seconds
Started Aug 02 08:03:44 PM PDT 24
Finished Aug 02 08:06:05 PM PDT 24
Peak memory 576664 kb
Host smart-b6b08561-9ac3-4aea-ac97-912e3d6c1c13
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392150711 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_al
l_with_reset_error.3392150711
Directory /workspace/62.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.2560641758
Short name T2867
Test name
Test status
Simulation time 383836135 ps
CPU time 17.07 seconds
Started Aug 02 08:03:41 PM PDT 24
Finished Aug 02 08:03:58 PM PDT 24
Peak memory 576052 kb
Host smart-d6b6634b-5a49-450e-8bb1-07d707c6d871
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560641758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_unmapped_addr.2560641758
Directory /workspace/62.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_access_same_device.1607389712
Short name T1838
Test name
Test status
Simulation time 558649766 ps
CPU time 50.73 seconds
Started Aug 02 08:03:51 PM PDT 24
Finished Aug 02 08:04:42 PM PDT 24
Peak memory 576008 kb
Host smart-9615c778-5bff-412a-8313-315033f45cf5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607389712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device
.1607389712
Directory /workspace/63.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.3940562776
Short name T2480
Test name
Test status
Simulation time 92477141347 ps
CPU time 1813.14 seconds
Started Aug 02 08:03:52 PM PDT 24
Finished Aug 02 08:34:06 PM PDT 24
Peak memory 575984 kb
Host smart-4bd000c5-82fb-4471-a6d9-7ae62df35b46
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940562776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_
device_slow_rsp.3940562776
Directory /workspace/63.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.2640200745
Short name T1546
Test name
Test status
Simulation time 967580387 ps
CPU time 38.32 seconds
Started Aug 02 08:03:52 PM PDT 24
Finished Aug 02 08:04:30 PM PDT 24
Peak memory 576052 kb
Host smart-329eb0dd-8a07-4f48-90e2-bee191b11182
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640200745 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_and_unmapped_add
r.2640200745
Directory /workspace/63.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_error_random.2972986767
Short name T1529
Test name
Test status
Simulation time 2039375438 ps
CPU time 79.54 seconds
Started Aug 02 08:03:51 PM PDT 24
Finished Aug 02 08:05:11 PM PDT 24
Peak memory 575768 kb
Host smart-817fdd88-8131-4633-9196-0e1f1bba5161
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972986767 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_random.2972986767
Directory /workspace/63.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_random.3363524751
Short name T1673
Test name
Test status
Simulation time 2334635206 ps
CPU time 81.71 seconds
Started Aug 02 08:03:50 PM PDT 24
Finished Aug 02 08:05:12 PM PDT 24
Peak memory 575916 kb
Host smart-077b00ad-c3f3-4d4b-857a-e591e88185d9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363524751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random.3363524751
Directory /workspace/63.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_random_large_delays.3808439484
Short name T1623
Test name
Test status
Simulation time 51314809863 ps
CPU time 571.86 seconds
Started Aug 02 08:03:55 PM PDT 24
Finished Aug 02 08:13:27 PM PDT 24
Peak memory 575856 kb
Host smart-cb4e125c-bd66-4db4-9025-eaff9081127c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808439484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_large_delays.3808439484
Directory /workspace/63.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_random_slow_rsp.3628980525
Short name T1905
Test name
Test status
Simulation time 33946973170 ps
CPU time 540.29 seconds
Started Aug 02 08:03:52 PM PDT 24
Finished Aug 02 08:12:52 PM PDT 24
Peak memory 576012 kb
Host smart-f2e883f0-31c4-42be-927d-d03dc8764f1f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628980525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_slow_rsp.3628980525
Directory /workspace/63.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_random_zero_delays.961723539
Short name T1887
Test name
Test status
Simulation time 363104521 ps
CPU time 30.84 seconds
Started Aug 02 08:03:52 PM PDT 24
Finished Aug 02 08:04:23 PM PDT 24
Peak memory 575740 kb
Host smart-f7a9be90-01ab-4ee9-b7e1-c755c364611f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961723539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_zero_dela
ys.961723539
Directory /workspace/63.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_same_source.627294634
Short name T2447
Test name
Test status
Simulation time 169977183 ps
CPU time 15.13 seconds
Started Aug 02 08:03:51 PM PDT 24
Finished Aug 02 08:04:06 PM PDT 24
Peak memory 576016 kb
Host smart-702ec6a1-ff89-4cc2-aa9d-4c41aa07405b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627294634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_same_source.627294634
Directory /workspace/63.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_smoke.3808751955
Short name T656
Test name
Test status
Simulation time 54840867 ps
CPU time 7.12 seconds
Started Aug 02 08:03:41 PM PDT 24
Finished Aug 02 08:03:48 PM PDT 24
Peak memory 574536 kb
Host smart-cf508302-767f-4709-b8b1-4841e2e57a05
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808751955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke.3808751955
Directory /workspace/63.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_smoke_large_delays.520038991
Short name T2497
Test name
Test status
Simulation time 9249436203 ps
CPU time 95.54 seconds
Started Aug 02 08:03:52 PM PDT 24
Finished Aug 02 08:05:28 PM PDT 24
Peak memory 574540 kb
Host smart-2a1f9bac-c0aa-48a2-98fc-c8f9c8616e31
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520038991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_large_delays.520038991
Directory /workspace/63.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.598031488
Short name T2077
Test name
Test status
Simulation time 4425591429 ps
CPU time 74.99 seconds
Started Aug 02 08:04:37 PM PDT 24
Finished Aug 02 08:05:52 PM PDT 24
Peak memory 574536 kb
Host smart-4b6d6585-ec04-4b40-b1f7-66c1461410d1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598031488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_slow_rsp.598031488
Directory /workspace/63.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_smoke_zero_delays.3229545999
Short name T2442
Test name
Test status
Simulation time 45570989 ps
CPU time 6.03 seconds
Started Aug 02 08:03:43 PM PDT 24
Finished Aug 02 08:03:50 PM PDT 24
Peak memory 573752 kb
Host smart-cd1e99c0-1717-405c-b909-dea117534bd6
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229545999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_zero_delay
s.3229545999
Directory /workspace/63.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_stress_all.1873324400
Short name T2836
Test name
Test status
Simulation time 5705717143 ps
CPU time 209.09 seconds
Started Aug 02 08:04:06 PM PDT 24
Finished Aug 02 08:07:35 PM PDT 24
Peak memory 575948 kb
Host smart-5234273c-8890-4ebd-ab4e-0c2ed7f44f80
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873324400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all.1873324400
Directory /workspace/63.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.2227882738
Short name T1931
Test name
Test status
Simulation time 6694291923 ps
CPU time 234.04 seconds
Started Aug 02 08:03:55 PM PDT 24
Finished Aug 02 08:07:49 PM PDT 24
Peak memory 576160 kb
Host smart-03b5f696-13b7-477d-a594-94b8c8a43b30
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227882738 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_error.2227882738
Directory /workspace/63.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.1879590305
Short name T510
Test name
Test status
Simulation time 6308233966 ps
CPU time 434.37 seconds
Started Aug 02 08:03:51 PM PDT 24
Finished Aug 02 08:11:06 PM PDT 24
Peak memory 576828 kb
Host smart-e5b0c3c4-80e2-406b-92a2-671717c3ccc7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879590305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all
_with_rand_reset.1879590305
Directory /workspace/63.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_unmapped_addr.1402683476
Short name T1858
Test name
Test status
Simulation time 91710721 ps
CPU time 6.63 seconds
Started Aug 02 08:03:51 PM PDT 24
Finished Aug 02 08:03:57 PM PDT 24
Peak memory 574536 kb
Host smart-15e4c025-49f8-42bf-ba8b-0ea75ebab428
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402683476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_unmapped_addr.1402683476
Directory /workspace/63.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_access_same_device.3056350862
Short name T1962
Test name
Test status
Simulation time 139638380 ps
CPU time 11.66 seconds
Started Aug 02 08:04:04 PM PDT 24
Finished Aug 02 08:04:16 PM PDT 24
Peak memory 575908 kb
Host smart-a18c1278-92a4-4502-8de6-5e8608be8cf5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056350862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device
.3056350862
Directory /workspace/64.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.1986817984
Short name T2657
Test name
Test status
Simulation time 5709941613 ps
CPU time 98.91 seconds
Started Aug 02 08:04:09 PM PDT 24
Finished Aug 02 08:05:48 PM PDT 24
Peak memory 574520 kb
Host smart-d30ebddf-9c3a-4c2b-bbbe-60e1a8588a34
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986817984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_
device_slow_rsp.1986817984
Directory /workspace/64.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.719124708
Short name T1736
Test name
Test status
Simulation time 1204206493 ps
CPU time 49.8 seconds
Started Aug 02 08:04:07 PM PDT 24
Finished Aug 02 08:04:57 PM PDT 24
Peak memory 575784 kb
Host smart-2371b0d7-9d60-438b-82ee-e3e827191727
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719124708 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_and_unmapped_addr
.719124708
Directory /workspace/64.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_error_random.121402559
Short name T2151
Test name
Test status
Simulation time 177514845 ps
CPU time 16.93 seconds
Started Aug 02 08:04:05 PM PDT 24
Finished Aug 02 08:04:22 PM PDT 24
Peak memory 575696 kb
Host smart-285d471e-32be-4896-96f1-4c0612cc24da
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121402559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_random.121402559
Directory /workspace/64.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_random.221047640
Short name T1700
Test name
Test status
Simulation time 126393396 ps
CPU time 7.62 seconds
Started Aug 02 08:03:50 PM PDT 24
Finished Aug 02 08:03:57 PM PDT 24
Peak memory 574624 kb
Host smart-94ab215b-e265-4b19-8c09-0e12edcbfdef
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221047640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random.221047640
Directory /workspace/64.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_random_large_delays.1835995756
Short name T1975
Test name
Test status
Simulation time 2506374497 ps
CPU time 30.01 seconds
Started Aug 02 08:03:55 PM PDT 24
Finished Aug 02 08:04:25 PM PDT 24
Peak memory 573856 kb
Host smart-e69a4767-ba79-46f8-84d1-468867aceabf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835995756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_large_delays.1835995756
Directory /workspace/64.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.715156416
Short name T588
Test name
Test status
Simulation time 62074032150 ps
CPU time 1077.74 seconds
Started Aug 02 08:04:09 PM PDT 24
Finished Aug 02 08:22:07 PM PDT 24
Peak memory 575884 kb
Host smart-87b51aa0-0f49-4ddf-abc6-7528b8070caf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715156416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_slow_rsp.715156416
Directory /workspace/64.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_random_zero_delays.2267193009
Short name T2229
Test name
Test status
Simulation time 33133424 ps
CPU time 5.96 seconds
Started Aug 02 08:03:49 PM PDT 24
Finished Aug 02 08:03:55 PM PDT 24
Peak memory 573828 kb
Host smart-e8dcfafe-20a7-49e4-94fa-2e7802a15bcb
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267193009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_zero_del
ays.2267193009
Directory /workspace/64.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_same_source.3180565526
Short name T1628
Test name
Test status
Simulation time 273430540 ps
CPU time 20.69 seconds
Started Aug 02 08:04:05 PM PDT 24
Finished Aug 02 08:04:26 PM PDT 24
Peak memory 575856 kb
Host smart-6805c221-9169-4776-be8e-d3aa387010bb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180565526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_same_source.3180565526
Directory /workspace/64.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_smoke.2896450748
Short name T2876
Test name
Test status
Simulation time 212736773 ps
CPU time 9.19 seconds
Started Aug 02 08:03:55 PM PDT 24
Finished Aug 02 08:04:04 PM PDT 24
Peak memory 573864 kb
Host smart-6cddcfb8-ada2-4f04-8713-6649ec46eb4c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896450748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke.2896450748
Directory /workspace/64.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_smoke_large_delays.1125548473
Short name T1684
Test name
Test status
Simulation time 7717457330 ps
CPU time 73.26 seconds
Started Aug 02 08:03:50 PM PDT 24
Finished Aug 02 08:05:03 PM PDT 24
Peak memory 573892 kb
Host smart-d2f33478-7eeb-44b3-b98c-5468c38adbf9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125548473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_large_delays.1125548473
Directory /workspace/64.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.4102383690
Short name T1600
Test name
Test status
Simulation time 6012220803 ps
CPU time 101.74 seconds
Started Aug 02 08:03:53 PM PDT 24
Finished Aug 02 08:05:34 PM PDT 24
Peak memory 573972 kb
Host smart-25bf4174-9985-405e-a210-e7452a25d8fd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102383690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_slow_rsp.4102383690
Directory /workspace/64.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.1567133357
Short name T2441
Test name
Test status
Simulation time 51748837 ps
CPU time 6.82 seconds
Started Aug 02 08:03:54 PM PDT 24
Finished Aug 02 08:04:01 PM PDT 24
Peak memory 573844 kb
Host smart-4b550f88-5271-4803-8918-55519f259db2
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567133357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_zero_delay
s.1567133357
Directory /workspace/64.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_stress_all.2924069093
Short name T2485
Test name
Test status
Simulation time 599472947 ps
CPU time 44.79 seconds
Started Aug 02 08:04:06 PM PDT 24
Finished Aug 02 08:04:51 PM PDT 24
Peak memory 575936 kb
Host smart-33099c0d-b13b-4e37-9382-3d34f2c516a3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924069093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all.2924069093
Directory /workspace/64.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_error.3518578060
Short name T2709
Test name
Test status
Simulation time 2314493792 ps
CPU time 171.78 seconds
Started Aug 02 08:04:09 PM PDT 24
Finished Aug 02 08:07:01 PM PDT 24
Peak memory 575896 kb
Host smart-a0c562e6-f6dc-4eeb-bafb-ba30a80cfa2f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518578060 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_error.3518578060
Directory /workspace/64.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.2137409606
Short name T1920
Test name
Test status
Simulation time 241169451 ps
CPU time 60.3 seconds
Started Aug 02 08:04:05 PM PDT 24
Finished Aug 02 08:05:06 PM PDT 24
Peak memory 575936 kb
Host smart-c9b6a8b7-27ef-4001-b514-99dc283c8be4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137409606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all
_with_rand_reset.2137409606
Directory /workspace/64.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.2057940033
Short name T2793
Test name
Test status
Simulation time 836433394 ps
CPU time 194.96 seconds
Started Aug 02 08:04:07 PM PDT 24
Finished Aug 02 08:07:22 PM PDT 24
Peak memory 575940 kb
Host smart-ac45da5d-ca40-4d9c-bd61-3d1497bb6bd7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057940033 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_al
l_with_reset_error.2057940033
Directory /workspace/64.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.1887923407
Short name T2659
Test name
Test status
Simulation time 524761926 ps
CPU time 24.87 seconds
Started Aug 02 08:04:10 PM PDT 24
Finished Aug 02 08:04:34 PM PDT 24
Peak memory 575912 kb
Host smart-792ad3b9-d8fe-49aa-87be-9535e5e1d214
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887923407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_unmapped_addr.1887923407
Directory /workspace/64.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_access_same_device.174519105
Short name T1781
Test name
Test status
Simulation time 858126482 ps
CPU time 36.13 seconds
Started Aug 02 08:04:07 PM PDT 24
Finished Aug 02 08:04:43 PM PDT 24
Peak memory 575964 kb
Host smart-3789545d-ae0b-4df6-894d-1fd0fd6384b6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174519105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device.
174519105
Directory /workspace/65.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.3784832887
Short name T2667
Test name
Test status
Simulation time 149583044185 ps
CPU time 2585.07 seconds
Started Aug 02 08:04:08 PM PDT 24
Finished Aug 02 08:47:13 PM PDT 24
Peak memory 576896 kb
Host smart-a6939087-b71d-46bd-83fe-3fd3ed52bfbc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784832887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_
device_slow_rsp.3784832887
Directory /workspace/65.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.2416737840
Short name T1584
Test name
Test status
Simulation time 71141220 ps
CPU time 5.79 seconds
Started Aug 02 08:04:05 PM PDT 24
Finished Aug 02 08:04:11 PM PDT 24
Peak memory 573856 kb
Host smart-6a51d23a-712e-48ff-9acd-ee8e1fd78905
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416737840 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_and_unmapped_add
r.2416737840
Directory /workspace/65.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_error_random.124711772
Short name T2746
Test name
Test status
Simulation time 421689810 ps
CPU time 16.89 seconds
Started Aug 02 08:04:06 PM PDT 24
Finished Aug 02 08:04:23 PM PDT 24
Peak memory 575848 kb
Host smart-a5b17320-5e46-4c1f-8704-1a07e5385daa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124711772 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_random.124711772
Directory /workspace/65.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_random.2954886208
Short name T2875
Test name
Test status
Simulation time 123739089 ps
CPU time 7.85 seconds
Started Aug 02 08:04:07 PM PDT 24
Finished Aug 02 08:04:14 PM PDT 24
Peak memory 574612 kb
Host smart-53348248-1c18-4f61-81c7-044ae0593e7b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954886208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random.2954886208
Directory /workspace/65.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_random_large_delays.2973715563
Short name T2425
Test name
Test status
Simulation time 87009509297 ps
CPU time 992.71 seconds
Started Aug 02 08:04:06 PM PDT 24
Finished Aug 02 08:20:39 PM PDT 24
Peak memory 575940 kb
Host smart-ff1f6b4d-55fc-44d8-9a4f-5b4ce846a92c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973715563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_large_delays.2973715563
Directory /workspace/65.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.783805569
Short name T2537
Test name
Test status
Simulation time 18905419352 ps
CPU time 339.19 seconds
Started Aug 02 08:04:09 PM PDT 24
Finished Aug 02 08:09:48 PM PDT 24
Peak memory 576024 kb
Host smart-b571a2d0-e500-4e0d-a0da-78c769f839e7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783805569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_slow_rsp.783805569
Directory /workspace/65.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.3134798154
Short name T518
Test name
Test status
Simulation time 145532723 ps
CPU time 14.4 seconds
Started Aug 02 08:04:04 PM PDT 24
Finished Aug 02 08:04:19 PM PDT 24
Peak memory 575868 kb
Host smart-4a265b7c-a5b2-4355-a53d-76e43277d675
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134798154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_zero_del
ays.3134798154
Directory /workspace/65.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_same_source.2855131301
Short name T2694
Test name
Test status
Simulation time 362657303 ps
CPU time 31.42 seconds
Started Aug 02 08:04:03 PM PDT 24
Finished Aug 02 08:04:35 PM PDT 24
Peak memory 575864 kb
Host smart-75a44b3a-b68c-4966-966c-a1216923f4d6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855131301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_same_source.2855131301
Directory /workspace/65.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_smoke.2617084851
Short name T1417
Test name
Test status
Simulation time 181037573 ps
CPU time 8.59 seconds
Started Aug 02 08:04:06 PM PDT 24
Finished Aug 02 08:04:14 PM PDT 24
Peak memory 574564 kb
Host smart-474e044a-998c-4a7a-bc42-e29d3e65242c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617084851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke.2617084851
Directory /workspace/65.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_smoke_large_delays.2836738285
Short name T2468
Test name
Test status
Simulation time 10658362543 ps
CPU time 112.61 seconds
Started Aug 02 08:04:07 PM PDT 24
Finished Aug 02 08:06:00 PM PDT 24
Peak memory 573840 kb
Host smart-fb2d7ec4-b48c-484b-91aa-fbbf0087eea9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836738285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_large_delays.2836738285
Directory /workspace/65.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.363321156
Short name T2404
Test name
Test status
Simulation time 4362614651 ps
CPU time 74.74 seconds
Started Aug 02 08:04:08 PM PDT 24
Finished Aug 02 08:05:23 PM PDT 24
Peak memory 573928 kb
Host smart-cb48194c-9b2a-4810-8c4f-3e59cea4b4c9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363321156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_slow_rsp.363321156
Directory /workspace/65.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.2761109648
Short name T1422
Test name
Test status
Simulation time 57073647 ps
CPU time 7.26 seconds
Started Aug 02 08:04:09 PM PDT 24
Finished Aug 02 08:04:17 PM PDT 24
Peak memory 573768 kb
Host smart-e567909d-654b-4829-9f42-a07d4243ee2e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761109648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_zero_delay
s.2761109648
Directory /workspace/65.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_stress_all.1770307822
Short name T1621
Test name
Test status
Simulation time 1888117574 ps
CPU time 73.22 seconds
Started Aug 02 08:04:04 PM PDT 24
Finished Aug 02 08:05:17 PM PDT 24
Peak memory 576012 kb
Host smart-0c07a7bb-1620-4a2d-8cc5-6bcde224e14d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770307822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all.1770307822
Directory /workspace/65.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_error.1621962898
Short name T2354
Test name
Test status
Simulation time 9833124496 ps
CPU time 349.94 seconds
Started Aug 02 08:04:10 PM PDT 24
Finished Aug 02 08:10:00 PM PDT 24
Peak memory 576136 kb
Host smart-e2a2bb53-880a-4fd0-9126-2a9d4458bd16
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621962898 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_error.1621962898
Directory /workspace/65.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.3228613001
Short name T2430
Test name
Test status
Simulation time 5789318995 ps
CPU time 766.2 seconds
Started Aug 02 08:04:08 PM PDT 24
Finished Aug 02 08:16:55 PM PDT 24
Peak memory 576744 kb
Host smart-f768fc5c-983a-433c-96e9-c1b52659e2a5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228613001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all
_with_rand_reset.3228613001
Directory /workspace/65.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.538262144
Short name T2251
Test name
Test status
Simulation time 352604629 ps
CPU time 126.93 seconds
Started Aug 02 08:04:04 PM PDT 24
Finished Aug 02 08:06:11 PM PDT 24
Peak memory 576828 kb
Host smart-7c1cf231-5177-495f-bf7d-5888dd11e518
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538262144 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all
_with_reset_error.538262144
Directory /workspace/65.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_unmapped_addr.4051890217
Short name T1660
Test name
Test status
Simulation time 236594526 ps
CPU time 26.41 seconds
Started Aug 02 08:04:06 PM PDT 24
Finished Aug 02 08:04:33 PM PDT 24
Peak memory 575920 kb
Host smart-8cbced47-a1d9-4b5d-bfcd-96705aba6a72
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051890217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_unmapped_addr.4051890217
Directory /workspace/65.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_access_same_device.226205734
Short name T1659
Test name
Test status
Simulation time 2290165725 ps
CPU time 82.81 seconds
Started Aug 02 08:04:17 PM PDT 24
Finished Aug 02 08:05:40 PM PDT 24
Peak memory 575788 kb
Host smart-85a7b0dd-6aed-4ef2-9330-593b12b82476
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226205734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device.
226205734
Directory /workspace/66.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.3437462097
Short name T2369
Test name
Test status
Simulation time 88186076232 ps
CPU time 1616.79 seconds
Started Aug 02 08:04:25 PM PDT 24
Finished Aug 02 08:31:22 PM PDT 24
Peak memory 576056 kb
Host smart-a114e56d-1ff0-48bd-8807-2333b94ec213
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437462097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_
device_slow_rsp.3437462097
Directory /workspace/66.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.3177927112
Short name T1460
Test name
Test status
Simulation time 1039686749 ps
CPU time 39.6 seconds
Started Aug 02 08:04:23 PM PDT 24
Finished Aug 02 08:05:03 PM PDT 24
Peak memory 575960 kb
Host smart-ce5fb310-e98e-46b9-8574-9007cc6d131c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177927112 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_and_unmapped_add
r.3177927112
Directory /workspace/66.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_error_random.2630552971
Short name T1969
Test name
Test status
Simulation time 1858302585 ps
CPU time 56.71 seconds
Started Aug 02 08:04:23 PM PDT 24
Finished Aug 02 08:05:20 PM PDT 24
Peak memory 575880 kb
Host smart-a3e0d265-d140-483b-84ea-dadd7df49db2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630552971 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_random.2630552971
Directory /workspace/66.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_random.2509014519
Short name T1737
Test name
Test status
Simulation time 880825282 ps
CPU time 30.77 seconds
Started Aug 02 08:04:09 PM PDT 24
Finished Aug 02 08:04:40 PM PDT 24
Peak memory 575788 kb
Host smart-fb881845-3661-4876-8bab-6165c9291ede
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509014519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random.2509014519
Directory /workspace/66.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_random_large_delays.3547646377
Short name T1614
Test name
Test status
Simulation time 72349149397 ps
CPU time 795.3 seconds
Started Aug 02 08:04:07 PM PDT 24
Finished Aug 02 08:17:23 PM PDT 24
Peak memory 575920 kb
Host smart-7b6203f5-c2f5-4b90-b4e0-ab9145097ed9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547646377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_large_delays.3547646377
Directory /workspace/66.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_random_slow_rsp.3231125853
Short name T2511
Test name
Test status
Simulation time 48124641295 ps
CPU time 898.07 seconds
Started Aug 02 08:04:10 PM PDT 24
Finished Aug 02 08:19:08 PM PDT 24
Peak memory 575884 kb
Host smart-05ddf563-0264-49c3-8a18-942f00e49074
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231125853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_slow_rsp.3231125853
Directory /workspace/66.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_random_zero_delays.2404685246
Short name T1596
Test name
Test status
Simulation time 493463054 ps
CPU time 45.81 seconds
Started Aug 02 08:04:07 PM PDT 24
Finished Aug 02 08:04:52 PM PDT 24
Peak memory 575772 kb
Host smart-fd0323fe-8cd9-41f4-8487-4973b29be56d
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404685246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_zero_del
ays.2404685246
Directory /workspace/66.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_same_source.2034051797
Short name T2554
Test name
Test status
Simulation time 99027006 ps
CPU time 9.18 seconds
Started Aug 02 08:04:25 PM PDT 24
Finished Aug 02 08:04:34 PM PDT 24
Peak memory 575820 kb
Host smart-d10cb88b-9934-4edc-ba86-81ce1bd77868
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034051797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_same_source.2034051797
Directory /workspace/66.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_smoke.2016986796
Short name T675
Test name
Test status
Simulation time 51076161 ps
CPU time 6.85 seconds
Started Aug 02 08:04:07 PM PDT 24
Finished Aug 02 08:04:14 PM PDT 24
Peak memory 574560 kb
Host smart-3889b818-64b4-4d1f-ac07-6fa89128df42
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016986796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke.2016986796
Directory /workspace/66.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_smoke_large_delays.2581218442
Short name T766
Test name
Test status
Simulation time 10705111459 ps
CPU time 123.43 seconds
Started Aug 02 08:04:10 PM PDT 24
Finished Aug 02 08:06:13 PM PDT 24
Peak memory 574560 kb
Host smart-1c49eb8f-8742-4c92-9f1c-201de3dc30e8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581218442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_large_delays.2581218442
Directory /workspace/66.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.862801821
Short name T2105
Test name
Test status
Simulation time 3368513780 ps
CPU time 56.34 seconds
Started Aug 02 08:04:05 PM PDT 24
Finished Aug 02 08:05:01 PM PDT 24
Peak memory 574552 kb
Host smart-06cedb05-5c94-48b8-97cb-6b9ea4ed5714
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862801821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_slow_rsp.862801821
Directory /workspace/66.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.2517628413
Short name T1452
Test name
Test status
Simulation time 39159102 ps
CPU time 6.27 seconds
Started Aug 02 08:04:07 PM PDT 24
Finished Aug 02 08:04:13 PM PDT 24
Peak memory 573768 kb
Host smart-828ba97e-584c-4970-b121-aefb53458750
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517628413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_zero_delay
s.2517628413
Directory /workspace/66.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_stress_all.1730719240
Short name T2926
Test name
Test status
Simulation time 3532043613 ps
CPU time 296.25 seconds
Started Aug 02 08:04:23 PM PDT 24
Finished Aug 02 08:09:20 PM PDT 24
Peak memory 576796 kb
Host smart-505d952c-72d5-4db2-a726-86d84467a350
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730719240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all.1730719240
Directory /workspace/66.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.1698262808
Short name T1708
Test name
Test status
Simulation time 10110301810 ps
CPU time 362.22 seconds
Started Aug 02 08:04:20 PM PDT 24
Finished Aug 02 08:10:23 PM PDT 24
Peak memory 576752 kb
Host smart-dd746b7a-47dd-48b6-8ca4-3daa13730532
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698262808 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_error.1698262808
Directory /workspace/66.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.2607225121
Short name T1918
Test name
Test status
Simulation time 7603559687 ps
CPU time 437.65 seconds
Started Aug 02 08:04:28 PM PDT 24
Finished Aug 02 08:11:45 PM PDT 24
Peak memory 576824 kb
Host smart-0504e824-c8da-442c-9e29-713274fa7d6d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607225121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all
_with_rand_reset.2607225121
Directory /workspace/66.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.1435819353
Short name T908
Test name
Test status
Simulation time 88383775 ps
CPU time 19.67 seconds
Started Aug 02 08:04:24 PM PDT 24
Finished Aug 02 08:04:44 PM PDT 24
Peak memory 576016 kb
Host smart-e8a4f443-db19-4ebd-9bd9-650cd62241b8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435819353 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_al
l_with_reset_error.1435819353
Directory /workspace/66.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.1736763635
Short name T2144
Test name
Test status
Simulation time 779595185 ps
CPU time 31.89 seconds
Started Aug 02 08:04:23 PM PDT 24
Finished Aug 02 08:04:55 PM PDT 24
Peak memory 575988 kb
Host smart-bacc1bfc-2c3f-4d9d-890c-94ba1b07d80a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736763635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_unmapped_addr.1736763635
Directory /workspace/66.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_access_same_device.2050731501
Short name T2375
Test name
Test status
Simulation time 469394414 ps
CPU time 49 seconds
Started Aug 02 08:04:24 PM PDT 24
Finished Aug 02 08:05:13 PM PDT 24
Peak memory 575840 kb
Host smart-b32c0bb8-dadd-49db-9372-51ce50cdf56b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050731501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device
.2050731501
Directory /workspace/67.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.2612941730
Short name T1739
Test name
Test status
Simulation time 31399847753 ps
CPU time 518.07 seconds
Started Aug 02 08:04:24 PM PDT 24
Finished Aug 02 08:13:03 PM PDT 24
Peak memory 576020 kb
Host smart-bd4bbc14-4d6c-4972-b180-c6a85a2e2c34
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612941730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_
device_slow_rsp.2612941730
Directory /workspace/67.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.1779798618
Short name T1457
Test name
Test status
Simulation time 158333687 ps
CPU time 15.91 seconds
Started Aug 02 08:04:21 PM PDT 24
Finished Aug 02 08:04:37 PM PDT 24
Peak memory 575708 kb
Host smart-f5713fe4-f1c2-4daa-adcf-9c8867c7266f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779798618 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_and_unmapped_add
r.1779798618
Directory /workspace/67.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_error_random.3202340260
Short name T1897
Test name
Test status
Simulation time 174292541 ps
CPU time 15.61 seconds
Started Aug 02 08:04:23 PM PDT 24
Finished Aug 02 08:04:38 PM PDT 24
Peak memory 575904 kb
Host smart-a99a0219-ccb2-4cfc-80c1-64cc00d46b76
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202340260 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_random.3202340260
Directory /workspace/67.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_random.2855775831
Short name T2731
Test name
Test status
Simulation time 1823344244 ps
CPU time 70.55 seconds
Started Aug 02 08:04:21 PM PDT 24
Finished Aug 02 08:05:32 PM PDT 24
Peak memory 575884 kb
Host smart-7cdb6167-3b7d-41b6-a862-c988e2e19618
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855775831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random.2855775831
Directory /workspace/67.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_random_large_delays.3363797060
Short name T2191
Test name
Test status
Simulation time 11786481597 ps
CPU time 119.68 seconds
Started Aug 02 08:04:22 PM PDT 24
Finished Aug 02 08:06:22 PM PDT 24
Peak memory 576728 kb
Host smart-91813acf-a611-4df7-bf4c-9e0dd741b133
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363797060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_large_delays.3363797060
Directory /workspace/67.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_random_slow_rsp.823098596
Short name T2104
Test name
Test status
Simulation time 39372732307 ps
CPU time 666.32 seconds
Started Aug 02 08:04:24 PM PDT 24
Finished Aug 02 08:15:30 PM PDT 24
Peak memory 575844 kb
Host smart-3fa6ebdc-33b6-449a-8d00-3ed62f8a4265
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823098596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_slow_rsp.823098596
Directory /workspace/67.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.3817545831
Short name T2861
Test name
Test status
Simulation time 283983171 ps
CPU time 27.65 seconds
Started Aug 02 08:04:24 PM PDT 24
Finished Aug 02 08:04:52 PM PDT 24
Peak memory 575880 kb
Host smart-67fb2c58-375d-420d-b033-3b535c68ae83
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817545831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_zero_del
ays.3817545831
Directory /workspace/67.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_same_source.1739910036
Short name T2784
Test name
Test status
Simulation time 75112950 ps
CPU time 8.14 seconds
Started Aug 02 08:04:24 PM PDT 24
Finished Aug 02 08:04:32 PM PDT 24
Peak memory 575692 kb
Host smart-4a080766-dc2a-4348-acc4-d4b25bcfe590
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739910036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_same_source.1739910036
Directory /workspace/67.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_smoke.1316745340
Short name T2762
Test name
Test status
Simulation time 46477259 ps
CPU time 6.53 seconds
Started Aug 02 08:04:21 PM PDT 24
Finished Aug 02 08:04:27 PM PDT 24
Peak memory 573832 kb
Host smart-afc28542-9638-420d-8c5b-05608b16a257
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316745340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke.1316745340
Directory /workspace/67.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_smoke_large_delays.1933093077
Short name T1612
Test name
Test status
Simulation time 5765014063 ps
CPU time 60.56 seconds
Started Aug 02 08:04:39 PM PDT 24
Finished Aug 02 08:05:39 PM PDT 24
Peak memory 574616 kb
Host smart-1405a207-c7f6-40c0-a185-6f109acc1e29
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933093077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_large_delays.1933093077
Directory /workspace/67.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_smoke_zero_delays.2178170925
Short name T1455
Test name
Test status
Simulation time 42005272 ps
CPU time 5.64 seconds
Started Aug 02 08:04:24 PM PDT 24
Finished Aug 02 08:04:30 PM PDT 24
Peak memory 573824 kb
Host smart-c283c969-e369-466d-86f0-0f6f930e109b
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178170925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_zero_delay
s.2178170925
Directory /workspace/67.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_stress_all.3433579326
Short name T1860
Test name
Test status
Simulation time 20864308807 ps
CPU time 838.25 seconds
Started Aug 02 08:04:26 PM PDT 24
Finished Aug 02 08:18:25 PM PDT 24
Peak memory 576028 kb
Host smart-af2677d5-0931-4d6c-9739-63270c4125a8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433579326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all.3433579326
Directory /workspace/67.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_error.2033184680
Short name T2022
Test name
Test status
Simulation time 7717493941 ps
CPU time 246.51 seconds
Started Aug 02 08:04:23 PM PDT 24
Finished Aug 02 08:08:30 PM PDT 24
Peak memory 576016 kb
Host smart-2dd830bb-5933-4022-a017-00148144615e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033184680 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_error.2033184680
Directory /workspace/67.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.2693520297
Short name T2013
Test name
Test status
Simulation time 9005954257 ps
CPU time 402.36 seconds
Started Aug 02 08:04:22 PM PDT 24
Finished Aug 02 08:11:05 PM PDT 24
Peak memory 576000 kb
Host smart-e2fbf246-2ff6-4dc6-8e1d-e366733dedbe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693520297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all
_with_rand_reset.2693520297
Directory /workspace/67.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.3608977936
Short name T2223
Test name
Test status
Simulation time 381758835 ps
CPU time 119.43 seconds
Started Aug 02 08:04:24 PM PDT 24
Finished Aug 02 08:06:24 PM PDT 24
Peak memory 576772 kb
Host smart-bdde3804-9547-4e19-852d-c3d6e99f099d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608977936 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_al
l_with_reset_error.3608977936
Directory /workspace/67.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_unmapped_addr.3762023825
Short name T1936
Test name
Test status
Simulation time 40134280 ps
CPU time 6.74 seconds
Started Aug 02 08:04:25 PM PDT 24
Finished Aug 02 08:04:33 PM PDT 24
Peak memory 573976 kb
Host smart-848dfe1b-5346-4373-8116-ed830753067c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762023825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_unmapped_addr.3762023825
Directory /workspace/67.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_access_same_device.775485853
Short name T2367
Test name
Test status
Simulation time 2046101235 ps
CPU time 82.13 seconds
Started Aug 02 08:04:46 PM PDT 24
Finished Aug 02 08:06:09 PM PDT 24
Peak memory 575864 kb
Host smart-14b1ac9a-8876-4556-a3c7-69bf1f62acd7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775485853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device.
775485853
Directory /workspace/68.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.759625025
Short name T872
Test name
Test status
Simulation time 57821374763 ps
CPU time 1052.34 seconds
Started Aug 02 08:04:42 PM PDT 24
Finished Aug 02 08:22:14 PM PDT 24
Peak memory 575864 kb
Host smart-a8084b70-b417-4140-aee3-855120315af8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759625025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_d
evice_slow_rsp.759625025
Directory /workspace/68.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.158477201
Short name T2776
Test name
Test status
Simulation time 942404107 ps
CPU time 35.04 seconds
Started Aug 02 08:04:40 PM PDT 24
Finished Aug 02 08:05:15 PM PDT 24
Peak memory 575848 kb
Host smart-4f174b28-dee5-40c3-be01-662e076bde0b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158477201 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_and_unmapped_addr
.158477201
Directory /workspace/68.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_error_random.3847991838
Short name T1808
Test name
Test status
Simulation time 1059819952 ps
CPU time 38.56 seconds
Started Aug 02 08:04:40 PM PDT 24
Finished Aug 02 08:05:19 PM PDT 24
Peak memory 576052 kb
Host smart-1cecdab8-173b-442d-b474-af24d8762891
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847991838 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_random.3847991838
Directory /workspace/68.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_random.1014964167
Short name T634
Test name
Test status
Simulation time 62571685 ps
CPU time 7.95 seconds
Started Aug 02 08:04:40 PM PDT 24
Finished Aug 02 08:04:48 PM PDT 24
Peak memory 575908 kb
Host smart-3471e262-8810-4694-a206-a1fa461fbaf2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014964167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random.1014964167
Directory /workspace/68.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_random_large_delays.2119807827
Short name T580
Test name
Test status
Simulation time 98838571490 ps
CPU time 1099.45 seconds
Started Aug 02 08:04:43 PM PDT 24
Finished Aug 02 08:23:03 PM PDT 24
Peak memory 576092 kb
Host smart-b2b6be3f-654b-43ac-a384-09f11e4f5712
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119807827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_large_delays.2119807827
Directory /workspace/68.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_random_slow_rsp.3027584351
Short name T2062
Test name
Test status
Simulation time 47345497463 ps
CPU time 920.04 seconds
Started Aug 02 08:04:37 PM PDT 24
Finished Aug 02 08:19:58 PM PDT 24
Peak memory 576108 kb
Host smart-d6495259-1582-4e63-b125-4bc60ed1fffa
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027584351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_slow_rsp.3027584351
Directory /workspace/68.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_random_zero_delays.749318629
Short name T2276
Test name
Test status
Simulation time 65404504 ps
CPU time 7.81 seconds
Started Aug 02 08:04:42 PM PDT 24
Finished Aug 02 08:04:50 PM PDT 24
Peak memory 575888 kb
Host smart-021c094e-f0c8-4a18-b737-e6428c23815e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749318629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_zero_dela
ys.749318629
Directory /workspace/68.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_same_source.2373422225
Short name T1751
Test name
Test status
Simulation time 372595455 ps
CPU time 26.49 seconds
Started Aug 02 08:04:36 PM PDT 24
Finished Aug 02 08:05:02 PM PDT 24
Peak memory 575876 kb
Host smart-bdfde3e7-7f21-42de-8a1a-01e8895aec34
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373422225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_same_source.2373422225
Directory /workspace/68.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_smoke.3654231185
Short name T1447
Test name
Test status
Simulation time 52060850 ps
CPU time 6.43 seconds
Started Aug 02 08:04:34 PM PDT 24
Finished Aug 02 08:04:40 PM PDT 24
Peak memory 573848 kb
Host smart-27631b89-486c-41a7-9aa2-33d9d1dde08a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654231185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke.3654231185
Directory /workspace/68.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_smoke_large_delays.2408863328
Short name T2381
Test name
Test status
Simulation time 8953772056 ps
CPU time 89.77 seconds
Started Aug 02 08:04:41 PM PDT 24
Finished Aug 02 08:06:10 PM PDT 24
Peak memory 573908 kb
Host smart-83b7c94c-d851-4c8a-a8b3-f0140a2953f3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408863328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_large_delays.2408863328
Directory /workspace/68.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.2704601323
Short name T1906
Test name
Test status
Simulation time 4222325097 ps
CPU time 73.04 seconds
Started Aug 02 08:04:33 PM PDT 24
Finished Aug 02 08:05:46 PM PDT 24
Peak memory 573872 kb
Host smart-4f6be3d7-ffdc-49e6-8eab-1fa9418bb036
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704601323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_slow_rsp.2704601323
Directory /workspace/68.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_smoke_zero_delays.3049238621
Short name T447
Test name
Test status
Simulation time 46563916 ps
CPU time 6.39 seconds
Started Aug 02 08:04:40 PM PDT 24
Finished Aug 02 08:04:47 PM PDT 24
Peak memory 574480 kb
Host smart-de841d58-7624-4025-b17e-dddd44d9e393
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049238621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_zero_delay
s.3049238621
Directory /workspace/68.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_stress_all.3418779173
Short name T2865
Test name
Test status
Simulation time 5645680403 ps
CPU time 205.64 seconds
Started Aug 02 08:04:43 PM PDT 24
Finished Aug 02 08:08:08 PM PDT 24
Peak memory 576044 kb
Host smart-142f98b2-fe1f-49df-ad13-a6d218669e00
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418779173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all.3418779173
Directory /workspace/68.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.3469297223
Short name T2763
Test name
Test status
Simulation time 366741756 ps
CPU time 157.21 seconds
Started Aug 02 08:04:45 PM PDT 24
Finished Aug 02 08:07:23 PM PDT 24
Peak memory 575960 kb
Host smart-1ce86082-5150-4bbf-b9ac-797ecf7bec41
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469297223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all
_with_rand_reset.3469297223
Directory /workspace/68.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.2256244059
Short name T701
Test name
Test status
Simulation time 3620282674 ps
CPU time 465.14 seconds
Started Aug 02 08:04:35 PM PDT 24
Finished Aug 02 08:12:20 PM PDT 24
Peak memory 577864 kb
Host smart-0bea716d-d8b9-4f58-9bd7-31d9198450e5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256244059 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_al
l_with_reset_error.2256244059
Directory /workspace/68.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_unmapped_addr.3660384340
Short name T1626
Test name
Test status
Simulation time 1453951774 ps
CPU time 67.34 seconds
Started Aug 02 08:04:38 PM PDT 24
Finished Aug 02 08:05:45 PM PDT 24
Peak memory 575824 kb
Host smart-dfa4754f-7835-47d0-8966-2bce253b7901
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660384340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_unmapped_addr.3660384340
Directory /workspace/68.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_access_same_device.2156688541
Short name T1878
Test name
Test status
Simulation time 927614976 ps
CPU time 64.47 seconds
Started Aug 02 08:04:48 PM PDT 24
Finished Aug 02 08:05:52 PM PDT 24
Peak memory 575936 kb
Host smart-caccffdd-746c-4b09-b04d-4634a6ce5d9d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156688541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device
.2156688541
Directory /workspace/69.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.1092609859
Short name T838
Test name
Test status
Simulation time 50028319415 ps
CPU time 913.22 seconds
Started Aug 02 08:04:45 PM PDT 24
Finished Aug 02 08:19:58 PM PDT 24
Peak memory 575996 kb
Host smart-3705683a-688e-4099-bc38-639852f4a594
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092609859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_
device_slow_rsp.1092609859
Directory /workspace/69.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.2514679969
Short name T702
Test name
Test status
Simulation time 1401346369 ps
CPU time 56.18 seconds
Started Aug 02 08:04:50 PM PDT 24
Finished Aug 02 08:05:46 PM PDT 24
Peak memory 575784 kb
Host smart-90816ec4-74cf-4e19-b1ad-05880da04a98
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514679969 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_and_unmapped_add
r.2514679969
Directory /workspace/69.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_error_random.624014370
Short name T2684
Test name
Test status
Simulation time 2401178370 ps
CPU time 83.61 seconds
Started Aug 02 08:04:45 PM PDT 24
Finished Aug 02 08:06:09 PM PDT 24
Peak memory 575728 kb
Host smart-65403d9e-4658-437e-9cc8-2dd0a1f06a69
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624014370 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_random.624014370
Directory /workspace/69.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_random.3550248403
Short name T2128
Test name
Test status
Simulation time 257571775 ps
CPU time 22.75 seconds
Started Aug 02 08:04:36 PM PDT 24
Finished Aug 02 08:04:59 PM PDT 24
Peak memory 575800 kb
Host smart-9e739c63-599a-4481-8d96-ed857bbdfa8f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550248403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random.3550248403
Directory /workspace/69.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_random_large_delays.456564456
Short name T2000
Test name
Test status
Simulation time 105616593074 ps
CPU time 1264.44 seconds
Started Aug 02 08:04:48 PM PDT 24
Finished Aug 02 08:25:52 PM PDT 24
Peak memory 575992 kb
Host smart-58b08ef0-e0ed-442b-8e7e-984c541cfa69
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456564456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_large_delays.456564456
Directory /workspace/69.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_random_slow_rsp.350698083
Short name T1479
Test name
Test status
Simulation time 8095312372 ps
CPU time 142.12 seconds
Started Aug 02 08:04:45 PM PDT 24
Finished Aug 02 08:07:07 PM PDT 24
Peak memory 576028 kb
Host smart-4a4df317-fedd-4b57-8362-e1c822753bd5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350698083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_slow_rsp.350698083
Directory /workspace/69.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_random_zero_delays.3289967201
Short name T2118
Test name
Test status
Simulation time 155362518 ps
CPU time 15.89 seconds
Started Aug 02 08:04:52 PM PDT 24
Finished Aug 02 08:05:08 PM PDT 24
Peak memory 575416 kb
Host smart-a6809063-bebf-445b-ab0c-b55a6f5ab67a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289967201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_zero_del
ays.3289967201
Directory /workspace/69.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_same_source.2312510147
Short name T1426
Test name
Test status
Simulation time 526939964 ps
CPU time 17.26 seconds
Started Aug 02 08:04:47 PM PDT 24
Finished Aug 02 08:05:04 PM PDT 24
Peak memory 575840 kb
Host smart-73962ec5-75b4-4fff-90cc-af37c4a6e350
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312510147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_same_source.2312510147
Directory /workspace/69.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_smoke.2651370253
Short name T2821
Test name
Test status
Simulation time 44076390 ps
CPU time 6.39 seconds
Started Aug 02 08:04:47 PM PDT 24
Finished Aug 02 08:04:54 PM PDT 24
Peak memory 573840 kb
Host smart-dba2ac60-0129-4759-a1f4-7608a6719a3c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651370253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke.2651370253
Directory /workspace/69.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_smoke_large_delays.3141315383
Short name T2783
Test name
Test status
Simulation time 8715610518 ps
CPU time 96.25 seconds
Started Aug 02 08:04:46 PM PDT 24
Finished Aug 02 08:06:22 PM PDT 24
Peak memory 573876 kb
Host smart-c707b27a-7a75-42ce-ae78-6a20fc6ac0cf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141315383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_large_delays.3141315383
Directory /workspace/69.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.2296152238
Short name T1774
Test name
Test status
Simulation time 3960461706 ps
CPU time 69.08 seconds
Started Aug 02 08:04:37 PM PDT 24
Finished Aug 02 08:05:46 PM PDT 24
Peak memory 573800 kb
Host smart-23535916-0f99-49ad-94bd-795e7fa59767
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296152238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_slow_rsp.2296152238
Directory /workspace/69.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_smoke_zero_delays.4198071769
Short name T2261
Test name
Test status
Simulation time 42403477 ps
CPU time 6.41 seconds
Started Aug 02 08:04:36 PM PDT 24
Finished Aug 02 08:04:42 PM PDT 24
Peak memory 574564 kb
Host smart-540eca80-33b0-4d57-8f28-ff14991ba7e6
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198071769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_zero_delay
s.4198071769
Directory /workspace/69.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_stress_all.3584581692
Short name T479
Test name
Test status
Simulation time 1612524727 ps
CPU time 136.82 seconds
Started Aug 02 08:04:44 PM PDT 24
Finished Aug 02 08:07:01 PM PDT 24
Peak memory 575980 kb
Host smart-fb6ba21a-141d-47e2-8db9-c5e8c99579b8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584581692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all.3584581692
Directory /workspace/69.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.1566384888
Short name T700
Test name
Test status
Simulation time 10247621991 ps
CPU time 345.16 seconds
Started Aug 02 08:04:52 PM PDT 24
Finished Aug 02 08:10:37 PM PDT 24
Peak memory 576328 kb
Host smart-2927e389-afdc-4d0c-aa5d-edc25aebb1e3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566384888 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_error.1566384888
Directory /workspace/69.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.35490702
Short name T79
Test name
Test status
Simulation time 336088701 ps
CPU time 126.47 seconds
Started Aug 02 08:04:52 PM PDT 24
Finished Aug 02 08:06:58 PM PDT 24
Peak memory 575428 kb
Host smart-f3890c5e-2c24-4f41-835c-862e1d7fbb5f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35490702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_w
ith_rand_reset.35490702
Directory /workspace/69.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.734411111
Short name T895
Test name
Test status
Simulation time 466998530 ps
CPU time 170.26 seconds
Started Aug 02 08:04:45 PM PDT 24
Finished Aug 02 08:07:36 PM PDT 24
Peak memory 576768 kb
Host smart-3e2b4d2c-70d6-4d60-81d7-7ddefca9bac1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734411111 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all
_with_reset_error.734411111
Directory /workspace/69.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.2924903457
Short name T2545
Test name
Test status
Simulation time 52144043 ps
CPU time 8.64 seconds
Started Aug 02 08:04:48 PM PDT 24
Finished Aug 02 08:04:56 PM PDT 24
Peak memory 575920 kb
Host smart-f36e31a1-f08e-41cf-b126-a5d53ac14d32
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924903457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_unmapped_addr.2924903457
Directory /workspace/69.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.1693533604
Short name T396
Test name
Test status
Simulation time 6243619150 ps
CPU time 462.37 seconds
Started Aug 02 07:53:12 PM PDT 24
Finished Aug 02 08:00:55 PM PDT 24
Peak memory 643108 kb
Host smart-40be51b8-4478-41fa-bd91-f235eb3b9e64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693533604 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.chip_csr_mem_rw_with_rand_reset.1693533604
Directory /workspace/7.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.chip_csr_rw.2942618091
Short name T416
Test name
Test status
Simulation time 5898651797 ps
CPU time 565.12 seconds
Started Aug 02 07:53:15 PM PDT 24
Finished Aug 02 08:02:40 PM PDT 24
Peak memory 599348 kb
Host smart-2e3e4944-8b45-46ae-a507-e4fdafb80444
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942618091 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_rw.2942618091
Directory /workspace/7.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.2996262596
Short name T408
Test name
Test status
Simulation time 17008586474 ps
CPU time 2428.47 seconds
Started Aug 02 07:53:00 PM PDT 24
Finished Aug 02 08:33:29 PM PDT 24
Peak memory 593224 kb
Host smart-843cbefd-f91f-4548-992f-5bd5afc234ee
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996262596 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.chip_same_csr_outstanding.2996262596
Directory /workspace/7.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_access_same_device.406167215
Short name T1498
Test name
Test status
Simulation time 2770608028 ps
CPU time 107.83 seconds
Started Aug 02 07:52:58 PM PDT 24
Finished Aug 02 07:54:45 PM PDT 24
Peak memory 575916 kb
Host smart-f1778f30-91c4-48a7-813a-ae3ef79ca21a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406167215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.406167215
Directory /workspace/7.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.651872844
Short name T2199
Test name
Test status
Simulation time 12901132813 ps
CPU time 220.68 seconds
Started Aug 02 07:53:00 PM PDT 24
Finished Aug 02 07:56:41 PM PDT 24
Peak memory 576684 kb
Host smart-4d4d0168-f6a4-4de6-98b9-874dc2045b1c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651872844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_de
vice_slow_rsp.651872844
Directory /workspace/7.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.1646991576
Short name T1757
Test name
Test status
Simulation time 874832443 ps
CPU time 33.71 seconds
Started Aug 02 07:53:14 PM PDT 24
Finished Aug 02 07:53:48 PM PDT 24
Peak memory 575896 kb
Host smart-b35e16f8-3386-4d75-ae67-4ce9725382ae
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646991576 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr
.1646991576
Directory /workspace/7.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_error_random.981410546
Short name T2154
Test name
Test status
Simulation time 1722448315 ps
CPU time 53.59 seconds
Started Aug 02 07:53:12 PM PDT 24
Finished Aug 02 07:54:06 PM PDT 24
Peak memory 575892 kb
Host smart-c76bb960-85f5-4a38-a6f5-d8236fb0158a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981410546 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.981410546
Directory /workspace/7.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_random.2797211251
Short name T514
Test name
Test status
Simulation time 954938785 ps
CPU time 37.9 seconds
Started Aug 02 07:53:01 PM PDT 24
Finished Aug 02 07:53:39 PM PDT 24
Peak memory 575768 kb
Host smart-db6d46bb-f403-4f59-82c5-74831e359ae7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797211251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random.2797211251
Directory /workspace/7.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_random_large_delays.2187601230
Short name T2418
Test name
Test status
Simulation time 19200803886 ps
CPU time 202.33 seconds
Started Aug 02 07:53:00 PM PDT 24
Finished Aug 02 07:56:22 PM PDT 24
Peak memory 576128 kb
Host smart-370c2e14-0c58-4aad-a3c9-0f945d6855aa
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187601230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.2187601230
Directory /workspace/7.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.2787326176
Short name T2271
Test name
Test status
Simulation time 61135365568 ps
CPU time 1095.7 seconds
Started Aug 02 07:52:58 PM PDT 24
Finished Aug 02 08:11:14 PM PDT 24
Peak memory 575980 kb
Host smart-3921a66f-9956-47e4-a8f5-706d7ccc17cf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787326176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.2787326176
Directory /workspace/7.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_random_zero_delays.2586384555
Short name T666
Test name
Test status
Simulation time 458338613 ps
CPU time 38.53 seconds
Started Aug 02 07:53:03 PM PDT 24
Finished Aug 02 07:53:42 PM PDT 24
Peak memory 575900 kb
Host smart-339dc007-d196-44a5-89c6-c3f1ccde2a12
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586384555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_dela
ys.2586384555
Directory /workspace/7.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_same_source.1720656288
Short name T2887
Test name
Test status
Simulation time 55157421 ps
CPU time 7.42 seconds
Started Aug 02 07:53:13 PM PDT 24
Finished Aug 02 07:53:20 PM PDT 24
Peak memory 574452 kb
Host smart-f271df4c-1522-4018-9830-4a3350d9dbcd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720656288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.1720656288
Directory /workspace/7.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_smoke.2683398184
Short name T1809
Test name
Test status
Simulation time 44785785 ps
CPU time 6.39 seconds
Started Aug 02 07:53:00 PM PDT 24
Finished Aug 02 07:53:06 PM PDT 24
Peak memory 573784 kb
Host smart-1d403b23-273b-4be1-acb1-adcf488ffdfd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683398184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.2683398184
Directory /workspace/7.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_smoke_large_delays.1793594972
Short name T1605
Test name
Test status
Simulation time 8609014802 ps
CPU time 96.68 seconds
Started Aug 02 07:53:00 PM PDT 24
Finished Aug 02 07:54:37 PM PDT 24
Peak memory 574556 kb
Host smart-b1b9b9f8-b64c-4a41-94e0-9209071d735b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793594972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.1793594972
Directory /workspace/7.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.2385206416
Short name T2426
Test name
Test status
Simulation time 5191921939 ps
CPU time 83.54 seconds
Started Aug 02 07:52:57 PM PDT 24
Finished Aug 02 07:54:21 PM PDT 24
Peak memory 573872 kb
Host smart-c7f73133-fecd-44bf-b03f-cf567740fbc7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385206416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.2385206416
Directory /workspace/7.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_smoke_zero_delays.310154228
Short name T1563
Test name
Test status
Simulation time 44132777 ps
CPU time 6.06 seconds
Started Aug 02 07:52:59 PM PDT 24
Finished Aug 02 07:53:05 PM PDT 24
Peak memory 573780 kb
Host smart-ec12a49e-788c-4ff0-b23e-a33950705378
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310154228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.
310154228
Directory /workspace/7.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_stress_all.1790560835
Short name T1453
Test name
Test status
Simulation time 218992671 ps
CPU time 10.01 seconds
Started Aug 02 07:53:13 PM PDT 24
Finished Aug 02 07:53:23 PM PDT 24
Peak memory 573932 kb
Host smart-935a867d-246f-4887-ab87-8512b09db9ec
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790560835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.1790560835
Directory /workspace/7.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.3165283461
Short name T902
Test name
Test status
Simulation time 158074776 ps
CPU time 55.42 seconds
Started Aug 02 07:53:10 PM PDT 24
Finished Aug 02 07:54:05 PM PDT 24
Peak memory 575936 kb
Host smart-8fab11f5-329e-4858-b7ca-ed6160dbb47a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165283461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_
with_rand_reset.3165283461
Directory /workspace/7.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.2480591142
Short name T2780
Test name
Test status
Simulation time 301714257 ps
CPU time 111.7 seconds
Started Aug 02 07:53:14 PM PDT 24
Finished Aug 02 07:55:05 PM PDT 24
Peak memory 576740 kb
Host smart-9355ddcf-09df-453d-8b18-b7f6784c408e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480591142 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all
_with_reset_error.2480591142
Directory /workspace/7.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_unmapped_addr.1211656563
Short name T1632
Test name
Test status
Simulation time 134365837 ps
CPU time 8.07 seconds
Started Aug 02 07:53:13 PM PDT 24
Finished Aug 02 07:53:22 PM PDT 24
Peak memory 573952 kb
Host smart-8801390f-c473-4c47-a3df-5161f91871ed
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211656563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.1211656563
Directory /workspace/7.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_access_same_device.4238228627
Short name T1815
Test name
Test status
Simulation time 981447310 ps
CPU time 64.79 seconds
Started Aug 02 08:04:52 PM PDT 24
Finished Aug 02 08:05:57 PM PDT 24
Peak memory 575444 kb
Host smart-29498833-e62c-4e80-8a75-6e3337be7a60
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238228627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device
.4238228627
Directory /workspace/70.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.3712729947
Short name T2924
Test name
Test status
Simulation time 43849127838 ps
CPU time 797.74 seconds
Started Aug 02 08:05:04 PM PDT 24
Finished Aug 02 08:18:21 PM PDT 24
Peak memory 576016 kb
Host smart-5ed0ad2c-49ee-4bdf-af14-9fb458bfbd4e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712729947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_
device_slow_rsp.3712729947
Directory /workspace/70.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.1211407629
Short name T2934
Test name
Test status
Simulation time 287335443 ps
CPU time 32.23 seconds
Started Aug 02 08:04:57 PM PDT 24
Finished Aug 02 08:05:29 PM PDT 24
Peak memory 575980 kb
Host smart-2d9de884-e2dc-401b-be45-f8467f40ac7c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211407629 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_and_unmapped_add
r.1211407629
Directory /workspace/70.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_error_random.610315475
Short name T2051
Test name
Test status
Simulation time 602436862 ps
CPU time 49.17 seconds
Started Aug 02 08:05:00 PM PDT 24
Finished Aug 02 08:05:49 PM PDT 24
Peak memory 575944 kb
Host smart-fbd9ffc8-e683-47ba-bc84-8397df36b57c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610315475 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_random.610315475
Directory /workspace/70.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_random.825690504
Short name T2448
Test name
Test status
Simulation time 437161941 ps
CPU time 17.79 seconds
Started Aug 02 08:04:44 PM PDT 24
Finished Aug 02 08:05:02 PM PDT 24
Peak memory 575848 kb
Host smart-67cbb127-e753-4c1a-a131-54226edc68bd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825690504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random.825690504
Directory /workspace/70.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_random_large_delays.3294228888
Short name T2595
Test name
Test status
Simulation time 30356323471 ps
CPU time 341.66 seconds
Started Aug 02 08:04:45 PM PDT 24
Finished Aug 02 08:10:27 PM PDT 24
Peak memory 576780 kb
Host smart-3d1cf280-9e94-4aee-9b74-dab43c98e7fa
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294228888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_large_delays.3294228888
Directory /workspace/70.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_random_slow_rsp.1867087316
Short name T1830
Test name
Test status
Simulation time 6275516310 ps
CPU time 106.15 seconds
Started Aug 02 08:04:50 PM PDT 24
Finished Aug 02 08:06:36 PM PDT 24
Peak memory 575984 kb
Host smart-b8d16dfc-7aec-4af7-b68d-038bd557bdea
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867087316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_slow_rsp.1867087316
Directory /workspace/70.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.2432915138
Short name T624
Test name
Test status
Simulation time 41336730 ps
CPU time 7.18 seconds
Started Aug 02 08:04:46 PM PDT 24
Finished Aug 02 08:04:53 PM PDT 24
Peak memory 573792 kb
Host smart-adcd0a0c-0cc2-4b32-9108-69c6683b6bf8
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432915138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_zero_del
ays.2432915138
Directory /workspace/70.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_same_source.1944041967
Short name T680
Test name
Test status
Simulation time 403200119 ps
CPU time 27.95 seconds
Started Aug 02 08:04:59 PM PDT 24
Finished Aug 02 08:05:27 PM PDT 24
Peak memory 575748 kb
Host smart-5d18d04b-6376-462c-8c0e-ef5a53ad95e0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944041967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_same_source.1944041967
Directory /workspace/70.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_smoke.2129783348
Short name T1574
Test name
Test status
Simulation time 168675853 ps
CPU time 8.22 seconds
Started Aug 02 08:04:46 PM PDT 24
Finished Aug 02 08:04:54 PM PDT 24
Peak memory 573784 kb
Host smart-f138d27b-3316-4a00-95a5-18c1f537b46c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129783348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke.2129783348
Directory /workspace/70.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_smoke_large_delays.1634236033
Short name T2279
Test name
Test status
Simulation time 6558988389 ps
CPU time 65.13 seconds
Started Aug 02 08:04:47 PM PDT 24
Finished Aug 02 08:05:52 PM PDT 24
Peak memory 573904 kb
Host smart-996a12af-e88c-40df-ac4a-29b31a1ed0fa
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634236033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_large_delays.1634236033
Directory /workspace/70.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.3267365197
Short name T2218
Test name
Test status
Simulation time 4683914064 ps
CPU time 81.01 seconds
Started Aug 02 08:04:47 PM PDT 24
Finished Aug 02 08:06:08 PM PDT 24
Peak memory 574564 kb
Host smart-fc222764-0aa7-49d4-8412-ef1ddf9b6001
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267365197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_slow_rsp.3267365197
Directory /workspace/70.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_smoke_zero_delays.517706022
Short name T2556
Test name
Test status
Simulation time 49606159 ps
CPU time 6.78 seconds
Started Aug 02 08:04:43 PM PDT 24
Finished Aug 02 08:04:50 PM PDT 24
Peak memory 573876 kb
Host smart-c909aaf8-27c9-4ce9-9ff7-f54f016b0ebb
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517706022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_zero_delays
.517706022
Directory /workspace/70.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_stress_all.2007967746
Short name T1610
Test name
Test status
Simulation time 1446640839 ps
CPU time 108.06 seconds
Started Aug 02 08:04:58 PM PDT 24
Finished Aug 02 08:06:47 PM PDT 24
Peak memory 575896 kb
Host smart-fb4e2fff-fbb6-44a5-b51e-d8440f8043f1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007967746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all.2007967746
Directory /workspace/70.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.1491639631
Short name T266
Test name
Test status
Simulation time 122823847 ps
CPU time 30.73 seconds
Started Aug 02 08:04:57 PM PDT 24
Finished Aug 02 08:05:28 PM PDT 24
Peak memory 575892 kb
Host smart-268b768f-a666-47a0-bdfb-138a579b468b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491639631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all
_with_rand_reset.1491639631
Directory /workspace/70.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.3541871758
Short name T1675
Test name
Test status
Simulation time 3501115003 ps
CPU time 309.9 seconds
Started Aug 02 08:04:59 PM PDT 24
Finished Aug 02 08:10:09 PM PDT 24
Peak memory 576020 kb
Host smart-779fcb27-6fc7-437c-a15a-fb0d4b80e820
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541871758 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_al
l_with_reset_error.3541871758
Directory /workspace/70.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.501584535
Short name T644
Test name
Test status
Simulation time 243960986 ps
CPU time 24.62 seconds
Started Aug 02 08:04:58 PM PDT 24
Finished Aug 02 08:05:23 PM PDT 24
Peak memory 575820 kb
Host smart-5344e5fc-0576-41a7-8a39-45c6adf1d880
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501584535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_unmapped_addr.501584535
Directory /workspace/70.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_access_same_device.976745387
Short name T855
Test name
Test status
Simulation time 1019577496 ps
CPU time 40.52 seconds
Started Aug 02 08:05:01 PM PDT 24
Finished Aug 02 08:05:42 PM PDT 24
Peak memory 575952 kb
Host smart-8e308393-2b01-44cc-bb4c-b3cf45192a5e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976745387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device.
976745387
Directory /workspace/71.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.3140018297
Short name T856
Test name
Test status
Simulation time 81880137492 ps
CPU time 1416.71 seconds
Started Aug 02 08:04:56 PM PDT 24
Finished Aug 02 08:28:33 PM PDT 24
Peak memory 576080 kb
Host smart-585df926-9706-49c9-bcde-beca47f626c7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140018297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_
device_slow_rsp.3140018297
Directory /workspace/71.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.2886768106
Short name T2228
Test name
Test status
Simulation time 336294855 ps
CPU time 16.81 seconds
Started Aug 02 08:04:58 PM PDT 24
Finished Aug 02 08:05:15 PM PDT 24
Peak memory 575940 kb
Host smart-6b809bca-cab3-4829-931a-e7093fda1cf7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886768106 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_and_unmapped_add
r.2886768106
Directory /workspace/71.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_error_random.3395549716
Short name T2558
Test name
Test status
Simulation time 1350801245 ps
CPU time 44.02 seconds
Started Aug 02 08:05:01 PM PDT 24
Finished Aug 02 08:05:45 PM PDT 24
Peak memory 575752 kb
Host smart-c6b5186b-4b0b-4107-8924-23d7d46df3ea
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395549716 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_random.3395549716
Directory /workspace/71.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_random.4048045645
Short name T1671
Test name
Test status
Simulation time 1658806699 ps
CPU time 59.07 seconds
Started Aug 02 08:04:58 PM PDT 24
Finished Aug 02 08:05:57 PM PDT 24
Peak memory 575772 kb
Host smart-73ad9c5f-94e0-4937-97be-58b61570bccd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048045645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random.4048045645
Directory /workspace/71.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_random_large_delays.2373546090
Short name T1501
Test name
Test status
Simulation time 31756547397 ps
CPU time 322.17 seconds
Started Aug 02 08:04:59 PM PDT 24
Finished Aug 02 08:10:22 PM PDT 24
Peak memory 575884 kb
Host smart-6a8dac76-543b-4ea3-98fe-bc9e61e65750
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373546090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_large_delays.2373546090
Directory /workspace/71.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_random_slow_rsp.2944219144
Short name T2858
Test name
Test status
Simulation time 32926459414 ps
CPU time 595.01 seconds
Started Aug 02 08:04:57 PM PDT 24
Finished Aug 02 08:14:53 PM PDT 24
Peak memory 576844 kb
Host smart-d6502c6d-9096-4281-9f93-3daf954ee912
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944219144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_slow_rsp.2944219144
Directory /workspace/71.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.143731839
Short name T2826
Test name
Test status
Simulation time 97477733 ps
CPU time 10.66 seconds
Started Aug 02 08:04:57 PM PDT 24
Finished Aug 02 08:05:08 PM PDT 24
Peak memory 575868 kb
Host smart-b2237a6f-ff19-400f-ac97-89729ab32baf
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143731839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_zero_dela
ys.143731839
Directory /workspace/71.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_same_source.1949096454
Short name T1566
Test name
Test status
Simulation time 369806119 ps
CPU time 27.86 seconds
Started Aug 02 08:04:57 PM PDT 24
Finished Aug 02 08:05:25 PM PDT 24
Peak memory 575920 kb
Host smart-692158af-7b1b-4e10-9ede-931299fcaaa2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949096454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_same_source.1949096454
Directory /workspace/71.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_smoke.2725812416
Short name T2091
Test name
Test status
Simulation time 164847289 ps
CPU time 7.07 seconds
Started Aug 02 08:04:57 PM PDT 24
Finished Aug 02 08:05:04 PM PDT 24
Peak memory 573896 kb
Host smart-62bd324d-2cce-4878-b4d6-5157a2fee192
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725812416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke.2725812416
Directory /workspace/71.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_smoke_large_delays.4186784450
Short name T2668
Test name
Test status
Simulation time 9259763848 ps
CPU time 92.43 seconds
Started Aug 02 08:05:01 PM PDT 24
Finished Aug 02 08:06:34 PM PDT 24
Peak memory 573932 kb
Host smart-e7da156e-fe8d-4b96-bf6f-a8e6230ba7e5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186784450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_large_delays.4186784450
Directory /workspace/71.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.3436562461
Short name T1431
Test name
Test status
Simulation time 5263387381 ps
CPU time 90.69 seconds
Started Aug 02 08:04:58 PM PDT 24
Finished Aug 02 08:06:29 PM PDT 24
Peak memory 573844 kb
Host smart-57a7519d-410e-4767-8c00-1e2895e1fe54
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436562461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_slow_rsp.3436562461
Directory /workspace/71.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_smoke_zero_delays.3257401763
Short name T1885
Test name
Test status
Simulation time 53936665 ps
CPU time 6.49 seconds
Started Aug 02 08:04:58 PM PDT 24
Finished Aug 02 08:05:04 PM PDT 24
Peak memory 574488 kb
Host smart-3313ddc9-ff1a-4e49-a07e-1bf79de14e80
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257401763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_zero_delay
s.3257401763
Directory /workspace/71.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_stress_all.360915571
Short name T640
Test name
Test status
Simulation time 1053993769 ps
CPU time 104.35 seconds
Started Aug 02 08:05:11 PM PDT 24
Finished Aug 02 08:06:55 PM PDT 24
Peak memory 576004 kb
Host smart-1604f18a-fafc-4cf5-b039-bcb8c8cf1fff
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360915571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all.360915571
Directory /workspace/71.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.223294329
Short name T1764
Test name
Test status
Simulation time 610905064 ps
CPU time 25.16 seconds
Started Aug 02 08:05:13 PM PDT 24
Finished Aug 02 08:05:38 PM PDT 24
Peak memory 576008 kb
Host smart-f30105f5-1819-4890-8b88-60f5d61e9f87
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223294329 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_error.223294329
Directory /workspace/71.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.3516104984
Short name T2172
Test name
Test status
Simulation time 238803470 ps
CPU time 86.14 seconds
Started Aug 02 08:05:10 PM PDT 24
Finished Aug 02 08:06:36 PM PDT 24
Peak memory 576712 kb
Host smart-dc680c1a-85a8-47a7-921a-eaee08267f1b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516104984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all
_with_rand_reset.3516104984
Directory /workspace/71.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.3373082221
Short name T2808
Test name
Test status
Simulation time 1634596018 ps
CPU time 178.41 seconds
Started Aug 02 08:05:13 PM PDT 24
Finished Aug 02 08:08:11 PM PDT 24
Peak memory 576756 kb
Host smart-109c5f84-39c7-4880-abcd-5b6d54af30c9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373082221 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_al
l_with_reset_error.3373082221
Directory /workspace/71.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_unmapped_addr.2515417865
Short name T2317
Test name
Test status
Simulation time 899638221 ps
CPU time 38.42 seconds
Started Aug 02 08:05:24 PM PDT 24
Finished Aug 02 08:06:03 PM PDT 24
Peak memory 575832 kb
Host smart-e37d9ed0-4b87-42b1-83f8-659540eed364
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515417865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_unmapped_addr.2515417865
Directory /workspace/71.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_access_same_device.1513480101
Short name T1929
Test name
Test status
Simulation time 2780133434 ps
CPU time 100.13 seconds
Started Aug 02 08:05:11 PM PDT 24
Finished Aug 02 08:06:51 PM PDT 24
Peak memory 575892 kb
Host smart-acb30e06-f1e0-497a-886d-7add0a83d461
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513480101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device
.1513480101
Directory /workspace/72.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.2373908736
Short name T1683
Test name
Test status
Simulation time 1281717214 ps
CPU time 50.6 seconds
Started Aug 02 08:05:13 PM PDT 24
Finished Aug 02 08:06:04 PM PDT 24
Peak memory 575844 kb
Host smart-6adb152e-04ee-4c85-8d62-7a1dfcf6ede8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373908736 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_and_unmapped_add
r.2373908736
Directory /workspace/72.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_error_random.71668799
Short name T2583
Test name
Test status
Simulation time 325723245 ps
CPU time 27.49 seconds
Started Aug 02 08:05:10 PM PDT 24
Finished Aug 02 08:05:37 PM PDT 24
Peak memory 575904 kb
Host smart-2a527b6b-ad22-4bf6-86b1-ed0d6be4f61a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71668799 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_random.71668799
Directory /workspace/72.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_random.261217912
Short name T2612
Test name
Test status
Simulation time 151791115 ps
CPU time 14.27 seconds
Started Aug 02 08:05:10 PM PDT 24
Finished Aug 02 08:05:24 PM PDT 24
Peak memory 575912 kb
Host smart-6401e4f2-03ef-4a1a-87e2-be450b7862ce
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261217912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random.261217912
Directory /workspace/72.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_random_large_delays.3893511069
Short name T582
Test name
Test status
Simulation time 70916842835 ps
CPU time 790.94 seconds
Started Aug 02 08:05:10 PM PDT 24
Finished Aug 02 08:18:21 PM PDT 24
Peak memory 576000 kb
Host smart-d7cc034a-d190-4bc5-a708-52ac73e9f491
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893511069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_large_delays.3893511069
Directory /workspace/72.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_random_slow_rsp.489278052
Short name T2561
Test name
Test status
Simulation time 9869388075 ps
CPU time 178.23 seconds
Started Aug 02 08:05:13 PM PDT 24
Finished Aug 02 08:08:11 PM PDT 24
Peak memory 575852 kb
Host smart-b2c98194-c7f2-42c4-b524-b515caf371e5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489278052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_slow_rsp.489278052
Directory /workspace/72.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.3018648061
Short name T2061
Test name
Test status
Simulation time 462147326 ps
CPU time 38.57 seconds
Started Aug 02 08:05:13 PM PDT 24
Finished Aug 02 08:05:52 PM PDT 24
Peak memory 575844 kb
Host smart-43a90988-8ac7-44ee-a992-427f03c11d78
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018648061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_zero_del
ays.3018648061
Directory /workspace/72.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_same_source.2221090025
Short name T612
Test name
Test status
Simulation time 351770833 ps
CPU time 27.78 seconds
Started Aug 02 08:05:10 PM PDT 24
Finished Aug 02 08:05:38 PM PDT 24
Peak memory 575796 kb
Host smart-d58160f9-4d26-4a72-bf0b-2499902f3452
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221090025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_same_source.2221090025
Directory /workspace/72.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_smoke.1434551040
Short name T2671
Test name
Test status
Simulation time 157778325 ps
CPU time 7.75 seconds
Started Aug 02 08:05:09 PM PDT 24
Finished Aug 02 08:05:17 PM PDT 24
Peak memory 573880 kb
Host smart-6ec546a1-7954-40ac-aea4-ba20c242fa34
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434551040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke.1434551040
Directory /workspace/72.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.2411227627
Short name T1491
Test name
Test status
Simulation time 8803934540 ps
CPU time 91.92 seconds
Started Aug 02 08:05:11 PM PDT 24
Finished Aug 02 08:06:43 PM PDT 24
Peak memory 574620 kb
Host smart-6804851d-aa1e-4a55-ba0f-a1a9a9a71c39
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411227627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_large_delays.2411227627
Directory /workspace/72.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.2684045582
Short name T2078
Test name
Test status
Simulation time 4577692729 ps
CPU time 75.83 seconds
Started Aug 02 08:05:09 PM PDT 24
Finished Aug 02 08:06:25 PM PDT 24
Peak memory 574600 kb
Host smart-ca33dc16-00bd-46d3-99b7-92e895376f54
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684045582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_slow_rsp.2684045582
Directory /workspace/72.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_smoke_zero_delays.1197143176
Short name T1497
Test name
Test status
Simulation time 45092875 ps
CPU time 6.15 seconds
Started Aug 02 08:05:09 PM PDT 24
Finished Aug 02 08:05:16 PM PDT 24
Peak memory 573768 kb
Host smart-f396e8ce-b26d-452e-9e06-c579cbbb63fe
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197143176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_zero_delay
s.1197143176
Directory /workspace/72.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_stress_all.2099989557
Short name T2092
Test name
Test status
Simulation time 843978200 ps
CPU time 36.47 seconds
Started Aug 02 08:05:10 PM PDT 24
Finished Aug 02 08:05:47 PM PDT 24
Peak memory 575988 kb
Host smart-0fbf8e00-fa59-4cde-919e-af44d8d77b64
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099989557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all.2099989557
Directory /workspace/72.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_error.415682512
Short name T2225
Test name
Test status
Simulation time 9960621371 ps
CPU time 322.71 seconds
Started Aug 02 08:05:10 PM PDT 24
Finished Aug 02 08:10:33 PM PDT 24
Peak memory 576064 kb
Host smart-c11256cc-291f-49f1-990f-4f3c563feb97
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415682512 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_error.415682512
Directory /workspace/72.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.1762211587
Short name T2086
Test name
Test status
Simulation time 3351012914 ps
CPU time 470.28 seconds
Started Aug 02 08:05:13 PM PDT 24
Finished Aug 02 08:13:03 PM PDT 24
Peak memory 576816 kb
Host smart-c9e94fdd-cacf-40a4-b009-71761670974b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762211587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all
_with_rand_reset.1762211587
Directory /workspace/72.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.358374841
Short name T1783
Test name
Test status
Simulation time 1927782530 ps
CPU time 245.08 seconds
Started Aug 02 08:05:22 PM PDT 24
Finished Aug 02 08:09:27 PM PDT 24
Peak memory 576764 kb
Host smart-46a082b8-3e00-48cf-8531-b71d8720f42d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358374841 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all
_with_reset_error.358374841
Directory /workspace/72.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_unmapped_addr.539257918
Short name T2751
Test name
Test status
Simulation time 20225507 ps
CPU time 5.56 seconds
Started Aug 02 08:05:09 PM PDT 24
Finished Aug 02 08:05:15 PM PDT 24
Peak memory 574516 kb
Host smart-99e6a951-0a63-4973-a6c5-ef836f72e35d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539257918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_unmapped_addr.539257918
Directory /workspace/72.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_access_same_device.1937056192
Short name T2197
Test name
Test status
Simulation time 372904597 ps
CPU time 28.06 seconds
Started Aug 02 08:05:31 PM PDT 24
Finished Aug 02 08:05:59 PM PDT 24
Peak memory 575972 kb
Host smart-dfa94d0d-0aba-45d7-94dc-a3dfcdabb446
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937056192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device
.1937056192
Directory /workspace/73.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.2209517935
Short name T2055
Test name
Test status
Simulation time 13048474568 ps
CPU time 217.78 seconds
Started Aug 02 08:05:25 PM PDT 24
Finished Aug 02 08:09:03 PM PDT 24
Peak memory 576040 kb
Host smart-0b1eeea2-d877-4d14-859d-0d5a193438a8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209517935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_
device_slow_rsp.2209517935
Directory /workspace/73.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.1679679765
Short name T1961
Test name
Test status
Simulation time 655745210 ps
CPU time 24.46 seconds
Started Aug 02 08:05:24 PM PDT 24
Finished Aug 02 08:05:48 PM PDT 24
Peak memory 575952 kb
Host smart-d044e7e4-c3a3-4afe-bbc5-ded948853f1d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679679765 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_and_unmapped_add
r.1679679765
Directory /workspace/73.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_error_random.138752997
Short name T1515
Test name
Test status
Simulation time 376451830 ps
CPU time 14.39 seconds
Started Aug 02 08:05:30 PM PDT 24
Finished Aug 02 08:05:45 PM PDT 24
Peak memory 575728 kb
Host smart-265a5b95-f80c-4dfc-b3de-96b2ed7c4698
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138752997 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_random.138752997
Directory /workspace/73.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_random.2963644674
Short name T1714
Test name
Test status
Simulation time 632953964 ps
CPU time 24.25 seconds
Started Aug 02 08:05:30 PM PDT 24
Finished Aug 02 08:05:54 PM PDT 24
Peak memory 575960 kb
Host smart-bbd4ba27-5edc-4457-8c98-93ef5fcde5b1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963644674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random.2963644674
Directory /workspace/73.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_random_large_delays.1528469505
Short name T1541
Test name
Test status
Simulation time 34204677597 ps
CPU time 369.35 seconds
Started Aug 02 08:05:31 PM PDT 24
Finished Aug 02 08:11:41 PM PDT 24
Peak memory 575900 kb
Host smart-52f8ca1d-a8ea-44bf-b9cd-f1161ecbd8c0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528469505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_large_delays.1528469505
Directory /workspace/73.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_random_slow_rsp.1385464423
Short name T2264
Test name
Test status
Simulation time 26808696302 ps
CPU time 419.95 seconds
Started Aug 02 08:05:26 PM PDT 24
Finished Aug 02 08:12:26 PM PDT 24
Peak memory 575880 kb
Host smart-54594474-9215-4762-911a-1d44cbeb36d7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385464423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_slow_rsp.1385464423
Directory /workspace/73.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_random_zero_delays.2494805669
Short name T2289
Test name
Test status
Simulation time 493818744 ps
CPU time 39.92 seconds
Started Aug 02 08:05:24 PM PDT 24
Finished Aug 02 08:06:04 PM PDT 24
Peak memory 575904 kb
Host smart-01ab0842-4a54-4cdf-b216-e49a5b5f9061
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494805669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_zero_del
ays.2494805669
Directory /workspace/73.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_same_source.3149449088
Short name T1760
Test name
Test status
Simulation time 428077354 ps
CPU time 32.09 seconds
Started Aug 02 08:05:30 PM PDT 24
Finished Aug 02 08:06:02 PM PDT 24
Peak memory 575784 kb
Host smart-f7a787bc-5b8e-4fb2-b4df-1c5ec5432dff
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149449088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_same_source.3149449088
Directory /workspace/73.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_smoke.4216296052
Short name T2035
Test name
Test status
Simulation time 115459095 ps
CPU time 6.96 seconds
Started Aug 02 08:05:23 PM PDT 24
Finished Aug 02 08:05:30 PM PDT 24
Peak memory 574484 kb
Host smart-80710343-1db7-425f-ab31-508d036289ea
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216296052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke.4216296052
Directory /workspace/73.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.1207799609
Short name T1613
Test name
Test status
Simulation time 8254513364 ps
CPU time 84.67 seconds
Started Aug 02 08:05:25 PM PDT 24
Finished Aug 02 08:06:49 PM PDT 24
Peak memory 574652 kb
Host smart-5a9649a9-8594-47ed-9a88-756692cb2e24
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207799609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_large_delays.1207799609
Directory /workspace/73.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.2657154590
Short name T1829
Test name
Test status
Simulation time 3752311237 ps
CPU time 67.97 seconds
Started Aug 02 08:05:23 PM PDT 24
Finished Aug 02 08:06:31 PM PDT 24
Peak memory 573912 kb
Host smart-c3f15efe-e71f-4bd8-bbc3-7dc6aaf5a35e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657154590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_slow_rsp.2657154590
Directory /workspace/73.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_smoke_zero_delays.1102493980
Short name T2287
Test name
Test status
Simulation time 51380013 ps
CPU time 6.06 seconds
Started Aug 02 08:05:26 PM PDT 24
Finished Aug 02 08:05:32 PM PDT 24
Peak memory 574532 kb
Host smart-7c9f007e-6344-4a9b-87a7-c6cab3ee4313
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102493980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_zero_delay
s.1102493980
Directory /workspace/73.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_stress_all.1837339765
Short name T2145
Test name
Test status
Simulation time 1655829892 ps
CPU time 128.57 seconds
Started Aug 02 08:05:26 PM PDT 24
Finished Aug 02 08:07:35 PM PDT 24
Peak memory 576712 kb
Host smart-d0bb2073-0062-45ad-b640-3baeaaa83c77
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837339765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all.1837339765
Directory /workspace/73.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.1804413301
Short name T2329
Test name
Test status
Simulation time 2930833647 ps
CPU time 107.46 seconds
Started Aug 02 08:05:22 PM PDT 24
Finished Aug 02 08:07:10 PM PDT 24
Peak memory 576132 kb
Host smart-eb365c27-e30d-460f-afd7-a43247a5e3ba
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804413301 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_error.1804413301
Directory /workspace/73.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.4034921825
Short name T598
Test name
Test status
Simulation time 674074696 ps
CPU time 220.52 seconds
Started Aug 02 08:05:31 PM PDT 24
Finished Aug 02 08:09:12 PM PDT 24
Peak memory 576776 kb
Host smart-f782053f-6802-4e65-944e-c78e5dec59f3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034921825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all
_with_rand_reset.4034921825
Directory /workspace/73.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.1262907746
Short name T852
Test name
Test status
Simulation time 8109498862 ps
CPU time 431.9 seconds
Started Aug 02 08:05:24 PM PDT 24
Finished Aug 02 08:12:37 PM PDT 24
Peak memory 575960 kb
Host smart-c2ad0655-b126-4b74-989f-50512404251e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262907746 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_al
l_with_reset_error.1262907746
Directory /workspace/73.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_unmapped_addr.3644353278
Short name T2578
Test name
Test status
Simulation time 609673206 ps
CPU time 24.16 seconds
Started Aug 02 08:05:25 PM PDT 24
Finished Aug 02 08:05:49 PM PDT 24
Peak memory 575952 kb
Host smart-a3924870-4bff-4931-91e0-cee6863a97f0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644353278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_unmapped_addr.3644353278
Directory /workspace/73.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_access_same_device.3469013793
Short name T2344
Test name
Test status
Simulation time 1278925454 ps
CPU time 54.96 seconds
Started Aug 02 08:05:39 PM PDT 24
Finished Aug 02 08:06:34 PM PDT 24
Peak memory 576044 kb
Host smart-882ddad5-5bed-4607-862e-91c66a9e04c0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469013793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device
.3469013793
Directory /workspace/74.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.179901258
Short name T2727
Test name
Test status
Simulation time 141958573470 ps
CPU time 2423.79 seconds
Started Aug 02 08:05:36 PM PDT 24
Finished Aug 02 08:46:00 PM PDT 24
Peak memory 576120 kb
Host smart-86729547-566f-4fdc-9e59-1321fa31e893
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179901258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_d
evice_slow_rsp.179901258
Directory /workspace/74.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.1994523541
Short name T2063
Test name
Test status
Simulation time 191512606 ps
CPU time 23.22 seconds
Started Aug 02 08:05:40 PM PDT 24
Finished Aug 02 08:06:03 PM PDT 24
Peak memory 576000 kb
Host smart-fa677116-fa0d-48cc-9333-69ab1d83daa4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994523541 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_and_unmapped_add
r.1994523541
Directory /workspace/74.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_error_random.2780553516
Short name T1539
Test name
Test status
Simulation time 1237719187 ps
CPU time 42.79 seconds
Started Aug 02 08:05:41 PM PDT 24
Finished Aug 02 08:06:24 PM PDT 24
Peak memory 575896 kb
Host smart-b21e5eec-42e7-4ac6-88bd-11f3e10c2c26
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780553516 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_random.2780553516
Directory /workspace/74.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_random.148495128
Short name T2333
Test name
Test status
Simulation time 516472662 ps
CPU time 47 seconds
Started Aug 02 08:05:39 PM PDT 24
Finished Aug 02 08:06:26 PM PDT 24
Peak memory 575956 kb
Host smart-82277186-293d-434e-9e62-36254ec5282c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148495128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random.148495128
Directory /workspace/74.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_random_large_delays.1750217813
Short name T1786
Test name
Test status
Simulation time 75633378949 ps
CPU time 879.19 seconds
Started Aug 02 08:05:39 PM PDT 24
Finished Aug 02 08:20:19 PM PDT 24
Peak memory 576060 kb
Host smart-088da8ab-cb25-4246-af56-9a47d9d5a6fb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750217813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_large_delays.1750217813
Directory /workspace/74.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_random_slow_rsp.496410854
Short name T2637
Test name
Test status
Simulation time 15964042070 ps
CPU time 290.02 seconds
Started Aug 02 08:05:39 PM PDT 24
Finished Aug 02 08:10:29 PM PDT 24
Peak memory 575908 kb
Host smart-f9e8fbed-6c2a-49e3-93a8-9a8534563b0b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496410854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_slow_rsp.496410854
Directory /workspace/74.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_random_zero_delays.449740234
Short name T1932
Test name
Test status
Simulation time 127514064 ps
CPU time 12.53 seconds
Started Aug 02 08:05:37 PM PDT 24
Finished Aug 02 08:05:50 PM PDT 24
Peak memory 575856 kb
Host smart-d2b01a13-468a-4802-afc6-92d0a02d04bc
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449740234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_zero_dela
ys.449740234
Directory /workspace/74.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_same_source.3195733169
Short name T605
Test name
Test status
Simulation time 233024081 ps
CPU time 20.41 seconds
Started Aug 02 08:05:39 PM PDT 24
Finished Aug 02 08:05:59 PM PDT 24
Peak memory 575896 kb
Host smart-17e6de8b-ba9d-4e21-b3b1-3c5b0a37f25b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195733169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_same_source.3195733169
Directory /workspace/74.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_smoke.695673815
Short name T2142
Test name
Test status
Simulation time 190762491 ps
CPU time 8.86 seconds
Started Aug 02 08:05:30 PM PDT 24
Finished Aug 02 08:05:39 PM PDT 24
Peak memory 574504 kb
Host smart-9ae9dc47-fbed-49c6-96cb-cc78b8be6d6f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695673815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke.695673815
Directory /workspace/74.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_smoke_large_delays.2824489106
Short name T2268
Test name
Test status
Simulation time 9422228722 ps
CPU time 98.08 seconds
Started Aug 02 08:05:21 PM PDT 24
Finished Aug 02 08:06:59 PM PDT 24
Peak memory 573992 kb
Host smart-3f45d0ac-7ab6-4cf5-b0d3-67a0153cfb95
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824489106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_large_delays.2824489106
Directory /workspace/74.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.4102997641
Short name T503
Test name
Test status
Simulation time 6010851216 ps
CPU time 96.72 seconds
Started Aug 02 08:05:37 PM PDT 24
Finished Aug 02 08:07:14 PM PDT 24
Peak memory 573920 kb
Host smart-a9d9eefd-2f94-42d1-bb36-ad0e7351320f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102997641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_slow_rsp.4102997641
Directory /workspace/74.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_smoke_zero_delays.1499388553
Short name T1948
Test name
Test status
Simulation time 50360657 ps
CPU time 6.44 seconds
Started Aug 02 08:05:31 PM PDT 24
Finished Aug 02 08:05:37 PM PDT 24
Peak memory 573852 kb
Host smart-dd6c1e65-aa8d-4086-8995-3cf1ebac9f69
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499388553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_zero_delay
s.1499388553
Directory /workspace/74.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_stress_all.272710662
Short name T2635
Test name
Test status
Simulation time 1436460510 ps
CPU time 115.19 seconds
Started Aug 02 08:05:39 PM PDT 24
Finished Aug 02 08:07:34 PM PDT 24
Peak memory 575904 kb
Host smart-8683f491-fa20-4841-bd76-fcf977bb3c80
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272710662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all.272710662
Directory /workspace/74.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.2925739415
Short name T1627
Test name
Test status
Simulation time 139604886 ps
CPU time 13.82 seconds
Started Aug 02 08:05:37 PM PDT 24
Finished Aug 02 08:05:51 PM PDT 24
Peak memory 575660 kb
Host smart-e854371e-c451-4e49-8865-2c2e1ad3c924
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925739415 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_error.2925739415
Directory /workspace/74.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.1891405284
Short name T2409
Test name
Test status
Simulation time 4596176495 ps
CPU time 283.27 seconds
Started Aug 02 08:05:38 PM PDT 24
Finished Aug 02 08:10:21 PM PDT 24
Peak memory 576024 kb
Host smart-1985a337-a992-43ad-b35b-82f834aa163b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891405284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all
_with_rand_reset.1891405284
Directory /workspace/74.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.1289613399
Short name T2542
Test name
Test status
Simulation time 1694650519 ps
CPU time 236.55 seconds
Started Aug 02 08:05:37 PM PDT 24
Finished Aug 02 08:09:33 PM PDT 24
Peak memory 576724 kb
Host smart-d81eb711-82a8-43ad-b7f6-d1c36696d7f9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289613399 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_al
l_with_reset_error.1289613399
Directory /workspace/74.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_unmapped_addr.1892163900
Short name T1825
Test name
Test status
Simulation time 194764730 ps
CPU time 22.99 seconds
Started Aug 02 08:05:39 PM PDT 24
Finished Aug 02 08:06:02 PM PDT 24
Peak memory 575788 kb
Host smart-9d7fe5ed-c75e-4b6b-b764-7a4e35164fe6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892163900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_unmapped_addr.1892163900
Directory /workspace/74.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_access_same_device.3344314507
Short name T2714
Test name
Test status
Simulation time 1614784032 ps
CPU time 77.09 seconds
Started Aug 02 08:05:39 PM PDT 24
Finished Aug 02 08:06:56 PM PDT 24
Peak memory 575916 kb
Host smart-399b6c6a-1383-4b0f-8f54-c5651f0185d0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344314507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device
.3344314507
Directory /workspace/75.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.3613641212
Short name T875
Test name
Test status
Simulation time 59420390454 ps
CPU time 1056.03 seconds
Started Aug 02 08:05:38 PM PDT 24
Finished Aug 02 08:23:14 PM PDT 24
Peak memory 575916 kb
Host smart-25f92e75-bd88-4788-b069-ce6453f80c79
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613641212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_
device_slow_rsp.3613641212
Directory /workspace/75.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.4010642604
Short name T1881
Test name
Test status
Simulation time 230701420 ps
CPU time 25.45 seconds
Started Aug 02 08:05:50 PM PDT 24
Finished Aug 02 08:06:16 PM PDT 24
Peak memory 576044 kb
Host smart-7a474747-c4e8-428c-8d0b-e852a88a1dfb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010642604 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_and_unmapped_add
r.4010642604
Directory /workspace/75.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_error_random.2537760184
Short name T1549
Test name
Test status
Simulation time 2521923870 ps
CPU time 90.62 seconds
Started Aug 02 08:05:52 PM PDT 24
Finished Aug 02 08:07:23 PM PDT 24
Peak memory 575956 kb
Host smart-608dab82-42a9-45b1-bbdf-6e684b7ee0eb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537760184 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_random.2537760184
Directory /workspace/75.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_random.1332901551
Short name T2888
Test name
Test status
Simulation time 77812486 ps
CPU time 6.56 seconds
Started Aug 02 08:05:39 PM PDT 24
Finished Aug 02 08:05:45 PM PDT 24
Peak memory 574524 kb
Host smart-4f496b03-af42-4ad8-8bbd-a5cc96b83615
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332901551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random.1332901551
Directory /workspace/75.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.1141986692
Short name T599
Test name
Test status
Simulation time 108992937993 ps
CPU time 1152.69 seconds
Started Aug 02 08:05:39 PM PDT 24
Finished Aug 02 08:24:52 PM PDT 24
Peak memory 576024 kb
Host smart-bdeaf8d6-5e12-4d91-b3e5-857d14886bb2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141986692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_large_delays.1141986692
Directory /workspace/75.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.3093677687
Short name T2074
Test name
Test status
Simulation time 7934193306 ps
CPU time 136.4 seconds
Started Aug 02 08:05:38 PM PDT 24
Finished Aug 02 08:07:55 PM PDT 24
Peak memory 575844 kb
Host smart-7637e67f-95c7-4f5f-923f-f484f7d07c8c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093677687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_slow_rsp.3093677687
Directory /workspace/75.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_random_zero_delays.1955879318
Short name T504
Test name
Test status
Simulation time 410583858 ps
CPU time 34.52 seconds
Started Aug 02 08:05:42 PM PDT 24
Finished Aug 02 08:06:16 PM PDT 24
Peak memory 575936 kb
Host smart-f99a1492-7457-4afc-917d-ba9cb927d5f2
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955879318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_zero_del
ays.1955879318
Directory /workspace/75.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_same_source.3406699184
Short name T2643
Test name
Test status
Simulation time 35007671 ps
CPU time 5.79 seconds
Started Aug 02 08:05:46 PM PDT 24
Finished Aug 02 08:05:52 PM PDT 24
Peak memory 574600 kb
Host smart-e909d76c-db2a-4ca6-b9e3-770d7fbc4ebc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406699184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_same_source.3406699184
Directory /workspace/75.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_smoke.1875593200
Short name T1788
Test name
Test status
Simulation time 46698633 ps
CPU time 6.34 seconds
Started Aug 02 08:05:41 PM PDT 24
Finished Aug 02 08:05:48 PM PDT 24
Peak memory 573880 kb
Host smart-9c6f13b3-ef92-4ebf-b5d6-142955e99afa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875593200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke.1875593200
Directory /workspace/75.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.2018752266
Short name T2490
Test name
Test status
Simulation time 8425644116 ps
CPU time 83.01 seconds
Started Aug 02 08:05:39 PM PDT 24
Finished Aug 02 08:07:03 PM PDT 24
Peak memory 574728 kb
Host smart-a4d624d4-9ecf-4199-bf61-bbdce2622f90
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018752266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_large_delays.2018752266
Directory /workspace/75.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.95322834
Short name T1524
Test name
Test status
Simulation time 5687133705 ps
CPU time 98.33 seconds
Started Aug 02 08:05:39 PM PDT 24
Finished Aug 02 08:07:17 PM PDT 24
Peak memory 573924 kb
Host smart-97e14b28-9463-4864-bb59-7dc857cafb3f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95322834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_slow_rsp.95322834
Directory /workspace/75.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_smoke_zero_delays.1752916885
Short name T1901
Test name
Test status
Simulation time 45761319 ps
CPU time 6.19 seconds
Started Aug 02 08:05:37 PM PDT 24
Finished Aug 02 08:05:44 PM PDT 24
Peak memory 573808 kb
Host smart-0d7fb7c0-0d0d-4bc5-a2ad-7507def104bd
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752916885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_zero_delay
s.1752916885
Directory /workspace/75.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_stress_all.1511970847
Short name T1735
Test name
Test status
Simulation time 8832906283 ps
CPU time 286.2 seconds
Started Aug 02 08:05:53 PM PDT 24
Finished Aug 02 08:10:39 PM PDT 24
Peak memory 576188 kb
Host smart-3086a53a-dd75-4fb7-bc2c-9501870df0f2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511970847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all.1511970847
Directory /workspace/75.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.1646919023
Short name T2185
Test name
Test status
Simulation time 6909521073 ps
CPU time 242.04 seconds
Started Aug 02 08:05:52 PM PDT 24
Finished Aug 02 08:09:55 PM PDT 24
Peak memory 576112 kb
Host smart-54314310-8dc8-4adb-97f4-05e622965ad0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646919023 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_error.1646919023
Directory /workspace/75.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.2770112323
Short name T2907
Test name
Test status
Simulation time 2497364338 ps
CPU time 310.75 seconds
Started Aug 02 08:05:52 PM PDT 24
Finished Aug 02 08:11:03 PM PDT 24
Peak memory 576116 kb
Host smart-34c807f0-fc15-4332-b806-d2cb300289d4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770112323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all
_with_rand_reset.2770112323
Directory /workspace/75.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.285837767
Short name T2781
Test name
Test status
Simulation time 6636680473 ps
CPU time 330.24 seconds
Started Aug 02 08:06:03 PM PDT 24
Finished Aug 02 08:11:33 PM PDT 24
Peak memory 576872 kb
Host smart-b8477f61-6497-4ae1-9f02-ab874884f939
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285837767 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all
_with_reset_error.285837767
Directory /workspace/75.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.2481651405
Short name T2413
Test name
Test status
Simulation time 1016355772 ps
CPU time 47.52 seconds
Started Aug 02 08:05:49 PM PDT 24
Finished Aug 02 08:06:36 PM PDT 24
Peak memory 576080 kb
Host smart-93ae1e90-3180-47d5-a39d-985ddf395b88
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481651405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_unmapped_addr.2481651405
Directory /workspace/75.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_access_same_device.583734482
Short name T2652
Test name
Test status
Simulation time 718637807 ps
CPU time 53.95 seconds
Started Aug 02 08:06:03 PM PDT 24
Finished Aug 02 08:06:57 PM PDT 24
Peak memory 575972 kb
Host smart-38094d0b-fbd6-4f1f-947b-39ef7ad84df6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583734482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device.
583734482
Directory /workspace/76.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.3098712902
Short name T767
Test name
Test status
Simulation time 62327260508 ps
CPU time 1040.7 seconds
Started Aug 02 08:05:49 PM PDT 24
Finished Aug 02 08:23:10 PM PDT 24
Peak memory 576048 kb
Host smart-0e283c4c-e7c8-455b-9488-3e5ed02ab7aa
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098712902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_
device_slow_rsp.3098712902
Directory /workspace/76.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.3948469261
Short name T2877
Test name
Test status
Simulation time 846140542 ps
CPU time 32.16 seconds
Started Aug 02 08:06:03 PM PDT 24
Finished Aug 02 08:06:35 PM PDT 24
Peak memory 575964 kb
Host smart-3999870a-30fd-4db0-944d-7c65b5a0652a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948469261 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_and_unmapped_add
r.3948469261
Directory /workspace/76.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_error_random.4173749386
Short name T1680
Test name
Test status
Simulation time 1765993264 ps
CPU time 59.33 seconds
Started Aug 02 08:05:49 PM PDT 24
Finished Aug 02 08:06:48 PM PDT 24
Peak memory 576056 kb
Host smart-63a9bb62-0314-452b-b273-c919a026766e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173749386 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_random.4173749386
Directory /workspace/76.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_random.1024162425
Short name T572
Test name
Test status
Simulation time 317758255 ps
CPU time 13.95 seconds
Started Aug 02 08:05:50 PM PDT 24
Finished Aug 02 08:06:04 PM PDT 24
Peak memory 575788 kb
Host smart-b596d0aa-219e-4fb0-876f-c35098d0c403
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024162425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random.1024162425
Directory /workspace/76.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_random_large_delays.3716119051
Short name T478
Test name
Test status
Simulation time 88093170567 ps
CPU time 1015.67 seconds
Started Aug 02 08:05:50 PM PDT 24
Finished Aug 02 08:22:46 PM PDT 24
Peak memory 576028 kb
Host smart-5bcad9d6-fed3-408a-b5d2-b8e382b407bd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716119051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_large_delays.3716119051
Directory /workspace/76.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_random_slow_rsp.1747967603
Short name T460
Test name
Test status
Simulation time 30196341713 ps
CPU time 530.02 seconds
Started Aug 02 08:05:51 PM PDT 24
Finished Aug 02 08:14:42 PM PDT 24
Peak memory 576848 kb
Host smart-a1952708-5d12-4b39-a47b-bd19b9300ff8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747967603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_slow_rsp.1747967603
Directory /workspace/76.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.1476112407
Short name T1944
Test name
Test status
Simulation time 174002377 ps
CPU time 19.47 seconds
Started Aug 02 08:05:51 PM PDT 24
Finished Aug 02 08:06:11 PM PDT 24
Peak memory 575896 kb
Host smart-5a28efee-67b3-4e65-b9b6-c7d17b877233
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476112407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_zero_del
ays.1476112407
Directory /workspace/76.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_same_source.252916508
Short name T2904
Test name
Test status
Simulation time 1095847798 ps
CPU time 34.25 seconds
Started Aug 02 08:05:50 PM PDT 24
Finished Aug 02 08:06:24 PM PDT 24
Peak memory 575676 kb
Host smart-21e9fe73-e518-405a-bef5-e3f8de94fad5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252916508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_same_source.252916508
Directory /workspace/76.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_smoke.3650247114
Short name T2510
Test name
Test status
Simulation time 177473919 ps
CPU time 8.17 seconds
Started Aug 02 08:05:50 PM PDT 24
Finished Aug 02 08:05:58 PM PDT 24
Peak memory 574516 kb
Host smart-e38a6461-367b-46ad-b152-d55dce343953
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650247114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke.3650247114
Directory /workspace/76.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_smoke_large_delays.4126976126
Short name T2398
Test name
Test status
Simulation time 8773894959 ps
CPU time 89.42 seconds
Started Aug 02 08:05:52 PM PDT 24
Finished Aug 02 08:07:22 PM PDT 24
Peak memory 574604 kb
Host smart-18895d3e-daa1-4ee3-b1b5-0b1223d949b0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126976126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_large_delays.4126976126
Directory /workspace/76.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.2575046638
Short name T2360
Test name
Test status
Simulation time 5112602607 ps
CPU time 85.69 seconds
Started Aug 02 08:05:51 PM PDT 24
Finished Aug 02 08:07:16 PM PDT 24
Peak memory 574040 kb
Host smart-4f64efdc-2256-424d-b82b-557c00571d49
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575046638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_slow_rsp.2575046638
Directory /workspace/76.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_smoke_zero_delays.4030683824
Short name T2081
Test name
Test status
Simulation time 55079451 ps
CPU time 6.61 seconds
Started Aug 02 08:06:03 PM PDT 24
Finished Aug 02 08:06:09 PM PDT 24
Peak memory 574564 kb
Host smart-55ed1538-4385-4bcd-bcb3-a399ff1955be
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030683824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_zero_delay
s.4030683824
Directory /workspace/76.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_stress_all.1115269251
Short name T1934
Test name
Test status
Simulation time 153571391 ps
CPU time 18.97 seconds
Started Aug 02 08:06:03 PM PDT 24
Finished Aug 02 08:06:22 PM PDT 24
Peak memory 576060 kb
Host smart-5700fc5c-9662-46d3-b8f6-2f4cae04b5a8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115269251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all.1115269251
Directory /workspace/76.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.2773580318
Short name T1843
Test name
Test status
Simulation time 4300439656 ps
CPU time 322.33 seconds
Started Aug 02 08:05:50 PM PDT 24
Finished Aug 02 08:11:12 PM PDT 24
Peak memory 575996 kb
Host smart-a32515eb-8d47-4410-bc1c-80a1baea1905
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773580318 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_error.2773580318
Directory /workspace/76.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.3272471808
Short name T584
Test name
Test status
Simulation time 2677617251 ps
CPU time 197.48 seconds
Started Aug 02 08:05:54 PM PDT 24
Finished Aug 02 08:09:11 PM PDT 24
Peak memory 576824 kb
Host smart-d934dc23-f3fb-48f8-9f06-43a01a4cce2c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272471808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all
_with_rand_reset.3272471808
Directory /workspace/76.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_unmapped_addr.4170839744
Short name T2522
Test name
Test status
Simulation time 236367689 ps
CPU time 24.61 seconds
Started Aug 02 08:05:50 PM PDT 24
Finished Aug 02 08:06:15 PM PDT 24
Peak memory 575832 kb
Host smart-888d195b-b091-4c0c-ad4f-ee236ebce615
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170839744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_unmapped_addr.4170839744
Directory /workspace/76.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_access_same_device.1534982327
Short name T2624
Test name
Test status
Simulation time 1070809344 ps
CPU time 69.89 seconds
Started Aug 02 08:06:06 PM PDT 24
Finished Aug 02 08:07:16 PM PDT 24
Peak memory 575836 kb
Host smart-53db1361-1826-47b7-b067-6292b24a2f04
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534982327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device
.1534982327
Directory /workspace/77.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.2782794086
Short name T2682
Test name
Test status
Simulation time 101961606943 ps
CPU time 1923.15 seconds
Started Aug 02 08:06:00 PM PDT 24
Finished Aug 02 08:38:04 PM PDT 24
Peak memory 575988 kb
Host smart-5d940c09-4fb0-46d7-8517-284c4dbb3f06
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782794086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_
device_slow_rsp.2782794086
Directory /workspace/77.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.340171236
Short name T2436
Test name
Test status
Simulation time 953750864 ps
CPU time 38.41 seconds
Started Aug 02 08:06:02 PM PDT 24
Finished Aug 02 08:06:41 PM PDT 24
Peak memory 575832 kb
Host smart-861d6af0-8b71-4250-b093-7bfbc3e0ec00
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340171236 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_and_unmapped_addr
.340171236
Directory /workspace/77.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_error_random.652170933
Short name T2593
Test name
Test status
Simulation time 1498210974 ps
CPU time 45.96 seconds
Started Aug 02 08:06:02 PM PDT 24
Finished Aug 02 08:06:48 PM PDT 24
Peak memory 575684 kb
Host smart-cfa4cb08-7029-423f-98e8-36107b8be635
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652170933 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_random.652170933
Directory /workspace/77.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_random.3280106011
Short name T2452
Test name
Test status
Simulation time 1607499222 ps
CPU time 57.23 seconds
Started Aug 02 08:06:03 PM PDT 24
Finished Aug 02 08:07:00 PM PDT 24
Peak memory 575940 kb
Host smart-dea9d161-74a9-47f1-89ef-e7ca4fe638e3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280106011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random.3280106011
Directory /workspace/77.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_random_large_delays.2307720601
Short name T2747
Test name
Test status
Simulation time 82626707402 ps
CPU time 908.94 seconds
Started Aug 02 08:05:58 PM PDT 24
Finished Aug 02 08:21:07 PM PDT 24
Peak memory 576044 kb
Host smart-a50cd20c-cb02-47c3-a2b3-1266de76abe1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307720601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_large_delays.2307720601
Directory /workspace/77.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_random_slow_rsp.2860574778
Short name T2365
Test name
Test status
Simulation time 14594937072 ps
CPU time 229.67 seconds
Started Aug 02 08:06:05 PM PDT 24
Finished Aug 02 08:09:55 PM PDT 24
Peak memory 576004 kb
Host smart-b178dc9e-392e-4b21-be6c-683189de8052
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860574778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_slow_rsp.2860574778
Directory /workspace/77.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.563415545
Short name T2696
Test name
Test status
Simulation time 284996885 ps
CPU time 23.61 seconds
Started Aug 02 08:06:05 PM PDT 24
Finished Aug 02 08:06:29 PM PDT 24
Peak memory 575824 kb
Host smart-d954909d-022f-44cd-804a-d17bfb6f2766
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563415545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_zero_dela
ys.563415545
Directory /workspace/77.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_same_source.2144016917
Short name T1532
Test name
Test status
Simulation time 556046095 ps
CPU time 19.06 seconds
Started Aug 02 08:05:59 PM PDT 24
Finished Aug 02 08:06:18 PM PDT 24
Peak memory 575784 kb
Host smart-ca5a4178-53d6-42fd-8af3-d6ad8ee111ad
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144016917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_same_source.2144016917
Directory /workspace/77.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_smoke.2014859686
Short name T2523
Test name
Test status
Simulation time 56154927 ps
CPU time 6.79 seconds
Started Aug 02 08:05:53 PM PDT 24
Finished Aug 02 08:06:00 PM PDT 24
Peak memory 574540 kb
Host smart-ec884413-198c-4870-a7e5-a371ad2f1def
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014859686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke.2014859686
Directory /workspace/77.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_smoke_large_delays.75806660
Short name T2202
Test name
Test status
Simulation time 8306696747 ps
CPU time 84.08 seconds
Started Aug 02 08:05:52 PM PDT 24
Finished Aug 02 08:07:16 PM PDT 24
Peak memory 574596 kb
Host smart-ba2a0bc3-7315-4594-afb9-db204aba090c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75806660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_large_delays.75806660
Directory /workspace/77.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.485038239
Short name T1535
Test name
Test status
Simulation time 5618019142 ps
CPU time 96.21 seconds
Started Aug 02 08:05:51 PM PDT 24
Finished Aug 02 08:07:27 PM PDT 24
Peak memory 574656 kb
Host smart-45887918-3bd8-497b-aecd-4394529fe57f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485038239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_slow_rsp.485038239
Directory /workspace/77.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_smoke_zero_delays.1855233275
Short name T1792
Test name
Test status
Simulation time 46501706 ps
CPU time 5.83 seconds
Started Aug 02 08:05:54 PM PDT 24
Finished Aug 02 08:06:00 PM PDT 24
Peak memory 574472 kb
Host smart-9fbb6cf9-2af1-48b7-a2bb-ac3aaf156b26
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855233275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_zero_delay
s.1855233275
Directory /workspace/77.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.3091937352
Short name T449
Test name
Test status
Simulation time 12448798504 ps
CPU time 353.33 seconds
Started Aug 02 08:06:00 PM PDT 24
Finished Aug 02 08:11:53 PM PDT 24
Peak memory 576152 kb
Host smart-20315c7d-4623-4831-b312-838a0a65875b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091937352 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_error.3091937352
Directory /workspace/77.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.3880933414
Short name T669
Test name
Test status
Simulation time 385377765 ps
CPU time 126.8 seconds
Started Aug 02 08:05:59 PM PDT 24
Finished Aug 02 08:08:06 PM PDT 24
Peak memory 575908 kb
Host smart-c53d8390-adb8-4bc3-bde1-f21881cb9ff8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880933414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all
_with_rand_reset.3880933414
Directory /workspace/77.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.1704253825
Short name T909
Test name
Test status
Simulation time 11160092876 ps
CPU time 489.49 seconds
Started Aug 02 08:06:00 PM PDT 24
Finished Aug 02 08:14:10 PM PDT 24
Peak memory 576832 kb
Host smart-9bee7668-1bc9-49b2-a791-2ade35d78106
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704253825 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_al
l_with_reset_error.1704253825
Directory /workspace/77.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.1834220375
Short name T1485
Test name
Test status
Simulation time 26054709 ps
CPU time 5.82 seconds
Started Aug 02 08:06:02 PM PDT 24
Finished Aug 02 08:06:08 PM PDT 24
Peak memory 573816 kb
Host smart-a17d1469-892f-4a9d-b13a-c291c620db60
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834220375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_unmapped_addr.1834220375
Directory /workspace/77.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_access_same_device.4141398020
Short name T876
Test name
Test status
Simulation time 1932189646 ps
CPU time 77.16 seconds
Started Aug 02 08:06:01 PM PDT 24
Finished Aug 02 08:07:18 PM PDT 24
Peak memory 575844 kb
Host smart-cd4c6662-a7af-4201-9b74-d827e172afb0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141398020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device
.4141398020
Directory /workspace/78.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.406803925
Short name T2008
Test name
Test status
Simulation time 1530457985 ps
CPU time 59.58 seconds
Started Aug 02 08:06:13 PM PDT 24
Finished Aug 02 08:07:13 PM PDT 24
Peak memory 575776 kb
Host smart-f3523cc0-50a6-4022-a835-f316e79a5744
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406803925 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_and_unmapped_addr
.406803925
Directory /workspace/78.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_error_random.2422258410
Short name T1595
Test name
Test status
Simulation time 173734083 ps
CPU time 17.88 seconds
Started Aug 02 08:06:13 PM PDT 24
Finished Aug 02 08:06:31 PM PDT 24
Peak memory 575632 kb
Host smart-2d9cc7b8-5535-4bd2-893f-8bee93ac968b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422258410 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_random.2422258410
Directory /workspace/78.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_random.239032549
Short name T2263
Test name
Test status
Simulation time 358032981 ps
CPU time 31.4 seconds
Started Aug 02 08:06:02 PM PDT 24
Finished Aug 02 08:06:33 PM PDT 24
Peak memory 575932 kb
Host smart-1b05007f-c195-42fb-8a65-55fb102205ff
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239032549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random.239032549
Directory /workspace/78.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_random_large_delays.1069846713
Short name T2807
Test name
Test status
Simulation time 9975262969 ps
CPU time 101.56 seconds
Started Aug 02 08:05:59 PM PDT 24
Finished Aug 02 08:07:40 PM PDT 24
Peak memory 575856 kb
Host smart-a9ddf833-dda8-4fea-aa57-15f3555191bd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069846713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_large_delays.1069846713
Directory /workspace/78.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_random_slow_rsp.379704470
Short name T2840
Test name
Test status
Simulation time 40993989340 ps
CPU time 666.13 seconds
Started Aug 02 08:05:59 PM PDT 24
Finished Aug 02 08:17:05 PM PDT 24
Peak memory 576020 kb
Host smart-ba5eb570-4e21-47d1-a1e8-d5b86c569d41
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379704470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_slow_rsp.379704470
Directory /workspace/78.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.993716651
Short name T2819
Test name
Test status
Simulation time 480281616 ps
CPU time 39.78 seconds
Started Aug 02 08:06:03 PM PDT 24
Finished Aug 02 08:06:43 PM PDT 24
Peak memory 575816 kb
Host smart-14ad7491-ea91-4b7d-b672-30b73b4624ab
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993716651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_zero_dela
ys.993716651
Directory /workspace/78.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_same_source.1894286786
Short name T2003
Test name
Test status
Simulation time 385745589 ps
CPU time 28.28 seconds
Started Aug 02 08:06:14 PM PDT 24
Finished Aug 02 08:06:42 PM PDT 24
Peak memory 575820 kb
Host smart-33e2a599-1af7-4b59-8b59-02802615ee62
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894286786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_same_source.1894286786
Directory /workspace/78.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_smoke.3180399313
Short name T2339
Test name
Test status
Simulation time 51158167 ps
CPU time 6.73 seconds
Started Aug 02 08:06:00 PM PDT 24
Finished Aug 02 08:06:07 PM PDT 24
Peak memory 573872 kb
Host smart-f408dd36-8189-4ba4-bba2-45ca97149856
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180399313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke.3180399313
Directory /workspace/78.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_smoke_large_delays.1842102569
Short name T2412
Test name
Test status
Simulation time 9531390742 ps
CPU time 92.12 seconds
Started Aug 02 08:05:59 PM PDT 24
Finished Aug 02 08:07:31 PM PDT 24
Peak memory 573992 kb
Host smart-69fc5360-d308-40b9-a9d0-0a644de4b281
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842102569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_large_delays.1842102569
Directory /workspace/78.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.756213428
Short name T2526
Test name
Test status
Simulation time 5751738216 ps
CPU time 102.28 seconds
Started Aug 02 08:06:00 PM PDT 24
Finished Aug 02 08:07:43 PM PDT 24
Peak memory 574540 kb
Host smart-112c24b8-ebf2-46f5-ae6e-39087dba54c7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756213428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_slow_rsp.756213428
Directory /workspace/78.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_smoke_zero_delays.855253806
Short name T707
Test name
Test status
Simulation time 38888914 ps
CPU time 5.88 seconds
Started Aug 02 08:06:00 PM PDT 24
Finished Aug 02 08:06:06 PM PDT 24
Peak memory 573820 kb
Host smart-b5057371-b369-4e4d-8584-8fca1b8ebfc9
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855253806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_zero_delays
.855253806
Directory /workspace/78.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_stress_all.544550098
Short name T2429
Test name
Test status
Simulation time 850602791 ps
CPU time 74.51 seconds
Started Aug 02 08:06:14 PM PDT 24
Finished Aug 02 08:07:28 PM PDT 24
Peak memory 575936 kb
Host smart-72491139-2fdc-4876-82b0-7b59a81a5ce4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544550098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all.544550098
Directory /workspace/78.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.938022071
Short name T2331
Test name
Test status
Simulation time 1585370986 ps
CPU time 142.32 seconds
Started Aug 02 08:06:14 PM PDT 24
Finished Aug 02 08:08:36 PM PDT 24
Peak memory 576716 kb
Host smart-ace3e33b-24ec-41a4-b2e8-ffc88feb6a38
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938022071 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_error.938022071
Directory /workspace/78.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.1810804895
Short name T2779
Test name
Test status
Simulation time 1419882737 ps
CPU time 128.04 seconds
Started Aug 02 08:06:13 PM PDT 24
Finished Aug 02 08:08:21 PM PDT 24
Peak memory 575992 kb
Host smart-0088a850-df1a-4c92-8cec-4e041f14d312
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810804895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all
_with_rand_reset.1810804895
Directory /workspace/78.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.1825401321
Short name T901
Test name
Test status
Simulation time 230249054 ps
CPU time 45.83 seconds
Started Aug 02 08:06:16 PM PDT 24
Finished Aug 02 08:07:02 PM PDT 24
Peak memory 576156 kb
Host smart-ab7a77df-065d-40e4-859d-af31bc3a04d8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825401321 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_al
l_with_reset_error.1825401321
Directory /workspace/78.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_unmapped_addr.3322761122
Short name T2023
Test name
Test status
Simulation time 1180704307 ps
CPU time 49.83 seconds
Started Aug 02 08:06:11 PM PDT 24
Finished Aug 02 08:07:01 PM PDT 24
Peak memory 575884 kb
Host smart-d08ff41c-205c-40c9-800b-05924e0036b5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322761122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_unmapped_addr.3322761122
Directory /workspace/78.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_access_same_device.2825241221
Short name T492
Test name
Test status
Simulation time 794585128 ps
CPU time 27.58 seconds
Started Aug 02 08:06:16 PM PDT 24
Finished Aug 02 08:06:44 PM PDT 24
Peak memory 575984 kb
Host smart-f723798f-df77-4ff4-8179-d5c84b64dbf0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825241221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device
.2825241221
Directory /workspace/79.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.3613783129
Short name T879
Test name
Test status
Simulation time 53725564943 ps
CPU time 925.45 seconds
Started Aug 02 08:06:13 PM PDT 24
Finished Aug 02 08:21:39 PM PDT 24
Peak memory 575904 kb
Host smart-6cf80e72-e2fd-46fe-b29b-74984bf00f5d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613783129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_
device_slow_rsp.3613783129
Directory /workspace/79.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.3766498374
Short name T1654
Test name
Test status
Simulation time 203818340 ps
CPU time 24.82 seconds
Started Aug 02 08:06:28 PM PDT 24
Finished Aug 02 08:06:53 PM PDT 24
Peak memory 575948 kb
Host smart-fa5a58fa-2d61-40e9-a74b-ffe4f98d5aec
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766498374 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_and_unmapped_add
r.3766498374
Directory /workspace/79.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_error_random.325147836
Short name T2380
Test name
Test status
Simulation time 447258120 ps
CPU time 32.32 seconds
Started Aug 02 08:06:29 PM PDT 24
Finished Aug 02 08:07:01 PM PDT 24
Peak memory 575960 kb
Host smart-427a3209-4f38-4518-864b-c9683226bf37
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325147836 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_random.325147836
Directory /workspace/79.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_random.1308721440
Short name T2248
Test name
Test status
Simulation time 485662663 ps
CPU time 38.75 seconds
Started Aug 02 08:06:12 PM PDT 24
Finished Aug 02 08:06:51 PM PDT 24
Peak memory 576016 kb
Host smart-22a47337-19ae-480a-9b16-e719495ff7e3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308721440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random.1308721440
Directory /workspace/79.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_random_large_delays.606402595
Short name T551
Test name
Test status
Simulation time 94457960510 ps
CPU time 1031.56 seconds
Started Aug 02 08:06:13 PM PDT 24
Finished Aug 02 08:23:24 PM PDT 24
Peak memory 575932 kb
Host smart-91827c00-79ab-4052-88c9-bbc2aa5c3220
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606402595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_large_delays.606402595
Directory /workspace/79.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_random_slow_rsp.1588455361
Short name T1448
Test name
Test status
Simulation time 18922284889 ps
CPU time 330.67 seconds
Started Aug 02 08:06:13 PM PDT 24
Finished Aug 02 08:11:43 PM PDT 24
Peak memory 575892 kb
Host smart-4d2438bd-f73c-4539-9417-1b7d08ee052a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588455361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_slow_rsp.1588455361
Directory /workspace/79.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_random_zero_delays.1679998198
Short name T628
Test name
Test status
Simulation time 318138413 ps
CPU time 26 seconds
Started Aug 02 08:06:16 PM PDT 24
Finished Aug 02 08:06:42 PM PDT 24
Peak memory 575816 kb
Host smart-84a8f50f-dac8-4d23-9ab6-6502b04cb15f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679998198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_zero_del
ays.1679998198
Directory /workspace/79.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_same_source.2202400668
Short name T1794
Test name
Test status
Simulation time 435081283 ps
CPU time 15 seconds
Started Aug 02 08:06:29 PM PDT 24
Finished Aug 02 08:06:44 PM PDT 24
Peak memory 575664 kb
Host smart-2151c5fc-fd47-4fb1-be42-c2ccf2eb9829
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202400668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_same_source.2202400668
Directory /workspace/79.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_smoke.643824288
Short name T2299
Test name
Test status
Simulation time 217854125 ps
CPU time 8.55 seconds
Started Aug 02 08:06:15 PM PDT 24
Finished Aug 02 08:06:24 PM PDT 24
Peak memory 574452 kb
Host smart-37ab0b56-a261-4633-bf2a-a0bbe167e845
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643824288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke.643824288
Directory /workspace/79.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.1946631071
Short name T2600
Test name
Test status
Simulation time 7327543275 ps
CPU time 72.3 seconds
Started Aug 02 08:06:14 PM PDT 24
Finished Aug 02 08:07:27 PM PDT 24
Peak memory 574676 kb
Host smart-cd57576e-d14c-4298-9643-5589eeb43ef9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946631071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_large_delays.1946631071
Directory /workspace/79.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.689195387
Short name T1939
Test name
Test status
Simulation time 3679555728 ps
CPU time 61.65 seconds
Started Aug 02 08:06:11 PM PDT 24
Finished Aug 02 08:07:13 PM PDT 24
Peak memory 574524 kb
Host smart-c601c49a-a52e-460f-bbcd-32c2d3023140
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689195387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_slow_rsp.689195387
Directory /workspace/79.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.3777083885
Short name T1771
Test name
Test status
Simulation time 36312168 ps
CPU time 5.68 seconds
Started Aug 02 08:06:14 PM PDT 24
Finished Aug 02 08:06:20 PM PDT 24
Peak memory 573816 kb
Host smart-877d9035-cdb0-4ab5-8dbe-477c3c0ee149
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777083885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_zero_delay
s.3777083885
Directory /workspace/79.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_stress_all.1449342925
Short name T2870
Test name
Test status
Simulation time 1924115816 ps
CPU time 149.57 seconds
Started Aug 02 08:06:31 PM PDT 24
Finished Aug 02 08:09:01 PM PDT 24
Peak memory 576036 kb
Host smart-542fe3c7-fe34-4940-91f2-a11230995a8c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449342925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all.1449342925
Directory /workspace/79.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.840334885
Short name T1946
Test name
Test status
Simulation time 882326648 ps
CPU time 70.17 seconds
Started Aug 02 08:06:30 PM PDT 24
Finished Aug 02 08:07:40 PM PDT 24
Peak memory 576140 kb
Host smart-ca7a047f-c8f0-4c1d-8da9-7664f9309700
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840334885 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_error.840334885
Directory /workspace/79.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.2016189267
Short name T2571
Test name
Test status
Simulation time 4807958197 ps
CPU time 311.83 seconds
Started Aug 02 08:06:29 PM PDT 24
Finished Aug 02 08:11:41 PM PDT 24
Peak memory 576784 kb
Host smart-b9f647db-66b2-4417-9425-75a309feeac4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016189267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all
_with_rand_reset.2016189267
Directory /workspace/79.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.2415598149
Short name T888
Test name
Test status
Simulation time 279548384 ps
CPU time 73.7 seconds
Started Aug 02 08:06:29 PM PDT 24
Finished Aug 02 08:07:43 PM PDT 24
Peak memory 576708 kb
Host smart-bc782159-23d6-4517-9762-8d5713bd6fa5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415598149 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_al
l_with_reset_error.2415598149
Directory /workspace/79.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_unmapped_addr.4110740323
Short name T487
Test name
Test status
Simulation time 1276856963 ps
CPU time 52.5 seconds
Started Aug 02 08:06:32 PM PDT 24
Finished Aug 02 08:07:25 PM PDT 24
Peak memory 575816 kb
Host smart-4b68f724-c5f9-486c-8eae-4107c1ac39f1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110740323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_unmapped_addr.4110740323
Directory /workspace/79.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.782623886
Short name T1772
Test name
Test status
Simulation time 5782023464 ps
CPU time 359.94 seconds
Started Aug 02 07:53:45 PM PDT 24
Finished Aug 02 07:59:45 PM PDT 24
Peak memory 643756 kb
Host smart-2bb3722f-3acc-4c46-8bda-9052232882f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782623886 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.chip_csr_mem_rw_with_rand_reset.782623886
Directory /workspace/8.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.chip_csr_rw.1790228000
Short name T451
Test name
Test status
Simulation time 5589052280 ps
CPU time 527.98 seconds
Started Aug 02 07:53:32 PM PDT 24
Finished Aug 02 08:02:20 PM PDT 24
Peak memory 599028 kb
Host smart-0491ccd9-72bf-42cd-92c9-04e8936066ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790228000 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_csr_rw.1790228000
Directory /workspace/8.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.2551936458
Short name T441
Test name
Test status
Simulation time 29468026018 ps
CPU time 3214.94 seconds
Started Aug 02 07:53:11 PM PDT 24
Finished Aug 02 08:46:47 PM PDT 24
Peak memory 593632 kb
Host smart-e5af8854-1945-43e4-a30b-165ba51daffd
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551936458 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.chip_same_csr_outstanding.2551936458
Directory /workspace/8.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_access_same_device.1415965223
Short name T2011
Test name
Test status
Simulation time 310202060 ps
CPU time 12.97 seconds
Started Aug 02 07:53:27 PM PDT 24
Finished Aug 02 07:53:40 PM PDT 24
Peak memory 573800 kb
Host smart-2df1d7dc-23d7-4417-8295-f1a87233ae18
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415965223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.
1415965223
Directory /workspace/8.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.449966933
Short name T2445
Test name
Test status
Simulation time 141489125076 ps
CPU time 2296.08 seconds
Started Aug 02 07:53:31 PM PDT 24
Finished Aug 02 08:31:47 PM PDT 24
Peak memory 575996 kb
Host smart-2077a213-7443-4ca4-aaee-78835cb383ac
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449966933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_de
vice_slow_rsp.449966933
Directory /workspace/8.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.339852367
Short name T1643
Test name
Test status
Simulation time 1374151782 ps
CPU time 48.95 seconds
Started Aug 02 07:53:29 PM PDT 24
Finished Aug 02 07:54:18 PM PDT 24
Peak memory 576016 kb
Host smart-e552fa2b-da0b-4dcb-b639-6201b766db6e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339852367 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.
339852367
Directory /workspace/8.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_error_random.3785737102
Short name T2163
Test name
Test status
Simulation time 2331130862 ps
CPU time 71.76 seconds
Started Aug 02 07:53:29 PM PDT 24
Finished Aug 02 07:54:40 PM PDT 24
Peak memory 575984 kb
Host smart-711df951-92c3-45ac-9cf5-ff6279ef7f5e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785737102 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.3785737102
Directory /workspace/8.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_random.3847097826
Short name T2235
Test name
Test status
Simulation time 170181616 ps
CPU time 15.45 seconds
Started Aug 02 07:53:31 PM PDT 24
Finished Aug 02 07:53:46 PM PDT 24
Peak memory 575904 kb
Host smart-896be327-8984-4497-8bc9-6f039ed4251b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847097826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random.3847097826
Directory /workspace/8.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_random_large_delays.1713601443
Short name T2739
Test name
Test status
Simulation time 57621845476 ps
CPU time 582.3 seconds
Started Aug 02 07:53:31 PM PDT 24
Finished Aug 02 08:03:14 PM PDT 24
Peak memory 575900 kb
Host smart-08a69212-c0fd-485f-9fa8-33cadc0fe954
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713601443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.1713601443
Directory /workspace/8.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.1761972114
Short name T571
Test name
Test status
Simulation time 56832587438 ps
CPU time 944.25 seconds
Started Aug 02 07:53:36 PM PDT 24
Finished Aug 02 08:09:20 PM PDT 24
Peak memory 576056 kb
Host smart-79d0f953-5d38-46ae-b222-d4966695f7f6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761972114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.1761972114
Directory /workspace/8.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.994981155
Short name T2194
Test name
Test status
Simulation time 214920485 ps
CPU time 19.71 seconds
Started Aug 02 07:53:30 PM PDT 24
Finished Aug 02 07:53:49 PM PDT 24
Peak memory 575900 kb
Host smart-7d999f30-c686-4ec2-89e4-d678a036bd3f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994981155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delay
s.994981155
Directory /workspace/8.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_same_source.293301896
Short name T78
Test name
Test status
Simulation time 658364565 ps
CPU time 19.67 seconds
Started Aug 02 07:53:37 PM PDT 24
Finished Aug 02 07:53:57 PM PDT 24
Peak memory 575864 kb
Host smart-f81c26c3-9890-41ed-9dda-b314dbbfc5b2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293301896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.293301896
Directory /workspace/8.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_smoke.1781135946
Short name T1461
Test name
Test status
Simulation time 185121827 ps
CPU time 8.53 seconds
Started Aug 02 07:53:18 PM PDT 24
Finished Aug 02 07:53:26 PM PDT 24
Peak memory 573932 kb
Host smart-2b1b5530-4b2a-47b8-b104-5e4d6dd5975a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781135946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.1781135946
Directory /workspace/8.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_smoke_large_delays.1937238922
Short name T2278
Test name
Test status
Simulation time 7060654782 ps
CPU time 72.95 seconds
Started Aug 02 07:53:18 PM PDT 24
Finished Aug 02 07:54:31 PM PDT 24
Peak memory 574732 kb
Host smart-e5e1aa5c-347c-4f2e-a7fb-eccbe16620de
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937238922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.1937238922
Directory /workspace/8.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.1193634999
Short name T534
Test name
Test status
Simulation time 5018147696 ps
CPU time 82.98 seconds
Started Aug 02 07:53:12 PM PDT 24
Finished Aug 02 07:54:35 PM PDT 24
Peak memory 574656 kb
Host smart-7b67b0e7-bd58-4084-ba84-a86a4ce29abe
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193634999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.1193634999
Directory /workspace/8.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_smoke_zero_delays.3296793996
Short name T1801
Test name
Test status
Simulation time 59611582 ps
CPU time 6.44 seconds
Started Aug 02 07:53:12 PM PDT 24
Finished Aug 02 07:53:19 PM PDT 24
Peak memory 573832 kb
Host smart-ddd743dd-4eb0-400c-a61c-25c23bfa5563
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296793996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays
.3296793996
Directory /workspace/8.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_stress_all.3440196410
Short name T1750
Test name
Test status
Simulation time 14744256297 ps
CPU time 563.67 seconds
Started Aug 02 07:53:30 PM PDT 24
Finished Aug 02 08:02:53 PM PDT 24
Peak memory 576820 kb
Host smart-2f39ed4a-eceb-40ab-b1d9-7d6c08586cfe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440196410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.3440196410
Directory /workspace/8.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.960934597
Short name T2882
Test name
Test status
Simulation time 4376604040 ps
CPU time 315.76 seconds
Started Aug 02 07:53:31 PM PDT 24
Finished Aug 02 07:58:47 PM PDT 24
Peak memory 576836 kb
Host smart-55cb86de-cf68-4a3a-abdb-3ff426a5f71f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960934597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.960934597
Directory /workspace/8.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.3429970763
Short name T2773
Test name
Test status
Simulation time 4467413444 ps
CPU time 505.81 seconds
Started Aug 02 07:53:34 PM PDT 24
Finished Aug 02 08:02:00 PM PDT 24
Peak memory 580164 kb
Host smart-37328b32-7356-4634-8595-5b84f7a99a0a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429970763 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all
_with_reset_error.3429970763
Directory /workspace/8.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.4079771161
Short name T2440
Test name
Test status
Simulation time 511664368 ps
CPU time 22.57 seconds
Started Aug 02 07:53:32 PM PDT 24
Finished Aug 02 07:53:55 PM PDT 24
Peak memory 575976 kb
Host smart-e360c245-ddc3-4d48-a899-3a2c6bca0242
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079771161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.4079771161
Directory /workspace/8.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_access_same_device.1313252361
Short name T2723
Test name
Test status
Simulation time 3294369569 ps
CPU time 121 seconds
Started Aug 02 08:06:32 PM PDT 24
Finished Aug 02 08:08:33 PM PDT 24
Peak memory 575900 kb
Host smart-99ebeec5-5c70-4c06-82e6-22586d342634
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313252361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device
.1313252361
Directory /workspace/80.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.2539645557
Short name T2645
Test name
Test status
Simulation time 81007778894 ps
CPU time 1407.05 seconds
Started Aug 02 08:06:28 PM PDT 24
Finished Aug 02 08:29:55 PM PDT 24
Peak memory 576052 kb
Host smart-a06b4867-b73c-470f-955b-d7d44a44fdcf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539645557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_
device_slow_rsp.2539645557
Directory /workspace/80.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.898869713
Short name T2371
Test name
Test status
Simulation time 1341751615 ps
CPU time 48.94 seconds
Started Aug 02 08:06:43 PM PDT 24
Finished Aug 02 08:07:32 PM PDT 24
Peak memory 576072 kb
Host smart-0e768b0d-3c4f-4429-90ba-c01287b33567
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898869713 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_and_unmapped_addr
.898869713
Directory /workspace/80.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_error_random.1766879080
Short name T2306
Test name
Test status
Simulation time 368288267 ps
CPU time 29.69 seconds
Started Aug 02 08:06:28 PM PDT 24
Finished Aug 02 08:06:58 PM PDT 24
Peak memory 575952 kb
Host smart-1d3149f9-c9d2-4edb-9d59-97bbbc989287
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766879080 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_random.1766879080
Directory /workspace/80.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_random.3854402554
Short name T461
Test name
Test status
Simulation time 425265586 ps
CPU time 38.14 seconds
Started Aug 02 08:06:30 PM PDT 24
Finished Aug 02 08:07:08 PM PDT 24
Peak memory 576016 kb
Host smart-1eb35245-7676-4401-9d80-bebcc4740e52
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854402554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random.3854402554
Directory /workspace/80.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_random_large_delays.1007029739
Short name T623
Test name
Test status
Simulation time 45619791798 ps
CPU time 457.99 seconds
Started Aug 02 08:06:29 PM PDT 24
Finished Aug 02 08:14:08 PM PDT 24
Peak memory 575816 kb
Host smart-32e0a089-5db4-4472-b192-fa10abaa95d4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007029739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_large_delays.1007029739
Directory /workspace/80.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_random_slow_rsp.2030539145
Short name T663
Test name
Test status
Simulation time 60992691150 ps
CPU time 1126.79 seconds
Started Aug 02 08:06:30 PM PDT 24
Finished Aug 02 08:25:17 PM PDT 24
Peak memory 575888 kb
Host smart-7eb5de30-2650-4bf2-8d5d-3bd6c05af206
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030539145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_slow_rsp.2030539145
Directory /workspace/80.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_random_zero_delays.1719959464
Short name T1875
Test name
Test status
Simulation time 303386309 ps
CPU time 26.7 seconds
Started Aug 02 08:06:30 PM PDT 24
Finished Aug 02 08:06:57 PM PDT 24
Peak memory 575796 kb
Host smart-da4032ed-c69b-407f-aa2d-bdb04b056bf5
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719959464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_zero_del
ays.1719959464
Directory /workspace/80.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_same_source.2567152253
Short name T2621
Test name
Test status
Simulation time 963399465 ps
CPU time 29.91 seconds
Started Aug 02 08:06:29 PM PDT 24
Finished Aug 02 08:06:59 PM PDT 24
Peak memory 575776 kb
Host smart-2c2263f2-1275-410c-a13a-864dc8ef8785
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567152253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_same_source.2567152253
Directory /workspace/80.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_smoke.1605098902
Short name T683
Test name
Test status
Simulation time 55406234 ps
CPU time 6.23 seconds
Started Aug 02 08:06:30 PM PDT 24
Finished Aug 02 08:06:36 PM PDT 24
Peak memory 574520 kb
Host smart-7afb71e0-9a43-49e3-9e17-b5ed6b657ee2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605098902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke.1605098902
Directory /workspace/80.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.461860674
Short name T1667
Test name
Test status
Simulation time 4727876323 ps
CPU time 80.97 seconds
Started Aug 02 08:06:30 PM PDT 24
Finished Aug 02 08:07:51 PM PDT 24
Peak memory 573920 kb
Host smart-10baec6d-0014-4e57-8391-5f56d93b9500
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461860674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_slow_rsp.461860674
Directory /workspace/80.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.1584875872
Short name T2002
Test name
Test status
Simulation time 59708981 ps
CPU time 6.57 seconds
Started Aug 02 08:06:30 PM PDT 24
Finished Aug 02 08:06:37 PM PDT 24
Peak memory 574532 kb
Host smart-d5ae46e8-2b7e-4bae-8327-402e04cba6ca
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584875872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_zero_delay
s.1584875872
Directory /workspace/80.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_stress_all.534057380
Short name T2559
Test name
Test status
Simulation time 3947759098 ps
CPU time 322.63 seconds
Started Aug 02 08:06:45 PM PDT 24
Finished Aug 02 08:12:08 PM PDT 24
Peak memory 575996 kb
Host smart-82e82e5e-786c-4712-90e0-22fb081110b9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534057380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all.534057380
Directory /workspace/80.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.3863977581
Short name T2167
Test name
Test status
Simulation time 6023080554 ps
CPU time 210.14 seconds
Started Aug 02 08:06:44 PM PDT 24
Finished Aug 02 08:10:15 PM PDT 24
Peak memory 575948 kb
Host smart-c8f8d53d-2a8a-4b2e-ac9c-6af552aa4eda
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863977581 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_error.3863977581
Directory /workspace/80.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.668712199
Short name T686
Test name
Test status
Simulation time 666620219 ps
CPU time 281.32 seconds
Started Aug 02 08:06:42 PM PDT 24
Finished Aug 02 08:11:24 PM PDT 24
Peak memory 575920 kb
Host smart-a3ed87c6-eec3-4061-8370-8fef5f9649aa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668712199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_
with_rand_reset.668712199
Directory /workspace/80.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.2924676353
Short name T911
Test name
Test status
Simulation time 409034588 ps
CPU time 129.55 seconds
Started Aug 02 08:06:44 PM PDT 24
Finished Aug 02 08:08:53 PM PDT 24
Peak memory 576832 kb
Host smart-9a1bac13-2e19-4edf-86bc-b107a5f3fbd3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924676353 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_al
l_with_reset_error.2924676353
Directory /workspace/80.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_unmapped_addr.3779360728
Short name T1823
Test name
Test status
Simulation time 121610643 ps
CPU time 17.4 seconds
Started Aug 02 08:06:32 PM PDT 24
Finished Aug 02 08:06:49 PM PDT 24
Peak memory 575816 kb
Host smart-8dab9c1f-6900-43d5-93c6-84abbf2592b3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779360728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_unmapped_addr.3779360728
Directory /workspace/80.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_access_same_device.1266976262
Short name T2806
Test name
Test status
Simulation time 921127830 ps
CPU time 32.42 seconds
Started Aug 02 08:06:45 PM PDT 24
Finished Aug 02 08:07:18 PM PDT 24
Peak memory 575768 kb
Host smart-2a10847b-32a2-41a4-a5b3-389d109befb8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266976262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device
.1266976262
Directory /workspace/81.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.1189064414
Short name T853
Test name
Test status
Simulation time 86345611142 ps
CPU time 1338.78 seconds
Started Aug 02 08:06:45 PM PDT 24
Finished Aug 02 08:29:04 PM PDT 24
Peak memory 576780 kb
Host smart-89e41e4b-70a2-493b-8ee7-527618da881a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189064414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_
device_slow_rsp.1189064414
Directory /workspace/81.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.2099935392
Short name T1446
Test name
Test status
Simulation time 238039036 ps
CPU time 26.84 seconds
Started Aug 02 08:06:44 PM PDT 24
Finished Aug 02 08:07:11 PM PDT 24
Peak memory 575812 kb
Host smart-45742a0a-02cb-49cc-9101-4aaec52ae1b8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099935392 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_and_unmapped_add
r.2099935392
Directory /workspace/81.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_error_random.1106311749
Short name T1465
Test name
Test status
Simulation time 67375886 ps
CPU time 8.5 seconds
Started Aug 02 08:06:43 PM PDT 24
Finished Aug 02 08:06:52 PM PDT 24
Peak memory 575976 kb
Host smart-0c115257-00bc-40e7-92a3-fadd5b3e8898
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106311749 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_random.1106311749
Directory /workspace/81.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_random.4001787179
Short name T2438
Test name
Test status
Simulation time 1134606630 ps
CPU time 37.42 seconds
Started Aug 02 08:06:50 PM PDT 24
Finished Aug 02 08:07:28 PM PDT 24
Peak memory 575944 kb
Host smart-edffb377-4fce-42af-ada4-74d788642b8a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001787179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random.4001787179
Directory /workspace/81.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_random_large_delays.4167358119
Short name T1731
Test name
Test status
Simulation time 75875882481 ps
CPU time 814.33 seconds
Started Aug 02 08:06:46 PM PDT 24
Finished Aug 02 08:20:20 PM PDT 24
Peak memory 575872 kb
Host smart-eb68df3a-70b8-41b2-ba17-cf6c8681f1e5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167358119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_large_delays.4167358119
Directory /workspace/81.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.3375543964
Short name T1686
Test name
Test status
Simulation time 13992977046 ps
CPU time 221.93 seconds
Started Aug 02 08:06:44 PM PDT 24
Finished Aug 02 08:10:26 PM PDT 24
Peak memory 576852 kb
Host smart-bcab6490-701e-48f0-8d82-00c91403468b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375543964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_slow_rsp.3375543964
Directory /workspace/81.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_random_zero_delays.275451750
Short name T2477
Test name
Test status
Simulation time 33500895 ps
CPU time 6.66 seconds
Started Aug 02 08:06:45 PM PDT 24
Finished Aug 02 08:06:51 PM PDT 24
Peak memory 574444 kb
Host smart-d2b33747-67bc-4e22-815d-a3006f30ef51
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275451750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_zero_dela
ys.275451750
Directory /workspace/81.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_same_source.2948105958
Short name T1978
Test name
Test status
Simulation time 1361321908 ps
CPU time 39.56 seconds
Started Aug 02 08:06:46 PM PDT 24
Finished Aug 02 08:07:26 PM PDT 24
Peak memory 575916 kb
Host smart-51e9c097-1d8f-4fda-b879-d4a2a6f32690
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948105958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_same_source.2948105958
Directory /workspace/81.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_smoke.125382859
Short name T2181
Test name
Test status
Simulation time 176869504 ps
CPU time 7.86 seconds
Started Aug 02 08:06:45 PM PDT 24
Finished Aug 02 08:06:53 PM PDT 24
Peak memory 573784 kb
Host smart-57a1da7d-284a-4512-8d6d-21dd62122d3c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125382859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke.125382859
Directory /workspace/81.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_smoke_large_delays.3368329877
Short name T2505
Test name
Test status
Simulation time 9185499993 ps
CPU time 100.61 seconds
Started Aug 02 08:06:44 PM PDT 24
Finished Aug 02 08:08:25 PM PDT 24
Peak memory 574572 kb
Host smart-a86b8002-efe9-4f51-be02-4059eaaa2d95
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368329877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_large_delays.3368329877
Directory /workspace/81.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.1458927756
Short name T2332
Test name
Test status
Simulation time 5009740057 ps
CPU time 87.51 seconds
Started Aug 02 08:06:44 PM PDT 24
Finished Aug 02 08:08:12 PM PDT 24
Peak memory 573924 kb
Host smart-c13eaa5a-37c2-4406-ab61-b349d55f7251
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458927756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_slow_rsp.1458927756
Directory /workspace/81.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_smoke_zero_delays.2399985115
Short name T1423
Test name
Test status
Simulation time 48229697 ps
CPU time 6.32 seconds
Started Aug 02 08:06:46 PM PDT 24
Finished Aug 02 08:06:52 PM PDT 24
Peak memory 573784 kb
Host smart-9b1fd767-164e-437a-9ed3-4e453b748d37
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399985115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_zero_delay
s.2399985115
Directory /workspace/81.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_stress_all.1206642088
Short name T2315
Test name
Test status
Simulation time 14382797067 ps
CPU time 541.67 seconds
Started Aug 02 08:06:43 PM PDT 24
Finished Aug 02 08:15:46 PM PDT 24
Peak memory 576828 kb
Host smart-82a45449-0a94-4dd1-b2d4-ed618e6646ca
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206642088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all.1206642088
Directory /workspace/81.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.3182896384
Short name T2650
Test name
Test status
Simulation time 565231535 ps
CPU time 43.2 seconds
Started Aug 02 08:06:43 PM PDT 24
Finished Aug 02 08:07:26 PM PDT 24
Peak memory 575780 kb
Host smart-6485bb00-4c97-4e9d-8a56-b8db94b4f9af
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182896384 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_error.3182896384
Directory /workspace/81.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.123471115
Short name T609
Test name
Test status
Simulation time 1763356984 ps
CPU time 317.01 seconds
Started Aug 02 08:06:45 PM PDT 24
Finished Aug 02 08:12:02 PM PDT 24
Peak memory 575940 kb
Host smart-7a93b9fd-01eb-4977-b262-168db8c1f10e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123471115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_
with_rand_reset.123471115
Directory /workspace/81.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.771753729
Short name T2543
Test name
Test status
Simulation time 4724210778 ps
CPU time 634.71 seconds
Started Aug 02 08:06:45 PM PDT 24
Finished Aug 02 08:17:20 PM PDT 24
Peak memory 582740 kb
Host smart-31e0d669-4938-4235-b536-bd1bead45dc7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771753729 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all
_with_reset_error.771753729
Directory /workspace/81.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_unmapped_addr.3232707968
Short name T2552
Test name
Test status
Simulation time 253305816 ps
CPU time 27.83 seconds
Started Aug 02 08:06:45 PM PDT 24
Finished Aug 02 08:07:13 PM PDT 24
Peak memory 575832 kb
Host smart-20744c07-1fe0-42a1-a247-fb19db1355a0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232707968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_unmapped_addr.3232707968
Directory /workspace/81.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_access_same_device.719239613
Short name T2866
Test name
Test status
Simulation time 2015879869 ps
CPU time 78.16 seconds
Started Aug 02 08:07:02 PM PDT 24
Finished Aug 02 08:08:20 PM PDT 24
Peak memory 575848 kb
Host smart-4f6c1ed7-c239-4ccb-bc43-d95151aa00f0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719239613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device.
719239613
Directory /workspace/82.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.2890968804
Short name T2741
Test name
Test status
Simulation time 57970495787 ps
CPU time 988.13 seconds
Started Aug 02 08:07:09 PM PDT 24
Finished Aug 02 08:23:37 PM PDT 24
Peak memory 575940 kb
Host smart-6c6253fb-e9a4-44a4-93aa-3c0c93d58bad
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890968804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_
device_slow_rsp.2890968804
Directory /workspace/82.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.1520232707
Short name T1437
Test name
Test status
Simulation time 21020094 ps
CPU time 5.5 seconds
Started Aug 02 08:07:00 PM PDT 24
Finished Aug 02 08:07:06 PM PDT 24
Peak memory 573824 kb
Host smart-b5198706-6ee4-4b07-8127-08346e56703f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520232707 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_and_unmapped_add
r.1520232707
Directory /workspace/82.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_error_random.2500921755
Short name T1645
Test name
Test status
Simulation time 259144379 ps
CPU time 21.15 seconds
Started Aug 02 08:07:08 PM PDT 24
Finished Aug 02 08:07:30 PM PDT 24
Peak memory 575984 kb
Host smart-c3397e1f-4667-42ed-8f6f-ca9a7ec8447b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500921755 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_random.2500921755
Directory /workspace/82.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_random.1674726706
Short name T2184
Test name
Test status
Simulation time 354108622 ps
CPU time 15.33 seconds
Started Aug 02 08:07:01 PM PDT 24
Finished Aug 02 08:07:17 PM PDT 24
Peak memory 575992 kb
Host smart-ac0816a6-add6-48b2-88d2-517d1d5463e1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674726706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random.1674726706
Directory /workspace/82.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_random_large_delays.2669887635
Short name T1841
Test name
Test status
Simulation time 87633350719 ps
CPU time 1027.83 seconds
Started Aug 02 08:07:00 PM PDT 24
Finished Aug 02 08:24:08 PM PDT 24
Peak memory 576076 kb
Host smart-bd23d922-4d7f-45be-a255-6b5f6d19180b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669887635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_large_delays.2669887635
Directory /workspace/82.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_random_slow_rsp.2940165439
Short name T2209
Test name
Test status
Simulation time 34983415175 ps
CPU time 645.05 seconds
Started Aug 02 08:07:06 PM PDT 24
Finished Aug 02 08:17:51 PM PDT 24
Peak memory 575984 kb
Host smart-1c9f231d-8d2a-40b5-90a8-d5f679b9e5b2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940165439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_slow_rsp.2940165439
Directory /workspace/82.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.3004659057
Short name T2121
Test name
Test status
Simulation time 191292295 ps
CPU time 17.73 seconds
Started Aug 02 08:06:59 PM PDT 24
Finished Aug 02 08:07:17 PM PDT 24
Peak memory 575756 kb
Host smart-83b5e7db-f415-43ab-9130-5b4469c7f6ee
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004659057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_zero_del
ays.3004659057
Directory /workspace/82.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_same_source.792603051
Short name T2131
Test name
Test status
Simulation time 861573753 ps
CPU time 26.37 seconds
Started Aug 02 08:07:00 PM PDT 24
Finished Aug 02 08:07:27 PM PDT 24
Peak memory 575748 kb
Host smart-5abebdf7-20b9-480d-9fdf-99e4dd79bb03
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792603051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_same_source.792603051
Directory /workspace/82.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_smoke.3378360850
Short name T1409
Test name
Test status
Simulation time 235678074 ps
CPU time 10.79 seconds
Started Aug 02 08:06:46 PM PDT 24
Finished Aug 02 08:06:57 PM PDT 24
Peak memory 574536 kb
Host smart-5c7355ed-d944-4e05-915a-b7ab049ae888
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378360850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke.3378360850
Directory /workspace/82.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_smoke_large_delays.1476938282
Short name T1882
Test name
Test status
Simulation time 8683922783 ps
CPU time 89.03 seconds
Started Aug 02 08:06:59 PM PDT 24
Finished Aug 02 08:08:29 PM PDT 24
Peak memory 574676 kb
Host smart-92af887c-e18f-4419-ab0f-b9cb9760c8fb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476938282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_large_delays.1476938282
Directory /workspace/82.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.1243096650
Short name T2207
Test name
Test status
Simulation time 4835229590 ps
CPU time 76.73 seconds
Started Aug 02 08:06:58 PM PDT 24
Finished Aug 02 08:08:14 PM PDT 24
Peak memory 573896 kb
Host smart-aee78199-12cd-422b-bb87-2a9760485963
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243096650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_slow_rsp.1243096650
Directory /workspace/82.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_smoke_zero_delays.755751698
Short name T2364
Test name
Test status
Simulation time 56117054 ps
CPU time 7.57 seconds
Started Aug 02 08:06:57 PM PDT 24
Finished Aug 02 08:07:05 PM PDT 24
Peak memory 574500 kb
Host smart-7f1d69b0-459e-4c2b-95af-243170c7964e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755751698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_zero_delays
.755751698
Directory /workspace/82.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_stress_all.2641165712
Short name T2777
Test name
Test status
Simulation time 15592065357 ps
CPU time 570.46 seconds
Started Aug 02 08:07:01 PM PDT 24
Finished Aug 02 08:16:32 PM PDT 24
Peak memory 576036 kb
Host smart-c4efeb1b-99b4-48ea-98f0-708bf555a8e3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641165712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all.2641165712
Directory /workspace/82.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.800349655
Short name T2037
Test name
Test status
Simulation time 8223988610 ps
CPU time 298.71 seconds
Started Aug 02 08:07:06 PM PDT 24
Finished Aug 02 08:12:05 PM PDT 24
Peak memory 576760 kb
Host smart-be13cbbb-9e65-4da0-9ed6-2bc950db0dd3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800349655 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_error.800349655
Directory /workspace/82.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.3943920957
Short name T500
Test name
Test status
Simulation time 5990322663 ps
CPU time 330.33 seconds
Started Aug 02 08:06:57 PM PDT 24
Finished Aug 02 08:12:28 PM PDT 24
Peak memory 575972 kb
Host smart-a6b46295-7b94-44c9-8154-d92167078d3a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943920957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all
_with_rand_reset.3943920957
Directory /workspace/82.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.3871641986
Short name T2837
Test name
Test status
Simulation time 16848641964 ps
CPU time 783.99 seconds
Started Aug 02 08:07:01 PM PDT 24
Finished Aug 02 08:20:05 PM PDT 24
Peak memory 582936 kb
Host smart-5a11806d-19a8-4353-8591-c805a179cdf8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871641986 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_al
l_with_reset_error.3871641986
Directory /workspace/82.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_unmapped_addr.2977970572
Short name T2803
Test name
Test status
Simulation time 42491850 ps
CPU time 7.38 seconds
Started Aug 02 08:07:07 PM PDT 24
Finished Aug 02 08:07:14 PM PDT 24
Peak memory 574620 kb
Host smart-1d27a237-c897-477d-8c49-6c6cf4e17310
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977970572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_unmapped_addr.2977970572
Directory /workspace/82.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_access_same_device.902167943
Short name T1734
Test name
Test status
Simulation time 498369987 ps
CPU time 26.83 seconds
Started Aug 02 08:06:58 PM PDT 24
Finished Aug 02 08:07:25 PM PDT 24
Peak memory 575872 kb
Host smart-258fa503-01bd-4fde-8d98-498178e1b13d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902167943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device.
902167943
Directory /workspace/83.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.4227556208
Short name T2750
Test name
Test status
Simulation time 145414292761 ps
CPU time 2766.15 seconds
Started Aug 02 08:06:56 PM PDT 24
Finished Aug 02 08:53:03 PM PDT 24
Peak memory 575848 kb
Host smart-f932157b-bb2e-4e84-9594-35ceb56247d9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227556208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_
device_slow_rsp.4227556208
Directory /workspace/83.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.4162481987
Short name T1503
Test name
Test status
Simulation time 155721269 ps
CPU time 16.26 seconds
Started Aug 02 08:06:56 PM PDT 24
Finished Aug 02 08:07:12 PM PDT 24
Peak memory 575940 kb
Host smart-72d5d9e9-ff91-471d-8538-2240f64f6fe5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162481987 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_and_unmapped_add
r.4162481987
Directory /workspace/83.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_error_random.2563178140
Short name T696
Test name
Test status
Simulation time 622415136 ps
CPU time 47.91 seconds
Started Aug 02 08:06:59 PM PDT 24
Finished Aug 02 08:07:47 PM PDT 24
Peak memory 575956 kb
Host smart-73ffaa36-da33-4bf2-a71c-0303a65b6faa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563178140 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_random.2563178140
Directory /workspace/83.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_random.1231314026
Short name T516
Test name
Test status
Simulation time 1225431479 ps
CPU time 43.51 seconds
Started Aug 02 08:06:57 PM PDT 24
Finished Aug 02 08:07:41 PM PDT 24
Peak memory 575972 kb
Host smart-5415be5d-0a03-4928-a250-fc9c63bdbcfb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231314026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random.1231314026
Directory /workspace/83.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_random_large_delays.2740487306
Short name T2392
Test name
Test status
Simulation time 86054270617 ps
CPU time 914.17 seconds
Started Aug 02 08:07:09 PM PDT 24
Finished Aug 02 08:22:23 PM PDT 24
Peak memory 576808 kb
Host smart-49542099-911f-46fe-a3bf-7a193af90a88
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740487306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_large_delays.2740487306
Directory /workspace/83.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_random_slow_rsp.2562325373
Short name T1506
Test name
Test status
Simulation time 61545608388 ps
CPU time 1061.14 seconds
Started Aug 02 08:06:59 PM PDT 24
Finished Aug 02 08:24:41 PM PDT 24
Peak memory 575992 kb
Host smart-37629f3b-a2e9-460b-89c1-24d8e5b5dbdc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562325373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_slow_rsp.2562325373
Directory /workspace/83.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.3582138516
Short name T2722
Test name
Test status
Simulation time 585459058 ps
CPU time 44.43 seconds
Started Aug 02 08:07:09 PM PDT 24
Finished Aug 02 08:07:53 PM PDT 24
Peak memory 575800 kb
Host smart-7064cad8-fc33-40fe-9368-c4bd0a63638e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582138516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_zero_del
ays.3582138516
Directory /workspace/83.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_same_source.1756618685
Short name T1733
Test name
Test status
Simulation time 890104487 ps
CPU time 28.08 seconds
Started Aug 02 08:07:03 PM PDT 24
Finished Aug 02 08:07:31 PM PDT 24
Peak memory 575896 kb
Host smart-15fc91a6-5218-42f1-8d62-75d240c65878
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756618685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_same_source.1756618685
Directory /workspace/83.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_smoke.2291352795
Short name T1742
Test name
Test status
Simulation time 39419851 ps
CPU time 6.13 seconds
Started Aug 02 08:07:01 PM PDT 24
Finished Aug 02 08:07:08 PM PDT 24
Peak memory 573852 kb
Host smart-64c766b0-ac0a-4fc6-ba6e-30f6769b36ca
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291352795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke.2291352795
Directory /workspace/83.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.1620197999
Short name T1507
Test name
Test status
Simulation time 8727451898 ps
CPU time 95.02 seconds
Started Aug 02 08:07:00 PM PDT 24
Finished Aug 02 08:08:35 PM PDT 24
Peak memory 574584 kb
Host smart-27045b3a-6ab9-4933-9271-02e186b98ffb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620197999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_large_delays.1620197999
Directory /workspace/83.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.1123495935
Short name T2162
Test name
Test status
Simulation time 4767227388 ps
CPU time 71.18 seconds
Started Aug 02 08:07:01 PM PDT 24
Finished Aug 02 08:08:12 PM PDT 24
Peak memory 573948 kb
Host smart-bef3043c-5898-4c46-90b4-c85b53369e0c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123495935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_slow_rsp.1123495935
Directory /workspace/83.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_smoke_zero_delays.1102190725
Short name T2479
Test name
Test status
Simulation time 54226760 ps
CPU time 6.37 seconds
Started Aug 02 08:07:00 PM PDT 24
Finished Aug 02 08:07:07 PM PDT 24
Peak memory 574500 kb
Host smart-ab47dac2-149d-4d44-9886-f36b91ac2d58
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102190725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_zero_delay
s.1102190725
Directory /workspace/83.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_stress_all.4263205498
Short name T1845
Test name
Test status
Simulation time 4960932493 ps
CPU time 158.15 seconds
Started Aug 02 08:07:07 PM PDT 24
Finished Aug 02 08:09:45 PM PDT 24
Peak memory 576048 kb
Host smart-e30b6e6f-425c-45d7-bb7d-c922ededcc91
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263205498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all.4263205498
Directory /workspace/83.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_error.981293532
Short name T1777
Test name
Test status
Simulation time 2348340591 ps
CPU time 180.01 seconds
Started Aug 02 08:06:56 PM PDT 24
Finished Aug 02 08:09:56 PM PDT 24
Peak memory 576196 kb
Host smart-310adc66-43ef-495a-a96d-2d8d6cbdee08
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981293532 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_error.981293532
Directory /workspace/83.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.3227501243
Short name T2673
Test name
Test status
Simulation time 3567254345 ps
CPU time 259.56 seconds
Started Aug 02 08:06:59 PM PDT 24
Finished Aug 02 08:11:18 PM PDT 24
Peak memory 575924 kb
Host smart-e0035e8f-aede-4762-8859-cb41475bcfbd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227501243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all
_with_rand_reset.3227501243
Directory /workspace/83.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.3933304195
Short name T1778
Test name
Test status
Simulation time 32410448 ps
CPU time 14.21 seconds
Started Aug 02 08:06:59 PM PDT 24
Finished Aug 02 08:07:14 PM PDT 24
Peak memory 574480 kb
Host smart-6d042b78-f2b8-40cb-989c-5c25c6ea532f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933304195 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_al
l_with_reset_error.3933304195
Directory /workspace/83.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_unmapped_addr.153497151
Short name T2361
Test name
Test status
Simulation time 211763047 ps
CPU time 10.56 seconds
Started Aug 02 08:07:00 PM PDT 24
Finished Aug 02 08:07:10 PM PDT 24
Peak memory 576008 kb
Host smart-43c13a4c-f78b-4674-a4ad-0fce0e3cc57b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153497151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_unmapped_addr.153497151
Directory /workspace/83.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_access_same_device.463116912
Short name T2507
Test name
Test status
Simulation time 609935160 ps
CPU time 26.71 seconds
Started Aug 02 08:07:10 PM PDT 24
Finished Aug 02 08:07:37 PM PDT 24
Peak memory 575748 kb
Host smart-8976b7f7-72e2-4a1c-b041-0d786fb55e22
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463116912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device.
463116912
Directory /workspace/84.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.2218974178
Short name T870
Test name
Test status
Simulation time 52008147164 ps
CPU time 1010.72 seconds
Started Aug 02 08:07:14 PM PDT 24
Finished Aug 02 08:24:05 PM PDT 24
Peak memory 576000 kb
Host smart-044c3212-dccc-47ac-857d-b466ebed1eee
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218974178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_
device_slow_rsp.2218974178
Directory /workspace/84.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.2309505965
Short name T1545
Test name
Test status
Simulation time 1139766015 ps
CPU time 41.72 seconds
Started Aug 02 08:07:10 PM PDT 24
Finished Aug 02 08:07:52 PM PDT 24
Peak memory 575980 kb
Host smart-2fd863c8-7fbd-4209-a683-53e6a3478329
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309505965 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_and_unmapped_add
r.2309505965
Directory /workspace/84.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_error_random.2238205774
Short name T2224
Test name
Test status
Simulation time 991340497 ps
CPU time 33.58 seconds
Started Aug 02 08:07:12 PM PDT 24
Finished Aug 02 08:07:46 PM PDT 24
Peak memory 575732 kb
Host smart-7948071f-3f85-43f2-9825-657c1d6fd77d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238205774 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_random.2238205774
Directory /workspace/84.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_random.1003203167
Short name T1870
Test name
Test status
Simulation time 585974226 ps
CPU time 47.65 seconds
Started Aug 02 08:07:10 PM PDT 24
Finished Aug 02 08:07:58 PM PDT 24
Peak memory 575956 kb
Host smart-11a949b8-c0ad-4943-8698-3339e3a19afd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003203167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random.1003203167
Directory /workspace/84.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_random_large_delays.1021746836
Short name T1807
Test name
Test status
Simulation time 109433590627 ps
CPU time 1090.12 seconds
Started Aug 02 08:07:16 PM PDT 24
Finished Aug 02 08:25:27 PM PDT 24
Peak memory 576060 kb
Host smart-83f48769-4aed-493c-9202-da5b7e046598
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021746836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_large_delays.1021746836
Directory /workspace/84.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_random_slow_rsp.3969646004
Short name T1940
Test name
Test status
Simulation time 19869847543 ps
CPU time 354.67 seconds
Started Aug 02 08:07:16 PM PDT 24
Finished Aug 02 08:13:11 PM PDT 24
Peak memory 575836 kb
Host smart-10b141c0-3336-41c2-b526-d6581242e7d8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969646004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_slow_rsp.3969646004
Directory /workspace/84.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_random_zero_delays.24772891
Short name T2704
Test name
Test status
Simulation time 359910230 ps
CPU time 31 seconds
Started Aug 02 08:07:12 PM PDT 24
Finished Aug 02 08:07:43 PM PDT 24
Peak memory 575872 kb
Host smart-c9c25ca9-2fcd-43db-9998-bd0457d4b0f8
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24772891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_zero_delay
s.24772891
Directory /workspace/84.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_same_source.1364744449
Short name T565
Test name
Test status
Simulation time 608536437 ps
CPU time 20.13 seconds
Started Aug 02 08:07:13 PM PDT 24
Finished Aug 02 08:07:33 PM PDT 24
Peak memory 575856 kb
Host smart-33b34946-80dd-4104-86b9-2e1f7647c6fc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364744449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_same_source.1364744449
Directory /workspace/84.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_smoke.4277523564
Short name T1625
Test name
Test status
Simulation time 40110570 ps
CPU time 6.24 seconds
Started Aug 02 08:06:57 PM PDT 24
Finished Aug 02 08:07:03 PM PDT 24
Peak memory 573768 kb
Host smart-71da2ccb-eaca-454d-adc4-4f6e4a5aafbd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277523564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke.4277523564
Directory /workspace/84.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.2440646333
Short name T2724
Test name
Test status
Simulation time 7526022407 ps
CPU time 77.32 seconds
Started Aug 02 08:07:11 PM PDT 24
Finished Aug 02 08:08:28 PM PDT 24
Peak memory 573852 kb
Host smart-0e9c4812-b36f-4936-85af-be96849dd70e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440646333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_large_delays.2440646333
Directory /workspace/84.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.92616229
Short name T1927
Test name
Test status
Simulation time 3833154993 ps
CPU time 64.83 seconds
Started Aug 02 08:07:12 PM PDT 24
Finished Aug 02 08:08:17 PM PDT 24
Peak memory 573980 kb
Host smart-d0729318-5f94-401d-83b4-768e677ca985
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92616229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_slow_rsp.92616229
Directory /workspace/84.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_smoke_zero_delays.3126136484
Short name T2437
Test name
Test status
Simulation time 56355843 ps
CPU time 6.38 seconds
Started Aug 02 08:07:10 PM PDT 24
Finished Aug 02 08:07:16 PM PDT 24
Peak memory 573796 kb
Host smart-1659c350-a4a7-4241-a98b-fe3f575f66a9
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126136484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_zero_delay
s.3126136484
Directory /workspace/84.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_stress_all.1806569132
Short name T2527
Test name
Test status
Simulation time 3982598181 ps
CPU time 305.03 seconds
Started Aug 02 08:07:12 PM PDT 24
Finished Aug 02 08:12:17 PM PDT 24
Peak memory 575972 kb
Host smart-8e809cc9-349b-4102-9475-2c07aae5dd70
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806569132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all.1806569132
Directory /workspace/84.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.1687638429
Short name T2473
Test name
Test status
Simulation time 6176982096 ps
CPU time 208.73 seconds
Started Aug 02 08:07:16 PM PDT 24
Finished Aug 02 08:10:44 PM PDT 24
Peak memory 576128 kb
Host smart-a1e296f6-ec0e-4a3b-803d-e815a1a17561
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687638429 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_error.1687638429
Directory /workspace/84.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.2953977129
Short name T2427
Test name
Test status
Simulation time 393606557 ps
CPU time 138.29 seconds
Started Aug 02 08:07:14 PM PDT 24
Finished Aug 02 08:09:33 PM PDT 24
Peak memory 576652 kb
Host smart-36472d25-100b-43e3-abd0-0def5cf52db3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953977129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all
_with_rand_reset.2953977129
Directory /workspace/84.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.4255185721
Short name T1594
Test name
Test status
Simulation time 599496265 ps
CPU time 183.16 seconds
Started Aug 02 08:07:17 PM PDT 24
Finished Aug 02 08:10:20 PM PDT 24
Peak memory 576864 kb
Host smart-e84049db-1225-40a8-abfc-ed4f4a0c6170
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255185721 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_al
l_with_reset_error.4255185721
Directory /workspace/84.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_unmapped_addr.501039119
Short name T2591
Test name
Test status
Simulation time 1252153005 ps
CPU time 51.19 seconds
Started Aug 02 08:07:11 PM PDT 24
Finished Aug 02 08:08:02 PM PDT 24
Peak memory 575932 kb
Host smart-cb9167a2-a937-419a-bbd5-e1cfc29ae8da
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501039119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_unmapped_addr.501039119
Directory /workspace/84.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_access_same_device.3287235188
Short name T2909
Test name
Test status
Simulation time 722445622 ps
CPU time 61.19 seconds
Started Aug 02 08:07:13 PM PDT 24
Finished Aug 02 08:08:14 PM PDT 24
Peak memory 575840 kb
Host smart-49aaed6d-92b0-4ece-9614-5e1091cca193
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287235188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device
.3287235188
Directory /workspace/85.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.3835345519
Short name T2432
Test name
Test status
Simulation time 96583496148 ps
CPU time 1869.37 seconds
Started Aug 02 08:07:26 PM PDT 24
Finished Aug 02 08:38:35 PM PDT 24
Peak memory 576788 kb
Host smart-2836afbc-d800-4956-b194-e4672288894a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835345519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_
device_slow_rsp.3835345519
Directory /workspace/85.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.4183214877
Short name T1410
Test name
Test status
Simulation time 606182811 ps
CPU time 25.2 seconds
Started Aug 02 08:07:25 PM PDT 24
Finished Aug 02 08:07:51 PM PDT 24
Peak memory 575980 kb
Host smart-167471ba-3783-4622-8191-2a8810e05d6a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183214877 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_and_unmapped_add
r.4183214877
Directory /workspace/85.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_error_random.2256024659
Short name T1561
Test name
Test status
Simulation time 458168713 ps
CPU time 33.64 seconds
Started Aug 02 08:07:30 PM PDT 24
Finished Aug 02 08:08:04 PM PDT 24
Peak memory 575916 kb
Host smart-ba28a8be-64f3-4d1c-b326-e7c729bc9703
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256024659 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_random.2256024659
Directory /workspace/85.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_random.1684133454
Short name T2089
Test name
Test status
Simulation time 325482733 ps
CPU time 29.03 seconds
Started Aug 02 08:07:11 PM PDT 24
Finished Aug 02 08:07:40 PM PDT 24
Peak memory 575940 kb
Host smart-3bdb53bc-6e13-4f06-8090-3db16e2099c6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684133454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random.1684133454
Directory /workspace/85.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_random_large_delays.608230966
Short name T2772
Test name
Test status
Simulation time 51639301480 ps
CPU time 536.22 seconds
Started Aug 02 08:07:12 PM PDT 24
Finished Aug 02 08:16:08 PM PDT 24
Peak memory 575936 kb
Host smart-c83fa3cd-ad28-41c8-87b2-e9629194dfa0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608230966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_large_delays.608230966
Directory /workspace/85.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_random_slow_rsp.3715266481
Short name T2634
Test name
Test status
Simulation time 53386037823 ps
CPU time 1012.78 seconds
Started Aug 02 08:07:11 PM PDT 24
Finished Aug 02 08:24:04 PM PDT 24
Peak memory 575996 kb
Host smart-76c630e5-b2e7-4627-980d-d1490af5cfaa
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715266481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_slow_rsp.3715266481
Directory /workspace/85.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_random_zero_delays.3119267022
Short name T625
Test name
Test status
Simulation time 131731170 ps
CPU time 13.88 seconds
Started Aug 02 08:07:11 PM PDT 24
Finished Aug 02 08:07:25 PM PDT 24
Peak memory 575844 kb
Host smart-20d76a5d-e4de-4f87-90fd-87c08e58cf14
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119267022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_zero_del
ays.3119267022
Directory /workspace/85.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_same_source.450840283
Short name T1717
Test name
Test status
Simulation time 962476939 ps
CPU time 29.37 seconds
Started Aug 02 08:07:24 PM PDT 24
Finished Aug 02 08:07:53 PM PDT 24
Peak memory 575796 kb
Host smart-1444ac43-fceb-4e8d-beca-2882ac93f90b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450840283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_same_source.450840283
Directory /workspace/85.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_smoke.4004496843
Short name T1678
Test name
Test status
Simulation time 254635435 ps
CPU time 10.12 seconds
Started Aug 02 08:07:11 PM PDT 24
Finished Aug 02 08:07:21 PM PDT 24
Peak memory 573828 kb
Host smart-0e289194-07b4-421b-a7d8-31a05e39978c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004496843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke.4004496843
Directory /workspace/85.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.3776404644
Short name T1641
Test name
Test status
Simulation time 6594287976 ps
CPU time 70.07 seconds
Started Aug 02 08:07:16 PM PDT 24
Finished Aug 02 08:08:27 PM PDT 24
Peak memory 574028 kb
Host smart-f1523987-d6bf-4626-bd46-6eb3977470f4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776404644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_large_delays.3776404644
Directory /workspace/85.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.1746330551
Short name T2285
Test name
Test status
Simulation time 4275211770 ps
CPU time 66.55 seconds
Started Aug 02 08:07:10 PM PDT 24
Finished Aug 02 08:08:17 PM PDT 24
Peak memory 573908 kb
Host smart-225e0e89-0e3e-4dcc-9f72-8b001d2cfcfc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746330551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_slow_rsp.1746330551
Directory /workspace/85.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_smoke_zero_delays.42301698
Short name T1542
Test name
Test status
Simulation time 45269964 ps
CPU time 6.42 seconds
Started Aug 02 08:07:10 PM PDT 24
Finished Aug 02 08:07:17 PM PDT 24
Peak memory 573836 kb
Host smart-c5876431-da0e-4b3b-a2a1-4bfd91eb2627
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42301698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_zero_delays.42301698
Directory /workspace/85.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_stress_all.1904862940
Short name T560
Test name
Test status
Simulation time 6240114100 ps
CPU time 234.89 seconds
Started Aug 02 08:07:25 PM PDT 24
Finished Aug 02 08:11:20 PM PDT 24
Peak memory 576768 kb
Host smart-25b488c3-d502-4138-9dd7-529bf611ebdb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904862940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all.1904862940
Directory /workspace/85.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.3235894637
Short name T2391
Test name
Test status
Simulation time 7850246963 ps
CPU time 275.95 seconds
Started Aug 02 08:07:27 PM PDT 24
Finished Aug 02 08:12:03 PM PDT 24
Peak memory 575976 kb
Host smart-f15f5cea-4e3e-46fb-a26f-a5b135d48ae5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235894637 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_error.3235894637
Directory /workspace/85.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.2926415761
Short name T1921
Test name
Test status
Simulation time 167992997 ps
CPU time 66.64 seconds
Started Aug 02 08:07:28 PM PDT 24
Finished Aug 02 08:08:35 PM PDT 24
Peak memory 576036 kb
Host smart-5eda7f6b-31a5-456d-8818-c22d9a9e8613
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926415761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all
_with_rand_reset.2926415761
Directory /workspace/85.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.934796558
Short name T1908
Test name
Test status
Simulation time 1873933768 ps
CPU time 365.07 seconds
Started Aug 02 08:07:28 PM PDT 24
Finished Aug 02 08:13:33 PM PDT 24
Peak memory 576840 kb
Host smart-b4d74ffc-f1b0-4ba8-a865-b9952d08de9f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934796558 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all
_with_reset_error.934796558
Directory /workspace/85.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_unmapped_addr.3099673920
Short name T539
Test name
Test status
Simulation time 261803199 ps
CPU time 29.47 seconds
Started Aug 02 08:07:25 PM PDT 24
Finished Aug 02 08:07:55 PM PDT 24
Peak memory 575932 kb
Host smart-4b933741-b5f1-4f55-9d91-fabbe704d869
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099673920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_unmapped_addr.3099673920
Directory /workspace/85.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_access_same_device.2195539630
Short name T2377
Test name
Test status
Simulation time 845724620 ps
CPU time 63.64 seconds
Started Aug 02 08:07:25 PM PDT 24
Finished Aug 02 08:08:29 PM PDT 24
Peak memory 575940 kb
Host smart-c908cdc8-4cdb-4acd-b1e9-aa0d1bb67098
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195539630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device
.2195539630
Directory /workspace/86.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.3528383837
Short name T2767
Test name
Test status
Simulation time 10227095079 ps
CPU time 177.44 seconds
Started Aug 02 08:07:26 PM PDT 24
Finished Aug 02 08:10:24 PM PDT 24
Peak memory 576088 kb
Host smart-0abcdefa-447d-410a-b1ee-9df9fef874ed
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528383837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_
device_slow_rsp.3528383837
Directory /workspace/86.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.3636518062
Short name T2335
Test name
Test status
Simulation time 741386180 ps
CPU time 30.46 seconds
Started Aug 02 08:07:39 PM PDT 24
Finished Aug 02 08:08:09 PM PDT 24
Peak memory 575684 kb
Host smart-25f35aef-f6ac-4349-8c1f-aba86ccdd270
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636518062 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_and_unmapped_add
r.3636518062
Directory /workspace/86.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_error_random.2028501974
Short name T2057
Test name
Test status
Simulation time 2715581594 ps
CPU time 92.33 seconds
Started Aug 02 08:07:23 PM PDT 24
Finished Aug 02 08:08:56 PM PDT 24
Peak memory 575824 kb
Host smart-2cd13350-5f51-4f3b-afc4-534b8fd32826
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028501974 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_random.2028501974
Directory /workspace/86.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_random.1933385143
Short name T474
Test name
Test status
Simulation time 228178523 ps
CPU time 19.82 seconds
Started Aug 02 08:07:24 PM PDT 24
Finished Aug 02 08:07:44 PM PDT 24
Peak memory 575892 kb
Host smart-32e55820-e03c-4ba0-a7fb-4b281e087cab
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933385143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random.1933385143
Directory /workspace/86.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_random_large_delays.1221615484
Short name T2883
Test name
Test status
Simulation time 31295535973 ps
CPU time 324.12 seconds
Started Aug 02 08:07:26 PM PDT 24
Finished Aug 02 08:12:50 PM PDT 24
Peak memory 576036 kb
Host smart-1e1551f3-2011-42f3-a097-2832186c3fe4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221615484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_large_delays.1221615484
Directory /workspace/86.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_random_slow_rsp.126805473
Short name T616
Test name
Test status
Simulation time 55289772161 ps
CPU time 986.53 seconds
Started Aug 02 08:07:28 PM PDT 24
Finished Aug 02 08:23:55 PM PDT 24
Peak memory 575892 kb
Host smart-64c916dc-80b3-4d3d-b624-f9ebceb2c4bc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126805473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_slow_rsp.126805473
Directory /workspace/86.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.2153962984
Short name T2788
Test name
Test status
Simulation time 554431505 ps
CPU time 43.26 seconds
Started Aug 02 08:07:31 PM PDT 24
Finished Aug 02 08:08:14 PM PDT 24
Peak memory 575844 kb
Host smart-7b110e9f-b0ca-4aa8-9e24-d6b302e8d9a8
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153962984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_zero_del
ays.2153962984
Directory /workspace/86.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_same_source.1519852755
Short name T1980
Test name
Test status
Simulation time 1423860932 ps
CPU time 43.26 seconds
Started Aug 02 08:07:28 PM PDT 24
Finished Aug 02 08:08:12 PM PDT 24
Peak memory 575808 kb
Host smart-aadbe2da-cc15-4421-b9ce-b1b1cb147cc7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519852755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_same_source.1519852755
Directory /workspace/86.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_smoke.2450568244
Short name T2917
Test name
Test status
Simulation time 196657307 ps
CPU time 8.65 seconds
Started Aug 02 08:07:26 PM PDT 24
Finished Aug 02 08:07:35 PM PDT 24
Peak memory 573864 kb
Host smart-1d014dfc-fd19-4573-9b8b-83de556c2553
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450568244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke.2450568244
Directory /workspace/86.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_smoke_large_delays.1030290144
Short name T2108
Test name
Test status
Simulation time 7946999630 ps
CPU time 82.51 seconds
Started Aug 02 08:07:26 PM PDT 24
Finished Aug 02 08:08:48 PM PDT 24
Peak memory 574564 kb
Host smart-264ad67f-aaf7-47fc-9c1e-67dd43e6be17
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030290144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_large_delays.1030290144
Directory /workspace/86.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.2541829196
Short name T1517
Test name
Test status
Simulation time 5584193303 ps
CPU time 93.36 seconds
Started Aug 02 08:07:24 PM PDT 24
Finished Aug 02 08:08:58 PM PDT 24
Peak memory 574556 kb
Host smart-ca9781e3-6b99-4ee2-9285-6b0a5272a1a0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541829196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_slow_rsp.2541829196
Directory /workspace/86.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_smoke_zero_delays.3315583396
Short name T2809
Test name
Test status
Simulation time 45267502 ps
CPU time 6.04 seconds
Started Aug 02 08:07:25 PM PDT 24
Finished Aug 02 08:07:31 PM PDT 24
Peak memory 574476 kb
Host smart-9c26234f-e878-4595-a897-c4054c4c7b15
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315583396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_zero_delay
s.3315583396
Directory /workspace/86.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_stress_all.2002300640
Short name T536
Test name
Test status
Simulation time 4278437800 ps
CPU time 161.4 seconds
Started Aug 02 08:07:40 PM PDT 24
Finished Aug 02 08:10:21 PM PDT 24
Peak memory 575964 kb
Host smart-7213f287-678f-46d7-bc89-a6317e3aabfe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002300640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all.2002300640
Directory /workspace/86.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.2932114296
Short name T552
Test name
Test status
Simulation time 1362504754 ps
CPU time 104.75 seconds
Started Aug 02 08:07:36 PM PDT 24
Finished Aug 02 08:09:20 PM PDT 24
Peak memory 576092 kb
Host smart-3443b08e-6083-4367-ac71-634c5357a155
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932114296 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_error.2932114296
Directory /workspace/86.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.383913449
Short name T483
Test name
Test status
Simulation time 2137823639 ps
CPU time 330.63 seconds
Started Aug 02 08:07:36 PM PDT 24
Finished Aug 02 08:13:07 PM PDT 24
Peak memory 575952 kb
Host smart-a98eb487-a43c-4739-8bfd-96bd3fee95c7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383913449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_
with_rand_reset.383913449
Directory /workspace/86.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.3171300630
Short name T699
Test name
Test status
Simulation time 331336635 ps
CPU time 115.2 seconds
Started Aug 02 08:07:36 PM PDT 24
Finished Aug 02 08:09:31 PM PDT 24
Peak memory 576756 kb
Host smart-fd14b963-eb4d-402d-aff4-c2a2933c8d46
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171300630 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_al
l_with_reset_error.3171300630
Directory /workspace/86.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_unmapped_addr.655525157
Short name T1847
Test name
Test status
Simulation time 64912120 ps
CPU time 9.85 seconds
Started Aug 02 08:07:36 PM PDT 24
Finished Aug 02 08:07:46 PM PDT 24
Peak memory 575900 kb
Host smart-4c8f9ba6-94da-483f-85ad-192db5592239
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655525157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_unmapped_addr.655525157
Directory /workspace/86.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_access_same_device.3964187265
Short name T2033
Test name
Test status
Simulation time 1706841599 ps
CPU time 71.76 seconds
Started Aug 02 08:07:39 PM PDT 24
Finished Aug 02 08:08:51 PM PDT 24
Peak memory 575876 kb
Host smart-b46d5c34-8ad9-4c32-b578-ff2224caf920
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964187265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device
.3964187265
Directory /workspace/87.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.329310976
Short name T2198
Test name
Test status
Simulation time 142723907154 ps
CPU time 2557.17 seconds
Started Aug 02 08:07:33 PM PDT 24
Finished Aug 02 08:50:11 PM PDT 24
Peak memory 576044 kb
Host smart-c184f1d4-d4cc-429a-9d32-9ddc81da6f35
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329310976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_d
evice_slow_rsp.329310976
Directory /workspace/87.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.2565975828
Short name T1865
Test name
Test status
Simulation time 138936460 ps
CPU time 8.41 seconds
Started Aug 02 08:07:39 PM PDT 24
Finished Aug 02 08:07:47 PM PDT 24
Peak memory 574464 kb
Host smart-0b3edce9-868f-4d9c-9ac0-d6a6a5718567
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565975828 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_and_unmapped_add
r.2565975828
Directory /workspace/87.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_error_random.1621238287
Short name T1597
Test name
Test status
Simulation time 448630819 ps
CPU time 32.78 seconds
Started Aug 02 08:07:35 PM PDT 24
Finished Aug 02 08:08:08 PM PDT 24
Peak memory 575968 kb
Host smart-3c3c4b1f-1639-4015-8203-b0689444c045
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621238287 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_random.1621238287
Directory /workspace/87.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_random.4196444907
Short name T1743
Test name
Test status
Simulation time 99858864 ps
CPU time 10.84 seconds
Started Aug 02 08:07:35 PM PDT 24
Finished Aug 02 08:07:46 PM PDT 24
Peak memory 575852 kb
Host smart-8fb5d221-8f10-4c61-878c-b6f54b48f85d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196444907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random.4196444907
Directory /workspace/87.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_random_large_delays.4197441439
Short name T2897
Test name
Test status
Simulation time 22477772095 ps
CPU time 256.35 seconds
Started Aug 02 08:07:40 PM PDT 24
Finished Aug 02 08:11:56 PM PDT 24
Peak memory 575980 kb
Host smart-3964646b-d0e8-4297-835d-2d6de03be28d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197441439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_large_delays.4197441439
Directory /workspace/87.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_random_slow_rsp.2722319661
Short name T2455
Test name
Test status
Simulation time 67654516017 ps
CPU time 1268.78 seconds
Started Aug 02 08:07:39 PM PDT 24
Finished Aug 02 08:28:48 PM PDT 24
Peak memory 575996 kb
Host smart-89c07786-3959-4df1-8429-dd0152e05831
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722319661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_slow_rsp.2722319661
Directory /workspace/87.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_random_zero_delays.971800043
Short name T2026
Test name
Test status
Simulation time 408242609 ps
CPU time 34.79 seconds
Started Aug 02 08:07:36 PM PDT 24
Finished Aug 02 08:08:11 PM PDT 24
Peak memory 575880 kb
Host smart-37502954-4110-4ef8-b0ca-0c1858118225
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971800043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_zero_dela
ys.971800043
Directory /workspace/87.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_same_source.285220078
Short name T2582
Test name
Test status
Simulation time 1747897957 ps
CPU time 48.53 seconds
Started Aug 02 08:07:41 PM PDT 24
Finished Aug 02 08:08:29 PM PDT 24
Peak memory 575884 kb
Host smart-f61c510a-c5c2-4f8d-a525-73dab5a1989d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285220078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_same_source.285220078
Directory /workspace/87.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_smoke.3894941509
Short name T1478
Test name
Test status
Simulation time 54279557 ps
CPU time 6.63 seconds
Started Aug 02 08:07:36 PM PDT 24
Finished Aug 02 08:07:43 PM PDT 24
Peak memory 574556 kb
Host smart-e38fe195-0e30-49ec-97fe-5a837e5afa5f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894941509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke.3894941509
Directory /workspace/87.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_smoke_large_delays.2970312877
Short name T1432
Test name
Test status
Simulation time 7982698900 ps
CPU time 87.12 seconds
Started Aug 02 08:07:36 PM PDT 24
Finished Aug 02 08:09:03 PM PDT 24
Peak memory 573860 kb
Host smart-7e2698f5-7d59-4bc1-83b7-bca867b670ae
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970312877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_large_delays.2970312877
Directory /workspace/87.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.1535923884
Short name T1982
Test name
Test status
Simulation time 5291896072 ps
CPU time 90.67 seconds
Started Aug 02 08:07:39 PM PDT 24
Finished Aug 02 08:09:10 PM PDT 24
Peak memory 573824 kb
Host smart-04479720-3baf-4285-95eb-0e95692809f4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535923884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_slow_rsp.1535923884
Directory /workspace/87.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_smoke_zero_delays.2853124983
Short name T2082
Test name
Test status
Simulation time 44296703 ps
CPU time 6.27 seconds
Started Aug 02 08:07:36 PM PDT 24
Finished Aug 02 08:07:42 PM PDT 24
Peak memory 573740 kb
Host smart-6cce63d1-9e97-4fbb-bf11-58520461efdb
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853124983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_zero_delay
s.2853124983
Directory /workspace/87.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_stress_all.1018740267
Short name T2636
Test name
Test status
Simulation time 4270517003 ps
CPU time 130.51 seconds
Started Aug 02 08:07:49 PM PDT 24
Finished Aug 02 08:09:59 PM PDT 24
Peak memory 576164 kb
Host smart-3e948c5f-e464-4677-ab88-f47abdbcbd52
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018740267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all.1018740267
Directory /workspace/87.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_error.2307305165
Short name T1960
Test name
Test status
Simulation time 1933663487 ps
CPU time 127.7 seconds
Started Aug 02 08:07:49 PM PDT 24
Finished Aug 02 08:09:56 PM PDT 24
Peak memory 576176 kb
Host smart-6f9088de-b122-4153-b48d-e27a0ba04239
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307305165 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_error.2307305165
Directory /workspace/87.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.1610979932
Short name T1874
Test name
Test status
Simulation time 491221325 ps
CPU time 248.08 seconds
Started Aug 02 08:07:50 PM PDT 24
Finished Aug 02 08:11:58 PM PDT 24
Peak memory 575940 kb
Host smart-683daaa6-c591-4f66-ad7c-ab32fe3f7e16
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610979932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all
_with_rand_reset.1610979932
Directory /workspace/87.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.3051223149
Short name T2898
Test name
Test status
Simulation time 7646325821 ps
CPU time 670.64 seconds
Started Aug 02 08:07:50 PM PDT 24
Finished Aug 02 08:19:00 PM PDT 24
Peak memory 576828 kb
Host smart-1181916e-02c0-4aa2-af3c-7960dd6cb09a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051223149 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_al
l_with_reset_error.3051223149
Directory /workspace/87.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_unmapped_addr.2761847713
Short name T1576
Test name
Test status
Simulation time 293430473 ps
CPU time 34.56 seconds
Started Aug 02 08:07:35 PM PDT 24
Finished Aug 02 08:08:09 PM PDT 24
Peak memory 575896 kb
Host smart-c1270b1a-708b-458e-980b-ccab7e15b183
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761847713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_unmapped_addr.2761847713
Directory /workspace/87.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_access_same_device.2558493373
Short name T2149
Test name
Test status
Simulation time 1614978676 ps
CPU time 62.66 seconds
Started Aug 02 08:07:51 PM PDT 24
Finished Aug 02 08:08:54 PM PDT 24
Peak memory 575876 kb
Host smart-c2b7cea9-6187-4b00-9f93-573f56df93e3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558493373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device
.2558493373
Directory /workspace/88.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.613287604
Short name T2873
Test name
Test status
Simulation time 111633959170 ps
CPU time 1971.96 seconds
Started Aug 02 08:07:51 PM PDT 24
Finished Aug 02 08:40:43 PM PDT 24
Peak memory 575944 kb
Host smart-648b4777-49e1-40c7-8f64-dacfcc7c71ce
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613287604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_d
evice_slow_rsp.613287604
Directory /workspace/88.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.410831529
Short name T2638
Test name
Test status
Simulation time 208030549 ps
CPU time 21.91 seconds
Started Aug 02 08:07:49 PM PDT 24
Finished Aug 02 08:08:11 PM PDT 24
Peak memory 575676 kb
Host smart-b6696910-6214-48c2-8c7d-4ac3b1a30d5c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410831529 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_and_unmapped_addr
.410831529
Directory /workspace/88.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_error_random.426914809
Short name T2761
Test name
Test status
Simulation time 1067650549 ps
CPU time 32.02 seconds
Started Aug 02 08:07:49 PM PDT 24
Finished Aug 02 08:08:21 PM PDT 24
Peak memory 575900 kb
Host smart-63dbdcb6-0253-452d-a684-df6534dc46a1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426914809 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_random.426914809
Directory /workspace/88.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_random.476633870
Short name T2359
Test name
Test status
Simulation time 451431913 ps
CPU time 42.04 seconds
Started Aug 02 08:07:51 PM PDT 24
Finished Aug 02 08:08:33 PM PDT 24
Peak memory 575876 kb
Host smart-c485ef67-1669-4fee-8d49-20e9da2658f6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476633870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random.476633870
Directory /workspace/88.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_random_large_delays.1563335973
Short name T2628
Test name
Test status
Simulation time 40521934664 ps
CPU time 409.15 seconds
Started Aug 02 08:07:49 PM PDT 24
Finished Aug 02 08:14:39 PM PDT 24
Peak memory 576784 kb
Host smart-88efedcc-75c0-41c9-a39b-c761959af60a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563335973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_large_delays.1563335973
Directory /workspace/88.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.1460272916
Short name T463
Test name
Test status
Simulation time 68639412053 ps
CPU time 1276.21 seconds
Started Aug 02 08:07:51 PM PDT 24
Finished Aug 02 08:29:07 PM PDT 24
Peak memory 575972 kb
Host smart-a38ba65c-68a6-4890-b39a-a256adcca1aa
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460272916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_slow_rsp.1460272916
Directory /workspace/88.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_random_zero_delays.1042019693
Short name T614
Test name
Test status
Simulation time 550525713 ps
CPU time 49.24 seconds
Started Aug 02 08:07:50 PM PDT 24
Finished Aug 02 08:08:39 PM PDT 24
Peak memory 575820 kb
Host smart-6defad8e-3273-43e0-82f7-97f7171b3c4e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042019693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_zero_del
ays.1042019693
Directory /workspace/88.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_same_source.651347380
Short name T595
Test name
Test status
Simulation time 92950038 ps
CPU time 10.35 seconds
Started Aug 02 08:07:49 PM PDT 24
Finished Aug 02 08:07:59 PM PDT 24
Peak memory 575864 kb
Host smart-1bf65cc1-698e-4861-810a-e01d429cebc5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651347380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_same_source.651347380
Directory /workspace/88.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_smoke.223703474
Short name T1499
Test name
Test status
Simulation time 163560366 ps
CPU time 7.59 seconds
Started Aug 02 08:07:49 PM PDT 24
Finished Aug 02 08:07:57 PM PDT 24
Peak memory 573908 kb
Host smart-20d136f9-446e-4265-876f-306ed2379ebc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223703474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke.223703474
Directory /workspace/88.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.1684385348
Short name T587
Test name
Test status
Simulation time 7343852828 ps
CPU time 73.8 seconds
Started Aug 02 08:07:47 PM PDT 24
Finished Aug 02 08:09:01 PM PDT 24
Peak memory 573924 kb
Host smart-3a590efc-ad4a-45f4-b305-6e8c82f3cd70
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684385348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_large_delays.1684385348
Directory /workspace/88.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.1508756776
Short name T2785
Test name
Test status
Simulation time 4663568125 ps
CPU time 78.21 seconds
Started Aug 02 08:07:49 PM PDT 24
Finished Aug 02 08:09:07 PM PDT 24
Peak memory 573996 kb
Host smart-e5d7104b-3e91-464d-bab5-fc4592f91ee6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508756776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_slow_rsp.1508756776
Directory /workspace/88.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_smoke_zero_delays.2017415672
Short name T1886
Test name
Test status
Simulation time 49778657 ps
CPU time 6.54 seconds
Started Aug 02 08:07:50 PM PDT 24
Finished Aug 02 08:07:57 PM PDT 24
Peak memory 573820 kb
Host smart-366264dc-3890-47fd-847e-7714a9086056
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017415672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_zero_delay
s.2017415672
Directory /workspace/88.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_stress_all.1191220273
Short name T2838
Test name
Test status
Simulation time 316628901 ps
CPU time 23.64 seconds
Started Aug 02 08:07:50 PM PDT 24
Finished Aug 02 08:08:14 PM PDT 24
Peak memory 575956 kb
Host smart-bda28e02-6574-4027-8f9a-6fa7d9b03913
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191220273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all.1191220273
Directory /workspace/88.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.3005403549
Short name T1904
Test name
Test status
Simulation time 1701985980 ps
CPU time 109.72 seconds
Started Aug 02 08:08:05 PM PDT 24
Finished Aug 02 08:09:55 PM PDT 24
Peak memory 576180 kb
Host smart-12c439e4-025d-44d9-bef0-cf12fe82e9c8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005403549 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_error.3005403549
Directory /workspace/88.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.2688351938
Short name T2071
Test name
Test status
Simulation time 7395949031 ps
CPU time 422.51 seconds
Started Aug 02 08:07:48 PM PDT 24
Finished Aug 02 08:14:51 PM PDT 24
Peak memory 576804 kb
Host smart-d1187b23-65d7-493d-894b-370096d5dd15
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688351938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all
_with_rand_reset.2688351938
Directory /workspace/88.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.788574063
Short name T647
Test name
Test status
Simulation time 2619966531 ps
CPU time 192.9 seconds
Started Aug 02 08:08:06 PM PDT 24
Finished Aug 02 08:11:19 PM PDT 24
Peak memory 575960 kb
Host smart-af76816d-ec88-4347-872a-d8f6d55afb10
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788574063 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all
_with_reset_error.788574063
Directory /workspace/88.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_unmapped_addr.1407025257
Short name T1851
Test name
Test status
Simulation time 1322140949 ps
CPU time 52.17 seconds
Started Aug 02 08:07:48 PM PDT 24
Finished Aug 02 08:08:41 PM PDT 24
Peak memory 575872 kb
Host smart-b1491cf3-6852-497b-b6fe-37c0ed8ed2db
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407025257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_unmapped_addr.1407025257
Directory /workspace/88.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_access_same_device.3834121474
Short name T859
Test name
Test status
Simulation time 414639932 ps
CPU time 32.61 seconds
Started Aug 02 08:08:06 PM PDT 24
Finished Aug 02 08:08:38 PM PDT 24
Peak memory 575788 kb
Host smart-26da416b-2fbd-43fb-a6c7-105a2ade4c19
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834121474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device
.3834121474
Directory /workspace/89.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.712636199
Short name T2665
Test name
Test status
Simulation time 97597848405 ps
CPU time 1858.78 seconds
Started Aug 02 08:08:04 PM PDT 24
Finished Aug 02 08:39:03 PM PDT 24
Peak memory 576100 kb
Host smart-570df9ee-0631-4e11-a855-250d63888d3a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712636199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_d
evice_slow_rsp.712636199
Directory /workspace/89.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.2925541807
Short name T1925
Test name
Test status
Simulation time 188154858 ps
CPU time 19.64 seconds
Started Aug 02 08:08:05 PM PDT 24
Finished Aug 02 08:08:25 PM PDT 24
Peak memory 576036 kb
Host smart-46f21980-f849-48a1-aed7-0efadfb18c27
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925541807 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_and_unmapped_add
r.2925541807
Directory /workspace/89.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_error_random.3297598150
Short name T2366
Test name
Test status
Simulation time 356762220 ps
CPU time 28.48 seconds
Started Aug 02 08:08:04 PM PDT 24
Finished Aug 02 08:08:32 PM PDT 24
Peak memory 575960 kb
Host smart-bdc60172-3b07-451c-bed6-c98b382f175c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297598150 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_random.3297598150
Directory /workspace/89.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_random.135190452
Short name T513
Test name
Test status
Simulation time 107931016 ps
CPU time 11.84 seconds
Started Aug 02 08:08:03 PM PDT 24
Finished Aug 02 08:08:15 PM PDT 24
Peak memory 575936 kb
Host smart-973b7ef5-c1f9-401b-97aa-769d406ef422
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135190452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random.135190452
Directory /workspace/89.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_random_large_delays.2490084404
Short name T1634
Test name
Test status
Simulation time 100085441753 ps
CPU time 1072.54 seconds
Started Aug 02 08:08:03 PM PDT 24
Finished Aug 02 08:25:56 PM PDT 24
Peak memory 576024 kb
Host smart-e42929da-af2d-4158-a660-a6e8b68e63d6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490084404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_large_delays.2490084404
Directory /workspace/89.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_random_slow_rsp.259452465
Short name T2553
Test name
Test status
Simulation time 15086983945 ps
CPU time 259.97 seconds
Started Aug 02 08:08:04 PM PDT 24
Finished Aug 02 08:12:24 PM PDT 24
Peak memory 575832 kb
Host smart-14578bae-ec27-48a9-9310-1d362e0100e4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259452465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_slow_rsp.259452465
Directory /workspace/89.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_random_zero_delays.463990713
Short name T1489
Test name
Test status
Simulation time 41168939 ps
CPU time 6.03 seconds
Started Aug 02 08:08:05 PM PDT 24
Finished Aug 02 08:08:11 PM PDT 24
Peak memory 574496 kb
Host smart-85191d05-8aca-4758-b25a-383ea4b9bbf5
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463990713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_zero_dela
ys.463990713
Directory /workspace/89.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_same_source.1873521994
Short name T1822
Test name
Test status
Simulation time 183697487 ps
CPU time 15.75 seconds
Started Aug 02 08:08:03 PM PDT 24
Finished Aug 02 08:08:19 PM PDT 24
Peak memory 575876 kb
Host smart-04ffe07a-baad-416d-8137-68cf450dfaf7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873521994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_same_source.1873521994
Directory /workspace/89.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_smoke.1194052955
Short name T2255
Test name
Test status
Simulation time 42900740 ps
CPU time 6.1 seconds
Started Aug 02 08:08:03 PM PDT 24
Finished Aug 02 08:08:10 PM PDT 24
Peak memory 574556 kb
Host smart-24b6e843-f5e6-4b15-8fda-fba23f0acd17
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194052955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke.1194052955
Directory /workspace/89.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_smoke_large_delays.961872712
Short name T574
Test name
Test status
Simulation time 7718377787 ps
CPU time 83.03 seconds
Started Aug 02 08:08:01 PM PDT 24
Finished Aug 02 08:09:24 PM PDT 24
Peak memory 574716 kb
Host smart-e9d6df70-4f0f-4152-bd2f-e7934727c7e4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961872712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_large_delays.961872712
Directory /workspace/89.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.3985290456
Short name T1481
Test name
Test status
Simulation time 4972094117 ps
CPU time 86.13 seconds
Started Aug 02 08:08:03 PM PDT 24
Finished Aug 02 08:09:29 PM PDT 24
Peak memory 573896 kb
Host smart-143700ac-e21a-4458-9f2c-c26ba072c7ad
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985290456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_slow_rsp.3985290456
Directory /workspace/89.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.1448072492
Short name T2275
Test name
Test status
Simulation time 38619170 ps
CPU time 6.17 seconds
Started Aug 02 08:08:03 PM PDT 24
Finished Aug 02 08:08:10 PM PDT 24
Peak memory 573812 kb
Host smart-003c9183-d0bc-4ad3-98ad-cd618949b09f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448072492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_zero_delay
s.1448072492
Directory /workspace/89.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_stress_all.4252960404
Short name T2330
Test name
Test status
Simulation time 15822039656 ps
CPU time 618.91 seconds
Started Aug 02 08:08:05 PM PDT 24
Finished Aug 02 08:18:24 PM PDT 24
Peak memory 575896 kb
Host smart-074b0e29-e510-40f6-8f54-75b6281ba08e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252960404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all.4252960404
Directory /workspace/89.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.445410297
Short name T1525
Test name
Test status
Simulation time 1599481997 ps
CPU time 123.23 seconds
Started Aug 02 08:08:02 PM PDT 24
Finished Aug 02 08:10:05 PM PDT 24
Peak memory 576064 kb
Host smart-d49c95ef-9785-45a1-835d-3ac1614655d2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445410297 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_error.445410297
Directory /workspace/89.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.654025458
Short name T1570
Test name
Test status
Simulation time 1400585305 ps
CPU time 304.24 seconds
Started Aug 02 08:08:03 PM PDT 24
Finished Aug 02 08:13:08 PM PDT 24
Peak memory 575856 kb
Host smart-74d51711-1696-4143-a0b3-d11f49349fff
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654025458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_
with_rand_reset.654025458
Directory /workspace/89.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.2688082512
Short name T2644
Test name
Test status
Simulation time 9282652576 ps
CPU time 433.35 seconds
Started Aug 02 08:08:05 PM PDT 24
Finished Aug 02 08:15:18 PM PDT 24
Peak memory 576792 kb
Host smart-ddce6138-75dd-4897-b169-b7187e51d05b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688082512 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_al
l_with_reset_error.2688082512
Directory /workspace/89.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.1323463443
Short name T1912
Test name
Test status
Simulation time 744202144 ps
CPU time 33.98 seconds
Started Aug 02 08:08:04 PM PDT 24
Finished Aug 02 08:08:38 PM PDT 24
Peak memory 575980 kb
Host smart-b7a71833-dedb-4cb1-91ea-2f7d75e793a1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323463443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_unmapped_addr.1323463443
Directory /workspace/89.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.2942823539
Short name T454
Test name
Test status
Simulation time 6346599880 ps
CPU time 481.18 seconds
Started Aug 02 07:53:48 PM PDT 24
Finished Aug 02 08:01:50 PM PDT 24
Peak memory 638696 kb
Host smart-48d61a02-9fe5-4aca-be26-421ace8217a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942823539 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.chip_csr_mem_rw_with_rand_reset.2942823539
Directory /workspace/9.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.chip_csr_rw.1163711226
Short name T2260
Test name
Test status
Simulation time 4492384860 ps
CPU time 383.56 seconds
Started Aug 02 07:53:53 PM PDT 24
Finished Aug 02 08:00:17 PM PDT 24
Peak memory 597548 kb
Host smart-4d77f585-4e58-4de9-a1a0-67d882b7ea1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163711226 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_rw.1163711226
Directory /workspace/9.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.chip_tl_errors.3880665786
Short name T694
Test name
Test status
Simulation time 3407861979 ps
CPU time 183.49 seconds
Started Aug 02 07:53:29 PM PDT 24
Finished Aug 02 07:56:33 PM PDT 24
Peak memory 603736 kb
Host smart-830430e6-34b1-42bf-9143-3460509c983c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880665786 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_tl_errors.3880665786
Directory /workspace/9.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_access_same_device.3695673683
Short name T2338
Test name
Test status
Simulation time 596701369 ps
CPU time 23.7 seconds
Started Aug 02 07:53:51 PM PDT 24
Finished Aug 02 07:54:15 PM PDT 24
Peak memory 575928 kb
Host smart-30562c6f-4ac2-42bf-ae01-845803102708
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695673683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.
3695673683
Directory /workspace/9.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.2556777461
Short name T2901
Test name
Test status
Simulation time 155467023171 ps
CPU time 2702.29 seconds
Started Aug 02 07:53:53 PM PDT 24
Finished Aug 02 08:38:55 PM PDT 24
Peak memory 576052 kb
Host smart-d4263f19-38c0-45d8-810c-52ff302d29f9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556777461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_d
evice_slow_rsp.2556777461
Directory /workspace/9.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.1122940977
Short name T2393
Test name
Test status
Simulation time 25959298 ps
CPU time 5.17 seconds
Started Aug 02 07:53:50 PM PDT 24
Finished Aug 02 07:53:56 PM PDT 24
Peak memory 574472 kb
Host smart-6a674a1c-dbf9-41ae-970d-deb9cc3fc954
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122940977 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr
.1122940977
Directory /workspace/9.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_error_random.1445758527
Short name T1418
Test name
Test status
Simulation time 850935745 ps
CPU time 31.71 seconds
Started Aug 02 07:53:50 PM PDT 24
Finished Aug 02 07:54:22 PM PDT 24
Peak memory 575652 kb
Host smart-90b517db-6c79-4c33-a345-c9b655cd04a0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445758527 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.1445758527
Directory /workspace/9.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_random.1852921579
Short name T1756
Test name
Test status
Simulation time 454688318 ps
CPU time 36.16 seconds
Started Aug 02 07:53:51 PM PDT 24
Finished Aug 02 07:54:27 PM PDT 24
Peak memory 575796 kb
Host smart-afa93a8c-f00e-456f-ba65-8cf153a9fce7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852921579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random.1852921579
Directory /workspace/9.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_random_large_delays.3317661076
Short name T2698
Test name
Test status
Simulation time 84292964955 ps
CPU time 952.04 seconds
Started Aug 02 07:53:50 PM PDT 24
Finished Aug 02 08:09:43 PM PDT 24
Peak memory 575880 kb
Host smart-3a23ffa5-43f6-4a3c-b674-6f9c45e8af7e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317661076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.3317661076
Directory /workspace/9.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_random_slow_rsp.50249702
Short name T1505
Test name
Test status
Simulation time 7340247492 ps
CPU time 113.77 seconds
Started Aug 02 07:53:49 PM PDT 24
Finished Aug 02 07:55:43 PM PDT 24
Peak memory 575932 kb
Host smart-e1897e3d-8783-4a92-8ca9-4645ce199b82
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50249702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.50249702
Directory /workspace/9.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_random_zero_delays.4052991435
Short name T2395
Test name
Test status
Simulation time 65953240 ps
CPU time 8.78 seconds
Started Aug 02 07:53:50 PM PDT 24
Finished Aug 02 07:53:59 PM PDT 24
Peak memory 575876 kb
Host smart-06347db4-0c15-4170-95e0-202e66c14622
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052991435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_dela
ys.4052991435
Directory /workspace/9.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_same_source.425606445
Short name T2816
Test name
Test status
Simulation time 1803345056 ps
CPU time 51.06 seconds
Started Aug 02 07:53:48 PM PDT 24
Finished Aug 02 07:54:39 PM PDT 24
Peak memory 575860 kb
Host smart-58d2de69-cdd7-4ff9-b743-0bbf1a05539a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425606445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.425606445
Directory /workspace/9.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_smoke.4109419403
Short name T2390
Test name
Test status
Simulation time 139652335 ps
CPU time 7.72 seconds
Started Aug 02 07:53:34 PM PDT 24
Finished Aug 02 07:53:42 PM PDT 24
Peak memory 574520 kb
Host smart-688f226d-67fb-4e43-829f-a42d06eb2242
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109419403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.4109419403
Directory /workspace/9.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_smoke_large_delays.1430529977
Short name T2651
Test name
Test status
Simulation time 8591216746 ps
CPU time 87.2 seconds
Started Aug 02 07:53:49 PM PDT 24
Finished Aug 02 07:55:16 PM PDT 24
Peak memory 574592 kb
Host smart-5b0d92a2-c566-49d9-ba81-c6fb7df96dea
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430529977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.1430529977
Directory /workspace/9.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.3666769637
Short name T2147
Test name
Test status
Simulation time 4856241705 ps
CPU time 81.87 seconds
Started Aug 02 07:53:53 PM PDT 24
Finished Aug 02 07:55:15 PM PDT 24
Peak memory 573892 kb
Host smart-1a6121e9-ff81-4e2c-b1fb-003231bcd32c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666769637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.3666769637
Directory /workspace/9.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_smoke_zero_delays.882979775
Short name T1821
Test name
Test status
Simulation time 42364812 ps
CPU time 5.5 seconds
Started Aug 02 07:53:30 PM PDT 24
Finished Aug 02 07:53:36 PM PDT 24
Peak memory 574600 kb
Host smart-9978a6f9-bbf2-4aec-a3f4-7dc07da2cfa3
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882979775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.
882979775
Directory /workspace/9.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_stress_all.1382300254
Short name T2748
Test name
Test status
Simulation time 1462353737 ps
CPU time 49.62 seconds
Started Aug 02 07:53:50 PM PDT 24
Finished Aug 02 07:54:40 PM PDT 24
Peak memory 576120 kb
Host smart-ff32bdd5-2b42-4c82-9b13-0457ed5380c5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382300254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.1382300254
Directory /workspace/9.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_error.2360242338
Short name T2922
Test name
Test status
Simulation time 1371284880 ps
CPU time 43.11 seconds
Started Aug 02 07:53:51 PM PDT 24
Finished Aug 02 07:54:34 PM PDT 24
Peak memory 575784 kb
Host smart-deaa320f-a465-455c-8484-f7bde7fdb264
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360242338 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.2360242338
Directory /workspace/9.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.4274805208
Short name T589
Test name
Test status
Simulation time 4562364943 ps
CPU time 483.7 seconds
Started Aug 02 07:53:54 PM PDT 24
Finished Aug 02 08:01:58 PM PDT 24
Peak memory 576748 kb
Host smart-b3503bd6-8b9d-416c-8787-4adf4f6a894e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274805208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_
with_rand_reset.4274805208
Directory /workspace/9.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.2185572012
Short name T1674
Test name
Test status
Simulation time 2305078013 ps
CPU time 198.46 seconds
Started Aug 02 07:53:51 PM PDT 24
Finished Aug 02 07:57:09 PM PDT 24
Peak memory 576768 kb
Host smart-28f04db8-cfd0-438c-8560-894fa95608d5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185572012 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all
_with_reset_error.2185572012
Directory /workspace/9.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.3197827441
Short name T2386
Test name
Test status
Simulation time 366086986 ps
CPU time 18.39 seconds
Started Aug 02 07:53:49 PM PDT 24
Finished Aug 02 07:54:08 PM PDT 24
Peak memory 575936 kb
Host smart-5e760399-5a0c-4242-9fb4-f9e7e0e86169
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197827441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.3197827441
Directory /workspace/9.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_access_same_device.2877497608
Short name T1814
Test name
Test status
Simulation time 1057262396 ps
CPU time 44.23 seconds
Started Aug 02 08:08:17 PM PDT 24
Finished Aug 02 08:09:01 PM PDT 24
Peak memory 576032 kb
Host smart-28f1fe31-83e9-4378-b4c7-002018fa25fe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877497608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device
.2877497608
Directory /workspace/90.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.2342128882
Short name T637
Test name
Test status
Simulation time 94173635192 ps
CPU time 1751.12 seconds
Started Aug 02 08:08:19 PM PDT 24
Finished Aug 02 08:37:30 PM PDT 24
Peak memory 575964 kb
Host smart-816e1890-38aa-42fd-b81e-758f44712e6d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342128882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_
device_slow_rsp.2342128882
Directory /workspace/90.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.2457046559
Short name T2744
Test name
Test status
Simulation time 315759235 ps
CPU time 33.35 seconds
Started Aug 02 08:08:23 PM PDT 24
Finished Aug 02 08:08:56 PM PDT 24
Peak memory 575856 kb
Host smart-65c986b2-25db-4b06-bb0c-16746749b116
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457046559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_and_unmapped_add
r.2457046559
Directory /workspace/90.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_error_random.1514229892
Short name T1490
Test name
Test status
Simulation time 1268482190 ps
CPU time 41.17 seconds
Started Aug 02 08:08:24 PM PDT 24
Finished Aug 02 08:09:05 PM PDT 24
Peak memory 575992 kb
Host smart-9d23dc6c-198c-47e3-b998-4764fd131c0e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514229892 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_random.1514229892
Directory /workspace/90.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_random.2372670275
Short name T2685
Test name
Test status
Simulation time 1688208803 ps
CPU time 54.63 seconds
Started Aug 02 08:08:17 PM PDT 24
Finished Aug 02 08:09:12 PM PDT 24
Peak memory 575920 kb
Host smart-8df393e1-67c3-421e-8ac6-875f9fefb5b1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372670275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random.2372670275
Directory /workspace/90.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_random_large_delays.3722749505
Short name T617
Test name
Test status
Simulation time 22045263102 ps
CPU time 224.59 seconds
Started Aug 02 08:08:19 PM PDT 24
Finished Aug 02 08:12:04 PM PDT 24
Peak memory 576000 kb
Host smart-e938848b-23d7-4c20-b7aa-2f558f9bd947
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722749505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_large_delays.3722749505
Directory /workspace/90.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_random_slow_rsp.3841057291
Short name T1916
Test name
Test status
Simulation time 55089789925 ps
CPU time 926.83 seconds
Started Aug 02 08:08:16 PM PDT 24
Finished Aug 02 08:23:43 PM PDT 24
Peak memory 575852 kb
Host smart-8170994d-22f4-4305-83d2-2ebd09788a3f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841057291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_slow_rsp.3841057291
Directory /workspace/90.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.2741851746
Short name T1582
Test name
Test status
Simulation time 69758488 ps
CPU time 8.3 seconds
Started Aug 02 08:08:18 PM PDT 24
Finished Aug 02 08:08:26 PM PDT 24
Peak memory 575820 kb
Host smart-5e7efe64-4332-42af-ae8d-de5909bb39d8
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741851746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_zero_del
ays.2741851746
Directory /workspace/90.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_same_source.3019473753
Short name T643
Test name
Test status
Simulation time 187793517 ps
CPU time 15.77 seconds
Started Aug 02 08:08:19 PM PDT 24
Finished Aug 02 08:08:35 PM PDT 24
Peak memory 575724 kb
Host smart-e81d4e83-971f-48cf-9974-0df88f48f11c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019473753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_same_source.3019473753
Directory /workspace/90.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_smoke.9373263
Short name T1550
Test name
Test status
Simulation time 204663031 ps
CPU time 8.9 seconds
Started Aug 02 08:08:04 PM PDT 24
Finished Aug 02 08:08:13 PM PDT 24
Peak memory 573788 kb
Host smart-a2aca069-a073-4dfa-a623-6f26c3ca79a1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9373263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke.9373263
Directory /workspace/90.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_smoke_large_delays.762576317
Short name T2146
Test name
Test status
Simulation time 9235820677 ps
CPU time 94.52 seconds
Started Aug 02 08:08:17 PM PDT 24
Finished Aug 02 08:09:51 PM PDT 24
Peak memory 574644 kb
Host smart-72da81b5-d4ab-410b-851b-0cdd6c3046a4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762576317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_large_delays.762576317
Directory /workspace/90.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.1397470533
Short name T2309
Test name
Test status
Simulation time 3554146343 ps
CPU time 62.1 seconds
Started Aug 02 08:08:19 PM PDT 24
Finished Aug 02 08:09:22 PM PDT 24
Peak memory 573812 kb
Host smart-bfb05113-e0f9-4e9d-8c5c-71a699e8918c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397470533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_slow_rsp.1397470533
Directory /workspace/90.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_smoke_zero_delays.311486374
Short name T2715
Test name
Test status
Simulation time 50058660 ps
CPU time 6.17 seconds
Started Aug 02 08:08:17 PM PDT 24
Finished Aug 02 08:08:23 PM PDT 24
Peak memory 574544 kb
Host smart-9bab062d-0653-453a-a097-8a591bcc6440
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311486374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_zero_delays
.311486374
Directory /workspace/90.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_stress_all.4252689830
Short name T1758
Test name
Test status
Simulation time 6308951201 ps
CPU time 224.05 seconds
Started Aug 02 08:08:17 PM PDT 24
Finished Aug 02 08:12:01 PM PDT 24
Peak memory 576900 kb
Host smart-0a44044a-df13-45ab-800c-afc1cd56c4e1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252689830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all.4252689830
Directory /workspace/90.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.4168577063
Short name T2387
Test name
Test status
Simulation time 9447888659 ps
CPU time 335 seconds
Started Aug 02 08:08:18 PM PDT 24
Finished Aug 02 08:13:53 PM PDT 24
Peak memory 576740 kb
Host smart-d42dc912-3cd6-4730-b228-ea3a55dfdfc2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168577063 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_error.4168577063
Directory /workspace/90.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.1401645219
Short name T2735
Test name
Test status
Simulation time 526391423 ps
CPU time 200.47 seconds
Started Aug 02 08:08:19 PM PDT 24
Finished Aug 02 08:11:40 PM PDT 24
Peak memory 576740 kb
Host smart-82d25fbd-bce5-49fa-81f6-e93f23a48db6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401645219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all
_with_rand_reset.1401645219
Directory /workspace/90.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.2171155901
Short name T892
Test name
Test status
Simulation time 339672082 ps
CPU time 113.11 seconds
Started Aug 02 08:08:17 PM PDT 24
Finished Aug 02 08:10:10 PM PDT 24
Peak memory 575904 kb
Host smart-41c18b8a-db3f-4c71-ad67-5feaf03fe3ec
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171155901 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_al
l_with_reset_error.2171155901
Directory /workspace/90.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_unmapped_addr.2754159978
Short name T1511
Test name
Test status
Simulation time 184718389 ps
CPU time 22.86 seconds
Started Aug 02 08:08:19 PM PDT 24
Finished Aug 02 08:08:42 PM PDT 24
Peak memory 575884 kb
Host smart-2461b635-b78f-412f-a958-85a24db354ab
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754159978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_unmapped_addr.2754159978
Directory /workspace/90.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_access_same_device.979296100
Short name T1992
Test name
Test status
Simulation time 268361078 ps
CPU time 19.74 seconds
Started Aug 02 08:08:19 PM PDT 24
Finished Aug 02 08:08:38 PM PDT 24
Peak memory 575904 kb
Host smart-f08bd331-011b-4c63-a8ae-fb62850843be
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979296100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device.
979296100
Directory /workspace/91.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.4286633295
Short name T561
Test name
Test status
Simulation time 141283292264 ps
CPU time 2513.77 seconds
Started Aug 02 08:08:17 PM PDT 24
Finished Aug 02 08:50:11 PM PDT 24
Peak memory 576052 kb
Host smart-6955a4ec-63a8-4b0a-84fe-ab4907f9d49a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286633295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_
device_slow_rsp.4286633295
Directory /workspace/91.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.4193812817
Short name T1677
Test name
Test status
Simulation time 1017824073 ps
CPU time 40.03 seconds
Started Aug 02 08:08:46 PM PDT 24
Finished Aug 02 08:09:26 PM PDT 24
Peak memory 575896 kb
Host smart-7544b5bc-b6e2-4643-8892-e29e8e672136
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193812817 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_and_unmapped_add
r.4193812817
Directory /workspace/91.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_error_random.2707776034
Short name T1420
Test name
Test status
Simulation time 587668902 ps
CPU time 23.15 seconds
Started Aug 02 08:08:23 PM PDT 24
Finished Aug 02 08:08:46 PM PDT 24
Peak memory 575928 kb
Host smart-a00b3276-3bd2-47f5-902f-681922adcef2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707776034 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_random.2707776034
Directory /workspace/91.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_random.543617025
Short name T532
Test name
Test status
Simulation time 1622869090 ps
CPU time 56.75 seconds
Started Aug 02 08:08:23 PM PDT 24
Finished Aug 02 08:09:20 PM PDT 24
Peak memory 575788 kb
Host smart-b62aa506-2119-4a5a-9249-b7edafd040c5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543617025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random.543617025
Directory /workspace/91.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.1082947982
Short name T606
Test name
Test status
Simulation time 25608530304 ps
CPU time 270.8 seconds
Started Aug 02 08:08:18 PM PDT 24
Finished Aug 02 08:12:49 PM PDT 24
Peak memory 576016 kb
Host smart-d7c728b5-0293-48ac-8ded-2fc0d059acea
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082947982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_large_delays.1082947982
Directory /workspace/91.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_random_slow_rsp.3319504904
Short name T668
Test name
Test status
Simulation time 24720916651 ps
CPU time 430.93 seconds
Started Aug 02 08:08:17 PM PDT 24
Finished Aug 02 08:15:28 PM PDT 24
Peak memory 576052 kb
Host smart-cb6ca3c2-69b9-4f17-8cb0-444737e1411c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319504904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_slow_rsp.3319504904
Directory /workspace/91.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_random_zero_delays.500042001
Short name T2919
Test name
Test status
Simulation time 125382837 ps
CPU time 11.9 seconds
Started Aug 02 08:08:18 PM PDT 24
Finished Aug 02 08:08:30 PM PDT 24
Peak memory 575920 kb
Host smart-9e864105-bb7a-4127-94aa-526c7ac041a5
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500042001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_zero_dela
ys.500042001
Directory /workspace/91.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_same_source.3454713876
Short name T1996
Test name
Test status
Simulation time 1706108936 ps
CPU time 45.44 seconds
Started Aug 02 08:08:19 PM PDT 24
Finished Aug 02 08:09:04 PM PDT 24
Peak memory 575860 kb
Host smart-c787133c-2859-4019-b2ab-e99dfa304e86
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454713876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_same_source.3454713876
Directory /workspace/91.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_smoke.2907046116
Short name T2764
Test name
Test status
Simulation time 209157882 ps
CPU time 9.05 seconds
Started Aug 02 08:08:20 PM PDT 24
Finished Aug 02 08:08:29 PM PDT 24
Peak memory 573864 kb
Host smart-f29c3420-af37-4c2a-967d-3f125b732c37
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907046116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke.2907046116
Directory /workspace/91.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_smoke_large_delays.2377554961
Short name T2658
Test name
Test status
Simulation time 8534266464 ps
CPU time 90.85 seconds
Started Aug 02 08:08:17 PM PDT 24
Finished Aug 02 08:09:48 PM PDT 24
Peak memory 574528 kb
Host smart-f61ac423-d7d4-4774-beda-c8a505a9cd40
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377554961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_large_delays.2377554961
Directory /workspace/91.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.486196415
Short name T1833
Test name
Test status
Simulation time 4161071992 ps
CPU time 67.4 seconds
Started Aug 02 08:08:16 PM PDT 24
Finished Aug 02 08:09:23 PM PDT 24
Peak memory 574520 kb
Host smart-8551235a-70c8-4460-98fd-454853326b56
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486196415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_slow_rsp.486196415
Directory /workspace/91.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.935268690
Short name T2117
Test name
Test status
Simulation time 48010663 ps
CPU time 6.31 seconds
Started Aug 02 08:08:18 PM PDT 24
Finished Aug 02 08:08:24 PM PDT 24
Peak memory 574540 kb
Host smart-3d6b14c6-d213-40f3-bfbf-3fdf6a8aa81c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935268690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_zero_delays
.935268690
Directory /workspace/91.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_stress_all.966385830
Short name T1840
Test name
Test status
Simulation time 1208682466 ps
CPU time 95.11 seconds
Started Aug 02 08:08:43 PM PDT 24
Finished Aug 02 08:10:18 PM PDT 24
Peak memory 576032 kb
Host smart-589116ae-1004-49c9-b014-18be46571d32
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966385830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all.966385830
Directory /workspace/91.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.3965060211
Short name T2711
Test name
Test status
Simulation time 29061593 ps
CPU time 32.39 seconds
Started Aug 02 08:08:41 PM PDT 24
Finished Aug 02 08:09:14 PM PDT 24
Peak memory 574752 kb
Host smart-5d80e6ba-f020-44e3-9b35-eb3b376115f6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965060211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all
_with_rand_reset.3965060211
Directory /workspace/91.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_unmapped_addr.2861206743
Short name T2324
Test name
Test status
Simulation time 387714921 ps
CPU time 18.52 seconds
Started Aug 02 08:08:45 PM PDT 24
Finished Aug 02 08:09:04 PM PDT 24
Peak memory 575924 kb
Host smart-8781e91f-f847-4180-9ba0-e10c71283055
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861206743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_unmapped_addr.2861206743
Directory /workspace/91.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_access_same_device.174893162
Short name T2529
Test name
Test status
Simulation time 1740664450 ps
CPU time 70.61 seconds
Started Aug 02 08:08:41 PM PDT 24
Finished Aug 02 08:09:52 PM PDT 24
Peak memory 575800 kb
Host smart-ca54c04f-4d1a-46fd-adaa-4f50b9d87837
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174893162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device.
174893162
Directory /workspace/92.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.3966050173
Short name T1974
Test name
Test status
Simulation time 65818609180 ps
CPU time 1283.39 seconds
Started Aug 02 08:08:44 PM PDT 24
Finished Aug 02 08:30:08 PM PDT 24
Peak memory 576052 kb
Host smart-7180c639-e438-44c3-8bbd-71030c4c219b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966050173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_
device_slow_rsp.3966050173
Directory /workspace/92.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.380103758
Short name T1454
Test name
Test status
Simulation time 288286674 ps
CPU time 31.48 seconds
Started Aug 02 08:08:41 PM PDT 24
Finished Aug 02 08:09:12 PM PDT 24
Peak memory 575704 kb
Host smart-484c7108-8273-44b0-9e84-4889e0b0a8e8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380103758 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_and_unmapped_addr
.380103758
Directory /workspace/92.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_error_random.859240347
Short name T2743
Test name
Test status
Simulation time 150670995 ps
CPU time 8.05 seconds
Started Aug 02 08:08:40 PM PDT 24
Finished Aug 02 08:08:49 PM PDT 24
Peak memory 573880 kb
Host smart-dbafd347-604a-4d4a-a157-7fd46159b602
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859240347 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_random.859240347
Directory /workspace/92.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_random.370289349
Short name T466
Test name
Test status
Simulation time 1684567472 ps
CPU time 51.21 seconds
Started Aug 02 08:08:41 PM PDT 24
Finished Aug 02 08:09:33 PM PDT 24
Peak memory 575920 kb
Host smart-3c671eef-10e2-4481-b938-372ba479d40b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370289349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random.370289349
Directory /workspace/92.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_random_large_delays.4142548867
Short name T511
Test name
Test status
Simulation time 48938375012 ps
CPU time 584.7 seconds
Started Aug 02 08:08:43 PM PDT 24
Finished Aug 02 08:18:28 PM PDT 24
Peak memory 576760 kb
Host smart-62755169-ed9a-4b8e-9b3d-37b78ce93a8b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142548867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_large_delays.4142548867
Directory /workspace/92.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_random_slow_rsp.1043924379
Short name T1933
Test name
Test status
Simulation time 49060220350 ps
CPU time 932.89 seconds
Started Aug 02 08:08:44 PM PDT 24
Finished Aug 02 08:24:17 PM PDT 24
Peak memory 575888 kb
Host smart-08915b9c-17b7-4d15-a4b7-7eca7c0ad180
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043924379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_slow_rsp.1043924379
Directory /workspace/92.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.4258977537
Short name T2794
Test name
Test status
Simulation time 633677618 ps
CPU time 54.53 seconds
Started Aug 02 08:08:40 PM PDT 24
Finished Aug 02 08:09:35 PM PDT 24
Peak memory 575960 kb
Host smart-aecaf556-cf8e-4aa6-8d82-87f81429a3c8
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258977537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_zero_del
ays.4258977537
Directory /workspace/92.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_same_source.3021920242
Short name T2674
Test name
Test status
Simulation time 903193257 ps
CPU time 27.13 seconds
Started Aug 02 08:08:43 PM PDT 24
Finished Aug 02 08:09:10 PM PDT 24
Peak memory 575844 kb
Host smart-cc36d196-4490-474f-b2f8-561351a934c5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021920242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_same_source.3021920242
Directory /workspace/92.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_smoke.1442973278
Short name T1730
Test name
Test status
Simulation time 202911989 ps
CPU time 8.34 seconds
Started Aug 02 08:08:45 PM PDT 24
Finished Aug 02 08:08:54 PM PDT 24
Peak memory 574504 kb
Host smart-cf2459ff-8450-4dce-9c7e-b68a6c06a998
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442973278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke.1442973278
Directory /workspace/92.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_smoke_large_delays.1412868177
Short name T1970
Test name
Test status
Simulation time 8946777083 ps
CPU time 87.13 seconds
Started Aug 02 08:08:44 PM PDT 24
Finished Aug 02 08:10:11 PM PDT 24
Peak memory 573960 kb
Host smart-4e56a211-9f41-4abc-ab4f-48ccbcf8a0f2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412868177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_large_delays.1412868177
Directory /workspace/92.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.3722689843
Short name T1486
Test name
Test status
Simulation time 5889071906 ps
CPU time 95.4 seconds
Started Aug 02 08:08:46 PM PDT 24
Finished Aug 02 08:10:21 PM PDT 24
Peak memory 573896 kb
Host smart-a8d9a947-cd4d-49fd-9745-934a1c03c4b9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722689843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_slow_rsp.3722689843
Directory /workspace/92.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.288704393
Short name T2817
Test name
Test status
Simulation time 46973349 ps
CPU time 6.26 seconds
Started Aug 02 08:08:41 PM PDT 24
Finished Aug 02 08:08:47 PM PDT 24
Peak memory 573848 kb
Host smart-07e2d493-61bb-4989-8e83-a6899fbff7d9
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288704393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_zero_delays
.288704393
Directory /workspace/92.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_stress_all.2664169428
Short name T1806
Test name
Test status
Simulation time 5887130103 ps
CPU time 179.36 seconds
Started Aug 02 08:08:44 PM PDT 24
Finished Aug 02 08:11:44 PM PDT 24
Peak memory 576088 kb
Host smart-1e880623-16c2-4d00-9e4b-711a4af90601
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664169428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all.2664169428
Directory /workspace/92.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_error.984590109
Short name T1849
Test name
Test status
Simulation time 7184592300 ps
CPU time 250.76 seconds
Started Aug 02 08:08:45 PM PDT 24
Finished Aug 02 08:12:56 PM PDT 24
Peak memory 576220 kb
Host smart-f700541b-f54c-4cb1-a5bd-8e728f3af521
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984590109 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_error.984590109
Directory /workspace/92.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.1665394278
Short name T2666
Test name
Test status
Simulation time 163656587 ps
CPU time 92.71 seconds
Started Aug 02 08:08:41 PM PDT 24
Finished Aug 02 08:10:14 PM PDT 24
Peak memory 575916 kb
Host smart-d36c9376-e1c6-4ade-b671-1c4b67c597bf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665394278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all
_with_rand_reset.1665394278
Directory /workspace/92.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.1140639726
Short name T2446
Test name
Test status
Simulation time 350281663 ps
CPU time 100.42 seconds
Started Aug 02 08:08:41 PM PDT 24
Finished Aug 02 08:10:22 PM PDT 24
Peak memory 575920 kb
Host smart-b9d089f1-6595-436a-b8f7-84187900c020
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140639726 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_al
l_with_reset_error.1140639726
Directory /workspace/92.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_unmapped_addr.4160180733
Short name T2351
Test name
Test status
Simulation time 175856150 ps
CPU time 20.5 seconds
Started Aug 02 08:08:46 PM PDT 24
Finished Aug 02 08:09:06 PM PDT 24
Peak memory 575868 kb
Host smart-2ae505e8-84ff-4683-b0b9-efea19f499bc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160180733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_unmapped_addr.4160180733
Directory /workspace/92.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_access_same_device.1310302409
Short name T2032
Test name
Test status
Simulation time 645172369 ps
CPU time 64.24 seconds
Started Aug 02 08:08:41 PM PDT 24
Finished Aug 02 08:09:45 PM PDT 24
Peak memory 575808 kb
Host smart-d2e01b96-3fbf-46df-b7a7-f9c26c30ab27
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310302409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device
.1310302409
Directory /workspace/93.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.3291390286
Short name T2334
Test name
Test status
Simulation time 42518772341 ps
CPU time 807.84 seconds
Started Aug 02 08:08:45 PM PDT 24
Finished Aug 02 08:22:14 PM PDT 24
Peak memory 576776 kb
Host smart-f64effff-138c-4bce-b96a-10783fb88a81
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291390286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_
device_slow_rsp.3291390286
Directory /workspace/93.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.4015134398
Short name T1482
Test name
Test status
Simulation time 525133165 ps
CPU time 21.13 seconds
Started Aug 02 08:09:08 PM PDT 24
Finished Aug 02 08:09:29 PM PDT 24
Peak memory 575912 kb
Host smart-0d896ada-b744-4834-a4e3-bc37e6109d8b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015134398 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_and_unmapped_add
r.4015134398
Directory /workspace/93.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_error_random.1147824138
Short name T2787
Test name
Test status
Simulation time 36667003 ps
CPU time 5.76 seconds
Started Aug 02 08:09:04 PM PDT 24
Finished Aug 02 08:09:09 PM PDT 24
Peak memory 573888 kb
Host smart-e6772026-2626-4f0c-9570-83a81d91561a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147824138 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_random.1147824138
Directory /workspace/93.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_random.1808602159
Short name T2604
Test name
Test status
Simulation time 1619032697 ps
CPU time 60.2 seconds
Started Aug 02 08:08:40 PM PDT 24
Finished Aug 02 08:09:41 PM PDT 24
Peak memory 575932 kb
Host smart-37ec21bc-6d24-40c7-8a29-1ae6db65dfdc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808602159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random.1808602159
Directory /workspace/93.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_random_large_delays.2337858191
Short name T1922
Test name
Test status
Simulation time 16017672172 ps
CPU time 156.04 seconds
Started Aug 02 08:08:46 PM PDT 24
Finished Aug 02 08:11:22 PM PDT 24
Peak memory 575996 kb
Host smart-7181c169-0885-4bc5-9e17-a69952469d1b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337858191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_large_delays.2337858191
Directory /workspace/93.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.290136677
Short name T593
Test name
Test status
Simulation time 15334958756 ps
CPU time 293.77 seconds
Started Aug 02 08:08:40 PM PDT 24
Finished Aug 02 08:13:34 PM PDT 24
Peak memory 575896 kb
Host smart-457e0890-b702-4bac-9595-43110bce0996
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290136677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_slow_rsp.290136677
Directory /workspace/93.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_random_zero_delays.3635397191
Short name T1424
Test name
Test status
Simulation time 155738045 ps
CPU time 15.52 seconds
Started Aug 02 08:08:44 PM PDT 24
Finished Aug 02 08:09:00 PM PDT 24
Peak memory 575784 kb
Host smart-55aacca6-9193-4ff4-ba35-e276446d32d1
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635397191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_zero_del
ays.3635397191
Directory /workspace/93.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_same_source.2896448222
Short name T1429
Test name
Test status
Simulation time 100690449 ps
CPU time 10.27 seconds
Started Aug 02 08:08:41 PM PDT 24
Finished Aug 02 08:08:52 PM PDT 24
Peak memory 575948 kb
Host smart-458b2f04-0af4-425e-b64d-58a6fc364bc7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896448222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_same_source.2896448222
Directory /workspace/93.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_smoke.99444423
Short name T1484
Test name
Test status
Simulation time 200083141 ps
CPU time 8.7 seconds
Started Aug 02 08:08:41 PM PDT 24
Finished Aug 02 08:08:50 PM PDT 24
Peak memory 573796 kb
Host smart-c74cddeb-7701-430b-95c1-5ae39024aff5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99444423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke.99444423
Directory /workspace/93.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_smoke_large_delays.833214138
Short name T2519
Test name
Test status
Simulation time 9353748084 ps
CPU time 95.79 seconds
Started Aug 02 08:08:42 PM PDT 24
Finished Aug 02 08:10:18 PM PDT 24
Peak memory 573940 kb
Host smart-496e10bf-8741-4df3-927b-5c575dbcb7af
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833214138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_large_delays.833214138
Directory /workspace/93.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.47059553
Short name T2693
Test name
Test status
Simulation time 5649108256 ps
CPU time 93.53 seconds
Started Aug 02 08:08:41 PM PDT 24
Finished Aug 02 08:10:15 PM PDT 24
Peak memory 573916 kb
Host smart-593c58e8-91a7-40df-8233-5c5fd110e79e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47059553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_slow_rsp.47059553
Directory /workspace/93.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_smoke_zero_delays.3928863018
Short name T1722
Test name
Test status
Simulation time 39847745 ps
CPU time 6.15 seconds
Started Aug 02 08:08:45 PM PDT 24
Finished Aug 02 08:08:51 PM PDT 24
Peak memory 573832 kb
Host smart-ce75789c-5dd0-4fb2-b67d-672448d6d61c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928863018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_zero_delay
s.3928863018
Directory /workspace/93.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_stress_all.2305206112
Short name T636
Test name
Test status
Simulation time 261292671 ps
CPU time 23.81 seconds
Started Aug 02 08:09:05 PM PDT 24
Finished Aug 02 08:09:28 PM PDT 24
Peak memory 575888 kb
Host smart-eee0a163-2cc6-440b-ad4c-a46dce238313
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305206112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all.2305206112
Directory /workspace/93.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.3453031842
Short name T2629
Test name
Test status
Simulation time 8715898897 ps
CPU time 313.33 seconds
Started Aug 02 08:09:08 PM PDT 24
Finished Aug 02 08:14:21 PM PDT 24
Peak memory 576024 kb
Host smart-1c2ad5c7-8454-4c43-b268-30bd673bc726
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453031842 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_error.3453031842
Directory /workspace/93.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.2937799693
Short name T2619
Test name
Test status
Simulation time 3523811279 ps
CPU time 512.82 seconds
Started Aug 02 08:09:05 PM PDT 24
Finished Aug 02 08:17:38 PM PDT 24
Peak memory 576780 kb
Host smart-3b4c9348-51d7-4194-9ce0-4fdc48f887b8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937799693 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_al
l_with_reset_error.2937799693
Directory /workspace/93.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_unmapped_addr.895010496
Short name T1592
Test name
Test status
Simulation time 268614723 ps
CPU time 32.79 seconds
Started Aug 02 08:09:11 PM PDT 24
Finished Aug 02 08:09:43 PM PDT 24
Peak memory 575836 kb
Host smart-ff829298-72c7-4c26-b43f-69058001c590
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895010496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_unmapped_addr.895010496
Directory /workspace/93.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_access_same_device.2551980464
Short name T858
Test name
Test status
Simulation time 792062791 ps
CPU time 27.87 seconds
Started Aug 02 08:09:07 PM PDT 24
Finished Aug 02 08:09:35 PM PDT 24
Peak memory 575792 kb
Host smart-b43e3117-89bb-46ee-a3a2-3c288506cb90
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551980464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device
.2551980464
Directory /workspace/94.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.2068377322
Short name T2895
Test name
Test status
Simulation time 69445083486 ps
CPU time 1355.6 seconds
Started Aug 02 08:09:12 PM PDT 24
Finished Aug 02 08:31:48 PM PDT 24
Peak memory 576060 kb
Host smart-5842bca3-9e5b-4573-bacd-65e87192f2e6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068377322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_
device_slow_rsp.2068377322
Directory /workspace/94.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.3920343904
Short name T1729
Test name
Test status
Simulation time 887897544 ps
CPU time 38.02 seconds
Started Aug 02 08:09:03 PM PDT 24
Finished Aug 02 08:09:41 PM PDT 24
Peak memory 575932 kb
Host smart-c7d22eb9-bc57-4f7a-868d-1d23d470cbc4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920343904 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_and_unmapped_add
r.3920343904
Directory /workspace/94.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_error_random.3303224165
Short name T2546
Test name
Test status
Simulation time 156023934 ps
CPU time 15.24 seconds
Started Aug 02 08:09:11 PM PDT 24
Finished Aug 02 08:09:26 PM PDT 24
Peak memory 575912 kb
Host smart-b16a0b21-2095-43e7-86b3-20e290cae12c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303224165 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_random.3303224165
Directory /workspace/94.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_random.4032221015
Short name T1785
Test name
Test status
Simulation time 1755965181 ps
CPU time 57.5 seconds
Started Aug 02 08:09:05 PM PDT 24
Finished Aug 02 08:10:02 PM PDT 24
Peak memory 575896 kb
Host smart-ebff3a6d-0d07-4a76-8fa2-a774bce3f3dd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032221015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random.4032221015
Directory /workspace/94.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_random_large_delays.1893615588
Short name T1657
Test name
Test status
Simulation time 95348859199 ps
CPU time 1104.21 seconds
Started Aug 02 08:09:04 PM PDT 24
Finished Aug 02 08:27:28 PM PDT 24
Peak memory 576092 kb
Host smart-e8e34ad8-333c-4722-81f4-eb69210eb128
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893615588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_large_delays.1893615588
Directory /workspace/94.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_random_slow_rsp.1917384334
Short name T2890
Test name
Test status
Simulation time 40342541376 ps
CPU time 680.94 seconds
Started Aug 02 08:09:08 PM PDT 24
Finished Aug 02 08:20:30 PM PDT 24
Peak memory 576040 kb
Host smart-1ede5ad8-83a8-4d27-b131-8a442549a0e5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917384334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_slow_rsp.1917384334
Directory /workspace/94.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_random_zero_delays.3524105258
Short name T1719
Test name
Test status
Simulation time 600039804 ps
CPU time 45.43 seconds
Started Aug 02 08:09:10 PM PDT 24
Finished Aug 02 08:09:55 PM PDT 24
Peak memory 575816 kb
Host smart-b1a39b53-b63b-46ac-a3c2-86fd5517122d
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524105258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_zero_del
ays.3524105258
Directory /workspace/94.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_same_source.1344984381
Short name T2720
Test name
Test status
Simulation time 194130198 ps
CPU time 16.2 seconds
Started Aug 02 08:09:03 PM PDT 24
Finished Aug 02 08:09:19 PM PDT 24
Peak memory 575848 kb
Host smart-90e00b75-928d-4002-be80-6e4e1869b43f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344984381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_same_source.1344984381
Directory /workspace/94.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_smoke.739205136
Short name T1989
Test name
Test status
Simulation time 190745966 ps
CPU time 8.62 seconds
Started Aug 02 08:09:07 PM PDT 24
Finished Aug 02 08:09:15 PM PDT 24
Peak memory 573824 kb
Host smart-07c69691-15a2-4946-9d9d-c770d8d063af
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739205136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke.739205136
Directory /workspace/94.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_smoke_large_delays.4201326264
Short name T1617
Test name
Test status
Simulation time 9545259275 ps
CPU time 105.31 seconds
Started Aug 02 08:09:07 PM PDT 24
Finished Aug 02 08:10:53 PM PDT 24
Peak memory 573940 kb
Host smart-e27a8d47-f04a-4cdb-b801-1b129ba639f1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201326264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_large_delays.4201326264
Directory /workspace/94.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.3245410610
Short name T1547
Test name
Test status
Simulation time 6279118188 ps
CPU time 106.12 seconds
Started Aug 02 08:09:05 PM PDT 24
Finished Aug 02 08:10:52 PM PDT 24
Peak memory 574652 kb
Host smart-952d1398-24ad-4be4-a968-cda2598bea26
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245410610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_slow_rsp.3245410610
Directory /workspace/94.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_smoke_zero_delays.3080873054
Short name T1472
Test name
Test status
Simulation time 41458939 ps
CPU time 6.29 seconds
Started Aug 02 08:09:04 PM PDT 24
Finished Aug 02 08:09:11 PM PDT 24
Peak memory 573736 kb
Host smart-fd6bd0fd-5a79-4f33-a043-f68cbc19c5ae
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080873054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_zero_delay
s.3080873054
Directory /workspace/94.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_stress_all.886445787
Short name T468
Test name
Test status
Simulation time 15633106188 ps
CPU time 650.33 seconds
Started Aug 02 08:09:04 PM PDT 24
Finished Aug 02 08:19:55 PM PDT 24
Peak memory 575948 kb
Host smart-cfd804a0-8c9b-4f6d-a280-f304a6223f9a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886445787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all.886445787
Directory /workspace/94.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_error.184379287
Short name T1652
Test name
Test status
Simulation time 5617440674 ps
CPU time 230.02 seconds
Started Aug 02 08:09:03 PM PDT 24
Finished Aug 02 08:12:53 PM PDT 24
Peak memory 576252 kb
Host smart-02178eb1-3af9-4d7e-a5a2-e062c460edec
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184379287 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_error.184379287
Directory /workspace/94.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.3408574657
Short name T676
Test name
Test status
Simulation time 8025567516 ps
CPU time 498.46 seconds
Started Aug 02 08:09:09 PM PDT 24
Finished Aug 02 08:17:28 PM PDT 24
Peak memory 576776 kb
Host smart-d07bf16d-9458-4d6b-881c-3e7d0a57450c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408574657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all
_with_rand_reset.3408574657
Directory /workspace/94.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.2718259003
Short name T910
Test name
Test status
Simulation time 11229877326 ps
CPU time 693.94 seconds
Started Aug 02 08:09:06 PM PDT 24
Finished Aug 02 08:20:40 PM PDT 24
Peak memory 577988 kb
Host smart-af422a1e-a8c7-4c98-b860-f10d2021fccd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718259003 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_al
l_with_reset_error.2718259003
Directory /workspace/94.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_unmapped_addr.2741026044
Short name T2620
Test name
Test status
Simulation time 321428234 ps
CPU time 33.99 seconds
Started Aug 02 08:09:09 PM PDT 24
Finished Aug 02 08:09:43 PM PDT 24
Peak memory 575900 kb
Host smart-a6b5ec22-f435-4d50-b483-5a02735ce1b0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741026044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_unmapped_addr.2741026044
Directory /workspace/94.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_access_same_device.1914333036
Short name T2066
Test name
Test status
Simulation time 759235093 ps
CPU time 29.63 seconds
Started Aug 02 08:09:06 PM PDT 24
Finished Aug 02 08:09:36 PM PDT 24
Peak memory 575832 kb
Host smart-13feb40f-fcae-44a1-9093-a02cda0ec740
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914333036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device
.1914333036
Directory /workspace/95.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.2975389670
Short name T1744
Test name
Test status
Simulation time 30793954 ps
CPU time 6.22 seconds
Started Aug 02 08:09:08 PM PDT 24
Finished Aug 02 08:09:15 PM PDT 24
Peak memory 573900 kb
Host smart-3fc110a7-2c87-4f5c-8e41-c2265e62c1c6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975389670 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_and_unmapped_add
r.2975389670
Directory /workspace/95.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_error_random.2278377562
Short name T1655
Test name
Test status
Simulation time 2258710523 ps
CPU time 75.43 seconds
Started Aug 02 08:09:08 PM PDT 24
Finished Aug 02 08:10:24 PM PDT 24
Peak memory 575760 kb
Host smart-8d3e4dee-b06b-46ac-95e7-d36b9610a8ef
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278377562 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_random.2278377562
Directory /workspace/95.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_random.805089008
Short name T499
Test name
Test status
Simulation time 531107782 ps
CPU time 42.36 seconds
Started Aug 02 08:09:09 PM PDT 24
Finished Aug 02 08:09:52 PM PDT 24
Peak memory 575816 kb
Host smart-7e99f3b5-7a84-489b-bf28-eb772cf49dab
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805089008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random.805089008
Directory /workspace/95.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_random_large_delays.1363174205
Short name T2588
Test name
Test status
Simulation time 88172733701 ps
CPU time 912.19 seconds
Started Aug 02 08:09:05 PM PDT 24
Finished Aug 02 08:24:18 PM PDT 24
Peak memory 576044 kb
Host smart-6d5ecec8-58ef-4a0b-9706-e195c23c2de7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363174205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_large_delays.1363174205
Directory /workspace/95.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_random_slow_rsp.1479997989
Short name T1649
Test name
Test status
Simulation time 57552805329 ps
CPU time 1150.64 seconds
Started Aug 02 08:09:10 PM PDT 24
Finished Aug 02 08:28:21 PM PDT 24
Peak memory 576008 kb
Host smart-429398de-0158-4c39-a4cc-c71e9f8016f6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479997989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_slow_rsp.1479997989
Directory /workspace/95.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_random_zero_delays.4037306254
Short name T2487
Test name
Test status
Simulation time 281000115 ps
CPU time 27.44 seconds
Started Aug 02 08:09:09 PM PDT 24
Finished Aug 02 08:09:36 PM PDT 24
Peak memory 575784 kb
Host smart-88f556c8-4226-4e8d-a6c1-5a2900315a81
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037306254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_zero_del
ays.4037306254
Directory /workspace/95.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_same_source.3522722599
Short name T2182
Test name
Test status
Simulation time 224098206 ps
CPU time 8.74 seconds
Started Aug 02 08:09:08 PM PDT 24
Finished Aug 02 08:09:17 PM PDT 24
Peak memory 574476 kb
Host smart-4824ab82-e56b-4d69-b54f-467968b25947
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522722599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_same_source.3522722599
Directory /workspace/95.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_smoke.1621420671
Short name T1559
Test name
Test status
Simulation time 236639751 ps
CPU time 9.65 seconds
Started Aug 02 08:09:09 PM PDT 24
Finished Aug 02 08:09:19 PM PDT 24
Peak memory 574560 kb
Host smart-d63eebbc-04c5-4a05-bc11-0cca3a340115
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621420671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke.1621420671
Directory /workspace/95.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_smoke_large_delays.1733288406
Short name T2046
Test name
Test status
Simulation time 8003173622 ps
CPU time 84.12 seconds
Started Aug 02 08:09:09 PM PDT 24
Finished Aug 02 08:10:33 PM PDT 24
Peak memory 574592 kb
Host smart-3c1d3702-63ac-485c-a994-16db5f26a69a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733288406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_large_delays.1733288406
Directory /workspace/95.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.351928784
Short name T2929
Test name
Test status
Simulation time 5043936176 ps
CPU time 82.01 seconds
Started Aug 02 08:09:05 PM PDT 24
Finished Aug 02 08:10:27 PM PDT 24
Peak memory 573924 kb
Host smart-f3c16822-1aa3-47bc-97dc-3cf5a2c58ada
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351928784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_slow_rsp.351928784
Directory /workspace/95.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_smoke_zero_delays.968223706
Short name T2453
Test name
Test status
Simulation time 55563560 ps
CPU time 7.03 seconds
Started Aug 02 08:09:08 PM PDT 24
Finished Aug 02 08:09:15 PM PDT 24
Peak memory 574480 kb
Host smart-cd1f3822-0fb5-4df9-a27e-5a8b3bbe7f03
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968223706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_zero_delays
.968223706
Directory /workspace/95.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_stress_all.1694771584
Short name T594
Test name
Test status
Simulation time 3984116007 ps
CPU time 139.16 seconds
Started Aug 02 08:09:02 PM PDT 24
Finished Aug 02 08:11:21 PM PDT 24
Peak memory 576080 kb
Host smart-bdc71672-e41f-4b63-bf98-5d9b643979cf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694771584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all.1694771584
Directory /workspace/95.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.1284916917
Short name T1690
Test name
Test status
Simulation time 10937154633 ps
CPU time 362.51 seconds
Started Aug 02 08:09:07 PM PDT 24
Finished Aug 02 08:15:10 PM PDT 24
Peak memory 576120 kb
Host smart-cb3069b3-6d3f-4e57-8a0e-3f1aab3df7d2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284916917 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_error.1284916917
Directory /workspace/95.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.49451799
Short name T898
Test name
Test status
Simulation time 2931672109 ps
CPU time 199.95 seconds
Started Aug 02 08:09:05 PM PDT 24
Finished Aug 02 08:12:26 PM PDT 24
Peak memory 576808 kb
Host smart-b7f89c01-3c00-4aa6-8313-9a6d869ff8c9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49451799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_w
ith_rand_reset.49451799
Directory /workspace/95.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.695106582
Short name T2245
Test name
Test status
Simulation time 2915857175 ps
CPU time 410.2 seconds
Started Aug 02 08:09:06 PM PDT 24
Finished Aug 02 08:15:56 PM PDT 24
Peak memory 576888 kb
Host smart-d5a7097f-5394-414a-b291-a26c4a66fdf5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695106582 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all
_with_reset_error.695106582
Directory /workspace/95.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_unmapped_addr.668378905
Short name T600
Test name
Test status
Simulation time 330453228 ps
CPU time 35.79 seconds
Started Aug 02 08:09:09 PM PDT 24
Finished Aug 02 08:09:45 PM PDT 24
Peak memory 575952 kb
Host smart-ba7a9d61-5076-4200-9bf8-dd2fdfbb7538
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668378905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_unmapped_addr.668378905
Directory /workspace/95.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_access_same_device.482134247
Short name T501
Test name
Test status
Simulation time 2039654743 ps
CPU time 81.54 seconds
Started Aug 02 08:09:24 PM PDT 24
Finished Aug 02 08:10:45 PM PDT 24
Peak memory 575976 kb
Host smart-fd1bdd02-0ef6-4e6c-8486-da2be7db88c7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482134247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device.
482134247
Directory /workspace/96.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.3239097038
Short name T2928
Test name
Test status
Simulation time 134060462722 ps
CPU time 2573.6 seconds
Started Aug 02 08:09:20 PM PDT 24
Finished Aug 02 08:52:14 PM PDT 24
Peak memory 576084 kb
Host smart-21ce4766-879e-402e-bd64-abd67f5a4775
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239097038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_
device_slow_rsp.3239097038
Directory /workspace/96.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.2221786041
Short name T2737
Test name
Test status
Simulation time 148492134 ps
CPU time 16.95 seconds
Started Aug 02 08:09:22 PM PDT 24
Finished Aug 02 08:09:39 PM PDT 24
Peak memory 575980 kb
Host smart-485d712f-dedc-4ff5-b8dc-a84b3f9e53d8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221786041 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_and_unmapped_add
r.2221786041
Directory /workspace/96.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_error_random.1039571314
Short name T1844
Test name
Test status
Simulation time 1181208794 ps
CPU time 33.56 seconds
Started Aug 02 08:09:23 PM PDT 24
Finished Aug 02 08:09:57 PM PDT 24
Peak memory 575740 kb
Host smart-ed13f776-2169-4f43-8b24-fe8bf5553344
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039571314 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_random.1039571314
Directory /workspace/96.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_random.1115018762
Short name T2358
Test name
Test status
Simulation time 297517276 ps
CPU time 14.88 seconds
Started Aug 02 08:09:21 PM PDT 24
Finished Aug 02 08:09:36 PM PDT 24
Peak memory 575840 kb
Host smart-450a2bf0-0108-4fb0-ac0b-d999e0a5ca86
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115018762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random.1115018762
Directory /workspace/96.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_random_large_delays.546608975
Short name T2111
Test name
Test status
Simulation time 84612063063 ps
CPU time 989.44 seconds
Started Aug 02 08:09:19 PM PDT 24
Finished Aug 02 08:25:49 PM PDT 24
Peak memory 575984 kb
Host smart-4ed4a3df-510e-41e8-a6ef-6f2464e1e172
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546608975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_large_delays.546608975
Directory /workspace/96.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_random_slow_rsp.1509259549
Short name T2336
Test name
Test status
Simulation time 45163704013 ps
CPU time 866.33 seconds
Started Aug 02 08:09:21 PM PDT 24
Finished Aug 02 08:23:48 PM PDT 24
Peak memory 575944 kb
Host smart-d2f2d0f9-dc85-41d8-a54b-fb8244bf4b35
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509259549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_slow_rsp.1509259549
Directory /workspace/96.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.41017903
Short name T2316
Test name
Test status
Simulation time 162185143 ps
CPU time 14.9 seconds
Started Aug 02 08:09:20 PM PDT 24
Finished Aug 02 08:09:35 PM PDT 24
Peak memory 575740 kb
Host smart-c2091c24-6a7e-44cf-aeda-0fcf0e1d81bd
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41017903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_zero_delay
s.41017903
Directory /workspace/96.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_same_source.728463031
Short name T471
Test name
Test status
Simulation time 2360097406 ps
CPU time 71.48 seconds
Started Aug 02 08:09:20 PM PDT 24
Finished Aug 02 08:10:32 PM PDT 24
Peak memory 575764 kb
Host smart-30cbe953-7262-4bdf-8465-ca71f256bf0c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728463031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_same_source.728463031
Directory /workspace/96.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_smoke.938935323
Short name T1998
Test name
Test status
Simulation time 48589335 ps
CPU time 6.09 seconds
Started Aug 02 08:09:10 PM PDT 24
Finished Aug 02 08:09:16 PM PDT 24
Peak memory 573832 kb
Host smart-ff8b2bec-7887-48c6-9f80-bd0e893f8d72
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938935323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke.938935323
Directory /workspace/96.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.438067803
Short name T2827
Test name
Test status
Simulation time 6232289310 ps
CPU time 60.86 seconds
Started Aug 02 08:09:24 PM PDT 24
Finished Aug 02 08:10:25 PM PDT 24
Peak memory 573856 kb
Host smart-bcc8a5c9-836d-49d4-9491-31dbbe0605b9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438067803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_large_delays.438067803
Directory /workspace/96.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.1616062019
Short name T2509
Test name
Test status
Simulation time 5526212486 ps
CPU time 95.08 seconds
Started Aug 02 08:09:19 PM PDT 24
Finished Aug 02 08:10:54 PM PDT 24
Peak memory 574624 kb
Host smart-a21d24a2-5eb6-4dee-8a70-788006fa956c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616062019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_slow_rsp.1616062019
Directory /workspace/96.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.4256930864
Short name T1416
Test name
Test status
Simulation time 56667830 ps
CPU time 6.62 seconds
Started Aug 02 08:09:24 PM PDT 24
Finished Aug 02 08:09:31 PM PDT 24
Peak memory 573852 kb
Host smart-984e63c3-d088-4eef-b442-1a10d8f3cc53
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256930864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_zero_delay
s.4256930864
Directory /workspace/96.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_stress_all.2084649931
Short name T2702
Test name
Test status
Simulation time 10250534119 ps
CPU time 350.84 seconds
Started Aug 02 08:09:19 PM PDT 24
Finished Aug 02 08:15:10 PM PDT 24
Peak memory 576032 kb
Host smart-d80e77be-e3e6-4c4f-8617-16e7d36a317a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084649931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all.2084649931
Directory /workspace/96.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.3703877382
Short name T1644
Test name
Test status
Simulation time 2028608375 ps
CPU time 158.62 seconds
Started Aug 02 08:09:24 PM PDT 24
Finished Aug 02 08:12:02 PM PDT 24
Peak memory 575900 kb
Host smart-126823ac-37f4-408f-83e2-c5076d5780dc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703877382 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_error.3703877382
Directory /workspace/96.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.1003537707
Short name T470
Test name
Test status
Simulation time 7112328094 ps
CPU time 386.97 seconds
Started Aug 02 08:09:22 PM PDT 24
Finished Aug 02 08:15:49 PM PDT 24
Peak memory 576824 kb
Host smart-807f7930-cbd1-46bd-a84e-5ff079651777
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003537707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all
_with_rand_reset.1003537707
Directory /workspace/96.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.2791593762
Short name T2782
Test name
Test status
Simulation time 8735183147 ps
CPU time 399.15 seconds
Started Aug 02 08:09:22 PM PDT 24
Finished Aug 02 08:16:02 PM PDT 24
Peak memory 576808 kb
Host smart-a86582a2-5274-4081-bc71-ee1fb2d3c218
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791593762 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_al
l_with_reset_error.2791593762
Directory /workspace/96.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_unmapped_addr.2173276872
Short name T684
Test name
Test status
Simulation time 202515852 ps
CPU time 25.41 seconds
Started Aug 02 08:09:20 PM PDT 24
Finished Aug 02 08:09:45 PM PDT 24
Peak memory 575888 kb
Host smart-8ebb23b9-3d51-419e-a360-436e7a283960
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173276872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_unmapped_addr.2173276872
Directory /workspace/96.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_access_same_device.3413669984
Short name T2541
Test name
Test status
Simulation time 1423955112 ps
CPU time 47.52 seconds
Started Aug 02 08:09:21 PM PDT 24
Finished Aug 02 08:10:09 PM PDT 24
Peak memory 575776 kb
Host smart-c9292215-918a-4886-aaa5-7219b092d2ef
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413669984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device
.3413669984
Directory /workspace/97.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.1344771351
Short name T1834
Test name
Test status
Simulation time 66669922777 ps
CPU time 1216.04 seconds
Started Aug 02 08:09:19 PM PDT 24
Finished Aug 02 08:29:35 PM PDT 24
Peak memory 575932 kb
Host smart-77e7e3e2-f606-46ab-b1cc-303737fc23a1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344771351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_
device_slow_rsp.1344771351
Directory /workspace/97.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.3880179665
Short name T1740
Test name
Test status
Simulation time 36732241 ps
CPU time 6.37 seconds
Started Aug 02 08:09:33 PM PDT 24
Finished Aug 02 08:09:40 PM PDT 24
Peak memory 573936 kb
Host smart-9fe6d3c3-cb6e-4449-b2b9-6275056f02ee
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880179665 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_and_unmapped_add
r.3880179665
Directory /workspace/97.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_error_random.1138151160
Short name T1693
Test name
Test status
Simulation time 1433001188 ps
CPU time 46.55 seconds
Started Aug 02 08:09:20 PM PDT 24
Finished Aug 02 08:10:07 PM PDT 24
Peak memory 575928 kb
Host smart-e2f416d8-b66e-4c36-96bd-d9e5d83ac580
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138151160 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_random.1138151160
Directory /workspace/97.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_random.3853167972
Short name T1676
Test name
Test status
Simulation time 1385183327 ps
CPU time 52.59 seconds
Started Aug 02 08:09:17 PM PDT 24
Finished Aug 02 08:10:10 PM PDT 24
Peak memory 575892 kb
Host smart-3556e614-3182-4863-a590-c1e713abf5a5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853167972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random.3853167972
Directory /workspace/97.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_random_large_delays.2392380709
Short name T2617
Test name
Test status
Simulation time 17128249145 ps
CPU time 176.35 seconds
Started Aug 02 08:09:19 PM PDT 24
Finished Aug 02 08:12:16 PM PDT 24
Peak memory 576044 kb
Host smart-f5481437-e414-4658-8a11-29062da3efd5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392380709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_large_delays.2392380709
Directory /workspace/97.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_random_slow_rsp.1322094194
Short name T1642
Test name
Test status
Simulation time 50933666778 ps
CPU time 874.91 seconds
Started Aug 02 08:09:22 PM PDT 24
Finished Aug 02 08:23:57 PM PDT 24
Peak memory 575844 kb
Host smart-64caba56-6b37-4c5f-94d7-33f780405c8c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322094194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_slow_rsp.1322094194
Directory /workspace/97.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.3027224209
Short name T2563
Test name
Test status
Simulation time 228230369 ps
CPU time 19.75 seconds
Started Aug 02 08:09:20 PM PDT 24
Finished Aug 02 08:09:40 PM PDT 24
Peak memory 575912 kb
Host smart-74c6e068-3e17-4a90-b90a-5a91059cf0cc
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027224209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_zero_del
ays.3027224209
Directory /workspace/97.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_same_source.3478038332
Short name T2148
Test name
Test status
Simulation time 115574610 ps
CPU time 10.68 seconds
Started Aug 02 08:09:25 PM PDT 24
Finished Aug 02 08:09:35 PM PDT 24
Peak memory 575876 kb
Host smart-a1ad4566-c176-41eb-a14c-20e027ec8f98
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478038332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_same_source.3478038332
Directory /workspace/97.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_smoke.1205975694
Short name T1666
Test name
Test status
Simulation time 179852186 ps
CPU time 8.23 seconds
Started Aug 02 08:09:21 PM PDT 24
Finished Aug 02 08:09:30 PM PDT 24
Peak memory 573732 kb
Host smart-ebf90a6d-7dd3-4421-9575-701d9b793deb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205975694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke.1205975694
Directory /workspace/97.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.1045572806
Short name T2205
Test name
Test status
Simulation time 6797241117 ps
CPU time 73.59 seconds
Started Aug 02 08:09:21 PM PDT 24
Finished Aug 02 08:10:35 PM PDT 24
Peak memory 574532 kb
Host smart-42b1bf28-21b9-4310-9d41-800dfdde36b7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045572806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_large_delays.1045572806
Directory /workspace/97.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.800372317
Short name T708
Test name
Test status
Simulation time 2360388457 ps
CPU time 39.26 seconds
Started Aug 02 08:09:37 PM PDT 24
Finished Aug 02 08:10:16 PM PDT 24
Peak memory 574632 kb
Host smart-29b5a7c0-d242-4f32-afc4-d18d988c8c29
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800372317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_slow_rsp.800372317
Directory /workspace/97.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_smoke_zero_delays.3227734026
Short name T2067
Test name
Test status
Simulation time 57591224 ps
CPU time 7.23 seconds
Started Aug 02 08:09:18 PM PDT 24
Finished Aug 02 08:09:25 PM PDT 24
Peak memory 574504 kb
Host smart-82ac441e-032b-4f65-83bf-3fea46f92b7a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227734026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_zero_delay
s.3227734026
Directory /workspace/97.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_stress_all.2370937227
Short name T497
Test name
Test status
Simulation time 4595965858 ps
CPU time 186.32 seconds
Started Aug 02 08:09:35 PM PDT 24
Finished Aug 02 08:12:41 PM PDT 24
Peak memory 576800 kb
Host smart-45fa83d6-1b0a-4189-a821-773f5b9f650a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370937227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all.2370937227
Directory /workspace/97.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.3805027261
Short name T1826
Test name
Test status
Simulation time 11977848751 ps
CPU time 528.73 seconds
Started Aug 02 08:09:38 PM PDT 24
Finished Aug 02 08:18:28 PM PDT 24
Peak memory 576756 kb
Host smart-034f1701-bc70-4b8e-b307-34e8f84bfdc2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805027261 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_error.3805027261
Directory /workspace/97.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.2723968192
Short name T2489
Test name
Test status
Simulation time 7758232507 ps
CPU time 579.13 seconds
Started Aug 02 08:09:38 PM PDT 24
Finished Aug 02 08:19:17 PM PDT 24
Peak memory 576824 kb
Host smart-e9e1b5f4-ce70-4c1b-8850-e9a1aa1c219f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723968192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all
_with_rand_reset.2723968192
Directory /workspace/97.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.3826541780
Short name T1863
Test name
Test status
Simulation time 215545747 ps
CPU time 84.4 seconds
Started Aug 02 08:09:38 PM PDT 24
Finished Aug 02 08:11:02 PM PDT 24
Peak memory 576748 kb
Host smart-ccaa7c24-007f-4e6d-ba89-9628252536c6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826541780 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_al
l_with_reset_error.3826541780
Directory /workspace/97.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_unmapped_addr.1413602395
Short name T662
Test name
Test status
Simulation time 260060169 ps
CPU time 29.03 seconds
Started Aug 02 08:09:21 PM PDT 24
Finished Aug 02 08:09:51 PM PDT 24
Peak memory 575828 kb
Host smart-ec9394e2-032c-4098-9d6f-f0aad055ba27
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413602395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_unmapped_addr.1413602395
Directory /workspace/97.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_access_same_device.3119871354
Short name T1831
Test name
Test status
Simulation time 2120302564 ps
CPU time 85.98 seconds
Started Aug 02 08:09:37 PM PDT 24
Finished Aug 02 08:11:03 PM PDT 24
Peak memory 575756 kb
Host smart-3f4970bb-ae8a-42d7-baa7-15289c44d42c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119871354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device
.3119871354
Directory /workspace/98.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.1903598839
Short name T2001
Test name
Test status
Simulation time 65899354299 ps
CPU time 1205.08 seconds
Started Aug 02 08:09:36 PM PDT 24
Finished Aug 02 08:29:41 PM PDT 24
Peak memory 576068 kb
Host smart-b285ebcf-5142-45ee-a7ce-f9527502fac9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903598839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_
device_slow_rsp.1903598839
Directory /workspace/98.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.4211702939
Short name T2585
Test name
Test status
Simulation time 448791998 ps
CPU time 21.39 seconds
Started Aug 02 08:09:36 PM PDT 24
Finished Aug 02 08:09:58 PM PDT 24
Peak memory 575900 kb
Host smart-67325ab7-f953-4b42-b5db-445d43388dee
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211702939 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_and_unmapped_add
r.4211702939
Directory /workspace/98.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_error_random.2884378270
Short name T2277
Test name
Test status
Simulation time 291955567 ps
CPU time 22.66 seconds
Started Aug 02 08:09:40 PM PDT 24
Finished Aug 02 08:10:02 PM PDT 24
Peak memory 575948 kb
Host smart-2a6879e8-8592-4e58-9c42-c3d9a3875e9e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884378270 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_random.2884378270
Directory /workspace/98.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_random.1995887096
Short name T2481
Test name
Test status
Simulation time 1695828117 ps
CPU time 62.89 seconds
Started Aug 02 08:09:39 PM PDT 24
Finished Aug 02 08:10:42 PM PDT 24
Peak memory 575792 kb
Host smart-9ffad43f-21e3-43d5-b706-5a99577b9dba
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995887096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random.1995887096
Directory /workspace/98.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_random_large_delays.2185714344
Short name T2292
Test name
Test status
Simulation time 100283653053 ps
CPU time 1173.3 seconds
Started Aug 02 08:09:35 PM PDT 24
Finished Aug 02 08:29:08 PM PDT 24
Peak memory 575976 kb
Host smart-a63c6d52-350e-46f9-968b-94f56164b1c3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185714344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_large_delays.2185714344
Directory /workspace/98.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_random_slow_rsp.1995757693
Short name T1984
Test name
Test status
Simulation time 35871886693 ps
CPU time 660.47 seconds
Started Aug 02 08:09:35 PM PDT 24
Finished Aug 02 08:20:37 PM PDT 24
Peak memory 576052 kb
Host smart-0fc18e0c-6749-4f89-b1ef-23bca8a99d94
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995757693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_slow_rsp.1995757693
Directory /workspace/98.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_random_zero_delays.1708064414
Short name T1914
Test name
Test status
Simulation time 212063026 ps
CPU time 17.96 seconds
Started Aug 02 08:09:34 PM PDT 24
Finished Aug 02 08:09:52 PM PDT 24
Peak memory 575848 kb
Host smart-ab66d4aa-7063-4af1-b7ed-f0a1c0c17130
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708064414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_zero_del
ays.1708064414
Directory /workspace/98.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_same_source.3940338246
Short name T1986
Test name
Test status
Simulation time 260752403 ps
CPU time 10.05 seconds
Started Aug 02 08:09:38 PM PDT 24
Finished Aug 02 08:09:48 PM PDT 24
Peak memory 575728 kb
Host smart-d3441186-69f1-47f8-8d4a-aae7140e739b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940338246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_same_source.3940338246
Directory /workspace/98.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_smoke.4025767215
Short name T2065
Test name
Test status
Simulation time 35692218 ps
CPU time 5.86 seconds
Started Aug 02 08:09:36 PM PDT 24
Finished Aug 02 08:09:42 PM PDT 24
Peak memory 574556 kb
Host smart-5a1dc3f5-581d-460d-b5e0-ee017b3c9346
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025767215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke.4025767215
Directory /workspace/98.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_smoke_large_delays.2192771371
Short name T2646
Test name
Test status
Simulation time 8134288277 ps
CPU time 81.19 seconds
Started Aug 02 08:09:39 PM PDT 24
Finished Aug 02 08:11:00 PM PDT 24
Peak memory 574584 kb
Host smart-f597f3b0-70f6-490c-84c3-d3c0d0bb9624
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192771371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_large_delays.2192771371
Directory /workspace/98.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.1798246459
Short name T2410
Test name
Test status
Simulation time 6210064380 ps
CPU time 107.89 seconds
Started Aug 02 08:09:36 PM PDT 24
Finished Aug 02 08:11:24 PM PDT 24
Peak memory 574616 kb
Host smart-99d011a3-1822-455a-9d12-a798dd893c78
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798246459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_slow_rsp.1798246459
Directory /workspace/98.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.1046643275
Short name T2830
Test name
Test status
Simulation time 39681255 ps
CPU time 5.79 seconds
Started Aug 02 08:09:48 PM PDT 24
Finished Aug 02 08:09:54 PM PDT 24
Peak memory 574508 kb
Host smart-44e3eaed-a4b5-4d29-9070-c83aec7c4386
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046643275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_zero_delay
s.1046643275
Directory /workspace/98.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_stress_all.2534136204
Short name T495
Test name
Test status
Simulation time 3476193121 ps
CPU time 285.47 seconds
Started Aug 02 08:09:39 PM PDT 24
Finished Aug 02 08:14:25 PM PDT 24
Peak memory 576044 kb
Host smart-b8316603-0baf-49b9-b005-b4cc3439df80
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534136204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all.2534136204
Directory /workspace/98.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.3542604500
Short name T1893
Test name
Test status
Simulation time 5740907919 ps
CPU time 230.88 seconds
Started Aug 02 08:09:37 PM PDT 24
Finished Aug 02 08:13:28 PM PDT 24
Peak memory 575912 kb
Host smart-bcad5fd7-c2b2-4b3c-9f9d-bb1ef205f947
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542604500 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_error.3542604500
Directory /workspace/98.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.3136683130
Short name T2603
Test name
Test status
Simulation time 839413474 ps
CPU time 291.98 seconds
Started Aug 02 08:09:39 PM PDT 24
Finished Aug 02 08:14:31 PM PDT 24
Peak memory 575932 kb
Host smart-fcf9dc0f-0e03-493a-afd2-2d3c1b9773cb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136683130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all
_with_rand_reset.3136683130
Directory /workspace/98.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.585545909
Short name T2680
Test name
Test status
Simulation time 33817770 ps
CPU time 24.56 seconds
Started Aug 02 08:09:36 PM PDT 24
Finished Aug 02 08:10:01 PM PDT 24
Peak memory 575832 kb
Host smart-8b9232bb-3767-4bab-85b4-0b187448b5d6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585545909 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all
_with_reset_error.585545909
Directory /workspace/98.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_unmapped_addr.1208171751
Short name T2766
Test name
Test status
Simulation time 491808982 ps
CPU time 21.57 seconds
Started Aug 02 08:09:35 PM PDT 24
Finished Aug 02 08:09:57 PM PDT 24
Peak memory 575836 kb
Host smart-8c662b7f-2c71-45c6-a1e6-94731d6bc5bb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208171751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_unmapped_addr.1208171751
Directory /workspace/98.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_access_same_device.2218889898
Short name T2713
Test name
Test status
Simulation time 2229089702 ps
CPU time 90.28 seconds
Started Aug 02 08:09:35 PM PDT 24
Finished Aug 02 08:11:05 PM PDT 24
Peak memory 576052 kb
Host smart-090bb279-8eae-407c-9fe5-dc6d19d37fdc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218889898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device
.2218889898
Directory /workspace/99.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.653922296
Short name T2363
Test name
Test status
Simulation time 32442845431 ps
CPU time 590.59 seconds
Started Aug 02 08:09:40 PM PDT 24
Finished Aug 02 08:19:31 PM PDT 24
Peak memory 575980 kb
Host smart-c7fd42b2-5edf-4de7-aa00-afeebb600455
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653922296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_d
evice_slow_rsp.653922296
Directory /workspace/99.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.3151423914
Short name T1670
Test name
Test status
Simulation time 224728625 ps
CPU time 22.32 seconds
Started Aug 02 08:09:51 PM PDT 24
Finished Aug 02 08:10:13 PM PDT 24
Peak memory 575916 kb
Host smart-647b3922-475b-4f77-8c07-1fd22bce96f0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151423914 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_and_unmapped_add
r.3151423914
Directory /workspace/99.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_error_random.3434722567
Short name T1405
Test name
Test status
Simulation time 324289639 ps
CPU time 23.75 seconds
Started Aug 02 08:09:35 PM PDT 24
Finished Aug 02 08:09:59 PM PDT 24
Peak memory 575860 kb
Host smart-fdce5468-9277-48a8-b86f-5e49daeb7812
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434722567 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_random.3434722567
Directory /workspace/99.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_random.2550449911
Short name T2136
Test name
Test status
Simulation time 685381506 ps
CPU time 26.59 seconds
Started Aug 02 08:09:35 PM PDT 24
Finished Aug 02 08:10:02 PM PDT 24
Peak memory 575808 kb
Host smart-9824a7c7-d669-421e-b56d-31d60ccda986
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550449911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random.2550449911
Directory /workspace/99.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_random_large_delays.2189107328
Short name T630
Test name
Test status
Simulation time 102698888386 ps
CPU time 1088.99 seconds
Started Aug 02 08:09:36 PM PDT 24
Finished Aug 02 08:27:45 PM PDT 24
Peak memory 576120 kb
Host smart-bf3af680-194b-4223-b92c-c7cfc99a38ec
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189107328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_large_delays.2189107328
Directory /workspace/99.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.1218902424
Short name T1682
Test name
Test status
Simulation time 55882722280 ps
CPU time 915.95 seconds
Started Aug 02 08:09:39 PM PDT 24
Finished Aug 02 08:24:55 PM PDT 24
Peak memory 576776 kb
Host smart-f622ec91-cfef-4604-a4e3-4e32a6a5e981
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218902424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_slow_rsp.1218902424
Directory /workspace/99.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_random_zero_delays.1764935733
Short name T506
Test name
Test status
Simulation time 274460530 ps
CPU time 25 seconds
Started Aug 02 08:09:39 PM PDT 24
Finished Aug 02 08:10:04 PM PDT 24
Peak memory 575884 kb
Host smart-312d7388-406b-400e-aa57-1add6637be3c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764935733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_zero_del
ays.1764935733
Directory /workspace/99.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_same_source.1112436931
Short name T1689
Test name
Test status
Simulation time 1300801970 ps
CPU time 34.69 seconds
Started Aug 02 08:09:37 PM PDT 24
Finished Aug 02 08:10:12 PM PDT 24
Peak memory 575884 kb
Host smart-b6a5746e-73d4-4817-aaf7-d8351360a443
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112436931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_same_source.1112436931
Directory /workspace/99.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_smoke.3669828431
Short name T2615
Test name
Test status
Simulation time 238049543 ps
CPU time 10.59 seconds
Started Aug 02 08:09:34 PM PDT 24
Finished Aug 02 08:09:45 PM PDT 24
Peak memory 573808 kb
Host smart-2e4a3d88-bfc4-43b5-b6a8-abb803083853
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669828431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke.3669828431
Directory /workspace/99.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.1778242298
Short name T2602
Test name
Test status
Simulation time 9981058831 ps
CPU time 101.86 seconds
Started Aug 02 08:09:36 PM PDT 24
Finished Aug 02 08:11:17 PM PDT 24
Peak memory 574728 kb
Host smart-f76e02d6-d931-41df-85a1-7e693ad03671
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778242298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_large_delays.1778242298
Directory /workspace/99.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.4086215710
Short name T2496
Test name
Test status
Simulation time 5799388804 ps
CPU time 94.2 seconds
Started Aug 02 08:09:35 PM PDT 24
Finished Aug 02 08:11:09 PM PDT 24
Peak memory 574636 kb
Host smart-5b3cc054-df2b-4030-967f-811006e8f9cd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086215710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_slow_rsp.4086215710
Directory /workspace/99.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_smoke_zero_delays.2250217702
Short name T1745
Test name
Test status
Simulation time 44348621 ps
CPU time 6.2 seconds
Started Aug 02 08:09:34 PM PDT 24
Finished Aug 02 08:09:41 PM PDT 24
Peak memory 574504 kb
Host smart-ea125f0b-e02a-4700-8a79-a63f109562c0
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250217702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_zero_delay
s.2250217702
Directory /workspace/99.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_stress_all.1040554686
Short name T632
Test name
Test status
Simulation time 550492712 ps
CPU time 35.71 seconds
Started Aug 02 08:09:53 PM PDT 24
Finished Aug 02 08:10:28 PM PDT 24
Peak memory 575896 kb
Host smart-ac2c9720-21d5-4d2b-a5a4-0545ee9271ae
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040554686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all.1040554686
Directory /workspace/99.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.688904089
Short name T2853
Test name
Test status
Simulation time 700519981 ps
CPU time 47.42 seconds
Started Aug 02 08:09:52 PM PDT 24
Finished Aug 02 08:10:39 PM PDT 24
Peak memory 575968 kb
Host smart-164d6dcf-36c7-4f35-b7cf-b509eab71de1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688904089 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_error.688904089
Directory /workspace/99.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.1923268893
Short name T507
Test name
Test status
Simulation time 218734285 ps
CPU time 123.15 seconds
Started Aug 02 08:09:51 PM PDT 24
Finished Aug 02 08:11:54 PM PDT 24
Peak memory 576716 kb
Host smart-c960fac3-54ed-496a-abfc-96af8a888343
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923268893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all
_with_rand_reset.1923268893
Directory /workspace/99.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.3733121576
Short name T903
Test name
Test status
Simulation time 598713728 ps
CPU time 209.08 seconds
Started Aug 02 08:09:50 PM PDT 24
Finished Aug 02 08:13:19 PM PDT 24
Peak memory 576740 kb
Host smart-118ac8aa-669b-4dca-bbe8-0919cf407935
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733121576 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_al
l_with_reset_error.3733121576
Directory /workspace/99.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_unmapped_addr.786430294
Short name T2609
Test name
Test status
Simulation time 959202567 ps
CPU time 40.25 seconds
Started Aug 02 08:09:50 PM PDT 24
Finished Aug 02 08:10:31 PM PDT 24
Peak memory 575844 kb
Host smart-a7f2ddfb-8b73-4348-bf17-d3ca863a3f5c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786430294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_unmapped_addr.786430294
Directory /workspace/99.xbar_unmapped_addr/latest

Test location /workspace/coverage/default/0.chip_jtag_csr_rw.4021909029
Short name T204
Test name
Test status
Simulation time 4066847138 ps
CPU time 252.94 seconds
Started Aug 02 08:11:45 PM PDT 24
Finished Aug 02 08:15:58 PM PDT 24
Peak memory 608080 kb
Host smart-78c2fb5c-5271-48ab-8eef-408453985960
User root
Command /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021909029 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T
EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.c
hip_jtag_csr_rw.4021909029
Directory /workspace/0.chip_jtag_csr_rw/latest

Test location /workspace/coverage/default/0.chip_jtag_mem_access.2406289072
Short name T82
Test name
Test status
Simulation time 13377080104 ps
CPU time 1626.79 seconds
Started Aug 02 08:11:54 PM PDT 24
Finished Aug 02 08:39:01 PM PDT 24
Peak memory 607936 kb
Host smart-52c06d5c-42e4-496e-bfa8-ddbef86c37e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406289072 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_
mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.2
406289072
Directory /workspace/0.chip_jtag_mem_access/latest

Test location /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.2046483795
Short name T435
Test name
Test status
Simulation time 4815228298 ps
CPU time 480.14 seconds
Started Aug 02 08:20:55 PM PDT 24
Finished Aug 02 08:28:56 PM PDT 24
Peak memory 619748 kb
Host smart-523d4edd-1c92-4a0d-9791-9843fafffba8
User root
Command /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2
046483795 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.2046483795
Directory /workspace/0.chip_rv_dm_ndm_reset_req/latest

Test location /workspace/coverage/default/0.chip_sival_flash_info_access.745976497
Short name T375
Test name
Test status
Simulation time 3683668992 ps
CPU time 275.96 seconds
Started Aug 02 08:17:46 PM PDT 24
Finished Aug 02 08:22:22 PM PDT 24
Peak memory 609960 kb
Host smart-f11fb941-4491-47c4-a333-9ae63fa82ee6
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=745976497 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.745976497
Directory /workspace/0.chip_sival_flash_info_access/latest

Test location /workspace/coverage/default/0.chip_sw_aes_enc.798127247
Short name T1381
Test name
Test status
Simulation time 3261327808 ps
CPU time 343.15 seconds
Started Aug 02 08:20:01 PM PDT 24
Finished Aug 02 08:25:45 PM PDT 24
Peak memory 609620 kb
Host smart-1321831d-db83-4a47-873c-8b4d5fd7484d
User root
Command /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798127247 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.798127247
Directory /workspace/0.chip_sw_aes_enc/latest

Test location /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.295197021
Short name T1108
Test name
Test status
Simulation time 3457353410 ps
CPU time 268.17 seconds
Started Aug 02 08:18:04 PM PDT 24
Finished Aug 02 08:22:33 PM PDT 24
Peak memory 609684 kb
Host smart-afff29d9-486c-4ff2-b169-786d69c5dcc6
User root
Command /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951
97021 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.295197021
Directory /workspace/0.chip_sw_aes_enc_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_aes_entropy.233650116
Short name T1201
Test name
Test status
Simulation time 2359200952 ps
CPU time 224.11 seconds
Started Aug 02 08:19:45 PM PDT 24
Finished Aug 02 08:23:29 PM PDT 24
Peak memory 609552 kb
Host smart-d8770988-cceb-41b1-b679-f5c5104e7b12
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233650116 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_entropy.233650116
Directory /workspace/0.chip_sw_aes_entropy/latest

Test location /workspace/coverage/default/0.chip_sw_aes_idle.2521545967
Short name T315
Test name
Test status
Simulation time 2906019546 ps
CPU time 324.41 seconds
Started Aug 02 08:22:35 PM PDT 24
Finished Aug 02 08:28:00 PM PDT 24
Peak memory 609492 kb
Host smart-c4a1f334-b297-4f53-b614-fb621865c144
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521545967 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.2521545967
Directory /workspace/0.chip_sw_aes_idle/latest

Test location /workspace/coverage/default/0.chip_sw_aes_masking_off.599975945
Short name T1172
Test name
Test status
Simulation time 2828889190 ps
CPU time 306.64 seconds
Started Aug 02 08:18:23 PM PDT 24
Finished Aug 02 08:23:30 PM PDT 24
Peak memory 610268 kb
Host smart-927b94f0-2132-4590-a29f-ee9730c997d3
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599975945 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.chip_sw_aes_masking_off.599975945
Directory /workspace/0.chip_sw_aes_masking_off/latest

Test location /workspace/coverage/default/0.chip_sw_aes_smoketest.2971705686
Short name T1141
Test name
Test status
Simulation time 3364976600 ps
CPU time 292.72 seconds
Started Aug 02 08:23:30 PM PDT 24
Finished Aug 02 08:28:23 PM PDT 24
Peak memory 608356 kb
Host smart-33290b3a-df91-4737-b8c9-2e1792a9b8a0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971705686 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.chip_sw_aes_smoketest.2971705686
Directory /workspace/0.chip_sw_aes_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_entropy.60313388
Short name T86
Test name
Test status
Simulation time 4025300531 ps
CPU time 363.18 seconds
Started Aug 02 08:18:54 PM PDT 24
Finished Aug 02 08:24:57 PM PDT 24
Peak memory 609524 kb
Host smart-bbfa2438-232d-4da2-9def-f6e5451536e2
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=60313388 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.60313388
Directory /workspace/0.chip_sw_alert_handler_entropy/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_escalation.61641010
Short name T1331
Test name
Test status
Simulation time 5877882786 ps
CPU time 596.35 seconds
Started Aug 02 08:18:20 PM PDT 24
Finished Aug 02 08:28:17 PM PDT 24
Peak memory 619640 kb
Host smart-f1412cb7-f3ac-47bf-a109-392d887c8c5f
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test
_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb
_random_seed=61641010 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.61641010
Directory /workspace/0.chip_sw_alert_handler_escalation/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.3221244253
Short name T1268
Test name
Test status
Simulation time 6971474128 ps
CPU time 1428.81 seconds
Started Aug 02 08:19:29 PM PDT 24
Finished Aug 02 08:43:19 PM PDT 24
Peak memory 609940 kb
Host smart-062f1a1e-20c7-4cf3-8d6f-ae7297a0d87f
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules,
test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3221244253 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_togg
le.3221244253
Directory /workspace/0.chip_sw_alert_handler_lpg_reset_toggle/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.751849280
Short name T1182
Test name
Test status
Simulation time 11178435230 ps
CPU time 1173.45 seconds
Started Aug 02 08:20:25 PM PDT 24
Finished Aug 02 08:39:59 PM PDT 24
Peak memory 610684 kb
Host smart-22d11f8d-7e23-453c-8741-76dcc8d84dd8
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler
_lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751849280 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_hand
ler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.chip_sw_alert_handler_lpg_sleep_mode_pings.751849280
Directory /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.1304188381
Short name T735
Test name
Test status
Simulation time 8376358220 ps
CPU time 1285.83 seconds
Started Aug 02 08:18:53 PM PDT 24
Finished Aug 02 08:40:20 PM PDT 24
Peak memory 610068 kb
Host smart-95f8c33f-56b6-4e0a-bf15-468d314c2e2e
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=1304188381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_ok.1304188381
Directory /workspace/0.chip_sw_alert_handler_ping_ok/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.987356246
Short name T1135
Test name
Test status
Simulation time 5301119888 ps
CPU time 598.19 seconds
Started Aug 02 08:18:36 PM PDT 24
Finished Aug 02 08:28:34 PM PDT 24
Peak memory 610116 kb
Host smart-7fd5741d-f7f8-476a-9ab0-0b00603c795f
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=987356246 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.987356246
Directory /workspace/0.chip_sw_alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1456708172
Short name T1254
Test name
Test status
Simulation time 255520032424 ps
CPU time 12421.4 seconds
Started Aug 02 08:18:51 PM PDT 24
Finished Aug 02 11:45:54 PM PDT 24
Peak memory 610832 kb
Host smart-747b04ef-b1b9-41b9-a987-6d134a408a63
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n
ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456708172 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1456708172
Directory /workspace/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest

Test location /workspace/coverage/default/0.chip_sw_all_escalation_resets.839973141
Short name T806
Test name
Test status
Simulation time 6079326560 ps
CPU time 630.64 seconds
Started Aug 02 08:20:27 PM PDT 24
Finished Aug 02 08:30:58 PM PDT 24
Peak memory 650320 kb
Host smart-78be6462-5dd8-43df-9dfa-188b15432b51
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
839973141 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.839973141
Directory /workspace/0.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/0.chip_sw_aon_timer_irq.956230889
Short name T1334
Test name
Test status
Simulation time 4116856296 ps
CPU time 494.27 seconds
Started Aug 02 08:20:40 PM PDT 24
Finished Aug 02 08:28:55 PM PDT 24
Peak memory 609276 kb
Host smart-7b8503e9-fe60-4c0c-a466-c83607adb139
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956230889 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.956230889
Directory /workspace/0.chip_sw_aon_timer_irq/latest

Test location /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2519040839
Short name T1102
Test name
Test status
Simulation time 7301621768 ps
CPU time 458.68 seconds
Started Aug 02 08:20:08 PM PDT 24
Finished Aug 02 08:27:47 PM PDT 24
Peak memory 610580 kb
Host smart-cc201c16-322b-4252-b8b1-13c6a7a2bd24
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2519040839 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2519040839
Directory /workspace/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.4104351345
Short name T283
Test name
Test status
Simulation time 3354120928 ps
CPU time 236.73 seconds
Started Aug 02 08:21:17 PM PDT 24
Finished Aug 02 08:25:13 PM PDT 24
Peak memory 609284 kb
Host smart-a15d3602-5b54-4e13-a88e-a8ffaa296a7e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104351345 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.chip_sw_aon_timer_smoketest.4104351345
Directory /workspace/0.chip_sw_aon_timer_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2863974520
Short name T1055
Test name
Test status
Simulation time 9756930440 ps
CPU time 880.36 seconds
Started Aug 02 08:20:08 PM PDT 24
Finished Aug 02 08:34:49 PM PDT 24
Peak memory 610568 kb
Host smart-0225f73d-6262-42c6-9bdc-a1588998da0d
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2863974520 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.2863974520
Directory /workspace/0.chip_sw_aon_timer_wdog_bite_reset/latest

Test location /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3155393916
Short name T1354
Test name
Test status
Simulation time 5471757720 ps
CPU time 550.24 seconds
Started Aug 02 08:19:11 PM PDT 24
Finished Aug 02 08:28:22 PM PDT 24
Peak memory 610704 kb
Host smart-91656ea6-08d5-42d3-ba0f-175994788ea8
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3155393916 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.3155393916
Directory /workspace/0.chip_sw_aon_timer_wdog_lc_escalate/latest

Test location /workspace/coverage/default/0.chip_sw_ast_clk_outputs.605158068
Short name T1051
Test name
Test status
Simulation time 7630868420 ps
CPU time 873.38 seconds
Started Aug 02 08:20:21 PM PDT 24
Finished Aug 02 08:34:55 PM PDT 24
Peak memory 617360 kb
Host smart-41b4407b-d646-4a00-91c3-746884642f19
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605158068 -assert nopos
tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.605158068
Directory /workspace/0.chip_sw_ast_clk_outputs/latest

Test location /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.896231761
Short name T135
Test name
Test status
Simulation time 21800295433 ps
CPU time 3451.98 seconds
Started Aug 02 08:24:18 PM PDT 24
Finished Aug 02 09:21:51 PM PDT 24
Peak memory 610676 kb
Host smart-5cbdcf08-d842-4b82-a82f-4b591c72ddbc
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896231761 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_rst_inputs.896231761
Directory /workspace/0.chip_sw_ast_clk_rst_inputs/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.297374073
Short name T1127
Test name
Test status
Simulation time 7217119127 ps
CPU time 392.68 seconds
Started Aug 02 08:18:24 PM PDT 24
Finished Aug 02 08:24:57 PM PDT 24
Peak memory 621456 kb
Host smart-41879d14-13fc-4657-a826-7b1702dcf726
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r
ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim
.tcl +ntb_random_seed=297374073 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.297374073
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_lc/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2428001824
Short name T51
Test name
Test status
Simulation time 4289918190 ps
CPU time 626.1 seconds
Started Aug 02 08:19:26 PM PDT 24
Finished Aug 02 08:29:53 PM PDT 24
Peak memory 612124 kb
Host smart-c42ec89e-2ddb-444a-927a-afcd7ea9f3de
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428001824 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c
lkmgr_external_clk_src_for_sw_fast_rma.2428001824
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.774778520
Short name T70
Test name
Test status
Simulation time 4433746144 ps
CPU time 588.29 seconds
Started Aug 02 08:20:48 PM PDT 24
Finished Aug 02 08:30:37 PM PDT 24
Peak memory 612948 kb
Host smart-131b2cb9-f37b-4253-bf55-b3b9248e2e99
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_
dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774778520 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM
_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.774778520
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2625863851
Short name T1116
Test name
Test status
Simulation time 5076797182 ps
CPU time 681.93 seconds
Started Aug 02 08:22:01 PM PDT 24
Finished Aug 02 08:33:24 PM PDT 24
Peak memory 612160 kb
Host smart-faa80c4e-c269-4ba0-bb02-b7f400633dc4
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625863851 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c
lkmgr_external_clk_src_for_sw_slow_dev.2625863851
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1399716066
Short name T1017
Test name
Test status
Simulation time 5230501408 ps
CPU time 557.26 seconds
Started Aug 02 08:19:03 PM PDT 24
Finished Aug 02 08:28:20 PM PDT 24
Peak memory 612876 kb
Host smart-a40c8d41-e369-49d8-a518-8017e3d5dc96
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399716066 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c
lkmgr_external_clk_src_for_sw_slow_rma.1399716066
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1422648333
Short name T119
Test name
Test status
Simulation time 4917496818 ps
CPU time 659.2 seconds
Started Aug 02 08:18:40 PM PDT 24
Finished Aug 02 08:29:39 PM PDT 24
Peak memory 613164 kb
Host smart-847ffc63-85cd-496d-8fcd-f9491c80a179
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_
dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422648333 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV
M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1422648333
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_jitter.4236060770
Short name T982
Test name
Test status
Simulation time 2755186785 ps
CPU time 247.96 seconds
Started Aug 02 08:23:55 PM PDT 24
Finished Aug 02 08:28:03 PM PDT 24
Peak memory 609616 kb
Host smart-9931247a-de85-4314-bb1f-bc063d7ceea0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236060770 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.chip_sw_clkmgr_jitter.4236060770
Directory /workspace/0.chip_sw_clkmgr_jitter/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.1926791008
Short name T932
Test name
Test status
Simulation time 3956454764 ps
CPU time 336.29 seconds
Started Aug 02 08:19:54 PM PDT 24
Finished Aug 02 08:25:31 PM PDT 24
Peak memory 609788 kb
Host smart-06208fb5-9ceb-43b9-89cc-4a8a43407ec0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926791008 -assert nopostproc +UV
M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_frequency.1926791008
Directory /workspace/0.chip_sw_clkmgr_jitter_frequency/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.563148541
Short name T1312
Test name
Test status
Simulation time 3037918233 ps
CPU time 185.92 seconds
Started Aug 02 08:19:23 PM PDT 24
Finished Aug 02 08:22:29 PM PDT 24
Peak memory 609300 kb
Host smart-2044fbf1-f913-4abd-a045-c398ab3a5e33
User root
Command /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563148541 -assert nopo
stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.563148541
Directory /workspace/0.chip_sw_clkmgr_jitter_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.2775418714
Short name T421
Test name
Test status
Simulation time 5135311800 ps
CPU time 605.99 seconds
Started Aug 02 08:22:10 PM PDT 24
Finished Aug 02 08:32:16 PM PDT 24
Peak memory 610196 kb
Host smart-81e94546-b1f9-4929-a508-08fd7af0c179
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775418714 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.2775418714
Directory /workspace/0.chip_sw_clkmgr_off_aes_trans/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.1142017104
Short name T948
Test name
Test status
Simulation time 5257439292 ps
CPU time 653.48 seconds
Started Aug 02 08:20:38 PM PDT 24
Finished Aug 02 08:31:32 PM PDT 24
Peak memory 610196 kb
Host smart-67a6951e-a1fb-40f6-8789-713007aedf91
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142017104 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.1142017104
Directory /workspace/0.chip_sw_clkmgr_off_hmac_trans/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.1773204424
Short name T1048
Test name
Test status
Simulation time 5046522836 ps
CPU time 575.51 seconds
Started Aug 02 08:20:02 PM PDT 24
Finished Aug 02 08:29:38 PM PDT 24
Peak memory 610552 kb
Host smart-d389aff1-3bc4-4b4f-8eb8-6617d0561029
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773204424 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.1773204424
Directory /workspace/0.chip_sw_clkmgr_off_kmac_trans/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2941930821
Short name T921
Test name
Test status
Simulation time 4969646528 ps
CPU time 484.98 seconds
Started Aug 02 08:19:57 PM PDT 24
Finished Aug 02 08:28:02 PM PDT 24
Peak memory 610456 kb
Host smart-be7a6324-e4f0-49b8-9930-4c873458eeaf
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941930821 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.chip_sw_clkmgr_off_otbn_trans.2941930821
Directory /workspace/0.chip_sw_clkmgr_off_otbn_trans/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.266855371
Short name T1113
Test name
Test status
Simulation time 9305227008 ps
CPU time 1516 seconds
Started Aug 02 08:23:09 PM PDT 24
Finished Aug 02 08:48:26 PM PDT 24
Peak memory 610504 kb
Host smart-04b7aafd-cf7f-40b2-a4b1-f739fb3c077c
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266855371
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.266855371
Directory /workspace/0.chip_sw_clkmgr_off_peri/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.838163385
Short name T105
Test name
Test status
Simulation time 3867406560 ps
CPU time 447.9 seconds
Started Aug 02 08:21:15 PM PDT 24
Finished Aug 02 08:28:44 PM PDT 24
Peak memory 609924 kb
Host smart-c8e97014-74a8-422a-9c0f-9b9d1ea325ed
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838163385 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.838163385
Directory /workspace/0.chip_sw_clkmgr_reset_frequency/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.3075529808
Short name T1191
Test name
Test status
Simulation time 4305989730 ps
CPU time 661.09 seconds
Started Aug 02 08:23:15 PM PDT 24
Finished Aug 02 08:34:17 PM PDT 24
Peak memory 610308 kb
Host smart-7d3b3f39-99d1-460a-a145-f9972bfc0cf6
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075529808 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.3075529808
Directory /workspace/0.chip_sw_clkmgr_sleep_frequency/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.1083460881
Short name T918
Test name
Test status
Simulation time 2601335000 ps
CPU time 232.44 seconds
Started Aug 02 08:23:33 PM PDT 24
Finished Aug 02 08:27:26 PM PDT 24
Peak memory 608548 kb
Host smart-d73d4812-4b21-4dbd-ae7b-67386d309ee0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083460881 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.chip_sw_clkmgr_smoketest.1083460881
Directory /workspace/0.chip_sw_clkmgr_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_coremark.971171362
Short name T1260
Test name
Test status
Simulation time 71361731240 ps
CPU time 14522.6 seconds
Started Aug 02 08:19:10 PM PDT 24
Finished Aug 03 12:21:14 AM PDT 24
Peak memory 610448 kb
Host smart-9c8c779b-6356-40a2-9b13-698320f70397
User root
Command /workspace/default/simv +en_uart_logger=1 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=coremark_test:1:new_rules,test_rom:0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=971171362 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_coremark.971171362
Directory /workspace/0.chip_sw_coremark/latest

Test location /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.589978167
Short name T946
Test name
Test status
Simulation time 18095768290 ps
CPU time 4605.75 seconds
Started Aug 02 08:20:28 PM PDT 24
Finished Aug 02 09:37:14 PM PDT 24
Peak memory 610264 kb
Host smart-14ab138f-96b0-45d9-ba2e-8fa0d4c108d6
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589978167 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency.589978167
Directory /workspace/0.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1152003249
Short name T185
Test name
Test status
Simulation time 3998273560 ps
CPU time 450.42 seconds
Started Aug 02 08:19:34 PM PDT 24
Finished Aug 02 08:27:05 PM PDT 24
Peak memory 610464 kb
Host smart-4ce3e2cd-4153-4414-b115-eef0d5b6d881
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11520
03249 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.1152003249
Directory /workspace/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest

Test location /workspace/coverage/default/0.chip_sw_csrng_kat_test.1830015977
Short name T311
Test name
Test status
Simulation time 3100829000 ps
CPU time 171.22 seconds
Started Aug 02 08:20:23 PM PDT 24
Finished Aug 02 08:23:15 PM PDT 24
Peak memory 609692 kb
Host smart-f97e04fb-f76b-42a7-843c-47c56baac38b
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830015977 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.1830015977
Directory /workspace/0.chip_sw_csrng_kat_test/latest

Test location /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.3616488160
Short name T1183
Test name
Test status
Simulation time 7303624750 ps
CPU time 674.42 seconds
Started Aug 02 08:20:22 PM PDT 24
Finished Aug 02 08:31:37 PM PDT 24
Peak memory 611132 kb
Host smart-41ff0a34-e8da-4733-9957-522820cde76a
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima
ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616488160 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_
lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csr
ng_lc_hw_debug_en_test.3616488160
Directory /workspace/0.chip_sw_csrng_lc_hw_debug_en_test/latest

Test location /workspace/coverage/default/0.chip_sw_csrng_smoketest.3312553287
Short name T1167
Test name
Test status
Simulation time 2998151982 ps
CPU time 227.95 seconds
Started Aug 02 08:24:57 PM PDT 24
Finished Aug 02 08:28:45 PM PDT 24
Peak memory 609620 kb
Host smart-3b01bed0-cec3-4b26-96f4-58e208e34790
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312553287 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.chip_sw_csrng_smoketest.3312553287
Directory /workspace/0.chip_sw_csrng_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_data_integrity_escalation.410461899
Short name T1236
Test name
Test status
Simulation time 6407752464 ps
CPU time 647.84 seconds
Started Aug 02 08:17:17 PM PDT 24
Finished Aug 02 08:28:06 PM PDT 24
Peak memory 610904 kb
Host smart-549c6d0d-183e-48a3-be75-1cd7b5f76ed9
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=410461899 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.410461899
Directory /workspace/0.chip_sw_data_integrity_escalation/latest

Test location /workspace/coverage/default/0.chip_sw_edn_auto_mode.367824456
Short name T120
Test name
Test status
Simulation time 4533535300 ps
CPU time 1040.55 seconds
Started Aug 02 08:21:08 PM PDT 24
Finished Aug 02 08:38:29 PM PDT 24
Peak memory 610052 kb
Host smart-061bf303-d7a9-4abc-b501-cc44705b4197
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_
build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367824456 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_a
uto_mode.367824456
Directory /workspace/0.chip_sw_edn_auto_mode/latest

Test location /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2506946028
Short name T244
Test name
Test status
Simulation time 5666988649 ps
CPU time 827.54 seconds
Started Aug 02 08:20:46 PM PDT 24
Finished Aug 02 08:34:34 PM PDT 24
Peak memory 611092 kb
Host smart-75b54f34-ec67-48e1-b270-65bad64d93d5
User root
Command /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e
ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506946028 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.2506946028
Directory /workspace/0.chip_sw_edn_entropy_reqs_jitter/latest

Test location /workspace/coverage/default/0.chip_sw_edn_kat.1827995665
Short name T121
Test name
Test status
Simulation time 3573386052 ps
CPU time 494.82 seconds
Started Aug 02 08:18:50 PM PDT 24
Finished Aug 02 08:27:05 PM PDT 24
Peak memory 615576 kb
Host smart-d38b5bee-9bcc-4f61-90fb-f1d26d95de10
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3
+accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827995665 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.chip_sw_edn_kat.1827995665
Directory /workspace/0.chip_sw_edn_kat/latest

Test location /workspace/coverage/default/0.chip_sw_edn_sw_mode.1478776634
Short name T1315
Test name
Test status
Simulation time 8693591064 ps
CPU time 1816.23 seconds
Started Aug 02 08:19:45 PM PDT 24
Finished Aug 02 08:50:02 PM PDT 24
Peak memory 609648 kb
Host smart-303605b8-281b-4892-abb2-7116b54b84d2
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478776634 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_sw_mode.1478776634
Directory /workspace/0.chip_sw_edn_sw_mode/latest

Test location /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.474292805
Short name T1081
Test name
Test status
Simulation time 3258220376 ps
CPU time 322.65 seconds
Started Aug 02 08:18:57 PM PDT 24
Finished Aug 02 08:24:21 PM PDT 24
Peak memory 609684 kb
Host smart-3a307d5e-1348-4897-962c-cf861b31516c
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47
4292805 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.474292805
Directory /workspace/0.chip_sw_entropy_src_ast_rng_req/latest

Test location /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.3289702020
Short name T1041
Test name
Test status
Simulation time 2527519278 ps
CPU time 248.96 seconds
Started Aug 02 08:18:43 PM PDT 24
Finished Aug 02 08:22:52 PM PDT 24
Peak memory 609732 kb
Host smart-1d117a1d-e0d2-4c15-8288-076c9a224a12
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289702020
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.3289702020
Directory /workspace/0.chip_sw_entropy_src_kat_test/latest

Test location /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.3109308563
Short name T934
Test name
Test status
Simulation time 4278102320 ps
CPU time 453.54 seconds
Started Aug 02 08:21:15 PM PDT 24
Finished Aug 02 08:28:49 PM PDT 24
Peak memory 609792 kb
Host smart-7cba51d3-bee4-4729-9d96-e103c1969353
User root
Command /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom:
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3109308563 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.3109308563
Directory /workspace/0.chip_sw_entropy_src_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_example_concurrency.2097464807
Short name T1223
Test name
Test status
Simulation time 2738406340 ps
CPU time 324.75 seconds
Started Aug 02 08:18:26 PM PDT 24
Finished Aug 02 08:23:52 PM PDT 24
Peak memory 609676 kb
Host smart-47d7b575-eaea-4b56-93b3-ba67ed307818
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097464807 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.chip_sw_example_concurrency.2097464807
Directory /workspace/0.chip_sw_example_concurrency/latest

Test location /workspace/coverage/default/0.chip_sw_example_flash.2837013144
Short name T991
Test name
Test status
Simulation time 2898152672 ps
CPU time 180.85 seconds
Started Aug 02 08:18:17 PM PDT 24
Finished Aug 02 08:21:18 PM PDT 24
Peak memory 609616 kb
Host smart-6b9a709e-2a48-4888-a8be-fb258892bf31
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837013144 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.chip_sw_example_flash.2837013144
Directory /workspace/0.chip_sw_example_flash/latest

Test location /workspace/coverage/default/0.chip_sw_example_manufacturer.257586304
Short name T1394
Test name
Test status
Simulation time 2461389732 ps
CPU time 299.36 seconds
Started Aug 02 08:18:14 PM PDT 24
Finished Aug 02 08:23:14 PM PDT 24
Peak memory 609336 kb
Host smart-86e10851-70e3-4e19-9325-b4e2e6f65118
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257586304 -assert nopostproc +UVM_TESTNAME=chip_b
ase_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 0.chip_sw_example_manufacturer.257586304
Directory /workspace/0.chip_sw_example_manufacturer/latest

Test location /workspace/coverage/default/0.chip_sw_example_rom.238342457
Short name T1376
Test name
Test status
Simulation time 2270205848 ps
CPU time 127.63 seconds
Started Aug 02 08:17:32 PM PDT 24
Finished Aug 02 08:19:40 PM PDT 24
Peak memory 609088 kb
Host smart-e20c5870-6a54-4359-abda-3be6c63bf45b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238342457 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.chip_sw_example_rom.238342457
Directory /workspace/0.chip_sw_example_rom/latest

Test location /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.3329173435
Short name T147
Test name
Test status
Simulation time 57697145720 ps
CPU time 11336.7 seconds
Started Aug 02 08:16:44 PM PDT 24
Finished Aug 02 11:25:42 PM PDT 24
Peak memory 624820 kb
Host smart-45b37d58-29b3-46ee-bdd6-4d99e8a54162
User root
Command /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new
_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s
im.tcl +ntb_random_seed=3329173435 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_exit_test_unlocked_bootstrap.3329173435
Directory /workspace/0.chip_sw_exit_test_unlocked_bootstrap/latest

Test location /workspace/coverage/default/0.chip_sw_flash_crash_alert.2877159688
Short name T937
Test name
Test status
Simulation time 5035726712 ps
CPU time 672.57 seconds
Started Aug 02 08:21:27 PM PDT 24
Finished Aug 02 08:32:40 PM PDT 24
Peak memory 611208 kb
Host smart-d3839ee5-795f-4af5-b479-5bbaf508274b
User root
Command /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:
new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool
s/sim.tcl +ntb_random_seed=2877159688 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.2877159688
Directory /workspace/0.chip_sw_flash_crash_alert/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_access.437167306
Short name T1350
Test name
Test status
Simulation time 5190639160 ps
CPU time 946.21 seconds
Started Aug 02 08:18:11 PM PDT 24
Finished Aug 02 08:33:58 PM PDT 24
Peak memory 610060 kb
Host smart-519a2246-2321-4aff-8daf-2198b449d7d8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437167306 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.chip_sw_flash_ctrl_access.437167306
Directory /workspace/0.chip_sw_flash_ctrl_access/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.2144808987
Short name T1392
Test name
Test status
Simulation time 5693425549 ps
CPU time 1090.29 seconds
Started Aug 02 08:18:26 PM PDT 24
Finished Aug 02 08:36:37 PM PDT 24
Peak memory 610080 kb
Host smart-3d5727b4-824e-40c6-bb6d-b2c30c30a321
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144808987 -assert nopostproc +UV
M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en.2144808987
Directory /workspace/0.chip_sw_flash_ctrl_access_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.280266165
Short name T1347
Test name
Test status
Simulation time 7270215445 ps
CPU time 1325.75 seconds
Started Aug 02 08:22:08 PM PDT 24
Finished Aug 02 08:44:15 PM PDT 24
Peak memory 610236 kb
Host smart-2035afbc-ec98-4606-ad77-77f4dd696545
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280266165 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.280266165
Directory /workspace/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.1166533418
Short name T95
Test name
Test status
Simulation time 5683292336 ps
CPU time 952.18 seconds
Started Aug 02 08:17:10 PM PDT 24
Finished Aug 02 08:33:02 PM PDT 24
Peak memory 609816 kb
Host smart-343b7fe8-d08d-4dfa-a692-3771f8b2a3a5
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166533418 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.chip_sw_flash_ctrl_clock_freqs.1166533418
Directory /workspace/0.chip_sw_flash_ctrl_clock_freqs/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.738193067
Short name T1100
Test name
Test status
Simulation time 3187413728 ps
CPU time 401.9 seconds
Started Aug 02 08:20:40 PM PDT 24
Finished Aug 02 08:27:23 PM PDT 24
Peak memory 609912 kb
Host smart-390e15f8-aeb4-46e1-9cd6-4d212edf23cc
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738193067 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_idle_low_power.738193067
Directory /workspace/0.chip_sw_flash_ctrl_idle_low_power/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.976428363
Short name T1034
Test name
Test status
Simulation time 5921013064 ps
CPU time 1161.65 seconds
Started Aug 02 08:19:34 PM PDT 24
Finished Aug 02 08:38:56 PM PDT 24
Peak memory 610028 kb
Host smart-13f1f85b-a42d-4a2d-95a6-9afde75c2243
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976428363 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_mem_protection.976428363
Directory /workspace/0.chip_sw_flash_ctrl_mem_protection/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2336126227
Short name T1360
Test name
Test status
Simulation time 4543103728 ps
CPU time 718.77 seconds
Started Aug 02 08:20:42 PM PDT 24
Finished Aug 02 08:32:43 PM PDT 24
Peak memory 610160 kb
Host smart-486ad34c-2f51-4ffd-ac97-2f0191396455
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336126227
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.2336126227
Directory /workspace/0.chip_sw_flash_ctrl_ops/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.3328166716
Short name T278
Test name
Test status
Simulation time 3703493013 ps
CPU time 734.69 seconds
Started Aug 02 08:20:29 PM PDT 24
Finished Aug 02 08:32:44 PM PDT 24
Peak memory 609884 kb
Host smart-658aabf0-2e3f-4954-968e-4ced71ec6b4b
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3328166716 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.3328166716
Directory /workspace/0.chip_sw_flash_ctrl_ops_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1833643414
Short name T334
Test name
Test status
Simulation time 4716975342 ps
CPU time 823.05 seconds
Started Aug 02 08:23:20 PM PDT 24
Finished Aug 02 08:37:04 PM PDT 24
Peak memory 610268 kb
Host smart-b0e22e23-0f78-478a-8893-8f32c925554e
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_
rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1833643414 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1833643414
Directory /workspace/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.1142730348
Short name T1388
Test name
Test status
Simulation time 3087738610 ps
CPU time 386.69 seconds
Started Aug 02 08:22:31 PM PDT 24
Finished Aug 02 08:28:58 PM PDT 24
Peak memory 609776 kb
Host smart-2754f7b7-b5ae-4fcc-9f6c-e93af86d0a03
User root
Command /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142730
348 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_write_clear.1142730348
Directory /workspace/0.chip_sw_flash_ctrl_write_clear/latest

Test location /workspace/coverage/default/0.chip_sw_flash_init.2700622629
Short name T168
Test name
Test status
Simulation time 23051563208 ps
CPU time 2362.54 seconds
Started Aug 02 08:16:53 PM PDT 24
Finished Aug 02 08:56:17 PM PDT 24
Peak memory 611612 kb
Host smart-5a4dc394-59f5-417c-8b63-f94d8381b51b
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700622629 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init.2700622629
Directory /workspace/0.chip_sw_flash_init/latest

Test location /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2098239444
Short name T167
Test name
Test status
Simulation time 23215616605 ps
CPU time 2254.51 seconds
Started Aug 02 08:21:16 PM PDT 24
Finished Aug 02 08:58:52 PM PDT 24
Peak memory 612496 kb
Host smart-2942c9a7-9302-4835-bd4b-748b965c1751
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2098239444 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.2098239444
Directory /workspace/0.chip_sw_flash_init_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.2424642966
Short name T1287
Test name
Test status
Simulation time 2719900610 ps
CPU time 188.33 seconds
Started Aug 02 08:30:21 PM PDT 24
Finished Aug 02 08:33:29 PM PDT 24
Peak memory 609756 kb
Host smart-fff158fc-54bb-418e-976c-d6e98ac5345e
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket
est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2424642966 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.2424642966
Directory /workspace/0.chip_sw_flash_scrambling_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_gpio_smoketest.1807336840
Short name T1241
Test name
Test status
Simulation time 3524205046 ps
CPU time 269.46 seconds
Started Aug 02 08:21:55 PM PDT 24
Finished Aug 02 08:26:25 PM PDT 24
Peak memory 608664 kb
Host smart-ff14cac0-e9e0-476d-b775-1816189b8975
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807336840 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.chip_sw_gpio_smoketest.1807336840
Directory /workspace/0.chip_sw_gpio_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_enc.321545156
Short name T376
Test name
Test status
Simulation time 2665833924 ps
CPU time 237.83 seconds
Started Aug 02 08:17:28 PM PDT 24
Finished Aug 02 08:21:26 PM PDT 24
Peak memory 609772 kb
Host smart-5cae9377-f87e-4428-9fc0-f38288dadb56
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321545156 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.chip_sw_hmac_enc.321545156
Directory /workspace/0.chip_sw_hmac_enc/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_enc_idle.235595438
Short name T1006
Test name
Test status
Simulation time 2936519724 ps
CPU time 274.8 seconds
Started Aug 02 08:21:38 PM PDT 24
Finished Aug 02 08:26:13 PM PDT 24
Peak memory 608500 kb
Host smart-36a3650f-9183-47f1-84ae-139de2b8cf84
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235595438 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.chip_sw_hmac_enc_idle.235595438
Directory /workspace/0.chip_sw_hmac_enc_idle/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.118170360
Short name T117
Test name
Test status
Simulation time 2892517906 ps
CPU time 223.32 seconds
Started Aug 02 08:20:06 PM PDT 24
Finished Aug 02 08:23:50 PM PDT 24
Peak memory 609576 kb
Host smart-e824e2f0-c179-40b0-92a8-c59e402f25ac
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118170360 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en.118170360
Directory /workspace/0.chip_sw_hmac_enc_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1466867133
Short name T1340
Test name
Test status
Simulation time 2756711636 ps
CPU time 218.75 seconds
Started Aug 02 08:19:45 PM PDT 24
Finished Aug 02 08:23:24 PM PDT 24
Peak memory 609772 kb
Host smart-4e44eead-4d49-4e35-a260-84de70a378e6
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466867133 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.1466867133
Directory /workspace/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_multistream.3979759871
Short name T1231
Test name
Test status
Simulation time 8520591700 ps
CPU time 1851.36 seconds
Started Aug 02 08:18:27 PM PDT 24
Finished Aug 02 08:49:19 PM PDT 24
Peak memory 608924 kb
Host smart-589282d7-1e8a-4bab-8844-53347f933130
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979759871 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.chip_sw_hmac_multistream.3979759871
Directory /workspace/0.chip_sw_hmac_multistream/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_oneshot.1814806652
Short name T1404
Test name
Test status
Simulation time 3306517714 ps
CPU time 358.43 seconds
Started Aug 02 08:19:47 PM PDT 24
Finished Aug 02 08:25:46 PM PDT 24
Peak memory 609684 kb
Host smart-c51ce582-85da-469e-8890-4a3661629ce9
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814806652 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.chip_sw_hmac_oneshot.1814806652
Directory /workspace/0.chip_sw_hmac_oneshot/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_smoketest.533809335
Short name T927
Test name
Test status
Simulation time 3214934536 ps
CPU time 515.19 seconds
Started Aug 02 08:23:11 PM PDT 24
Finished Aug 02 08:31:46 PM PDT 24
Peak memory 609328 kb
Host smart-da7f1e76-c061-41c9-b952-91af0d248f73
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533809335 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.chip_sw_hmac_smoketest.533809335
Directory /workspace/0.chip_sw_hmac_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.1255971410
Short name T351
Test name
Test status
Simulation time 3990518124 ps
CPU time 535.85 seconds
Started Aug 02 08:20:38 PM PDT 24
Finished Aug 02 08:29:35 PM PDT 24
Peak memory 609788 kb
Host smart-cf27d01c-29b4-4716-a202-6cb221ef9d8d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255971410 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.chip_sw_i2c_device_tx_rx.1255971410
Directory /workspace/0.chip_sw_i2c_device_tx_rx/latest

Test location /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.805508505
Short name T339
Test name
Test status
Simulation time 4192072586 ps
CPU time 796.21 seconds
Started Aug 02 08:20:56 PM PDT 24
Finished Aug 02 08:34:13 PM PDT 24
Peak memory 609788 kb
Host smart-657cb724-27e3-4cb0-9feb-e619cde30033
User root
Command /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805508505 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.805508505
Directory /workspace/0.chip_sw_i2c_host_tx_rx_idx1/latest

Test location /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2708192456
Short name T215
Test name
Test status
Simulation time 4313089928 ps
CPU time 531.75 seconds
Started Aug 02 08:19:06 PM PDT 24
Finished Aug 02 08:27:58 PM PDT 24
Peak memory 610232 kb
Host smart-0b59a143-b41c-4137-a9cd-59e2fdb2639e
User root
Command /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708192456 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.2708192456
Directory /workspace/0.chip_sw_i2c_host_tx_rx_idx2/latest

Test location /workspace/coverage/default/0.chip_sw_inject_scramble_seed.4043239832
Short name T205
Test name
Test status
Simulation time 65223598285 ps
CPU time 12980.3 seconds
Started Aug 02 08:18:57 PM PDT 24
Finished Aug 02 11:55:19 PM PDT 24
Peak memory 624796 kb
Host smart-2a2b3e21-50d2-4a5f-9372-a846be01b793
User root
Command /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4043239832 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.4043239832
Directory /workspace/0.chip_sw_inject_scramble_seed/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.3969335915
Short name T1216
Test name
Test status
Simulation time 9318966032 ps
CPU time 2048.11 seconds
Started Aug 02 08:23:05 PM PDT 24
Finished Aug 02 08:57:14 PM PDT 24
Peak memory 617708 kb
Host smart-fb46734f-9cf1-4ef8-b2ce-184ac2934fab
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969
335915 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation.3969335915
Directory /workspace/0.chip_sw_keymgr_key_derivation/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3408854674
Short name T1359
Test name
Test status
Simulation time 11028963718 ps
CPU time 2838.18 seconds
Started Aug 02 08:20:16 PM PDT 24
Finished Aug 02 09:07:35 PM PDT 24
Peak memory 616608 kb
Host smart-32b68bd7-fac8-427d-a0cf-6c664d0ec7f9
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3408854674 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en.3408854674
Directory /workspace/0.chip_sw_keymgr_key_derivation_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_app_rom.877987690
Short name T88
Test name
Test status
Simulation time 3382224440 ps
CPU time 251.02 seconds
Started Aug 02 08:19:46 PM PDT 24
Finished Aug 02 08:23:57 PM PDT 24
Peak memory 608396 kb
Host smart-539f72eb-26cb-4a27-983d-837746f3b7fd
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877987690 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.chip_sw_kmac_app_rom.877987690
Directory /workspace/0.chip_sw_kmac_app_rom/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_entropy.3249581327
Short name T1237
Test name
Test status
Simulation time 3068446620 ps
CPU time 219.06 seconds
Started Aug 02 08:19:06 PM PDT 24
Finished Aug 02 08:22:46 PM PDT 24
Peak memory 609776 kb
Host smart-9b57b443-0b73-4dcb-8fa7-be665f0d84e3
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249581327 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.chip_sw_kmac_entropy.3249581327
Directory /workspace/0.chip_sw_kmac_entropy/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_idle.252243928
Short name T1221
Test name
Test status
Simulation time 2949718594 ps
CPU time 298.06 seconds
Started Aug 02 08:19:38 PM PDT 24
Finished Aug 02 08:24:37 PM PDT 24
Peak memory 609648 kb
Host smart-197ff387-ddca-4c85-9a76-7ff169cd7906
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252243928 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.chip_sw_kmac_idle.252243928
Directory /workspace/0.chip_sw_kmac_idle/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.1065550305
Short name T975
Test name
Test status
Simulation time 2695585010 ps
CPU time 188 seconds
Started Aug 02 08:18:27 PM PDT 24
Finished Aug 02 08:21:35 PM PDT 24
Peak memory 608424 kb
Host smart-7287c1bb-4e08-4ea7-8a7b-1bb4a79ab5f0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065550305 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.chip_sw_kmac_mode_cshake.1065550305
Directory /workspace/0.chip_sw_kmac_mode_cshake/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.492926788
Short name T1086
Test name
Test status
Simulation time 2670541684 ps
CPU time 263.12 seconds
Started Aug 02 08:18:06 PM PDT 24
Finished Aug 02 08:22:29 PM PDT 24
Peak memory 609268 kb
Host smart-8dc96e3f-52e5-4f5d-be42-945b66c58cca
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492926788 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.chip_sw_kmac_mode_kmac.492926788
Directory /workspace/0.chip_sw_kmac_mode_kmac/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.4268996325
Short name T1192
Test name
Test status
Simulation time 3186657059 ps
CPU time 259.82 seconds
Started Aug 02 08:21:33 PM PDT 24
Finished Aug 02 08:25:54 PM PDT 24
Peak memory 609676 kb
Host smart-3bb79159-adfd-4da3-b5ac-75cda6c14025
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268996325 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.4268996325
Directory /workspace/0.chip_sw_kmac_mode_kmac_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2048343632
Short name T987
Test name
Test status
Simulation time 3633745875 ps
CPU time 277.19 seconds
Started Aug 02 08:24:26 PM PDT 24
Finished Aug 02 08:29:03 PM PDT 24
Peak memory 609832 kb
Host smart-de35091f-edbf-420a-897c-73120b345b9c
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20483436
32 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2048343632
Directory /workspace/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_smoketest.1966468547
Short name T1040
Test name
Test status
Simulation time 2652986832 ps
CPU time 230.42 seconds
Started Aug 02 08:22:13 PM PDT 24
Finished Aug 02 08:26:03 PM PDT 24
Peak memory 609600 kb
Host smart-11975d39-dae4-4f5e-8c21-42f962d574f5
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966468547 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.chip_sw_kmac_smoketest.1966468547
Directory /workspace/0.chip_sw_kmac_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.1441811655
Short name T302
Test name
Test status
Simulation time 3223653240 ps
CPU time 350.4 seconds
Started Aug 02 08:20:44 PM PDT 24
Finished Aug 02 08:26:35 PM PDT 24
Peak memory 609312 kb
Host smart-516dc7c0-a935-46ba-9f30-a39911889561
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441811655 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.chip_sw_lc_ctrl_otp_hw_cfg0.1441811655
Directory /workspace/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2429066350
Short name T718
Test name
Test status
Simulation time 3371259372 ps
CPU time 244.02 seconds
Started Aug 02 08:18:40 PM PDT 24
Finished Aug 02 08:22:44 PM PDT 24
Peak memory 621676 kb
Host smart-a4f2303a-8539-4a65-9ef5-198681c34e11
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24290663
50 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.2429066350
Directory /workspace/0.chip_sw_lc_ctrl_rand_to_scrap/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.1454814888
Short name T175
Test name
Test status
Simulation time 3487178142 ps
CPU time 179.27 seconds
Started Aug 02 08:20:22 PM PDT 24
Finished Aug 02 08:23:22 PM PDT 24
Peak memory 620672 kb
Host smart-4ea34f28-60cb-4dae-9739-7d58c32eec40
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules
,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1454814888 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.1454814888
Directory /workspace/0.chip_sw_lc_ctrl_raw_to_scrap/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3068587908
Short name T1251
Test name
Test status
Simulation time 4142366851 ps
CPU time 368.35 seconds
Started Aug 02 08:18:57 PM PDT 24
Finished Aug 02 08:25:07 PM PDT 24
Peak memory 621748 kb
Host smart-56684bb3-52cd-4f42-ac22-890a0b7e20c3
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules
,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3068587908 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.3068587908
Directory /workspace/0.chip_sw_lc_ctrl_rma_to_scrap/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.3131224093
Short name T174
Test name
Test status
Simulation time 3155066192 ps
CPU time 121.23 seconds
Started Aug 02 08:17:38 PM PDT 24
Finished Aug 02 08:19:39 PM PDT 24
Peak memory 620116 kb
Host smart-87e93c03-7860-4a89-9581-694ba591827b
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTestLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:n
ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131224093 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.3131224093
Directory /workspace/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.3260560745
Short name T189
Test name
Test status
Simulation time 5684079541 ps
CPU time 449.93 seconds
Started Aug 02 08:17:36 PM PDT 24
Finished Aug 02 08:25:06 PM PDT 24
Peak memory 624784 kb
Host smart-b360d87e-2b63-4868-b267-cbb8c2f349a7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260560745 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_transition.3260560745
Directory /workspace/0.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.2928695716
Short name T717
Test name
Test status
Simulation time 2640765751 ps
CPU time 123.14 seconds
Started Aug 02 08:19:09 PM PDT 24
Finished Aug 02 08:21:12 PM PDT 24
Peak memory 618024 kb
Host smart-a83acc76-71f3-4264-b061-8d6487162eb3
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes
t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2928695716 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.2928695716
Directory /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3337042930
Short name T715
Test name
Test status
Simulation time 2496135771 ps
CPU time 111.56 seconds
Started Aug 02 08:19:01 PM PDT 24
Finished Aug 02 08:20:53 PM PDT 24
Peak memory 617012 kb
Host smart-1d4e5206-a6f1-4ec0-9297-25fbb30847b6
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s
im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337042930 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES
T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3337042930
Directory /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest

Test location /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.3068635014
Short name T239
Test name
Test status
Simulation time 50132201604 ps
CPU time 5590.95 seconds
Started Aug 02 08:19:15 PM PDT 24
Finished Aug 02 09:52:27 PM PDT 24
Peak memory 620640 kb
Host smart-9ead5adf-1d33-41d8-91ba-01d8a5072cf1
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de
vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068635014 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c
hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip
_sw_lc_walkthrough_dev.3068635014
Directory /workspace/0.chip_sw_lc_walkthrough_dev/latest

Test location /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2712418277
Short name T243
Test name
Test status
Simulation time 45746223030 ps
CPU time 5589.65 seconds
Started Aug 02 08:20:12 PM PDT 24
Finished Aug 02 09:53:23 PM PDT 24
Peak memory 620204 kb
Host smart-09bd4b57-1a8c-4b68-b4a5-ac355bad10e9
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d
evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712418277 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi
p_sw_lc_walkthrough_prod.2712418277
Directory /workspace/0.chip_sw_lc_walkthrough_prod/latest

Test location /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.3874064929
Short name T170
Test name
Test status
Simulation time 8041319609 ps
CPU time 894.75 seconds
Started Aug 02 08:17:35 PM PDT 24
Finished Aug 02 08:32:31 PM PDT 24
Peak memory 619092 kb
Host smart-9ba2f0a4-e967-4f71-b4b0-b3974924683e
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa
lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874064929 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.3874064929
Directory /workspace/0.chip_sw_lc_walkthrough_prodend/latest

Test location /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.3291866727
Short name T1356
Test name
Test status
Simulation time 24637366612 ps
CPU time 2647.5 seconds
Started Aug 02 08:20:28 PM PDT 24
Finished Aug 02 09:04:36 PM PDT 24
Peak memory 621060 kb
Host smart-2f167be6-cf03-4ac2-9d00-8a56083d8db6
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks
_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3291866727 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_testun
locks.3291866727
Directory /workspace/0.chip_sw_lc_walkthrough_testunlocks/latest

Test location /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.341199994
Short name T346
Test name
Test status
Simulation time 17669919966 ps
CPU time 3955.76 seconds
Started Aug 02 08:21:18 PM PDT 24
Finished Aug 02 09:27:15 PM PDT 24
Peak memory 610336 kb
Host smart-e799c92d-2f26-40dd-b1c0-91ffdf18577f
User root
Command /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_
rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=341199994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.341199994
Directory /workspace/0.chip_sw_otbn_ecdsa_op_irq/latest

Test location /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2518275357
Short name T1264
Test name
Test status
Simulation time 19399567064 ps
CPU time 3697.45 seconds
Started Aug 02 08:21:40 PM PDT 24
Finished Aug 02 09:23:18 PM PDT 24
Peak memory 610384 kb
Host smart-15e26d0d-57d0-48f4-8952-75beb97de406
User root
Command /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne
w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2518275357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2518275357
Directory /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3555324157
Short name T1276
Test name
Test status
Simulation time 25052148533 ps
CPU time 4867.12 seconds
Started Aug 02 08:23:56 PM PDT 24
Finished Aug 02 09:45:04 PM PDT 24
Peak memory 610384 kb
Host smart-c370d6ae-5707-42f2-996a-357b3647a7ad
User root
Command /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e
cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555324157 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu
ced_freq.3555324157
Directory /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.489885139
Short name T293
Test name
Test status
Simulation time 3759256472 ps
CPU time 552.18 seconds
Started Aug 02 08:19:19 PM PDT 24
Finished Aug 02 08:28:31 PM PDT 24
Peak memory 608784 kb
Host smart-83122e63-8a05-4a4c-bf2f-af6ba1e6e14a
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn
_mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489885139 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.489885139
Directory /workspace/0.chip_sw_otbn_mem_scramble/latest

Test location /workspace/coverage/default/0.chip_sw_otbn_randomness.3262342703
Short name T304
Test name
Test status
Simulation time 5912442824 ps
CPU time 1039.61 seconds
Started Aug 02 08:19:35 PM PDT 24
Finished Aug 02 08:36:56 PM PDT 24
Peak memory 610360 kb
Host smart-8ea2b41a-d31e-4d53-ba03-fd5b49c40c1e
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3262342703 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.3262342703
Directory /workspace/0.chip_sw_otbn_randomness/latest

Test location /workspace/coverage/default/0.chip_sw_otbn_smoketest.2018813216
Short name T1314
Test name
Test status
Simulation time 8813463850 ps
CPU time 1912.3 seconds
Started Aug 02 08:25:49 PM PDT 24
Finished Aug 02 08:57:42 PM PDT 24
Peak memory 609008 kb
Host smart-689be514-1ad7-4401-b5df-c61e5c9b8a32
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018813216 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.chip_sw_otbn_smoketest.2018813216
Directory /workspace/0.chip_sw_otbn_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.2774804856
Short name T1400
Test name
Test status
Simulation time 27005422590 ps
CPU time 4818.49 seconds
Started Aug 02 08:19:28 PM PDT 24
Finished Aug 02 09:39:47 PM PDT 24
Peak memory 610484 kb
Host smart-876deaa6-3de9-4444-82de-2e7e279eec45
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=otp_ctrl_mem_access_test:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277480
4856 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_dai_lock.2774804856
Directory /workspace/0.chip_sw_otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.3108911507
Short name T420
Test name
Test status
Simulation time 2143707487 ps
CPU time 209.67 seconds
Started Aug 02 08:21:59 PM PDT 24
Finished Aug 02 08:25:29 PM PDT 24
Peak memory 609728 kb
Host smart-eba218fd-cee5-4993-8c9c-c2e522e4a05e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108911507 -assert nopostp
roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_ecc_error_vendor_test.3108911507
Directory /workspace/0.chip_sw_otp_ctrl_ecc_error_vendor_test/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.3005745801
Short name T1031
Test name
Test status
Simulation time 9030640304 ps
CPU time 1265.29 seconds
Started Aug 02 08:20:14 PM PDT 24
Finished Aug 02 08:41:20 PM PDT 24
Peak memory 610816 kb
Host smart-5afb0cb5-67cd-46c8-b52c-47b32106df19
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3005745801 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.3005745801
Directory /workspace/0.chip_sw_otp_ctrl_lc_signals_dev/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.785928354
Short name T224
Test name
Test status
Simulation time 7755431476 ps
CPU time 871.6 seconds
Started Aug 02 08:19:13 PM PDT 24
Finished Aug 02 08:33:45 PM PDT 24
Peak memory 610644 kb
Host smart-9885c16d-a7ac-4c26-937d-c2abb8f63f74
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=785928354 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.785928354
Directory /workspace/0.chip_sw_otp_ctrl_lc_signals_prod/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.892758078
Short name T1326
Test name
Test status
Simulation time 8741306270 ps
CPU time 1075.4 seconds
Started Aug 02 08:22:13 PM PDT 24
Finished Aug 02 08:40:08 PM PDT 24
Peak memory 610484 kb
Host smart-ec8f4410-0378-4fb0-859d-58a5f56dc0ee
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=892758078 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.892758078
Directory /workspace/0.chip_sw_otp_ctrl_lc_signals_rma/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.4013729665
Short name T276
Test name
Test status
Simulation time 4175299084 ps
CPU time 726.96 seconds
Started Aug 02 08:17:57 PM PDT 24
Finished Aug 02 08:30:04 PM PDT 24
Peak memory 609624 kb
Host smart-3984ee32-d8dd-4f9f-9e11-df337d3c9f29
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new
_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s
im.tcl +ntb_random_seed=4013729665 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.4013729665
Directory /workspace/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.4200380088
Short name T988
Test name
Test status
Simulation time 3126128808 ps
CPU time 261.94 seconds
Started Aug 02 08:23:08 PM PDT 24
Finished Aug 02 08:27:30 PM PDT 24
Peak memory 609624 kb
Host smart-653cbb9b-357b-4071-9dd1-a2709099e253
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200380088 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.chip_sw_otp_ctrl_smoketest.4200380088
Directory /workspace/0.chip_sw_otp_ctrl_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_power_sleep_load.1183913888
Short name T1358
Test name
Test status
Simulation time 9796029012 ps
CPU time 475.81 seconds
Started Aug 02 08:25:55 PM PDT 24
Finished Aug 02 08:33:51 PM PDT 24
Peak memory 610944 kb
Host smart-5aa4950b-3403-4011-9b1f-9564c65eeb8f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183913888 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.chip_sw_power_sleep_load.1183913888
Directory /workspace/0.chip_sw_power_sleep_load/latest

Test location /workspace/coverage/default/0.chip_sw_power_virus.1853303420
Short name T199
Test name
Test status
Simulation time 5565363504 ps
CPU time 1583.48 seconds
Started Aug 02 08:27:01 PM PDT 24
Finished Aug 02 08:53:25 PM PDT 24
Peak memory 625040 kb
Host smart-13cc7311-5636-4cb1-910d-33f01160f862
User root
Command /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +accelerate_cold_
power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtes
t_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1853303420 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_virus.1853303420
Directory /workspace/0.chip_sw_power_virus/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.1034128819
Short name T1016
Test name
Test status
Simulation time 9403307874 ps
CPU time 1503.34 seconds
Started Aug 02 08:22:06 PM PDT 24
Finished Aug 02 08:47:10 PM PDT 24
Peak memory 611120 kb
Host smart-454ef5a0-fdea-49e0-b5b2-40d30d3a9111
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034
128819 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.1034128819
Directory /workspace/0.chip_sw_pwrmgr_all_reset_reqs/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.3872614253
Short name T1283
Test name
Test status
Simulation time 27279717365 ps
CPU time 2961.6 seconds
Started Aug 02 08:20:02 PM PDT 24
Finished Aug 02 09:09:24 PM PDT 24
Peak memory 610640 kb
Host smart-7a583f9b-217f-4d3e-b0d1-df0790509a3a
User root
Command /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387
2614253 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.3872614253
Directory /workspace/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1335327803
Short name T18
Test name
Test status
Simulation time 21749891426 ps
CPU time 1601.21 seconds
Started Aug 02 08:22:04 PM PDT 24
Finished Aug 02 08:48:46 PM PDT 24
Peak memory 610856 kb
Host smart-dba4d76c-bb46-44ae-9393-43653f9b192d
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1335327803 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1335327803
Directory /workspace/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.2492747619
Short name T432
Test name
Test status
Simulation time 8735544540 ps
CPU time 516.08 seconds
Started Aug 02 08:18:51 PM PDT 24
Finished Aug 02 08:27:27 PM PDT 24
Peak memory 609564 kb
Host smart-8f484d36-6805-448c-8128-871ba766472a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492747619 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.2492747619
Directory /workspace/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.1650757800
Short name T1337
Test name
Test status
Simulation time 4712443492 ps
CPU time 319.36 seconds
Started Aug 02 08:19:07 PM PDT 24
Finished Aug 02 08:24:27 PM PDT 24
Peak memory 616320 kb
Host smart-4753bf68-1eca-42c0-b94a-12e9532451ac
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1650757800 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.1650757800
Directory /workspace/0.chip_sw_pwrmgr_main_power_glitch_reset/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1920426304
Short name T1304
Test name
Test status
Simulation time 9649533020 ps
CPU time 1248.43 seconds
Started Aug 02 08:22:54 PM PDT 24
Finished Aug 02 08:43:43 PM PDT 24
Peak memory 611536 kb
Host smart-a8b710a4-0e97-43c7-a68c-f46fb50dd5a4
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920426304 -assert nop
ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1920426304
Directory /workspace/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1667487648
Short name T422
Test name
Test status
Simulation time 7716487704 ps
CPU time 530.35 seconds
Started Aug 02 08:23:08 PM PDT 24
Finished Aug 02 08:31:59 PM PDT 24
Peak memory 609660 kb
Host smart-94df798c-3103-4f0c-b7d6-af9bf53c53f8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667487648 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1667487648
Directory /workspace/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.3771222130
Short name T1142
Test name
Test status
Simulation time 5694836419 ps
CPU time 647.98 seconds
Started Aug 02 08:18:03 PM PDT 24
Finished Aug 02 08:28:51 PM PDT 24
Peak memory 610808 kb
Host smart-b22a96f9-96c6-4739-8050-251fec038aa7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771222130 -assert nopostpr
oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_por_reset.3771222130
Directory /workspace/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.370235637
Short name T1273
Test name
Test status
Simulation time 19024660089 ps
CPU time 2294.6 seconds
Started Aug 02 08:18:15 PM PDT 24
Finished Aug 02 08:56:31 PM PDT 24
Peak memory 611572 kb
Host smart-8266798f-ce54-4920-9816-4875389e6f66
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=370235637 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.370235637
Directory /workspace/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2001590745
Short name T20
Test name
Test status
Simulation time 22534616760 ps
CPU time 1504.49 seconds
Started Aug 02 08:21:41 PM PDT 24
Finished Aug 02 08:46:46 PM PDT 24
Peak memory 611076 kb
Host smart-a0180a7f-330c-426b-9d9a-76d9c4352cdc
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2001590745 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2001590745
Directory /workspace/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.763053613
Short name T1018
Test name
Test status
Simulation time 46497213381 ps
CPU time 3760.32 seconds
Started Aug 02 08:21:47 PM PDT 24
Finished Aug 02 09:24:28 PM PDT 24
Peak memory 611812 kb
Host smart-3ae9a1a0-1d7c-4846-96d4-9e1012ac67fc
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power
_glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763053613 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glitc
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sl
eep_power_glitch_reset.763053613
Directory /workspace/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.1428111749
Short name T720
Test name
Test status
Simulation time 2725768284 ps
CPU time 226.36 seconds
Started Aug 02 08:18:23 PM PDT 24
Finished Aug 02 08:22:10 PM PDT 24
Peak memory 609696 kb
Host smart-4bec72a9-bbec-4d21-a1c2-6200b78bef2b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428111749 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_disabled.1428111749
Directory /workspace/0.chip_sw_pwrmgr_sleep_disabled/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.775802591
Short name T1267
Test name
Test status
Simulation time 6822694290 ps
CPU time 477.57 seconds
Started Aug 02 08:19:35 PM PDT 24
Finished Aug 02 08:27:33 PM PDT 24
Peak memory 616828 kb
Host smart-28127736-f85b-4d5e-a1dc-598b01fcf0e9
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=775802591 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_power_glitch_reset.775802591
Directory /workspace/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1648901956
Short name T1029
Test name
Test status
Simulation time 5765533278 ps
CPU time 622.24 seconds
Started Aug 02 08:20:43 PM PDT 24
Finished Aug 02 08:31:05 PM PDT 24
Peak memory 610904 kb
Host smart-ea384efe-6e8c-488b-bf87-849665261de6
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1648901956 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.1648901956
Directory /workspace/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.733594764
Short name T1342
Test name
Test status
Simulation time 5142354140 ps
CPU time 377.28 seconds
Started Aug 02 08:22:26 PM PDT 24
Finished Aug 02 08:28:44 PM PDT 24
Peak memory 610508 kb
Host smart-3a4ef212-4f1d-4c5a-8ca0-40d4dfbe38b0
User root
Command /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733594764 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.733594764
Directory /workspace/0.chip_sw_pwrmgr_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3053142619
Short name T941
Test name
Test status
Simulation time 8572173762 ps
CPU time 1532.92 seconds
Started Aug 02 08:18:29 PM PDT 24
Finished Aug 02 08:44:02 PM PDT 24
Peak memory 610916 kb
Host smart-49da75d8-1588-4a3c-b85e-f1a6c1fc57ef
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053142619 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.3053142619
Directory /workspace/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.4216091807
Short name T404
Test name
Test status
Simulation time 4502802920 ps
CPU time 541.67 seconds
Started Aug 02 08:19:34 PM PDT 24
Finished Aug 02 08:28:36 PM PDT 24
Peak memory 610596 kb
Host smart-c6975ba1-7ccc-4844-9792-c109e819b810
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216091807 -assert no
postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.4216091807
Directory /workspace/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.275796418
Short name T1021
Test name
Test status
Simulation time 5395806140 ps
CPU time 342.64 seconds
Started Aug 02 08:24:55 PM PDT 24
Finished Aug 02 08:30:38 PM PDT 24
Peak memory 610468 kb
Host smart-ae06b1a7-27ad-45dc-9ee9-0052183191a5
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275796418 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.chip_sw_pwrmgr_usbdev_smoketest.275796418
Directory /workspace/0.chip_sw_pwrmgr_usbdev_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.663705444
Short name T330
Test name
Test status
Simulation time 5681741720 ps
CPU time 675.84 seconds
Started Aug 02 08:18:32 PM PDT 24
Finished Aug 02 08:29:48 PM PDT 24
Peak memory 610348 kb
Host smart-c88ac8e9-6a36-4fe2-b372-ea872f91a571
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663
705444 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.663705444
Directory /workspace/0.chip_sw_pwrmgr_wdog_reset/latest

Test location /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.1612592654
Short name T1397
Test name
Test status
Simulation time 8892430012 ps
CPU time 468.87 seconds
Started Aug 02 08:20:29 PM PDT 24
Finished Aug 02 08:28:18 PM PDT 24
Peak memory 624824 kb
Host smart-60ac4756-ad5e-4ea4-8d5f-74892ece28e2
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612592654 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.1612592654
Directory /workspace/0.chip_sw_rom_ctrl_integrity_check/latest

Test location /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.2674344622
Short name T249
Test name
Test status
Simulation time 6728913496 ps
CPU time 491.96 seconds
Started Aug 02 08:19:12 PM PDT 24
Finished Aug 02 08:27:25 PM PDT 24
Peak memory 610528 kb
Host smart-33b5ab11-08c0-457b-abaa-500d9d29bd08
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674344622 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.chip_sw_rstmgr_cpu_info.2674344622
Directory /workspace/0.chip_sw_rstmgr_cpu_info/latest

Test location /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.1738328896
Short name T1106
Test name
Test status
Simulation time 5643223592 ps
CPU time 511.78 seconds
Started Aug 02 08:20:53 PM PDT 24
Finished Aug 02 08:29:25 PM PDT 24
Peak memory 641844 kb
Host smart-09343004-419d-4d57-8dcd-23ba3fceae33
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1738328896 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.1738328896
Directory /workspace/0.chip_sw_rstmgr_rst_cnsty_escalation/latest

Test location /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.2475223190
Short name T981
Test name
Test status
Simulation time 3227998916 ps
CPU time 202.04 seconds
Started Aug 02 08:24:24 PM PDT 24
Finished Aug 02 08:27:46 PM PDT 24
Peak memory 609636 kb
Host smart-53e97dba-97d2-4df6-b05b-14394b956167
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475223190 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.chip_sw_rstmgr_smoketest.2475223190
Directory /workspace/0.chip_sw_rstmgr_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.1766902491
Short name T1005
Test name
Test status
Simulation time 4816314200 ps
CPU time 401.22 seconds
Started Aug 02 08:22:43 PM PDT 24
Finished Aug 02 08:29:24 PM PDT 24
Peak memory 610364 kb
Host smart-2fbe8351-943e-45e8-91e2-f2ab1c83d1dd
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766902491 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.chip_sw_rstmgr_sw_req.1766902491
Directory /workspace/0.chip_sw_rstmgr_sw_req/latest

Test location /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.3049817790
Short name T1213
Test name
Test status
Simulation time 2475267792 ps
CPU time 264.6 seconds
Started Aug 02 08:20:14 PM PDT 24
Finished Aug 02 08:24:40 PM PDT 24
Peak memory 609852 kb
Host smart-5df533ad-5768-499a-9a67-db34c1a74d39
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049817790 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.chip_sw_rstmgr_sw_rst.3049817790
Directory /workspace/0.chip_sw_rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.1938575897
Short name T310
Test name
Test status
Simulation time 2803172322 ps
CPU time 238.48 seconds
Started Aug 02 08:20:52 PM PDT 24
Finished Aug 02 08:24:51 PM PDT 24
Peak memory 609716 kb
Host smart-f7b3eb9f-3a5e-44d6-a3c2-1cc627b15df2
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938575897 -assert nopostp
roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.1938575897
Directory /workspace/0.chip_sw_rv_core_ibex_icache_invalidate/latest

Test location /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.1958243702
Short name T993
Test name
Test status
Simulation time 5760508000 ps
CPU time 997.11 seconds
Started Aug 02 08:18:32 PM PDT 24
Finished Aug 02 08:35:09 PM PDT 24
Peak memory 610132 kb
Host smart-e07aba72-50d9-4872-a2c6-f556c98849bd
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1958243702 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.1958243702
Directory /workspace/0.chip_sw_rv_core_ibex_rnd/latest

Test location /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2137943808
Short name T711
Test name
Test status
Simulation time 6080705000 ps
CPU time 609.76 seconds
Started Aug 02 08:19:28 PM PDT 24
Finished Aug 02 08:29:39 PM PDT 24
Peak memory 624396 kb
Host smart-757258cc-6f30-4dc4-971e-b9193a14e248
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137943808 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.2137943808
Directory /workspace/0.chip_sw_rv_dm_access_after_escalation_reset/latest

Test location /workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.4260533584
Short name T1115
Test name
Test status
Simulation time 5647280370 ps
CPU time 381.45 seconds
Started Aug 02 08:24:19 PM PDT 24
Finished Aug 02 08:30:41 PM PDT 24
Peak memory 620272 kb
Host smart-cbc89355-0dd0-40d5-8ecf-3f520a57ae7c
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260533584 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_wakeup.4260533584
Directory /workspace/0.chip_sw_rv_dm_access_after_wakeup/latest

Test location /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.3381190483
Short name T100
Test name
Test status
Simulation time 2221515660 ps
CPU time 240.99 seconds
Started Aug 02 08:21:48 PM PDT 24
Finished Aug 02 08:25:49 PM PDT 24
Peak memory 608440 kb
Host smart-7812e2d2-b9cb-4584-9924-401262310ff0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381190483 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.chip_sw_rv_plic_smoketest.3381190483
Directory /workspace/0.chip_sw_rv_plic_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_rv_timer_irq.226202024
Short name T260
Test name
Test status
Simulation time 3536888860 ps
CPU time 297.45 seconds
Started Aug 02 08:17:37 PM PDT 24
Finished Aug 02 08:22:35 PM PDT 24
Peak memory 608396 kb
Host smart-773eb855-dec2-4650-893e-3d899508c569
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226202024 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.chip_sw_rv_timer_irq.226202024
Directory /workspace/0.chip_sw_rv_timer_irq/latest

Test location /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.3510431177
Short name T1282
Test name
Test status
Simulation time 3095245776 ps
CPU time 276.55 seconds
Started Aug 02 08:25:39 PM PDT 24
Finished Aug 02 08:30:16 PM PDT 24
Peak memory 609676 kb
Host smart-dbbdab7b-3551-4072-aa8f-d064fcdf97d3
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510431177 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.chip_sw_rv_timer_smoketest.3510431177
Directory /workspace/0.chip_sw_rv_timer_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.2959244114
Short name T137
Test name
Test status
Simulation time 3440365818 ps
CPU time 331.88 seconds
Started Aug 02 08:20:48 PM PDT 24
Finished Aug 02 08:26:20 PM PDT 24
Peak memory 610888 kb
Host smart-7b8dd299-28de-4305-a809-0b701046ecde
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959244
114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.2959244114
Directory /workspace/0.chip_sw_sensor_ctrl_status/latest

Test location /workspace/coverage/default/0.chip_sw_sleep_pin_retention.532698168
Short name T55
Test name
Test status
Simulation time 3336756300 ps
CPU time 203.3 seconds
Started Aug 02 08:21:13 PM PDT 24
Finished Aug 02 08:24:36 PM PDT 24
Peak memory 610032 kb
Host smart-ec7ae19b-0a49-4716-b6dc-195ddd140496
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532698168 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_retention.532698168
Directory /workspace/0.chip_sw_sleep_pin_retention/latest

Test location /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.4240007928
Short name T1390
Test name
Test status
Simulation time 8626540196 ps
CPU time 1773.88 seconds
Started Aug 02 08:19:40 PM PDT 24
Finished Aug 02 08:49:15 PM PDT 24
Peak memory 610776 kb
Host smart-4ad5a232-3bb0-4427-a9e4-21bdec44fd81
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240007928 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.chip_sw_sleep_pwm_pulses.4240007928
Directory /workspace/0.chip_sw_sleep_pwm_pulses/latest

Test location /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.2949503944
Short name T1140
Test name
Test status
Simulation time 9199922316 ps
CPU time 751 seconds
Started Aug 02 08:21:12 PM PDT 24
Finished Aug 02 08:33:43 PM PDT 24
Peak memory 610664 kb
Host smart-d56b73dc-39b4-478a-97fc-4fea6095f1f0
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949503944 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S
EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sl
eep_sram_ret_contents_no_scramble.2949503944
Directory /workspace/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest

Test location /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1700617716
Short name T178
Test name
Test status
Simulation time 7917498316 ps
CPU time 823.79 seconds
Started Aug 02 08:21:05 PM PDT 24
Finished Aug 02 08:34:49 PM PDT 24
Peak memory 610720 kb
Host smart-6bef85eb-f2f5-4179-81c2-8cdf2c49eded
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700617716 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep
_sram_ret_contents_scramble.1700617716
Directory /workspace/0.chip_sw_sleep_sram_ret_contents_scramble/latest

Test location /workspace/coverage/default/0.chip_sw_spi_device_pass_through.1937936818
Short name T202
Test name
Test status
Simulation time 5824640569 ps
CPU time 622.96 seconds
Started Aug 02 08:21:54 PM PDT 24
Finished Aug 02 08:32:17 PM PDT 24
Peak memory 624812 kb
Host smart-dea9975c-2e27-46ca-a0a2-01268e9de18e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937936818 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through.1937936818
Directory /workspace/0.chip_sw_spi_device_pass_through/latest

Test location /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.146524666
Short name T13
Test name
Test status
Simulation time 4884434094 ps
CPU time 650.44 seconds
Started Aug 02 08:20:27 PM PDT 24
Finished Aug 02 08:31:18 PM PDT 24
Peak memory 624836 kb
Host smart-af6389f1-0c2c-40f3-b7b0-9579fdeab775
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146524666 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.146524666
Directory /workspace/0.chip_sw_spi_device_pass_through_collision/latest

Test location /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2938402939
Short name T246
Test name
Test status
Simulation time 4483529766 ps
CPU time 467.65 seconds
Started Aug 02 08:20:07 PM PDT 24
Finished Aug 02 08:27:56 PM PDT 24
Peak memory 611192 kb
Host smart-12899262-c48a-4918-8a86-af31eb607dc8
User root
Command /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s
w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938402939 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi
p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2938402939
Directory /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4137940810
Short name T677
Test name
Test status
Simulation time 5563855980 ps
CPU time 713.24 seconds
Started Aug 02 08:24:58 PM PDT 24
Finished Aug 02 08:36:53 PM PDT 24
Peak memory 611160 kb
Host smart-3e853ee8-50af-42a4-8486-6c7d8f5617d9
User root
Command /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk
_70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137940810 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4137940810
Directory /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.3082208571
Short name T431
Test name
Test status
Simulation time 2807142572 ps
CPU time 158.22 seconds
Started Aug 02 08:23:00 PM PDT 24
Finished Aug 02 08:25:39 PM PDT 24
Peak memory 609784 kb
Host smart-c1033031-58a0-4948-9d21-f3bd506e3beb
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082208571 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.chip_sw_sram_ctrl_smoketest.3082208571
Directory /workspace/0.chip_sw_sram_ctrl_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.2769273502
Short name T22
Test name
Test status
Simulation time 20357516612 ps
CPU time 3606.15 seconds
Started Aug 02 08:21:50 PM PDT 24
Finished Aug 02 09:21:57 PM PDT 24
Peak memory 610392 kb
Host smart-477813e3-33ce-4197-a0f7-087ed97b1090
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769273502 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.2769273502
Directory /workspace/0.chip_sw_sysrst_ctrl_ec_rst_l/latest

Test location /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.2159153481
Short name T1370
Test name
Test status
Simulation time 5012978357 ps
CPU time 545.74 seconds
Started Aug 02 08:18:21 PM PDT 24
Finished Aug 02 08:27:28 PM PDT 24
Peak memory 613480 kb
Host smart-ccac33fd-8172-4c6a-baf7-8d3fb61b3776
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159153481 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_in_irq.2159153481
Directory /workspace/0.chip_sw_sysrst_ctrl_in_irq/latest

Test location /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.954387310
Short name T206
Test name
Test status
Simulation time 2785901344 ps
CPU time 267.07 seconds
Started Aug 02 08:19:43 PM PDT 24
Finished Aug 02 08:24:11 PM PDT 24
Peak memory 613044 kb
Host smart-216e2afa-b182-48cf-a20f-61b279f04bda
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954387310 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_inputs.954387310
Directory /workspace/0.chip_sw_sysrst_ctrl_inputs/latest

Test location /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2743663050
Short name T41
Test name
Test status
Simulation time 5292852092 ps
CPU time 394.12 seconds
Started Aug 02 08:19:33 PM PDT 24
Finished Aug 02 08:26:08 PM PDT 24
Peak memory 609552 kb
Host smart-f897655d-8807-4df1-8e0d-25a4bf9b179b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743663050 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2743663050
Directory /workspace/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest

Test location /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.364094173
Short name T345
Test name
Test status
Simulation time 3781973242 ps
CPU time 462.06 seconds
Started Aug 02 08:16:54 PM PDT 24
Finished Aug 02 08:24:36 PM PDT 24
Peak memory 618904 kb
Host smart-03111315-f925-42b2-aa38-ee7ccdd5ca18
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=364094173 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.364094173
Directory /workspace/0.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/0.chip_sw_uart_smoketest.1246466585
Short name T1009
Test name
Test status
Simulation time 3409109914 ps
CPU time 283.18 seconds
Started Aug 02 08:26:13 PM PDT 24
Finished Aug 02 08:30:56 PM PDT 24
Peak memory 615068 kb
Host smart-a32f83e9-845b-48cd-9bf1-a14c7bc4c81d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246466585 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.chip_sw_uart_smoketest.1246466585
Directory /workspace/0.chip_sw_uart_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1604493097
Short name T217
Test name
Test status
Simulation time 3991406659 ps
CPU time 485.33 seconds
Started Aug 02 08:17:55 PM PDT 24
Finished Aug 02 08:26:02 PM PDT 24
Peak memory 624636 kb
Host smart-a0630782-ae77-43df-9ecb-916477b11f6b
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604493097 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx
_alt_clk_freq.1604493097
Directory /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1582153908
Short name T15
Test name
Test status
Simulation time 4262741958 ps
CPU time 408.37 seconds
Started Aug 02 08:17:20 PM PDT 24
Finished Aug 02 08:24:09 PM PDT 24
Peak memory 619772 kb
Host smart-3aa7c1c9-896b-4be9-96cd-0819c87901de
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582153908 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx
_alt_clk_freq_low_speed.1582153908
Directory /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1791358366
Short name T1203
Test name
Test status
Simulation time 77688805940 ps
CPU time 13308 seconds
Started Aug 02 08:17:16 PM PDT 24
Finished Aug 02 11:59:06 PM PDT 24
Peak memory 634128 kb
Host smart-eaed4135-5356-4af3-9533-ef63dd65f100
User root
Command /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1791358366 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_bootstrap.1791358366
Directory /workspace/0.chip_sw_uart_tx_rx_bootstrap/latest

Test location /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.314006921
Short name T1361
Test name
Test status
Simulation time 4394231390 ps
CPU time 633.03 seconds
Started Aug 02 08:19:30 PM PDT 24
Finished Aug 02 08:30:05 PM PDT 24
Peak memory 623936 kb
Host smart-1686a4fa-d3b1-4dab-9b0d-5a715a2f28a1
User root
Command /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314006921 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.314006921
Directory /workspace/0.chip_sw_uart_tx_rx_idx1/latest

Test location /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.3942232935
Short name T971
Test name
Test status
Simulation time 4180326744 ps
CPU time 529.48 seconds
Started Aug 02 08:16:48 PM PDT 24
Finished Aug 02 08:25:38 PM PDT 24
Peak memory 623648 kb
Host smart-1dc572da-6f4f-430a-a5d6-c48c95b659f2
User root
Command /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942232935 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.3942232935
Directory /workspace/0.chip_sw_uart_tx_rx_idx3/latest

Test location /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.277457520
Short name T1128
Test name
Test status
Simulation time 3488420871 ps
CPU time 311.44 seconds
Started Aug 02 08:24:12 PM PDT 24
Finished Aug 02 08:29:23 PM PDT 24
Peak memory 610096 kb
Host smart-fc1ce6cc-8038-476a-b7a7-de0549c11c6d
User root
Command /workspace/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw_images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277457520 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.277457520
Directory /workspace/0.chip_sw_usb_ast_clk_calib/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_dpi.1217015079
Short name T26
Test name
Test status
Simulation time 11406226046 ps
CPU time 3111.61 seconds
Started Aug 02 08:20:10 PM PDT 24
Finished Aug 02 09:12:03 PM PDT 24
Peak memory 610120 kb
Host smart-7abdce0c-8110-4c25-a919-1c3e3e29a874
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1217015079 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.1217015079
Directory /workspace/0.chip_sw_usbdev_dpi/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_pincfg.2858824783
Short name T76
Test name
Test status
Simulation time 31944322876 ps
CPU time 7615.63 seconds
Started Aug 02 08:18:47 PM PDT 24
Finished Aug 02 10:25:44 PM PDT 24
Peak memory 609268 kb
Host smart-defb5df0-2bbd-48ab-a7e1-f05197562020
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_r
ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim
.tcl +ntb_random_seed=2858824783 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.2858824783
Directory /workspace/0.chip_sw_usbdev_pincfg/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_pullup.379913651
Short name T19
Test name
Test status
Simulation time 3075971092 ps
CPU time 274.74 seconds
Started Aug 02 08:17:33 PM PDT 24
Finished Aug 02 08:22:08 PM PDT 24
Peak memory 609776 kb
Host smart-c1e69784-f592-42e9-8a69-1d086925ee28
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379913651
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.379913651
Directory /workspace/0.chip_sw_usbdev_pullup/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_setuprx.1273956985
Short name T24
Test name
Test status
Simulation time 3484721710 ps
CPU time 584.86 seconds
Started Aug 02 08:18:31 PM PDT 24
Finished Aug 02 08:28:17 PM PDT 24
Peak memory 609708 kb
Host smart-a8616b45-1ce0-4a5c-a00f-5282c830ae43
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127395698
5 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.1273956985
Directory /workspace/0.chip_sw_usbdev_setuprx/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_stream.1650975098
Short name T1187
Test name
Test status
Simulation time 19404454674 ps
CPU time 4684.91 seconds
Started Aug 02 08:18:41 PM PDT 24
Finished Aug 02 09:36:47 PM PDT 24
Peak memory 610240 kb
Host smart-ef0ef635-a5f9-4082-9709-457f68e77510
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_ru
les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1650975098 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.1650975098
Directory /workspace/0.chip_sw_usbdev_stream/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_vbus.1988952039
Short name T1026
Test name
Test status
Simulation time 3021399428 ps
CPU time 227.94 seconds
Started Aug 02 08:16:51 PM PDT 24
Finished Aug 02 08:20:39 PM PDT 24
Peak memory 608728 kb
Host smart-2cad977e-55d7-4097-80ed-8ab80213841d
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988952039 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.1988952039
Directory /workspace/0.chip_sw_usbdev_vbus/latest

Test location /workspace/coverage/default/0.chip_tap_straps_prod.2582690839
Short name T74
Test name
Test status
Simulation time 13814636414 ps
CPU time 1605.86 seconds
Started Aug 02 08:18:55 PM PDT 24
Finished Aug 02 08:45:42 PM PDT 24
Peak memory 624568 kb
Host smart-3d0d4085-d9e9-44b3-a6ad-dc951ca14bc9
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom
:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2582690839 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.2582690839
Directory /workspace/0.chip_tap_straps_prod/latest

Test location /workspace/coverage/default/0.chip_tap_straps_testunlock0.214133328
Short name T1165
Test name
Test status
Simulation time 7344162447 ps
CPU time 716.1 seconds
Started Aug 02 08:21:20 PM PDT 24
Finished Aug 02 08:33:17 PM PDT 24
Peak memory 632808 kb
Host smart-1b254d26-5c3c-4f58-b1fa-092045c19b29
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te
st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214133328 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_testunlock0.214133328
Directory /workspace/0.chip_tap_straps_testunlock0/latest

Test location /workspace/coverage/default/0.rom_e2e_asm_init_dev.352270429
Short name T1311
Test name
Test status
Simulation time 15369983400 ps
CPU time 3812.21 seconds
Started Aug 02 08:25:58 PM PDT 24
Finished Aug 02 09:29:30 PM PDT 24
Peak memory 610004 kb
Host smart-8b1b3db6-110f-478e-b537-e67f423a182c
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352270429 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE
Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.rom_e2e_asm_init_dev.352270429
Directory /workspace/0.rom_e2e_asm_init_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_asm_init_prod.296358949
Short name T1194
Test name
Test status
Simulation time 15662048557 ps
CPU time 3504.27 seconds
Started Aug 02 08:28:50 PM PDT 24
Finished Aug 02 09:27:15 PM PDT 24
Peak memory 610288 kb
Host smart-e6c10e2a-3278-4631-bd42-fc2b33ee1e47
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296358949 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S
EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rom_e2e_asm_init_prod.296358949
Directory /workspace/0.rom_e2e_asm_init_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.3053152478
Short name T1281
Test name
Test status
Simulation time 15736456332 ps
CPU time 4161.05 seconds
Started Aug 02 08:26:16 PM PDT 24
Finished Aug 02 09:35:38 PM PDT 24
Peak memory 610308 kb
Host smart-dca7b180-4312-4e2c-8779-a6db43f6d189
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053152478 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T
EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.rom_e2e_asm_init_prod_end.3053152478
Directory /workspace/0.rom_e2e_asm_init_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_asm_init_rma.2421169737
Short name T1078
Test name
Test status
Simulation time 14960481824 ps
CPU time 4059.03 seconds
Started Aug 02 08:25:53 PM PDT 24
Finished Aug 02 09:33:33 PM PDT 24
Peak memory 610264 kb
Host smart-903d87e4-5b6f-4286-a882-8f04bf7c41ac
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421169737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S
EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rom_e2e_asm_init_rma.2421169737
Directory /workspace/0.rom_e2e_asm_init_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.1879900384
Short name T1008
Test name
Test status
Simulation time 11467620846 ps
CPU time 3142.18 seconds
Started Aug 02 08:25:01 PM PDT 24
Finished Aug 02 09:17:24 PM PDT 24
Peak memory 610588 kb
Host smart-4fb4e259-913d-4d14-868d-a3c0424b9a39
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879900384 -assert nopostproc +UVM_TESTNAME=chip_base_te
st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.rom_e2e_asm_init_test_unlocked0.1879900384
Directory /workspace/0.rom_e2e_asm_init_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1537044553
Short name T400
Test name
Test status
Simulation time 24123843710 ps
CPU time 5708.68 seconds
Started Aug 02 08:27:58 PM PDT 24
Finished Aug 02 10:03:07 PM PDT 24
Peak memory 610068 kb
Host smart-6ec9c479-6096-48ce-a675-7fefaefbed33
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1537044553 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1537044553
Directory /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.161557880
Short name T425
Test name
Test status
Simulation time 24646143008 ps
CPU time 6354.33 seconds
Started Aug 02 08:26:36 PM PDT 24
Finished Aug 02 10:12:32 PM PDT 24
Peak memory 610076 kb
Host smart-6d84a05e-d146-41e9-b501-83227b1a025a
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=161557880 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.161557880
Directory /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.4135784027
Short name T1062
Test name
Test status
Simulation time 23468722420 ps
CPU time 5722.06 seconds
Started Aug 02 08:25:47 PM PDT 24
Finished Aug 02 10:01:09 PM PDT 24
Peak memory 610140 kb
Host smart-ebcda51f-50cc-4daa-94c8-2be90daf1d82
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=4135784027 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.4135784027
Directory /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.327782517
Short name T399
Test name
Test status
Simulation time 18312724086 ps
CPU time 4376.57 seconds
Started Aug 02 08:26:28 PM PDT 24
Finished Aug 02 09:39:25 PM PDT 24
Peak memory 610112 kb
Host smart-f2404203-9d6f-47c5-baaa-94c78b2fe17f
User root
Command /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,
mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=327782517 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.327782517
Directory /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3426042090
Short name T427
Test name
Test status
Simulation time 15349589446 ps
CPU time 3939.16 seconds
Started Aug 02 08:30:20 PM PDT 24
Finished Aug 02 09:35:59 PM PDT 24
Peak memory 610132 kb
Host smart-9f3aa652-51b6-41ef-8f66-57d268417e01
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_dev:4,mask_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3426042090 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3426042090
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3993223268
Short name T1180
Test name
Test status
Simulation time 15529850176 ps
CPU time 4530.72 seconds
Started Aug 02 08:27:50 PM PDT 24
Finished Aug 02 09:43:21 PM PDT 24
Peak memory 610164 kb
Host smart-e4fd894c-bf34-4228-8e60-0088b42535dc
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod:4,mask_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3993223268 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3993223268
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.2621181588
Short name T1373
Test name
Test status
Simulation time 15234610440 ps
CPU time 3966.9 seconds
Started Aug 02 08:27:32 PM PDT 24
Finished Aug 02 09:33:40 PM PDT 24
Peak memory 610140 kb
Host smart-22a2cc66-2430-489f-939a-8d67b764a98f
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,mask_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2621181588 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.2621181588
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.293017325
Short name T1121
Test name
Test status
Simulation time 14958305370 ps
CPU time 4131.94 seconds
Started Aug 02 08:26:37 PM PDT 24
Finished Aug 02 09:35:29 PM PDT 24
Peak memory 610152 kb
Host smart-255d3597-c857-4a3f-b423-de4956c3cf29
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_rma:4,mask_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=293017325 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.293017325
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2627235677
Short name T1072
Test name
Test status
Simulation time 15545697600 ps
CPU time 3634.65 seconds
Started Aug 02 08:24:57 PM PDT 24
Finished Aug 02 09:25:33 PM PDT 24
Peak memory 610268 kb
Host smart-e63ddd40-bedd-4d06-803a-382b3bd2b5a2
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627235677
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2627235677
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2982726338
Short name T1088
Test name
Test status
Simulation time 16176104410 ps
CPU time 4358.86 seconds
Started Aug 02 08:24:51 PM PDT 24
Finished Aug 02 09:37:31 PM PDT 24
Peak memory 609476 kb
Host smart-f2bb95d5-8c4c-467d-ab16-a4f103280e96
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982726338
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2982726338
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3409868438
Short name T1077
Test name
Test status
Simulation time 15889473480 ps
CPU time 4911.04 seconds
Started Aug 02 08:26:42 PM PDT 24
Finished Aug 02 09:48:34 PM PDT 24
Peak memory 610204 kb
Host smart-0ee4ba4e-803f-42b9-8757-4f750f39f5e8
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340986
8438 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3409868438
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.4200166763
Short name T1120
Test name
Test status
Simulation time 15598834732 ps
CPU time 3842.56 seconds
Started Aug 02 08:30:16 PM PDT 24
Finished Aug 02 09:34:19 PM PDT 24
Peak memory 610236 kb
Host smart-cdd5771f-baba-4300-9cd8-42d0f37517e7
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200166763
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.4200166763
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.3863349981
Short name T1327
Test name
Test status
Simulation time 10879013478 ps
CPU time 3077.64 seconds
Started Aug 02 08:25:52 PM PDT 24
Finished Aug 02 09:17:10 PM PDT 24
Peak memory 610288 kb
Host smart-5c86071a-2dd4-4b34-9b3e-5741833b0869
User root
Command /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3863349981 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.3863349981
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_jtag_debug_dev.1980217019
Short name T401
Test name
Test status
Simulation time 10659868507 ps
CPU time 2117.88 seconds
Started Aug 02 08:25:39 PM PDT 24
Finished Aug 02 09:00:58 PM PDT 24
Peak memory 624388 kb
Host smart-3e70e571-3c62-42e9-9a74-477a8067ab28
User root
Command /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_disabled:4,mask_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19802
17019 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_dev.1980217019
Directory /workspace/0.rom_e2e_jtag_debug_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_jtag_debug_rma.3927129276
Short name T80
Test name
Test status
Simulation time 12106629589 ps
CPU time 2347.65 seconds
Started Aug 02 08:23:57 PM PDT 24
Finished Aug 02 09:03:06 PM PDT 24
Peak memory 624644 kb
Host smart-c75e2573-bef2-410c-90f7-b66b6baf4f8e
User root
Command /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_disabled:4,mask_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39271
29276 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_rma.3927129276
Directory /workspace/0.rom_e2e_jtag_debug_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.1089376461
Short name T1179
Test name
Test status
Simulation time 11339401014 ps
CPU time 2317.55 seconds
Started Aug 02 08:19:55 PM PDT 24
Finished Aug 02 08:58:33 PM PDT 24
Peak memory 624372 kb
Host smart-10702fd0-58cd-42f4-913c-82882ec5ce43
User root
Command /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlocked0_exec_disabled:4,mask_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=1089376461 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_test_unlocked0.1089376461
Directory /workspace/0.rom_e2e_jtag_debug_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.2912124293
Short name T439
Test name
Test status
Simulation time 32452314955 ps
CPU time 2573.86 seconds
Started Aug 02 08:22:59 PM PDT 24
Finished Aug 02 09:05:54 PM PDT 24
Peak memory 621236 kb
Host smart-68e2481e-4e3f-414c-b312-de7be2b44fb8
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_di
sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2912124293 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_dev.2912124293
Directory /workspace/0.rom_e2e_jtag_inject_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.2062696566
Short name T437
Test name
Test status
Simulation time 34690193633 ps
CPU time 2729.28 seconds
Started Aug 02 08:22:06 PM PDT 24
Finished Aug 02 09:07:36 PM PDT 24
Peak memory 623928 kb
Host smart-d1105e35-f906-4cec-b24f-8fe118250567
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_di
sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2062696566 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_rma.2062696566
Directory /workspace/0.rom_e2e_jtag_inject_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.309908370
Short name T438
Test name
Test status
Simulation time 25668888612 ps
CPU time 1953.87 seconds
Started Aug 02 08:23:57 PM PDT 24
Finished Aug 02 08:56:32 PM PDT 24
Peak memory 623912 kb
Host smart-1510b7dc-8af2-48bd-b101-022bb9ef0da3
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlock
ed0_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309908370 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_i
nject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_
test_unlocked0.309908370
Directory /workspace/0.rom_e2e_jtag_inject_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.2989182933
Short name T1066
Test name
Test status
Simulation time 15510626110 ps
CPU time 3496.09 seconds
Started Aug 02 08:28:39 PM PDT 24
Finished Aug 02 09:26:55 PM PDT 24
Peak memory 610056 kb
Host smart-532ee376-a3ef-4827-b600-087b71e794db
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid
_meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989182933 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip
_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_in
it_rom_ext_invalid_meas.2989182933
Directory /workspace/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest

Test location /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.3186585753
Short name T1227
Test name
Test status
Simulation time 14592230680 ps
CPU time 3550.07 seconds
Started Aug 02 08:29:36 PM PDT 24
Finished Aug 02 09:28:48 PM PDT 24
Peak memory 609180 kb
Host smart-cf3c8d6b-abcf-4c3f-8428-0e6dc508971f
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1:
new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186585753 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_meas.3186585753
Directory /workspace/0.rom_e2e_keymgr_init_rom_ext_meas/latest

Test location /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.4028686427
Short name T1305
Test name
Test status
Simulation time 14849561048 ps
CPU time 5268.82 seconds
Started Aug 02 08:22:32 PM PDT 24
Finished Aug 02 09:50:22 PM PDT 24
Peak memory 610180 kb
Host smart-87f58005-1887-4bf1-a034-2272041ef7de
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas
:1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028686427 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext
_no_meas.4028686427
Directory /workspace/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest

Test location /workspace/coverage/default/0.rom_e2e_self_hash.3253527366
Short name T423
Test name
Test status
Simulation time 25284241640 ps
CPU time 5421.78 seconds
Started Aug 02 08:29:44 PM PDT 24
Finished Aug 02 10:00:07 PM PDT 24
Peak memory 609896 kb
Host smart-25f47157-248d-4c5a-bc54-e2c6aa5e2017
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r
ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253527366 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_self_hash.3253527366
Directory /workspace/0.rom_e2e_self_hash/latest

Test location /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.480810429
Short name T1341
Test name
Test status
Simulation time 14822889100 ps
CPU time 3899.91 seconds
Started Aug 02 08:25:35 PM PDT 24
Finished Aug 02 09:30:36 PM PDT 24
Peak memory 611488 kb
Host smart-3af96016-3a77-48d4-84f3-a4153d1eecde
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne
w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480810429 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shut
down_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_s
hutdown_exception_c.480810429
Directory /workspace/0.rom_e2e_shutdown_exception_c/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.2577481073
Short name T1057
Test name
Test status
Simulation time 23623886400 ps
CPU time 7927.88 seconds
Started Aug 02 08:31:31 PM PDT 24
Finished Aug 02 10:43:39 PM PDT 24
Peak memory 611184 kb
Host smart-4cfd7dc9-0ab2-4237-8a96-62c13273b5d4
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_dev_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev
:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2577481073 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_b
ad_dev.2577481073
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.1923023316
Short name T279
Test name
Test status
Simulation time 23343815970 ps
CPU time 5911.24 seconds
Started Aug 02 08:32:18 PM PDT 24
Finished Aug 02 10:10:49 PM PDT 24
Peak memory 608416 kb
Host smart-e1690507-4656-4859-b101-c51b32d3454b
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p
rod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1923023316 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_
b_bad_prod.1923023316
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.3809164522
Short name T1058
Test name
Test status
Simulation time 24237151324 ps
CPU time 5179.81 seconds
Started Aug 02 08:28:12 PM PDT 24
Finished Aug 02 09:54:33 PM PDT 24
Peak memory 609324 kb
Host smart-b9e5b4c0-b578-452c-9b44-8af9f0168a91
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p
rod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool
s/sim.tcl +ntb_random_seed=3809164522 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_
bad_b_bad_prod_end.3809164522
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.3269248140
Short name T1289
Test name
Test status
Simulation time 23413703126 ps
CPU time 5699.31 seconds
Started Aug 02 08:26:34 PM PDT 24
Finished Aug 02 10:01:34 PM PDT 24
Peak memory 610236 kb
Host smart-c698a29b-ad62-4ac3-948c-2dd8ac7db917
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_r
ma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim
.tcl +ntb_random_seed=3269248140 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b
_bad_rma.3269248140
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.1503683942
Short name T1184
Test name
Test status
Simulation time 18112855300 ps
CPU time 4511.81 seconds
Started Aug 02 08:24:59 PM PDT 24
Finished Aug 02 09:40:12 PM PDT 24
Peak memory 609636 kb
Host smart-185af3ff-1221-4183-aed6-3e9a2423a2e0
User root
Command /workspace/default/simv +sw_test_timeout_ns=600_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_test_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_t
est_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1503683942 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b
_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_alw
ays_a_bad_b_bad_test_unlocked0.1503683942
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2549625090
Short name T1134
Test name
Test status
Simulation time 14392226976 ps
CPU time 4799.9 seconds
Started Aug 02 08:27:46 PM PDT 24
Finished Aug 02 09:47:46 PM PDT 24
Peak memory 609204 kb
Host smart-9a6e2551-3989-4e2e-a64a-b4226d7dd806
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549625090 -assert nopostproc +UVM_TESTNAME=chip_base_
test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2549625090
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.40436619
Short name T951
Test name
Test status
Simulation time 14112725401 ps
CPU time 3317.91 seconds
Started Aug 02 08:32:06 PM PDT 24
Finished Aug 02 09:27:24 PM PDT 24
Peak memory 610036 kb
Host smart-9663ca0f-9e6d-49aa-83ee-6d01abcc53fd
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40436619 -assert nopostproc +UVM_TESTNAME=chip_base_
test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.40436619
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3200407302
Short name T176
Test name
Test status
Simulation time 14746286470 ps
CPU time 3538.16 seconds
Started Aug 02 08:32:10 PM PDT 24
Finished Aug 02 09:31:08 PM PDT 24
Peak memory 610136 kb
Host smart-a59d445d-3d6d-40ae-b3ad-d53e71ce96a4
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200407302 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3200407302
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.3001882984
Short name T1225
Test name
Test status
Simulation time 13484909915 ps
CPU time 3925.08 seconds
Started Aug 02 08:30:04 PM PDT 24
Finished Aug 02 09:35:30 PM PDT 24
Peak memory 610456 kb
Host smart-f452f641-f523-4eff-a526-9ec773bd34a2
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001882984 -assert nopostproc +UVM_TESTNAME=chip_base
_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.3001882984
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1612693623
Short name T161
Test name
Test status
Simulation time 11328925845 ps
CPU time 2872.6 seconds
Started Aug 02 08:32:05 PM PDT 24
Finished Aug 02 09:19:58 PM PDT 24
Peak memory 609688 kb
Host smart-cef6c16b-ce60-496f-b83b-af264b3da8f5
User root
Command /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_test_key_0:new_rules,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612693623 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1612693623
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.2804170712
Short name T46
Test name
Test status
Simulation time 15007783616 ps
CPU time 3723.29 seconds
Started Aug 02 08:27:35 PM PDT 24
Finished Aug 02 09:29:39 PM PDT 24
Peak memory 609376 kb
Host smart-56224a7c-2d1e-44f7-8c4d-74c476a7226d
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804170712 -assert nopostproc +UVM_TESTNAME=chip_base_
test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.2804170712
Directory /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2812913937
Short name T1118
Test name
Test status
Simulation time 14864813420 ps
CPU time 3433.11 seconds
Started Aug 02 08:28:02 PM PDT 24
Finished Aug 02 09:25:16 PM PDT 24
Peak memory 610488 kb
Host smart-24ac4d63-8e90-4a0e-8fc9-04e12ade8f70
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812913937 -assert nopostproc +UVM_TESTNAME=chip_bas
e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2812913937
Directory /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1363141490
Short name T48
Test name
Test status
Simulation time 14706487570 ps
CPU time 4555.89 seconds
Started Aug 02 08:26:30 PM PDT 24
Finished Aug 02 09:42:27 PM PDT 24
Peak memory 610396 kb
Host smart-ab72897d-1352-4526-a27c-70a58a0db613
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363141490 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1363141490
Directory /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.3336279513
Short name T410
Test name
Test status
Simulation time 13992381667 ps
CPU time 3669.05 seconds
Started Aug 02 08:29:30 PM PDT 24
Finished Aug 02 09:30:40 PM PDT 24
Peak memory 609224 kb
Host smart-52b2977e-207d-4e71-b579-2ddb44bf24f8
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336279513 -assert nopostproc +UVM_TESTNAME=chip_base
_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.3336279513
Directory /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3378465888
Short name T1335
Test name
Test status
Simulation time 11426195540 ps
CPU time 2950.22 seconds
Started Aug 02 08:30:05 PM PDT 24
Finished Aug 02 09:19:15 PM PDT 24
Peak memory 610704 kb
Host smart-693fe114-f6f0-4b3f-80db-fc33c95f5b48
User root
Command /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378465888 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3378465888
Directory /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_smoke.368333806
Short name T1168
Test name
Test status
Simulation time 14121797078 ps
CPU time 4556.34 seconds
Started Aug 02 08:27:16 PM PDT 24
Finished Aug 02 09:43:13 PM PDT 24
Peak memory 610112 kb
Host smart-bfddcaa9-88fd-4e9f-a64b-8ff62f2ac5a0
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img
_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to
p/hw/dv/tools/sim.tcl +ntb_random_seed=368333806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.368333806
Directory /workspace/0.rom_e2e_smoke/latest

Test location /workspace/coverage/default/0.rom_e2e_static_critical.3231771422
Short name T924
Test name
Test status
Simulation time 17427178648 ps
CPU time 4752.6 seconds
Started Aug 02 08:31:22 PM PDT 24
Finished Aug 02 09:50:35 PM PDT 24
Peak memory 609904 kb
Host smart-d3b1e6ba-ac27-4bd1-a097-daae12988fd2
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul
es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231771422 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_static_critical.3231771422
Directory /workspace/0.rom_e2e_static_critical/latest

Test location /workspace/coverage/default/0.rom_keymgr_functest.1804427480
Short name T1263
Test name
Test status
Simulation time 3914691530 ps
CPU time 617.98 seconds
Started Aug 02 08:23:04 PM PDT 24
Finished Aug 02 08:33:22 PM PDT 24
Peak memory 610084 kb
Host smart-42aee45c-e76a-46cb-beb0-ee9f257cf844
User root
Command /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804427480 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_keymgr_functest.1804427480
Directory /workspace/0.rom_keymgr_functest/latest

Test location /workspace/coverage/default/0.rom_volatile_raw_unlock.3180596990
Short name T1398
Test name
Test status
Simulation time 2046206591 ps
CPU time 117.38 seconds
Started Aug 02 08:21:43 PM PDT 24
Finished Aug 02 08:23:42 PM PDT 24
Peak memory 616912 kb
Host smart-f0a11674-6e5a-4051-b869-59c5da51f779
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1
+sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180596990 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.3180596990
Directory /workspace/0.rom_volatile_raw_unlock/latest

Test location /workspace/coverage/default/1.chip_jtag_mem_access.3716114376
Short name T203
Test name
Test status
Simulation time 13902858254 ps
CPU time 1503.62 seconds
Started Aug 02 08:23:40 PM PDT 24
Finished Aug 02 08:48:44 PM PDT 24
Peak memory 607968 kb
Host smart-b2bcce3d-8ad9-4cfe-a958-4796432a25ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716114376 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_
mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.3
716114376
Directory /workspace/1.chip_jtag_mem_access/latest

Test location /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2991543041
Short name T71
Test name
Test status
Simulation time 3179055000 ps
CPU time 361.88 seconds
Started Aug 02 08:30:36 PM PDT 24
Finished Aug 02 08:36:38 PM PDT 24
Peak memory 621080 kb
Host smart-590e6fde-9628-4fab-9900-74709be9f34d
User root
Command /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2
991543041 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.2991543041
Directory /workspace/1.chip_rv_dm_ndm_reset_req/latest

Test location /workspace/coverage/default/1.chip_sival_flash_info_access.2019488318
Short name T1126
Test name
Test status
Simulation time 2372252488 ps
CPU time 249.12 seconds
Started Aug 02 08:23:20 PM PDT 24
Finished Aug 02 08:27:30 PM PDT 24
Peak memory 609976 kb
Host smart-6a32a469-1db0-4623-9833-27329fe5ad45
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=2019488318 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.2019488318
Directory /workspace/1.chip_sival_flash_info_access/latest

Test location /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1586829833
Short name T1144
Test name
Test status
Simulation time 18427487240 ps
CPU time 541.34 seconds
Started Aug 02 08:26:22 PM PDT 24
Finished Aug 02 08:35:24 PM PDT 24
Peak memory 619448 kb
Host smart-9b67ef10-1407-4903-aa48-b5ddb6d6b68d
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom:
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1586829833 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1586829833
Directory /workspace/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest

Test location /workspace/coverage/default/1.chip_sw_aes_enc.3407572228
Short name T1393
Test name
Test status
Simulation time 2792445560 ps
CPU time 283.8 seconds
Started Aug 02 08:27:49 PM PDT 24
Finished Aug 02 08:32:33 PM PDT 24
Peak memory 609360 kb
Host smart-77115b0b-1a4c-4c9c-bb20-ce2a1706499a
User root
Command /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407572228 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.3407572228
Directory /workspace/1.chip_sw_aes_enc/latest

Test location /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.2402547339
Short name T1278
Test name
Test status
Simulation time 2779297227 ps
CPU time 258.72 seconds
Started Aug 02 08:26:49 PM PDT 24
Finished Aug 02 08:31:07 PM PDT 24
Peak memory 608516 kb
Host smart-3fd965d2-df69-41ac-8f34-c4aa8ea5b853
User root
Command /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402
547339 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.2402547339
Directory /workspace/1.chip_sw_aes_enc_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2002514183
Short name T118
Test name
Test status
Simulation time 2884592307 ps
CPU time 241.56 seconds
Started Aug 02 08:31:17 PM PDT 24
Finished Aug 02 08:35:19 PM PDT 24
Peak memory 609560 kb
Host smart-95b35343-8dd6-46f0-b6b3-5774ed09c223
User root
Command /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,
test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2002514183 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.2002514183
Directory /workspace/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_aes_entropy.619492533
Short name T1256
Test name
Test status
Simulation time 3301060760 ps
CPU time 245.6 seconds
Started Aug 02 08:28:51 PM PDT 24
Finished Aug 02 08:32:57 PM PDT 24
Peak memory 609720 kb
Host smart-862e3341-520e-4548-a2bd-91648cd3cfda
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619492533 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_entropy.619492533
Directory /workspace/1.chip_sw_aes_entropy/latest

Test location /workspace/coverage/default/1.chip_sw_aes_idle.2299659523
Short name T954
Test name
Test status
Simulation time 3009042448 ps
CPU time 199.84 seconds
Started Aug 02 08:28:44 PM PDT 24
Finished Aug 02 08:32:04 PM PDT 24
Peak memory 609648 kb
Host smart-b4134895-b3c9-464d-af0b-918632061382
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299659523 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.2299659523
Directory /workspace/1.chip_sw_aes_idle/latest

Test location /workspace/coverage/default/1.chip_sw_aes_masking_off.3636568012
Short name T1002
Test name
Test status
Simulation time 3799546833 ps
CPU time 357.41 seconds
Started Aug 02 08:27:47 PM PDT 24
Finished Aug 02 08:33:44 PM PDT 24
Peak memory 610516 kb
Host smart-fa29631f-50f3-4aa0-885d-29f44d0f0254
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636568012 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.chip_sw_aes_masking_off.3636568012
Directory /workspace/1.chip_sw_aes_masking_off/latest

Test location /workspace/coverage/default/1.chip_sw_aes_smoketest.2367542631
Short name T1291
Test name
Test status
Simulation time 2591670808 ps
CPU time 347.32 seconds
Started Aug 02 08:35:04 PM PDT 24
Finished Aug 02 08:40:51 PM PDT 24
Peak memory 609752 kb
Host smart-a46b4fcf-3429-435f-a006-958868d14361
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367542631 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.chip_sw_aes_smoketest.2367542631
Directory /workspace/1.chip_sw_aes_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_escalation.3507680051
Short name T223
Test name
Test status
Simulation time 5227571052 ps
CPU time 662.24 seconds
Started Aug 02 08:28:24 PM PDT 24
Finished Aug 02 08:39:27 PM PDT 24
Peak memory 619676 kb
Host smart-8e63dbfe-594f-4651-89d7-d209d79a4ed5
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test
_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb
_random_seed=3507680051 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.3507680051
Directory /workspace/1.chip_sw_alert_handler_escalation/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.1216847379
Short name T992
Test name
Test status
Simulation time 9269374968 ps
CPU time 2212.5 seconds
Started Aug 02 08:28:53 PM PDT 24
Finished Aug 02 09:05:46 PM PDT 24
Peak memory 609884 kb
Host smart-fd1779dd-0be1-4bb6-8e8f-b52a5e6ee47a
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1216847379 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.1216847379
Directory /workspace/1.chip_sw_alert_handler_lpg_clkoff/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.63227327
Short name T1139
Test name
Test status
Simulation time 6051711560 ps
CPU time 1244.11 seconds
Started Aug 02 08:28:49 PM PDT 24
Finished Aug 02 08:49:34 PM PDT 24
Peak memory 610080 kb
Host smart-ae6ec6b6-8d2e-4425-8d1c-cec1e247e546
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules,
test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=63227327 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_toggle.63227327
Directory /workspace/1.chip_sw_alert_handler_lpg_reset_toggle/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.2965619304
Short name T1019
Test name
Test status
Simulation time 8207047730 ps
CPU time 1728.08 seconds
Started Aug 02 08:29:20 PM PDT 24
Finished Aug 02 08:58:09 PM PDT 24
Peak memory 609976 kb
Host smart-934ed9e8-bdf0-44ef-a991-5e9cb6bc793d
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=2965619304 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_ok.2965619304
Directory /workspace/1.chip_sw_alert_handler_ping_ok/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.602031363
Short name T436
Test name
Test status
Simulation time 3845563016 ps
CPU time 301.38 seconds
Started Aug 02 08:26:53 PM PDT 24
Finished Aug 02 08:31:55 PM PDT 24
Peak memory 609544 kb
Host smart-af8c75c3-5c28-43f5-961d-2d61e09483c2
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=602031363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.602031363
Directory /workspace/1.chip_sw_alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.chip_sw_alert_test.2693446921
Short name T53
Test name
Test status
Simulation time 3088299736 ps
CPU time 277.94 seconds
Started Aug 02 08:29:48 PM PDT 24
Finished Aug 02 08:34:27 PM PDT 24
Peak memory 609936 kb
Host smart-709ece4f-0cfb-42bd-ac96-8a9e57cc5afd
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693446921 -assert nopostproc +UVM_TESTNAME=chip_ba
se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.chip_sw_alert_test.2693446921
Directory /workspace/1.chip_sw_alert_test/latest

Test location /workspace/coverage/default/1.chip_sw_all_escalation_resets.3472994534
Short name T64
Test name
Test status
Simulation time 6211970046 ps
CPU time 717.68 seconds
Started Aug 02 08:25:39 PM PDT 24
Finished Aug 02 08:37:38 PM PDT 24
Peak memory 650040 kb
Host smart-b50d4548-cc39-46ac-8c54-af0c89a00e4e
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3472994534 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.3472994534
Directory /workspace/1.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/1.chip_sw_aon_timer_irq.2885484862
Short name T1349
Test name
Test status
Simulation time 4301554868 ps
CPU time 422.66 seconds
Started Aug 02 08:27:19 PM PDT 24
Finished Aug 02 08:34:21 PM PDT 24
Peak memory 609868 kb
Host smart-acf010a9-d5bf-4702-9d56-e95a33f4ae41
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885484862 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.2885484862
Directory /workspace/1.chip_sw_aon_timer_irq/latest

Test location /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.521276758
Short name T952
Test name
Test status
Simulation time 7218485736 ps
CPU time 424.82 seconds
Started Aug 02 08:26:51 PM PDT 24
Finished Aug 02 08:33:57 PM PDT 24
Peak memory 609180 kb
Host smart-863fc609-a7d3-4607-8b58-713b81626b03
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=521276758 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.521276758
Directory /workspace/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.2074088314
Short name T949
Test name
Test status
Simulation time 3024954032 ps
CPU time 415.27 seconds
Started Aug 02 08:32:24 PM PDT 24
Finished Aug 02 08:39:20 PM PDT 24
Peak memory 609712 kb
Host smart-a718ba05-b8fa-4816-9638-606684ba7dfc
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074088314 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.chip_sw_aon_timer_smoketest.2074088314
Directory /workspace/1.chip_sw_aon_timer_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.1495858587
Short name T1007
Test name
Test status
Simulation time 9147466880 ps
CPU time 690.76 seconds
Started Aug 02 08:26:07 PM PDT 24
Finished Aug 02 08:37:38 PM PDT 24
Peak memory 610468 kb
Host smart-ff2b3318-0bfa-4e10-9744-7f8a64621e22
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1495858587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.1495858587
Directory /workspace/1.chip_sw_aon_timer_wdog_bite_reset/latest

Test location /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.3123442003
Short name T940
Test name
Test status
Simulation time 5801511780 ps
CPU time 527.11 seconds
Started Aug 02 08:25:52 PM PDT 24
Finished Aug 02 08:34:40 PM PDT 24
Peak memory 609444 kb
Host smart-a471bbfa-b72b-4bc9-b145-c4c92f75089e
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3123442003 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.3123442003
Directory /workspace/1.chip_sw_aon_timer_wdog_lc_escalate/latest

Test location /workspace/coverage/default/1.chip_sw_ast_clk_outputs.2421037061
Short name T756
Test name
Test status
Simulation time 7906857786 ps
CPU time 1026.25 seconds
Started Aug 02 08:31:19 PM PDT 24
Finished Aug 02 08:48:25 PM PDT 24
Peak memory 616356 kb
Host smart-7b2c3fa8-e9fe-44f0-83f1-56fc4aa7c035
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421037061 -assert nopo
stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.2421037061
Directory /workspace/1.chip_sw_ast_clk_outputs/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.3479589488
Short name T1109
Test name
Test status
Simulation time 12958132358 ps
CPU time 1044.95 seconds
Started Aug 02 08:30:09 PM PDT 24
Finished Aug 02 08:47:34 PM PDT 24
Peak memory 620516 kb
Host smart-1d0a6193-9c58-4798-ac51-c8d2edf8f85d
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r
ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim
.tcl +ntb_random_seed=3479589488 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.3479589488
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_lc/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3935745004
Short name T1082
Test name
Test status
Simulation time 3500742380 ps
CPU time 631.52 seconds
Started Aug 02 08:30:44 PM PDT 24
Finished Aug 02 08:41:16 PM PDT 24
Peak memory 612248 kb
Host smart-6820ee80-b65e-475a-a842-0f5db77a23fa
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935745004 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c
lkmgr_external_clk_src_for_sw_fast_dev.3935745004
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1585992918
Short name T930
Test name
Test status
Simulation time 4154480808 ps
CPU time 610.37 seconds
Started Aug 02 08:31:19 PM PDT 24
Finished Aug 02 08:41:29 PM PDT 24
Peak memory 613164 kb
Host smart-61b5e3d4-0d3c-450f-8a24-7d207679ec67
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585992918 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c
lkmgr_external_clk_src_for_sw_fast_rma.1585992918
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.686831991
Short name T947
Test name
Test status
Simulation time 3480681184 ps
CPU time 665.58 seconds
Started Aug 02 08:30:11 PM PDT 24
Finished Aug 02 08:41:17 PM PDT 24
Peak memory 613128 kb
Host smart-1d81bb10-f02b-4de8-8fbb-f976b9f40323
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_
dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686831991 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM
_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.686831991
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1518887621
Short name T1092
Test name
Test status
Simulation time 4804039140 ps
CPU time 671.87 seconds
Started Aug 02 08:31:30 PM PDT 24
Finished Aug 02 08:42:42 PM PDT 24
Peak memory 612104 kb
Host smart-50dfb2ed-2f4f-4294-9bb7-5f05b480a904
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518887621 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c
lkmgr_external_clk_src_for_sw_slow_dev.1518887621
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2955789653
Short name T1020
Test name
Test status
Simulation time 5521821050 ps
CPU time 620.08 seconds
Started Aug 02 08:30:40 PM PDT 24
Finished Aug 02 08:41:00 PM PDT 24
Peak memory 612116 kb
Host smart-e6646c8b-497f-449d-89a0-761c5411be6c
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955789653 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c
lkmgr_external_clk_src_for_sw_slow_rma.2955789653
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2666976401
Short name T1043
Test name
Test status
Simulation time 4526975948 ps
CPU time 582.82 seconds
Started Aug 02 08:30:42 PM PDT 24
Finished Aug 02 08:40:25 PM PDT 24
Peak memory 613152 kb
Host smart-47d0bfda-8933-4844-9060-a7598222b4e3
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_
dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666976401 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV
M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2666976401
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_jitter.3098716671
Short name T1037
Test name
Test status
Simulation time 2609237122 ps
CPU time 252.99 seconds
Started Aug 02 08:31:06 PM PDT 24
Finished Aug 02 08:35:19 PM PDT 24
Peak memory 609548 kb
Host smart-34fd2b1d-fbe0-4131-b07d-20d44724b577
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098716671 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.chip_sw_clkmgr_jitter.3098716671
Directory /workspace/1.chip_sw_clkmgr_jitter/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.3276406713
Short name T1063
Test name
Test status
Simulation time 3147555366 ps
CPU time 570.68 seconds
Started Aug 02 08:32:50 PM PDT 24
Finished Aug 02 08:42:20 PM PDT 24
Peak memory 609732 kb
Host smart-1a25f4ad-8462-449b-b878-817937ef3916
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276406713 -assert nopostproc +UV
M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_frequency.3276406713
Directory /workspace/1.chip_sw_clkmgr_jitter_frequency/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.2433817750
Short name T1178
Test name
Test status
Simulation time 2992125288 ps
CPU time 227.91 seconds
Started Aug 02 08:35:41 PM PDT 24
Finished Aug 02 08:39:29 PM PDT 24
Peak memory 609592 kb
Host smart-ae6343ab-a985-4aab-ab37-7e83265d829d
User root
Command /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433817750 -assert nop
ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.2433817750
Directory /workspace/1.chip_sw_clkmgr_jitter_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.4247217634
Short name T1195
Test name
Test status
Simulation time 4285584360 ps
CPU time 467.48 seconds
Started Aug 02 08:31:00 PM PDT 24
Finished Aug 02 08:38:48 PM PDT 24
Peak memory 610048 kb
Host smart-4413c526-c573-4af0-a2a9-a9437b1645e7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247217634 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.4247217634
Directory /workspace/1.chip_sw_clkmgr_off_aes_trans/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.2617044854
Short name T1129
Test name
Test status
Simulation time 5036901760 ps
CPU time 536.57 seconds
Started Aug 02 08:30:45 PM PDT 24
Finished Aug 02 08:39:42 PM PDT 24
Peak memory 610600 kb
Host smart-e355f1dc-164a-4609-8cd4-5be6208f17dc
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617044854 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.chip_sw_clkmgr_off_hmac_trans.2617044854
Directory /workspace/1.chip_sw_clkmgr_off_hmac_trans/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.591431367
Short name T1012
Test name
Test status
Simulation time 3914708372 ps
CPU time 421.73 seconds
Started Aug 02 08:32:40 PM PDT 24
Finished Aug 02 08:39:42 PM PDT 24
Peak memory 609908 kb
Host smart-ce891af7-ce7a-4db6-974b-31511eb0a462
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591431367 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.chip_sw_clkmgr_off_kmac_trans.591431367
Directory /workspace/1.chip_sw_clkmgr_off_kmac_trans/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.1290038191
Short name T1303
Test name
Test status
Simulation time 3916963216 ps
CPU time 377.04 seconds
Started Aug 02 08:32:25 PM PDT 24
Finished Aug 02 08:38:42 PM PDT 24
Peak memory 610136 kb
Host smart-991b6f6f-6709-4440-a1b6-09858e11b9a2
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290038191 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.chip_sw_clkmgr_off_otbn_trans.1290038191
Directory /workspace/1.chip_sw_clkmgr_off_otbn_trans/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.130305852
Short name T1316
Test name
Test status
Simulation time 10772131184 ps
CPU time 1806.16 seconds
Started Aug 02 08:33:02 PM PDT 24
Finished Aug 02 09:03:08 PM PDT 24
Peak memory 610280 kb
Host smart-4bd69741-f835-4f40-95cc-cda0b0c8a8cc
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130305852
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.130305852
Directory /workspace/1.chip_sw_clkmgr_off_peri/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.1042327813
Short name T1186
Test name
Test status
Simulation time 3288101040 ps
CPU time 492.93 seconds
Started Aug 02 08:30:48 PM PDT 24
Finished Aug 02 08:39:01 PM PDT 24
Peak memory 609848 kb
Host smart-ea786527-c08f-434c-8ecf-bb08d3de671d
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042327813 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.1042327813
Directory /workspace/1.chip_sw_clkmgr_reset_frequency/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.570748476
Short name T936
Test name
Test status
Simulation time 5073744358 ps
CPU time 678.86 seconds
Started Aug 02 08:33:47 PM PDT 24
Finished Aug 02 08:45:06 PM PDT 24
Peak memory 610324 kb
Host smart-aebf34c0-5cc0-4e5c-8875-86e75059b068
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570748476 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.570748476
Directory /workspace/1.chip_sw_clkmgr_sleep_frequency/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.3848150707
Short name T1321
Test name
Test status
Simulation time 3295908480 ps
CPU time 269.8 seconds
Started Aug 02 08:33:19 PM PDT 24
Finished Aug 02 08:37:49 PM PDT 24
Peak memory 608444 kb
Host smart-ace4743b-abfb-4565-81f4-5b2276c91c62
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848150707 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.chip_sw_clkmgr_smoketest.3848150707
Directory /workspace/1.chip_sw_clkmgr_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.1016146220
Short name T267
Test name
Test status
Simulation time 15007587142 ps
CPU time 3302.18 seconds
Started Aug 02 08:27:47 PM PDT 24
Finished Aug 02 09:22:50 PM PDT 24
Peak memory 609368 kb
Host smart-8bb8d5c6-18a8-4366-b1ee-cad637032bdf
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016146220 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency.1016146220
Directory /workspace/1.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.737545103
Short name T290
Test name
Test status
Simulation time 3341974028 ps
CPU time 450.02 seconds
Started Aug 02 08:28:40 PM PDT 24
Finished Aug 02 08:36:11 PM PDT 24
Peak memory 609700 kb
Host smart-6c77473a-391b-4986-91e6-ad6a8cbbb129
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73754
5103 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.737545103
Directory /workspace/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest

Test location /workspace/coverage/default/1.chip_sw_csrng_kat_test.2424795252
Short name T1176
Test name
Test status
Simulation time 3141319342 ps
CPU time 268.76 seconds
Started Aug 02 08:28:26 PM PDT 24
Finished Aug 02 08:32:55 PM PDT 24
Peak memory 609484 kb
Host smart-ca1bfa93-bd61-4362-b665-baa78122e509
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424795252 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_kat_test.2424795252
Directory /workspace/1.chip_sw_csrng_kat_test/latest

Test location /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.2639948697
Short name T1090
Test name
Test status
Simulation time 6545536840 ps
CPU time 717.66 seconds
Started Aug 02 08:29:54 PM PDT 24
Finished Aug 02 08:41:52 PM PDT 24
Peak memory 611160 kb
Host smart-7869e2bc-2cb7-4476-a3aa-d50c3deea102
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima
ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639948697 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_
lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csr
ng_lc_hw_debug_en_test.2639948697
Directory /workspace/1.chip_sw_csrng_lc_hw_debug_en_test/latest

Test location /workspace/coverage/default/1.chip_sw_csrng_smoketest.2141481954
Short name T958
Test name
Test status
Simulation time 3317305124 ps
CPU time 382.73 seconds
Started Aug 02 08:33:22 PM PDT 24
Finished Aug 02 08:39:45 PM PDT 24
Peak memory 608384 kb
Host smart-b6238f54-1bae-4661-acb4-f79edeef3fe1
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141481954 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.chip_sw_csrng_smoketest.2141481954
Directory /workspace/1.chip_sw_csrng_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_edn_auto_mode.3996918046
Short name T1374
Test name
Test status
Simulation time 4824682680 ps
CPU time 1125.64 seconds
Started Aug 02 08:30:48 PM PDT 24
Finished Aug 02 08:49:34 PM PDT 24
Peak memory 610292 kb
Host smart-43978a4f-cc73-489d-a439-b375d8e22802
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_
build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996918046 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_
auto_mode.3996918046
Directory /workspace/1.chip_sw_edn_auto_mode/latest

Test location /workspace/coverage/default/1.chip_sw_edn_boot_mode.2368116910
Short name T688
Test name
Test status
Simulation time 3136171980 ps
CPU time 704.24 seconds
Started Aug 02 08:28:27 PM PDT 24
Finished Aug 02 08:40:12 PM PDT 24
Peak memory 609788 kb
Host smart-b8944f75-3472-4b94-81c3-948d4cf3160c
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_
build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368116910 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_
boot_mode.2368116910
Directory /workspace/1.chip_sw_edn_boot_mode/latest

Test location /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.169937194
Short name T1188
Test name
Test status
Simulation time 7187247080 ps
CPU time 1111.07 seconds
Started Aug 02 08:32:40 PM PDT 24
Finished Aug 02 08:51:11 PM PDT 24
Peak memory 610712 kb
Host smart-fb5af308-f0db-4fdc-af76-7641a78b42d6
User root
Command /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed
n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=169937194 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.169937194
Directory /workspace/1.chip_sw_edn_entropy_reqs/latest

Test location /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3078773672
Short name T1377
Test name
Test status
Simulation time 7784550570 ps
CPU time 1398.95 seconds
Started Aug 02 08:29:06 PM PDT 24
Finished Aug 02 08:52:25 PM PDT 24
Peak memory 610988 kb
Host smart-8ebd1f3b-ce03-4fb8-a621-38f41552da15
User root
Command /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e
ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078773672 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.3078773672
Directory /workspace/1.chip_sw_edn_entropy_reqs_jitter/latest

Test location /workspace/coverage/default/1.chip_sw_edn_kat.3103469495
Short name T1028
Test name
Test status
Simulation time 3288563138 ps
CPU time 661.65 seconds
Started Aug 02 08:28:32 PM PDT 24
Finished Aug 02 08:39:34 PM PDT 24
Peak memory 615604 kb
Host smart-598641fe-0138-46da-b6e0-4ffccafd375f
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3
+accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103469495 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.chip_sw_edn_kat.3103469495
Directory /workspace/1.chip_sw_edn_kat/latest

Test location /workspace/coverage/default/1.chip_sw_edn_sw_mode.4281086309
Short name T1198
Test name
Test status
Simulation time 8407581086 ps
CPU time 1506.32 seconds
Started Aug 02 08:27:27 PM PDT 24
Finished Aug 02 08:52:33 PM PDT 24
Peak memory 609340 kb
Host smart-5b5723a9-0ff4-491c-b35e-44e63c4a47b3
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281086309 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_sw_mode.4281086309
Directory /workspace/1.chip_sw_edn_sw_mode/latest

Test location /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.488902991
Short name T938
Test name
Test status
Simulation time 2900768006 ps
CPU time 247.24 seconds
Started Aug 02 08:29:20 PM PDT 24
Finished Aug 02 08:33:27 PM PDT 24
Peak memory 608436 kb
Host smart-eee4eee8-693e-45f3-8b4e-5456913ee540
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48
8902991 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.488902991
Directory /workspace/1.chip_sw_entropy_src_ast_rng_req/latest

Test location /workspace/coverage/default/1.chip_sw_entropy_src_csrng.2163474942
Short name T1364
Test name
Test status
Simulation time 7996727938 ps
CPU time 1914.37 seconds
Started Aug 02 08:29:41 PM PDT 24
Finished Aug 02 09:01:36 PM PDT 24
Peak memory 610288 kb
Host smart-5e11e0ea-60de-4dfe-bb02-ca995ae4c1e4
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_
csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2163474942 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.2163474942
Directory /workspace/1.chip_sw_entropy_src_csrng/latest

Test location /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2624772623
Short name T1396
Test name
Test status
Simulation time 3129795792 ps
CPU time 225.01 seconds
Started Aug 02 08:27:33 PM PDT 24
Finished Aug 02 08:31:18 PM PDT 24
Peak memory 609836 kb
Host smart-d8ed092e-7d8c-447a-b7eb-1c0963081bc3
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624772623
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.2624772623
Directory /workspace/1.chip_sw_entropy_src_kat_test/latest

Test location /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.4160557679
Short name T983
Test name
Test status
Simulation time 4128345136 ps
CPU time 470.35 seconds
Started Aug 02 08:35:11 PM PDT 24
Finished Aug 02 08:43:01 PM PDT 24
Peak memory 609820 kb
Host smart-9d558ad3-a776-467b-ac10-ae1ad3a60b4b
User root
Command /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom:
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4160557679 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.4160557679
Directory /workspace/1.chip_sw_entropy_src_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_example_concurrency.30599559
Short name T976
Test name
Test status
Simulation time 2485719050 ps
CPU time 242.72 seconds
Started Aug 02 08:24:05 PM PDT 24
Finished Aug 02 08:28:08 PM PDT 24
Peak memory 608416 kb
Host smart-45335014-f95b-42e6-bd5d-fb111e99495c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30599559 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.chip_sw_example_concurrency.30599559
Directory /workspace/1.chip_sw_example_concurrency/latest

Test location /workspace/coverage/default/1.chip_sw_example_flash.663733100
Short name T1181
Test name
Test status
Simulation time 3309579520 ps
CPU time 252.93 seconds
Started Aug 02 08:22:56 PM PDT 24
Finished Aug 02 08:27:10 PM PDT 24
Peak memory 609588 kb
Host smart-50748495-f125-42e3-a84f-7c208544e75f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663733100 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.chip_sw_example_flash.663733100
Directory /workspace/1.chip_sw_example_flash/latest

Test location /workspace/coverage/default/1.chip_sw_example_manufacturer.3769183639
Short name T1042
Test name
Test status
Simulation time 2160335948 ps
CPU time 194.6 seconds
Started Aug 02 08:23:39 PM PDT 24
Finished Aug 02 08:26:54 PM PDT 24
Peak memory 609536 kb
Host smart-f246541b-f77f-4575-8ede-ea5fd533c29c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769183639 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.chip_sw_example_manufacturer.3769183639
Directory /workspace/1.chip_sw_example_manufacturer/latest

Test location /workspace/coverage/default/1.chip_sw_example_rom.1405880539
Short name T933
Test name
Test status
Simulation time 2123725704 ps
CPU time 115.13 seconds
Started Aug 02 08:22:39 PM PDT 24
Finished Aug 02 08:24:34 PM PDT 24
Peak memory 609104 kb
Host smart-23c5a704-f4db-4085-b58b-0a7c245865a5
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405880539 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.chip_sw_example_rom.1405880539
Directory /workspace/1.chip_sw_example_rom/latest

Test location /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.3500925056
Short name T1259
Test name
Test status
Simulation time 58619994540 ps
CPU time 10189.2 seconds
Started Aug 02 08:22:23 PM PDT 24
Finished Aug 02 11:12:13 PM PDT 24
Peak memory 624756 kb
Host smart-1e44ff46-da4e-4d1c-aed7-0c217e3534b0
User root
Command /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new
_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s
im.tcl +ntb_random_seed=3500925056 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_exit_test_unlocked_bootstrap.3500925056
Directory /workspace/1.chip_sw_exit_test_unlocked_bootstrap/latest

Test location /workspace/coverage/default/1.chip_sw_flash_crash_alert.3241921418
Short name T275
Test name
Test status
Simulation time 5115007676 ps
CPU time 660.98 seconds
Started Aug 02 08:32:30 PM PDT 24
Finished Aug 02 08:43:32 PM PDT 24
Peak memory 611044 kb
Host smart-c869a7ba-bfad-41ec-a70f-63815e1dc9cc
User root
Command /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:
new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool
s/sim.tcl +ntb_random_seed=3241921418 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.3241921418
Directory /workspace/1.chip_sw_flash_crash_alert/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_access.3071906896
Short name T1070
Test name
Test status
Simulation time 5265484960 ps
CPU time 1048.32 seconds
Started Aug 02 08:24:39 PM PDT 24
Finished Aug 02 08:42:08 PM PDT 24
Peak memory 610024 kb
Host smart-427ef16e-c1f3-4ba5-8b92-a0a43731c643
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071906896 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.chip_sw_flash_ctrl_access.3071906896
Directory /workspace/1.chip_sw_flash_ctrl_access/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1655713764
Short name T765
Test name
Test status
Simulation time 6082901374 ps
CPU time 1233.93 seconds
Started Aug 02 08:28:25 PM PDT 24
Finished Aug 02 08:48:59 PM PDT 24
Peak memory 609440 kb
Host smart-4bf92171-5e62-4f1a-aac3-a7594804b666
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655713764 -assert nopostproc +UV
M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en.1655713764
Directory /workspace/1.chip_sw_flash_ctrl_access_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.121040840
Short name T985
Test name
Test status
Simulation time 7366252083 ps
CPU time 1266.07 seconds
Started Aug 02 08:32:39 PM PDT 24
Finished Aug 02 08:53:45 PM PDT 24
Peak memory 608928 kb
Host smart-cea3ec8d-b4fe-49c0-9509-783de2fb60eb
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121040840 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.121040840
Directory /workspace/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.3385514843
Short name T1067
Test name
Test status
Simulation time 6117921128 ps
CPU time 1229.18 seconds
Started Aug 02 08:23:36 PM PDT 24
Finished Aug 02 08:44:05 PM PDT 24
Peak memory 610128 kb
Host smart-124ef659-1400-404d-8c8c-e070dd063100
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385514843 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.chip_sw_flash_ctrl_clock_freqs.3385514843
Directory /workspace/1.chip_sw_flash_ctrl_clock_freqs/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.3777843727
Short name T1204
Test name
Test status
Simulation time 2879402688 ps
CPU time 365.89 seconds
Started Aug 02 08:23:45 PM PDT 24
Finished Aug 02 08:29:51 PM PDT 24
Peak memory 609944 kb
Host smart-f448dd28-1b16-4ce8-a079-d8bbc6af2e4d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777843727 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_idle_low_power.3777843727
Directory /workspace/1.chip_sw_flash_ctrl_idle_low_power/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.4030865358
Short name T241
Test name
Test status
Simulation time 5030838515 ps
CPU time 445.32 seconds
Started Aug 02 08:23:13 PM PDT 24
Finished Aug 02 08:30:38 PM PDT 24
Peak memory 610908 kb
Host smart-456b461f-4707-4255-a969-2ad423c81f52
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40
30865358 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_lc_rw_en.4030865358
Directory /workspace/1.chip_sw_flash_ctrl_lc_rw_en/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.4250027820
Short name T1083
Test name
Test status
Simulation time 5705118014 ps
CPU time 1131.49 seconds
Started Aug 02 08:32:24 PM PDT 24
Finished Aug 02 08:51:16 PM PDT 24
Peak memory 610060 kb
Host smart-409a3782-dcf6-4dd5-a5df-bcabafd42f3a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250027820 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_mem_protection.4250027820
Directory /workspace/1.chip_sw_flash_ctrl_mem_protection/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.2410486731
Short name T1097
Test name
Test status
Simulation time 4689732644 ps
CPU time 642.69 seconds
Started Aug 02 08:27:07 PM PDT 24
Finished Aug 02 08:37:50 PM PDT 24
Peak memory 609924 kb
Host smart-7fca7d02-d787-46b3-a5d7-3b30f3cf4f0e
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410486731
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.2410486731
Directory /workspace/1.chip_sw_flash_ctrl_ops/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.716430398
Short name T1351
Test name
Test status
Simulation time 4060007714 ps
CPU time 826.28 seconds
Started Aug 02 08:24:09 PM PDT 24
Finished Aug 02 08:37:55 PM PDT 24
Peak memory 609848 kb
Host smart-4a92b4b1-b42c-4272-857e-6927367ec1d1
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=716430398 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.716430398
Directory /workspace/1.chip_sw_flash_ctrl_ops_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.3981617330
Short name T1150
Test name
Test status
Simulation time 3557305120 ps
CPU time 264.9 seconds
Started Aug 02 08:30:59 PM PDT 24
Finished Aug 02 08:35:24 PM PDT 24
Peak memory 609776 kb
Host smart-12846e59-ebeb-4b66-b088-32699f0917d2
User root
Command /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981617
330 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_write_clear.3981617330
Directory /workspace/1.chip_sw_flash_ctrl_write_clear/latest

Test location /workspace/coverage/default/1.chip_sw_flash_init.562621356
Short name T1143
Test name
Test status
Simulation time 23089302246 ps
CPU time 1598.79 seconds
Started Aug 02 08:23:23 PM PDT 24
Finished Aug 02 08:50:02 PM PDT 24
Peak memory 613680 kb
Host smart-98fdebca-b533-4800-9552-742903705657
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562621356 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init.562621356
Directory /workspace/1.chip_sw_flash_init/latest

Test location /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.179509016
Short name T1220
Test name
Test status
Simulation time 26591845997 ps
CPU time 2236.09 seconds
Started Aug 02 08:33:16 PM PDT 24
Finished Aug 02 09:10:32 PM PDT 24
Peak memory 611612 kb
Host smart-f344c05c-5277-4602-8c05-25aa7511004f
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=179509016 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.179509016
Directory /workspace/1.chip_sw_flash_init_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.3312373943
Short name T1212
Test name
Test status
Simulation time 2175012750 ps
CPU time 257.75 seconds
Started Aug 02 08:37:06 PM PDT 24
Finished Aug 02 08:41:24 PM PDT 24
Peak memory 609580 kb
Host smart-d9c944fd-5c7e-493e-acef-a30cab6860c3
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket
est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3312373943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.3312373943
Directory /workspace/1.chip_sw_flash_scrambling_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_gpio_smoketest.645558836
Short name T211
Test name
Test status
Simulation time 3639318634 ps
CPU time 382.93 seconds
Started Aug 02 08:33:31 PM PDT 24
Finished Aug 02 08:39:54 PM PDT 24
Peak memory 608608 kb
Host smart-3baba613-b6ee-459b-8e2e-bdc0be44cfe1
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645558836 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.chip_sw_gpio_smoketest.645558836
Directory /workspace/1.chip_sw_gpio_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_enc.4033647328
Short name T1011
Test name
Test status
Simulation time 3227863052 ps
CPU time 238.55 seconds
Started Aug 02 08:30:54 PM PDT 24
Finished Aug 02 08:34:53 PM PDT 24
Peak memory 608604 kb
Host smart-4da84d1d-0662-4fdf-8f62-a1eec1c4d357
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033647328 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.chip_sw_hmac_enc.4033647328
Directory /workspace/1.chip_sw_hmac_enc/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_enc_idle.1998441894
Short name T966
Test name
Test status
Simulation time 2314646028 ps
CPU time 285.32 seconds
Started Aug 02 08:28:41 PM PDT 24
Finished Aug 02 08:33:27 PM PDT 24
Peak memory 609784 kb
Host smart-9482ccd3-104e-4750-a2c1-38e09b6a81ac
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998441894 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.chip_sw_hmac_enc_idle.1998441894
Directory /workspace/1.chip_sw_hmac_enc_idle/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.4159110477
Short name T377
Test name
Test status
Simulation time 3066521557 ps
CPU time 284.72 seconds
Started Aug 02 08:29:54 PM PDT 24
Finished Aug 02 08:34:39 PM PDT 24
Peak memory 609700 kb
Host smart-619a7fa3-d57a-4358-aeec-4823bf822e83
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159110477 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en.4159110477
Directory /workspace/1.chip_sw_hmac_enc_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.631741510
Short name T1052
Test name
Test status
Simulation time 3174270920 ps
CPU time 330.19 seconds
Started Aug 02 08:33:03 PM PDT 24
Finished Aug 02 08:38:34 PM PDT 24
Peak memory 608520 kb
Host smart-b516a59d-a3c2-49dc-8fd6-534b3f0f6de6
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631741510 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.631741510
Directory /workspace/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_multistream.1569918719
Short name T1211
Test name
Test status
Simulation time 8681453484 ps
CPU time 1701.5 seconds
Started Aug 02 08:30:27 PM PDT 24
Finished Aug 02 08:58:49 PM PDT 24
Peak memory 608988 kb
Host smart-ced6037f-993d-40da-8788-e46ef7994564
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569918719 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.chip_sw_hmac_multistream.1569918719
Directory /workspace/1.chip_sw_hmac_multistream/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_oneshot.2007125362
Short name T730
Test name
Test status
Simulation time 2670167464 ps
CPU time 402.89 seconds
Started Aug 02 08:29:38 PM PDT 24
Finished Aug 02 08:36:21 PM PDT 24
Peak memory 608464 kb
Host smart-1f750219-234c-4b90-ab9c-6a743d342ac1
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007125362 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.chip_sw_hmac_oneshot.2007125362
Directory /workspace/1.chip_sw_hmac_oneshot/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_smoketest.2397603806
Short name T1329
Test name
Test status
Simulation time 3471552120 ps
CPU time 404.94 seconds
Started Aug 02 08:33:44 PM PDT 24
Finished Aug 02 08:40:30 PM PDT 24
Peak memory 609684 kb
Host smart-faab94e5-327b-4e9d-b592-e73b8e0b16d1
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397603806 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.chip_sw_hmac_smoketest.2397603806
Directory /workspace/1.chip_sw_hmac_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.2555170962
Short name T349
Test name
Test status
Simulation time 4056678328 ps
CPU time 676.75 seconds
Started Aug 02 08:25:44 PM PDT 24
Finished Aug 02 08:37:02 PM PDT 24
Peak memory 609752 kb
Host smart-1a700988-6109-4f34-b1c4-8b124acab205
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555170962 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.2555170962
Directory /workspace/1.chip_sw_i2c_device_tx_rx/latest

Test location /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.3046991551
Short name T359
Test name
Test status
Simulation time 3975987416 ps
CPU time 815.31 seconds
Started Aug 02 08:23:33 PM PDT 24
Finished Aug 02 08:37:08 PM PDT 24
Peak memory 608904 kb
Host smart-6b95ce40-eced-43e6-99d9-d07ce84873b7
User root
Command /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046991551 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx.3046991551
Directory /workspace/1.chip_sw_i2c_host_tx_rx/latest

Test location /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3138250209
Short name T338
Test name
Test status
Simulation time 4624720742 ps
CPU time 1017.85 seconds
Started Aug 02 08:26:37 PM PDT 24
Finished Aug 02 08:43:36 PM PDT 24
Peak memory 610212 kb
Host smart-33a48366-56cc-44ae-971d-d216fca5b0e7
User root
Command /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138250209 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.3138250209
Directory /workspace/1.chip_sw_i2c_host_tx_rx_idx1/latest

Test location /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.2571206543
Short name T313
Test name
Test status
Simulation time 5495988304 ps
CPU time 638.24 seconds
Started Aug 02 08:24:37 PM PDT 24
Finished Aug 02 08:35:16 PM PDT 24
Peak memory 609352 kb
Host smart-62773d36-988c-4eaa-817a-3e6613e6d64c
User root
Command /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571206543 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.2571206543
Directory /workspace/1.chip_sw_i2c_host_tx_rx_idx2/latest

Test location /workspace/coverage/default/1.chip_sw_inject_scramble_seed.3425411988
Short name T1205
Test name
Test status
Simulation time 64509143556 ps
CPU time 11758.5 seconds
Started Aug 02 08:22:31 PM PDT 24
Finished Aug 02 11:38:30 PM PDT 24
Peak memory 624796 kb
Host smart-b26c25d0-4cc6-4f5d-b111-f4c1d962b746
User root
Command /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3425411988 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.3425411988
Directory /workspace/1.chip_sw_inject_scramble_seed/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.426458015
Short name T1228
Test name
Test status
Simulation time 6944715720 ps
CPU time 1683.11 seconds
Started Aug 02 08:28:48 PM PDT 24
Finished Aug 02 08:56:51 PM PDT 24
Peak memory 618312 kb
Host smart-630396d5-3e1c-40a4-bcde-cba11f80d672
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264
58015 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation.426458015
Directory /workspace/1.chip_sw_keymgr_key_derivation/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.3026172200
Short name T1299
Test name
Test status
Simulation time 7499720591 ps
CPU time 1373.46 seconds
Started Aug 02 08:29:58 PM PDT 24
Finished Aug 02 08:52:52 PM PDT 24
Peak memory 616680 kb
Host smart-0d034d80-e4a7-472a-b194-889fffe93d1f
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3026172200 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en.3026172200
Directory /workspace/1.chip_sw_keymgr_key_derivation_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.396838284
Short name T1049
Test name
Test status
Simulation time 8619095214 ps
CPU time 1337.13 seconds
Started Aug 02 08:32:10 PM PDT 24
Finished Aug 02 08:54:28 PM PDT 24
Peak memory 617864 kb
Host smart-71b6dcfb-02eb-434b-ac4b-a56946b47306
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=396838284 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en_
reduced_freq.396838284
Directory /workspace/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.3430932636
Short name T1032
Test name
Test status
Simulation time 9920788610 ps
CPU time 2236.33 seconds
Started Aug 02 08:30:38 PM PDT 24
Finished Aug 02 09:07:55 PM PDT 24
Peak memory 617660 kb
Host smart-74d4db68-abca-420c-be6d-fac1c3dc864b
User root
Command /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3430932636 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.3430932636
Directory /workspace/1.chip_sw_keymgr_key_derivation_prod/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.52426715
Short name T230
Test name
Test status
Simulation time 7214961810 ps
CPU time 1727.39 seconds
Started Aug 02 08:30:36 PM PDT 24
Finished Aug 02 08:59:24 PM PDT 24
Peak memory 611324 kb
Host smart-870d205a-1662-4d0f-aa6e-48b27bc6953f
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524267
15 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_aes.52426715
Directory /workspace/1.chip_sw_keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.1954510515
Short name T1325
Test name
Test status
Simulation time 13050109032 ps
CPU time 3017.41 seconds
Started Aug 02 08:30:53 PM PDT 24
Finished Aug 02 09:21:11 PM PDT 24
Peak memory 611088 kb
Host smart-25a249c7-6dc1-46e7-a2a1-7d25d5d4ca74
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19545
10515 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.1954510515
Directory /workspace/1.chip_sw_keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.731154572
Short name T233
Test name
Test status
Simulation time 16670912098 ps
CPU time 3760.23 seconds
Started Aug 02 08:30:01 PM PDT 24
Finished Aug 02 09:32:42 PM PDT 24
Peak memory 610964 kb
Host smart-ab0fd37b-1770-4760-9e8f-646623d8c27c
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73115
4572 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.731154572
Directory /workspace/1.chip_sw_keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_app_rom.1833227004
Short name T1171
Test name
Test status
Simulation time 2801721980 ps
CPU time 192.69 seconds
Started Aug 02 08:29:20 PM PDT 24
Finished Aug 02 08:32:33 PM PDT 24
Peak memory 608396 kb
Host smart-74f7daaa-66b1-434f-be49-1690cd6ad863
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833227004 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.chip_sw_kmac_app_rom.1833227004
Directory /workspace/1.chip_sw_kmac_app_rom/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_entropy.3148356927
Short name T1288
Test name
Test status
Simulation time 3338485224 ps
CPU time 306.05 seconds
Started Aug 02 08:25:32 PM PDT 24
Finished Aug 02 08:30:39 PM PDT 24
Peak memory 609560 kb
Host smart-0fe31354-f6fd-4214-834c-728f52708248
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148356927 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.chip_sw_kmac_entropy.3148356927
Directory /workspace/1.chip_sw_kmac_entropy/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_idle.4175233735
Short name T1068
Test name
Test status
Simulation time 3344134296 ps
CPU time 238.36 seconds
Started Aug 02 08:30:13 PM PDT 24
Finished Aug 02 08:34:11 PM PDT 24
Peak memory 608424 kb
Host smart-d505674f-2a94-4c55-8aba-4ce866b85730
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175233735 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.chip_sw_kmac_idle.4175233735
Directory /workspace/1.chip_sw_kmac_idle/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3269876515
Short name T999
Test name
Test status
Simulation time 3337463400 ps
CPU time 339.48 seconds
Started Aug 02 08:30:37 PM PDT 24
Finished Aug 02 08:36:17 PM PDT 24
Peak memory 609716 kb
Host smart-04bf8a2a-078d-407f-8466-4f4acd266dcd
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269876515 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.chip_sw_kmac_mode_cshake.3269876515
Directory /workspace/1.chip_sw_kmac_mode_cshake/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2250455591
Short name T1226
Test name
Test status
Simulation time 3350690352 ps
CPU time 344.5 seconds
Started Aug 02 08:29:59 PM PDT 24
Finished Aug 02 08:35:44 PM PDT 24
Peak memory 608616 kb
Host smart-5ed178d5-3827-4b82-a8e2-21be1ec50efb
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250455591 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.chip_sw_kmac_mode_kmac.2250455591
Directory /workspace/1.chip_sw_kmac_mode_kmac/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.3049104428
Short name T446
Test name
Test status
Simulation time 3352267508 ps
CPU time 356.8 seconds
Started Aug 02 08:30:03 PM PDT 24
Finished Aug 02 08:36:00 PM PDT 24
Peak memory 609668 kb
Host smart-f59772be-3e1a-4733-aa9b-14c7b15bbe38
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049104428 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.3049104428
Directory /workspace/1.chip_sw_kmac_mode_kmac_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3565629230
Short name T1124
Test name
Test status
Simulation time 3045752921 ps
CPU time 285.42 seconds
Started Aug 02 08:32:04 PM PDT 24
Finished Aug 02 08:36:50 PM PDT 24
Peak memory 609856 kb
Host smart-29c1f159-f2f5-4faf-8dc5-1a28ad3af25b
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35656292
30 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3565629230
Directory /workspace/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_smoketest.123429111
Short name T1265
Test name
Test status
Simulation time 3170009320 ps
CPU time 360.74 seconds
Started Aug 02 08:33:03 PM PDT 24
Finished Aug 02 08:39:04 PM PDT 24
Peak memory 609660 kb
Host smart-24651bbb-46ac-4a7e-91d1-ff0c116b165c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123429111 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.chip_sw_kmac_smoketest.123429111
Directory /workspace/1.chip_sw_kmac_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.447033899
Short name T919
Test name
Test status
Simulation time 3088997704 ps
CPU time 367.03 seconds
Started Aug 02 08:23:41 PM PDT 24
Finished Aug 02 08:29:49 PM PDT 24
Peak memory 608496 kb
Host smart-6c108cf2-2468-467e-a305-b133350a7410
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447033899 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg0.447033899
Directory /workspace/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest

Test location /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.182507279
Short name T163
Test name
Test status
Simulation time 5479180048 ps
CPU time 518.59 seconds
Started Aug 02 08:30:51 PM PDT 24
Finished Aug 02 08:39:30 PM PDT 24
Peak memory 611088 kb
Host smart-a8689c07-e1a6-4be4-b2bc-66c58af026ba
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=182507279 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_program_error.182507279
Directory /workspace/1.chip_sw_lc_ctrl_program_error/latest

Test location /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3838529995
Short name T1371
Test name
Test status
Simulation time 2505751427 ps
CPU time 107.4 seconds
Started Aug 02 08:23:50 PM PDT 24
Finished Aug 02 08:25:38 PM PDT 24
Peak memory 617052 kb
Host smart-828088c7-9cd9-45c9-935b-970bd6e5a754
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s
im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838529995 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES
T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3838529995
Directory /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest

Test location /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.3729418929
Short name T1357
Test name
Test status
Simulation time 49416082215 ps
CPU time 5481.02 seconds
Started Aug 02 08:24:34 PM PDT 24
Finished Aug 02 09:55:56 PM PDT 24
Peak memory 620964 kb
Host smart-9753e05c-3175-41fd-aaa4-388b342e1df7
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de
vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729418929 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c
hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip
_sw_lc_walkthrough_dev.3729418929
Directory /workspace/1.chip_sw_lc_walkthrough_dev/latest

Test location /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.272728730
Short name T1200
Test name
Test status
Simulation time 50517301344 ps
CPU time 5821.11 seconds
Started Aug 02 08:27:21 PM PDT 24
Finished Aug 02 10:04:23 PM PDT 24
Peak memory 621008 kb
Host smart-c77b7b6c-7e78-476f-abc4-68580a38b313
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d
evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272728730 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c
hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip
_sw_lc_walkthrough_prod.272728730
Directory /workspace/1.chip_sw_lc_walkthrough_prod/latest

Test location /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.1340812225
Short name T1069
Test name
Test status
Simulation time 8756033358 ps
CPU time 980.32 seconds
Started Aug 02 08:28:31 PM PDT 24
Finished Aug 02 08:44:52 PM PDT 24
Peak memory 620392 kb
Host smart-fa7b5490-ccbb-47a7-bb7f-5883a4e9f141
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa
lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340812225 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.1340812225
Directory /workspace/1.chip_sw_lc_walkthrough_prodend/latest

Test location /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.4271578632
Short name T238
Test name
Test status
Simulation time 48677073400 ps
CPU time 5756.64 seconds
Started Aug 02 08:24:55 PM PDT 24
Finished Aug 02 10:00:53 PM PDT 24
Peak memory 620576 kb
Host smart-5f1e12ca-5eee-425e-9b9f-9af669d27c20
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de
vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271578632 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c
hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip
_sw_lc_walkthrough_rma.4271578632
Directory /workspace/1.chip_sw_lc_walkthrough_rma/latest

Test location /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.1600656878
Short name T1382
Test name
Test status
Simulation time 22956761416 ps
CPU time 2119.03 seconds
Started Aug 02 08:25:32 PM PDT 24
Finished Aug 02 09:00:51 PM PDT 24
Peak memory 619928 kb
Host smart-1f27f3ec-009c-4e4c-8937-2c1afff3258c
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks
_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1600656878 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testun
locks.1600656878
Directory /workspace/1.chip_sw_lc_walkthrough_testunlocks/latest

Test location /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.3640960626
Short name T1015
Test name
Test status
Simulation time 17333933400 ps
CPU time 3782.91 seconds
Started Aug 02 08:28:10 PM PDT 24
Finished Aug 02 09:31:13 PM PDT 24
Peak memory 610344 kb
Host smart-9ecd314b-3987-4e1c-ae5d-52f1a14fa26e
User root
Command /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_
rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3640960626 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.3640960626
Directory /workspace/1.chip_sw_otbn_ecdsa_op_irq/latest

Test location /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.3055631588
Short name T284
Test name
Test status
Simulation time 18781137523 ps
CPU time 3958.32 seconds
Started Aug 02 08:28:09 PM PDT 24
Finished Aug 02 09:34:08 PM PDT 24
Peak memory 610104 kb
Host smart-b595f598-38a1-43b3-a085-7c3b94681f58
User root
Command /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne
w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3055631588 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.3055631588
Directory /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1319736711
Short name T1300
Test name
Test status
Simulation time 25519032404 ps
CPU time 3448.32 seconds
Started Aug 02 08:31:17 PM PDT 24
Finished Aug 02 09:28:46 PM PDT 24
Peak memory 610288 kb
Host smart-546f9ec1-dfc5-427f-b730-7750c8d4f5f3
User root
Command /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e
cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319736711 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu
ced_freq.1319736711
Directory /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3464618768
Short name T292
Test name
Test status
Simulation time 3930961904 ps
CPU time 569.23 seconds
Started Aug 02 08:28:24 PM PDT 24
Finished Aug 02 08:37:54 PM PDT 24
Peak memory 609776 kb
Host smart-20490d2f-819b-4762-9aef-c8fed819f751
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn
_mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464618768 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.3464618768
Directory /workspace/1.chip_sw_otbn_mem_scramble/latest

Test location /workspace/coverage/default/1.chip_sw_otbn_randomness.3673229845
Short name T1219
Test name
Test status
Simulation time 6363456520 ps
CPU time 996.45 seconds
Started Aug 02 08:27:21 PM PDT 24
Finished Aug 02 08:43:58 PM PDT 24
Peak memory 610276 kb
Host smart-959c19f0-4bb8-420e-9010-368547330781
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3673229845 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.3673229845
Directory /workspace/1.chip_sw_otbn_randomness/latest

Test location /workspace/coverage/default/1.chip_sw_otbn_smoketest.1577453034
Short name T145
Test name
Test status
Simulation time 9244961960 ps
CPU time 2156.6 seconds
Started Aug 02 08:32:50 PM PDT 24
Finished Aug 02 09:08:47 PM PDT 24
Peak memory 610364 kb
Host smart-025b765a-99a5-4e3b-bd3f-d66612c26baf
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577453034 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.chip_sw_otbn_smoketest.1577453034
Directory /workspace/1.chip_sw_otbn_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.865986194
Short name T1054
Test name
Test status
Simulation time 2628097692 ps
CPU time 299.02 seconds
Started Aug 02 08:27:16 PM PDT 24
Finished Aug 02 08:32:15 PM PDT 24
Peak memory 609848 kb
Host smart-dd4e1383-2142-42f5-b5e5-eef32a237990
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865986194 -assert nopostpr
oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_ecc_error_vendor_test.865986194
Directory /workspace/1.chip_sw_otp_ctrl_ecc_error_vendor_test/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3028797095
Short name T1399
Test name
Test status
Simulation time 7945802000 ps
CPU time 1682.29 seconds
Started Aug 02 08:24:58 PM PDT 24
Finished Aug 02 08:53:01 PM PDT 24
Peak memory 610732 kb
Host smart-68efc307-74ba-40d5-815b-15143d592792
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3028797095 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.3028797095
Directory /workspace/1.chip_sw_otp_ctrl_lc_signals_dev/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.906223898
Short name T1355
Test name
Test status
Simulation time 8407548176 ps
CPU time 1285.7 seconds
Started Aug 02 08:25:33 PM PDT 24
Finished Aug 02 08:46:59 PM PDT 24
Peak memory 610720 kb
Host smart-623009cf-db81-446d-8162-4144d26cdccc
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=906223898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.906223898
Directory /workspace/1.chip_sw_otp_ctrl_lc_signals_prod/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.2592003458
Short name T227
Test name
Test status
Simulation time 9285826650 ps
CPU time 1440.07 seconds
Started Aug 02 08:24:32 PM PDT 24
Finished Aug 02 08:48:32 PM PDT 24
Peak memory 610480 kb
Host smart-1f93142d-479d-455b-bd5d-e97f34a59108
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2592003458 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.2592003458
Directory /workspace/1.chip_sw_otp_ctrl_lc_signals_rma/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2934869827
Short name T1065
Test name
Test status
Simulation time 4262740888 ps
CPU time 666.05 seconds
Started Aug 02 08:23:57 PM PDT 24
Finished Aug 02 08:35:03 PM PDT 24
Peak memory 609672 kb
Host smart-5b3ab82d-aaee-4a33-a049-5b152e572b89
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new
_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s
im.tcl +ntb_random_seed=2934869827 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2934869827
Directory /workspace/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.2069728903
Short name T1217
Test name
Test status
Simulation time 3022456742 ps
CPU time 248.59 seconds
Started Aug 02 08:34:07 PM PDT 24
Finished Aug 02 08:38:16 PM PDT 24
Peak memory 609672 kb
Host smart-7640813c-528e-4742-b42b-64b08536cd17
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069728903 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.chip_sw_otp_ctrl_smoketest.2069728903
Directory /workspace/1.chip_sw_otp_ctrl_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.151806825
Short name T156
Test name
Test status
Simulation time 2885980217 ps
CPU time 276.69 seconds
Started Aug 02 08:24:33 PM PDT 24
Finished Aug 02 08:29:10 PM PDT 24
Peak memory 622568 kb
Host smart-8dc740ef-a96c-4851-a1c8-0afde4ef1aa1
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151806825 -assert nopostp
roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.151806825
Directory /workspace/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest

Test location /workspace/coverage/default/1.chip_sw_pattgen_ios.1400765394
Short name T1244
Test name
Test status
Simulation time 3180011192 ps
CPU time 335.73 seconds
Started Aug 02 08:24:07 PM PDT 24
Finished Aug 02 08:29:44 PM PDT 24
Peak memory 612384 kb
Host smart-1249a961-584d-42c7-af27-d52c4d543268
User root
Command /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400765394 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.1400765394
Directory /workspace/1.chip_sw_pattgen_ios/latest

Test location /workspace/coverage/default/1.chip_sw_plic_sw_irq.3530821183
Short name T258
Test name
Test status
Simulation time 3133221012 ps
CPU time 284.03 seconds
Started Aug 02 08:29:59 PM PDT 24
Finished Aug 02 08:34:44 PM PDT 24
Peak memory 609652 kb
Host smart-7eeda957-98db-409a-aca1-4af3d0332267
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530821183 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.chip_sw_plic_sw_irq.3530821183
Directory /workspace/1.chip_sw_plic_sw_irq/latest

Test location /workspace/coverage/default/1.chip_sw_power_idle_load.3770107343
Short name T144
Test name
Test status
Simulation time 3911657260 ps
CPU time 487.23 seconds
Started Aug 02 08:31:24 PM PDT 24
Finished Aug 02 08:39:32 PM PDT 24
Peak memory 609320 kb
Host smart-08c85908-e22a-46b5-b2f1-c7260167d9a9
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770107343 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.chip_sw_power_idle_load.3770107343
Directory /workspace/1.chip_sw_power_idle_load/latest

Test location /workspace/coverage/default/1.chip_sw_power_sleep_load.2949163128
Short name T1000
Test name
Test status
Simulation time 11609897450 ps
CPU time 732.82 seconds
Started Aug 02 08:32:05 PM PDT 24
Finished Aug 02 08:44:18 PM PDT 24
Peak memory 610992 kb
Host smart-5dc2bba0-6c0f-42b8-821e-c4f0136c5c5a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949163128 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.chip_sw_power_sleep_load.2949163128
Directory /workspace/1.chip_sw_power_sleep_load/latest

Test location /workspace/coverage/default/1.chip_sw_power_virus.2685708982
Short name T200
Test name
Test status
Simulation time 6233583688 ps
CPU time 1457.47 seconds
Started Aug 02 08:36:20 PM PDT 24
Finished Aug 02 09:00:37 PM PDT 24
Peak memory 624976 kb
Host smart-232547a6-0edd-4488-90d0-a229b1714f69
User root
Command /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +accelerate_cold_
power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtes
t_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2685708982 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_virus.2685708982
Directory /workspace/1.chip_sw_power_virus/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.1120973503
Short name T1293
Test name
Test status
Simulation time 13853446930 ps
CPU time 1851.27 seconds
Started Aug 02 08:24:17 PM PDT 24
Finished Aug 02 08:55:08 PM PDT 24
Peak memory 611516 kb
Host smart-a2e016ca-1d96-4c55-8b2d-b3f25386187c
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120
973503 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.1120973503
Directory /workspace/1.chip_sw_pwrmgr_all_reset_reqs/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.1039191247
Short name T1294
Test name
Test status
Simulation time 29804295933 ps
CPU time 2509.25 seconds
Started Aug 02 08:30:51 PM PDT 24
Finished Aug 02 09:12:41 PM PDT 24
Peak memory 611192 kb
Host smart-2c705e06-af93-47e7-913a-6a031ca960db
User root
Command /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103
9191247 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.1039191247
Directory /workspace/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2159995190
Short name T705
Test name
Test status
Simulation time 15605264904 ps
CPU time 1483.31 seconds
Started Aug 02 08:26:47 PM PDT 24
Finished Aug 02 08:51:31 PM PDT 24
Peak memory 611644 kb
Host smart-396c802c-2e7f-434e-a7c2-f1e678666281
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2159995190 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2159995190
Directory /workspace/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2036864572
Short name T434
Test name
Test status
Simulation time 23749361272 ps
CPU time 1215.69 seconds
Started Aug 02 08:30:29 PM PDT 24
Finished Aug 02 08:50:45 PM PDT 24
Peak memory 610864 kb
Host smart-b353d378-2889-4c34-947b-bbf5156400cc
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2036864572 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2036864572
Directory /workspace/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.3755198447
Short name T1248
Test name
Test status
Simulation time 9094181064 ps
CPU time 552.16 seconds
Started Aug 02 08:25:27 PM PDT 24
Finished Aug 02 08:34:40 PM PDT 24
Peak memory 610884 kb
Host smart-0476f806-28f0-424e-b392-546fc8b80a31
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755198447 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_por_reset.3755198447
Directory /workspace/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2253011349
Short name T1148
Test name
Test status
Simulation time 6891548816 ps
CPU time 525.12 seconds
Started Aug 02 08:24:39 PM PDT 24
Finished Aug 02 08:33:25 PM PDT 24
Peak memory 617148 kb
Host smart-155a8e8c-10a8-4bdf-bf1a-fb5f6a899148
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2253011349 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2253011349
Directory /workspace/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.1841666517
Short name T1384
Test name
Test status
Simulation time 8513306314 ps
CPU time 681.37 seconds
Started Aug 02 08:24:19 PM PDT 24
Finished Aug 02 08:35:42 PM PDT 24
Peak memory 610840 kb
Host smart-8f7054be-58b7-441e-866e-963087462940
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841666517 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.chip_sw_pwrmgr_full_aon_reset.1841666517
Directory /workspace/1.chip_sw_pwrmgr_full_aon_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.3469168590
Short name T352
Test name
Test status
Simulation time 4029631220 ps
CPU time 491.6 seconds
Started Aug 02 08:31:12 PM PDT 24
Finished Aug 02 08:39:24 PM PDT 24
Peak memory 609740 kb
Host smart-225b9b0d-3409-4a6b-9e93-3206cba37709
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469168590 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.chip_sw_pwrmgr_lowpower_cancel.3469168590
Directory /workspace/1.chip_sw_pwrmgr_lowpower_cancel/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.589095554
Short name T312
Test name
Test status
Simulation time 4173849670 ps
CPU time 311.75 seconds
Started Aug 02 08:24:04 PM PDT 24
Finished Aug 02 08:29:16 PM PDT 24
Peak memory 616356 kb
Host smart-a67fbda0-0787-4d2e-b219-fb75a5a4cbbf
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=589095554 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.589095554
Directory /workspace/1.chip_sw_pwrmgr_main_power_glitch_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3888559312
Short name T1104
Test name
Test status
Simulation time 12566647231 ps
CPU time 1231.31 seconds
Started Aug 02 08:26:32 PM PDT 24
Finished Aug 02 08:47:04 PM PDT 24
Peak memory 611612 kb
Host smart-8706fe38-7bfe-474c-a10f-fc484f46e659
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888559312 -assert nop
ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3888559312
Directory /workspace/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4082832399
Short name T1279
Test name
Test status
Simulation time 7410702446 ps
CPU time 411.79 seconds
Started Aug 02 08:31:10 PM PDT 24
Finished Aug 02 08:38:02 PM PDT 24
Peak memory 610688 kb
Host smart-229a37f1-d0d2-4012-8c65-db5c9c81a2f2
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082832399 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4082832399
Directory /workspace/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.2128058548
Short name T1372
Test name
Test status
Simulation time 5506554674 ps
CPU time 561.56 seconds
Started Aug 02 08:25:47 PM PDT 24
Finished Aug 02 08:35:09 PM PDT 24
Peak memory 610844 kb
Host smart-5e90d591-f8d7-464b-8d97-de91e2daa304
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128058548 -assert nopostpr
oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.2128058548
Directory /workspace/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3129380924
Short name T1111
Test name
Test status
Simulation time 24573455385 ps
CPU time 2665.76 seconds
Started Aug 02 08:27:03 PM PDT 24
Finished Aug 02 09:11:29 PM PDT 24
Peak memory 611600 kb
Host smart-b40661c6-225a-424a-956d-0efaf86b3e65
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3129380924 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3129380924
Directory /workspace/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1090904802
Short name T103
Test name
Test status
Simulation time 22169739990 ps
CPU time 1527.77 seconds
Started Aug 02 08:31:07 PM PDT 24
Finished Aug 02 08:56:36 PM PDT 24
Peak memory 611112 kb
Host smart-5eb0f3de-c0f7-4ef7-99d8-3aef25f369e7
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1090904802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1090904802
Directory /workspace/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3287834753
Short name T1234
Test name
Test status
Simulation time 47242650626 ps
CPU time 3569 seconds
Started Aug 02 08:25:57 PM PDT 24
Finished Aug 02 09:25:28 PM PDT 24
Peak memory 611568 kb
Host smart-49bdf1ba-512c-414b-8db3-b678e4f140c4
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power
_glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287834753 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit
ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_s
leep_power_glitch_reset.3287834753
Directory /workspace/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3071355531
Short name T379
Test name
Test status
Simulation time 7108594532 ps
CPU time 600.65 seconds
Started Aug 02 08:30:37 PM PDT 24
Finished Aug 02 08:40:38 PM PDT 24
Peak memory 610844 kb
Host smart-1a36275b-70fe-44f1-abee-f0dff214f01e
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul
es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3071355531 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sensor_ctrl_deep_s
leep_wake_up.3071355531
Directory /workspace/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.824624383
Short name T719
Test name
Test status
Simulation time 3600852500 ps
CPU time 255.59 seconds
Started Aug 02 08:25:17 PM PDT 24
Finished Aug 02 08:29:34 PM PDT 24
Peak memory 609520 kb
Host smart-4d284e51-c92b-4fe0-8317-c25e0c86e095
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824624383 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_disabled.824624383
Directory /workspace/1.chip_sw_pwrmgr_sleep_disabled/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.1786782450
Short name T704
Test name
Test status
Simulation time 6060727939 ps
CPU time 397.7 seconds
Started Aug 02 08:26:18 PM PDT 24
Finished Aug 02 08:32:56 PM PDT 24
Peak memory 616764 kb
Host smart-3d6861c3-c667-45d6-9c64-7d5cdc532f97
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=1786782450 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_power_glitch_reset.1786782450
Directory /workspace/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3344552727
Short name T125
Test name
Test status
Simulation time 5168507160 ps
CPU time 499.87 seconds
Started Aug 02 08:31:28 PM PDT 24
Finished Aug 02 08:39:49 PM PDT 24
Peak memory 609992 kb
Host smart-1308ad9c-15e2-43c6-a002-269422b7f609
User root
Command /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33445527
27 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3344552727
Directory /workspace/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.722982701
Short name T1308
Test name
Test status
Simulation time 6750327128 ps
CPU time 558.05 seconds
Started Aug 02 08:30:48 PM PDT 24
Finished Aug 02 08:40:06 PM PDT 24
Peak memory 610784 kb
Host smart-6ec9bd95-3b8f-4aca-a46a-2c3b8ea46e9f
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=722982701 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.722982701
Directory /workspace/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.1373352890
Short name T915
Test name
Test status
Simulation time 5233762676 ps
CPU time 349.28 seconds
Started Aug 02 08:32:55 PM PDT 24
Finished Aug 02 08:38:45 PM PDT 24
Peak memory 610480 kb
Host smart-877ece73-08f4-4a1d-baa2-e80d2b129814
User root
Command /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373352890 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.1373352890
Directory /workspace/1.chip_sw_pwrmgr_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.2313969076
Short name T1274
Test name
Test status
Simulation time 6273894695 ps
CPU time 1105.39 seconds
Started Aug 02 08:25:38 PM PDT 24
Finished Aug 02 08:44:04 PM PDT 24
Peak memory 610924 kb
Host smart-9e3ce33c-580a-43d4-b8b1-61cee190f024
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313969076 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.2313969076
Directory /workspace/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.875511970
Short name T329
Test name
Test status
Simulation time 4271875020 ps
CPU time 547.98 seconds
Started Aug 02 08:27:37 PM PDT 24
Finished Aug 02 08:36:45 PM PDT 24
Peak memory 609004 kb
Host smart-e10aa8b0-c068-4c96-837b-e8a66c041b2c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875511970 -assert nop
ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.875511970
Directory /workspace/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.3081457420
Short name T1153
Test name
Test status
Simulation time 4772186806 ps
CPU time 379.46 seconds
Started Aug 02 08:32:23 PM PDT 24
Finished Aug 02 08:38:43 PM PDT 24
Peak memory 610460 kb
Host smart-43cb10d1-105b-416f-9259-8d79631a4fa8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081457420 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.chip_sw_pwrmgr_usbdev_smoketest.3081457420
Directory /workspace/1.chip_sw_pwrmgr_usbdev_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.311851415
Short name T262
Test name
Test status
Simulation time 5333429180 ps
CPU time 433.67 seconds
Started Aug 02 08:27:46 PM PDT 24
Finished Aug 02 08:35:00 PM PDT 24
Peak memory 609140 kb
Host smart-e0ce5bd5-4f5b-40b8-a031-24c382534bc2
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311
851415 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.311851415
Directory /workspace/1.chip_sw_pwrmgr_wdog_reset/latest

Test location /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.1965151606
Short name T280
Test name
Test status
Simulation time 8795731734 ps
CPU time 738.08 seconds
Started Aug 02 08:30:04 PM PDT 24
Finished Aug 02 08:42:23 PM PDT 24
Peak memory 624780 kb
Host smart-22a5454c-5dea-4cd5-867a-66c8675a2161
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965151606 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.1965151606
Directory /workspace/1.chip_sw_rom_ctrl_integrity_check/latest

Test location /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.410749997
Short name T270
Test name
Test status
Simulation time 4229064754 ps
CPU time 519.53 seconds
Started Aug 02 08:25:19 PM PDT 24
Finished Aug 02 08:33:58 PM PDT 24
Peak memory 610260 kb
Host smart-e43dd897-f5de-413a-9c45-9912ec721557
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410749997 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.chip_sw_rstmgr_cpu_info.410749997
Directory /workspace/1.chip_sw_rstmgr_cpu_info/latest

Test location /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.3113740536
Short name T1339
Test name
Test status
Simulation time 5466907936 ps
CPU time 870.77 seconds
Started Aug 02 08:25:29 PM PDT 24
Finished Aug 02 08:40:00 PM PDT 24
Peak memory 642860 kb
Host smart-d1eb382f-a1d2-44cb-8279-416f64544f1c
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3113740536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.3113740536
Directory /workspace/1.chip_sw_rstmgr_rst_cnsty_escalation/latest

Test location /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.730663949
Short name T939
Test name
Test status
Simulation time 2191360856 ps
CPU time 169.36 seconds
Started Aug 02 08:32:43 PM PDT 24
Finished Aug 02 08:35:33 PM PDT 24
Peak memory 609648 kb
Host smart-f72dde53-5245-4563-9992-0b68edc7ca6f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730663949 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.chip_sw_rstmgr_smoketest.730663949
Directory /workspace/1.chip_sw_rstmgr_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.503902570
Short name T917
Test name
Test status
Simulation time 4107024800 ps
CPU time 332.53 seconds
Started Aug 02 08:25:21 PM PDT 24
Finished Aug 02 08:30:54 PM PDT 24
Peak memory 609960 kb
Host smart-8d650fb6-a735-431f-bd10-f6dbfbf894e1
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503902570 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.chip_sw_rstmgr_sw_req.503902570
Directory /workspace/1.chip_sw_rstmgr_sw_req/latest

Test location /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.1481495520
Short name T415
Test name
Test status
Simulation time 2776593248 ps
CPU time 211.08 seconds
Started Aug 02 08:24:38 PM PDT 24
Finished Aug 02 08:28:09 PM PDT 24
Peak memory 609680 kb
Host smart-ccdf56b9-57c5-4dba-b4f7-8171afe106d2
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481495520 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.chip_sw_rstmgr_sw_rst.1481495520
Directory /workspace/1.chip_sw_rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.2198179537
Short name T309
Test name
Test status
Simulation time 3193151384 ps
CPU time 328.24 seconds
Started Aug 02 08:32:27 PM PDT 24
Finished Aug 02 08:37:56 PM PDT 24
Peak memory 609752 kb
Host smart-a0a0a2a6-be9f-45f3-b3da-d1ddabba2ecc
User root
Command /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=2198179537 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.2198179537
Directory /workspace/1.chip_sw_rv_core_ibex_address_translation/latest

Test location /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.185143575
Short name T182
Test name
Test status
Simulation time 2931357054 ps
CPU time 191.63 seconds
Started Aug 02 08:30:57 PM PDT 24
Finished Aug 02 08:34:09 PM PDT 24
Peak memory 609924 kb
Host smart-ad67aecd-6988-4688-9f23-194589359bc5
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185143575 -assert nopostpr
oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.185143575
Directory /workspace/1.chip_sw_rv_core_ibex_icache_invalidate/latest

Test location /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.3870102255
Short name T546
Test name
Test status
Simulation time 4234970000 ps
CPU time 741.22 seconds
Started Aug 02 08:30:42 PM PDT 24
Finished Aug 02 08:43:03 PM PDT 24
Peak memory 609996 kb
Host smart-44f6e52b-f8a3-4f25-bc46-eec8e4460edd
User root
Command /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38701
02255 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.3870102255
Directory /workspace/1.chip_sw_rv_core_ibex_nmi_irq/latest

Test location /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.4207694338
Short name T1235
Test name
Test status
Simulation time 5598732316 ps
CPU time 1019.65 seconds
Started Aug 02 08:28:29 PM PDT 24
Finished Aug 02 08:45:30 PM PDT 24
Peak memory 610008 kb
Host smart-9876d736-7ca1-4f81-a0b5-6622a25a8176
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4207694338 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.4207694338
Directory /workspace/1.chip_sw_rv_core_ibex_rnd/latest

Test location /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.722213614
Short name T1084
Test name
Test status
Simulation time 5964554560 ps
CPU time 482.65 seconds
Started Aug 02 08:31:49 PM PDT 24
Finished Aug 02 08:39:52 PM PDT 24
Peak memory 619580 kb
Host smart-6bcd5cbb-375c-40cf-9acb-95ecbd4f52d0
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722213614 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_wakeup.722213614
Directory /workspace/1.chip_sw_rv_dm_access_after_wakeup/latest

Test location /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1496466254
Short name T318
Test name
Test status
Simulation time 3636726956 ps
CPU time 437.38 seconds
Started Aug 02 08:32:55 PM PDT 24
Finished Aug 02 08:40:13 PM PDT 24
Peak memory 621332 kb
Host smart-a7757f63-1945-451c-a5d4-5afa327f3540
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149646
6254 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1496466254
Directory /workspace/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest

Test location /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.4158799802
Short name T1146
Test name
Test status
Simulation time 2657333374 ps
CPU time 335.69 seconds
Started Aug 02 08:33:30 PM PDT 24
Finished Aug 02 08:39:06 PM PDT 24
Peak memory 609700 kb
Host smart-d131e6f9-8186-49fa-b6bf-9c353b09b1dd
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158799802 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.chip_sw_rv_plic_smoketest.4158799802
Directory /workspace/1.chip_sw_rv_plic_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_rv_timer_irq.3596615584
Short name T261
Test name
Test status
Simulation time 2892530548 ps
CPU time 430.3 seconds
Started Aug 02 08:24:48 PM PDT 24
Finished Aug 02 08:31:58 PM PDT 24
Peak memory 609616 kb
Host smart-99cf10d5-8927-4dfc-821a-b637260e7c39
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596615584 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.chip_sw_rv_timer_irq.3596615584
Directory /workspace/1.chip_sw_rv_timer_irq/latest

Test location /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.1833902531
Short name T288
Test name
Test status
Simulation time 2984634596 ps
CPU time 285.42 seconds
Started Aug 02 08:33:43 PM PDT 24
Finished Aug 02 08:38:28 PM PDT 24
Peak memory 608460 kb
Host smart-91278487-f6f9-4de8-bebe-c0055c6bf120
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833902531 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.chip_sw_rv_timer_smoketest.1833902531
Directory /workspace/1.chip_sw_rv_timer_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3014444544
Short name T132
Test name
Test status
Simulation time 7612613540 ps
CPU time 985.01 seconds
Started Aug 02 08:31:00 PM PDT 24
Finished Aug 02 08:47:25 PM PDT 24
Peak memory 610664 kb
Host smart-7fccb60e-5495-40f9-a889-966d422f7a9c
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30144445
44 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.3014444544
Directory /workspace/1.chip_sw_sensor_ctrl_alert/latest

Test location /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1797368657
Short name T136
Test name
Test status
Simulation time 3161808100 ps
CPU time 201.62 seconds
Started Aug 02 08:31:10 PM PDT 24
Finished Aug 02 08:34:32 PM PDT 24
Peak memory 609588 kb
Host smart-184c0157-44c5-48a9-91ba-e510097e6680
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797368
657 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.1797368657
Directory /workspace/1.chip_sw_sensor_ctrl_status/latest

Test location /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.1330842741
Short name T973
Test name
Test status
Simulation time 9340041878 ps
CPU time 1623.87 seconds
Started Aug 02 08:23:20 PM PDT 24
Finished Aug 02 08:50:25 PM PDT 24
Peak memory 610696 kb
Host smart-658eca3b-7e96-4fda-a4a5-be187f614de4
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330842741 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.chip_sw_sleep_pwm_pulses.1330842741
Directory /workspace/1.chip_sw_sleep_pwm_pulses/latest

Test location /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.2903579201
Short name T107
Test name
Test status
Simulation time 7550463400 ps
CPU time 792.49 seconds
Started Aug 02 08:30:31 PM PDT 24
Finished Aug 02 08:43:44 PM PDT 24
Peak memory 610660 kb
Host smart-4baac584-f653-4c26-ab42-b6e89f9ef425
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903579201 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S
EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sl
eep_sram_ret_contents_no_scramble.2903579201
Directory /workspace/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest

Test location /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.4074248044
Short name T1233
Test name
Test status
Simulation time 7542829240 ps
CPU time 1006.24 seconds
Started Aug 02 08:32:27 PM PDT 24
Finished Aug 02 08:49:14 PM PDT 24
Peak memory 610424 kb
Host smart-06cec379-54a2-49b5-b3ff-f2265847ea71
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074248044 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep
_sram_ret_contents_scramble.4074248044
Directory /workspace/1.chip_sw_sleep_sram_ret_contents_scramble/latest

Test location /workspace/coverage/default/1.chip_sw_spi_device_pass_through.3197107123
Short name T201
Test name
Test status
Simulation time 6226505655 ps
CPU time 625.8 seconds
Started Aug 02 08:23:37 PM PDT 24
Finished Aug 02 08:34:03 PM PDT 24
Peak memory 624780 kb
Host smart-ddd5b054-12ad-4815-8d0e-0f45362158cc
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197107123 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through.3197107123
Directory /workspace/1.chip_sw_spi_device_pass_through/latest

Test location /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.2885875034
Short name T198
Test name
Test status
Simulation time 4632077644 ps
CPU time 529.27 seconds
Started Aug 02 08:25:25 PM PDT 24
Finished Aug 02 08:34:15 PM PDT 24
Peak memory 624840 kb
Host smart-23ccf8f5-0c83-4e01-a7d8-2984f38d52be
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885875034 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.2885875034
Directory /workspace/1.chip_sw_spi_device_pass_through_collision/latest

Test location /workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.4197414336
Short name T59
Test name
Test status
Simulation time 4154481878 ps
CPU time 305.66 seconds
Started Aug 02 08:25:16 PM PDT 24
Finished Aug 02 08:30:22 PM PDT 24
Peak memory 617860 kb
Host smart-fe3f0bd4-9b8d-4e3b-8ad6-7710272dbedc
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197414336 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pinmux_sleep_retention.4197414336
Directory /workspace/1.chip_sw_spi_device_pinmux_sleep_retention/latest

Test location /workspace/coverage/default/1.chip_sw_spi_device_tpm.1401752406
Short name T42
Test name
Test status
Simulation time 3087125529 ps
CPU time 302.24 seconds
Started Aug 02 08:27:02 PM PDT 24
Finished Aug 02 08:32:05 PM PDT 24
Peak memory 618688 kb
Host smart-065e73fd-ad83-4c75-ad4a-7f8ede4a6c05
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401752406 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_tpm.1401752406
Directory /workspace/1.chip_sw_spi_device_tpm/latest

Test location /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.3653269781
Short name T37
Test name
Test status
Simulation time 2708739800 ps
CPU time 312.47 seconds
Started Aug 02 08:23:57 PM PDT 24
Finished Aug 02 08:29:10 PM PDT 24
Peak memory 610184 kb
Host smart-4ff346b0-9a20-48e5-8dc1-06a55738b98e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653269781 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.chip_sw_spi_host_tx_rx.3653269781
Directory /workspace/1.chip_sw_spi_host_tx_rx/latest

Test location /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.2054901045
Short name T181
Test name
Test status
Simulation time 7233093975 ps
CPU time 835.65 seconds
Started Aug 02 08:29:59 PM PDT 24
Finished Aug 02 08:43:55 PM PDT 24
Peak memory 610456 kb
Host smart-a54db05c-ab82-4eab-8bf3-609e0f1ca370
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054901045 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.2054901045
Directory /workspace/1.chip_sw_sram_ctrl_execution_main/latest

Test location /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.3692554385
Short name T108
Test name
Test status
Simulation time 4036574584 ps
CPU time 572.22 seconds
Started Aug 02 08:30:13 PM PDT 24
Finished Aug 02 08:39:46 PM PDT 24
Peak memory 609600 kb
Host smart-8cfd3af3-8400-4c32-9412-22c7131f4bce
User root
Command /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692554385 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr
l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw
_sram_ctrl_scrambled_access.3692554385
Directory /workspace/1.chip_sw_sram_ctrl_scrambled_access/latest

Test location /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2505951264
Short name T664
Test name
Test status
Simulation time 4783210760 ps
CPU time 496.15 seconds
Started Aug 02 08:29:53 PM PDT 24
Finished Aug 02 08:38:10 PM PDT 24
Peak memory 609672 kb
Host smart-7f916a69-98dd-4292-acd5-21559e28d683
User root
Command /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s
w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505951264 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi
p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2505951264
Directory /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.633345369
Short name T291
Test name
Test status
Simulation time 4817630295 ps
CPU time 623.41 seconds
Started Aug 02 08:32:17 PM PDT 24
Finished Aug 02 08:42:41 PM PDT 24
Peak memory 610844 kb
Host smart-f2bd6bea-cb27-4c1f-83f5-a93f6423072f
User root
Command /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk
_70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633345369 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.633345369
Directory /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.2611637483
Short name T1322
Test name
Test status
Simulation time 2691947240 ps
CPU time 270.4 seconds
Started Aug 02 08:33:26 PM PDT 24
Finished Aug 02 08:37:57 PM PDT 24
Peak memory 609788 kb
Host smart-bfb3332c-ea08-4bdc-9c06-e4b514a5f8d7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611637483 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.chip_sw_sram_ctrl_smoketest.2611637483
Directory /workspace/1.chip_sw_sram_ctrl_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.526058732
Short name T1257
Test name
Test status
Simulation time 20279324665 ps
CPU time 3379.69 seconds
Started Aug 02 08:28:02 PM PDT 24
Finished Aug 02 09:24:22 PM PDT 24
Peak memory 610856 kb
Host smart-40a571e5-eebb-4a79-9dc6-f539bbb03019
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526058732 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.526058732
Directory /workspace/1.chip_sw_sysrst_ctrl_ec_rst_l/latest

Test location /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.3533798294
Short name T1306
Test name
Test status
Simulation time 4668782685 ps
CPU time 532.11 seconds
Started Aug 02 08:25:31 PM PDT 24
Finished Aug 02 08:34:25 PM PDT 24
Peak memory 613644 kb
Host smart-d5085880-03fd-4ab2-84d4-94ef12df95b6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533798294 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_in_irq.3533798294
Directory /workspace/1.chip_sw_sysrst_ctrl_in_irq/latest

Test location /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.1478439721
Short name T1309
Test name
Test status
Simulation time 3237832725 ps
CPU time 270.81 seconds
Started Aug 02 08:26:23 PM PDT 24
Finished Aug 02 08:30:55 PM PDT 24
Peak memory 613336 kb
Host smart-d09a9ddb-a029-423b-a727-502cb6a188fb
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478439721 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_inputs.1478439721
Directory /workspace/1.chip_sw_sysrst_ctrl_inputs/latest

Test location /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.3221758748
Short name T1252
Test name
Test status
Simulation time 3630443816 ps
CPU time 536.13 seconds
Started Aug 02 08:30:11 PM PDT 24
Finished Aug 02 08:39:08 PM PDT 24
Peak memory 609368 kb
Host smart-ad0f6d71-25c0-4f27-bd9f-03519e7c09d8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221758748 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_outputs.3221758748
Directory /workspace/1.chip_sw_sysrst_ctrl_outputs/latest

Test location /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.2278702970
Short name T207
Test name
Test status
Simulation time 23697588700 ps
CPU time 1965.21 seconds
Started Aug 02 08:28:05 PM PDT 24
Finished Aug 02 09:00:51 PM PDT 24
Peak memory 613928 kb
Host smart-04a0681b-afcd-4299-9bdd-ef516f8a13b2
User root
Command /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22787029
70 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.2278702970
Directory /workspace/1.chip_sw_sysrst_ctrl_reset/latest

Test location /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3280823466
Short name T40
Test name
Test status
Simulation time 5703619560 ps
CPU time 497.05 seconds
Started Aug 02 08:26:28 PM PDT 24
Finished Aug 02 08:34:46 PM PDT 24
Peak memory 609596 kb
Host smart-a1500c6f-c322-452a-88fe-154131516cd6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280823466 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3280823466
Directory /workspace/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest

Test location /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.1410714520
Short name T357
Test name
Test status
Simulation time 8327806822 ps
CPU time 1580.9 seconds
Started Aug 02 08:25:15 PM PDT 24
Finished Aug 02 08:51:37 PM PDT 24
Peak memory 624508 kb
Host smart-c2954ae5-0c18-4034-945a-3ad4c1cdfdf2
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=1410714520 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.1410714520
Directory /workspace/1.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/1.chip_sw_uart_smoketest.441366610
Short name T920
Test name
Test status
Simulation time 3533687724 ps
CPU time 288.61 seconds
Started Aug 02 08:32:56 PM PDT 24
Finished Aug 02 08:37:45 PM PDT 24
Peak memory 615088 kb
Host smart-bb54fb79-f2fc-4aaf-b4e4-cf99243a0397
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441366610 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.chip_sw_uart_smoketest.441366610
Directory /workspace/1.chip_sw_uart_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_uart_tx_rx.679856892
Short name T1272
Test name
Test status
Simulation time 4773124120 ps
CPU time 544.85 seconds
Started Aug 02 08:24:15 PM PDT 24
Finished Aug 02 08:33:20 PM PDT 24
Peak memory 624224 kb
Host smart-6b28674f-d077-4f71-8111-2651ad6b127b
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679856892 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.679856892
Directory /workspace/1.chip_sw_uart_tx_rx/latest

Test location /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.786814170
Short name T1284
Test name
Test status
Simulation time 12994233977 ps
CPU time 2858.66 seconds
Started Aug 02 08:26:31 PM PDT 24
Finished Aug 02 09:14:10 PM PDT 24
Peak memory 624616 kb
Host smart-b07887d4-4829-419b-a30a-9a6ac084d0f5
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786814170 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba
udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_
alt_clk_freq.786814170
Directory /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3955899518
Short name T967
Test name
Test status
Simulation time 9371897879 ps
CPU time 1280.54 seconds
Started Aug 02 08:23:10 PM PDT 24
Finished Aug 02 08:44:32 PM PDT 24
Peak memory 623308 kb
Host smart-0d2f4cb3-f334-41c6-942b-68ab03b3def3
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955899518 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx
_alt_clk_freq_low_speed.3955899518
Directory /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.2902502851
Short name T314
Test name
Test status
Simulation time 77470355695 ps
CPU time 14906.1 seconds
Started Aug 02 08:24:58 PM PDT 24
Finished Aug 03 12:33:26 AM PDT 24
Peak memory 636136 kb
Host smart-f06f0d1f-5d64-4f3d-bb0a-9ae0107b12c5
User root
Command /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2902502851 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.2902502851
Directory /workspace/1.chip_sw_uart_tx_rx_bootstrap/latest

Test location /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.1129376040
Short name T1391
Test name
Test status
Simulation time 4369759940 ps
CPU time 684.93 seconds
Started Aug 02 08:26:09 PM PDT 24
Finished Aug 02 08:37:35 PM PDT 24
Peak memory 623864 kb
Host smart-d7f247e2-b6a3-4a54-b764-4eacb37a66c3
User root
Command /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129376040 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.1129376040
Directory /workspace/1.chip_sw_uart_tx_rx_idx1/latest

Test location /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.2362130861
Short name T1319
Test name
Test status
Simulation time 4204375110 ps
CPU time 633.34 seconds
Started Aug 02 08:23:19 PM PDT 24
Finished Aug 02 08:33:53 PM PDT 24
Peak memory 623944 kb
Host smart-4be13492-2af1-4a4b-a524-7954eb7c6c5a
User root
Command /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362130861 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.2362130861
Directory /workspace/1.chip_sw_uart_tx_rx_idx2/latest

Test location /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.4172610717
Short name T1280
Test name
Test status
Simulation time 4048478446 ps
CPU time 658.88 seconds
Started Aug 02 08:26:21 PM PDT 24
Finished Aug 02 08:37:20 PM PDT 24
Peak memory 623760 kb
Host smart-190c6bc1-ae0e-47f9-8659-8f6e397420ff
User root
Command /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172610717 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.4172610717
Directory /workspace/1.chip_sw_uart_tx_rx_idx3/latest

Test location /workspace/coverage/default/1.chip_tap_straps_dev.1813495487
Short name T1302
Test name
Test status
Simulation time 3092220416 ps
CPU time 219.21 seconds
Started Aug 02 08:30:58 PM PDT 24
Finished Aug 02 08:34:37 PM PDT 24
Peak memory 624276 kb
Host smart-1e55c7e7-c196-4bfa-8362-f0928184ac58
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:
new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1813495487 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.1813495487
Directory /workspace/1.chip_tap_straps_dev/latest

Test location /workspace/coverage/default/1.chip_tap_straps_prod.4283507397
Short name T1098
Test name
Test status
Simulation time 2712390294 ps
CPU time 200.78 seconds
Started Aug 02 08:30:31 PM PDT 24
Finished Aug 02 08:33:52 PM PDT 24
Peak memory 622012 kb
Host smart-c818b021-17b7-44bc-84fc-5e1dc38d9938
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom
:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4283507397 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.4283507397
Directory /workspace/1.chip_tap_straps_prod/latest

Test location /workspace/coverage/default/1.rom_e2e_asm_init_dev.1025217277
Short name T1193
Test name
Test status
Simulation time 15238678197 ps
CPU time 3426.27 seconds
Started Aug 02 08:40:09 PM PDT 24
Finished Aug 02 09:37:16 PM PDT 24
Peak memory 610284 kb
Host smart-be5f54bd-c36f-4202-a05a-fe6d73a6922b
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025217277 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S
EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rom_e2e_asm_init_dev.1025217277
Directory /workspace/1.rom_e2e_asm_init_dev/latest

Test location /workspace/coverage/default/1.rom_e2e_asm_init_prod.2992804014
Short name T394
Test name
Test status
Simulation time 15408904985 ps
CPU time 4129.91 seconds
Started Aug 02 08:37:49 PM PDT 24
Finished Aug 02 09:46:40 PM PDT 24
Peak memory 610176 kb
Host smart-c9ff76e5-5b39-4ca9-af7c-26abcdb59a0a
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992804014 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_
SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rom_e2e_asm_init_prod.2992804014
Directory /workspace/1.rom_e2e_asm_init_prod/latest

Test location /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.2984237493
Short name T289
Test name
Test status
Simulation time 15929304060 ps
CPU time 4511.85 seconds
Started Aug 02 08:42:00 PM PDT 24
Finished Aug 02 09:57:13 PM PDT 24
Peak memory 610044 kb
Host smart-fc51ebc2-bee8-414d-9c4f-7fc74b3156bb
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984237493 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T
EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_e2e_asm_init_prod_end.2984237493
Directory /workspace/1.rom_e2e_asm_init_prod_end/latest

Test location /workspace/coverage/default/1.rom_e2e_asm_init_rma.1028856785
Short name T286
Test name
Test status
Simulation time 15095961663 ps
CPU time 3906.24 seconds
Started Aug 02 08:41:23 PM PDT 24
Finished Aug 02 09:46:30 PM PDT 24
Peak memory 610328 kb
Host smart-84a1413c-d14e-474b-acbb-3f8b2d67a7db
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028856785 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S
EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rom_e2e_asm_init_rma.1028856785
Directory /workspace/1.rom_e2e_asm_init_rma/latest

Test location /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.1024436438
Short name T1346
Test name
Test status
Simulation time 11244659703 ps
CPU time 2595.53 seconds
Started Aug 02 08:37:17 PM PDT 24
Finished Aug 02 09:20:33 PM PDT 24
Peak memory 611404 kb
Host smart-c12bc024-2119-40e0-915b-6134544fd365
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024436438 -assert nopostproc +UVM_TESTNAME=chip_base_te
st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.rom_e2e_asm_init_test_unlocked0.1024436438
Directory /workspace/1.rom_e2e_asm_init_test_unlocked0/latest

Test location /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.61201462
Short name T931
Test name
Test status
Simulation time 14610664180 ps
CPU time 4004.21 seconds
Started Aug 02 08:38:37 PM PDT 24
Finished Aug 02 09:45:22 PM PDT 24
Peak memory 610108 kb
Host smart-8934f3f2-b81a-4ec2-a032-4dc9d482cc3f
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid
_meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61201462 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_s
w_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init
_rom_ext_invalid_meas.61201462
Directory /workspace/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest

Test location /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.1334664798
Short name T1270
Test name
Test status
Simulation time 15628077690 ps
CPU time 4637.07 seconds
Started Aug 02 08:41:46 PM PDT 24
Finished Aug 02 09:59:04 PM PDT 24
Peak memory 610216 kb
Host smart-a4e4af10-f919-4689-a2c4-c7067e3e05c1
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1:
new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334664798 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_meas.1334664798
Directory /workspace/1.rom_e2e_keymgr_init_rom_ext_meas/latest

Test location /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.385953099
Short name T1202
Test name
Test status
Simulation time 14767857320 ps
CPU time 3751.48 seconds
Started Aug 02 08:41:46 PM PDT 24
Finished Aug 02 09:44:19 PM PDT 24
Peak memory 610024 kb
Host smart-b150d5bb-c898-4a7f-9718-1fe84d6026c8
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas
:1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385953099 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_
no_meas.385953099
Directory /workspace/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest

Test location /workspace/coverage/default/1.rom_e2e_self_hash.3928008035
Short name T1323
Test name
Test status
Simulation time 27073886600 ps
CPU time 6448.74 seconds
Started Aug 02 08:37:08 PM PDT 24
Finished Aug 02 10:24:37 PM PDT 24
Peak memory 609892 kb
Host smart-4f61ee94-1bd0-4f3e-a86b-0388878787c0
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r
ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928008035 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_self_hash.3928008035
Directory /workspace/1.rom_e2e_self_hash/latest

Test location /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.2918484843
Short name T1229
Test name
Test status
Simulation time 14892660160 ps
CPU time 3643.71 seconds
Started Aug 02 08:36:50 PM PDT 24
Finished Aug 02 09:37:34 PM PDT 24
Peak memory 611520 kb
Host smart-6b6b24eb-1770-4a95-a209-ab717f6de370
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne
w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918484843 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu
tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_
shutdown_exception_c.2918484843
Directory /workspace/1.rom_e2e_shutdown_exception_c/latest

Test location /workspace/coverage/default/1.rom_e2e_shutdown_output.3983740643
Short name T1318
Test name
Test status
Simulation time 23840339046 ps
CPU time 3011.56 seconds
Started Aug 02 08:37:16 PM PDT 24
Finished Aug 02 09:27:28 PM PDT 24
Peak memory 611884 kb
Host smart-4f487a01-a891-4438-87e1-0982b9c54a20
User root
Command /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f
lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983740643 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi
p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rom_e2e_shutdown_output.3983740643
Directory /workspace/1.rom_e2e_shutdown_output/latest

Test location /workspace/coverage/default/1.rom_e2e_smoke.3030744841
Short name T1240
Test name
Test status
Simulation time 15005442662 ps
CPU time 3428.95 seconds
Started Aug 02 08:38:07 PM PDT 24
Finished Aug 02 09:35:16 PM PDT 24
Peak memory 609820 kb
Host smart-cbc89589-4f2f-4d07-bbc7-2de9e705fa15
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img
_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to
p/hw/dv/tools/sim.tcl +ntb_random_seed=3030744841 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.3030744841
Directory /workspace/1.rom_e2e_smoke/latest

Test location /workspace/coverage/default/1.rom_e2e_static_critical.1243136746
Short name T1169
Test name
Test status
Simulation time 16898336472 ps
CPU time 4529.46 seconds
Started Aug 02 08:36:45 PM PDT 24
Finished Aug 02 09:52:15 PM PDT 24
Peak memory 610180 kb
Host smart-0e7ccabc-c087-4f0f-8ec4-edc39024e1e2
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul
es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243136746 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_static_critical.1243136746
Directory /workspace/1.rom_e2e_static_critical/latest

Test location /workspace/coverage/default/1.rom_keymgr_functest.4132183832
Short name T220
Test name
Test status
Simulation time 4602149592 ps
CPU time 561.38 seconds
Started Aug 02 08:32:56 PM PDT 24
Finished Aug 02 08:42:18 PM PDT 24
Peak memory 610660 kb
Host smart-78889252-7fc2-4dbf-a443-41be5afe6d46
User root
Command /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132183832 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_keymgr_functest.4132183832
Directory /workspace/1.rom_keymgr_functest/latest

Test location /workspace/coverage/default/1.rom_raw_unlock.3392638447
Short name T1352
Test name
Test status
Simulation time 6242355590 ps
CPU time 276.12 seconds
Started Aug 02 08:34:04 PM PDT 24
Finished Aug 02 08:38:40 PM PDT 24
Peak memory 623920 kb
Host smart-fb2a9861-1b98-42b6-9ab1-60ede1d850b5
User root
Command /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE
xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3392638447 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_raw_unlock.3392638447
Directory /workspace/1.rom_raw_unlock/latest

Test location /workspace/coverage/default/1.rom_volatile_raw_unlock.2771858762
Short name T714
Test name
Test status
Simulation time 1828060856 ps
CPU time 106.52 seconds
Started Aug 02 08:33:00 PM PDT 24
Finished Aug 02 08:34:47 PM PDT 24
Peak memory 616888 kb
Host smart-e8aa6ecb-6165-4e15-b9cf-d75fe84bf208
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1
+sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771858762 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.2771858762
Directory /workspace/1.rom_volatile_raw_unlock/latest

Test location /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.2458968463
Short name T1152
Test name
Test status
Simulation time 5498527419 ps
CPU time 444.74 seconds
Started Aug 02 08:47:52 PM PDT 24
Finished Aug 02 08:55:17 PM PDT 24
Peak memory 620384 kb
Host smart-3e43a5e3-8f61-4ffc-a30a-b94c2481cc45
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458968463 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.chip_sw_lc_ctrl_transition.2458968463
Directory /workspace/10.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.1896502622
Short name T216
Test name
Test status
Simulation time 3927652870 ps
CPU time 541.56 seconds
Started Aug 02 08:47:51 PM PDT 24
Finished Aug 02 08:56:53 PM PDT 24
Peak memory 624484 kb
Host smart-993e2efc-ba50-4a22-8a45-de4f2889f693
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=1896502622 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.1896502622
Directory /workspace/10.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/11.chip_sw_all_escalation_resets.1272189145
Short name T782
Test name
Test status
Simulation time 6269668898 ps
CPU time 643.82 seconds
Started Aug 02 08:46:09 PM PDT 24
Finished Aug 02 08:56:53 PM PDT 24
Peak memory 650584 kb
Host smart-8ad57c8c-95d5-413b-b87e-8169592338b6
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1272189145 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.1272189145
Directory /workspace/11.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.4187657437
Short name T49
Test name
Test status
Simulation time 6748020041 ps
CPU time 535.16 seconds
Started Aug 02 08:48:55 PM PDT 24
Finished Aug 02 08:57:51 PM PDT 24
Peak memory 620380 kb
Host smart-05d471d4-5870-4f5b-900f-db744b92c67a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187657437 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.chip_sw_lc_ctrl_transition.4187657437
Directory /workspace/11.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.2874645303
Short name T1023
Test name
Test status
Simulation time 3845827060 ps
CPU time 609.96 seconds
Started Aug 02 08:47:36 PM PDT 24
Finished Aug 02 08:57:46 PM PDT 24
Peak memory 624504 kb
Host smart-784ca9d6-0b4b-4580-9c0c-36b78380d83d
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=2874645303 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.2874645303
Directory /workspace/11.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.762581642
Short name T1243
Test name
Test status
Simulation time 11977340273 ps
CPU time 722.99 seconds
Started Aug 02 08:48:09 PM PDT 24
Finished Aug 02 09:00:12 PM PDT 24
Peak memory 624212 kb
Host smart-72987690-a563-40a1-abf4-7d8c8a08b022
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762581642 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.chip_sw_lc_ctrl_transition.762581642
Directory /workspace/12.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.1561462456
Short name T1133
Test name
Test status
Simulation time 3885665154 ps
CPU time 546.14 seconds
Started Aug 02 08:47:10 PM PDT 24
Finished Aug 02 08:56:17 PM PDT 24
Peak memory 624516 kb
Host smart-f91bab8b-67f2-43c9-b0a4-fc8aa8e96d7b
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=1561462456 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.1561462456
Directory /workspace/12.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.380347636
Short name T1050
Test name
Test status
Simulation time 3921463704 ps
CPU time 385.56 seconds
Started Aug 02 08:48:07 PM PDT 24
Finished Aug 02 08:54:33 PM PDT 24
Peak memory 649216 kb
Host smart-18f17a91-3620-4427-a976-91c9bfb07837
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380347636 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_s
w_alert_handler_lpg_sleep_mode_alerts.380347636
Directory /workspace/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/13.chip_sw_all_escalation_resets.1181466804
Short name T364
Test name
Test status
Simulation time 5984910478 ps
CPU time 585.11 seconds
Started Aug 02 08:49:15 PM PDT 24
Finished Aug 02 08:59:01 PM PDT 24
Peak memory 616908 kb
Host smart-565a42ae-e176-475d-bdc8-e2f6d39c9ed4
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1181466804 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.1181466804
Directory /workspace/13.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.2359086798
Short name T943
Test name
Test status
Simulation time 7373082382 ps
CPU time 586.97 seconds
Started Aug 02 08:47:22 PM PDT 24
Finished Aug 02 08:57:09 PM PDT 24
Peak memory 620428 kb
Host smart-bec3bed5-b71a-455c-82c4-73e61aa78bec
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359086798 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.chip_sw_lc_ctrl_transition.2359086798
Directory /workspace/13.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.659577236
Short name T1363
Test name
Test status
Simulation time 13416684216 ps
CPU time 2775.85 seconds
Started Aug 02 08:50:04 PM PDT 24
Finished Aug 02 09:36:21 PM PDT 24
Peak memory 624572 kb
Host smart-ccc32b3f-b933-4823-b066-6212fc9d2e33
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=659577236 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.659577236
Directory /workspace/13.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.10970142
Short name T99
Test name
Test status
Simulation time 13832281010 ps
CPU time 1279.19 seconds
Started Aug 02 08:47:41 PM PDT 24
Finished Aug 02 09:09:01 PM PDT 24
Peak memory 620380 kb
Host smart-e7d4a00b-533f-4411-99e9-a08a4dc185c0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10970142 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 14.chip_sw_lc_ctrl_transition.10970142
Directory /workspace/14.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.3124198360
Short name T1075
Test name
Test status
Simulation time 13186555800 ps
CPU time 2557.31 seconds
Started Aug 02 08:48:20 PM PDT 24
Finished Aug 02 09:30:58 PM PDT 24
Peak memory 624496 kb
Host smart-35b77602-30fa-44f6-a0c2-a94594e95525
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3124198360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.3124198360
Directory /workspace/14.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/15.chip_sw_all_escalation_resets.221311382
Short name T1232
Test name
Test status
Simulation time 3843832328 ps
CPU time 512.72 seconds
Started Aug 02 08:51:11 PM PDT 24
Finished Aug 02 08:59:45 PM PDT 24
Peak memory 649716 kb
Host smart-ea070397-94bc-4f4b-83fb-c89d9a467993
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
221311382 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.221311382
Directory /workspace/15.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.3000543921
Short name T977
Test name
Test status
Simulation time 3844717716 ps
CPU time 570.46 seconds
Started Aug 02 08:47:10 PM PDT 24
Finished Aug 02 08:56:41 PM PDT 24
Peak memory 623316 kb
Host smart-15570e92-4439-43e7-9f09-072b4d2b6c1b
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3000543921 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.3000543921
Directory /workspace/15.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.1878051550
Short name T332
Test name
Test status
Simulation time 12854902020 ps
CPU time 2505.16 seconds
Started Aug 02 08:50:38 PM PDT 24
Finished Aug 02 09:32:24 PM PDT 24
Peak memory 624524 kb
Host smart-ffaceaaa-7589-40b7-bf59-d8bbdb28364f
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=1878051550 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.1878051550
Directory /workspace/16.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/17.chip_sw_all_escalation_resets.1893440132
Short name T1061
Test name
Test status
Simulation time 4324680164 ps
CPU time 555.22 seconds
Started Aug 02 08:47:20 PM PDT 24
Finished Aug 02 08:56:35 PM PDT 24
Peak memory 619872 kb
Host smart-59a2d08e-bfd3-453f-91bf-87d72514af1a
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1893440132 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.1893440132
Directory /workspace/17.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.265037904
Short name T1073
Test name
Test status
Simulation time 4280321720 ps
CPU time 548.66 seconds
Started Aug 02 08:47:15 PM PDT 24
Finished Aug 02 08:56:24 PM PDT 24
Peak memory 624584 kb
Host smart-6901bac6-c9f5-498b-977e-585d1c727682
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=265037904 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.265037904
Directory /workspace/17.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2206785467
Short name T779
Test name
Test status
Simulation time 4228715592 ps
CPU time 529.86 seconds
Started Aug 02 08:48:37 PM PDT 24
Finished Aug 02 08:57:27 PM PDT 24
Peak memory 649344 kb
Host smart-14c126a0-a5a1-45e8-8061-df546cb7df4c
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206785467 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2206785467
Directory /workspace/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.2748636162
Short name T1071
Test name
Test status
Simulation time 9233626340 ps
CPU time 1797.46 seconds
Started Aug 02 08:48:13 PM PDT 24
Finished Aug 02 09:18:11 PM PDT 24
Peak memory 624516 kb
Host smart-fb864d38-5ec9-4b13-9707-4c4f091a2b27
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=2748636162 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.2748636162
Directory /workspace/18.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.3054835989
Short name T786
Test name
Test status
Simulation time 3795671230 ps
CPU time 307.7 seconds
Started Aug 02 08:49:40 PM PDT 24
Finished Aug 02 08:54:48 PM PDT 24
Peak memory 649036 kb
Host smart-1a08bd2b-29bb-4ab2-a9bb-ebad0efa9860
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054835989 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3054835989
Directory /workspace/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/19.chip_sw_all_escalation_resets.2559539019
Short name T1095
Test name
Test status
Simulation time 4590383200 ps
CPU time 599.68 seconds
Started Aug 02 08:48:00 PM PDT 24
Finished Aug 02 08:58:00 PM PDT 24
Peak memory 619572 kb
Host smart-47cce1a1-2ca9-40e6-8c6b-da3477107d93
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2559539019 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.2559539019
Directory /workspace/19.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.3071248310
Short name T1137
Test name
Test status
Simulation time 4038675200 ps
CPU time 524.12 seconds
Started Aug 02 08:47:42 PM PDT 24
Finished Aug 02 08:56:27 PM PDT 24
Peak memory 619260 kb
Host smart-643c3574-76e3-45f6-9f96-3d6fb380e66a
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3071248310 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.3071248310
Directory /workspace/19.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/2.chip_jtag_csr_rw.3401988236
Short name T81
Test name
Test status
Simulation time 10613479013 ps
CPU time 1177.98 seconds
Started Aug 02 08:33:24 PM PDT 24
Finished Aug 02 08:53:03 PM PDT 24
Peak memory 608084 kb
Host smart-6991737c-379e-485e-ad5a-d4aa27e8fc33
User root
Command /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401988236 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T
EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.c
hip_jtag_csr_rw.3401988236
Directory /workspace/2.chip_jtag_csr_rw/latest

Test location /workspace/coverage/default/2.chip_jtag_mem_access.3824766876
Short name T83
Test name
Test status
Simulation time 13358730560 ps
CPU time 1293.29 seconds
Started Aug 02 08:33:14 PM PDT 24
Finished Aug 02 08:54:47 PM PDT 24
Peak memory 607948 kb
Host smart-ae691c16-ccb6-4874-b44b-c4da73d26b27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824766876 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_
mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.3
824766876
Directory /workspace/2.chip_jtag_mem_access/latest

Test location /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.622693127
Short name T109
Test name
Test status
Simulation time 3464800478 ps
CPU time 473.2 seconds
Started Aug 02 08:41:06 PM PDT 24
Finished Aug 02 08:49:00 PM PDT 24
Peak memory 619836 kb
Host smart-58b4011a-41fc-4ad1-a49d-9cf0b41c20dd
User root
Command /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6
22693127 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.622693127
Directory /workspace/2.chip_rv_dm_ndm_reset_req/latest

Test location /workspace/coverage/default/2.chip_sival_flash_info_access.3051967721
Short name T1353
Test name
Test status
Simulation time 3457766216 ps
CPU time 357.41 seconds
Started Aug 02 08:33:16 PM PDT 24
Finished Aug 02 08:39:14 PM PDT 24
Peak memory 609968 kb
Host smart-c67b1398-b179-48fb-a4b5-90e9d7da1bdc
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=3051967721 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.3051967721
Directory /workspace/2.chip_sival_flash_info_access/latest

Test location /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1635792655
Short name T111
Test name
Test status
Simulation time 19900460320 ps
CPU time 728.67 seconds
Started Aug 02 08:40:29 PM PDT 24
Finished Aug 02 08:52:38 PM PDT 24
Peak memory 619724 kb
Host smart-18e79a81-b1d8-4f0a-9c74-9a9173e24ec4
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom:
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1635792655 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1635792655
Directory /workspace/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest

Test location /workspace/coverage/default/2.chip_sw_aes_enc.2736705623
Short name T1313
Test name
Test status
Simulation time 2813871268 ps
CPU time 252.63 seconds
Started Aug 02 08:39:04 PM PDT 24
Finished Aug 02 08:43:17 PM PDT 24
Peak memory 609792 kb
Host smart-3f296939-c4b8-4b4a-82e7-dec27f81327f
User root
Command /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736705623 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.2736705623
Directory /workspace/2.chip_sw_aes_enc/latest

Test location /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.4177382301
Short name T945
Test name
Test status
Simulation time 3172673261 ps
CPU time 219.89 seconds
Started Aug 02 08:37:17 PM PDT 24
Finished Aug 02 08:40:57 PM PDT 24
Peak memory 608540 kb
Host smart-0d4b4c2a-ea58-4374-b601-1a3b3b3564df
User root
Command /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177
382301 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.4177382301
Directory /workspace/2.chip_sw_aes_enc_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.2899494502
Short name T995
Test name
Test status
Simulation time 3573074165 ps
CPU time 248.26 seconds
Started Aug 02 08:41:27 PM PDT 24
Finished Aug 02 08:45:35 PM PDT 24
Peak memory 609728 kb
Host smart-db6cc022-3628-4d15-b766-0c1dc42f1d42
User root
Command /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,
test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2899494502 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.2899494502
Directory /workspace/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_aes_entropy.1641505135
Short name T430
Test name
Test status
Simulation time 2544571464 ps
CPU time 227.19 seconds
Started Aug 02 08:37:22 PM PDT 24
Finished Aug 02 08:41:10 PM PDT 24
Peak memory 609692 kb
Host smart-6344557d-c7cd-41db-9339-9969eda4d46c
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641505135 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_entropy.1641505135
Directory /workspace/2.chip_sw_aes_entropy/latest

Test location /workspace/coverage/default/2.chip_sw_aes_idle.1088398126
Short name T1093
Test name
Test status
Simulation time 2805798320 ps
CPU time 265.88 seconds
Started Aug 02 08:36:34 PM PDT 24
Finished Aug 02 08:41:01 PM PDT 24
Peak memory 609612 kb
Host smart-fdb4c118-758e-40e0-897f-104f03b2b6b3
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088398126 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.1088398126
Directory /workspace/2.chip_sw_aes_idle/latest

Test location /workspace/coverage/default/2.chip_sw_aes_masking_off.2146769625
Short name T274
Test name
Test status
Simulation time 3131523371 ps
CPU time 376.69 seconds
Started Aug 02 08:38:52 PM PDT 24
Finished Aug 02 08:45:10 PM PDT 24
Peak memory 610524 kb
Host smart-8e7c655b-be6d-4c8b-861d-71caaf31a7e7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146769625 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.chip_sw_aes_masking_off.2146769625
Directory /workspace/2.chip_sw_aes_masking_off/latest

Test location /workspace/coverage/default/2.chip_sw_aes_smoketest.3270878451
Short name T1022
Test name
Test status
Simulation time 3380051270 ps
CPU time 377.35 seconds
Started Aug 02 08:43:31 PM PDT 24
Finished Aug 02 08:49:49 PM PDT 24
Peak memory 609656 kb
Host smart-71118dd6-b7fc-4235-8965-28ebce7983a0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270878451 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.chip_sw_aes_smoketest.3270878451
Directory /workspace/2.chip_sw_aes_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_entropy.2594249644
Short name T1091
Test name
Test status
Simulation time 3643165317 ps
CPU time 258.62 seconds
Started Aug 02 08:37:35 PM PDT 24
Finished Aug 02 08:41:54 PM PDT 24
Peak memory 609720 kb
Host smart-adeca168-e5e5-4b53-be11-7ec8f7507386
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2594249644 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.2594249644
Directory /workspace/2.chip_sw_alert_handler_entropy/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_escalation.4178188152
Short name T1027
Test name
Test status
Simulation time 4577710242 ps
CPU time 807.99 seconds
Started Aug 02 08:37:59 PM PDT 24
Finished Aug 02 08:51:27 PM PDT 24
Peak memory 619712 kb
Host smart-db4eabfd-3504-4e11-a7fd-c010afe873d4
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test
_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb
_random_seed=4178188152 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.4178188152
Directory /workspace/2.chip_sw_alert_handler_escalation/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.3114825911
Short name T925
Test name
Test status
Simulation time 6805497350 ps
CPU time 1387.26 seconds
Started Aug 02 08:38:56 PM PDT 24
Finished Aug 02 09:02:04 PM PDT 24
Peak memory 610008 kb
Host smart-4d163b1a-d1ab-48ec-b890-ecedde2219d5
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3114825911 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.3114825911
Directory /workspace/2.chip_sw_alert_handler_lpg_clkoff/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.1273351579
Short name T1122
Test name
Test status
Simulation time 7301873264 ps
CPU time 1421.61 seconds
Started Aug 02 08:37:46 PM PDT 24
Finished Aug 02 09:01:28 PM PDT 24
Peak memory 610100 kb
Host smart-90019be8-915f-4a21-88cb-8da1cdea66ef
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules,
test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1273351579 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_togg
le.1273351579
Directory /workspace/2.chip_sw_alert_handler_lpg_reset_toggle/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.17320799
Short name T152
Test name
Test status
Simulation time 12034580084 ps
CPU time 1341.28 seconds
Started Aug 02 08:38:18 PM PDT 24
Finished Aug 02 09:00:40 PM PDT 24
Peak memory 610716 kb
Host smart-aeffc842-7950-42c8-9e01-ed29ddae9c4f
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler
_lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17320799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handl
er_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.chip_sw_alert_handler_lpg_sleep_mode_pings.17320799
Directory /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.1436713999
Short name T389
Test name
Test status
Simulation time 7940907516 ps
CPU time 1371.69 seconds
Started Aug 02 08:40:32 PM PDT 24
Finished Aug 02 09:03:24 PM PDT 24
Peak memory 610056 kb
Host smart-dea59247-1b02-4b4a-9538-1c0b5b536487
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=1436713999 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_ok.1436713999
Directory /workspace/2.chip_sw_alert_handler_ping_ok/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.3481576656
Short name T1222
Test name
Test status
Simulation time 5194442002 ps
CPU time 570.85 seconds
Started Aug 02 08:40:00 PM PDT 24
Finished Aug 02 08:49:32 PM PDT 24
Peak memory 609824 kb
Host smart-924713bc-3ec0-4ecb-a628-0cb9ac637759
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3481576656 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.3481576656
Directory /workspace/2.chip_sw_alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.4276206006
Short name T269
Test name
Test status
Simulation time 254733475100 ps
CPU time 13248.5 seconds
Started Aug 02 08:39:58 PM PDT 24
Finished Aug 03 12:20:48 AM PDT 24
Peak memory 610560 kb
Host smart-5212bd31-f329-4c1a-9106-3b4c45caec24
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n
ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276206006 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.4276206006
Directory /workspace/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest

Test location /workspace/coverage/default/2.chip_sw_alert_test.2268648731
Short name T54
Test name
Test status
Simulation time 2674145710 ps
CPU time 289.41 seconds
Started Aug 02 08:38:26 PM PDT 24
Finished Aug 02 08:43:16 PM PDT 24
Peak memory 610008 kb
Host smart-e32bd716-800b-43ff-a53c-1419c96af511
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268648731 -assert nopostproc +UVM_TESTNAME=chip_ba
se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.chip_sw_alert_test.2268648731
Directory /workspace/2.chip_sw_alert_test/latest

Test location /workspace/coverage/default/2.chip_sw_aon_timer_irq.3988452988
Short name T353
Test name
Test status
Simulation time 4726127488 ps
CPU time 593.42 seconds
Started Aug 02 08:36:29 PM PDT 24
Finished Aug 02 08:46:23 PM PDT 24
Peak memory 610032 kb
Host smart-c0235f95-d295-437f-a43f-51a4caaaa609
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988452988 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.3988452988
Directory /workspace/2.chip_sw_aon_timer_irq/latest

Test location /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3409848496
Short name T1215
Test name
Test status
Simulation time 6542977536 ps
CPU time 515.2 seconds
Started Aug 02 08:37:48 PM PDT 24
Finished Aug 02 08:46:23 PM PDT 24
Peak memory 610528 kb
Host smart-f4195282-adf0-42c4-9791-e3c7eb1532e5
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3409848496 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3409848496
Directory /workspace/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.3876064921
Short name T1079
Test name
Test status
Simulation time 3326412020 ps
CPU time 303.8 seconds
Started Aug 02 08:43:12 PM PDT 24
Finished Aug 02 08:48:16 PM PDT 24
Peak memory 609540 kb
Host smart-9d764422-5905-46e8-9211-1e49ec5fecdc
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876064921 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.chip_sw_aon_timer_smoketest.3876064921
Directory /workspace/2.chip_sw_aon_timer_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.2424832821
Short name T1160
Test name
Test status
Simulation time 10076873556 ps
CPU time 1249.7 seconds
Started Aug 02 08:36:48 PM PDT 24
Finished Aug 02 08:57:38 PM PDT 24
Peak memory 610552 kb
Host smart-9fea0af5-08dc-47aa-b5e4-059617a3c8ba
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2424832821 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.2424832821
Directory /workspace/2.chip_sw_aon_timer_wdog_bite_reset/latest

Test location /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.3963161892
Short name T996
Test name
Test status
Simulation time 5299728798 ps
CPU time 741.83 seconds
Started Aug 02 08:37:28 PM PDT 24
Finished Aug 02 08:49:50 PM PDT 24
Peak memory 610676 kb
Host smart-a50d119c-d845-48b1-8e56-431e70571975
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3963161892 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.3963161892
Directory /workspace/2.chip_sw_aon_timer_wdog_lc_escalate/latest

Test location /workspace/coverage/default/2.chip_sw_ast_clk_outputs.246566229
Short name T1255
Test name
Test status
Simulation time 8403035000 ps
CPU time 1030.34 seconds
Started Aug 02 08:40:51 PM PDT 24
Finished Aug 02 08:58:02 PM PDT 24
Peak memory 617068 kb
Host smart-01e66961-0450-43cc-911d-20bd47ce2815
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246566229 -assert nopos
tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.246566229
Directory /workspace/2.chip_sw_ast_clk_outputs/latest

Test location /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.2979298128
Short name T114
Test name
Test status
Simulation time 20793944557 ps
CPU time 4237.21 seconds
Started Aug 02 08:42:09 PM PDT 24
Finished Aug 02 09:52:47 PM PDT 24
Peak memory 610880 kb
Host smart-2fa24bd1-e018-48c4-a396-ab3fe17b6080
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979298128
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_rst_inputs.2979298128
Directory /workspace/2.chip_sw_ast_clk_rst_inputs/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1003229451
Short name T960
Test name
Test status
Simulation time 7713651940 ps
CPU time 481.46 seconds
Started Aug 02 08:43:53 PM PDT 24
Finished Aug 02 08:51:55 PM PDT 24
Peak memory 621228 kb
Host smart-8325b9d6-cb78-4774-bac0-2de8a7976459
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r
ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim
.tcl +ntb_random_seed=1003229451 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.1003229451
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_lc/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3004902669
Short name T1275
Test name
Test status
Simulation time 3719168376 ps
CPU time 777.94 seconds
Started Aug 02 08:39:10 PM PDT 24
Finished Aug 02 08:52:08 PM PDT 24
Peak memory 612140 kb
Host smart-a11e47ed-c51f-4057-a314-b193b3c8e64c
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004902669 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c
lkmgr_external_clk_src_for_sw_fast_dev.3004902669
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.4205763672
Short name T980
Test name
Test status
Simulation time 3876864218 ps
CPU time 479.59 seconds
Started Aug 02 08:45:09 PM PDT 24
Finished Aug 02 08:53:09 PM PDT 24
Peak memory 613168 kb
Host smart-d8e5962d-4563-4f55-81a9-346b5bff08bc
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205763672 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c
lkmgr_external_clk_src_for_sw_fast_rma.4205763672
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.960530598
Short name T1173
Test name
Test status
Simulation time 4475640352 ps
CPU time 711.48 seconds
Started Aug 02 08:39:47 PM PDT 24
Finished Aug 02 08:51:39 PM PDT 24
Peak memory 613168 kb
Host smart-e46dc907-0da0-46d8-8109-fa3c6894a827
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_
dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960530598 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM
_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.960530598
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3695842147
Short name T1175
Test name
Test status
Simulation time 5258619508 ps
CPU time 694.09 seconds
Started Aug 02 08:39:20 PM PDT 24
Finished Aug 02 08:50:55 PM PDT 24
Peak memory 612136 kb
Host smart-5bdbe12d-d07b-4420-afc0-6875ba77c20e
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695842147 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c
lkmgr_external_clk_src_for_sw_slow_dev.3695842147
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2452319540
Short name T972
Test name
Test status
Simulation time 5058809632 ps
CPU time 900.94 seconds
Started Aug 02 08:43:50 PM PDT 24
Finished Aug 02 08:58:52 PM PDT 24
Peak memory 612900 kb
Host smart-fc572d5a-4060-4e1e-906e-cdca642493e5
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452319540 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c
lkmgr_external_clk_src_for_sw_slow_rma.2452319540
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.4187987542
Short name T1123
Test name
Test status
Simulation time 4922897976 ps
CPU time 710.73 seconds
Started Aug 02 08:39:32 PM PDT 24
Finished Aug 02 08:51:23 PM PDT 24
Peak memory 612952 kb
Host smart-bb0611d7-b676-45ef-96cf-190c4cfa4e33
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_
dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187987542 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV
M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.4187987542
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_jitter.547500642
Short name T116
Test name
Test status
Simulation time 2738904079 ps
CPU time 172.58 seconds
Started Aug 02 08:39:51 PM PDT 24
Finished Aug 02 08:42:43 PM PDT 24
Peak memory 609660 kb
Host smart-2046e191-8121-46c6-bdae-f085631388cf
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547500642 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.chip_sw_clkmgr_jitter.547500642
Directory /workspace/2.chip_sw_clkmgr_jitter/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2791390767
Short name T1242
Test name
Test status
Simulation time 3610704330 ps
CPU time 467.26 seconds
Started Aug 02 08:40:25 PM PDT 24
Finished Aug 02 08:48:12 PM PDT 24
Peak memory 609792 kb
Host smart-62373028-b555-4f59-9a9b-ca322c1e740f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791390767 -assert nopostproc +UV
M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_frequency.2791390767
Directory /workspace/2.chip_sw_clkmgr_jitter_frequency/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3477157454
Short name T1379
Test name
Test status
Simulation time 3022731529 ps
CPU time 175.72 seconds
Started Aug 02 08:42:25 PM PDT 24
Finished Aug 02 08:45:21 PM PDT 24
Peak memory 609656 kb
Host smart-bb3e791a-ac1a-43f9-8eb1-0e4bda21e58c
User root
Command /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477157454 -assert nop
ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.3477157454
Directory /workspace/2.chip_sw_clkmgr_jitter_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3370208467
Short name T1258
Test name
Test status
Simulation time 5304752358 ps
CPU time 449.13 seconds
Started Aug 02 08:39:12 PM PDT 24
Finished Aug 02 08:46:41 PM PDT 24
Peak memory 610468 kb
Host smart-7f3a6813-6a9e-40ba-b457-96440fea7944
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370208467 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.3370208467
Directory /workspace/2.chip_sw_clkmgr_off_aes_trans/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.2561832422
Short name T1199
Test name
Test status
Simulation time 4669247512 ps
CPU time 508.24 seconds
Started Aug 02 08:44:15 PM PDT 24
Finished Aug 02 08:52:44 PM PDT 24
Peak memory 610452 kb
Host smart-1d2eed16-c1a3-4121-82b9-ca1b47b65325
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561832422 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.chip_sw_clkmgr_off_hmac_trans.2561832422
Directory /workspace/2.chip_sw_clkmgr_off_hmac_trans/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.2946683895
Short name T959
Test name
Test status
Simulation time 4323977932 ps
CPU time 478.59 seconds
Started Aug 02 08:40:24 PM PDT 24
Finished Aug 02 08:48:23 PM PDT 24
Peak memory 609288 kb
Host smart-26d38fd3-b057-4956-b849-d1408c32ba94
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946683895 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.chip_sw_clkmgr_off_kmac_trans.2946683895
Directory /workspace/2.chip_sw_clkmgr_off_kmac_trans/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3562141318
Short name T1145
Test name
Test status
Simulation time 5124531632 ps
CPU time 495.65 seconds
Started Aug 02 08:38:56 PM PDT 24
Finished Aug 02 08:47:12 PM PDT 24
Peak memory 610308 kb
Host smart-d5c191c1-8585-4f85-9463-3629e80d2e25
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562141318 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.chip_sw_clkmgr_off_otbn_trans.3562141318
Directory /workspace/2.chip_sw_clkmgr_off_otbn_trans/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.3586513487
Short name T1336
Test name
Test status
Simulation time 12620410960 ps
CPU time 1271.09 seconds
Started Aug 02 08:40:02 PM PDT 24
Finished Aug 02 09:01:14 PM PDT 24
Peak memory 610552 kb
Host smart-7ca014fc-e523-46cb-9ec1-56f3e306a861
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586513487
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.3586513487
Directory /workspace/2.chip_sw_clkmgr_off_peri/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.3206330366
Short name T1177
Test name
Test status
Simulation time 3752958240 ps
CPU time 380.36 seconds
Started Aug 02 08:45:19 PM PDT 24
Finished Aug 02 08:51:39 PM PDT 24
Peak memory 608692 kb
Host smart-dbf04fa9-c91c-49a5-a268-f3dc0907f22a
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206330366 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.3206330366
Directory /workspace/2.chip_sw_clkmgr_reset_frequency/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.452380183
Short name T1024
Test name
Test status
Simulation time 4363225728 ps
CPU time 500.42 seconds
Started Aug 02 08:45:10 PM PDT 24
Finished Aug 02 08:53:31 PM PDT 24
Peak memory 610332 kb
Host smart-07d03b90-a1ab-40d0-a498-62a13e1f9d34
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452380183 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.452380183
Directory /workspace/2.chip_sw_clkmgr_sleep_frequency/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.1161914117
Short name T935
Test name
Test status
Simulation time 2866410860 ps
CPU time 210.07 seconds
Started Aug 02 08:41:55 PM PDT 24
Finished Aug 02 08:45:25 PM PDT 24
Peak memory 609668 kb
Host smart-2b5b0aec-83a3-45c4-ae42-217405d9b84a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161914117 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.chip_sw_clkmgr_smoketest.1161914117
Directory /workspace/2.chip_sw_clkmgr_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.85310597
Short name T1307
Test name
Test status
Simulation time 17067014872 ps
CPU time 3860.53 seconds
Started Aug 02 08:37:53 PM PDT 24
Finished Aug 02 09:42:14 PM PDT 24
Peak memory 609448 kb
Host smart-8621d054-78ab-4520-98bc-3ab87768b07b
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85310597 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency.85310597
Directory /workspace/2.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.2659451771
Short name T964
Test name
Test status
Simulation time 20122894083 ps
CPU time 3129.86 seconds
Started Aug 02 08:42:54 PM PDT 24
Finished Aug 02 09:35:04 PM PDT 24
Peak memory 610452 kb
Host smart-4a78eb32-58ef-458e-8118-8476b04b2525
User root
Command /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_
cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2659451771 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency_reduced_freq.2659451771
Directory /workspace/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.4149164341
Short name T184
Test name
Test status
Simulation time 4054178756 ps
CPU time 457.97 seconds
Started Aug 02 08:40:32 PM PDT 24
Finished Aug 02 08:48:10 PM PDT 24
Peak memory 609308 kb
Host smart-869eb42b-c3a9-4f2d-8b25-1af83183db65
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41491
64341 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.4149164341
Directory /workspace/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest

Test location /workspace/coverage/default/2.chip_sw_csrng_kat_test.190714019
Short name T1343
Test name
Test status
Simulation time 3174602864 ps
CPU time 312.71 seconds
Started Aug 02 08:38:33 PM PDT 24
Finished Aug 02 08:43:46 PM PDT 24
Peak memory 609656 kb
Host smart-fe00dfc6-e130-4eb6-95bb-99b94fc8e5a3
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190714019 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.190714019
Directory /workspace/2.chip_sw_csrng_kat_test/latest

Test location /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.2766137200
Short name T1332
Test name
Test status
Simulation time 5790283201 ps
CPU time 619.19 seconds
Started Aug 02 08:38:28 PM PDT 24
Finished Aug 02 08:48:47 PM PDT 24
Peak memory 611448 kb
Host smart-8ae131ee-8a76-4d5f-be24-ec526ef4c751
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima
ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766137200 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_
lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csr
ng_lc_hw_debug_en_test.2766137200
Directory /workspace/2.chip_sw_csrng_lc_hw_debug_en_test/latest

Test location /workspace/coverage/default/2.chip_sw_csrng_smoketest.1186868646
Short name T1147
Test name
Test status
Simulation time 3308743424 ps
CPU time 285.87 seconds
Started Aug 02 08:43:31 PM PDT 24
Finished Aug 02 08:48:18 PM PDT 24
Peak memory 609584 kb
Host smart-42c6e88d-b0fe-4316-b487-212f5918deac
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186868646 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.chip_sw_csrng_smoketest.1186868646
Directory /workspace/2.chip_sw_csrng_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_data_integrity_escalation.235372737
Short name T281
Test name
Test status
Simulation time 5477914510 ps
CPU time 856.37 seconds
Started Aug 02 08:37:41 PM PDT 24
Finished Aug 02 08:51:58 PM PDT 24
Peak memory 610796 kb
Host smart-6db34fe7-c45f-4ebf-8984-37378d2dec02
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=235372737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.235372737
Directory /workspace/2.chip_sw_data_integrity_escalation/latest

Test location /workspace/coverage/default/2.chip_sw_edn_auto_mode.2494685630
Short name T961
Test name
Test status
Simulation time 4221305172 ps
CPU time 1042.65 seconds
Started Aug 02 08:37:40 PM PDT 24
Finished Aug 02 08:55:03 PM PDT 24
Peak memory 609804 kb
Host smart-69a660d1-7acd-4c51-b0aa-9d3f4e24c98d
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_
build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494685630 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_
auto_mode.2494685630
Directory /workspace/2.chip_sw_edn_auto_mode/latest

Test location /workspace/coverage/default/2.chip_sw_edn_boot_mode.4061924015
Short name T403
Test name
Test status
Simulation time 3154018920 ps
CPU time 553.94 seconds
Started Aug 02 08:39:24 PM PDT 24
Finished Aug 02 08:48:38 PM PDT 24
Peak memory 609772 kb
Host smart-a6b4ad72-f9de-4941-8ff5-0e4ca0e4bc39
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_
build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061924015 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_
boot_mode.4061924015
Directory /workspace/2.chip_sw_edn_boot_mode/latest

Test location /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.155261479
Short name T221
Test name
Test status
Simulation time 6843117944 ps
CPU time 853.89 seconds
Started Aug 02 08:38:45 PM PDT 24
Finished Aug 02 08:52:59 PM PDT 24
Peak memory 609692 kb
Host smart-87d80f40-7ca2-4b93-b8c8-d1aa9ce34660
User root
Command /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed
n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=155261479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.155261479
Directory /workspace/2.chip_sw_edn_entropy_reqs/latest

Test location /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.958868840
Short name T1053
Test name
Test status
Simulation time 5976304475 ps
CPU time 864.38 seconds
Started Aug 02 08:41:48 PM PDT 24
Finished Aug 02 08:56:13 PM PDT 24
Peak memory 610716 kb
Host smart-dea73551-73cd-4136-9c7b-62675d00e0a0
User root
Command /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e
ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958868840 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.958868840
Directory /workspace/2.chip_sw_edn_entropy_reqs_jitter/latest

Test location /workspace/coverage/default/2.chip_sw_edn_kat.377889486
Short name T1059
Test name
Test status
Simulation time 3793235656 ps
CPU time 639.28 seconds
Started Aug 02 08:40:15 PM PDT 24
Finished Aug 02 08:50:55 PM PDT 24
Peak memory 615368 kb
Host smart-95b58381-5996-44bf-9c56-a82c05d9e1e1
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3
+accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377889486 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.chip_sw_edn_kat.377889486
Directory /workspace/2.chip_sw_edn_kat/latest

Test location /workspace/coverage/default/2.chip_sw_edn_sw_mode.3491428243
Short name T1064
Test name
Test status
Simulation time 10609595810 ps
CPU time 2032.53 seconds
Started Aug 02 08:38:10 PM PDT 24
Finished Aug 02 09:12:02 PM PDT 24
Peak memory 610064 kb
Host smart-bafba696-6198-45f6-9c5f-486072cd4105
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491428243 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_sw_mode.3491428243
Directory /workspace/2.chip_sw_edn_sw_mode/latest

Test location /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.2778160271
Short name T1039
Test name
Test status
Simulation time 3116176760 ps
CPU time 292.36 seconds
Started Aug 02 08:37:42 PM PDT 24
Finished Aug 02 08:42:35 PM PDT 24
Peak memory 608432 kb
Host smart-4a184133-b1e9-4ab5-9d43-0703b13ffc25
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27
78160271 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.2778160271
Directory /workspace/2.chip_sw_entropy_src_ast_rng_req/latest

Test location /workspace/coverage/default/2.chip_sw_entropy_src_csrng.4176164559
Short name T344
Test name
Test status
Simulation time 6306736556 ps
CPU time 1187 seconds
Started Aug 02 08:39:40 PM PDT 24
Finished Aug 02 08:59:28 PM PDT 24
Peak memory 610412 kb
Host smart-c1a2c694-0162-4640-84b0-9d416bef3877
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_
csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4176164559 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.4176164559
Directory /workspace/2.chip_sw_entropy_src_csrng/latest

Test location /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.2130864707
Short name T968
Test name
Test status
Simulation time 2011340020 ps
CPU time 187.32 seconds
Started Aug 02 08:36:31 PM PDT 24
Finished Aug 02 08:39:39 PM PDT 24
Peak memory 608488 kb
Host smart-70355adf-cd48-48df-8210-119b9bfa1428
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130864707
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.2130864707
Directory /workspace/2.chip_sw_entropy_src_kat_test/latest

Test location /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.1996535014
Short name T1045
Test name
Test status
Simulation time 2985346724 ps
CPU time 469.9 seconds
Started Aug 02 08:43:36 PM PDT 24
Finished Aug 02 08:51:27 PM PDT 24
Peak memory 609760 kb
Host smart-018d21cd-e1c7-4810-a278-a5af57b9171f
User root
Command /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom:
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1996535014 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.1996535014
Directory /workspace/2.chip_sw_entropy_src_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_example_concurrency.654077185
Short name T1210
Test name
Test status
Simulation time 3122218856 ps
CPU time 207.14 seconds
Started Aug 02 08:33:01 PM PDT 24
Finished Aug 02 08:36:28 PM PDT 24
Peak memory 609704 kb
Host smart-af3c4e08-5aa3-4394-8286-8a19a035a4fb
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654077185 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.chip_sw_example_concurrency.654077185
Directory /workspace/2.chip_sw_example_concurrency/latest

Test location /workspace/coverage/default/2.chip_sw_example_flash.2504141116
Short name T922
Test name
Test status
Simulation time 3143170650 ps
CPU time 256.86 seconds
Started Aug 02 08:33:45 PM PDT 24
Finished Aug 02 08:38:02 PM PDT 24
Peak memory 609692 kb
Host smart-84008a07-5fc5-43a4-959b-ba03a3e2889b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504141116 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.chip_sw_example_flash.2504141116
Directory /workspace/2.chip_sw_example_flash/latest

Test location /workspace/coverage/default/2.chip_sw_example_manufacturer.2325540147
Short name T1386
Test name
Test status
Simulation time 2477396514 ps
CPU time 227.47 seconds
Started Aug 02 08:34:00 PM PDT 24
Finished Aug 02 08:37:47 PM PDT 24
Peak memory 609708 kb
Host smart-c89ebc0e-1aca-4d74-9e7f-c34263db2f00
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325540147 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.chip_sw_example_manufacturer.2325540147
Directory /workspace/2.chip_sw_example_manufacturer/latest

Test location /workspace/coverage/default/2.chip_sw_example_rom.3273325894
Short name T429
Test name
Test status
Simulation time 2613514280 ps
CPU time 154.89 seconds
Started Aug 02 08:33:37 PM PDT 24
Finished Aug 02 08:36:13 PM PDT 24
Peak memory 610164 kb
Host smart-307dcf1b-21bd-413a-b2a0-c271f61d6566
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273325894 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.chip_sw_example_rom.3273325894
Directory /workspace/2.chip_sw_example_rom/latest

Test location /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.2926976785
Short name T1365
Test name
Test status
Simulation time 58327684341 ps
CPU time 10421.7 seconds
Started Aug 02 08:37:03 PM PDT 24
Finished Aug 02 11:30:47 PM PDT 24
Peak memory 624736 kb
Host smart-e3f48b33-08f8-49ca-9c99-46cb29c37271
User root
Command /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new
_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s
im.tcl +ntb_random_seed=2926976785 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_exit_test_unlocked_bootstrap.2926976785
Directory /workspace/2.chip_sw_exit_test_unlocked_bootstrap/latest

Test location /workspace/coverage/default/2.chip_sw_flash_crash_alert.2288265389
Short name T327
Test name
Test status
Simulation time 6103342086 ps
CPU time 831.05 seconds
Started Aug 02 08:40:59 PM PDT 24
Finished Aug 02 08:54:51 PM PDT 24
Peak memory 611240 kb
Host smart-e810edbd-36bb-40c5-9625-c5ae06cc859b
User root
Command /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:
new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool
s/sim.tcl +ntb_random_seed=2288265389 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.2288265389
Directory /workspace/2.chip_sw_flash_crash_alert/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_access.447206575
Short name T390
Test name
Test status
Simulation time 5236616852 ps
CPU time 1231.44 seconds
Started Aug 02 08:35:50 PM PDT 24
Finished Aug 02 08:56:22 PM PDT 24
Peak memory 610064 kb
Host smart-b70fdbce-65c3-4e3f-a5b6-05add7b36266
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447206575 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.chip_sw_flash_ctrl_access.447206575
Directory /workspace/2.chip_sw_flash_ctrl_access/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.939486881
Short name T1366
Test name
Test status
Simulation time 6218474148 ps
CPU time 1118.12 seconds
Started Aug 02 08:34:43 PM PDT 24
Finished Aug 02 08:53:22 PM PDT 24
Peak memory 610224 kb
Host smart-5b18e8f9-07f7-41a4-b613-132b544a4e53
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939486881 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en.939486881
Directory /workspace/2.chip_sw_flash_ctrl_access_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.683555712
Short name T1310
Test name
Test status
Simulation time 7953163905 ps
CPU time 1177.51 seconds
Started Aug 02 08:41:13 PM PDT 24
Finished Aug 02 09:00:51 PM PDT 24
Peak memory 608976 kb
Host smart-3b9069da-eb68-4435-8600-828b890fa263
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683555712 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.683555712
Directory /workspace/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.3727820792
Short name T1249
Test name
Test status
Simulation time 6144108147 ps
CPU time 1042.46 seconds
Started Aug 02 08:35:04 PM PDT 24
Finished Aug 02 08:52:26 PM PDT 24
Peak memory 609316 kb
Host smart-2a0bd1f1-5046-436c-adb2-ad9f2d252ae3
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727820792 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.chip_sw_flash_ctrl_clock_freqs.3727820792
Directory /workspace/2.chip_sw_flash_ctrl_clock_freqs/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.1927789489
Short name T1185
Test name
Test status
Simulation time 4147559960 ps
CPU time 363.81 seconds
Started Aug 02 08:36:01 PM PDT 24
Finished Aug 02 08:42:05 PM PDT 24
Peak memory 609900 kb
Host smart-a76ae364-74f0-4a7d-85c7-5f0e2fec4ab6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927789489 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_idle_low_power.1927789489
Directory /workspace/2.chip_sw_flash_ctrl_idle_low_power/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.299214306
Short name T240
Test name
Test status
Simulation time 4483000432 ps
CPU time 567.04 seconds
Started Aug 02 08:34:32 PM PDT 24
Finished Aug 02 08:43:59 PM PDT 24
Peak memory 609292 kb
Host smart-e981c373-4e51-43a3-ab56-96f455ce8b44
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29
9214306 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_lc_rw_en.299214306
Directory /workspace/2.chip_sw_flash_ctrl_lc_rw_en/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.3117130305
Short name T953
Test name
Test status
Simulation time 5586497360 ps
CPU time 1261.07 seconds
Started Aug 02 08:42:41 PM PDT 24
Finished Aug 02 09:03:42 PM PDT 24
Peak memory 610100 kb
Host smart-cb61b90e-8116-4a9a-be5b-ca7ff35c0bd1
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117130305 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_mem_protection.3117130305
Directory /workspace/2.chip_sw_flash_ctrl_mem_protection/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.36226506
Short name T367
Test name
Test status
Simulation time 4341035570 ps
CPU time 554.75 seconds
Started Aug 02 08:36:52 PM PDT 24
Finished Aug 02 08:46:07 PM PDT 24
Peak memory 608988 kb
Host smart-1e34f718-4f0b-4a79-8087-53ba9314a7b5
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=36226506 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.36226506
Directory /workspace/2.chip_sw_flash_ctrl_ops_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.421480944
Short name T366
Test name
Test status
Simulation time 4851757432 ps
CPU time 661.33 seconds
Started Aug 02 08:43:13 PM PDT 24
Finished Aug 02 08:54:14 PM PDT 24
Peak memory 610080 kb
Host smart-7bae32fa-f629-4902-8e6c-125d39d3aab7
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_
rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=421480944 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.421480944
Directory /workspace/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.3978144449
Short name T1094
Test name
Test status
Simulation time 2730436828 ps
CPU time 332.45 seconds
Started Aug 02 08:41:01 PM PDT 24
Finished Aug 02 08:46:34 PM PDT 24
Peak memory 608628 kb
Host smart-ed5c2056-d10a-4923-9b25-55df2c83c8ea
User root
Command /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978144
449 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_write_clear.3978144449
Directory /workspace/2.chip_sw_flash_ctrl_write_clear/latest

Test location /workspace/coverage/default/2.chip_sw_flash_init.82209650
Short name T1189
Test name
Test status
Simulation time 22258432500 ps
CPU time 1918.29 seconds
Started Aug 02 08:34:06 PM PDT 24
Finished Aug 02 09:06:05 PM PDT 24
Peak memory 613784 kb
Host smart-5e03da6b-9147-444d-9d0f-ff2d305cb327
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82209650 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init.82209650
Directory /workspace/2.chip_sw_flash_init/latest

Test location /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.1377111403
Short name T1253
Test name
Test status
Simulation time 2185027830 ps
CPU time 201.78 seconds
Started Aug 02 08:46:52 PM PDT 24
Finished Aug 02 08:50:14 PM PDT 24
Peak memory 609740 kb
Host smart-eb9a86db-4e42-4ae8-8b3d-16312c5f906f
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket
est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1377111403 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.1377111403
Directory /workspace/2.chip_sw_flash_scrambling_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_gpio.2457910393
Short name T30
Test name
Test status
Simulation time 4419745908 ps
CPU time 444.17 seconds
Started Aug 02 08:35:00 PM PDT 24
Finished Aug 02 08:42:25 PM PDT 24
Peak memory 610040 kb
Host smart-37d4f9f6-32ef-45bb-b627-aae478763164
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457910393 -assert nopostproc +UVM_TESTNAME=chip_bas
e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.chip_sw_gpio.2457910393
Directory /workspace/2.chip_sw_gpio/latest

Test location /workspace/coverage/default/2.chip_sw_gpio_smoketest.3394088557
Short name T27
Test name
Test status
Simulation time 2934374347 ps
CPU time 306.99 seconds
Started Aug 02 08:43:39 PM PDT 24
Finished Aug 02 08:48:46 PM PDT 24
Peak memory 608732 kb
Host smart-106c850a-7e0b-4a79-acb9-131d1a662833
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394088557 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.chip_sw_gpio_smoketest.3394088557
Directory /workspace/2.chip_sw_gpio_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_enc.3246528607
Short name T994
Test name
Test status
Simulation time 2677752012 ps
CPU time 393.61 seconds
Started Aug 02 08:39:19 PM PDT 24
Finished Aug 02 08:45:53 PM PDT 24
Peak memory 609872 kb
Host smart-4fb8dd00-05b1-46d5-9394-4da76e747e0a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246528607 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.chip_sw_hmac_enc.3246528607
Directory /workspace/2.chip_sw_hmac_enc/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_enc_idle.2823809069
Short name T1103
Test name
Test status
Simulation time 2733474514 ps
CPU time 350.16 seconds
Started Aug 02 08:39:20 PM PDT 24
Finished Aug 02 08:45:11 PM PDT 24
Peak memory 609812 kb
Host smart-05c6c3a4-20fa-42e0-b76b-a9be38265047
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823809069 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.chip_sw_hmac_enc_idle.2823809069
Directory /workspace/2.chip_sw_hmac_enc_idle/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.1726650794
Short name T368
Test name
Test status
Simulation time 3100968267 ps
CPU time 378.62 seconds
Started Aug 02 08:38:43 PM PDT 24
Finished Aug 02 08:45:01 PM PDT 24
Peak memory 609728 kb
Host smart-b35890c4-0015-4307-b78a-8cd38433a7c0
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726650794 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en.1726650794
Directory /workspace/2.chip_sw_hmac_enc_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.4075267764
Short name T1402
Test name
Test status
Simulation time 3405510611 ps
CPU time 340.79 seconds
Started Aug 02 08:42:12 PM PDT 24
Finished Aug 02 08:47:53 PM PDT 24
Peak memory 608456 kb
Host smart-7e772577-a2bb-488d-984c-6ce90f8ba0c3
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075267764 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.4075267764
Directory /workspace/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_multistream.3047107053
Short name T1130
Test name
Test status
Simulation time 7838002654 ps
CPU time 1956.14 seconds
Started Aug 02 08:40:46 PM PDT 24
Finished Aug 02 09:13:22 PM PDT 24
Peak memory 610112 kb
Host smart-1d4159e1-e245-4911-9b01-f14e5a06a1c6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047107053 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.chip_sw_hmac_multistream.3047107053
Directory /workspace/2.chip_sw_hmac_multistream/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_oneshot.2474645656
Short name T298
Test name
Test status
Simulation time 3145590816 ps
CPU time 435.5 seconds
Started Aug 02 08:38:23 PM PDT 24
Finished Aug 02 08:45:39 PM PDT 24
Peak memory 608552 kb
Host smart-fa521501-a2e2-4fdf-85b3-c8205dc17d2d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474645656 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.chip_sw_hmac_oneshot.2474645656
Directory /workspace/2.chip_sw_hmac_oneshot/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_smoketest.3069563213
Short name T1239
Test name
Test status
Simulation time 3333084812 ps
CPU time 359.24 seconds
Started Aug 02 08:44:29 PM PDT 24
Finished Aug 02 08:50:28 PM PDT 24
Peak memory 609728 kb
Host smart-bb6bec6b-b5fc-4c60-b211-8d5bc785132f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069563213 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.chip_sw_hmac_smoketest.3069563213
Directory /workspace/2.chip_sw_hmac_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.3592197649
Short name T350
Test name
Test status
Simulation time 4192707906 ps
CPU time 658.26 seconds
Started Aug 02 08:35:09 PM PDT 24
Finished Aug 02 08:46:07 PM PDT 24
Peak memory 609148 kb
Host smart-8a5bda6c-82b7-445f-aae1-8bd59afc3f74
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592197649 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.3592197649
Directory /workspace/2.chip_sw_i2c_device_tx_rx/latest

Test location /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.2105462387
Short name T4
Test name
Test status
Simulation time 5238455772 ps
CPU time 942.91 seconds
Started Aug 02 08:35:17 PM PDT 24
Finished Aug 02 08:51:01 PM PDT 24
Peak memory 609332 kb
Host smart-2940b980-123c-474f-a11c-c1a7825d4f87
User root
Command /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105462387 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx.2105462387
Directory /workspace/2.chip_sw_i2c_host_tx_rx/latest

Test location /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.3845063458
Short name T984
Test name
Test status
Simulation time 4855327036 ps
CPU time 895.34 seconds
Started Aug 02 08:34:10 PM PDT 24
Finished Aug 02 08:49:05 PM PDT 24
Peak memory 610004 kb
Host smart-16e74f04-22d7-45cf-a6ee-364b2bcd764b
User root
Command /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845063458 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.3845063458
Directory /workspace/2.chip_sw_i2c_host_tx_rx_idx1/latest

Test location /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.618986501
Short name T1013
Test name
Test status
Simulation time 5398447584 ps
CPU time 860.72 seconds
Started Aug 02 08:35:19 PM PDT 24
Finished Aug 02 08:49:41 PM PDT 24
Peak memory 609264 kb
Host smart-6b9643bd-4e32-4749-aef1-20fa88a531a5
User root
Command /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618986501 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.618986501
Directory /workspace/2.chip_sw_i2c_host_tx_rx_idx2/latest

Test location /workspace/coverage/default/2.chip_sw_inject_scramble_seed.3634392734
Short name T7
Test name
Test status
Simulation time 65244550559 ps
CPU time 11478.3 seconds
Started Aug 02 08:34:24 PM PDT 24
Finished Aug 02 11:45:44 PM PDT 24
Peak memory 624768 kb
Host smart-8fb86354-7275-484b-8fb4-a39533516e14
User root
Command /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3634392734 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.3634392734
Directory /workspace/2.chip_sw_inject_scramble_seed/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1160991192
Short name T1190
Test name
Test status
Simulation time 12005662548 ps
CPU time 2088.56 seconds
Started Aug 02 08:42:13 PM PDT 24
Finished Aug 02 09:17:02 PM PDT 24
Peak memory 618184 kb
Host smart-3dcb7715-89d0-45ed-a20d-771994dc1ed2
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160
991192 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation.1160991192
Directory /workspace/2.chip_sw_keymgr_key_derivation/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.1207973261
Short name T1036
Test name
Test status
Simulation time 8478096725 ps
CPU time 1169.11 seconds
Started Aug 02 08:39:08 PM PDT 24
Finished Aug 02 08:58:37 PM PDT 24
Peak memory 618044 kb
Host smart-2df340b7-6667-4967-8c50-da7c3aac55ad
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1207973261 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.1207973261
Directory /workspace/2.chip_sw_keymgr_key_derivation_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.222866895
Short name T1164
Test name
Test status
Simulation time 9751923837 ps
CPU time 1521.8 seconds
Started Aug 02 08:44:32 PM PDT 24
Finished Aug 02 09:09:54 PM PDT 24
Peak memory 617944 kb
Host smart-21888b1f-9245-4e86-b7d1-4760cdb65b9d
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=222866895 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en_
reduced_freq.222866895
Directory /workspace/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.1434635348
Short name T235
Test name
Test status
Simulation time 12589624800 ps
CPU time 2203.67 seconds
Started Aug 02 08:38:25 PM PDT 24
Finished Aug 02 09:15:09 PM PDT 24
Peak memory 617952 kb
Host smart-46e547c2-7d88-4352-985f-4cb3cb49a8c9
User root
Command /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1434635348 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.1434635348
Directory /workspace/2.chip_sw_keymgr_key_derivation_prod/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2073893527
Short name T231
Test name
Test status
Simulation time 7185578386 ps
CPU time 1341.9 seconds
Started Aug 02 08:38:15 PM PDT 24
Finished Aug 02 09:00:37 PM PDT 24
Peak memory 611372 kb
Host smart-d83ece55-9b59-479f-bb72-25a904fdb9fa
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207389
3527 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.2073893527
Directory /workspace/2.chip_sw_keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.1198829737
Short name T1277
Test name
Test status
Simulation time 13950853316 ps
CPU time 2825.92 seconds
Started Aug 02 08:40:15 PM PDT 24
Finished Aug 02 09:27:21 PM PDT 24
Peak memory 610416 kb
Host smart-8a8917b9-1c65-47b6-b168-595f5f15d32e
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11988
29737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.1198829737
Directory /workspace/2.chip_sw_keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.2713108241
Short name T232
Test name
Test status
Simulation time 11143658268 ps
CPU time 2895.44 seconds
Started Aug 02 08:39:19 PM PDT 24
Finished Aug 02 09:27:35 PM PDT 24
Peak memory 610916 kb
Host smart-648e1450-741a-40d9-b95c-1422aa42485c
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27131
08241 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.2713108241
Directory /workspace/2.chip_sw_keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_app_rom.1034169331
Short name T1131
Test name
Test status
Simulation time 3395716340 ps
CPU time 207.92 seconds
Started Aug 02 08:38:55 PM PDT 24
Finished Aug 02 08:42:23 PM PDT 24
Peak memory 608416 kb
Host smart-3ccccc72-91ea-459e-a03e-3c370719b99c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034169331 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.chip_sw_kmac_app_rom.1034169331
Directory /workspace/2.chip_sw_kmac_app_rom/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_entropy.2728425401
Short name T1207
Test name
Test status
Simulation time 3332828520 ps
CPU time 328.11 seconds
Started Aug 02 08:34:52 PM PDT 24
Finished Aug 02 08:40:20 PM PDT 24
Peak memory 609796 kb
Host smart-43f40ca7-e6c3-42e0-85ab-cf13195a4ceb
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728425401 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.chip_sw_kmac_entropy.2728425401
Directory /workspace/2.chip_sw_kmac_entropy/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_idle.2625783285
Short name T317
Test name
Test status
Simulation time 2921764632 ps
CPU time 220.18 seconds
Started Aug 02 08:38:54 PM PDT 24
Finished Aug 02 08:42:34 PM PDT 24
Peak memory 608452 kb
Host smart-252482b0-4243-4db3-94d6-577b9c40ac1d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625783285 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.chip_sw_kmac_idle.2625783285
Directory /workspace/2.chip_sw_kmac_idle/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.1143002470
Short name T1271
Test name
Test status
Simulation time 3201375750 ps
CPU time 338.64 seconds
Started Aug 02 08:38:57 PM PDT 24
Finished Aug 02 08:44:36 PM PDT 24
Peak memory 609676 kb
Host smart-f0f58ce0-62cb-42c5-8d65-28632444e8e0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143002470 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.chip_sw_kmac_mode_cshake.1143002470
Directory /workspace/2.chip_sw_kmac_mode_cshake/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.2786182446
Short name T1298
Test name
Test status
Simulation time 2615375320 ps
CPU time 262.91 seconds
Started Aug 02 08:37:45 PM PDT 24
Finished Aug 02 08:42:08 PM PDT 24
Peak memory 609748 kb
Host smart-a3200e10-6766-4069-b102-a409bbaa648c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786182446 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.chip_sw_kmac_mode_kmac.2786182446
Directory /workspace/2.chip_sw_kmac_mode_kmac/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.996907045
Short name T1157
Test name
Test status
Simulation time 3216228358 ps
CPU time 293.82 seconds
Started Aug 02 08:40:48 PM PDT 24
Finished Aug 02 08:45:42 PM PDT 24
Peak memory 609640 kb
Host smart-2c9ffccb-67bb-4ce6-a4d5-7de8aa9f064e
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996907045 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.996907045
Directory /workspace/2.chip_sw_kmac_mode_kmac_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3918102259
Short name T1087
Test name
Test status
Simulation time 3164445311 ps
CPU time 271.02 seconds
Started Aug 02 08:40:57 PM PDT 24
Finished Aug 02 08:45:28 PM PDT 24
Peak memory 608560 kb
Host smart-8e513235-8fed-488b-a31e-c3392c2aff35
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39181022
59 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3918102259
Directory /workspace/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_smoketest.3753044566
Short name T102
Test name
Test status
Simulation time 3309482440 ps
CPU time 305.7 seconds
Started Aug 02 08:44:56 PM PDT 24
Finished Aug 02 08:50:02 PM PDT 24
Peak memory 609700 kb
Host smart-fbf93386-a2c4-4ede-b3d2-d9bc762fc4a5
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753044566 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.chip_sw_kmac_smoketest.3753044566
Directory /workspace/2.chip_sw_kmac_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.2989164311
Short name T1105
Test name
Test status
Simulation time 3300349386 ps
CPU time 283.22 seconds
Started Aug 02 08:35:28 PM PDT 24
Finished Aug 02 08:40:11 PM PDT 24
Peak memory 609688 kb
Host smart-0dedb06b-ab28-4fab-a308-6ffe4fb129e0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989164311 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.chip_sw_lc_ctrl_otp_hw_cfg0.2989164311
Directory /workspace/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest

Test location /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.4156142389
Short name T165
Test name
Test status
Simulation time 4947969902 ps
CPU time 609.43 seconds
Started Aug 02 08:40:08 PM PDT 24
Finished Aug 02 08:50:18 PM PDT 24
Peak memory 611084 kb
Host smart-88f338bb-e40f-4689-9b76-0261abe968ef
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4156142389 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_program_error.4156142389
Directory /workspace/2.chip_sw_lc_ctrl_program_error/latest

Test location /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.3440114666
Short name T978
Test name
Test status
Simulation time 10357824317 ps
CPU time 759.36 seconds
Started Aug 02 08:36:22 PM PDT 24
Finished Aug 02 08:49:02 PM PDT 24
Peak memory 620412 kb
Host smart-8fe604cb-4c95-430e-a407-94ad6ce96038
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440114666 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_transition.3440114666
Directory /workspace/2.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.3339148685
Short name T158
Test name
Test status
Simulation time 2439356211 ps
CPU time 116.9 seconds
Started Aug 02 08:41:21 PM PDT 24
Finished Aug 02 08:43:18 PM PDT 24
Peak memory 616996 kb
Host smart-e21da3ef-669e-449f-9176-f69f3599e8e8
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes
t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3339148685 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.3339148685
Directory /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest

Test location /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3632629708
Short name T1218
Test name
Test status
Simulation time 2555327310 ps
CPU time 120.24 seconds
Started Aug 02 08:37:06 PM PDT 24
Finished Aug 02 08:39:07 PM PDT 24
Peak memory 617832 kb
Host smart-bfc56bb4-2e5b-459a-9d5f-f61e3d938f5f
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s
im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632629708 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES
T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3632629708
Directory /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest

Test location /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.3133937687
Short name T237
Test name
Test status
Simulation time 50793205004 ps
CPU time 5350.28 seconds
Started Aug 02 08:36:48 PM PDT 24
Finished Aug 02 10:05:59 PM PDT 24
Peak memory 619532 kb
Host smart-693a6e11-2da0-4381-8a85-24f243730951
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d
evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133937687 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chi
p_sw_lc_walkthrough_prod.3133937687
Directory /workspace/2.chip_sw_lc_walkthrough_prod/latest

Test location /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.242462823
Short name T1383
Test name
Test status
Simulation time 11537105920 ps
CPU time 1049.54 seconds
Started Aug 02 08:36:11 PM PDT 24
Finished Aug 02 08:53:41 PM PDT 24
Peak memory 620292 kb
Host smart-fb00c659-ba47-451c-9c58-426f09923f30
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa
lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=242462823 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.242462823
Directory /workspace/2.chip_sw_lc_walkthrough_prodend/latest

Test location /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.308970586
Short name T1395
Test name
Test status
Simulation time 44691163882 ps
CPU time 4480.6 seconds
Started Aug 02 08:41:17 PM PDT 24
Finished Aug 02 09:55:59 PM PDT 24
Peak memory 615788 kb
Host smart-ded28f44-da54-41e5-8f8d-27e3e5c287fa
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de
vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308970586 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch
ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_
sw_lc_walkthrough_rma.308970586
Directory /workspace/2.chip_sw_lc_walkthrough_rma/latest

Test location /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.4100641281
Short name T1403
Test name
Test status
Simulation time 24388320464 ps
CPU time 1776.01 seconds
Started Aug 02 08:38:53 PM PDT 24
Finished Aug 02 09:08:29 PM PDT 24
Peak memory 619952 kb
Host smart-5b2d2767-fa6c-41d2-881d-f5b0c22c594e
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks
_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4100641281 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testun
locks.4100641281
Directory /workspace/2.chip_sw_lc_walkthrough_testunlocks/latest

Test location /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.3987367271
Short name T1010
Test name
Test status
Simulation time 17481846216 ps
CPU time 3262.31 seconds
Started Aug 02 08:37:11 PM PDT 24
Finished Aug 02 09:31:34 PM PDT 24
Peak memory 610284 kb
Host smart-c42322f9-9a54-4e10-a5ab-9b0c024b4934
User root
Command /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_
rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3987367271 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.3987367271
Directory /workspace/2.chip_sw_otbn_ecdsa_op_irq/latest

Test location /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3619452545
Short name T1138
Test name
Test status
Simulation time 19308218158 ps
CPU time 3785.41 seconds
Started Aug 02 08:38:37 PM PDT 24
Finished Aug 02 09:41:43 PM PDT 24
Peak memory 610136 kb
Host smart-9020f432-559b-4418-a5dc-120ad6f1a92a
User root
Command /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne
w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3619452545 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3619452545
Directory /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2994795607
Short name T146
Test name
Test status
Simulation time 24575537315 ps
CPU time 5308.06 seconds
Started Aug 02 08:47:11 PM PDT 24
Finished Aug 02 10:15:40 PM PDT 24
Peak memory 610152 kb
Host smart-cfe95d3b-206b-4e81-8f08-2e19baa6d1d4
User root
Command /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e
cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994795607 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu
ced_freq.2994795607
Directory /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.605048286
Short name T1330
Test name
Test status
Simulation time 3453779010 ps
CPU time 474.66 seconds
Started Aug 02 08:37:44 PM PDT 24
Finished Aug 02 08:45:39 PM PDT 24
Peak memory 609816 kb
Host smart-0d28fda0-459e-4dd3-a56d-fc12e042ea90
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn
_mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605048286 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.605048286
Directory /workspace/2.chip_sw_otbn_mem_scramble/latest

Test location /workspace/coverage/default/2.chip_sw_otbn_randomness.160021235
Short name T1375
Test name
Test status
Simulation time 6068552152 ps
CPU time 1022.77 seconds
Started Aug 02 08:38:23 PM PDT 24
Finished Aug 02 08:55:26 PM PDT 24
Peak memory 610300 kb
Host smart-13c67367-40bf-4cb6-9ade-c4b5214ac675
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=160021235 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.160021235
Directory /workspace/2.chip_sw_otbn_randomness/latest

Test location /workspace/coverage/default/2.chip_sw_otbn_smoketest.3258261136
Short name T89
Test name
Test status
Simulation time 6729439744 ps
CPU time 1253.72 seconds
Started Aug 02 08:42:25 PM PDT 24
Finished Aug 02 09:03:19 PM PDT 24
Peak memory 610196 kb
Host smart-faab5ab4-33ec-4b40-8b02-e1df9de95b1d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258261136 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.chip_sw_otbn_smoketest.3258261136
Directory /workspace/2.chip_sw_otbn_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.3183441023
Short name T929
Test name
Test status
Simulation time 2958292750 ps
CPU time 265.26 seconds
Started Aug 02 08:35:42 PM PDT 24
Finished Aug 02 08:40:07 PM PDT 24
Peak memory 608792 kb
Host smart-85aabcc5-6e9a-4d2b-8b9b-b1e5d28cb012
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183441023 -assert nopostp
roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_ecc_error_vendor_test.3183441023
Directory /workspace/2.chip_sw_otp_ctrl_ecc_error_vendor_test/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.435590275
Short name T1262
Test name
Test status
Simulation time 7897570044 ps
CPU time 1212.03 seconds
Started Aug 02 08:38:28 PM PDT 24
Finished Aug 02 08:58:40 PM PDT 24
Peak memory 610700 kb
Host smart-8c1f9955-6862-4140-873f-01aff1ffa835
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=435590275 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.435590275
Directory /workspace/2.chip_sw_otp_ctrl_lc_signals_dev/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.906237149
Short name T162
Test name
Test status
Simulation time 6878074760 ps
CPU time 1325.04 seconds
Started Aug 02 08:40:54 PM PDT 24
Finished Aug 02 09:03:00 PM PDT 24
Peak memory 610452 kb
Host smart-898bb18a-94b4-4bbf-b15d-466e9e9da0ed
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=906237149 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.906237149
Directory /workspace/2.chip_sw_otp_ctrl_lc_signals_prod/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.2852912723
Short name T225
Test name
Test status
Simulation time 6120766904 ps
CPU time 1329.98 seconds
Started Aug 02 08:40:29 PM PDT 24
Finished Aug 02 09:02:39 PM PDT 24
Peak memory 610724 kb
Host smart-9487cf30-d93e-4724-9c5e-09e60ec9865e
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2852912723 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.2852912723
Directory /workspace/2.chip_sw_otp_ctrl_lc_signals_rma/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3061935772
Short name T1158
Test name
Test status
Simulation time 5037196734 ps
CPU time 732.54 seconds
Started Aug 02 08:36:43 PM PDT 24
Finished Aug 02 08:48:56 PM PDT 24
Peak memory 609876 kb
Host smart-baedf55e-bd61-43e8-ad54-1f6d5a829238
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new
_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s
im.tcl +ntb_random_seed=3061935772 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3061935772
Directory /workspace/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.3040490285
Short name T1080
Test name
Test status
Simulation time 2844794326 ps
CPU time 263.56 seconds
Started Aug 02 08:43:41 PM PDT 24
Finished Aug 02 08:48:05 PM PDT 24
Peak memory 609668 kb
Host smart-6f3cb1de-fa13-47f3-9f09-6f38c1b3e2a5
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040490285 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.chip_sw_otp_ctrl_smoketest.3040490285
Directory /workspace/2.chip_sw_otp_ctrl_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_pattgen_ios.3371126574
Short name T360
Test name
Test status
Simulation time 2701760840 ps
CPU time 335.73 seconds
Started Aug 02 08:35:08 PM PDT 24
Finished Aug 02 08:40:46 PM PDT 24
Peak memory 612520 kb
Host smart-be105420-f47e-4326-a55a-6c2ac1e8c6aa
User root
Command /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371126574 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.3371126574
Directory /workspace/2.chip_sw_pattgen_ios/latest

Test location /workspace/coverage/default/2.chip_sw_plic_sw_irq.3681610594
Short name T257
Test name
Test status
Simulation time 2491470008 ps
CPU time 352.03 seconds
Started Aug 02 08:41:02 PM PDT 24
Finished Aug 02 08:46:55 PM PDT 24
Peak memory 608468 kb
Host smart-ec7c0e5f-4806-422a-87f6-268ed4ce5a3f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681610594 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.chip_sw_plic_sw_irq.3681610594
Directory /workspace/2.chip_sw_plic_sw_irq/latest

Test location /workspace/coverage/default/2.chip_sw_power_idle_load.3900340546
Short name T1107
Test name
Test status
Simulation time 4578012634 ps
CPU time 673.29 seconds
Started Aug 02 08:42:17 PM PDT 24
Finished Aug 02 08:53:31 PM PDT 24
Peak memory 609172 kb
Host smart-eecb7673-d71c-4212-8c00-d2462677895d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900340546 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.chip_sw_power_idle_load.3900340546
Directory /workspace/2.chip_sw_power_idle_load/latest

Test location /workspace/coverage/default/2.chip_sw_power_sleep_load.2727832348
Short name T1033
Test name
Test status
Simulation time 10244739232 ps
CPU time 619 seconds
Started Aug 02 08:42:34 PM PDT 24
Finished Aug 02 08:52:53 PM PDT 24
Peak memory 610984 kb
Host smart-2fe73874-f8d4-484a-876d-7528e75657a8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727832348 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.2727832348
Directory /workspace/2.chip_sw_power_sleep_load/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.1419760561
Short name T374
Test name
Test status
Simulation time 11126835566 ps
CPU time 1482.11 seconds
Started Aug 02 08:37:47 PM PDT 24
Finished Aug 02 09:02:29 PM PDT 24
Peak memory 611632 kb
Host smart-c68b2ef1-3407-40ff-92c0-5685968c8ee5
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419
760561 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.1419760561
Directory /workspace/2.chip_sw_pwrmgr_all_reset_reqs/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1216412944
Short name T1004
Test name
Test status
Simulation time 23865511256 ps
CPU time 1662.65 seconds
Started Aug 02 08:40:03 PM PDT 24
Finished Aug 02 09:07:47 PM PDT 24
Peak memory 611064 kb
Host smart-d5c87640-25fb-4d80-b1c2-9e97e063570d
User root
Command /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121
6412944 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.1216412944
Directory /workspace/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.824086173
Short name T1245
Test name
Test status
Simulation time 16249411473 ps
CPU time 1530.92 seconds
Started Aug 02 08:40:19 PM PDT 24
Finished Aug 02 09:05:50 PM PDT 24
Peak memory 611296 kb
Host smart-79042cb8-6cba-4ef1-815d-abe225b1388c
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=824086173 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.824086173
Directory /workspace/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.2179560184
Short name T391
Test name
Test status
Simulation time 8483625556 ps
CPU time 745.15 seconds
Started Aug 02 08:36:41 PM PDT 24
Finished Aug 02 08:49:07 PM PDT 24
Peak memory 610844 kb
Host smart-acab4c6d-05e3-4646-b90d-2fba493ad502
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179560184 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_por_reset.2179560184
Directory /workspace/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3823631459
Short name T424
Test name
Test status
Simulation time 6336295318 ps
CPU time 419.57 seconds
Started Aug 02 08:37:22 PM PDT 24
Finished Aug 02 08:44:22 PM PDT 24
Peak memory 616312 kb
Host smart-51b5f335-be79-4a69-a148-f3a54907414e
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3823631459 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3823631459
Directory /workspace/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2976068557
Short name T1297
Test name
Test status
Simulation time 9118720955 ps
CPU time 620.42 seconds
Started Aug 02 08:37:33 PM PDT 24
Finished Aug 02 08:47:53 PM PDT 24
Peak memory 610908 kb
Host smart-a9dcccc4-766e-462f-a3fb-23d4b1fd5131
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976068557 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.chip_sw_pwrmgr_full_aon_reset.2976068557
Directory /workspace/2.chip_sw_pwrmgr_full_aon_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.1903801691
Short name T354
Test name
Test status
Simulation time 4800005734 ps
CPU time 422.31 seconds
Started Aug 02 08:40:51 PM PDT 24
Finished Aug 02 08:47:54 PM PDT 24
Peak memory 609380 kb
Host smart-9ade1d03-2794-4405-83e1-ac4eaa9e3108
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903801691 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.chip_sw_pwrmgr_lowpower_cancel.1903801691
Directory /workspace/2.chip_sw_pwrmgr_lowpower_cancel/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.560704184
Short name T1224
Test name
Test status
Simulation time 5361428180 ps
CPU time 503.32 seconds
Started Aug 02 08:36:10 PM PDT 24
Finished Aug 02 08:44:34 PM PDT 24
Peak memory 616648 kb
Host smart-7a422b27-38ad-43ff-b14a-2d7da34a4423
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=560704184 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.560704184
Directory /workspace/2.chip_sw_pwrmgr_main_power_glitch_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4137006231
Short name T1136
Test name
Test status
Simulation time 10301621887 ps
CPU time 1121.02 seconds
Started Aug 02 08:36:19 PM PDT 24
Finished Aug 02 08:55:00 PM PDT 24
Peak memory 611488 kb
Host smart-f30447da-95dd-409c-a3ca-e53f66072d2e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137006231 -assert nop
ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4137006231
Directory /workspace/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4204417385
Short name T433
Test name
Test status
Simulation time 7674276092 ps
CPU time 424.04 seconds
Started Aug 02 08:41:37 PM PDT 24
Finished Aug 02 08:48:41 PM PDT 24
Peak memory 610744 kb
Host smart-ab6964f1-ba5a-4457-a318-f347ffc49728
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204417385 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4204417385
Directory /workspace/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.2376783435
Short name T1089
Test name
Test status
Simulation time 5572568686 ps
CPU time 845.23 seconds
Started Aug 02 08:40:03 PM PDT 24
Finished Aug 02 08:54:08 PM PDT 24
Peak memory 610832 kb
Host smart-ed875c7b-b273-4e58-8d33-4f987ac0341a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376783435 -assert nopostpr
oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.2376783435
Directory /workspace/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1735131167
Short name T104
Test name
Test status
Simulation time 21421284032 ps
CPU time 1284.51 seconds
Started Aug 02 08:40:30 PM PDT 24
Finished Aug 02 09:01:55 PM PDT 24
Peak memory 611116 kb
Host smart-d7400e6b-6c9a-4062-9613-adfaa68b3874
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1735131167 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1735131167
Directory /workspace/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2988681278
Short name T1362
Test name
Test status
Simulation time 42221817185 ps
CPU time 3411.57 seconds
Started Aug 02 08:38:11 PM PDT 24
Finished Aug 02 09:35:03 PM PDT 24
Peak memory 613132 kb
Host smart-93b4d2c2-97af-41ff-bc61-2343f41ed63c
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power
_glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988681278 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit
ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_s
leep_power_glitch_reset.2988681278
Directory /workspace/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.295401902
Short name T378
Test name
Test status
Simulation time 5802016460 ps
CPU time 404.25 seconds
Started Aug 02 08:40:46 PM PDT 24
Finished Aug 02 08:47:30 PM PDT 24
Peak memory 611200 kb
Host smart-60621485-d3d5-4c21-8793-c1b304161794
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul
es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=295401902 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sensor_ctrl_deep_sl
eep_wake_up.295401902
Directory /workspace/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.723582272
Short name T2
Test name
Test status
Simulation time 3627184248 ps
CPU time 378.04 seconds
Started Aug 02 08:37:49 PM PDT 24
Finished Aug 02 08:44:07 PM PDT 24
Peak memory 609776 kb
Host smart-c7d9f521-ee95-4338-8ef9-08d0858efb32
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723582272 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_disabled.723582272
Directory /workspace/2.chip_sw_pwrmgr_sleep_disabled/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.159269569
Short name T1056
Test name
Test status
Simulation time 5991402723 ps
CPU time 369.32 seconds
Started Aug 02 08:37:33 PM PDT 24
Finished Aug 02 08:43:43 PM PDT 24
Peak memory 617568 kb
Host smart-43877394-b5c4-48c0-b0b0-dc08b86d41a0
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=159269569 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_power_glitch_reset.159269569
Directory /workspace/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1532150821
Short name T126
Test name
Test status
Simulation time 5237430736 ps
CPU time 518.96 seconds
Started Aug 02 08:40:40 PM PDT 24
Finished Aug 02 08:49:19 PM PDT 24
Peak memory 610020 kb
Host smart-328fa41f-6895-41a0-8bbc-aad13dc4fb05
User root
Command /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15321508
21 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1532150821
Directory /workspace/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3794133738
Short name T1247
Test name
Test status
Simulation time 6185892416 ps
CPU time 526.05 seconds
Started Aug 02 08:41:56 PM PDT 24
Finished Aug 02 08:50:42 PM PDT 24
Peak memory 610556 kb
Host smart-7443b2cc-7e7c-44cc-a3a0-c0f2f4852881
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3794133738 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.3794133738
Directory /workspace/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.3997749102
Short name T914
Test name
Test status
Simulation time 6405327720 ps
CPU time 507.11 seconds
Started Aug 02 08:44:33 PM PDT 24
Finished Aug 02 08:53:01 PM PDT 24
Peak memory 610184 kb
Host smart-5a2d494b-fe8c-4400-9b16-63f85ac92b53
User root
Command /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997749102 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.3997749102
Directory /workspace/2.chip_sw_pwrmgr_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.1957265984
Short name T263
Test name
Test status
Simulation time 7515858260 ps
CPU time 1185.88 seconds
Started Aug 02 08:36:13 PM PDT 24
Finished Aug 02 08:56:00 PM PDT 24
Peak memory 610420 kb
Host smart-155d18ee-1ff5-444f-8e17-3464022ff5df
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957265984 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.1957265984
Directory /workspace/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.1198594647
Short name T989
Test name
Test status
Simulation time 5182988018 ps
CPU time 622.24 seconds
Started Aug 02 08:39:00 PM PDT 24
Finished Aug 02 08:49:22 PM PDT 24
Peak memory 610536 kb
Host smart-bfb390f6-33a1-4feb-a087-6607258835d7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198594647 -assert no
postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.1198594647
Directory /workspace/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.2512318770
Short name T1301
Test name
Test status
Simulation time 5606075860 ps
CPU time 530.42 seconds
Started Aug 02 08:43:11 PM PDT 24
Finished Aug 02 08:52:01 PM PDT 24
Peak memory 610116 kb
Host smart-538d44e9-e465-4d37-89be-8d5d437d4ea9
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512318770 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.chip_sw_pwrmgr_usbdev_smoketest.2512318770
Directory /workspace/2.chip_sw_pwrmgr_usbdev_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.424976040
Short name T1110
Test name
Test status
Simulation time 5745583660 ps
CPU time 653.43 seconds
Started Aug 02 08:36:45 PM PDT 24
Finished Aug 02 08:47:39 PM PDT 24
Peak memory 610424 kb
Host smart-7436ff80-027f-4c79-9087-f11268009960
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424
976040 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.424976040
Directory /workspace/2.chip_sw_pwrmgr_wdog_reset/latest

Test location /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1874340238
Short name T412
Test name
Test status
Simulation time 9924844691 ps
CPU time 500.53 seconds
Started Aug 02 08:39:36 PM PDT 24
Finished Aug 02 08:47:57 PM PDT 24
Peak memory 624732 kb
Host smart-56e3e342-beb7-46d0-97d6-30b66800f01e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874340238 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.1874340238
Directory /workspace/2.chip_sw_rom_ctrl_integrity_check/latest

Test location /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1326503251
Short name T342
Test name
Test status
Simulation time 12223199768 ps
CPU time 1580.59 seconds
Started Aug 02 08:41:17 PM PDT 24
Finished Aug 02 09:07:39 PM PDT 24
Peak memory 610668 kb
Host smart-9a039bba-c267-4489-ad34-9b0f8a27ee2f
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test
_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb
_random_seed=1326503251 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.1326503251
Directory /workspace/2.chip_sw_rstmgr_alert_info/latest

Test location /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.775894550
Short name T248
Test name
Test status
Simulation time 4662739372 ps
CPU time 531.68 seconds
Started Aug 02 08:35:44 PM PDT 24
Finished Aug 02 08:44:36 PM PDT 24
Peak memory 609260 kb
Host smart-47fdfdb8-f0c7-41e0-be55-cb23d306d7c6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775894550 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.chip_sw_rstmgr_cpu_info.775894550
Directory /workspace/2.chip_sw_rstmgr_cpu_info/latest

Test location /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.3517898812
Short name T979
Test name
Test status
Simulation time 3130629016 ps
CPU time 160.19 seconds
Started Aug 02 08:43:15 PM PDT 24
Finished Aug 02 08:45:55 PM PDT 24
Peak memory 609632 kb
Host smart-eaab8e64-0d14-4ea0-bbfc-749fb8327272
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517898812 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.chip_sw_rstmgr_smoketest.3517898812
Directory /workspace/2.chip_sw_rstmgr_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.2755719304
Short name T1117
Test name
Test status
Simulation time 4939330126 ps
CPU time 525.28 seconds
Started Aug 02 08:36:54 PM PDT 24
Finished Aug 02 08:45:39 PM PDT 24
Peak memory 610416 kb
Host smart-01bf5b23-c036-4abf-807c-74a052497b70
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755719304 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.chip_sw_rstmgr_sw_req.2755719304
Directory /workspace/2.chip_sw_rstmgr_sw_req/latest

Test location /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.3030005383
Short name T1096
Test name
Test status
Simulation time 2836257048 ps
CPU time 180.38 seconds
Started Aug 02 08:41:33 PM PDT 24
Finished Aug 02 08:44:33 PM PDT 24
Peak memory 609688 kb
Host smart-ff6392db-b117-46a4-b271-6c83e6095c4d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030005383 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.chip_sw_rstmgr_sw_rst.3030005383
Directory /workspace/2.chip_sw_rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.1072451625
Short name T183
Test name
Test status
Simulation time 2939340760 ps
CPU time 221.2 seconds
Started Aug 02 08:46:07 PM PDT 24
Finished Aug 02 08:49:48 PM PDT 24
Peak memory 609812 kb
Host smart-447d90cb-acb5-4fee-b265-b3170bb12919
User root
Command /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=1072451625 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.1072451625
Directory /workspace/2.chip_sw_rv_core_ibex_address_translation/latest

Test location /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.2197359959
Short name T308
Test name
Test status
Simulation time 3526458313 ps
CPU time 296.23 seconds
Started Aug 02 08:42:49 PM PDT 24
Finished Aug 02 08:47:45 PM PDT 24
Peak memory 609448 kb
Host smart-fe113599-9562-41df-b309-782bf51f5668
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197359959 -assert nopostp
roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.2197359959
Directory /workspace/2.chip_sw_rv_core_ibex_icache_invalidate/latest

Test location /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.2223810613
Short name T732
Test name
Test status
Simulation time 4928105376 ps
CPU time 900.57 seconds
Started Aug 02 08:37:47 PM PDT 24
Finished Aug 02 08:52:48 PM PDT 24
Peak memory 610196 kb
Host smart-5d0d24ec-df3d-4b51-bfc3-b0c6c6399304
User root
Command /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22238
10613 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.2223810613
Directory /workspace/2.chip_sw_rv_core_ibex_nmi_irq/latest

Test location /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.731757242
Short name T926
Test name
Test status
Simulation time 5447845450 ps
CPU time 1059.9 seconds
Started Aug 02 08:40:02 PM PDT 24
Finished Aug 02 08:57:43 PM PDT 24
Peak memory 610088 kb
Host smart-d0804ffa-5c31-43b5-ad01-fa8ea2cdedd2
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=731757242 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.731757242
Directory /workspace/2.chip_sw_rv_core_ibex_rnd/latest

Test location /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2198428492
Short name T712
Test name
Test status
Simulation time 4854082493 ps
CPU time 677.34 seconds
Started Aug 02 08:40:38 PM PDT 24
Finished Aug 02 08:51:55 PM PDT 24
Peak memory 624532 kb
Host smart-ff66d7a9-2ac4-4a0e-ade7-00594ee1190d
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198428492 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.2198428492
Directory /workspace/2.chip_sw_rv_dm_access_after_escalation_reset/latest

Test location /workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.583341976
Short name T72
Test name
Test status
Simulation time 5319023668 ps
CPU time 465.68 seconds
Started Aug 02 08:43:10 PM PDT 24
Finished Aug 02 08:50:56 PM PDT 24
Peak memory 621252 kb
Host smart-3dacee54-293c-413d-b746-927e13a1de84
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583341976 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_wakeup.583341976
Directory /workspace/2.chip_sw_rv_dm_access_after_wakeup/latest

Test location /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3687382565
Short name T265
Test name
Test status
Simulation time 5679593100 ps
CPU time 593.93 seconds
Started Aug 02 08:40:14 PM PDT 24
Finished Aug 02 08:50:08 PM PDT 24
Peak memory 620328 kb
Host smart-94f8e459-dc71-4cc9-98d1-693595916e30
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368738
2565 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3687382565
Directory /workspace/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest

Test location /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.1190929961
Short name T1001
Test name
Test status
Simulation time 3035849114 ps
CPU time 291.87 seconds
Started Aug 02 08:44:17 PM PDT 24
Finished Aug 02 08:49:09 PM PDT 24
Peak memory 608444 kb
Host smart-2e246205-45b5-444e-8726-9249127343ff
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190929961 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.chip_sw_rv_plic_smoketest.1190929961
Directory /workspace/2.chip_sw_rv_plic_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_rv_timer_irq.793367787
Short name T1324
Test name
Test status
Simulation time 2728828458 ps
CPU time 255.61 seconds
Started Aug 02 08:36:35 PM PDT 24
Finished Aug 02 08:40:51 PM PDT 24
Peak memory 609644 kb
Host smart-30113fe0-c68a-4bcd-a2ca-81d43b6fce2a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793367787 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.chip_sw_rv_timer_irq.793367787
Directory /workspace/2.chip_sw_rv_timer_irq/latest

Test location /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3720868692
Short name T1296
Test name
Test status
Simulation time 2482875560 ps
CPU time 294.54 seconds
Started Aug 02 08:43:23 PM PDT 24
Finished Aug 02 08:48:17 PM PDT 24
Peak memory 609644 kb
Host smart-743f82ae-0cf3-4615-b56c-d2dfaffad981
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720868692 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.chip_sw_rv_timer_smoketest.3720868692
Directory /workspace/2.chip_sw_rv_timer_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_rv_timer_systick_test.4105007936
Short name T1044
Test name
Test status
Simulation time 38574519684 ps
CPU time 6733.33 seconds
Started Aug 02 08:36:42 PM PDT 24
Finished Aug 02 10:28:55 PM PDT 24
Peak memory 608860 kb
Host smart-0c550374-09d9-429c-90d0-401f178e9e48
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=rv_timer_systick_test:1:new_rules,test_rom:0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410500793
6 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_timer_systick_test.4105007936
Directory /workspace/2.chip_sw_rv_timer_systick_test/latest

Test location /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1402204130
Short name T131
Test name
Test status
Simulation time 8334403580 ps
CPU time 1027.68 seconds
Started Aug 02 08:40:07 PM PDT 24
Finished Aug 02 08:57:15 PM PDT 24
Peak memory 610576 kb
Host smart-4f33e442-149c-4ec9-a891-609fa24ada7f
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14022041
30 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.1402204130
Directory /workspace/2.chip_sw_sensor_ctrl_alert/latest

Test location /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.1489504253
Short name T1328
Test name
Test status
Simulation time 2371307914 ps
CPU time 290.42 seconds
Started Aug 02 08:39:13 PM PDT 24
Finished Aug 02 08:44:03 PM PDT 24
Peak memory 610412 kb
Host smart-bd75bb7b-c6ba-49f8-8478-a01a02d02c83
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489504
253 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.1489504253
Directory /workspace/2.chip_sw_sensor_ctrl_status/latest

Test location /workspace/coverage/default/2.chip_sw_sleep_pin_retention.2761042644
Short name T28
Test name
Test status
Simulation time 3644767490 ps
CPU time 273.01 seconds
Started Aug 02 08:37:53 PM PDT 24
Finished Aug 02 08:42:26 PM PDT 24
Peak memory 608888 kb
Host smart-6d261fdf-db35-486b-877b-68413faeb01f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761042644 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_retention.2761042644
Directory /workspace/2.chip_sw_sleep_pin_retention/latest

Test location /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.1965529079
Short name T963
Test name
Test status
Simulation time 9954710526 ps
CPU time 1468.34 seconds
Started Aug 02 08:34:11 PM PDT 24
Finished Aug 02 08:58:40 PM PDT 24
Peak memory 610780 kb
Host smart-5d620ebf-8011-478c-bec2-e7613798c56e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965529079 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.chip_sw_sleep_pwm_pulses.1965529079
Directory /workspace/2.chip_sw_sleep_pwm_pulses/latest

Test location /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.2708856438
Short name T916
Test name
Test status
Simulation time 7400786122 ps
CPU time 645.28 seconds
Started Aug 02 08:40:19 PM PDT 24
Finished Aug 02 08:51:05 PM PDT 24
Peak memory 610420 kb
Host smart-942c6e20-b4c1-40eb-b704-7917ca1dc848
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708856438 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S
EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sl
eep_sram_ret_contents_no_scramble.2708856438
Directory /workspace/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest

Test location /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2346265925
Short name T179
Test name
Test status
Simulation time 8786031644 ps
CPU time 924.24 seconds
Started Aug 02 08:39:46 PM PDT 24
Finished Aug 02 08:55:11 PM PDT 24
Peak memory 610692 kb
Host smart-1c47034f-e36b-419e-9168-ee05e68f7e4c
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346265925 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep
_sram_ret_contents_scramble.2346265925
Directory /workspace/2.chip_sw_sleep_sram_ret_contents_scramble/latest

Test location /workspace/coverage/default/2.chip_sw_spi_device_pass_through.2097776333
Short name T45
Test name
Test status
Simulation time 7125529072 ps
CPU time 862.06 seconds
Started Aug 02 08:35:06 PM PDT 24
Finished Aug 02 08:49:29 PM PDT 24
Peak memory 624844 kb
Host smart-5151c857-5b44-403b-8556-acddf66208db
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097776333 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through.2097776333
Directory /workspace/2.chip_sw_spi_device_pass_through/latest

Test location /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.1582486214
Short name T12
Test name
Test status
Simulation time 4111431260 ps
CPU time 604.85 seconds
Started Aug 02 08:35:02 PM PDT 24
Finished Aug 02 08:45:07 PM PDT 24
Peak memory 624892 kb
Host smart-9d05ade0-b42b-4553-b837-c0f79d739c65
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582486214 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.1582486214
Directory /workspace/2.chip_sw_spi_device_pass_through_collision/latest

Test location /workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.2335299061
Short name T58
Test name
Test status
Simulation time 3218339028 ps
CPU time 224.95 seconds
Started Aug 02 08:35:37 PM PDT 24
Finished Aug 02 08:39:22 PM PDT 24
Peak memory 619160 kb
Host smart-671f7ec5-a97f-4fa8-820b-02c29d822428
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335299061 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pinmux_sleep_retention.2335299061
Directory /workspace/2.chip_sw_spi_device_pinmux_sleep_retention/latest

Test location /workspace/coverage/default/2.chip_sw_spi_device_tpm.623894725
Short name T44
Test name
Test status
Simulation time 3221013230 ps
CPU time 389.42 seconds
Started Aug 02 08:35:27 PM PDT 24
Finished Aug 02 08:41:57 PM PDT 24
Peak memory 619564 kb
Host smart-57442dae-7d9d-4521-8721-3fba8bc3f242
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623894725 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_tpm.623894725
Directory /workspace/2.chip_sw_spi_device_tpm/latest

Test location /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.2762220123
Short name T316
Test name
Test status
Simulation time 10017330261 ps
CPU time 1135.17 seconds
Started Aug 02 08:41:03 PM PDT 24
Finished Aug 02 08:59:59 PM PDT 24
Peak memory 610696 kb
Host smart-55f66b21-9b53-4703-a791-0fda0f1bffcf
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762220123 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.2762220123
Directory /workspace/2.chip_sw_sram_ctrl_execution_main/latest

Test location /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3116875014
Short name T1380
Test name
Test status
Simulation time 4635632984 ps
CPU time 657.92 seconds
Started Aug 02 08:41:02 PM PDT 24
Finished Aug 02 08:52:00 PM PDT 24
Peak memory 611172 kb
Host smart-bb6e97ff-be38-40e3-a183-0bb0eb57628f
User root
Command /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116875014 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr
l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw
_sram_ctrl_scrambled_access.3116875014
Directory /workspace/2.chip_sw_sram_ctrl_scrambled_access/latest

Test location /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2283169699
Short name T297
Test name
Test status
Simulation time 4109116814 ps
CPU time 639.81 seconds
Started Aug 02 08:38:53 PM PDT 24
Finished Aug 02 08:49:33 PM PDT 24
Peak memory 610900 kb
Host smart-0b052380-937f-46e5-8bdd-b1d8bf102e83
User root
Command /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s
w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283169699 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi
p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2283169699
Directory /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3162981468
Short name T294
Test name
Test status
Simulation time 5274424144 ps
CPU time 560.4 seconds
Started Aug 02 08:41:23 PM PDT 24
Finished Aug 02 08:50:44 PM PDT 24
Peak memory 611128 kb
Host smart-66b184aa-99e6-4959-947b-a04ffb24b23f
User root
Command /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk
_70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162981468 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3162981468
Directory /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.3916687957
Short name T418
Test name
Test status
Simulation time 3529494640 ps
CPU time 318.47 seconds
Started Aug 02 08:43:05 PM PDT 24
Finished Aug 02 08:48:24 PM PDT 24
Peak memory 609604 kb
Host smart-550f554e-2ad0-40c6-89d1-26dd8f38c121
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916687957 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.chip_sw_sram_ctrl_smoketest.3916687957
Directory /workspace/2.chip_sw_sram_ctrl_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3690938632
Short name T1206
Test name
Test status
Simulation time 21086616256 ps
CPU time 3741.08 seconds
Started Aug 02 08:36:56 PM PDT 24
Finished Aug 02 09:39:18 PM PDT 24
Peak memory 610912 kb
Host smart-e7a9af6d-0cd9-4eaf-a5c4-4d56a21743f2
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690938632 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.3690938632
Directory /workspace/2.chip_sw_sysrst_ctrl_ec_rst_l/latest

Test location /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.30178582
Short name T1317
Test name
Test status
Simulation time 5544480023 ps
CPU time 824.43 seconds
Started Aug 02 08:38:14 PM PDT 24
Finished Aug 02 08:52:00 PM PDT 24
Peak memory 613776 kb
Host smart-78325417-4efd-4839-93f0-e4bd21b6f918
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30178582 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_in_irq.30178582
Directory /workspace/2.chip_sw_sysrst_ctrl_in_irq/latest

Test location /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.2827203434
Short name T208
Test name
Test status
Simulation time 2558320037 ps
CPU time 278.12 seconds
Started Aug 02 08:37:13 PM PDT 24
Finished Aug 02 08:41:52 PM PDT 24
Peak memory 613040 kb
Host smart-37cf64f4-bebc-47f4-abb3-4ab20d658ae8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827203434 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_inputs.2827203434
Directory /workspace/2.chip_sw_sysrst_ctrl_inputs/latest

Test location /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.2202872878
Short name T1290
Test name
Test status
Simulation time 3410616936 ps
CPU time 444.34 seconds
Started Aug 02 08:41:49 PM PDT 24
Finished Aug 02 08:49:15 PM PDT 24
Peak memory 609992 kb
Host smart-879737c3-7ff2-4e02-8ebf-499a12abe6d5
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202872878 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_outputs.2202872878
Directory /workspace/2.chip_sw_sysrst_ctrl_outputs/latest

Test location /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.3604973324
Short name T209
Test name
Test status
Simulation time 21240827868 ps
CPU time 1630.17 seconds
Started Aug 02 08:37:33 PM PDT 24
Finished Aug 02 09:04:44 PM PDT 24
Peak memory 613660 kb
Host smart-2a04378b-134c-4391-bea6-487653a6cdf4
User root
Command /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36049733
24 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.3604973324
Directory /workspace/2.chip_sw_sysrst_ctrl_reset/latest

Test location /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1472190369
Short name T39
Test name
Test status
Simulation time 5149559772 ps
CPU time 455.22 seconds
Started Aug 02 08:37:44 PM PDT 24
Finished Aug 02 08:45:20 PM PDT 24
Peak memory 610492 kb
Host smart-782ce7de-7f77-418c-8e33-5b9ff328bf87
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472190369 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1472190369
Directory /workspace/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest

Test location /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.1052043053
Short name T1161
Test name
Test status
Simulation time 8650756522 ps
CPU time 1739.4 seconds
Started Aug 02 08:37:23 PM PDT 24
Finished Aug 02 09:06:23 PM PDT 24
Peak memory 624488 kb
Host smart-d2ff598e-0462-4492-b0d7-29da84628b56
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=1052043053 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.1052043053
Directory /workspace/2.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/2.chip_sw_uart_smoketest.3046175256
Short name T1378
Test name
Test status
Simulation time 2598895786 ps
CPU time 224.62 seconds
Started Aug 02 08:42:11 PM PDT 24
Finished Aug 02 08:45:56 PM PDT 24
Peak memory 615084 kb
Host smart-981dc29f-3945-4b82-8d17-046d608a5a61
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046175256 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.chip_sw_uart_smoketest.3046175256
Directory /workspace/2.chip_sw_uart_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx.3731269738
Short name T218
Test name
Test status
Simulation time 3944770624 ps
CPU time 617.25 seconds
Started Aug 02 08:33:56 PM PDT 24
Finished Aug 02 08:44:14 PM PDT 24
Peak memory 623920 kb
Host smart-4abc861f-a6a2-41b1-9ae0-cf30699c35d6
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731269738 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.3731269738
Directory /workspace/2.chip_sw_uart_tx_rx/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1820180910
Short name T950
Test name
Test status
Simulation time 8278921964 ps
CPU time 1804.38 seconds
Started Aug 02 08:34:23 PM PDT 24
Finished Aug 02 09:04:28 PM PDT 24
Peak memory 624532 kb
Host smart-7a17d194-ff67-4408-8d8a-4b977e6e0da9
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820180910 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx
_alt_clk_freq.1820180910
Directory /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.205555206
Short name T1285
Test name
Test status
Simulation time 4544422162 ps
CPU time 645.17 seconds
Started Aug 02 08:36:08 PM PDT 24
Finished Aug 02 08:46:54 PM PDT 24
Peak memory 624560 kb
Host smart-3b0f05b1-3e68-421e-9da3-e1a9aaed7b73
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205555206 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba
udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_
alt_clk_freq_low_speed.205555206
Directory /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.2029471382
Short name T1230
Test name
Test status
Simulation time 79046478420 ps
CPU time 13866.5 seconds
Started Aug 02 08:34:05 PM PDT 24
Finished Aug 03 12:25:13 AM PDT 24
Peak memory 634100 kb
Host smart-0059d91f-d38f-4219-a022-cf783e4cfe90
User root
Command /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2029471382 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_bootstrap.2029471382
Directory /workspace/2.chip_sw_uart_tx_rx_bootstrap/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.4215204136
Short name T1367
Test name
Test status
Simulation time 4480432260 ps
CPU time 759 seconds
Started Aug 02 08:35:44 PM PDT 24
Finished Aug 02 08:48:23 PM PDT 24
Peak memory 624340 kb
Host smart-afca3a9e-856b-4a5c-986a-2bca084e9486
User root
Command /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215204136 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.4215204136
Directory /workspace/2.chip_sw_uart_tx_rx_idx1/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.2712458277
Short name T303
Test name
Test status
Simulation time 4368199366 ps
CPU time 655.09 seconds
Started Aug 02 08:35:34 PM PDT 24
Finished Aug 02 08:46:30 PM PDT 24
Peak memory 623712 kb
Host smart-f7e633ee-16a4-4493-af81-4eeed7163d57
User root
Command /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712458277 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.2712458277
Directory /workspace/2.chip_sw_uart_tx_rx_idx2/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.714293261
Short name T944
Test name
Test status
Simulation time 4230640098 ps
CPU time 678.71 seconds
Started Aug 02 08:36:45 PM PDT 24
Finished Aug 02 08:48:05 PM PDT 24
Peak memory 623944 kb
Host smart-26a677d9-5595-4795-9148-af64ff500a5f
User root
Command /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714293261 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.714293261
Directory /workspace/2.chip_sw_uart_tx_rx_idx3/latest

Test location /workspace/coverage/default/2.chip_tap_straps_prod.227289029
Short name T196
Test name
Test status
Simulation time 3065686261 ps
CPU time 160.93 seconds
Started Aug 02 08:40:53 PM PDT 24
Finished Aug 02 08:43:34 PM PDT 24
Peak memory 623940 kb
Host smart-b33c9e8f-4576-49f6-884f-cd3ed025812b
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom
:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=227289029 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.227289029
Directory /workspace/2.chip_tap_straps_prod/latest

Test location /workspace/coverage/default/2.rom_e2e_asm_init_dev.3166523208
Short name T1025
Test name
Test status
Simulation time 15175400998 ps
CPU time 4592.93 seconds
Started Aug 02 08:51:47 PM PDT 24
Finished Aug 02 10:08:20 PM PDT 24
Peak memory 610328 kb
Host smart-a1e47785-0375-44ae-bd5c-96b8af282f4b
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166523208 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S
EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rom_e2e_asm_init_dev.3166523208
Directory /workspace/2.rom_e2e_asm_init_dev/latest

Test location /workspace/coverage/default/2.rom_e2e_asm_init_prod.2458342617
Short name T300
Test name
Test status
Simulation time 15275094905 ps
CPU time 3443.93 seconds
Started Aug 02 08:47:39 PM PDT 24
Finished Aug 02 09:45:03 PM PDT 24
Peak memory 610356 kb
Host smart-582c2928-ae54-46fb-a189-e3dc67fafe4b
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458342617 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_
SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rom_e2e_asm_init_prod.2458342617
Directory /workspace/2.rom_e2e_asm_init_prod/latest

Test location /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2859907739
Short name T177
Test name
Test status
Simulation time 14996741194 ps
CPU time 4096.84 seconds
Started Aug 02 08:50:05 PM PDT 24
Finished Aug 02 09:58:23 PM PDT 24
Peak memory 610376 kb
Host smart-cd3c9640-13ca-4b9e-b851-96ff77482de6
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859907739 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T
EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_e2e_asm_init_prod_end.2859907739
Directory /workspace/2.rom_e2e_asm_init_prod_end/latest

Test location /workspace/coverage/default/2.rom_e2e_asm_init_rma.4013482382
Short name T997
Test name
Test status
Simulation time 15160801761 ps
CPU time 3211.14 seconds
Started Aug 02 08:48:36 PM PDT 24
Finished Aug 02 09:42:08 PM PDT 24
Peak memory 610300 kb
Host smart-b3f2456c-9ca0-4fa7-ad62-8405bb151966
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013482382 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S
EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rom_e2e_asm_init_rma.4013482382
Directory /workspace/2.rom_e2e_asm_init_rma/latest

Test location /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.4043442446
Short name T923
Test name
Test status
Simulation time 11358245909 ps
CPU time 3497.49 seconds
Started Aug 02 08:51:49 PM PDT 24
Finished Aug 02 09:50:06 PM PDT 24
Peak memory 610624 kb
Host smart-d4c1a3dd-a333-40ef-b02a-79f9416dd343
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043442446 -assert nopostproc +UVM_TESTNAME=chip_base_te
st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.rom_e2e_asm_init_test_unlocked0.4043442446
Directory /workspace/2.rom_e2e_asm_init_test_unlocked0/latest

Test location /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.865348525
Short name T97
Test name
Test status
Simulation time 14279518810 ps
CPU time 3564.75 seconds
Started Aug 02 08:48:15 PM PDT 24
Finished Aug 02 09:47:41 PM PDT 24
Peak memory 609936 kb
Host smart-74aa4d60-7596-486f-b2f1-dbe37b8b230a
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid
_meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865348525 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_
sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_ini
t_rom_ext_invalid_meas.865348525
Directory /workspace/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest

Test location /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.865620902
Short name T990
Test name
Test status
Simulation time 15173581528 ps
CPU time 4128.42 seconds
Started Aug 02 08:50:00 PM PDT 24
Finished Aug 02 09:58:49 PM PDT 24
Peak memory 610072 kb
Host smart-d12bd1ce-7099-4eba-befb-21270c386055
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1:
new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865620902 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_meas.865620902
Directory /workspace/2.rom_e2e_keymgr_init_rom_ext_meas/latest

Test location /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.876909283
Short name T998
Test name
Test status
Simulation time 15188850178 ps
CPU time 4300.82 seconds
Started Aug 02 08:47:27 PM PDT 24
Finished Aug 02 09:59:08 PM PDT 24
Peak memory 610092 kb
Host smart-f7c65473-812f-40d9-8537-6468128e516c
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas
:1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876909283 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_
no_meas.876909283
Directory /workspace/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest

Test location /workspace/coverage/default/2.rom_e2e_self_hash.1928890471
Short name T956
Test name
Test status
Simulation time 26501214910 ps
CPU time 5496.73 seconds
Started Aug 02 08:48:34 PM PDT 24
Finished Aug 02 10:20:12 PM PDT 24
Peak memory 609988 kb
Host smart-79895a05-b5b3-4c35-ad93-77e171fe2943
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r
ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928890471 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_self_hash.1928890471
Directory /workspace/2.rom_e2e_self_hash/latest

Test location /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.3282165587
Short name T1196
Test name
Test status
Simulation time 14910776480 ps
CPU time 3424.67 seconds
Started Aug 02 08:46:53 PM PDT 24
Finished Aug 02 09:43:58 PM PDT 24
Peak memory 611168 kb
Host smart-1c01107d-e740-448b-ad5e-4d4a6f17342b
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne
w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282165587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu
tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_
shutdown_exception_c.3282165587
Directory /workspace/2.rom_e2e_shutdown_exception_c/latest

Test location /workspace/coverage/default/2.rom_e2e_shutdown_output.911319803
Short name T962
Test name
Test status
Simulation time 24294935676 ps
CPU time 3474.37 seconds
Started Aug 02 08:47:40 PM PDT 24
Finished Aug 02 09:45:35 PM PDT 24
Peak memory 611780 kb
Host smart-43b96295-6065-4115-be1a-fb6010ed9474
User root
Command /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f
lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911319803 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip
_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rom_e2e_shutdown_output.911319803
Directory /workspace/2.rom_e2e_shutdown_output/latest

Test location /workspace/coverage/default/2.rom_e2e_smoke.2732619103
Short name T169
Test name
Test status
Simulation time 14630812456 ps
CPU time 3066.35 seconds
Started Aug 02 08:47:25 PM PDT 24
Finished Aug 02 09:38:32 PM PDT 24
Peak memory 610140 kb
Host smart-2153a02e-da34-405c-8309-269bec27df9f
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img
_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to
p/hw/dv/tools/sim.tcl +ntb_random_seed=2732619103 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.2732619103
Directory /workspace/2.rom_e2e_smoke/latest

Test location /workspace/coverage/default/2.rom_e2e_static_critical.4178395215
Short name T1197
Test name
Test status
Simulation time 17199873128 ps
CPU time 3454.08 seconds
Started Aug 02 08:45:49 PM PDT 24
Finished Aug 02 09:43:24 PM PDT 24
Peak memory 610204 kb
Host smart-cb48bfe2-1c6c-4600-a19d-f56224bd71c5
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul
es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178395215 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_static_critical.4178395215
Directory /workspace/2.rom_e2e_static_critical/latest

Test location /workspace/coverage/default/2.rom_keymgr_functest.1961482466
Short name T1369
Test name
Test status
Simulation time 4941367444 ps
CPU time 803.09 seconds
Started Aug 02 08:43:44 PM PDT 24
Finished Aug 02 08:57:08 PM PDT 24
Peak memory 610620 kb
Host smart-939090ab-3302-4aa0-aab4-bbc0dc0b923a
User root
Command /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961482466 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_keymgr_functest.1961482466
Directory /workspace/2.rom_keymgr_functest/latest

Test location /workspace/coverage/default/2.rom_raw_unlock.1145868849
Short name T148
Test name
Test status
Simulation time 6391582773 ps
CPU time 282.67 seconds
Started Aug 02 08:42:47 PM PDT 24
Finished Aug 02 08:47:29 PM PDT 24
Peak memory 623520 kb
Host smart-d4ddc171-b045-41d5-a9e2-4814c9d182fd
User root
Command /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE
xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1145868849 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_raw_unlock.1145868849
Directory /workspace/2.rom_raw_unlock/latest

Test location /workspace/coverage/default/2.rom_volatile_raw_unlock.175761677
Short name T716
Test name
Test status
Simulation time 2419039406 ps
CPU time 121.44 seconds
Started Aug 02 08:43:56 PM PDT 24
Finished Aug 02 08:45:58 PM PDT 24
Peak memory 617028 kb
Host smart-bc81b7ce-ae98-4cd0-bdc1-0e3bbac00946
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1
+sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175761677 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.175761677
Directory /workspace/2.rom_volatile_raw_unlock/latest

Test location /workspace/coverage/default/20.chip_sw_all_escalation_resets.811898373
Short name T1132
Test name
Test status
Simulation time 4985099384 ps
CPU time 708.63 seconds
Started Aug 02 08:49:05 PM PDT 24
Finished Aug 02 09:00:55 PM PDT 24
Peak memory 649900 kb
Host smart-2d0d62f3-41a7-4b11-8f77-6fa1d1ad4d5a
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
811898373 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.811898373
Directory /workspace/20.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/23.chip_sw_all_escalation_resets.3488631944
Short name T1320
Test name
Test status
Simulation time 5678103436 ps
CPU time 567.07 seconds
Started Aug 02 08:47:57 PM PDT 24
Finished Aug 02 08:57:24 PM PDT 24
Peak memory 650076 kb
Host smart-134c66de-141c-4685-a04c-98f1adf49619
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3488631944 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.3488631944
Directory /workspace/23.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.4173261451
Short name T811
Test name
Test status
Simulation time 3903464514 ps
CPU time 430.45 seconds
Started Aug 02 08:48:40 PM PDT 24
Finished Aug 02 08:55:51 PM PDT 24
Peak memory 648924 kb
Host smart-d3fa2b10-8066-4e2f-a616-e54e82e2c03d
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173261451 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_
sw_alert_handler_lpg_sleep_mode_alerts.4173261451
Directory /workspace/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/24.chip_sw_all_escalation_resets.1062577033
Short name T986
Test name
Test status
Simulation time 5391358680 ps
CPU time 733.12 seconds
Started Aug 02 08:48:48 PM PDT 24
Finished Aug 02 09:01:02 PM PDT 24
Peak memory 619664 kb
Host smart-5e63444f-675f-48a9-b301-80e2eaef9fcc
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1062577033 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.1062577033
Directory /workspace/24.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.4166910556
Short name T817
Test name
Test status
Simulation time 3522000136 ps
CPU time 419.63 seconds
Started Aug 02 08:50:25 PM PDT 24
Finished Aug 02 08:57:25 PM PDT 24
Peak memory 649228 kb
Host smart-929012bc-c2c0-4d4c-8e26-a691d7000c51
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166910556 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_
sw_alert_handler_lpg_sleep_mode_alerts.4166910556
Directory /workspace/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2065978304
Short name T1076
Test name
Test status
Simulation time 3929777656 ps
CPU time 429.62 seconds
Started Aug 02 08:49:20 PM PDT 24
Finished Aug 02 08:56:29 PM PDT 24
Peak memory 618744 kb
Host smart-29fe81f5-8403-456c-9ff6-e4e525362c08
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065978304 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2065978304
Directory /workspace/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/26.chip_sw_all_escalation_resets.3047346564
Short name T1250
Test name
Test status
Simulation time 4594128112 ps
CPU time 690.03 seconds
Started Aug 02 08:49:45 PM PDT 24
Finished Aug 02 09:01:16 PM PDT 24
Peak memory 617008 kb
Host smart-30f492b8-cdee-42f8-b259-509f2a5bf9c0
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3047346564 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.3047346564
Directory /workspace/26.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/27.chip_sw_all_escalation_resets.18230134
Short name T1162
Test name
Test status
Simulation time 5550733778 ps
CPU time 700.29 seconds
Started Aug 02 08:49:07 PM PDT 24
Finished Aug 02 09:00:48 PM PDT 24
Peak memory 650308 kb
Host smart-53ef18f1-d935-4424-8ba6-92587cd6efd0
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
18230134 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.18230134
Directory /workspace/27.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/28.chip_sw_all_escalation_resets.1313256570
Short name T1261
Test name
Test status
Simulation time 5793739760 ps
CPU time 554.21 seconds
Started Aug 02 08:49:22 PM PDT 24
Finished Aug 02 08:58:36 PM PDT 24
Peak memory 650360 kb
Host smart-2fa83007-5076-4f31-8ae2-5dffcfff1c4b
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1313256570 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.1313256570
Directory /workspace/28.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1508210936
Short name T306
Test name
Test status
Simulation time 3737978552 ps
CPU time 438.89 seconds
Started Aug 02 08:50:14 PM PDT 24
Finished Aug 02 08:57:33 PM PDT 24
Peak memory 649424 kb
Host smart-8692d6c1-6b90-4025-af22-2a4f5598be53
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508210936 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1508210936
Directory /workspace/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/3.chip_sw_all_escalation_resets.2870810417
Short name T774
Test name
Test status
Simulation time 5520464696 ps
CPU time 494.85 seconds
Started Aug 02 08:43:16 PM PDT 24
Finished Aug 02 08:51:31 PM PDT 24
Peak memory 650000 kb
Host smart-0611c092-a42f-4598-93f7-9c38de5c2dac
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2870810417 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.2870810417
Directory /workspace/3.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.4110419101
Short name T1238
Test name
Test status
Simulation time 6596436106 ps
CPU time 518.43 seconds
Started Aug 02 08:42:50 PM PDT 24
Finished Aug 02 08:51:29 PM PDT 24
Peak memory 610552 kb
Host smart-ce7cead9-dc5d-481c-aed8-863db1b8e1dd
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4110419101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.4110419101
Directory /workspace/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.3144428911
Short name T122
Test name
Test status
Simulation time 8816174330 ps
CPU time 1859.51 seconds
Started Aug 02 08:42:57 PM PDT 24
Finished Aug 02 09:13:57 PM PDT 24
Peak memory 610200 kb
Host smart-c30b615c-ca21-4339-a749-929d71584ff8
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144428911 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 3.chip_sw_csrng_edn_concurrency.3144428911
Directory /workspace/3.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/3.chip_sw_data_integrity_escalation.2276989424
Short name T296
Test name
Test status
Simulation time 6397650800 ps
CPU time 847.98 seconds
Started Aug 02 08:43:17 PM PDT 24
Finished Aug 02 08:57:26 PM PDT 24
Peak memory 611040 kb
Host smart-3c19d8d2-7a8a-4790-9298-65b7fa06870b
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2276989424 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.2276989424
Directory /workspace/3.chip_sw_data_integrity_escalation/latest

Test location /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.1533965936
Short name T1174
Test name
Test status
Simulation time 5680872895 ps
CPU time 514.54 seconds
Started Aug 02 08:43:48 PM PDT 24
Finished Aug 02 08:52:22 PM PDT 24
Peak memory 624656 kb
Host smart-bea673d6-5da6-4599-b5d0-957de58b291e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533965936 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.chip_sw_lc_ctrl_transition.1533965936
Directory /workspace/3.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.4010066729
Short name T1368
Test name
Test status
Simulation time 7837984548 ps
CPU time 1131.07 seconds
Started Aug 02 08:43:19 PM PDT 24
Finished Aug 02 09:02:10 PM PDT 24
Peak memory 610584 kb
Host smart-fca43a39-8562-4bd6-bf61-dee2ed10a532
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40100667
29 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.4010066729
Directory /workspace/3.chip_sw_sensor_ctrl_alert/latest

Test location /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.2290474390
Short name T1154
Test name
Test status
Simulation time 4820602040 ps
CPU time 721.25 seconds
Started Aug 02 08:43:05 PM PDT 24
Finished Aug 02 08:55:06 PM PDT 24
Peak memory 624580 kb
Host smart-3661bd02-bff9-41f6-befc-001dbf37986c
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=2290474390 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.2290474390
Directory /workspace/3.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/3.chip_sw_uart_tx_rx.2137922337
Short name T1155
Test name
Test status
Simulation time 4516927180 ps
CPU time 782.69 seconds
Started Aug 02 08:43:17 PM PDT 24
Finished Aug 02 08:56:21 PM PDT 24
Peak memory 623932 kb
Host smart-15adb7f1-f145-46b2-80ee-3983b59458c5
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137922337 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.2137922337
Directory /workspace/3.chip_sw_uart_tx_rx/latest

Test location /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1264412263
Short name T214
Test name
Test status
Simulation time 9245951245 ps
CPU time 1090.21 seconds
Started Aug 02 08:44:02 PM PDT 24
Finished Aug 02 09:02:13 PM PDT 24
Peak memory 618988 kb
Host smart-94eadbd3-7f44-444b-b00e-f33a039c9f5b
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264412263 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx
_alt_clk_freq_low_speed.1264412263
Directory /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.693402173
Short name T1170
Test name
Test status
Simulation time 4820563950 ps
CPU time 596.79 seconds
Started Aug 02 08:45:01 PM PDT 24
Finished Aug 02 08:54:58 PM PDT 24
Peak memory 624212 kb
Host smart-b201b427-730e-40c6-998b-12ff5cd5789f
User root
Command /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693402173 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.693402173
Directory /workspace/3.chip_sw_uart_tx_rx_idx1/latest

Test location /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.3384424397
Short name T1119
Test name
Test status
Simulation time 3629661896 ps
CPU time 765.53 seconds
Started Aug 02 08:45:56 PM PDT 24
Finished Aug 02 08:58:42 PM PDT 24
Peak memory 624016 kb
Host smart-65530d1d-ebd0-49bf-8828-4e516ce4f7d1
User root
Command /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384424397 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.3384424397
Directory /workspace/3.chip_sw_uart_tx_rx_idx2/latest

Test location /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.2404129293
Short name T1030
Test name
Test status
Simulation time 4284933976 ps
CPU time 665.73 seconds
Started Aug 02 08:45:07 PM PDT 24
Finished Aug 02 08:56:13 PM PDT 24
Peak memory 623964 kb
Host smart-87fd0252-2757-4467-a1cd-5b574a325551
User root
Command /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404129293 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.2404129293
Directory /workspace/3.chip_sw_uart_tx_rx_idx3/latest

Test location /workspace/coverage/default/3.chip_tap_straps_dev.1210013833
Short name T1101
Test name
Test status
Simulation time 7090969073 ps
CPU time 653.45 seconds
Started Aug 02 08:43:09 PM PDT 24
Finished Aug 02 08:54:02 PM PDT 24
Peak memory 624516 kb
Host smart-e89ee93c-b431-4388-9b9d-55065a682fd4
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:
new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1210013833 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.1210013833
Directory /workspace/3.chip_tap_straps_dev/latest

Test location /workspace/coverage/default/3.chip_tap_straps_prod.1025330781
Short name T1003
Test name
Test status
Simulation time 2551256739 ps
CPU time 149.65 seconds
Started Aug 02 08:43:12 PM PDT 24
Finished Aug 02 08:45:41 PM PDT 24
Peak memory 623376 kb
Host smart-c9b6bd36-957e-4e7d-b7c4-0074601af692
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom
:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1025330781 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.1025330781
Directory /workspace/3.chip_tap_straps_prod/latest

Test location /workspace/coverage/default/3.chip_tap_straps_testunlock0.1186918142
Short name T73
Test name
Test status
Simulation time 5909879098 ps
CPU time 580.35 seconds
Started Aug 02 08:45:10 PM PDT 24
Finished Aug 02 08:54:51 PM PDT 24
Peak memory 624608 kb
Host smart-a34a852d-b61e-4f51-91f9-e0b319d683af
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te
st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186918142 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_testunlock0.1186918142
Directory /workspace/3.chip_tap_straps_testunlock0/latest

Test location /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1762287904
Short name T755
Test name
Test status
Simulation time 3685750368 ps
CPU time 344.04 seconds
Started Aug 02 08:49:13 PM PDT 24
Finished Aug 02 08:54:57 PM PDT 24
Peak memory 649040 kb
Host smart-22ae2314-1878-43d0-8626-75e8c9e7524e
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762287904 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1762287904
Directory /workspace/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/31.chip_sw_all_escalation_resets.3286399245
Short name T65
Test name
Test status
Simulation time 5467350430 ps
CPU time 619.25 seconds
Started Aug 02 08:49:38 PM PDT 24
Finished Aug 02 08:59:58 PM PDT 24
Peak memory 649900 kb
Host smart-2bcc253d-862e-4573-a014-f41c538e29be
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3286399245 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_all_escalation_resets.3286399245
Directory /workspace/31.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/33.chip_sw_all_escalation_resets.2980990978
Short name T1114
Test name
Test status
Simulation time 4849527704 ps
CPU time 567.89 seconds
Started Aug 02 08:48:18 PM PDT 24
Finished Aug 02 08:57:46 PM PDT 24
Peak memory 616928 kb
Host smart-a336a095-4da7-40f6-89cc-a3646c83e49e
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2980990978 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.2980990978
Directory /workspace/33.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/34.chip_sw_all_escalation_resets.2513405468
Short name T370
Test name
Test status
Simulation time 4682726080 ps
CPU time 719.29 seconds
Started Aug 02 08:49:22 PM PDT 24
Finished Aug 02 09:01:22 PM PDT 24
Peak memory 650004 kb
Host smart-b2905a6e-4f04-486f-aeeb-5258525bbedc
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2513405468 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.2513405468
Directory /workspace/34.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3255992678
Short name T823
Test name
Test status
Simulation time 4264408408 ps
CPU time 474.92 seconds
Started Aug 02 08:51:02 PM PDT 24
Finished Aug 02 08:58:57 PM PDT 24
Peak memory 649064 kb
Host smart-55633ebf-2354-44cc-bac2-33fde79a252e
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255992678 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3255992678
Directory /workspace/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3480837715
Short name T969
Test name
Test status
Simulation time 3151247800 ps
CPU time 426.56 seconds
Started Aug 02 08:51:22 PM PDT 24
Finished Aug 02 08:58:29 PM PDT 24
Peak memory 618988 kb
Host smart-3183fd16-b13e-4ce9-b592-067f90bfe123
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480837715 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3480837715
Directory /workspace/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/37.chip_sw_all_escalation_resets.2956582523
Short name T813
Test name
Test status
Simulation time 5668715432 ps
CPU time 650.71 seconds
Started Aug 02 08:48:52 PM PDT 24
Finished Aug 02 08:59:43 PM PDT 24
Peak memory 650256 kb
Host smart-811aecea-4cc9-47f0-bbe7-5c3f0da030dc
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2956582523 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.2956582523
Directory /workspace/37.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3847116329
Short name T754
Test name
Test status
Simulation time 3890274954 ps
CPU time 396.5 seconds
Started Aug 02 08:51:15 PM PDT 24
Finished Aug 02 08:57:52 PM PDT 24
Peak memory 649056 kb
Host smart-d06c6d5c-2cca-445e-b9ef-6b7288235b18
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847116329 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3847116329
Directory /workspace/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3431782875
Short name T970
Test name
Test status
Simulation time 7383761416 ps
CPU time 548.35 seconds
Started Aug 02 08:44:33 PM PDT 24
Finished Aug 02 08:53:41 PM PDT 24
Peak memory 610548 kb
Host smart-353f739d-a3e9-4807-bbff-f39395ef3439
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3431782875 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3431782875
Directory /workspace/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.4271497850
Short name T1074
Test name
Test status
Simulation time 15108731118 ps
CPU time 3313.83 seconds
Started Aug 02 08:45:50 PM PDT 24
Finished Aug 02 09:41:05 PM PDT 24
Peak memory 610424 kb
Host smart-21b2ab56-6dad-4c29-bb09-a1d02f84b304
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271497850 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 4.chip_sw_csrng_edn_concurrency.4271497850
Directory /workspace/4.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/4.chip_sw_data_integrity_escalation.2251612418
Short name T295
Test name
Test status
Simulation time 5799613242 ps
CPU time 609.8 seconds
Started Aug 02 08:44:23 PM PDT 24
Finished Aug 02 08:54:33 PM PDT 24
Peak memory 611280 kb
Host smart-d9f942b4-c1e1-4938-8596-f6524f9ec5d5
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2251612418 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.2251612418
Directory /workspace/4.chip_sw_data_integrity_escalation/latest

Test location /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1704474562
Short name T307
Test name
Test status
Simulation time 12222144022 ps
CPU time 1075.42 seconds
Started Aug 02 08:46:55 PM PDT 24
Finished Aug 02 09:04:51 PM PDT 24
Peak memory 620416 kb
Host smart-b78ef4f9-ff4c-4c4c-943d-0dd68a858e28
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704474562 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.chip_sw_lc_ctrl_transition.1704474562
Directory /workspace/4.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.685269052
Short name T133
Test name
Test status
Simulation time 4426862984 ps
CPU time 370.66 seconds
Started Aug 02 08:43:20 PM PDT 24
Finished Aug 02 08:49:31 PM PDT 24
Peak memory 610508 kb
Host smart-17af9445-a1d5-4b21-a7fa-90d12cd5deb3
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68526905
2 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.685269052
Directory /workspace/4.chip_sw_sensor_ctrl_alert/latest

Test location /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2821232339
Short name T1149
Test name
Test status
Simulation time 9034325300 ps
CPU time 1502.01 seconds
Started Aug 02 08:44:39 PM PDT 24
Finished Aug 02 09:09:42 PM PDT 24
Peak memory 624560 kb
Host smart-9650183f-2575-4a52-b606-96dd4a22afcd
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=2821232339 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.2821232339
Directory /workspace/4.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/4.chip_sw_uart_tx_rx.903692274
Short name T358
Test name
Test status
Simulation time 3960391074 ps
CPU time 646.44 seconds
Started Aug 02 08:45:21 PM PDT 24
Finished Aug 02 08:56:08 PM PDT 24
Peak memory 624028 kb
Host smart-abd0b926-c153-4eb6-add2-1cf77c40503b
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903692274 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.903692274
Directory /workspace/4.chip_sw_uart_tx_rx/latest

Test location /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.510383877
Short name T1269
Test name
Test status
Simulation time 8094616342 ps
CPU time 1662.51 seconds
Started Aug 02 08:46:58 PM PDT 24
Finished Aug 02 09:14:42 PM PDT 24
Peak memory 623256 kb
Host smart-19996dca-8bd9-4379-ac86-42ec3acbe875
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510383877 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba
udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_
alt_clk_freq.510383877
Directory /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2881885589
Short name T1085
Test name
Test status
Simulation time 7718453506 ps
CPU time 973.62 seconds
Started Aug 02 08:44:29 PM PDT 24
Finished Aug 02 09:00:43 PM PDT 24
Peak memory 624588 kb
Host smart-06a3d689-1144-404c-b573-8ea2e9e135b8
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881885589 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx
_alt_clk_freq_low_speed.2881885589
Directory /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.1271381732
Short name T213
Test name
Test status
Simulation time 4193733336 ps
CPU time 726.83 seconds
Started Aug 02 08:46:18 PM PDT 24
Finished Aug 02 08:58:26 PM PDT 24
Peak memory 623920 kb
Host smart-c0373511-ac1a-47b6-bfe1-60cb0d083b3d
User root
Command /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271381732 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.1271381732
Directory /workspace/4.chip_sw_uart_tx_rx_idx1/latest

Test location /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.2011093136
Short name T143
Test name
Test status
Simulation time 4629991016 ps
CPU time 542.34 seconds
Started Aug 02 08:46:48 PM PDT 24
Finished Aug 02 08:55:50 PM PDT 24
Peak memory 623964 kb
Host smart-e9c482f6-d37c-41b7-ab87-3c30c61f8a71
User root
Command /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011093136 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.2011093136
Directory /workspace/4.chip_sw_uart_tx_rx_idx2/latest

Test location /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.478791899
Short name T369
Test name
Test status
Simulation time 4197198696 ps
CPU time 649.92 seconds
Started Aug 02 08:44:34 PM PDT 24
Finished Aug 02 08:55:24 PM PDT 24
Peak memory 623924 kb
Host smart-058b17e4-eafd-499f-b8d8-ce8bdbed4b26
User root
Command /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478791899 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.478791899
Directory /workspace/4.chip_sw_uart_tx_rx_idx3/latest

Test location /workspace/coverage/default/4.chip_tap_straps_dev.3637491610
Short name T1046
Test name
Test status
Simulation time 3641453021 ps
CPU time 296.24 seconds
Started Aug 02 08:43:37 PM PDT 24
Finished Aug 02 08:48:33 PM PDT 24
Peak memory 624260 kb
Host smart-938b2fda-65df-40c9-bde9-c40d49b1c669
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:
new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3637491610 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.3637491610
Directory /workspace/4.chip_tap_straps_dev/latest

Test location /workspace/coverage/default/4.chip_tap_straps_prod.2094024289
Short name T1099
Test name
Test status
Simulation time 16995763895 ps
CPU time 1576.22 seconds
Started Aug 02 08:44:19 PM PDT 24
Finished Aug 02 09:10:36 PM PDT 24
Peak memory 624516 kb
Host smart-47cd5a0e-b4cd-4f9e-bff0-8f50833d04d6
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom
:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2094024289 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.2094024289
Directory /workspace/4.chip_tap_straps_prod/latest

Test location /workspace/coverage/default/4.chip_tap_straps_rma.994822040
Short name T68
Test name
Test status
Simulation time 2952268655 ps
CPU time 256.8 seconds
Started Aug 02 08:43:54 PM PDT 24
Finished Aug 02 08:48:11 PM PDT 24
Peak memory 633196 kb
Host smart-ecfc004c-e07f-4a82-ad30-7a96e6fc2720
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994822040 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_rma.994822040
Directory /workspace/4.chip_tap_straps_rma/latest

Test location /workspace/coverage/default/4.chip_tap_straps_testunlock0.3654037456
Short name T66
Test name
Test status
Simulation time 2450295593 ps
CPU time 159.24 seconds
Started Aug 02 08:43:20 PM PDT 24
Finished Aug 02 08:45:59 PM PDT 24
Peak memory 632596 kb
Host smart-dbcc14ee-c2b7-45a0-91c4-fcdee711fab0
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te
st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654037456 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_testunlock0.3654037456
Directory /workspace/4.chip_tap_straps_testunlock0/latest

Test location /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3486716199
Short name T764
Test name
Test status
Simulation time 4187094522 ps
CPU time 381.03 seconds
Started Aug 02 08:50:36 PM PDT 24
Finished Aug 02 08:56:57 PM PDT 24
Peak memory 649424 kb
Host smart-238a63af-4c50-4e04-8001-bd6322a7cb8e
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486716199 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3486716199
Directory /workspace/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/41.chip_sw_all_escalation_resets.2949709363
Short name T788
Test name
Test status
Simulation time 6227020472 ps
CPU time 689.08 seconds
Started Aug 02 08:49:23 PM PDT 24
Finished Aug 02 09:00:52 PM PDT 24
Peak memory 650324 kb
Host smart-398d81df-379d-49a3-9732-0ce1bd8b5f73
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2949709363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.2949709363
Directory /workspace/41.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/42.chip_sw_all_escalation_resets.363177597
Short name T789
Test name
Test status
Simulation time 5361391176 ps
CPU time 461.17 seconds
Started Aug 02 08:50:38 PM PDT 24
Finished Aug 02 08:58:19 PM PDT 24
Peak memory 650312 kb
Host smart-81a6bdb9-72dc-4135-90f7-21a677c9b28c
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
363177597 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.363177597
Directory /workspace/42.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2031822419
Short name T760
Test name
Test status
Simulation time 4133182720 ps
CPU time 429.12 seconds
Started Aug 02 08:49:44 PM PDT 24
Finished Aug 02 08:56:53 PM PDT 24
Peak memory 649108 kb
Host smart-2116e7b1-dc5c-4043-a2bd-5fc00886860d
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031822419 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2031822419
Directory /workspace/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/43.chip_sw_all_escalation_resets.1714702196
Short name T383
Test name
Test status
Simulation time 6295424728 ps
CPU time 726.84 seconds
Started Aug 02 08:50:31 PM PDT 24
Finished Aug 02 09:02:38 PM PDT 24
Peak memory 650012 kb
Host smart-ffcd9622-740f-4643-818a-def2d122a009
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1714702196 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.1714702196
Directory /workspace/43.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/44.chip_sw_all_escalation_resets.3431636492
Short name T808
Test name
Test status
Simulation time 5087615080 ps
CPU time 540.15 seconds
Started Aug 02 08:50:06 PM PDT 24
Finished Aug 02 08:59:07 PM PDT 24
Peak memory 650328 kb
Host smart-7e7c611f-3d3d-423a-9068-6a35e7134517
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3431636492 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.3431636492
Directory /workspace/44.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2469881181
Short name T768
Test name
Test status
Simulation time 3507501988 ps
CPU time 410.69 seconds
Started Aug 02 08:50:38 PM PDT 24
Finished Aug 02 08:57:29 PM PDT 24
Peak memory 649156 kb
Host smart-b2cd4aab-1e3c-45b8-9416-7382c804c10b
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469881181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2469881181
Directory /workspace/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.207294885
Short name T90
Test name
Test status
Simulation time 4195848720 ps
CPU time 327.78 seconds
Started Aug 02 08:50:04 PM PDT 24
Finished Aug 02 08:55:32 PM PDT 24
Peak memory 649408 kb
Host smart-1249e05a-6d6f-49af-a99c-2372869af9d7
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207294885 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_s
w_alert_handler_lpg_sleep_mode_alerts.207294885
Directory /workspace/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/47.chip_sw_all_escalation_resets.579025291
Short name T1266
Test name
Test status
Simulation time 6302676532 ps
CPU time 666.57 seconds
Started Aug 02 08:50:30 PM PDT 24
Finished Aug 02 09:01:37 PM PDT 24
Peak memory 619688 kb
Host smart-3223653b-94b0-4a1e-9458-8a1e2a71730c
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
579025291 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.579025291
Directory /workspace/47.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/48.chip_sw_all_escalation_resets.2912315943
Short name T361
Test name
Test status
Simulation time 4643271876 ps
CPU time 625.68 seconds
Started Aug 02 08:51:24 PM PDT 24
Finished Aug 02 09:01:50 PM PDT 24
Peak memory 650140 kb
Host smart-6936135d-1082-488f-aab3-4523e31328cd
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2912315943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.2912315943
Directory /workspace/48.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.556219642
Short name T320
Test name
Test status
Simulation time 3972473192 ps
CPU time 526.51 seconds
Started Aug 02 08:51:44 PM PDT 24
Finished Aug 02 09:00:31 PM PDT 24
Peak memory 648924 kb
Host smart-292d6b12-22c6-4d11-9d8e-fe859c95cd3a
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556219642 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_s
w_alert_handler_lpg_sleep_mode_alerts.556219642
Directory /workspace/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1902063945
Short name T305
Test name
Test status
Simulation time 3847516580 ps
CPU time 533.2 seconds
Started Aug 02 08:46:54 PM PDT 24
Finished Aug 02 08:55:48 PM PDT 24
Peak memory 649348 kb
Host smart-a7c189f5-ab15-4693-9a28-cfe9246eaaea
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902063945 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_s
w_alert_handler_lpg_sleep_mode_alerts.1902063945
Directory /workspace/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/5.chip_sw_all_escalation_resets.2687422801
Short name T386
Test name
Test status
Simulation time 4841096080 ps
CPU time 535.91 seconds
Started Aug 02 08:45:58 PM PDT 24
Finished Aug 02 08:54:54 PM PDT 24
Peak memory 650120 kb
Host smart-533f6c23-b476-4021-9c2d-2584eebe21d3
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2687422801 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.2687422801
Directory /workspace/5.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.836346039
Short name T689
Test name
Test status
Simulation time 31395886150 ps
CPU time 9421.52 seconds
Started Aug 02 08:45:51 PM PDT 24
Finished Aug 02 11:22:54 PM PDT 24
Peak memory 609392 kb
Host smart-1d6ea519-0310-45bf-85b5-05ab6057a7be
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836346039 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.chip_sw_csrng_edn_concurrency.836346039
Directory /workspace/5.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/5.chip_sw_data_integrity_escalation.80351070
Short name T1246
Test name
Test status
Simulation time 4424948740 ps
CPU time 560.03 seconds
Started Aug 02 08:44:31 PM PDT 24
Finished Aug 02 08:53:51 PM PDT 24
Peak memory 611084 kb
Host smart-700cb57c-1b50-42ef-9f02-2ee25ebf18e8
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=80351070 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.80351070
Directory /workspace/5.chip_sw_data_integrity_escalation/latest

Test location /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1877562602
Short name T287
Test name
Test status
Simulation time 4524132098 ps
CPU time 538.48 seconds
Started Aug 02 08:45:02 PM PDT 24
Finished Aug 02 08:54:00 PM PDT 24
Peak memory 624744 kb
Host smart-f26c85df-f3e3-4c97-8c3e-dd61311f74ce
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877562602 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.chip_sw_lc_ctrl_transition.1877562602
Directory /workspace/5.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/50.chip_sw_all_escalation_resets.230725976
Short name T763
Test name
Test status
Simulation time 5782081600 ps
CPU time 759.95 seconds
Started Aug 02 08:50:38 PM PDT 24
Finished Aug 02 09:03:18 PM PDT 24
Peak memory 650320 kb
Host smart-43283b00-5b66-4d8f-85da-0ab99e44e20f
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
230725976 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.230725976
Directory /workspace/50.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.4273933943
Short name T751
Test name
Test status
Simulation time 3350798604 ps
CPU time 412.43 seconds
Started Aug 02 08:51:57 PM PDT 24
Finished Aug 02 08:58:50 PM PDT 24
Peak memory 649072 kb
Host smart-17761052-b525-4043-8b47-c6b8bbc46b98
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273933943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_
sw_alert_handler_lpg_sleep_mode_alerts.4273933943
Directory /workspace/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/51.chip_sw_all_escalation_resets.3273040574
Short name T743
Test name
Test status
Simulation time 4505617706 ps
CPU time 594.13 seconds
Started Aug 02 08:50:45 PM PDT 24
Finished Aug 02 09:00:39 PM PDT 24
Peak memory 650336 kb
Host smart-b36f1ddd-3192-4598-a2c2-d9aed9ee5ac4
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3273040574 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.3273040574
Directory /workspace/51.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2338223713
Short name T800
Test name
Test status
Simulation time 3337184132 ps
CPU time 352.46 seconds
Started Aug 02 08:51:45 PM PDT 24
Finished Aug 02 08:57:37 PM PDT 24
Peak memory 649180 kb
Host smart-928cb731-34c8-4527-8026-46b5c66862ad
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338223713 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2338223713
Directory /workspace/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/53.chip_sw_all_escalation_resets.2964878924
Short name T1333
Test name
Test status
Simulation time 6479950670 ps
CPU time 630.16 seconds
Started Aug 02 08:52:24 PM PDT 24
Finished Aug 02 09:02:55 PM PDT 24
Peak memory 650460 kb
Host smart-705d402c-918a-40f4-8308-b6c379934af7
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2964878924 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.2964878924
Directory /workspace/53.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3346536421
Short name T783
Test name
Test status
Simulation time 3739138480 ps
CPU time 406.42 seconds
Started Aug 02 08:52:13 PM PDT 24
Finished Aug 02 08:58:59 PM PDT 24
Peak memory 649192 kb
Host smart-54fb8591-2483-4c9c-a01b-f684663f3231
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346536421 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3346536421
Directory /workspace/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3728163735
Short name T803
Test name
Test status
Simulation time 3915561608 ps
CPU time 339.23 seconds
Started Aug 02 08:52:04 PM PDT 24
Finished Aug 02 08:57:43 PM PDT 24
Peak memory 649172 kb
Host smart-1898c766-1eae-472f-9a8e-01936888e273
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728163735 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3728163735
Directory /workspace/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/55.chip_sw_all_escalation_resets.3578056554
Short name T773
Test name
Test status
Simulation time 5031675148 ps
CPU time 580.23 seconds
Started Aug 02 08:51:29 PM PDT 24
Finished Aug 02 09:01:10 PM PDT 24
Peak memory 650236 kb
Host smart-95c9d5b3-a381-433f-82c0-24d496147b32
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3578056554 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.3578056554
Directory /workspace/55.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.2816460748
Short name T809
Test name
Test status
Simulation time 4016882856 ps
CPU time 421.25 seconds
Started Aug 02 08:53:40 PM PDT 24
Finished Aug 02 09:00:42 PM PDT 24
Peak memory 649168 kb
Host smart-357365cd-78ed-4ea8-adc1-f3c67ae470f4
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816460748 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2816460748
Directory /workspace/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/56.chip_sw_all_escalation_resets.457495679
Short name T271
Test name
Test status
Simulation time 4509077172 ps
CPU time 417.46 seconds
Started Aug 02 08:52:56 PM PDT 24
Finished Aug 02 08:59:53 PM PDT 24
Peak memory 650672 kb
Host smart-83b92e45-800c-4c4b-a9f4-2c3de1b256f7
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
457495679 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.457495679
Directory /workspace/56.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1458739796
Short name T1286
Test name
Test status
Simulation time 4396230842 ps
CPU time 407.21 seconds
Started Aug 02 08:52:19 PM PDT 24
Finished Aug 02 08:59:07 PM PDT 24
Peak memory 649016 kb
Host smart-8bb47de4-dd14-48fb-a3a3-7502a2aad3d0
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458739796 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1458739796
Directory /workspace/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/57.chip_sw_all_escalation_resets.3036237975
Short name T757
Test name
Test status
Simulation time 4706395856 ps
CPU time 787.01 seconds
Started Aug 02 08:51:44 PM PDT 24
Finished Aug 02 09:04:52 PM PDT 24
Peak memory 649996 kb
Host smart-603742f4-bc6e-496d-9f87-b4cd5ccd6f11
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3036237975 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.3036237975
Directory /workspace/57.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1273604074
Short name T1209
Test name
Test status
Simulation time 4456119168 ps
CPU time 344.78 seconds
Started Aug 02 08:54:52 PM PDT 24
Finished Aug 02 09:00:37 PM PDT 24
Peak memory 649500 kb
Host smart-bdcbafef-6ab9-4a7d-98eb-43cc7bb143af
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273604074 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1273604074
Directory /workspace/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/58.chip_sw_all_escalation_resets.1608834074
Short name T785
Test name
Test status
Simulation time 4880217356 ps
CPU time 502.13 seconds
Started Aug 02 08:52:11 PM PDT 24
Finished Aug 02 09:00:33 PM PDT 24
Peak memory 650316 kb
Host smart-1cb3a497-588b-4f30-bf8d-1bf5845d04fc
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1608834074 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.1608834074
Directory /workspace/58.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.60101872
Short name T96
Test name
Test status
Simulation time 3761184082 ps
CPU time 343.43 seconds
Started Aug 02 08:52:32 PM PDT 24
Finished Aug 02 08:58:16 PM PDT 24
Peak memory 648856 kb
Host smart-17673f37-6585-4805-a645-3605b3fdf6e5
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60101872 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_
escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw
_alert_handler_lpg_sleep_mode_alerts.60101872
Directory /workspace/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/59.chip_sw_all_escalation_resets.917728186
Short name T1112
Test name
Test status
Simulation time 5326179576 ps
CPU time 453.36 seconds
Started Aug 02 08:53:07 PM PDT 24
Finished Aug 02 09:00:40 PM PDT 24
Peak memory 650208 kb
Host smart-e6cb65e0-b63d-418d-a447-e557078df48f
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
917728186 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.917728186
Directory /workspace/59.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.1363014200
Short name T761
Test name
Test status
Simulation time 3419180914 ps
CPU time 430.61 seconds
Started Aug 02 08:46:50 PM PDT 24
Finished Aug 02 08:54:01 PM PDT 24
Peak memory 648780 kb
Host smart-06820e90-d624-48c2-a09c-94efc8f1e721
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363014200 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_s
w_alert_handler_lpg_sleep_mode_alerts.1363014200
Directory /workspace/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.1581562409
Short name T1389
Test name
Test status
Simulation time 17795182458 ps
CPU time 3745.6 seconds
Started Aug 02 08:46:09 PM PDT 24
Finished Aug 02 09:48:35 PM PDT 24
Peak memory 610328 kb
Host smart-46beee66-de44-4527-b616-d5678ec078ee
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581562409 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 6.chip_sw_csrng_edn_concurrency.1581562409
Directory /workspace/6.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2136993702
Short name T188
Test name
Test status
Simulation time 6554740405 ps
CPU time 611.26 seconds
Started Aug 02 08:45:29 PM PDT 24
Finished Aug 02 08:55:41 PM PDT 24
Peak memory 620484 kb
Host smart-2b02b907-bcc7-4c0d-9744-a360a2b64927
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136993702 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.chip_sw_lc_ctrl_transition.2136993702
Directory /workspace/6.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2807298361
Short name T1038
Test name
Test status
Simulation time 13607936130 ps
CPU time 2052.36 seconds
Started Aug 02 08:46:44 PM PDT 24
Finished Aug 02 09:20:57 PM PDT 24
Peak memory 623132 kb
Host smart-00925426-131b-4749-8c8f-5d6befe740ab
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=2807298361 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.2807298361
Directory /workspace/6.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.670337611
Short name T1387
Test name
Test status
Simulation time 3870263800 ps
CPU time 366.47 seconds
Started Aug 02 08:52:09 PM PDT 24
Finished Aug 02 08:58:16 PM PDT 24
Peak memory 649060 kb
Host smart-50178adf-9def-4104-a3cd-be3f84934ade
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670337611 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_s
w_alert_handler_lpg_sleep_mode_alerts.670337611
Directory /workspace/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/60.chip_sw_all_escalation_resets.2099730730
Short name T325
Test name
Test status
Simulation time 5652615540 ps
CPU time 556.24 seconds
Started Aug 02 08:52:39 PM PDT 24
Finished Aug 02 09:01:56 PM PDT 24
Peak memory 650564 kb
Host smart-f313286c-9e1d-4edc-943f-0b2f41250201
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2099730730 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.2099730730
Directory /workspace/60.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2467325627
Short name T762
Test name
Test status
Simulation time 3697481968 ps
CPU time 323.84 seconds
Started Aug 02 08:52:25 PM PDT 24
Finished Aug 02 08:57:49 PM PDT 24
Peak memory 649092 kb
Host smart-9f828db3-3795-4896-8a8e-e02a039572e5
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467325627 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2467325627
Directory /workspace/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/61.chip_sw_all_escalation_resets.162550773
Short name T321
Test name
Test status
Simulation time 6112394840 ps
CPU time 708.37 seconds
Started Aug 02 08:53:12 PM PDT 24
Finished Aug 02 09:05:01 PM PDT 24
Peak memory 650104 kb
Host smart-031fac6c-e8db-4a02-89bf-0ae5dec1f50a
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
162550773 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.162550773
Directory /workspace/61.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2276043282
Short name T753
Test name
Test status
Simulation time 4192408428 ps
CPU time 371.23 seconds
Started Aug 02 08:53:29 PM PDT 24
Finished Aug 02 08:59:40 PM PDT 24
Peak memory 648972 kb
Host smart-b6228164-bfe7-44b9-86b1-00aaba3afb54
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276043282 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2276043282
Directory /workspace/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/62.chip_sw_all_escalation_resets.2812955369
Short name T750
Test name
Test status
Simulation time 5838518374 ps
CPU time 447.3 seconds
Started Aug 02 08:55:07 PM PDT 24
Finished Aug 02 09:02:35 PM PDT 24
Peak memory 616908 kb
Host smart-a45624ed-38ff-4f03-afe8-1b2408d21bb6
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2812955369 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.2812955369
Directory /workspace/62.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/63.chip_sw_all_escalation_resets.1837850472
Short name T1344
Test name
Test status
Simulation time 4473835728 ps
CPU time 522.48 seconds
Started Aug 02 08:52:03 PM PDT 24
Finished Aug 02 09:00:46 PM PDT 24
Peak memory 650372 kb
Host smart-652da1f8-3207-4713-8aac-78bbf08edc48
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1837850472 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.1837850472
Directory /workspace/63.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3739036120
Short name T781
Test name
Test status
Simulation time 3394446256 ps
CPU time 384.48 seconds
Started Aug 02 08:53:21 PM PDT 24
Finished Aug 02 08:59:46 PM PDT 24
Peak memory 649240 kb
Host smart-a6a13112-0faf-47a9-8d02-1d7890778401
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739036120 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3739036120
Directory /workspace/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/64.chip_sw_all_escalation_resets.2046786312
Short name T772
Test name
Test status
Simulation time 4887305350 ps
CPU time 583.72 seconds
Started Aug 02 08:53:00 PM PDT 24
Finished Aug 02 09:02:44 PM PDT 24
Peak memory 650040 kb
Host smart-c89e1038-6343-42c3-b3e3-76b93b1ddf82
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2046786312 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.2046786312
Directory /workspace/64.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2963400256
Short name T741
Test name
Test status
Simulation time 3558016264 ps
CPU time 408.86 seconds
Started Aug 02 08:52:39 PM PDT 24
Finished Aug 02 08:59:28 PM PDT 24
Peak memory 648976 kb
Host smart-8613a83c-2be7-4819-a9dc-bff000fd961f
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963400256 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2963400256
Directory /workspace/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/65.chip_sw_all_escalation_resets.2774274498
Short name T385
Test name
Test status
Simulation time 5811880508 ps
CPU time 565.16 seconds
Started Aug 02 08:52:36 PM PDT 24
Finished Aug 02 09:02:02 PM PDT 24
Peak memory 650316 kb
Host smart-f614a004-f049-4975-ab8a-d17f42785927
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2774274498 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.2774274498
Directory /workspace/65.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/66.chip_sw_all_escalation_resets.259092073
Short name T253
Test name
Test status
Simulation time 5600561048 ps
CPU time 683.81 seconds
Started Aug 02 08:53:11 PM PDT 24
Finished Aug 02 09:04:35 PM PDT 24
Peak memory 650316 kb
Host smart-c0e46d8b-0594-446b-863a-94bb1bf10078
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
259092073 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.259092073
Directory /workspace/66.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.4192918384
Short name T251
Test name
Test status
Simulation time 4323441128 ps
CPU time 441.25 seconds
Started Aug 02 08:56:14 PM PDT 24
Finished Aug 02 09:03:35 PM PDT 24
Peak memory 649324 kb
Host smart-56b63727-30e6-4c2e-9117-e165fcfd44f5
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192918384 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_
sw_alert_handler_lpg_sleep_mode_alerts.4192918384
Directory /workspace/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/67.chip_sw_all_escalation_resets.269073357
Short name T799
Test name
Test status
Simulation time 5836050000 ps
CPU time 536.3 seconds
Started Aug 02 08:53:08 PM PDT 24
Finished Aug 02 09:02:04 PM PDT 24
Peak memory 650352 kb
Host smart-f907b225-f0c8-4eb0-8503-f9211eb9c398
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
269073357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.269073357
Directory /workspace/67.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1449277360
Short name T793
Test name
Test status
Simulation time 3989602492 ps
CPU time 435.52 seconds
Started Aug 02 08:55:52 PM PDT 24
Finished Aug 02 09:03:08 PM PDT 24
Peak memory 649124 kb
Host smart-40dc6b41-0966-46e0-bd2b-084c7ce33292
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449277360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1449277360
Directory /workspace/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2759182770
Short name T1163
Test name
Test status
Simulation time 3225540504 ps
CPU time 460.64 seconds
Started Aug 02 08:55:01 PM PDT 24
Finished Aug 02 09:02:42 PM PDT 24
Peak memory 649144 kb
Host smart-01f2f42d-b25f-4b53-ba32-02503a5401ff
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759182770 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2759182770
Directory /workspace/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/69.chip_sw_all_escalation_resets.1893418006
Short name T742
Test name
Test status
Simulation time 6172242840 ps
CPU time 625.02 seconds
Started Aug 02 08:54:42 PM PDT 24
Finished Aug 02 09:05:07 PM PDT 24
Peak memory 650280 kb
Host smart-0645b848-ea61-4a09-859b-069ed2f2fd31
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1893418006 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.1893418006
Directory /workspace/69.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/7.chip_sw_all_escalation_resets.1104621374
Short name T153
Test name
Test status
Simulation time 4838915744 ps
CPU time 661.91 seconds
Started Aug 02 08:45:15 PM PDT 24
Finished Aug 02 08:56:17 PM PDT 24
Peak memory 619704 kb
Host smart-a3c91343-867e-453e-8775-8e21ec615817
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1104621374 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.1104621374
Directory /workspace/7.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2306622910
Short name T1214
Test name
Test status
Simulation time 20775524552 ps
CPU time 5209.08 seconds
Started Aug 02 08:47:09 PM PDT 24
Finished Aug 02 10:13:59 PM PDT 24
Peak memory 610156 kb
Host smart-b37979ec-f25a-4f9d-9e57-bf1c3fec8a75
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306622910 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 7.chip_sw_csrng_edn_concurrency.2306622910
Directory /workspace/7.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.790806304
Short name T1125
Test name
Test status
Simulation time 11615053009 ps
CPU time 1040.03 seconds
Started Aug 02 08:46:14 PM PDT 24
Finished Aug 02 09:03:34 PM PDT 24
Peak memory 624760 kb
Host smart-83c7b9f1-9bc0-4ef7-b528-da08eb6e6e3a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790806304 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.chip_sw_lc_ctrl_transition.790806304
Directory /workspace/7.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2295906847
Short name T955
Test name
Test status
Simulation time 4087916632 ps
CPU time 480.23 seconds
Started Aug 02 08:45:56 PM PDT 24
Finished Aug 02 08:53:57 PM PDT 24
Peak memory 624492 kb
Host smart-f528c918-7ebd-485f-a39a-8da5081c6209
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=2295906847 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.2295906847
Directory /workspace/7.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2134153293
Short name T384
Test name
Test status
Simulation time 3822820280 ps
CPU time 406.64 seconds
Started Aug 02 08:54:26 PM PDT 24
Finished Aug 02 09:01:12 PM PDT 24
Peak memory 649104 kb
Host smart-a645093e-e2fe-46f2-9d1f-186a96dd8b81
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134153293 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2134153293
Directory /workspace/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/71.chip_sw_all_escalation_resets.2611145596
Short name T322
Test name
Test status
Simulation time 6267730836 ps
CPU time 673.6 seconds
Started Aug 02 08:53:52 PM PDT 24
Finished Aug 02 09:05:06 PM PDT 24
Peak memory 650452 kb
Host smart-84697698-f0b1-4766-b0c7-f2181ce76eaa
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2611145596 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.2611145596
Directory /workspace/71.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3768126746
Short name T154
Test name
Test status
Simulation time 3811385498 ps
CPU time 335.84 seconds
Started Aug 02 08:53:07 PM PDT 24
Finished Aug 02 08:58:43 PM PDT 24
Peak memory 619032 kb
Host smart-81b051e0-200f-4c61-a941-6c1a09c45bce
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768126746 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3768126746
Directory /workspace/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/72.chip_sw_all_escalation_resets.43905456
Short name T1035
Test name
Test status
Simulation time 4905494664 ps
CPU time 592.06 seconds
Started Aug 02 08:53:07 PM PDT 24
Finished Aug 02 09:03:00 PM PDT 24
Peak memory 616940 kb
Host smart-dca0e508-18f3-4fad-8533-a8369ed8d1f7
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
43905456 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.43905456
Directory /workspace/72.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1809524935
Short name T1156
Test name
Test status
Simulation time 4181841300 ps
CPU time 344.23 seconds
Started Aug 02 08:54:03 PM PDT 24
Finished Aug 02 08:59:47 PM PDT 24
Peak memory 648948 kb
Host smart-45d5fc2a-02de-41f9-a374-58443449a6a5
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809524935 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1809524935
Directory /workspace/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/73.chip_sw_all_escalation_resets.1953428363
Short name T1401
Test name
Test status
Simulation time 5551669116 ps
CPU time 502.57 seconds
Started Aug 02 08:54:35 PM PDT 24
Finished Aug 02 09:02:58 PM PDT 24
Peak memory 616912 kb
Host smart-036d1086-54ca-4696-957a-9e9263e113fa
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1953428363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.1953428363
Directory /workspace/73.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3960461121
Short name T737
Test name
Test status
Simulation time 3566274470 ps
CPU time 330.54 seconds
Started Aug 02 08:53:52 PM PDT 24
Finished Aug 02 08:59:23 PM PDT 24
Peak memory 649332 kb
Host smart-676c580a-7c5d-49f3-a063-f936972221d2
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960461121 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3960461121
Directory /workspace/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/74.chip_sw_all_escalation_resets.2243283309
Short name T805
Test name
Test status
Simulation time 4072765740 ps
CPU time 485.1 seconds
Started Aug 02 08:53:37 PM PDT 24
Finished Aug 02 09:01:42 PM PDT 24
Peak memory 650008 kb
Host smart-ee185b1b-949b-438d-b9cd-ad3d5d87e583
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2243283309 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.2243283309
Directory /workspace/74.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.311118844
Short name T790
Test name
Test status
Simulation time 3515942360 ps
CPU time 304.21 seconds
Started Aug 02 08:54:13 PM PDT 24
Finished Aug 02 08:59:18 PM PDT 24
Peak memory 649212 kb
Host smart-a5d82d64-3696-4a62-ae1c-108aff54dbfb
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311118844 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_s
w_alert_handler_lpg_sleep_mode_alerts.311118844
Directory /workspace/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1329030868
Short name T1208
Test name
Test status
Simulation time 3001299952 ps
CPU time 314.77 seconds
Started Aug 02 08:53:35 PM PDT 24
Finished Aug 02 08:58:50 PM PDT 24
Peak memory 649144 kb
Host smart-1955b6ca-399d-468b-a90d-3a5a4c97d576
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329030868 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1329030868
Directory /workspace/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/76.chip_sw_all_escalation_resets.2055723196
Short name T413
Test name
Test status
Simulation time 5538616108 ps
CPU time 645.32 seconds
Started Aug 02 08:54:21 PM PDT 24
Finished Aug 02 09:05:06 PM PDT 24
Peak memory 650268 kb
Host smart-36416319-ea56-42ff-8905-db46b1e3a1a3
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2055723196 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.2055723196
Directory /workspace/76.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.952434023
Short name T419
Test name
Test status
Simulation time 3329311640 ps
CPU time 307.3 seconds
Started Aug 02 08:53:41 PM PDT 24
Finished Aug 02 08:58:48 PM PDT 24
Peak memory 648828 kb
Host smart-3b7e28d4-b0ba-4a76-8a8e-da679b4353b1
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952434023 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_s
w_alert_handler_lpg_sleep_mode_alerts.952434023
Directory /workspace/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1501210434
Short name T93
Test name
Test status
Simulation time 3087770414 ps
CPU time 323.73 seconds
Started Aug 02 08:53:25 PM PDT 24
Finished Aug 02 08:58:48 PM PDT 24
Peak memory 649648 kb
Host smart-b982e73d-7054-4008-b953-17382622dff9
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501210434 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1501210434
Directory /workspace/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3233436387
Short name T299
Test name
Test status
Simulation time 3717122136 ps
CPU time 276.81 seconds
Started Aug 02 08:54:29 PM PDT 24
Finished Aug 02 08:59:06 PM PDT 24
Peak memory 648860 kb
Host smart-a35ed570-ac3d-4ebd-bdbc-703282f2675c
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233436387 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3233436387
Directory /workspace/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2235610722
Short name T426
Test name
Test status
Simulation time 3042800096 ps
CPU time 407.73 seconds
Started Aug 02 08:46:28 PM PDT 24
Finished Aug 02 08:53:17 PM PDT 24
Peak memory 649428 kb
Host smart-b173e3e4-6c69-4178-ad6b-97dfa02c3054
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235610722 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_s
w_alert_handler_lpg_sleep_mode_alerts.2235610722
Directory /workspace/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/8.chip_sw_all_escalation_resets.2342994411
Short name T387
Test name
Test status
Simulation time 5903340740 ps
CPU time 646.6 seconds
Started Aug 02 08:50:12 PM PDT 24
Finished Aug 02 09:00:59 PM PDT 24
Peak memory 650312 kb
Host smart-658a4ad7-5276-418c-a1dd-042c23a959aa
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2342994411 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.2342994411
Directory /workspace/8.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.3435834534
Short name T411
Test name
Test status
Simulation time 22083168544 ps
CPU time 5483.44 seconds
Started Aug 02 08:47:15 PM PDT 24
Finished Aug 02 10:18:39 PM PDT 24
Peak memory 609336 kb
Host smart-359f644c-fd84-44ff-80e4-8ec723858399
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435834534 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 8.chip_sw_csrng_edn_concurrency.3435834534
Directory /workspace/8.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2216687476
Short name T347
Test name
Test status
Simulation time 8774289588 ps
CPU time 1409.47 seconds
Started Aug 02 08:46:21 PM PDT 24
Finished Aug 02 09:09:50 PM PDT 24
Peak memory 624496 kb
Host smart-107ebd5e-a8af-4e27-8b24-8c46c010a12c
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=2216687476 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.2216687476
Directory /workspace/8.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.4283902533
Short name T759
Test name
Test status
Simulation time 3653041608 ps
CPU time 309.98 seconds
Started Aug 02 08:54:04 PM PDT 24
Finished Aug 02 08:59:14 PM PDT 24
Peak memory 649036 kb
Host smart-480369e8-f4e2-4b04-a6ad-378134d0e5c1
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283902533 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_
sw_alert_handler_lpg_sleep_mode_alerts.4283902533
Directory /workspace/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/80.chip_sw_all_escalation_resets.3357931521
Short name T974
Test name
Test status
Simulation time 5040971840 ps
CPU time 479.39 seconds
Started Aug 02 08:53:41 PM PDT 24
Finished Aug 02 09:01:41 PM PDT 24
Peak memory 619644 kb
Host smart-2f9f1252-ebd6-481b-9b18-da7af8c7ed05
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3357931521 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.3357931521
Directory /workspace/80.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/82.chip_sw_all_escalation_resets.467648704
Short name T1060
Test name
Test status
Simulation time 5461102872 ps
CPU time 636.87 seconds
Started Aug 02 08:53:18 PM PDT 24
Finished Aug 02 09:03:55 PM PDT 24
Peak memory 650316 kb
Host smart-a673bec1-51b0-4dae-94a9-c2fa2c285a73
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
467648704 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.467648704
Directory /workspace/82.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.4120288406
Short name T398
Test name
Test status
Simulation time 3352561550 ps
CPU time 376.92 seconds
Started Aug 02 08:54:26 PM PDT 24
Finished Aug 02 09:00:43 PM PDT 24
Peak memory 648820 kb
Host smart-9f78a4c5-8c31-43ae-a20a-1c9246852d10
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120288406 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_
sw_alert_handler_lpg_sleep_mode_alerts.4120288406
Directory /workspace/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/83.chip_sw_all_escalation_resets.1156392503
Short name T1338
Test name
Test status
Simulation time 5011497932 ps
CPU time 460.11 seconds
Started Aug 02 08:56:16 PM PDT 24
Finished Aug 02 09:03:57 PM PDT 24
Peak memory 650088 kb
Host smart-e4f80275-1227-48c4-8327-926dbb1ac457
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1156392503 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.1156392503
Directory /workspace/83.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1801976293
Short name T736
Test name
Test status
Simulation time 4583496444 ps
CPU time 374.74 seconds
Started Aug 02 08:54:31 PM PDT 24
Finished Aug 02 09:00:46 PM PDT 24
Peak memory 649588 kb
Host smart-b938b5dd-18ab-47e3-9ecd-7cdb1c0af843
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801976293 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1801976293
Directory /workspace/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/84.chip_sw_all_escalation_resets.1307222841
Short name T791
Test name
Test status
Simulation time 6058985532 ps
CPU time 545.08 seconds
Started Aug 02 08:54:30 PM PDT 24
Finished Aug 02 09:03:35 PM PDT 24
Peak memory 650332 kb
Host smart-ce8b8d6f-d229-4133-8a2f-e80b454603d5
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1307222841 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.1307222841
Directory /workspace/84.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.4100955564
Short name T392
Test name
Test status
Simulation time 3170080376 ps
CPU time 373.29 seconds
Started Aug 02 08:54:27 PM PDT 24
Finished Aug 02 09:00:40 PM PDT 24
Peak memory 649008 kb
Host smart-b4526f8f-6e67-4edd-88ff-d6946d8d1473
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100955564 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_
sw_alert_handler_lpg_sleep_mode_alerts.4100955564
Directory /workspace/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/85.chip_sw_all_escalation_resets.1630745083
Short name T748
Test name
Test status
Simulation time 5582460520 ps
CPU time 662.61 seconds
Started Aug 02 08:55:43 PM PDT 24
Finished Aug 02 09:06:46 PM PDT 24
Peak memory 650276 kb
Host smart-a09ed399-7f10-401e-a05b-60b8ac6976d9
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1630745083 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.1630745083
Directory /workspace/85.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/86.chip_sw_all_escalation_resets.4084573545
Short name T222
Test name
Test status
Simulation time 5784333648 ps
CPU time 638.35 seconds
Started Aug 02 08:54:46 PM PDT 24
Finished Aug 02 09:05:24 PM PDT 24
Peak memory 650356 kb
Host smart-4a32b4fa-a3b7-472b-954c-792571f09781
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4084573545 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.4084573545
Directory /workspace/86.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/87.chip_sw_all_escalation_resets.388748259
Short name T771
Test name
Test status
Simulation time 5047093108 ps
CPU time 550.13 seconds
Started Aug 02 08:55:08 PM PDT 24
Finished Aug 02 09:04:19 PM PDT 24
Peak memory 649916 kb
Host smart-b85d7b17-08ff-4896-9704-26ca8e892ac8
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
388748259 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.388748259
Directory /workspace/87.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1108859869
Short name T326
Test name
Test status
Simulation time 3367295784 ps
CPU time 364.52 seconds
Started Aug 02 08:56:11 PM PDT 24
Finished Aug 02 09:02:15 PM PDT 24
Peak memory 649220 kb
Host smart-4ffa3bc4-e838-4e84-a23e-c5a6d5384ea4
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108859869 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1108859869
Directory /workspace/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/88.chip_sw_all_escalation_resets.3073007986
Short name T388
Test name
Test status
Simulation time 4881890992 ps
CPU time 442.76 seconds
Started Aug 02 08:57:44 PM PDT 24
Finished Aug 02 09:05:07 PM PDT 24
Peak memory 650352 kb
Host smart-a36979ea-94c3-4d37-8f9f-037c5a08068c
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3073007986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.3073007986
Directory /workspace/88.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3648096183
Short name T744
Test name
Test status
Simulation time 3790640630 ps
CPU time 243.29 seconds
Started Aug 02 08:54:54 PM PDT 24
Finished Aug 02 08:58:58 PM PDT 24
Peak memory 649064 kb
Host smart-8479c54d-4a56-436a-a9f9-bceac019b833
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648096183 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3648096183
Directory /workspace/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/89.chip_sw_all_escalation_resets.1782675918
Short name T796
Test name
Test status
Simulation time 4938487168 ps
CPU time 467.37 seconds
Started Aug 02 08:54:48 PM PDT 24
Finished Aug 02 09:02:36 PM PDT 24
Peak memory 650336 kb
Host smart-949873a8-170b-4739-ab18-8d01ebd8c5fb
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1782675918 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.1782675918
Directory /workspace/89.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.4030246334
Short name T776
Test name
Test status
Simulation time 3505474836 ps
CPU time 385.16 seconds
Started Aug 02 08:46:37 PM PDT 24
Finished Aug 02 08:53:03 PM PDT 24
Peak memory 649152 kb
Host smart-d21677ff-2963-4891-afa0-f4bbdc49363b
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030246334 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_s
w_alert_handler_lpg_sleep_mode_alerts.4030246334
Directory /workspace/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/9.chip_sw_all_escalation_resets.1883692529
Short name T692
Test name
Test status
Simulation time 5394662200 ps
CPU time 749.76 seconds
Started Aug 02 08:48:07 PM PDT 24
Finished Aug 02 09:00:37 PM PDT 24
Peak memory 650572 kb
Host smart-f90c5cc5-c411-48e5-87a6-4b8c29ce47ea
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1883692529 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.1883692529
Directory /workspace/9.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.234807088
Short name T691
Test name
Test status
Simulation time 26924997816 ps
CPU time 5554.05 seconds
Started Aug 02 08:46:59 PM PDT 24
Finished Aug 02 10:19:34 PM PDT 24
Peak memory 610272 kb
Host smart-bafe1f4c-323d-47d1-af65-8608d14ef18b
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234807088 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.chip_sw_csrng_edn_concurrency.234807088
Directory /workspace/9.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.525930656
Short name T1166
Test name
Test status
Simulation time 4773217920 ps
CPU time 486.16 seconds
Started Aug 02 08:48:10 PM PDT 24
Finished Aug 02 08:56:16 PM PDT 24
Peak memory 620364 kb
Host smart-66ee890a-9a15-46eb-9aa1-18324eae78b4
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525930656 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.chip_sw_lc_ctrl_transition.525930656
Directory /workspace/9.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.370119368
Short name T1047
Test name
Test status
Simulation time 4543777000 ps
CPU time 620.68 seconds
Started Aug 02 08:46:43 PM PDT 24
Finished Aug 02 08:57:04 PM PDT 24
Peak memory 624464 kb
Host smart-93d5ad22-2810-494f-87e6-b42483bf0bd5
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=370119368 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.370119368
Directory /workspace/9.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/90.chip_sw_all_escalation_resets.2213302663
Short name T1151
Test name
Test status
Simulation time 5103924160 ps
CPU time 565.08 seconds
Started Aug 02 08:54:28 PM PDT 24
Finished Aug 02 09:03:53 PM PDT 24
Peak memory 650340 kb
Host smart-f8a02342-1ed1-40b1-b1d5-01adce19f59f
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2213302663 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.2213302663
Directory /workspace/90.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/91.chip_sw_all_escalation_resets.2463686265
Short name T101
Test name
Test status
Simulation time 5121734964 ps
CPU time 491.25 seconds
Started Aug 02 08:56:07 PM PDT 24
Finished Aug 02 09:04:19 PM PDT 24
Peak memory 650056 kb
Host smart-81cf5698-e162-47b9-84fb-48d7b0663920
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2463686265 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.2463686265
Directory /workspace/91.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/92.chip_sw_all_escalation_resets.627741631
Short name T94
Test name
Test status
Simulation time 5767351246 ps
CPU time 667.67 seconds
Started Aug 02 08:55:01 PM PDT 24
Finished Aug 02 09:06:09 PM PDT 24
Peak memory 650864 kb
Host smart-c263d07a-589d-4798-9470-79197c52b341
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
627741631 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.627741631
Directory /workspace/92.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/94.chip_sw_all_escalation_resets.2094192629
Short name T729
Test name
Test status
Simulation time 5795000520 ps
CPU time 616.99 seconds
Started Aug 02 08:54:38 PM PDT 24
Finished Aug 02 09:04:56 PM PDT 24
Peak memory 650296 kb
Host smart-852f676f-418c-48f5-9af7-13e9db0d0aa0
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2094192629 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.2094192629
Directory /workspace/94.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/95.chip_sw_all_escalation_resets.2542057638
Short name T794
Test name
Test status
Simulation time 4695545036 ps
CPU time 627.06 seconds
Started Aug 02 08:57:06 PM PDT 24
Finished Aug 02 09:07:33 PM PDT 24
Peak memory 650284 kb
Host smart-a5cabd7b-d11c-4645-9648-720f173bfc09
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2542057638 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.2542057638
Directory /workspace/95.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/96.chip_sw_all_escalation_resets.1225771143
Short name T815
Test name
Test status
Simulation time 5680225232 ps
CPU time 581.66 seconds
Started Aug 02 08:54:56 PM PDT 24
Finished Aug 02 09:04:38 PM PDT 24
Peak memory 650372 kb
Host smart-92863a3f-c761-4c47-9748-88e9e3b0d38e
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1225771143 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.1225771143
Directory /workspace/96.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/97.chip_sw_all_escalation_resets.1966230265
Short name T820
Test name
Test status
Simulation time 4360292160 ps
CPU time 508.43 seconds
Started Aug 02 08:55:04 PM PDT 24
Finished Aug 02 09:03:33 PM PDT 24
Peak memory 650396 kb
Host smart-2a1849e0-ac6e-400c-8782-c0481adf35e6
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1966230265 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.1966230265
Directory /workspace/97.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/98.chip_sw_all_escalation_resets.3106896735
Short name T1385
Test name
Test status
Simulation time 4564547166 ps
CPU time 550.26 seconds
Started Aug 02 08:55:21 PM PDT 24
Finished Aug 02 09:04:32 PM PDT 24
Peak memory 650384 kb
Host smart-18c8c006-01d0-45c7-9f69-ccc1d124d433
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3106896735 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.3106896735
Directory /workspace/98.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/99.chip_sw_all_escalation_resets.1477251174
Short name T828
Test name
Test status
Simulation time 5288589188 ps
CPU time 550.99 seconds
Started Aug 02 08:55:46 PM PDT 24
Finished Aug 02 09:04:57 PM PDT 24
Peak memory 649960 kb
Host smart-4a0ae1c1-b4af-49f2-80da-15fc7994f010
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1477251174 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.1477251174
Directory /workspace/99.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1961797458
Short name T197
Test name
Test status
Simulation time 4912760560 ps
CPU time 230.13 seconds
Started Aug 02 08:09:51 PM PDT 24
Finished Aug 02 08:13:41 PM PDT 24
Peak memory 649156 kb
Host smart-9ba602a4-40df-4954-a937-fa8e34aa4606
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961797458 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 2.chip_padctrl_attributes.1961797458
Directory /workspace/2.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3750462931
Short name T191
Test name
Test status
Simulation time 5003813105 ps
CPU time 248.62 seconds
Started Aug 02 08:09:52 PM PDT 24
Finished Aug 02 08:14:01 PM PDT 24
Peak memory 653420 kb
Host smart-4d04221b-6b86-4b1d-8d7b-ff1bf4733b27
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750462931 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 3.chip_padctrl_attributes.3750462931
Directory /workspace/3.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3640869915
Short name T195
Test name
Test status
Simulation time 5809033817 ps
CPU time 295.23 seconds
Started Aug 02 08:09:50 PM PDT 24
Finished Aug 02 08:14:46 PM PDT 24
Peak memory 649148 kb
Host smart-5006efc1-5ad9-4ff3-80ac-ec1f828391b4
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640869915 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 4.chip_padctrl_attributes.3640869915
Directory /workspace/4.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1122613393
Short name T194
Test name
Test status
Simulation time 4840267750 ps
CPU time 361.06 seconds
Started Aug 02 08:09:52 PM PDT 24
Finished Aug 02 08:15:54 PM PDT 24
Peak memory 657364 kb
Host smart-edfdc92f-01ac-4e42-9390-b8d93e51abdf
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122613393 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 5.chip_padctrl_attributes.1122613393
Directory /workspace/5.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2845217819
Short name T193
Test name
Test status
Simulation time 5276247850 ps
CPU time 278.75 seconds
Started Aug 02 08:09:51 PM PDT 24
Finished Aug 02 08:14:30 PM PDT 24
Peak memory 657376 kb
Host smart-f8067b4a-3af3-40cf-8931-56e5055f8dc2
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845217819 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 6.chip_padctrl_attributes.2845217819
Directory /workspace/6.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3641456681
Short name T190
Test name
Test status
Simulation time 5667801603 ps
CPU time 249.1 seconds
Started Aug 02 08:09:54 PM PDT 24
Finished Aug 02 08:14:03 PM PDT 24
Peak memory 657420 kb
Host smart-62e77b03-2302-4496-92db-2684cf835078
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641456681 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 7.chip_padctrl_attributes.3641456681
Directory /workspace/7.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.4106650320
Short name T192
Test name
Test status
Simulation time 4887798180 ps
CPU time 282.38 seconds
Started Aug 02 08:09:51 PM PDT 24
Finished Aug 02 08:14:33 PM PDT 24
Peak memory 654616 kb
Host smart-1e4c959f-6b41-473d-bb27-4b92a2e711cc
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106650320 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 8.chip_padctrl_attributes.4106650320
Directory /workspace/8.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.729425815
Short name T33
Test name
Test status
Simulation time 5021239048 ps
CPU time 266.17 seconds
Started Aug 02 08:09:52 PM PDT 24
Finished Aug 02 08:14:18 PM PDT 24
Peak memory 657376 kb
Host smart-531f9504-86d1-48c0-a81b-388b7edd191b
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729425815 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES
T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n
ull -cm_name 9.chip_padctrl_attributes.729425815
Directory /workspace/9.chip_padctrl_attributes/latest
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