| T296 |
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.2276989424 |
|
|
Aug 02 08:43:17 PM PDT 24 |
Aug 02 08:57:26 PM PDT 24 |
6397650800 ps |
| T1197 |
/workspace/coverage/default/2.rom_e2e_static_critical.4178395215 |
|
|
Aug 02 08:45:49 PM PDT 24 |
Aug 02 09:43:24 PM PDT 24 |
17199873128 ps |
| T1198 |
/workspace/coverage/default/1.chip_sw_edn_sw_mode.4281086309 |
|
|
Aug 02 08:27:27 PM PDT 24 |
Aug 02 08:52:33 PM PDT 24 |
8407581086 ps |
| T1199 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.2561832422 |
|
|
Aug 02 08:44:15 PM PDT 24 |
Aug 02 08:52:44 PM PDT 24 |
4669247512 ps |
| T1200 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.272728730 |
|
|
Aug 02 08:27:21 PM PDT 24 |
Aug 02 10:04:23 PM PDT 24 |
50517301344 ps |
| T1201 |
/workspace/coverage/default/0.chip_sw_aes_entropy.233650116 |
|
|
Aug 02 08:19:45 PM PDT 24 |
Aug 02 08:23:29 PM PDT 24 |
2359200952 ps |
| T1202 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.385953099 |
|
|
Aug 02 08:41:46 PM PDT 24 |
Aug 02 09:44:19 PM PDT 24 |
14767857320 ps |
| T1203 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1791358366 |
|
|
Aug 02 08:17:16 PM PDT 24 |
Aug 02 11:59:06 PM PDT 24 |
77688805940 ps |
| T1204 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.3777843727 |
|
|
Aug 02 08:23:45 PM PDT 24 |
Aug 02 08:29:51 PM PDT 24 |
2879402688 ps |
| T1205 |
/workspace/coverage/default/1.chip_sw_inject_scramble_seed.3425411988 |
|
|
Aug 02 08:22:31 PM PDT 24 |
Aug 02 11:38:30 PM PDT 24 |
64509143556 ps |
| T1206 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3690938632 |
|
|
Aug 02 08:36:56 PM PDT 24 |
Aug 02 09:39:18 PM PDT 24 |
21086616256 ps |
| T1207 |
/workspace/coverage/default/2.chip_sw_kmac_entropy.2728425401 |
|
|
Aug 02 08:34:52 PM PDT 24 |
Aug 02 08:40:20 PM PDT 24 |
3332828520 ps |
| T1208 |
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1329030868 |
|
|
Aug 02 08:53:35 PM PDT 24 |
Aug 02 08:58:50 PM PDT 24 |
3001299952 ps |
| T1209 |
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1273604074 |
|
|
Aug 02 08:54:52 PM PDT 24 |
Aug 02 09:00:37 PM PDT 24 |
4456119168 ps |
| T1210 |
/workspace/coverage/default/2.chip_sw_example_concurrency.654077185 |
|
|
Aug 02 08:33:01 PM PDT 24 |
Aug 02 08:36:28 PM PDT 24 |
3122218856 ps |
| T297 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2283169699 |
|
|
Aug 02 08:38:53 PM PDT 24 |
Aug 02 08:49:33 PM PDT 24 |
4109116814 ps |
| T157 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.591990282 |
|
|
Aug 02 08:40:24 PM PDT 24 |
Aug 02 08:44:04 PM PDT 24 |
2455394096 ps |
| T1211 |
/workspace/coverage/default/1.chip_sw_hmac_multistream.1569918719 |
|
|
Aug 02 08:30:27 PM PDT 24 |
Aug 02 08:58:49 PM PDT 24 |
8681453484 ps |
| T325 |
/workspace/coverage/default/60.chip_sw_all_escalation_resets.2099730730 |
|
|
Aug 02 08:52:39 PM PDT 24 |
Aug 02 09:01:56 PM PDT 24 |
5652615540 ps |
| T1212 |
/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.3312373943 |
|
|
Aug 02 08:37:06 PM PDT 24 |
Aug 02 08:41:24 PM PDT 24 |
2175012750 ps |
| T1213 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.3049817790 |
|
|
Aug 02 08:20:14 PM PDT 24 |
Aug 02 08:24:40 PM PDT 24 |
2475267792 ps |
| T1214 |
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2306622910 |
|
|
Aug 02 08:47:09 PM PDT 24 |
Aug 02 10:13:59 PM PDT 24 |
20775524552 ps |
| T712 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2198428492 |
|
|
Aug 02 08:40:38 PM PDT 24 |
Aug 02 08:51:55 PM PDT 24 |
4854082493 ps |
| T1215 |
/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3409848496 |
|
|
Aug 02 08:37:48 PM PDT 24 |
Aug 02 08:46:23 PM PDT 24 |
6542977536 ps |
| T1216 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.3969335915 |
|
|
Aug 02 08:23:05 PM PDT 24 |
Aug 02 08:57:14 PM PDT 24 |
9318966032 ps |
| T1217 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.2069728903 |
|
|
Aug 02 08:34:07 PM PDT 24 |
Aug 02 08:38:16 PM PDT 24 |
3022456742 ps |
| T1218 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3632629708 |
|
|
Aug 02 08:37:06 PM PDT 24 |
Aug 02 08:39:07 PM PDT 24 |
2555327310 ps |
| T127 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2157312214 |
|
|
Aug 02 08:20:37 PM PDT 24 |
Aug 02 08:29:01 PM PDT 24 |
5826907366 ps |
| T1219 |
/workspace/coverage/default/1.chip_sw_otbn_randomness.3673229845 |
|
|
Aug 02 08:27:21 PM PDT 24 |
Aug 02 08:43:58 PM PDT 24 |
6363456520 ps |
| T10 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.4091393357 |
|
|
Aug 02 08:23:34 PM PDT 24 |
Aug 02 08:27:53 PM PDT 24 |
2828390495 ps |
| T738 |
/workspace/coverage/default/40.chip_sw_all_escalation_resets.446636966 |
|
|
Aug 02 08:50:02 PM PDT 24 |
Aug 02 09:00:54 PM PDT 24 |
5307234252 ps |
| T1220 |
/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.179509016 |
|
|
Aug 02 08:33:16 PM PDT 24 |
Aug 02 09:10:32 PM PDT 24 |
26591845997 ps |
| T1221 |
/workspace/coverage/default/0.chip_sw_kmac_idle.252243928 |
|
|
Aug 02 08:19:38 PM PDT 24 |
Aug 02 08:24:37 PM PDT 24 |
2949718594 ps |
| T138 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1438934343 |
|
|
Aug 02 08:22:40 PM PDT 24 |
Aug 02 08:32:00 PM PDT 24 |
8412953176 ps |
| T434 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2036864572 |
|
|
Aug 02 08:30:29 PM PDT 24 |
Aug 02 08:50:45 PM PDT 24 |
23749361272 ps |
| T67 |
/workspace/coverage/default/3.chip_tap_straps_rma.1789483276 |
|
|
Aug 02 08:43:28 PM PDT 24 |
Aug 02 08:49:31 PM PDT 24 |
3690210952 ps |
| T1222 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.3481576656 |
|
|
Aug 02 08:40:00 PM PDT 24 |
Aug 02 08:49:32 PM PDT 24 |
5194442002 ps |
| T1223 |
/workspace/coverage/default/0.chip_sw_example_concurrency.2097464807 |
|
|
Aug 02 08:18:26 PM PDT 24 |
Aug 02 08:23:52 PM PDT 24 |
2738406340 ps |
| T1224 |
/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.560704184 |
|
|
Aug 02 08:36:10 PM PDT 24 |
Aug 02 08:44:34 PM PDT 24 |
5361428180 ps |
| T354 |
/workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.1903801691 |
|
|
Aug 02 08:40:51 PM PDT 24 |
Aug 02 08:47:54 PM PDT 24 |
4800005734 ps |
| T1225 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.3001882984 |
|
|
Aug 02 08:30:04 PM PDT 24 |
Aug 02 09:35:30 PM PDT 24 |
13484909915 ps |
| T1226 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2250455591 |
|
|
Aug 02 08:29:59 PM PDT 24 |
Aug 02 08:35:44 PM PDT 24 |
3350690352 ps |
| T1227 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.3186585753 |
|
|
Aug 02 08:29:36 PM PDT 24 |
Aug 02 09:28:48 PM PDT 24 |
14592230680 ps |
| T1228 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.426458015 |
|
|
Aug 02 08:28:48 PM PDT 24 |
Aug 02 08:56:51 PM PDT 24 |
6944715720 ps |
| T1229 |
/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.2918484843 |
|
|
Aug 02 08:36:50 PM PDT 24 |
Aug 02 09:37:34 PM PDT 24 |
14892660160 ps |
| T1230 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.2029471382 |
|
|
Aug 02 08:34:05 PM PDT 24 |
Aug 03 12:25:13 AM PDT 24 |
79046478420 ps |
| T1231 |
/workspace/coverage/default/0.chip_sw_hmac_multistream.3979759871 |
|
|
Aug 02 08:18:27 PM PDT 24 |
Aug 02 08:49:19 PM PDT 24 |
8520591700 ps |
| T1232 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.221311382 |
|
|
Aug 02 08:51:11 PM PDT 24 |
Aug 02 08:59:45 PM PDT 24 |
3843832328 ps |
| T1233 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.4074248044 |
|
|
Aug 02 08:32:27 PM PDT 24 |
Aug 02 08:49:14 PM PDT 24 |
7542829240 ps |
| T1234 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3287834753 |
|
|
Aug 02 08:25:57 PM PDT 24 |
Aug 02 09:25:28 PM PDT 24 |
47242650626 ps |
| T351 |
/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.1255971410 |
|
|
Aug 02 08:20:38 PM PDT 24 |
Aug 02 08:29:35 PM PDT 24 |
3990518124 ps |
| T209 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.3604973324 |
|
|
Aug 02 08:37:33 PM PDT 24 |
Aug 02 09:04:44 PM PDT 24 |
21240827868 ps |
| T1235 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.4207694338 |
|
|
Aug 02 08:28:29 PM PDT 24 |
Aug 02 08:45:30 PM PDT 24 |
5598732316 ps |
| T1236 |
/workspace/coverage/default/0.chip_sw_data_integrity_escalation.410461899 |
|
|
Aug 02 08:17:17 PM PDT 24 |
Aug 02 08:28:06 PM PDT 24 |
6407752464 ps |
| T783 |
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3346536421 |
|
|
Aug 02 08:52:13 PM PDT 24 |
Aug 02 08:58:59 PM PDT 24 |
3739138480 ps |
| T1237 |
/workspace/coverage/default/0.chip_sw_kmac_entropy.3249581327 |
|
|
Aug 02 08:19:06 PM PDT 24 |
Aug 02 08:22:46 PM PDT 24 |
3068446620 ps |
| T1238 |
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.4110419101 |
|
|
Aug 02 08:42:50 PM PDT 24 |
Aug 02 08:51:29 PM PDT 24 |
6596436106 ps |
| T1239 |
/workspace/coverage/default/2.chip_sw_hmac_smoketest.3069563213 |
|
|
Aug 02 08:44:29 PM PDT 24 |
Aug 02 08:50:28 PM PDT 24 |
3333084812 ps |
| T131 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1402204130 |
|
|
Aug 02 08:40:07 PM PDT 24 |
Aug 02 08:57:15 PM PDT 24 |
8334403580 ps |
| T309 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.2198179537 |
|
|
Aug 02 08:32:27 PM PDT 24 |
Aug 02 08:37:56 PM PDT 24 |
3193151384 ps |
| T1240 |
/workspace/coverage/default/1.rom_e2e_smoke.3030744841 |
|
|
Aug 02 08:38:07 PM PDT 24 |
Aug 02 09:35:16 PM PDT 24 |
15005442662 ps |
| T1241 |
/workspace/coverage/default/0.chip_sw_gpio_smoketest.1807336840 |
|
|
Aug 02 08:21:55 PM PDT 24 |
Aug 02 08:26:25 PM PDT 24 |
3524205046 ps |
| T1242 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2791390767 |
|
|
Aug 02 08:40:25 PM PDT 24 |
Aug 02 08:48:12 PM PDT 24 |
3610704330 ps |
| T1243 |
/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.762581642 |
|
|
Aug 02 08:48:09 PM PDT 24 |
Aug 02 09:00:12 PM PDT 24 |
11977340273 ps |
| T1244 |
/workspace/coverage/default/1.chip_sw_pattgen_ios.1400765394 |
|
|
Aug 02 08:24:07 PM PDT 24 |
Aug 02 08:29:44 PM PDT 24 |
3180011192 ps |
| T1245 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.824086173 |
|
|
Aug 02 08:40:19 PM PDT 24 |
Aug 02 09:05:50 PM PDT 24 |
16249411473 ps |
| T1246 |
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.80351070 |
|
|
Aug 02 08:44:31 PM PDT 24 |
Aug 02 08:53:51 PM PDT 24 |
4424948740 ps |
| T1247 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3794133738 |
|
|
Aug 02 08:41:56 PM PDT 24 |
Aug 02 08:50:42 PM PDT 24 |
6185892416 ps |
| T1248 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.3755198447 |
|
|
Aug 02 08:25:27 PM PDT 24 |
Aug 02 08:34:40 PM PDT 24 |
9094181064 ps |
| T44 |
/workspace/coverage/default/2.chip_sw_spi_device_tpm.623894725 |
|
|
Aug 02 08:35:27 PM PDT 24 |
Aug 02 08:41:57 PM PDT 24 |
3221013230 ps |
| T1249 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.3727820792 |
|
|
Aug 02 08:35:04 PM PDT 24 |
Aug 02 08:52:26 PM PDT 24 |
6144108147 ps |
| T238 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.4271578632 |
|
|
Aug 02 08:24:55 PM PDT 24 |
Aug 02 10:00:53 PM PDT 24 |
48677073400 ps |
| T1250 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.3047346564 |
|
|
Aug 02 08:49:45 PM PDT 24 |
Aug 02 09:01:16 PM PDT 24 |
4594128112 ps |
| T1251 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3068587908 |
|
|
Aug 02 08:18:57 PM PDT 24 |
Aug 02 08:25:07 PM PDT 24 |
4142366851 ps |
| T797 |
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1190150323 |
|
|
Aug 02 08:54:36 PM PDT 24 |
Aug 02 09:00:24 PM PDT 24 |
3742500094 ps |
| T1252 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.3221758748 |
|
|
Aug 02 08:30:11 PM PDT 24 |
Aug 02 08:39:08 PM PDT 24 |
3630443816 ps |
| T1253 |
/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.1377111403 |
|
|
Aug 02 08:46:52 PM PDT 24 |
Aug 02 08:50:14 PM PDT 24 |
2185027830 ps |
| T1254 |
/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1456708172 |
|
|
Aug 02 08:18:51 PM PDT 24 |
Aug 02 11:45:54 PM PDT 24 |
255520032424 ps |
| T1255 |
/workspace/coverage/default/2.chip_sw_ast_clk_outputs.246566229 |
|
|
Aug 02 08:40:51 PM PDT 24 |
Aug 02 08:58:02 PM PDT 24 |
8403035000 ps |
| T1256 |
/workspace/coverage/default/1.chip_sw_aes_entropy.619492533 |
|
|
Aug 02 08:28:51 PM PDT 24 |
Aug 02 08:32:57 PM PDT 24 |
3301060760 ps |
| T68 |
/workspace/coverage/default/4.chip_tap_straps_rma.994822040 |
|
|
Aug 02 08:43:54 PM PDT 24 |
Aug 02 08:48:11 PM PDT 24 |
2952268655 ps |
| T1257 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.526058732 |
|
|
Aug 02 08:28:02 PM PDT 24 |
Aug 02 09:24:22 PM PDT 24 |
20279324665 ps |
| T787 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.1019429584 |
|
|
Aug 02 08:47:46 PM PDT 24 |
Aug 02 08:56:03 PM PDT 24 |
5643764812 ps |
| T1258 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3370208467 |
|
|
Aug 02 08:39:12 PM PDT 24 |
Aug 02 08:46:41 PM PDT 24 |
5304752358 ps |
| T1259 |
/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.3500925056 |
|
|
Aug 02 08:22:23 PM PDT 24 |
Aug 02 11:12:13 PM PDT 24 |
58619994540 ps |
| T1260 |
/workspace/coverage/default/0.chip_sw_coremark.971171362 |
|
|
Aug 02 08:19:10 PM PDT 24 |
Aug 03 12:21:14 AM PDT 24 |
71361731240 ps |
| T1261 |
/workspace/coverage/default/28.chip_sw_all_escalation_resets.1313256570 |
|
|
Aug 02 08:49:22 PM PDT 24 |
Aug 02 08:58:36 PM PDT 24 |
5793739760 ps |
| T1262 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.435590275 |
|
|
Aug 02 08:38:28 PM PDT 24 |
Aug 02 08:58:40 PM PDT 24 |
7897570044 ps |
| T1263 |
/workspace/coverage/default/0.rom_keymgr_functest.1804427480 |
|
|
Aug 02 08:23:04 PM PDT 24 |
Aug 02 08:33:22 PM PDT 24 |
3914691530 ps |
| T1264 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2518275357 |
|
|
Aug 02 08:21:40 PM PDT 24 |
Aug 02 09:23:18 PM PDT 24 |
19399567064 ps |
| T1265 |
/workspace/coverage/default/1.chip_sw_kmac_smoketest.123429111 |
|
|
Aug 02 08:33:03 PM PDT 24 |
Aug 02 08:39:04 PM PDT 24 |
3170009320 ps |
| T1266 |
/workspace/coverage/default/47.chip_sw_all_escalation_resets.579025291 |
|
|
Aug 02 08:50:30 PM PDT 24 |
Aug 02 09:01:37 PM PDT 24 |
6302676532 ps |
| T1267 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.775802591 |
|
|
Aug 02 08:19:35 PM PDT 24 |
Aug 02 08:27:33 PM PDT 24 |
6822694290 ps |
| T1268 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.3221244253 |
|
|
Aug 02 08:19:29 PM PDT 24 |
Aug 02 08:43:19 PM PDT 24 |
6971474128 ps |
| T1269 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.510383877 |
|
|
Aug 02 08:46:58 PM PDT 24 |
Aug 02 09:14:42 PM PDT 24 |
8094616342 ps |
| T1270 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.1334664798 |
|
|
Aug 02 08:41:46 PM PDT 24 |
Aug 02 09:59:04 PM PDT 24 |
15628077690 ps |
| T1271 |
/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.1143002470 |
|
|
Aug 02 08:38:57 PM PDT 24 |
Aug 02 08:44:36 PM PDT 24 |
3201375750 ps |
| T1272 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx.679856892 |
|
|
Aug 02 08:24:15 PM PDT 24 |
Aug 02 08:33:20 PM PDT 24 |
4773124120 ps |
| T201 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through.3197107123 |
|
|
Aug 02 08:23:37 PM PDT 24 |
Aug 02 08:34:03 PM PDT 24 |
6226505655 ps |
| T1273 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.370235637 |
|
|
Aug 02 08:18:15 PM PDT 24 |
Aug 02 08:56:31 PM PDT 24 |
19024660089 ps |
| T1274 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.2313969076 |
|
|
Aug 02 08:25:38 PM PDT 24 |
Aug 02 08:44:04 PM PDT 24 |
6273894695 ps |
| T806 |
/workspace/coverage/default/0.chip_sw_all_escalation_resets.839973141 |
|
|
Aug 02 08:20:27 PM PDT 24 |
Aug 02 08:30:58 PM PDT 24 |
6079326560 ps |
| T1275 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3004902669 |
|
|
Aug 02 08:39:10 PM PDT 24 |
Aug 02 08:52:08 PM PDT 24 |
3719168376 ps |
| T1276 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3555324157 |
|
|
Aug 02 08:23:56 PM PDT 24 |
Aug 02 09:45:04 PM PDT 24 |
25052148533 ps |
| T132 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3014444544 |
|
|
Aug 02 08:31:00 PM PDT 24 |
Aug 02 08:47:25 PM PDT 24 |
7612613540 ps |
| T1277 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.1198829737 |
|
|
Aug 02 08:40:15 PM PDT 24 |
Aug 02 09:27:21 PM PDT 24 |
13950853316 ps |
| T1278 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.2402547339 |
|
|
Aug 02 08:26:49 PM PDT 24 |
Aug 02 08:31:07 PM PDT 24 |
2779297227 ps |
| T790 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.311118844 |
|
|
Aug 02 08:54:13 PM PDT 24 |
Aug 02 08:59:18 PM PDT 24 |
3515942360 ps |
| T782 |
/workspace/coverage/default/11.chip_sw_all_escalation_resets.1272189145 |
|
|
Aug 02 08:46:09 PM PDT 24 |
Aug 02 08:56:53 PM PDT 24 |
6269668898 ps |
| T386 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.2687422801 |
|
|
Aug 02 08:45:58 PM PDT 24 |
Aug 02 08:54:54 PM PDT 24 |
4841096080 ps |
| T816 |
/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.4153647520 |
|
|
Aug 02 08:43:31 PM PDT 24 |
Aug 02 08:49:07 PM PDT 24 |
3363035180 ps |
| T1279 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4082832399 |
|
|
Aug 02 08:31:10 PM PDT 24 |
Aug 02 08:38:02 PM PDT 24 |
7410702446 ps |
| T664 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2505951264 |
|
|
Aug 02 08:29:53 PM PDT 24 |
Aug 02 08:38:10 PM PDT 24 |
4783210760 ps |
| T359 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.3046991551 |
|
|
Aug 02 08:23:33 PM PDT 24 |
Aug 02 08:37:08 PM PDT 24 |
3975987416 ps |
| T1280 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.4172610717 |
|
|
Aug 02 08:26:21 PM PDT 24 |
Aug 02 08:37:20 PM PDT 24 |
4048478446 ps |
| T1281 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.3053152478 |
|
|
Aug 02 08:26:16 PM PDT 24 |
Aug 02 09:35:38 PM PDT 24 |
15736456332 ps |
| T1282 |
/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.3510431177 |
|
|
Aug 02 08:25:39 PM PDT 24 |
Aug 02 08:30:16 PM PDT 24 |
3095245776 ps |
| T1283 |
/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.3872614253 |
|
|
Aug 02 08:20:02 PM PDT 24 |
Aug 02 09:09:24 PM PDT 24 |
27279717365 ps |
| T1284 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.786814170 |
|
|
Aug 02 08:26:31 PM PDT 24 |
Aug 02 09:14:10 PM PDT 24 |
12994233977 ps |
| T1285 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.205555206 |
|
|
Aug 02 08:36:08 PM PDT 24 |
Aug 02 08:46:54 PM PDT 24 |
4544422162 ps |
| T1286 |
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1458739796 |
|
|
Aug 02 08:52:19 PM PDT 24 |
Aug 02 08:59:07 PM PDT 24 |
4396230842 ps |
| T1287 |
/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.2424642966 |
|
|
Aug 02 08:30:21 PM PDT 24 |
Aug 02 08:33:29 PM PDT 24 |
2719900610 ps |
| T1288 |
/workspace/coverage/default/1.chip_sw_kmac_entropy.3148356927 |
|
|
Aug 02 08:25:32 PM PDT 24 |
Aug 02 08:30:39 PM PDT 24 |
3338485224 ps |
| T233 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.731154572 |
|
|
Aug 02 08:30:01 PM PDT 24 |
Aug 02 09:32:42 PM PDT 24 |
16670912098 ps |
| T1289 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.3269248140 |
|
|
Aug 02 08:26:34 PM PDT 24 |
Aug 02 10:01:34 PM PDT 24 |
23413703126 ps |
| T1290 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.2202872878 |
|
|
Aug 02 08:41:49 PM PDT 24 |
Aug 02 08:49:15 PM PDT 24 |
3410616936 ps |
| T1291 |
/workspace/coverage/default/1.chip_sw_aes_smoketest.2367542631 |
|
|
Aug 02 08:35:04 PM PDT 24 |
Aug 02 08:40:51 PM PDT 24 |
2591670808 ps |
| T773 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.3578056554 |
|
|
Aug 02 08:51:29 PM PDT 24 |
Aug 02 09:01:10 PM PDT 24 |
5031675148 ps |
| T827 |
/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1171351215 |
|
|
Aug 02 08:49:29 PM PDT 24 |
Aug 02 08:56:21 PM PDT 24 |
3488791100 ps |
| T1292 |
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3218939167 |
|
|
Aug 02 08:50:56 PM PDT 24 |
Aug 02 08:56:51 PM PDT 24 |
3564859830 ps |
| T690 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3624973593 |
|
|
Aug 02 08:32:06 PM PDT 24 |
Aug 03 01:33:15 AM PDT 24 |
134920551086 ps |
| T1293 |
/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.1120973503 |
|
|
Aug 02 08:24:17 PM PDT 24 |
Aug 02 08:55:08 PM PDT 24 |
13853446930 ps |
| T1294 |
/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.1039191247 |
|
|
Aug 02 08:30:51 PM PDT 24 |
Aug 02 09:12:41 PM PDT 24 |
29804295933 ps |
| T1295 |
/workspace/coverage/default/30.chip_sw_all_escalation_resets.1810206637 |
|
|
Aug 02 08:48:14 PM PDT 24 |
Aug 02 08:59:03 PM PDT 24 |
5477011934 ps |
| T1296 |
/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3720868692 |
|
|
Aug 02 08:43:23 PM PDT 24 |
Aug 02 08:48:17 PM PDT 24 |
2482875560 ps |
| T1297 |
/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2976068557 |
|
|
Aug 02 08:37:33 PM PDT 24 |
Aug 02 08:47:53 PM PDT 24 |
9118720955 ps |
| T234 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2838386377 |
|
|
Aug 02 08:19:45 PM PDT 24 |
Aug 02 09:17:28 PM PDT 24 |
12846453400 ps |
| T825 |
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2347039454 |
|
|
Aug 02 08:51:03 PM PDT 24 |
Aug 02 08:57:02 PM PDT 24 |
4049867752 ps |
| T1298 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.2786182446 |
|
|
Aug 02 08:37:45 PM PDT 24 |
Aug 02 08:42:08 PM PDT 24 |
2615375320 ps |
| T1299 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.3026172200 |
|
|
Aug 02 08:29:58 PM PDT 24 |
Aug 02 08:52:52 PM PDT 24 |
7499720591 ps |
| T1300 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1319736711 |
|
|
Aug 02 08:31:17 PM PDT 24 |
Aug 02 09:28:46 PM PDT 24 |
25519032404 ps |
| T779 |
/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2206785467 |
|
|
Aug 02 08:48:37 PM PDT 24 |
Aug 02 08:57:27 PM PDT 24 |
4228715592 ps |
| T1301 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.2512318770 |
|
|
Aug 02 08:43:11 PM PDT 24 |
Aug 02 08:52:01 PM PDT 24 |
5606075860 ps |
| T340 |
/workspace/coverage/default/0.chip_plic_all_irqs_0.4031907559 |
|
|
Aug 02 08:21:34 PM PDT 24 |
Aug 02 08:39:43 PM PDT 24 |
5738897984 ps |
| T736 |
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1801976293 |
|
|
Aug 02 08:54:31 PM PDT 24 |
Aug 02 09:00:46 PM PDT 24 |
4583496444 ps |
| T1302 |
/workspace/coverage/default/1.chip_tap_straps_dev.1813495487 |
|
|
Aug 02 08:30:58 PM PDT 24 |
Aug 02 08:34:37 PM PDT 24 |
3092220416 ps |
| T1303 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.1290038191 |
|
|
Aug 02 08:32:25 PM PDT 24 |
Aug 02 08:38:42 PM PDT 24 |
3916963216 ps |
| T1304 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1920426304 |
|
|
Aug 02 08:22:54 PM PDT 24 |
Aug 02 08:43:43 PM PDT 24 |
9649533020 ps |
| T1305 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.4028686427 |
|
|
Aug 02 08:22:32 PM PDT 24 |
Aug 02 09:50:22 PM PDT 24 |
14849561048 ps |
| T1306 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.3533798294 |
|
|
Aug 02 08:25:31 PM PDT 24 |
Aug 02 08:34:25 PM PDT 24 |
4668782685 ps |
| T1307 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.85310597 |
|
|
Aug 02 08:37:53 PM PDT 24 |
Aug 02 09:42:14 PM PDT 24 |
17067014872 ps |
| T1308 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.722982701 |
|
|
Aug 02 08:30:48 PM PDT 24 |
Aug 02 08:40:06 PM PDT 24 |
6750327128 ps |
| T1309 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.1478439721 |
|
|
Aug 02 08:26:23 PM PDT 24 |
Aug 02 08:30:55 PM PDT 24 |
3237832725 ps |
| T1310 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.683555712 |
|
|
Aug 02 08:41:13 PM PDT 24 |
Aug 02 09:00:51 PM PDT 24 |
7953163905 ps |
| T1311 |
/workspace/coverage/default/0.rom_e2e_asm_init_dev.352270429 |
|
|
Aug 02 08:25:58 PM PDT 24 |
Aug 02 09:29:30 PM PDT 24 |
15369983400 ps |
| T1312 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.563148541 |
|
|
Aug 02 08:19:23 PM PDT 24 |
Aug 02 08:22:29 PM PDT 24 |
3037918233 ps |
| T1313 |
/workspace/coverage/default/2.chip_sw_aes_enc.2736705623 |
|
|
Aug 02 08:39:04 PM PDT 24 |
Aug 02 08:43:17 PM PDT 24 |
2813871268 ps |
| T1314 |
/workspace/coverage/default/0.chip_sw_otbn_smoketest.2018813216 |
|
|
Aug 02 08:25:49 PM PDT 24 |
Aug 02 08:57:42 PM PDT 24 |
8813463850 ps |
| T820 |
/workspace/coverage/default/97.chip_sw_all_escalation_resets.1966230265 |
|
|
Aug 02 08:55:04 PM PDT 24 |
Aug 02 09:03:33 PM PDT 24 |
4360292160 ps |
| T1315 |
/workspace/coverage/default/0.chip_sw_edn_sw_mode.1478776634 |
|
|
Aug 02 08:19:45 PM PDT 24 |
Aug 02 08:50:02 PM PDT 24 |
8693591064 ps |
| T380 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2548536299 |
|
|
Aug 02 08:22:50 PM PDT 24 |
Aug 02 08:31:42 PM PDT 24 |
6025049492 ps |
| T1316 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.130305852 |
|
|
Aug 02 08:33:02 PM PDT 24 |
Aug 02 09:03:08 PM PDT 24 |
10772131184 ps |
| T1317 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.30178582 |
|
|
Aug 02 08:38:14 PM PDT 24 |
Aug 02 08:52:00 PM PDT 24 |
5544480023 ps |
| T1318 |
/workspace/coverage/default/1.rom_e2e_shutdown_output.3983740643 |
|
|
Aug 02 08:37:16 PM PDT 24 |
Aug 02 09:27:28 PM PDT 24 |
23840339046 ps |
| T1319 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.2362130861 |
|
|
Aug 02 08:23:19 PM PDT 24 |
Aug 02 08:33:53 PM PDT 24 |
4204375110 ps |
| T402 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.1470472564 |
|
|
Aug 02 08:42:28 PM PDT 24 |
Aug 02 08:46:17 PM PDT 24 |
3274703264 ps |
| T1320 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.3488631944 |
|
|
Aug 02 08:47:57 PM PDT 24 |
Aug 02 08:57:24 PM PDT 24 |
5678103436 ps |
| T1321 |
/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.3848150707 |
|
|
Aug 02 08:33:19 PM PDT 24 |
Aug 02 08:37:49 PM PDT 24 |
3295908480 ps |
| T1322 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.2611637483 |
|
|
Aug 02 08:33:26 PM PDT 24 |
Aug 02 08:37:57 PM PDT 24 |
2691947240 ps |
| T1323 |
/workspace/coverage/default/1.rom_e2e_self_hash.3928008035 |
|
|
Aug 02 08:37:08 PM PDT 24 |
Aug 02 10:24:37 PM PDT 24 |
27073886600 ps |
| T1324 |
/workspace/coverage/default/2.chip_sw_rv_timer_irq.793367787 |
|
|
Aug 02 08:36:35 PM PDT 24 |
Aug 02 08:40:51 PM PDT 24 |
2728828458 ps |
| T1325 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.1954510515 |
|
|
Aug 02 08:30:53 PM PDT 24 |
Aug 02 09:21:11 PM PDT 24 |
13050109032 ps |
| T1326 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.892758078 |
|
|
Aug 02 08:22:13 PM PDT 24 |
Aug 02 08:40:08 PM PDT 24 |
8741306270 ps |
| T164 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.2061496238 |
|
|
Aug 02 08:21:29 PM PDT 24 |
Aug 02 08:27:29 PM PDT 24 |
4333318520 ps |
| T1327 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.3863349981 |
|
|
Aug 02 08:25:52 PM PDT 24 |
Aug 02 09:17:10 PM PDT 24 |
10879013478 ps |
| T1328 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.1489504253 |
|
|
Aug 02 08:39:13 PM PDT 24 |
Aug 02 08:44:03 PM PDT 24 |
2371307914 ps |
| T1329 |
/workspace/coverage/default/1.chip_sw_hmac_smoketest.2397603806 |
|
|
Aug 02 08:33:44 PM PDT 24 |
Aug 02 08:40:30 PM PDT 24 |
3471552120 ps |
| T1330 |
/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.605048286 |
|
|
Aug 02 08:37:44 PM PDT 24 |
Aug 02 08:45:39 PM PDT 24 |
3453779010 ps |
| T1331 |
/workspace/coverage/default/0.chip_sw_alert_handler_escalation.61641010 |
|
|
Aug 02 08:18:20 PM PDT 24 |
Aug 02 08:28:17 PM PDT 24 |
5877882786 ps |
| T1332 |
/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.2766137200 |
|
|
Aug 02 08:38:28 PM PDT 24 |
Aug 02 08:48:47 PM PDT 24 |
5790283201 ps |
| T1333 |
/workspace/coverage/default/53.chip_sw_all_escalation_resets.2964878924 |
|
|
Aug 02 08:52:24 PM PDT 24 |
Aug 02 09:02:55 PM PDT 24 |
6479950670 ps |
| T1334 |
/workspace/coverage/default/0.chip_sw_aon_timer_irq.956230889 |
|
|
Aug 02 08:20:40 PM PDT 24 |
Aug 02 08:28:55 PM PDT 24 |
4116856296 ps |
| T830 |
/workspace/coverage/default/79.chip_sw_all_escalation_resets.966808421 |
|
|
Aug 02 08:55:31 PM PDT 24 |
Aug 02 09:08:13 PM PDT 24 |
4711722354 ps |
| T1335 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3378465888 |
|
|
Aug 02 08:30:05 PM PDT 24 |
Aug 02 09:19:15 PM PDT 24 |
11426195540 ps |
| T1336 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.3586513487 |
|
|
Aug 02 08:40:02 PM PDT 24 |
Aug 02 09:01:14 PM PDT 24 |
12620410960 ps |
| T1337 |
/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.1650757800 |
|
|
Aug 02 08:19:07 PM PDT 24 |
Aug 02 08:24:27 PM PDT 24 |
4712443492 ps |
| T1338 |
/workspace/coverage/default/83.chip_sw_all_escalation_resets.1156392503 |
|
|
Aug 02 08:56:16 PM PDT 24 |
Aug 02 09:03:57 PM PDT 24 |
5011497932 ps |
| T387 |
/workspace/coverage/default/8.chip_sw_all_escalation_resets.2342994411 |
|
|
Aug 02 08:50:12 PM PDT 24 |
Aug 02 09:00:59 PM PDT 24 |
5903340740 ps |
| T1339 |
/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.3113740536 |
|
|
Aug 02 08:25:29 PM PDT 24 |
Aug 02 08:40:00 PM PDT 24 |
5466907936 ps |
| T1340 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1466867133 |
|
|
Aug 02 08:19:45 PM PDT 24 |
Aug 02 08:23:24 PM PDT 24 |
2756711636 ps |
| T1341 |
/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.480810429 |
|
|
Aug 02 08:25:35 PM PDT 24 |
Aug 02 09:30:36 PM PDT 24 |
14822889100 ps |
| T1342 |
/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.733594764 |
|
|
Aug 02 08:22:26 PM PDT 24 |
Aug 02 08:28:44 PM PDT 24 |
5142354140 ps |
| T1343 |
/workspace/coverage/default/2.chip_sw_csrng_kat_test.190714019 |
|
|
Aug 02 08:38:33 PM PDT 24 |
Aug 02 08:43:46 PM PDT 24 |
3174602864 ps |
| T1344 |
/workspace/coverage/default/63.chip_sw_all_escalation_resets.1837850472 |
|
|
Aug 02 08:52:03 PM PDT 24 |
Aug 02 09:00:46 PM PDT 24 |
4473835728 ps |
| T1345 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.3984646883 |
|
|
Aug 02 08:46:08 PM PDT 24 |
Aug 02 08:50:32 PM PDT 24 |
3551743352 ps |
| T1346 |
/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.1024436438 |
|
|
Aug 02 08:37:17 PM PDT 24 |
Aug 02 09:20:33 PM PDT 24 |
11244659703 ps |
| T1347 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.280266165 |
|
|
Aug 02 08:22:08 PM PDT 24 |
Aug 02 08:44:15 PM PDT 24 |
7270215445 ps |
| T342 |
/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1326503251 |
|
|
Aug 02 08:41:17 PM PDT 24 |
Aug 02 09:07:39 PM PDT 24 |
12223199768 ps |
| T1348 |
/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.781519201 |
|
|
Aug 02 08:35:21 PM PDT 24 |
Aug 02 09:54:37 PM PDT 24 |
42761514033 ps |
| T1349 |
/workspace/coverage/default/1.chip_sw_aon_timer_irq.2885484862 |
|
|
Aug 02 08:27:19 PM PDT 24 |
Aug 02 08:34:21 PM PDT 24 |
4301554868 ps |
| T1350 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access.437167306 |
|
|
Aug 02 08:18:11 PM PDT 24 |
Aug 02 08:33:58 PM PDT 24 |
5190639160 ps |
| T1351 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.716430398 |
|
|
Aug 02 08:24:09 PM PDT 24 |
Aug 02 08:37:55 PM PDT 24 |
4060007714 ps |
| T1352 |
/workspace/coverage/default/1.rom_raw_unlock.3392638447 |
|
|
Aug 02 08:34:04 PM PDT 24 |
Aug 02 08:38:40 PM PDT 24 |
6242355590 ps |
| T1353 |
/workspace/coverage/default/2.chip_sival_flash_info_access.3051967721 |
|
|
Aug 02 08:33:16 PM PDT 24 |
Aug 02 08:39:14 PM PDT 24 |
3457766216 ps |
| T202 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through.1937936818 |
|
|
Aug 02 08:21:54 PM PDT 24 |
Aug 02 08:32:17 PM PDT 24 |
5824640569 ps |
| T1354 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3155393916 |
|
|
Aug 02 08:19:11 PM PDT 24 |
Aug 02 08:28:22 PM PDT 24 |
5471757720 ps |
| T1355 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.906223898 |
|
|
Aug 02 08:25:33 PM PDT 24 |
Aug 02 08:46:59 PM PDT 24 |
8407548176 ps |
| T1356 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.3291866727 |
|
|
Aug 02 08:20:28 PM PDT 24 |
Aug 02 09:04:36 PM PDT 24 |
24637366612 ps |
| T821 |
/workspace/coverage/default/81.chip_sw_all_escalation_resets.3901795348 |
|
|
Aug 02 08:53:51 PM PDT 24 |
Aug 02 09:01:30 PM PDT 24 |
4062590600 ps |
| T1357 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.3729418929 |
|
|
Aug 02 08:24:34 PM PDT 24 |
Aug 02 09:55:56 PM PDT 24 |
49416082215 ps |
| T713 |
/workspace/coverage/default/2.chip_tap_straps_dev.1621858747 |
|
|
Aug 02 08:39:56 PM PDT 24 |
Aug 02 08:55:37 PM PDT 24 |
9609975278 ps |
| T1358 |
/workspace/coverage/default/0.chip_sw_power_sleep_load.1183913888 |
|
|
Aug 02 08:25:55 PM PDT 24 |
Aug 02 08:33:51 PM PDT 24 |
9796029012 ps |
| T310 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.1938575897 |
|
|
Aug 02 08:20:52 PM PDT 24 |
Aug 02 08:24:51 PM PDT 24 |
2803172322 ps |
| T1359 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3408854674 |
|
|
Aug 02 08:20:16 PM PDT 24 |
Aug 02 09:07:35 PM PDT 24 |
11028963718 ps |
| T677 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4137940810 |
|
|
Aug 02 08:24:58 PM PDT 24 |
Aug 02 08:36:53 PM PDT 24 |
5563855980 ps |
| T1360 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2336126227 |
|
|
Aug 02 08:20:42 PM PDT 24 |
Aug 02 08:32:43 PM PDT 24 |
4543103728 ps |
| T1361 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.314006921 |
|
|
Aug 02 08:19:30 PM PDT 24 |
Aug 02 08:30:05 PM PDT 24 |
4394231390 ps |
| T1362 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2988681278 |
|
|
Aug 02 08:38:11 PM PDT 24 |
Aug 02 09:35:03 PM PDT 24 |
42221817185 ps |
| T742 |
/workspace/coverage/default/69.chip_sw_all_escalation_resets.1893418006 |
|
|
Aug 02 08:54:42 PM PDT 24 |
Aug 02 09:05:07 PM PDT 24 |
6172242840 ps |
| T1363 |
/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.659577236 |
|
|
Aug 02 08:50:04 PM PDT 24 |
Aug 02 09:36:21 PM PDT 24 |
13416684216 ps |
| T1364 |
/workspace/coverage/default/1.chip_sw_entropy_src_csrng.2163474942 |
|
|
Aug 02 08:29:41 PM PDT 24 |
Aug 02 09:01:36 PM PDT 24 |
7996727938 ps |
| T1365 |
/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.2926976785 |
|
|
Aug 02 08:37:03 PM PDT 24 |
Aug 02 11:30:47 PM PDT 24 |
58327684341 ps |
| T1366 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.939486881 |
|
|
Aug 02 08:34:43 PM PDT 24 |
Aug 02 08:53:22 PM PDT 24 |
6218474148 ps |
| T1367 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.4215204136 |
|
|
Aug 02 08:35:44 PM PDT 24 |
Aug 02 08:48:23 PM PDT 24 |
4480432260 ps |
| T1368 |
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.4010066729 |
|
|
Aug 02 08:43:19 PM PDT 24 |
Aug 02 09:02:10 PM PDT 24 |
7837984548 ps |
| T784 |
/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1369951425 |
|
|
Aug 02 08:47:47 PM PDT 24 |
Aug 02 08:54:08 PM PDT 24 |
3243406778 ps |
| T1369 |
/workspace/coverage/default/2.rom_keymgr_functest.1961482466 |
|
|
Aug 02 08:43:44 PM PDT 24 |
Aug 02 08:57:08 PM PDT 24 |
4941367444 ps |
| T1370 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.2159153481 |
|
|
Aug 02 08:18:21 PM PDT 24 |
Aug 02 08:27:28 PM PDT 24 |
5012978357 ps |
| T1371 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3838529995 |
|
|
Aug 02 08:23:50 PM PDT 24 |
Aug 02 08:25:38 PM PDT 24 |
2505751427 ps |
| T1372 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.2128058548 |
|
|
Aug 02 08:25:47 PM PDT 24 |
Aug 02 08:35:09 PM PDT 24 |
5506554674 ps |
| T1373 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.2621181588 |
|
|
Aug 02 08:27:32 PM PDT 24 |
Aug 02 09:33:40 PM PDT 24 |
15234610440 ps |
| T1374 |
/workspace/coverage/default/1.chip_sw_edn_auto_mode.3996918046 |
|
|
Aug 02 08:30:48 PM PDT 24 |
Aug 02 08:49:34 PM PDT 24 |
4824682680 ps |
| T1375 |
/workspace/coverage/default/2.chip_sw_otbn_randomness.160021235 |
|
|
Aug 02 08:38:23 PM PDT 24 |
Aug 02 08:55:26 PM PDT 24 |
6068552152 ps |
| T1376 |
/workspace/coverage/default/0.chip_sw_example_rom.238342457 |
|
|
Aug 02 08:17:32 PM PDT 24 |
Aug 02 08:19:40 PM PDT 24 |
2270205848 ps |
| T1377 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3078773672 |
|
|
Aug 02 08:29:06 PM PDT 24 |
Aug 02 08:52:25 PM PDT 24 |
7784550570 ps |
| T326 |
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1108859869 |
|
|
Aug 02 08:56:11 PM PDT 24 |
Aug 02 09:02:15 PM PDT 24 |
3367295784 ps |
| T1378 |
/workspace/coverage/default/2.chip_sw_uart_smoketest.3046175256 |
|
|
Aug 02 08:42:11 PM PDT 24 |
Aug 02 08:45:56 PM PDT 24 |
2598895786 ps |
| T1379 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3477157454 |
|
|
Aug 02 08:42:25 PM PDT 24 |
Aug 02 08:45:21 PM PDT 24 |
3022731529 ps |
| T1380 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3116875014 |
|
|
Aug 02 08:41:02 PM PDT 24 |
Aug 02 08:52:00 PM PDT 24 |
4635632984 ps |
| T1381 |
/workspace/coverage/default/0.chip_sw_aes_enc.798127247 |
|
|
Aug 02 08:20:01 PM PDT 24 |
Aug 02 08:25:45 PM PDT 24 |
3261327808 ps |
| T1382 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.1600656878 |
|
|
Aug 02 08:25:32 PM PDT 24 |
Aug 02 09:00:51 PM PDT 24 |
22956761416 ps |
| T165 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.4156142389 |
|
|
Aug 02 08:40:08 PM PDT 24 |
Aug 02 08:50:18 PM PDT 24 |
4947969902 ps |
| T1383 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.242462823 |
|
|
Aug 02 08:36:11 PM PDT 24 |
Aug 02 08:53:41 PM PDT 24 |
11537105920 ps |
| T1384 |
/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.1841666517 |
|
|
Aug 02 08:24:19 PM PDT 24 |
Aug 02 08:35:42 PM PDT 24 |
8513306314 ps |
| T1385 |
/workspace/coverage/default/98.chip_sw_all_escalation_resets.3106896735 |
|
|
Aug 02 08:55:21 PM PDT 24 |
Aug 02 09:04:32 PM PDT 24 |
4564547166 ps |
| T1386 |
/workspace/coverage/default/2.chip_sw_example_manufacturer.2325540147 |
|
|
Aug 02 08:34:00 PM PDT 24 |
Aug 02 08:37:47 PM PDT 24 |
2477396514 ps |
| T1387 |
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.670337611 |
|
|
Aug 02 08:52:09 PM PDT 24 |
Aug 02 08:58:16 PM PDT 24 |
3870263800 ps |
| T1388 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.1142730348 |
|
|
Aug 02 08:22:31 PM PDT 24 |
Aug 02 08:28:58 PM PDT 24 |
3087738610 ps |
| T1389 |
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.1581562409 |
|
|
Aug 02 08:46:09 PM PDT 24 |
Aug 02 09:48:35 PM PDT 24 |
17795182458 ps |
| T1390 |
/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.4240007928 |
|
|
Aug 02 08:19:40 PM PDT 24 |
Aug 02 08:49:15 PM PDT 24 |
8626540196 ps |