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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.14 95.47 94.02 95.38 94.92 97.53 99.52


Total test records in report: 2935
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T316 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.2762220123 Aug 02 08:41:03 PM PDT 24 Aug 02 08:59:59 PM PDT 24 10017330261 ps
T1391 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.1129376040 Aug 02 08:26:09 PM PDT 24 Aug 02 08:37:35 PM PDT 24 4369759940 ps
T1392 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.2144808987 Aug 02 08:18:26 PM PDT 24 Aug 02 08:36:37 PM PDT 24 5693425549 ps
T1393 /workspace/coverage/default/1.chip_sw_aes_enc.3407572228 Aug 02 08:27:49 PM PDT 24 Aug 02 08:32:33 PM PDT 24 2792445560 ps
T1394 /workspace/coverage/default/0.chip_sw_example_manufacturer.257586304 Aug 02 08:18:14 PM PDT 24 Aug 02 08:23:14 PM PDT 24 2461389732 ps
T1395 /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.308970586 Aug 02 08:41:17 PM PDT 24 Aug 02 09:55:59 PM PDT 24 44691163882 ps
T1396 /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2624772623 Aug 02 08:27:33 PM PDT 24 Aug 02 08:31:18 PM PDT 24 3129795792 ps
T1397 /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.1612592654 Aug 02 08:20:29 PM PDT 24 Aug 02 08:28:18 PM PDT 24 8892430012 ps
T1398 /workspace/coverage/default/0.rom_volatile_raw_unlock.3180596990 Aug 02 08:21:43 PM PDT 24 Aug 02 08:23:42 PM PDT 24 2046206591 ps
T1399 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3028797095 Aug 02 08:24:58 PM PDT 24 Aug 02 08:53:01 PM PDT 24 7945802000 ps
T1400 /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.2774804856 Aug 02 08:19:28 PM PDT 24 Aug 02 09:39:47 PM PDT 24 27005422590 ps
T1401 /workspace/coverage/default/73.chip_sw_all_escalation_resets.1953428363 Aug 02 08:54:35 PM PDT 24 Aug 02 09:02:58 PM PDT 24 5551669116 ps
T814 /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1685553995 Aug 02 08:55:06 PM PDT 24 Aug 02 09:01:29 PM PDT 24 3689878784 ps
T1402 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.4075267764 Aug 02 08:42:12 PM PDT 24 Aug 02 08:47:53 PM PDT 24 3405510611 ps
T1403 /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.4100641281 Aug 02 08:38:53 PM PDT 24 Aug 02 09:08:29 PM PDT 24 24388320464 ps
T1404 /workspace/coverage/default/0.chip_sw_hmac_oneshot.1814806652 Aug 02 08:19:47 PM PDT 24 Aug 02 08:25:46 PM PDT 24 3306517714 ps
T77 /workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.794150666 Aug 02 08:04:23 PM PDT 24 Aug 02 08:05:18 PM PDT 24 3165229683 ps
T78 /workspace/coverage/cover_reg_top/8.xbar_same_source.293301896 Aug 02 07:53:37 PM PDT 24 Aug 02 07:53:57 PM PDT 24 658364565 ps
T79 /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.35490702 Aug 02 08:04:52 PM PDT 24 Aug 02 08:06:58 PM PDT 24 336088701 ps
T84 /workspace/coverage/cover_reg_top/58.xbar_random.3561237250 Aug 02 08:02:46 PM PDT 24 Aug 02 08:02:55 PM PDT 24 71143428 ps
T123 /workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.3054503073 Aug 02 08:06:28 PM PDT 24 Aug 02 08:07:41 PM PDT 24 7468648234 ps
T266 /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.1491639631 Aug 02 08:04:57 PM PDT 24 Aug 02 08:05:28 PM PDT 24 122823847 ps
T447 /workspace/coverage/cover_reg_top/68.xbar_smoke_zero_delays.3049238621 Aug 02 08:04:40 PM PDT 24 Aug 02 08:04:47 PM PDT 24 46563916 ps
T254 /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.2452701167 Aug 02 08:04:37 PM PDT 24 Aug 02 08:05:59 PM PDT 24 1025372702 ps
T553 /workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.1489131258 Aug 02 08:01:16 PM PDT 24 Aug 02 08:02:33 PM PDT 24 4780439224 ps
T255 /workspace/coverage/cover_reg_top/25.xbar_unmapped_addr.2031595693 Aug 02 07:57:11 PM PDT 24 Aug 02 07:57:44 PM PDT 24 282252121 ps
T547 /workspace/coverage/cover_reg_top/23.xbar_access_same_device.2289774253 Aug 02 07:56:46 PM PDT 24 Aug 02 07:58:14 PM PDT 24 2598072641 ps
T490 /workspace/coverage/cover_reg_top/77.xbar_stress_all.3259766813 Aug 02 08:05:59 PM PDT 24 Aug 02 08:16:19 PM PDT 24 18296671484 ps
T556 /workspace/coverage/cover_reg_top/42.xbar_access_same_device.3716442046 Aug 02 08:00:23 PM PDT 24 Aug 02 08:01:57 PM PDT 24 1220825524 ps
T256 /workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.1891849054 Aug 02 07:52:01 PM PDT 24 Aug 02 07:52:07 PM PDT 24 51040813 ps
T555 /workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.2123788845 Aug 02 08:02:19 PM PDT 24 Aug 02 08:15:58 PM PDT 24 44140696160 ps
T139 /workspace/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.26735090 Aug 02 07:56:00 PM PDT 24 Aug 02 08:03:38 PM PDT 24 7543619200 ps
T448 /workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.283838946 Aug 02 07:54:55 PM PDT 24 Aug 02 07:55:17 PM PDT 24 170957812 ps
T550 /workspace/coverage/cover_reg_top/36.xbar_access_same_device.2862739884 Aug 02 07:59:29 PM PDT 24 Aug 02 08:00:32 PM PDT 24 770287893 ps
T548 /workspace/coverage/cover_reg_top/45.xbar_stress_all.154511205 Aug 02 08:01:01 PM PDT 24 Aug 02 08:01:23 PM PDT 24 209870983 ps
T140 /workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.1182440837 Aug 02 07:53:55 PM PDT 24 Aug 02 08:22:07 PM PDT 24 15082799822 ps
T554 /workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2692321129 Aug 02 07:53:53 PM PDT 24 Aug 02 07:54:40 PM PDT 24 3024853132 ps
T767 /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.3098712902 Aug 02 08:05:49 PM PDT 24 Aug 02 08:23:10 PM PDT 24 62327260508 ps
T549 /workspace/coverage/cover_reg_top/27.chip_tl_errors.1154017389 Aug 02 07:57:35 PM PDT 24 Aug 02 08:00:49 PM PDT 24 3351631240 ps
T508 /workspace/coverage/cover_reg_top/54.xbar_same_source.4256868011 Aug 02 08:02:42 PM PDT 24 Aug 02 08:03:55 PM PDT 24 2521303593 ps
T766 /workspace/coverage/cover_reg_top/66.xbar_smoke_large_delays.2581218442 Aug 02 08:04:10 PM PDT 24 Aug 02 08:06:13 PM PDT 24 10705111459 ps
T449 /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.3091937352 Aug 02 08:06:00 PM PDT 24 Aug 02 08:11:53 PM PDT 24 12448798504 ps
T702 /workspace/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.2514679969 Aug 02 08:04:50 PM PDT 24 Aug 02 08:05:46 PM PDT 24 1401346369 ps
T487 /workspace/coverage/cover_reg_top/79.xbar_unmapped_addr.4110740323 Aug 02 08:06:32 PM PDT 24 Aug 02 08:07:25 PM PDT 24 1276856963 ps
T498 /workspace/coverage/cover_reg_top/43.xbar_random.619015520 Aug 02 08:00:33 PM PDT 24 Aug 02 08:01:35 PM PDT 24 1822414868 ps
T734 /workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.2232273680 Aug 02 07:54:02 PM PDT 24 Aug 02 07:54:19 PM PDT 24 155159940 ps
T551 /workspace/coverage/cover_reg_top/79.xbar_random_large_delays.606402595 Aug 02 08:06:13 PM PDT 24 Aug 02 08:23:24 PM PDT 24 94457960510 ps
T839 /workspace/coverage/cover_reg_top/61.xbar_error_random.3718125305 Aug 02 08:03:23 PM PDT 24 Aug 02 08:04:21 PM PDT 24 1613072551 ps
T578 /workspace/coverage/cover_reg_top/30.xbar_random_zero_delays.801744255 Aug 02 07:58:14 PM PDT 24 Aug 02 07:58:30 PM PDT 24 147540544 ps
T565 /workspace/coverage/cover_reg_top/84.xbar_same_source.1364744449 Aug 02 08:07:13 PM PDT 24 Aug 02 08:07:33 PM PDT 24 608536437 ps
T513 /workspace/coverage/cover_reg_top/89.xbar_random.135190452 Aug 02 08:08:03 PM PDT 24 Aug 02 08:08:15 PM PDT 24 107931016 ps
T899 /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.2482009044 Aug 02 07:58:24 PM PDT 24 Aug 02 07:58:46 PM PDT 24 54580826 ps
T693 /workspace/coverage/cover_reg_top/10.chip_tl_errors.3619109305 Aug 02 07:53:48 PM PDT 24 Aug 02 07:55:06 PM PDT 24 2584552443 ps
T844 /workspace/coverage/cover_reg_top/14.xbar_access_same_device.490620656 Aug 02 07:54:42 PM PDT 24 Aug 02 07:55:38 PM PDT 24 1390584236 ps
T642 /workspace/coverage/cover_reg_top/55.xbar_same_source.1194603491 Aug 02 08:02:37 PM PDT 24 Aug 02 08:02:59 PM PDT 24 641853047 ps
T908 /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.1435819353 Aug 02 08:04:24 PM PDT 24 Aug 02 08:04:44 PM PDT 24 88383775 ps
T606 /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.1082947982 Aug 02 08:08:18 PM PDT 24 Aug 02 08:12:49 PM PDT 24 25608530304 ps
T643 /workspace/coverage/cover_reg_top/90.xbar_same_source.3019473753 Aug 02 08:08:19 PM PDT 24 Aug 02 08:08:35 PM PDT 24 187793517 ps
T552 /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.2932114296 Aug 02 08:07:36 PM PDT 24 Aug 02 08:09:20 PM PDT 24 1362504754 ps
T1405 /workspace/coverage/cover_reg_top/99.xbar_error_random.3434722567 Aug 02 08:09:35 PM PDT 24 Aug 02 08:09:59 PM PDT 24 324289639 ps
T1406 /workspace/coverage/cover_reg_top/45.xbar_smoke_zero_delays.962773450 Aug 02 08:00:51 PM PDT 24 Aug 02 08:00:57 PM PDT 24 39913206 ps
T913 /workspace/coverage/cover_reg_top/1.chip_prim_tl_access.324374042 Aug 02 07:51:44 PM PDT 24 Aug 02 07:55:45 PM PDT 24 5997370408 ps
T1407 /workspace/coverage/cover_reg_top/3.xbar_error_random.841799838 Aug 02 07:52:17 PM PDT 24 Aug 02 07:53:06 PM PDT 24 1599278327 ps
T874 /workspace/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.2260993342 Aug 02 07:52:16 PM PDT 24 Aug 02 07:53:50 PM PDT 24 5865898162 ps
T1408 /workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.2811639857 Aug 02 07:58:49 PM PDT 24 Aug 02 08:00:19 PM PDT 24 5041034271 ps
T581 /workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.740051056 Aug 02 08:01:41 PM PDT 24 Aug 02 08:02:03 PM PDT 24 177374305 ps
T537 /workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.1378801060 Aug 02 07:56:03 PM PDT 24 Aug 02 07:56:41 PM PDT 24 436928978 ps
T1409 /workspace/coverage/cover_reg_top/82.xbar_smoke.3378360850 Aug 02 08:06:46 PM PDT 24 Aug 02 08:06:57 PM PDT 24 235678074 ps
T1410 /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.4183214877 Aug 02 08:07:25 PM PDT 24 Aug 02 08:07:51 PM PDT 24 606182811 ps
T562 /workspace/coverage/cover_reg_top/58.xbar_same_source.384536931 Aug 02 08:02:56 PM PDT 24 Aug 02 08:03:32 PM PDT 24 565216895 ps
T696 /workspace/coverage/cover_reg_top/83.xbar_error_random.2563178140 Aug 02 08:06:59 PM PDT 24 Aug 02 08:07:47 PM PDT 24 622415136 ps
T574 /workspace/coverage/cover_reg_top/89.xbar_smoke_large_delays.961872712 Aug 02 08:08:01 PM PDT 24 Aug 02 08:09:24 PM PDT 24 7718377787 ps
T697 /workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.2001602396 Aug 02 07:54:22 PM PDT 24 Aug 02 07:54:54 PM PDT 24 808099412 ps
T459 /workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.3738780383 Aug 02 08:00:57 PM PDT 24 Aug 02 08:11:49 PM PDT 24 39796388812 ps
T656 /workspace/coverage/cover_reg_top/63.xbar_smoke.3808751955 Aug 02 08:03:41 PM PDT 24 Aug 02 08:03:48 PM PDT 24 54840867 ps
T455 /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.3230437220 Aug 02 07:53:33 PM PDT 24 Aug 02 08:00:08 PM PDT 24 2114447123 ps
T569 /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.464644137 Aug 02 08:01:29 PM PDT 24 Aug 02 08:01:55 PM PDT 24 315511546 ps
T573 /workspace/coverage/cover_reg_top/10.xbar_smoke.3628241251 Aug 02 07:53:50 PM PDT 24 Aug 02 07:53:59 PM PDT 24 191034669 ps
T583 /workspace/coverage/cover_reg_top/54.xbar_smoke_zero_delays.2458499165 Aug 02 08:02:17 PM PDT 24 Aug 02 08:02:23 PM PDT 24 51951100 ps
T566 /workspace/coverage/cover_reg_top/11.chip_tl_errors.1448672495 Aug 02 07:54:08 PM PDT 24 Aug 02 07:57:42 PM PDT 24 3995204200 ps
T571 /workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.1761972114 Aug 02 07:53:36 PM PDT 24 Aug 02 08:09:20 PM PDT 24 56832587438 ps
T475 /workspace/coverage/cover_reg_top/57.xbar_access_same_device.1850220336 Aug 02 08:02:50 PM PDT 24 Aug 02 08:04:38 PM PDT 24 2693116272 ps
T703 /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.3608019666 Aug 02 08:00:50 PM PDT 24 Aug 02 08:02:35 PM PDT 24 1413987021 ps
T832 /workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.4102258687 Aug 02 07:58:09 PM PDT 24 Aug 02 08:34:02 PM PDT 24 118469977778 ps
T1411 /workspace/coverage/cover_reg_top/24.xbar_error_random.2535940259 Aug 02 07:56:56 PM PDT 24 Aug 02 07:57:51 PM PDT 24 1559932500 ps
T644 /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.501584535 Aug 02 08:04:58 PM PDT 24 Aug 02 08:05:23 PM PDT 24 243960986 ps
T707 /workspace/coverage/cover_reg_top/78.xbar_smoke_zero_delays.855253806 Aug 02 08:06:00 PM PDT 24 Aug 02 08:06:06 PM PDT 24 38888914 ps
T837 /workspace/coverage/cover_reg_top/45.xbar_access_same_device.295224987 Aug 02 08:00:55 PM PDT 24 Aug 02 08:01:37 PM PDT 24 1077692866 ps
T1412 /workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.1207157222 Aug 02 07:55:50 PM PDT 24 Aug 02 07:56:02 PM PDT 24 216094128 ps
T593 /workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.290136677 Aug 02 08:08:40 PM PDT 24 Aug 02 08:13:34 PM PDT 24 15334958756 ps
T623 /workspace/coverage/cover_reg_top/80.xbar_random_large_delays.1007029739 Aug 02 08:06:29 PM PDT 24 Aug 02 08:14:08 PM PDT 24 45619791798 ps
T557 /workspace/coverage/cover_reg_top/3.chip_tl_errors.3625339436 Aug 02 07:52:04 PM PDT 24 Aug 02 07:55:55 PM PDT 24 3046158901 ps
T851 /workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.3812636786 Aug 02 08:00:08 PM PDT 24 Aug 02 08:01:04 PM PDT 24 3326865745 ps
T1413 /workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.1387645956 Aug 02 08:01:29 PM PDT 24 Aug 02 08:02:21 PM PDT 24 1233018621 ps
T733 /workspace/coverage/cover_reg_top/21.xbar_error_random.4037393595 Aug 02 07:56:24 PM PDT 24 Aug 02 07:56:33 PM PDT 24 57688826 ps
T652 /workspace/coverage/cover_reg_top/3.xbar_smoke.3814804112 Aug 02 07:52:01 PM PDT 24 Aug 02 07:52:11 PM PDT 24 231907693 ps
T840 /workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.2281617925 Aug 02 07:54:54 PM PDT 24 Aug 02 08:13:47 PM PDT 24 66314293278 ps
T634 /workspace/coverage/cover_reg_top/68.xbar_random.1014964167 Aug 02 08:04:40 PM PDT 24 Aug 02 08:04:48 PM PDT 24 62571685 ps
T538 /workspace/coverage/cover_reg_top/11.xbar_same_source.63967501 Aug 02 07:54:03 PM PDT 24 Aug 02 07:54:37 PM PDT 24 513399384 ps
T564 /workspace/coverage/cover_reg_top/24.chip_tl_errors.1103709161 Aug 02 07:56:48 PM PDT 24 Aug 02 07:59:32 PM PDT 24 3981806900 ps
T708 /workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.800372317 Aug 02 08:09:37 PM PDT 24 Aug 02 08:10:16 PM PDT 24 2360388457 ps
T515 /workspace/coverage/cover_reg_top/47.xbar_random_zero_delays.866193538 Aug 02 08:01:05 PM PDT 24 Aug 02 08:01:36 PM PDT 24 333078767 ps
T1414 /workspace/coverage/cover_reg_top/55.xbar_smoke_large_delays.1679192812 Aug 02 08:02:35 PM PDT 24 Aug 02 08:03:51 PM PDT 24 7693774441 ps
T863 /workspace/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.3405209913 Aug 02 07:58:35 PM PDT 24 Aug 02 08:01:03 PM PDT 24 9190418036 ps
T505 /workspace/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.2807441143 Aug 02 07:59:40 PM PDT 24 Aug 02 08:01:16 PM PDT 24 5679533986 ps
T833 /workspace/coverage/cover_reg_top/24.xbar_access_same_device.140547514 Aug 02 07:57:00 PM PDT 24 Aug 02 07:57:35 PM PDT 24 920234911 ps
T530 /workspace/coverage/cover_reg_top/5.xbar_random_large_delays.3716108917 Aug 02 07:52:27 PM PDT 24 Aug 02 08:09:56 PM PDT 24 104148136529 ps
T461 /workspace/coverage/cover_reg_top/80.xbar_random.3854402554 Aug 02 08:06:30 PM PDT 24 Aug 02 08:07:08 PM PDT 24 425265586 ps
T1415 /workspace/coverage/cover_reg_top/28.xbar_smoke_large_delays.405565616 Aug 02 07:57:43 PM PDT 24 Aug 02 07:58:36 PM PDT 24 5069734833 ps
T1416 /workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.4256930864 Aug 02 08:09:24 PM PDT 24 Aug 02 08:09:31 PM PDT 24 56667830 ps
T701 /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.2256244059 Aug 02 08:04:35 PM PDT 24 Aug 02 08:12:20 PM PDT 24 3620282674 ps
T396 /workspace/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.1693533604 Aug 02 07:53:12 PM PDT 24 Aug 02 08:00:55 PM PDT 24 6243619150 ps
T141 /workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.3277679446 Aug 02 07:54:57 PM PDT 24 Aug 02 08:26:39 PM PDT 24 16408211596 ps
T1417 /workspace/coverage/cover_reg_top/65.xbar_smoke.2617084851 Aug 02 08:04:06 PM PDT 24 Aug 02 08:04:14 PM PDT 24 181037573 ps
T541 /workspace/coverage/cover_reg_top/42.xbar_random_zero_delays.2863639904 Aug 02 08:00:25 PM PDT 24 Aug 02 08:01:18 PM PDT 24 558364941 ps
T699 /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.3171300630 Aug 02 08:07:36 PM PDT 24 Aug 02 08:09:31 PM PDT 24 331336635 ps
T607 /workspace/coverage/cover_reg_top/1.xbar_random.128219342 Aug 02 07:51:45 PM PDT 24 Aug 02 07:52:02 PM PDT 24 201513423 ps
T543 /workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.1031724758 Aug 02 07:51:44 PM PDT 24 Aug 02 08:06:07 PM PDT 24 9149922329 ps
T1418 /workspace/coverage/cover_reg_top/9.xbar_error_random.1445758527 Aug 02 07:53:50 PM PDT 24 Aug 02 07:54:22 PM PDT 24 850935745 ps
T572 /workspace/coverage/cover_reg_top/76.xbar_random.1024162425 Aug 02 08:05:50 PM PDT 24 Aug 02 08:06:04 PM PDT 24 317758255 ps
T700 /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.1566384888 Aug 02 08:04:52 PM PDT 24 Aug 02 08:10:37 PM PDT 24 10247621991 ps
T1419 /workspace/coverage/cover_reg_top/36.xbar_smoke.373760137 Aug 02 07:59:28 PM PDT 24 Aug 02 07:59:34 PM PDT 24 36424987 ps
T531 /workspace/coverage/cover_reg_top/0.xbar_random_large_delays.2664766740 Aug 02 07:51:46 PM PDT 24 Aug 02 08:07:18 PM PDT 24 97920082278 ps
T895 /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.734411111 Aug 02 08:04:45 PM PDT 24 Aug 02 08:07:36 PM PDT 24 466998530 ps
T397 /workspace/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.3994650723 Aug 02 07:52:37 PM PDT 24 Aug 02 08:01:45 PM PDT 24 6183310324 ps
T1420 /workspace/coverage/cover_reg_top/91.xbar_error_random.2707776034 Aug 02 08:08:23 PM PDT 24 Aug 02 08:08:46 PM PDT 24 587668902 ps
T1421 /workspace/coverage/cover_reg_top/25.xbar_random_large_delays.2002051528 Aug 02 07:57:07 PM PDT 24 Aug 02 07:58:29 PM PDT 24 7805320617 ps
T610 /workspace/coverage/cover_reg_top/62.xbar_random_slow_rsp.1425625215 Aug 02 08:03:38 PM PDT 24 Aug 02 08:15:26 PM PDT 24 39394419587 ps
T539 /workspace/coverage/cover_reg_top/85.xbar_unmapped_addr.3099673920 Aug 02 08:07:25 PM PDT 24 Aug 02 08:07:55 PM PDT 24 261803199 ps
T662 /workspace/coverage/cover_reg_top/97.xbar_unmapped_addr.1413602395 Aug 02 08:09:21 PM PDT 24 Aug 02 08:09:51 PM PDT 24 260060169 ps
T630 /workspace/coverage/cover_reg_top/99.xbar_random_large_delays.2189107328 Aug 02 08:09:36 PM PDT 24 Aug 02 08:27:45 PM PDT 24 102698888386 ps
T609 /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.123471115 Aug 02 08:06:45 PM PDT 24 Aug 02 08:12:02 PM PDT 24 1763356984 ps
T469 /workspace/coverage/cover_reg_top/56.xbar_random_slow_rsp.3793826867 Aug 02 08:02:45 PM PDT 24 Aug 02 08:18:39 PM PDT 24 51527804770 ps
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T1451 /workspace/coverage/cover_reg_top/46.xbar_access_same_device.2497503469 Aug 02 08:01:07 PM PDT 24 Aug 02 08:01:21 PM PDT 24 186496675 ps
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T1455 /workspace/coverage/cover_reg_top/67.xbar_smoke_zero_delays.2178170925 Aug 02 08:04:24 PM PDT 24 Aug 02 08:04:30 PM PDT 24 42005272 ps
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T1459 /workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.2245691105 Aug 02 07:54:03 PM PDT 24 Aug 02 07:55:54 PM PDT 24 6661352539 ps
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T1460 /workspace/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.3177927112 Aug 02 08:04:23 PM PDT 24 Aug 02 08:05:03 PM PDT 24 1039686749 ps
T1461 /workspace/coverage/cover_reg_top/8.xbar_smoke.1781135946 Aug 02 07:53:18 PM PDT 24 Aug 02 07:53:26 PM PDT 24 185121827 ps
T1462 /workspace/coverage/cover_reg_top/39.xbar_error_random.2978663479 Aug 02 07:59:53 PM PDT 24 Aug 02 08:00:31 PM PDT 24 450765505 ps
T1463 /workspace/coverage/cover_reg_top/48.xbar_error_random.2918376213 Aug 02 08:01:28 PM PDT 24 Aug 02 08:02:02 PM PDT 24 411153705 ps
T616 /workspace/coverage/cover_reg_top/86.xbar_random_slow_rsp.126805473 Aug 02 08:07:28 PM PDT 24 Aug 02 08:23:55 PM PDT 24 55289772161 ps
T854 /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.515201832 Aug 02 07:59:26 PM PDT 24 Aug 02 08:07:16 PM PDT 24 7872350906 ps
T476 /workspace/coverage/cover_reg_top/37.xbar_same_source.2241208609 Aug 02 07:59:44 PM PDT 24 Aug 02 08:00:19 PM PDT 24 500600593 ps
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